[PATCH] turn "const static" into "static const"
[linux-2.6.git] / arch / arm / plat-omap / dma.c
1 /*
2  * linux/arch/arm/plat-omap/dma.c
3  *
4  * Copyright (C) 2003 Nokia Corporation
5  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6  * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7  * Graphics DMA and LCD DMA graphics tranformations
8  * by Imre Deak <imre.deak@nokia.com>
9  * OMAP2 support Copyright (C) 2004-2005 Texas Instruments, Inc.
10  * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11  * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
12  *
13  * Support functions for the OMAP internal DMA channels.
14  *
15  * This program is free software; you can redistribute it and/or modify
16  * it under the terms of the GNU General Public License version 2 as
17  * published by the Free Software Foundation.
18  *
19  */
20
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/sched.h>
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/interrupt.h>
27
28 #include <asm/system.h>
29 #include <asm/irq.h>
30 #include <asm/hardware.h>
31 #include <asm/dma.h>
32 #include <asm/io.h>
33
34 #include <asm/arch/tc.h>
35
36 #define DEBUG_PRINTS
37 #undef DEBUG_PRINTS
38 #ifdef DEBUG_PRINTS
39 #define debug_printk(x) printk x
40 #else
41 #define debug_printk(x)
42 #endif
43
44 #define OMAP_DMA_ACTIVE         0x01
45 #define OMAP_DMA_CCR_EN         (1 << 7)
46
47 #define OMAP_FUNC_MUX_ARM_BASE  (0xfffe1000 + 0xec)
48
49 static int enable_1510_mode = 0;
50
51 struct omap_dma_lch {
52         int next_lch;
53         int dev_id;
54         u16 saved_csr;
55         u16 enabled_irqs;
56         const char *dev_name;
57         void (* callback)(int lch, u16 ch_status, void *data);
58         void *data;
59         long flags;
60 };
61
62 static int dma_chan_count;
63
64 static spinlock_t dma_chan_lock;
65 static struct omap_dma_lch dma_chan[OMAP_LOGICAL_DMA_CH_COUNT];
66
67 static const u8 omap1_dma_irq[OMAP_LOGICAL_DMA_CH_COUNT] = {
68         INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
69         INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
70         INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
71         INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
72         INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
73 };
74
75 #define REVISIT_24XX()          printk(KERN_ERR "FIXME: no %s on 24xx\n", \
76                                                 __FUNCTION__);
77
78 #ifdef CONFIG_ARCH_OMAP15XX
79 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
80 int omap_dma_in_1510_mode(void)
81 {
82         return enable_1510_mode;
83 }
84 #else
85 #define omap_dma_in_1510_mode()         0
86 #endif
87
88 #ifdef CONFIG_ARCH_OMAP1
89 static inline int get_gdma_dev(int req)
90 {
91         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
92         int shift = ((req - 1) % 5) * 6;
93
94         return ((omap_readl(reg) >> shift) & 0x3f) + 1;
95 }
96
97 static inline void set_gdma_dev(int req, int dev)
98 {
99         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
100         int shift = ((req - 1) % 5) * 6;
101         u32 l;
102
103         l = omap_readl(reg);
104         l &= ~(0x3f << shift);
105         l |= (dev - 1) << shift;
106         omap_writel(l, reg);
107 }
108 #else
109 #define set_gdma_dev(req, dev)  do {} while (0)
110 #endif
111
112 static void clear_lch_regs(int lch)
113 {
114         int i;
115         u32 lch_base = OMAP_DMA_BASE + lch * 0x40;
116
117         for (i = 0; i < 0x2c; i += 2)
118                 omap_writew(0, lch_base + i);
119 }
120
121 void omap_set_dma_priority(int dst_port, int priority)
122 {
123         unsigned long reg;
124         u32 l;
125
126         switch (dst_port) {
127         case OMAP_DMA_PORT_OCP_T1:      /* FFFECC00 */
128                 reg = OMAP_TC_OCPT1_PRIOR;
129                 break;
130         case OMAP_DMA_PORT_OCP_T2:      /* FFFECCD0 */
131                 reg = OMAP_TC_OCPT2_PRIOR;
132                 break;
133         case OMAP_DMA_PORT_EMIFF:       /* FFFECC08 */
134                 reg = OMAP_TC_EMIFF_PRIOR;
135                 break;
136         case OMAP_DMA_PORT_EMIFS:       /* FFFECC04 */
137                 reg = OMAP_TC_EMIFS_PRIOR;
138                 break;
139         default:
140                 BUG();
141                 return;
142         }
143         l = omap_readl(reg);
144         l &= ~(0xf << 8);
145         l |= (priority & 0xf) << 8;
146         omap_writel(l, reg);
147 }
148
149 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
150                                   int frame_count, int sync_mode,
151                                   int dma_trigger, int src_or_dst_synch)
152 {
153         OMAP_DMA_CSDP_REG(lch) &= ~0x03;
154         OMAP_DMA_CSDP_REG(lch) |= data_type;
155
156         if (cpu_class_is_omap1()) {
157                 OMAP_DMA_CCR_REG(lch) &= ~(1 << 5);
158                 if (sync_mode == OMAP_DMA_SYNC_FRAME)
159                         OMAP_DMA_CCR_REG(lch) |= 1 << 5;
160
161                 OMAP1_DMA_CCR2_REG(lch) &= ~(1 << 2);
162                 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
163                         OMAP1_DMA_CCR2_REG(lch) |= 1 << 2;
164         }
165
166         if (cpu_is_omap24xx() && dma_trigger) {
167                 u32 val = OMAP_DMA_CCR_REG(lch);
168
169                 if (dma_trigger > 63)
170                         val |= 1 << 20;
171                 if (dma_trigger > 31)
172                         val |= 1 << 19;
173
174                 val |= (dma_trigger & 0x1f);
175
176                 if (sync_mode & OMAP_DMA_SYNC_FRAME)
177                         val |= 1 << 5;
178
179                 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
180                         val |= 1 << 18;
181
182                 if (src_or_dst_synch)
183                         val |= 1 << 24;         /* source synch */
184                 else
185                         val &= ~(1 << 24);      /* dest synch */
186
187                 OMAP_DMA_CCR_REG(lch) = val;
188         }
189
190         OMAP_DMA_CEN_REG(lch) = elem_count;
191         OMAP_DMA_CFN_REG(lch) = frame_count;
192 }
193
194 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
195 {
196         u16 w;
197
198         BUG_ON(omap_dma_in_1510_mode());
199
200         if (cpu_is_omap24xx()) {
201                 REVISIT_24XX();
202                 return;
203         }
204
205         w = OMAP1_DMA_CCR2_REG(lch) & ~0x03;
206         switch (mode) {
207         case OMAP_DMA_CONSTANT_FILL:
208                 w |= 0x01;
209                 break;
210         case OMAP_DMA_TRANSPARENT_COPY:
211                 w |= 0x02;
212                 break;
213         case OMAP_DMA_COLOR_DIS:
214                 break;
215         default:
216                 BUG();
217         }
218         OMAP1_DMA_CCR2_REG(lch) = w;
219
220         w = OMAP1_DMA_LCH_CTRL_REG(lch) & ~0x0f;
221         /* Default is channel type 2D */
222         if (mode) {
223                 OMAP1_DMA_COLOR_L_REG(lch) = (u16)color;
224                 OMAP1_DMA_COLOR_U_REG(lch) = (u16)(color >> 16);
225                 w |= 1;         /* Channel type G */
226         }
227         OMAP1_DMA_LCH_CTRL_REG(lch) = w;
228 }
229
230 /* Note that src_port is only for omap1 */
231 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
232                              unsigned long src_start,
233                              int src_ei, int src_fi)
234 {
235         if (cpu_class_is_omap1()) {
236                 OMAP_DMA_CSDP_REG(lch) &= ~(0x1f << 2);
237                 OMAP_DMA_CSDP_REG(lch) |= src_port << 2;
238         }
239
240         OMAP_DMA_CCR_REG(lch) &= ~(0x03 << 12);
241         OMAP_DMA_CCR_REG(lch) |= src_amode << 12;
242
243         if (cpu_class_is_omap1()) {
244                 OMAP1_DMA_CSSA_U_REG(lch) = src_start >> 16;
245                 OMAP1_DMA_CSSA_L_REG(lch) = src_start;
246         }
247
248         if (cpu_is_omap24xx())
249                 OMAP2_DMA_CSSA_REG(lch) = src_start;
250
251         OMAP_DMA_CSEI_REG(lch) = src_ei;
252         OMAP_DMA_CSFI_REG(lch) = src_fi;
253 }
254
255 void omap_set_dma_params(int lch, struct omap_dma_channel_params * params)
256 {
257         omap_set_dma_transfer_params(lch, params->data_type,
258                                      params->elem_count, params->frame_count,
259                                      params->sync_mode, params->trigger,
260                                      params->src_or_dst_synch);
261         omap_set_dma_src_params(lch, params->src_port,
262                                 params->src_amode, params->src_start,
263                                 params->src_ei, params->src_fi);
264
265         omap_set_dma_dest_params(lch, params->dst_port,
266                                  params->dst_amode, params->dst_start,
267                                  params->dst_ei, params->dst_fi);
268 }
269
270 void omap_set_dma_src_index(int lch, int eidx, int fidx)
271 {
272         if (cpu_is_omap24xx()) {
273                 REVISIT_24XX();
274                 return;
275         }
276         OMAP_DMA_CSEI_REG(lch) = eidx;
277         OMAP_DMA_CSFI_REG(lch) = fidx;
278 }
279
280 void omap_set_dma_src_data_pack(int lch, int enable)
281 {
282         OMAP_DMA_CSDP_REG(lch) &= ~(1 << 6);
283         if (enable)
284                 OMAP_DMA_CSDP_REG(lch) |= (1 << 6);
285 }
286
287 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
288 {
289         OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 7);
290
291         switch (burst_mode) {
292         case OMAP_DMA_DATA_BURST_DIS:
293                 break;
294         case OMAP_DMA_DATA_BURST_4:
295                 OMAP_DMA_CSDP_REG(lch) |= (0x02 << 7);
296                 break;
297         case OMAP_DMA_DATA_BURST_8:
298                 /* not supported by current hardware
299                  * w |= (0x03 << 7);
300                  * fall through
301                  */
302         default:
303                 BUG();
304         }
305 }
306
307 /* Note that dest_port is only for OMAP1 */
308 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
309                               unsigned long dest_start,
310                               int dst_ei, int dst_fi)
311 {
312         if (cpu_class_is_omap1()) {
313                 OMAP_DMA_CSDP_REG(lch) &= ~(0x1f << 9);
314                 OMAP_DMA_CSDP_REG(lch) |= dest_port << 9;
315         }
316
317         OMAP_DMA_CCR_REG(lch) &= ~(0x03 << 14);
318         OMAP_DMA_CCR_REG(lch) |= dest_amode << 14;
319
320         if (cpu_class_is_omap1()) {
321                 OMAP1_DMA_CDSA_U_REG(lch) = dest_start >> 16;
322                 OMAP1_DMA_CDSA_L_REG(lch) = dest_start;
323         }
324
325         if (cpu_is_omap24xx())
326                 OMAP2_DMA_CDSA_REG(lch) = dest_start;
327
328         OMAP_DMA_CDEI_REG(lch) = dst_ei;
329         OMAP_DMA_CDFI_REG(lch) = dst_fi;
330 }
331
332 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
333 {
334         if (cpu_is_omap24xx()) {
335                 REVISIT_24XX();
336                 return;
337         }
338         OMAP_DMA_CDEI_REG(lch) = eidx;
339         OMAP_DMA_CDFI_REG(lch) = fidx;
340 }
341
342 void omap_set_dma_dest_data_pack(int lch, int enable)
343 {
344         OMAP_DMA_CSDP_REG(lch) &= ~(1 << 13);
345         if (enable)
346                 OMAP_DMA_CSDP_REG(lch) |= 1 << 13;
347 }
348
349 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
350 {
351         OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 14);
352
353         switch (burst_mode) {
354         case OMAP_DMA_DATA_BURST_DIS:
355                 break;
356         case OMAP_DMA_DATA_BURST_4:
357                 OMAP_DMA_CSDP_REG(lch) |= (0x02 << 14);
358                 break;
359         case OMAP_DMA_DATA_BURST_8:
360                 OMAP_DMA_CSDP_REG(lch) |= (0x03 << 14);
361                 break;
362         default:
363                 printk(KERN_ERR "Invalid DMA burst mode\n");
364                 BUG();
365                 return;
366         }
367 }
368
369 static inline void omap_enable_channel_irq(int lch)
370 {
371         u32 status;
372
373         /* Read CSR to make sure it's cleared. */
374         status = OMAP_DMA_CSR_REG(lch);
375
376         /* Enable some nice interrupts. */
377         OMAP_DMA_CICR_REG(lch) = dma_chan[lch].enabled_irqs;
378
379         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
380 }
381
382 static void omap_disable_channel_irq(int lch)
383 {
384         if (cpu_is_omap24xx())
385                 OMAP_DMA_CICR_REG(lch) = 0;
386 }
387
388 void omap_enable_dma_irq(int lch, u16 bits)
389 {
390         dma_chan[lch].enabled_irqs |= bits;
391 }
392
393 void omap_disable_dma_irq(int lch, u16 bits)
394 {
395         dma_chan[lch].enabled_irqs &= ~bits;
396 }
397
398 static inline void enable_lnk(int lch)
399 {
400         if (cpu_class_is_omap1())
401                 OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 14);
402
403         /* Set the ENABLE_LNK bits */
404         if (dma_chan[lch].next_lch != -1)
405                 OMAP_DMA_CLNK_CTRL_REG(lch) =
406                         dma_chan[lch].next_lch | (1 << 15);
407 }
408
409 static inline void disable_lnk(int lch)
410 {
411         /* Disable interrupts */
412         if (cpu_class_is_omap1()) {
413                 OMAP_DMA_CICR_REG(lch) = 0;
414                 /* Set the STOP_LNK bit */
415                 OMAP_DMA_CLNK_CTRL_REG(lch) |= 1 << 14;
416         }
417
418         if (cpu_is_omap24xx()) {
419                 omap_disable_channel_irq(lch);
420                 /* Clear the ENABLE_LNK bit */
421                 OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 15);
422         }
423
424         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
425 }
426
427 static inline void omap2_enable_irq_lch(int lch)
428 {
429         u32 val;
430
431         if (!cpu_is_omap24xx())
432                 return;
433
434         val = omap_readl(OMAP_DMA4_IRQENABLE_L0);
435         val |= 1 << lch;
436         omap_writel(val, OMAP_DMA4_IRQENABLE_L0);
437 }
438
439 int omap_request_dma(int dev_id, const char *dev_name,
440                      void (* callback)(int lch, u16 ch_status, void *data),
441                      void *data, int *dma_ch_out)
442 {
443         int ch, free_ch = -1;
444         unsigned long flags;
445         struct omap_dma_lch *chan;
446
447         spin_lock_irqsave(&dma_chan_lock, flags);
448         for (ch = 0; ch < dma_chan_count; ch++) {
449                 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
450                         free_ch = ch;
451                         if (dev_id == 0)
452                                 break;
453                 }
454         }
455         if (free_ch == -1) {
456                 spin_unlock_irqrestore(&dma_chan_lock, flags);
457                 return -EBUSY;
458         }
459         chan = dma_chan + free_ch;
460         chan->dev_id = dev_id;
461
462         if (cpu_class_is_omap1())
463                 clear_lch_regs(free_ch);
464
465         if (cpu_is_omap24xx())
466                 omap_clear_dma(free_ch);
467
468         spin_unlock_irqrestore(&dma_chan_lock, flags);
469
470         chan->dev_name = dev_name;
471         chan->callback = callback;
472         chan->data = data;
473         chan->enabled_irqs = OMAP_DMA_TOUT_IRQ | OMAP_DMA_DROP_IRQ |
474                                 OMAP_DMA_BLOCK_IRQ;
475
476         if (cpu_is_omap24xx())
477                 chan->enabled_irqs |= OMAP2_DMA_TRANS_ERR_IRQ;
478
479         if (cpu_is_omap16xx()) {
480                 /* If the sync device is set, configure it dynamically. */
481                 if (dev_id != 0) {
482                         set_gdma_dev(free_ch + 1, dev_id);
483                         dev_id = free_ch + 1;
484                 }
485                 /* Disable the 1510 compatibility mode and set the sync device
486                  * id. */
487                 OMAP_DMA_CCR_REG(free_ch) = dev_id | (1 << 10);
488         } else if (cpu_is_omap730() || cpu_is_omap15xx()) {
489                 OMAP_DMA_CCR_REG(free_ch) = dev_id;
490         }
491
492         if (cpu_is_omap24xx()) {
493                 omap2_enable_irq_lch(free_ch);
494
495                 omap_enable_channel_irq(free_ch);
496                 /* Clear the CSR register and IRQ status register */
497                 OMAP_DMA_CSR_REG(free_ch) = 0x0;
498                 omap_writel(~0x0, OMAP_DMA4_IRQSTATUS_L0);
499         }
500
501         *dma_ch_out = free_ch;
502
503         return 0;
504 }
505
506 void omap_free_dma(int lch)
507 {
508         unsigned long flags;
509
510         spin_lock_irqsave(&dma_chan_lock, flags);
511         if (dma_chan[lch].dev_id == -1) {
512                 printk("omap_dma: trying to free nonallocated DMA channel %d\n",
513                        lch);
514                 spin_unlock_irqrestore(&dma_chan_lock, flags);
515                 return;
516         }
517         dma_chan[lch].dev_id = -1;
518         dma_chan[lch].next_lch = -1;
519         dma_chan[lch].callback = NULL;
520         spin_unlock_irqrestore(&dma_chan_lock, flags);
521
522         if (cpu_class_is_omap1()) {
523                 /* Disable all DMA interrupts for the channel. */
524                 OMAP_DMA_CICR_REG(lch) = 0;
525                 /* Make sure the DMA transfer is stopped. */
526                 OMAP_DMA_CCR_REG(lch) = 0;
527         }
528
529         if (cpu_is_omap24xx()) {
530                 u32 val;
531                 /* Disable interrupts */
532                 val = omap_readl(OMAP_DMA4_IRQENABLE_L0);
533                 val &= ~(1 << lch);
534                 omap_writel(val, OMAP_DMA4_IRQENABLE_L0);
535
536                 /* Clear the CSR register and IRQ status register */
537                 OMAP_DMA_CSR_REG(lch) = 0x0;
538
539                 val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
540                 val |= 1 << lch;
541                 omap_writel(val, OMAP_DMA4_IRQSTATUS_L0);
542
543                 /* Disable all DMA interrupts for the channel. */
544                 OMAP_DMA_CICR_REG(lch) = 0;
545
546                 /* Make sure the DMA transfer is stopped. */
547                 OMAP_DMA_CCR_REG(lch) = 0;
548                 omap_clear_dma(lch);
549         }
550 }
551
552 /*
553  * Clears any DMA state so the DMA engine is ready to restart with new buffers
554  * through omap_start_dma(). Any buffers in flight are discarded.
555  */
556 void omap_clear_dma(int lch)
557 {
558         unsigned long flags;
559
560         local_irq_save(flags);
561
562         if (cpu_class_is_omap1()) {
563                 int status;
564                 OMAP_DMA_CCR_REG(lch) &= ~OMAP_DMA_CCR_EN;
565
566                 /* Clear pending interrupts */
567                 status = OMAP_DMA_CSR_REG(lch);
568         }
569
570         if (cpu_is_omap24xx()) {
571                 int i;
572                 u32 lch_base = OMAP24XX_DMA_BASE + lch * 0x60 + 0x80;
573                 for (i = 0; i < 0x44; i += 4)
574                         omap_writel(0, lch_base + i);
575         }
576
577         local_irq_restore(flags);
578 }
579
580 void omap_start_dma(int lch)
581 {
582         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
583                 int next_lch, cur_lch;
584                 char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT];
585
586                 dma_chan_link_map[lch] = 1;
587                 /* Set the link register of the first channel */
588                 enable_lnk(lch);
589
590                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
591                 cur_lch = dma_chan[lch].next_lch;
592                 do {
593                         next_lch = dma_chan[cur_lch].next_lch;
594
595                         /* The loop case: we've been here already */
596                         if (dma_chan_link_map[cur_lch])
597                                 break;
598                         /* Mark the current channel */
599                         dma_chan_link_map[cur_lch] = 1;
600
601                         enable_lnk(cur_lch);
602                         omap_enable_channel_irq(cur_lch);
603
604                         cur_lch = next_lch;
605                 } while (next_lch != -1);
606         } else if (cpu_is_omap24xx()) {
607                 /* Errata: Need to write lch even if not using chaining */
608                 OMAP_DMA_CLNK_CTRL_REG(lch) = lch;
609         }
610
611         omap_enable_channel_irq(lch);
612
613         /* Errata: On ES2.0 BUFFERING disable must be set.
614          * This will always fail on ES1.0 */
615         if (cpu_is_omap24xx()) {
616                 OMAP_DMA_CCR_REG(lch) |= OMAP_DMA_CCR_EN;
617         }
618
619         OMAP_DMA_CCR_REG(lch) |= OMAP_DMA_CCR_EN;
620
621         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
622 }
623
624 void omap_stop_dma(int lch)
625 {
626         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
627                 int next_lch, cur_lch = lch;
628                 char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT];
629
630                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
631                 do {
632                         /* The loop case: we've been here already */
633                         if (dma_chan_link_map[cur_lch])
634                                 break;
635                         /* Mark the current channel */
636                         dma_chan_link_map[cur_lch] = 1;
637
638                         disable_lnk(cur_lch);
639
640                         next_lch = dma_chan[cur_lch].next_lch;
641                         cur_lch = next_lch;
642                 } while (next_lch != -1);
643
644                 return;
645         }
646
647         /* Disable all interrupts on the channel */
648         if (cpu_class_is_omap1())
649                 OMAP_DMA_CICR_REG(lch) = 0;
650
651         OMAP_DMA_CCR_REG(lch) &= ~OMAP_DMA_CCR_EN;
652         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
653 }
654
655 /*
656  * Returns current physical source address for the given DMA channel.
657  * If the channel is running the caller must disable interrupts prior calling
658  * this function and process the returned value before re-enabling interrupt to
659  * prevent races with the interrupt handler. Note that in continuous mode there
660  * is a chance for CSSA_L register overflow inbetween the two reads resulting
661  * in incorrect return value.
662  */
663 dma_addr_t omap_get_dma_src_pos(int lch)
664 {
665         dma_addr_t offset;
666
667         if (cpu_class_is_omap1())
668                 offset = (dma_addr_t) (OMAP1_DMA_CSSA_L_REG(lch) |
669                                        (OMAP1_DMA_CSSA_U_REG(lch) << 16));
670
671         if (cpu_is_omap24xx())
672                 offset = OMAP_DMA_CSAC_REG(lch);
673
674         return offset;
675 }
676
677 /*
678  * Returns current physical destination address for the given DMA channel.
679  * If the channel is running the caller must disable interrupts prior calling
680  * this function and process the returned value before re-enabling interrupt to
681  * prevent races with the interrupt handler. Note that in continuous mode there
682  * is a chance for CDSA_L register overflow inbetween the two reads resulting
683  * in incorrect return value.
684  */
685 dma_addr_t omap_get_dma_dst_pos(int lch)
686 {
687         dma_addr_t offset;
688
689         if (cpu_class_is_omap1())
690                 offset = (dma_addr_t) (OMAP1_DMA_CDSA_L_REG(lch) |
691                                        (OMAP1_DMA_CDSA_U_REG(lch) << 16));
692
693         if (cpu_is_omap24xx())
694                 offset = OMAP2_DMA_CDSA_REG(lch);
695
696         return offset;
697 }
698
699 /*
700  * Returns current source transfer counting for the given DMA channel.
701  * Can be used to monitor the progress of a transfer inside a block.
702  * It must be called with disabled interrupts.
703  */
704 int omap_get_dma_src_addr_counter(int lch)
705 {
706         return (dma_addr_t) OMAP_DMA_CSAC_REG(lch);
707 }
708
709 int omap_dma_running(void)
710 {
711         int lch;
712
713         /* Check if LCD DMA is running */
714         if (cpu_is_omap16xx())
715                 if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
716                         return 1;
717
718         for (lch = 0; lch < dma_chan_count; lch++)
719                 if (OMAP_DMA_CCR_REG(lch) & OMAP_DMA_CCR_EN)
720                         return 1;
721
722         return 0;
723 }
724
725 /*
726  * lch_queue DMA will start right after lch_head one is finished.
727  * For this DMA link to start, you still need to start (see omap_start_dma)
728  * the first one. That will fire up the entire queue.
729  */
730 void omap_dma_link_lch (int lch_head, int lch_queue)
731 {
732         if (omap_dma_in_1510_mode()) {
733                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
734                 BUG();
735                 return;
736         }
737
738         if ((dma_chan[lch_head].dev_id == -1) ||
739             (dma_chan[lch_queue].dev_id == -1)) {
740                 printk(KERN_ERR "omap_dma: trying to link "
741                        "non requested channels\n");
742                 dump_stack();
743         }
744
745         dma_chan[lch_head].next_lch = lch_queue;
746 }
747
748 /*
749  * Once the DMA queue is stopped, we can destroy it.
750  */
751 void omap_dma_unlink_lch (int lch_head, int lch_queue)
752 {
753         if (omap_dma_in_1510_mode()) {
754                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
755                 BUG();
756                 return;
757         }
758
759         if (dma_chan[lch_head].next_lch != lch_queue ||
760             dma_chan[lch_head].next_lch == -1) {
761                 printk(KERN_ERR "omap_dma: trying to unlink "
762                        "non linked channels\n");
763                 dump_stack();
764         }
765
766
767         if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
768             (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
769                 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
770                        "before unlinking\n");
771                 dump_stack();
772         }
773
774         dma_chan[lch_head].next_lch = -1;
775 }
776
777 /*----------------------------------------------------------------------------*/
778
779 #ifdef CONFIG_ARCH_OMAP1
780
781 static int omap1_dma_handle_ch(int ch)
782 {
783         u16 csr;
784
785         if (enable_1510_mode && ch >= 6) {
786                 csr = dma_chan[ch].saved_csr;
787                 dma_chan[ch].saved_csr = 0;
788         } else
789                 csr = OMAP_DMA_CSR_REG(ch);
790         if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
791                 dma_chan[ch + 6].saved_csr = csr >> 7;
792                 csr &= 0x7f;
793         }
794         if ((csr & 0x3f) == 0)
795                 return 0;
796         if (unlikely(dma_chan[ch].dev_id == -1)) {
797                 printk(KERN_WARNING "Spurious interrupt from DMA channel "
798                        "%d (CSR %04x)\n", ch, csr);
799                 return 0;
800         }
801         if (unlikely(csr & OMAP_DMA_TOUT_IRQ))
802                 printk(KERN_WARNING "DMA timeout with device %d\n",
803                        dma_chan[ch].dev_id);
804         if (unlikely(csr & OMAP_DMA_DROP_IRQ))
805                 printk(KERN_WARNING "DMA synchronization event drop occurred "
806                        "with device %d\n", dma_chan[ch].dev_id);
807         if (likely(csr & OMAP_DMA_BLOCK_IRQ))
808                 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
809         if (likely(dma_chan[ch].callback != NULL))
810                 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
811         return 1;
812 }
813
814 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id,
815                                          struct pt_regs *regs)
816 {
817         int ch = ((int) dev_id) - 1;
818         int handled = 0;
819
820         for (;;) {
821                 int handled_now = 0;
822
823                 handled_now += omap1_dma_handle_ch(ch);
824                 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
825                         handled_now += omap1_dma_handle_ch(ch + 6);
826                 if (!handled_now)
827                         break;
828                 handled += handled_now;
829         }
830
831         return handled ? IRQ_HANDLED : IRQ_NONE;
832 }
833
834 #else
835 #define omap1_dma_irq_handler   NULL
836 #endif
837
838 #ifdef CONFIG_ARCH_OMAP2
839
840 static int omap2_dma_handle_ch(int ch)
841 {
842         u32 status = OMAP_DMA_CSR_REG(ch);
843         u32 val;
844
845         if (!status)
846                 return 0;
847         if (unlikely(dma_chan[ch].dev_id == -1))
848                 return 0;
849         /* REVISIT: According to 24xx TRM, there's no TOUT_IE */
850         if (unlikely(status & OMAP_DMA_TOUT_IRQ))
851                 printk(KERN_INFO "DMA timeout with device %d\n",
852                        dma_chan[ch].dev_id);
853         if (unlikely(status & OMAP_DMA_DROP_IRQ))
854                 printk(KERN_INFO
855                        "DMA synchronization event drop occurred with device "
856                        "%d\n", dma_chan[ch].dev_id);
857
858         if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ))
859                 printk(KERN_INFO "DMA transaction error with device %d\n",
860                        dma_chan[ch].dev_id);
861
862         OMAP_DMA_CSR_REG(ch) = 0x20;
863
864         val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
865         /* ch in this function is from 0-31 while in register it is 1-32 */
866         val = 1 << (ch);
867         omap_writel(val, OMAP_DMA4_IRQSTATUS_L0);
868
869         if (likely(dma_chan[ch].callback != NULL))
870                 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
871
872         return 0;
873 }
874
875 /* STATUS register count is from 1-32 while our is 0-31 */
876 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id,
877                                          struct pt_regs *regs)
878 {
879         u32 val;
880         int i;
881
882         val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
883
884         for (i = 1; i <= OMAP_LOGICAL_DMA_CH_COUNT; i++) {
885                 int active = val & (1 << (i - 1));
886                 if (active)
887                         omap2_dma_handle_ch(i - 1);
888         }
889
890         return IRQ_HANDLED;
891 }
892
893 static struct irqaction omap24xx_dma_irq = {
894         .name = "DMA",
895         .handler = omap2_dma_irq_handler,
896         .flags = SA_INTERRUPT
897 };
898
899 #else
900 static struct irqaction omap24xx_dma_irq;
901 #endif
902
903 /*----------------------------------------------------------------------------*/
904
905 static struct lcd_dma_info {
906         spinlock_t lock;
907         int reserved;
908         void (* callback)(u16 status, void *data);
909         void *cb_data;
910
911         int active;
912         unsigned long addr, size;
913         int rotate, data_type, xres, yres;
914         int vxres;
915         int mirror;
916         int xscale, yscale;
917         int ext_ctrl;
918         int src_port;
919         int single_transfer;
920 } lcd_dma;
921
922 void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
923                          int data_type)
924 {
925         lcd_dma.addr = addr;
926         lcd_dma.data_type = data_type;
927         lcd_dma.xres = fb_xres;
928         lcd_dma.yres = fb_yres;
929 }
930
931 void omap_set_lcd_dma_src_port(int port)
932 {
933         lcd_dma.src_port = port;
934 }
935
936 void omap_set_lcd_dma_ext_controller(int external)
937 {
938         lcd_dma.ext_ctrl = external;
939 }
940
941 void omap_set_lcd_dma_single_transfer(int single)
942 {
943         lcd_dma.single_transfer = single;
944 }
945
946
947 void omap_set_lcd_dma_b1_rotation(int rotate)
948 {
949         if (omap_dma_in_1510_mode()) {
950                 printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
951                 BUG();
952                 return;
953         }
954         lcd_dma.rotate = rotate;
955 }
956
957 void omap_set_lcd_dma_b1_mirror(int mirror)
958 {
959         if (omap_dma_in_1510_mode()) {
960                 printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
961                 BUG();
962         }
963         lcd_dma.mirror = mirror;
964 }
965
966 void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
967 {
968         if (omap_dma_in_1510_mode()) {
969                 printk(KERN_ERR "DMA virtual resulotion is not supported "
970                                 "in 1510 mode\n");
971                 BUG();
972         }
973         lcd_dma.vxres = vxres;
974 }
975
976 void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
977 {
978         if (omap_dma_in_1510_mode()) {
979                 printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
980                 BUG();
981         }
982         lcd_dma.xscale = xscale;
983         lcd_dma.yscale = yscale;
984 }
985
986 static void set_b1_regs(void)
987 {
988         unsigned long top, bottom;
989         int es;
990         u16 w;
991         unsigned long en, fn;
992         long ei, fi;
993         unsigned long vxres;
994         unsigned int xscale, yscale;
995
996         switch (lcd_dma.data_type) {
997         case OMAP_DMA_DATA_TYPE_S8:
998                 es = 1;
999                 break;
1000         case OMAP_DMA_DATA_TYPE_S16:
1001                 es = 2;
1002                 break;
1003         case OMAP_DMA_DATA_TYPE_S32:
1004                 es = 4;
1005                 break;
1006         default:
1007                 BUG();
1008                 return;
1009         }
1010
1011         vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
1012         xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
1013         yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
1014         BUG_ON(vxres < lcd_dma.xres);
1015 #define PIXADDR(x,y) (lcd_dma.addr + ((y) * vxres * yscale + (x) * xscale) * es)
1016 #define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
1017         switch (lcd_dma.rotate) {
1018         case 0:
1019                 if (!lcd_dma.mirror) {
1020                         top = PIXADDR(0, 0);
1021                         bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
1022                         /* 1510 DMA requires the bottom address to be 2 more
1023                          * than the actual last memory access location. */
1024                         if (omap_dma_in_1510_mode() &&
1025                             lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
1026                                 bottom += 2;
1027                         ei = PIXSTEP(0, 0, 1, 0);
1028                         fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
1029                 } else {
1030                         top = PIXADDR(lcd_dma.xres - 1, 0);
1031                         bottom = PIXADDR(0, lcd_dma.yres - 1);
1032                         ei = PIXSTEP(1, 0, 0, 0);
1033                         fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
1034                 }
1035                 en = lcd_dma.xres;
1036                 fn = lcd_dma.yres;
1037                 break;
1038         case 90:
1039                 if (!lcd_dma.mirror) {
1040                         top = PIXADDR(0, lcd_dma.yres - 1);
1041                         bottom = PIXADDR(lcd_dma.xres - 1, 0);
1042                         ei = PIXSTEP(0, 1, 0, 0);
1043                         fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
1044                 } else {
1045                         top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
1046                         bottom = PIXADDR(0, 0);
1047                         ei = PIXSTEP(0, 1, 0, 0);
1048                         fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
1049                 }
1050                 en = lcd_dma.yres;
1051                 fn = lcd_dma.xres;
1052                 break;
1053         case 180:
1054                 if (!lcd_dma.mirror) {
1055                         top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
1056                         bottom = PIXADDR(0, 0);
1057                         ei = PIXSTEP(1, 0, 0, 0);
1058                         fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
1059                 } else {
1060                         top = PIXADDR(0, lcd_dma.yres - 1);
1061                         bottom = PIXADDR(lcd_dma.xres - 1, 0);
1062                         ei = PIXSTEP(0, 0, 1, 0);
1063                         fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
1064                 }
1065                 en = lcd_dma.xres;
1066                 fn = lcd_dma.yres;
1067                 break;
1068         case 270:
1069                 if (!lcd_dma.mirror) {
1070                         top = PIXADDR(lcd_dma.xres - 1, 0);
1071                         bottom = PIXADDR(0, lcd_dma.yres - 1);
1072                         ei = PIXSTEP(0, 0, 0, 1);
1073                         fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
1074                 } else {
1075                         top = PIXADDR(0, 0);
1076                         bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
1077                         ei = PIXSTEP(0, 0, 0, 1);
1078                         fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
1079                 }
1080                 en = lcd_dma.yres;
1081                 fn = lcd_dma.xres;
1082                 break;
1083         default:
1084                 BUG();
1085                 return; /* Supress warning about uninitialized vars */
1086         }
1087
1088         if (omap_dma_in_1510_mode()) {
1089                 omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
1090                 omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
1091                 omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
1092                 omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
1093
1094                 return;
1095         }
1096
1097         /* 1610 regs */
1098         omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
1099         omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
1100         omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
1101         omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
1102
1103         omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
1104         omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
1105
1106         w = omap_readw(OMAP1610_DMA_LCD_CSDP);
1107         w &= ~0x03;
1108         w |= lcd_dma.data_type;
1109         omap_writew(w, OMAP1610_DMA_LCD_CSDP);
1110
1111         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
1112         /* Always set the source port as SDRAM for now*/
1113         w &= ~(0x03 << 6);
1114         if (lcd_dma.callback != NULL)
1115                 w |= 1 << 1;            /* Block interrupt enable */
1116         else
1117                 w &= ~(1 << 1);
1118         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
1119
1120         if (!(lcd_dma.rotate || lcd_dma.mirror ||
1121               lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
1122                 return;
1123
1124         w = omap_readw(OMAP1610_DMA_LCD_CCR);
1125         /* Set the double-indexed addressing mode */
1126         w |= (0x03 << 12);
1127         omap_writew(w, OMAP1610_DMA_LCD_CCR);
1128
1129         omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
1130         omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
1131         omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
1132 }
1133
1134 static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id,
1135                                        struct pt_regs *regs)
1136 {
1137         u16 w;
1138
1139         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
1140         if (unlikely(!(w & (1 << 3)))) {
1141                 printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
1142                 return IRQ_NONE;
1143         }
1144         /* Ack the IRQ */
1145         w |= (1 << 3);
1146         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
1147         lcd_dma.active = 0;
1148         if (lcd_dma.callback != NULL)
1149                 lcd_dma.callback(w, lcd_dma.cb_data);
1150
1151         return IRQ_HANDLED;
1152 }
1153
1154 int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
1155                          void *data)
1156 {
1157         spin_lock_irq(&lcd_dma.lock);
1158         if (lcd_dma.reserved) {
1159                 spin_unlock_irq(&lcd_dma.lock);
1160                 printk(KERN_ERR "LCD DMA channel already reserved\n");
1161                 BUG();
1162                 return -EBUSY;
1163         }
1164         lcd_dma.reserved = 1;
1165         spin_unlock_irq(&lcd_dma.lock);
1166         lcd_dma.callback = callback;
1167         lcd_dma.cb_data = data;
1168         lcd_dma.active = 0;
1169         lcd_dma.single_transfer = 0;
1170         lcd_dma.rotate = 0;
1171         lcd_dma.vxres = 0;
1172         lcd_dma.mirror = 0;
1173         lcd_dma.xscale = 0;
1174         lcd_dma.yscale = 0;
1175         lcd_dma.ext_ctrl = 0;
1176         lcd_dma.src_port = 0;
1177
1178         return 0;
1179 }
1180
1181 void omap_free_lcd_dma(void)
1182 {
1183         spin_lock(&lcd_dma.lock);
1184         if (!lcd_dma.reserved) {
1185                 spin_unlock(&lcd_dma.lock);
1186                 printk(KERN_ERR "LCD DMA is not reserved\n");
1187                 BUG();
1188                 return;
1189         }
1190         if (!enable_1510_mode)
1191                 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
1192                             OMAP1610_DMA_LCD_CCR);
1193         lcd_dma.reserved = 0;
1194         spin_unlock(&lcd_dma.lock);
1195 }
1196
1197 void omap_enable_lcd_dma(void)
1198 {
1199         u16 w;
1200
1201         /* Set the Enable bit only if an external controller is
1202          * connected. Otherwise the OMAP internal controller will
1203          * start the transfer when it gets enabled.
1204          */
1205         if (enable_1510_mode || !lcd_dma.ext_ctrl)
1206                 return;
1207
1208         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
1209         w |= 1 << 8;
1210         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
1211
1212         lcd_dma.active = 1;
1213
1214         w = omap_readw(OMAP1610_DMA_LCD_CCR);
1215         w |= 1 << 7;
1216         omap_writew(w, OMAP1610_DMA_LCD_CCR);
1217 }
1218
1219 void omap_setup_lcd_dma(void)
1220 {
1221         BUG_ON(lcd_dma.active);
1222         if (!enable_1510_mode) {
1223                 /* Set some reasonable defaults */
1224                 omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
1225                 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
1226                 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
1227         }
1228         set_b1_regs();
1229         if (!enable_1510_mode) {
1230                 u16 w;
1231
1232                 w = omap_readw(OMAP1610_DMA_LCD_CCR);
1233                 /* If DMA was already active set the end_prog bit to have
1234                  * the programmed register set loaded into the active
1235                  * register set.
1236                  */
1237                 w |= 1 << 11;           /* End_prog */
1238                 if (!lcd_dma.single_transfer)
1239                         w |= (3 << 8);  /* Auto_init, repeat */
1240                 omap_writew(w, OMAP1610_DMA_LCD_CCR);
1241         }
1242 }
1243
1244 void omap_stop_lcd_dma(void)
1245 {
1246         u16 w;
1247
1248         lcd_dma.active = 0;
1249         if (enable_1510_mode || !lcd_dma.ext_ctrl)
1250                 return;
1251
1252         w = omap_readw(OMAP1610_DMA_LCD_CCR);
1253         w &= ~(1 << 7);
1254         omap_writew(w, OMAP1610_DMA_LCD_CCR);
1255
1256         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
1257         w &= ~(1 << 8);
1258         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
1259 }
1260
1261 /*----------------------------------------------------------------------------*/
1262
1263 static int __init omap_init_dma(void)
1264 {
1265         int ch, r;
1266
1267         if (cpu_is_omap15xx()) {
1268                 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
1269                 dma_chan_count = 9;
1270                 enable_1510_mode = 1;
1271         } else if (cpu_is_omap16xx() || cpu_is_omap730()) {
1272                 printk(KERN_INFO "OMAP DMA hardware version %d\n",
1273                        omap_readw(OMAP_DMA_HW_ID));
1274                 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
1275                        (omap_readw(OMAP_DMA_CAPS_0_U) << 16) |
1276                        omap_readw(OMAP_DMA_CAPS_0_L),
1277                        (omap_readw(OMAP_DMA_CAPS_1_U) << 16) |
1278                        omap_readw(OMAP_DMA_CAPS_1_L),
1279                        omap_readw(OMAP_DMA_CAPS_2), omap_readw(OMAP_DMA_CAPS_3),
1280                        omap_readw(OMAP_DMA_CAPS_4));
1281                 if (!enable_1510_mode) {
1282                         u16 w;
1283
1284                         /* Disable OMAP 3.0/3.1 compatibility mode. */
1285                         w = omap_readw(OMAP_DMA_GSCR);
1286                         w |= 1 << 3;
1287                         omap_writew(w, OMAP_DMA_GSCR);
1288                         dma_chan_count = 16;
1289                 } else
1290                         dma_chan_count = 9;
1291         } else if (cpu_is_omap24xx()) {
1292                 u8 revision = omap_readb(OMAP_DMA4_REVISION);
1293                 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
1294                        revision >> 4, revision & 0xf);
1295                 dma_chan_count = OMAP_LOGICAL_DMA_CH_COUNT;
1296         } else {
1297                 dma_chan_count = 0;
1298                 return 0;
1299         }
1300
1301         memset(&lcd_dma, 0, sizeof(lcd_dma));
1302         spin_lock_init(&lcd_dma.lock);
1303         spin_lock_init(&dma_chan_lock);
1304         memset(&dma_chan, 0, sizeof(dma_chan));
1305
1306         for (ch = 0; ch < dma_chan_count; ch++) {
1307                 omap_clear_dma(ch);
1308                 dma_chan[ch].dev_id = -1;
1309                 dma_chan[ch].next_lch = -1;
1310
1311                 if (ch >= 6 && enable_1510_mode)
1312                         continue;
1313
1314                 if (cpu_class_is_omap1()) {
1315                         /* request_irq() doesn't like dev_id (ie. ch) being
1316                          * zero, so we have to kludge around this. */
1317                         r = request_irq(omap1_dma_irq[ch],
1318                                         omap1_dma_irq_handler, 0, "DMA",
1319                                         (void *) (ch + 1));
1320                         if (r != 0) {
1321                                 int i;
1322
1323                                 printk(KERN_ERR "unable to request IRQ %d "
1324                                        "for DMA (error %d)\n",
1325                                        omap1_dma_irq[ch], r);
1326                                 for (i = 0; i < ch; i++)
1327                                         free_irq(omap1_dma_irq[i],
1328                                                  (void *) (i + 1));
1329                                 return r;
1330                         }
1331                 }
1332         }
1333
1334         if (cpu_is_omap24xx())
1335                 setup_irq(INT_24XX_SDMA_IRQ0, &omap24xx_dma_irq);
1336
1337         /* FIXME: Update LCD DMA to work on 24xx */
1338         if (cpu_class_is_omap1()) {
1339                 r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
1340                                 "LCD DMA", NULL);
1341                 if (r != 0) {
1342                         int i;
1343
1344                         printk(KERN_ERR "unable to request IRQ for LCD DMA "
1345                                "(error %d)\n", r);
1346                         for (i = 0; i < dma_chan_count; i++)
1347                                 free_irq(omap1_dma_irq[i], (void *) (i + 1));
1348                         return r;
1349                 }
1350         }
1351
1352         return 0;
1353 }
1354
1355 arch_initcall(omap_init_dma);
1356
1357 EXPORT_SYMBOL(omap_get_dma_src_pos);
1358 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1359 EXPORT_SYMBOL(omap_get_dma_src_addr_counter);
1360 EXPORT_SYMBOL(omap_clear_dma);
1361 EXPORT_SYMBOL(omap_set_dma_priority);
1362 EXPORT_SYMBOL(omap_request_dma);
1363 EXPORT_SYMBOL(omap_free_dma);
1364 EXPORT_SYMBOL(omap_start_dma);
1365 EXPORT_SYMBOL(omap_stop_dma);
1366 EXPORT_SYMBOL(omap_enable_dma_irq);
1367 EXPORT_SYMBOL(omap_disable_dma_irq);
1368
1369 EXPORT_SYMBOL(omap_set_dma_transfer_params);
1370 EXPORT_SYMBOL(omap_set_dma_color_mode);
1371
1372 EXPORT_SYMBOL(omap_set_dma_src_params);
1373 EXPORT_SYMBOL(omap_set_dma_src_index);
1374 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
1375 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
1376
1377 EXPORT_SYMBOL(omap_set_dma_dest_params);
1378 EXPORT_SYMBOL(omap_set_dma_dest_index);
1379 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
1380 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
1381
1382 EXPORT_SYMBOL(omap_set_dma_params);
1383
1384 EXPORT_SYMBOL(omap_dma_link_lch);
1385 EXPORT_SYMBOL(omap_dma_unlink_lch);
1386
1387 EXPORT_SYMBOL(omap_request_lcd_dma);
1388 EXPORT_SYMBOL(omap_free_lcd_dma);
1389 EXPORT_SYMBOL(omap_enable_lcd_dma);
1390 EXPORT_SYMBOL(omap_setup_lcd_dma);
1391 EXPORT_SYMBOL(omap_stop_lcd_dma);
1392 EXPORT_SYMBOL(omap_set_lcd_dma_b1);
1393 EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
1394 EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
1395 EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
1396 EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
1397 EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
1398 EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
1399