Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6.git] / arch / arm / plat-omap / dma.c
1 /*
2  * linux/arch/arm/plat-omap/dma.c
3  *
4  * Copyright (C) 2003 - 2008 Nokia Corporation
5  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6  * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7  * Graphics DMA and LCD DMA graphics tranformations
8  * by Imre Deak <imre.deak@nokia.com>
9  * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10  * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11  * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
12  *
13  * Copyright (C) 2009 Texas Instruments
14  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
15  *
16  * Support functions for the OMAP internal DMA channels.
17  *
18  * This program is free software; you can redistribute it and/or modify
19  * it under the terms of the GNU General Public License version 2 as
20  * published by the Free Software Foundation.
21  *
22  */
23
24 #include <linux/module.h>
25 #include <linux/init.h>
26 #include <linux/sched.h>
27 #include <linux/spinlock.h>
28 #include <linux/errno.h>
29 #include <linux/interrupt.h>
30 #include <linux/irq.h>
31 #include <linux/io.h>
32
33 #include <asm/system.h>
34 #include <mach/hardware.h>
35 #include <plat/dma.h>
36
37 #include <plat/tc.h>
38
39 #undef DEBUG
40
41 #ifndef CONFIG_ARCH_OMAP1
42 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
43         DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
44 };
45
46 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
47 #endif
48
49 #define OMAP_DMA_ACTIVE                 0x01
50 #define OMAP2_DMA_CSR_CLEAR_MASK        0xffe
51
52 #define OMAP_FUNC_MUX_ARM_BASE          (0xfffe1000 + 0xec)
53
54 static int enable_1510_mode;
55
56 static struct omap_dma_global_context_registers {
57         u32 dma_irqenable_l0;
58         u32 dma_ocp_sysconfig;
59         u32 dma_gcr;
60 } omap_dma_global_context;
61
62 struct omap_dma_lch {
63         int next_lch;
64         int dev_id;
65         u16 saved_csr;
66         u16 enabled_irqs;
67         const char *dev_name;
68         void (*callback)(int lch, u16 ch_status, void *data);
69         void *data;
70
71 #ifndef CONFIG_ARCH_OMAP1
72         /* required for Dynamic chaining */
73         int prev_linked_ch;
74         int next_linked_ch;
75         int state;
76         int chain_id;
77
78         int status;
79 #endif
80         long flags;
81 };
82
83 struct dma_link_info {
84         int *linked_dmach_q;
85         int no_of_lchs_linked;
86
87         int q_count;
88         int q_tail;
89         int q_head;
90
91         int chain_state;
92         int chain_mode;
93
94 };
95
96 static struct dma_link_info *dma_linked_lch;
97
98 #ifndef CONFIG_ARCH_OMAP1
99
100 /* Chain handling macros */
101 #define OMAP_DMA_CHAIN_QINIT(chain_id)                                  \
102         do {                                                            \
103                 dma_linked_lch[chain_id].q_head =                       \
104                 dma_linked_lch[chain_id].q_tail =                       \
105                 dma_linked_lch[chain_id].q_count = 0;                   \
106         } while (0)
107 #define OMAP_DMA_CHAIN_QFULL(chain_id)                                  \
108                 (dma_linked_lch[chain_id].no_of_lchs_linked ==          \
109                 dma_linked_lch[chain_id].q_count)
110 #define OMAP_DMA_CHAIN_QLAST(chain_id)                                  \
111         do {                                                            \
112                 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) ==      \
113                 dma_linked_lch[chain_id].q_count)                       \
114         } while (0)
115 #define OMAP_DMA_CHAIN_QEMPTY(chain_id)                                 \
116                 (0 == dma_linked_lch[chain_id].q_count)
117 #define __OMAP_DMA_CHAIN_INCQ(end)                                      \
118         ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
119 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id)                               \
120         do {                                                            \
121                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
122                 dma_linked_lch[chain_id].q_count--;                     \
123         } while (0)
124
125 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id)                               \
126         do {                                                            \
127                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
128                 dma_linked_lch[chain_id].q_count++; \
129         } while (0)
130 #endif
131
132 static int dma_lch_count;
133 static int dma_chan_count;
134 static int omap_dma_reserve_channels;
135
136 static spinlock_t dma_chan_lock;
137 static struct omap_dma_lch *dma_chan;
138 static void __iomem *omap_dma_base;
139
140 static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = {
141         INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
142         INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
143         INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
144         INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
145         INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
146 };
147
148 static inline void disable_lnk(int lch);
149 static void omap_disable_channel_irq(int lch);
150 static inline void omap_enable_channel_irq(int lch);
151
152 #define REVISIT_24XX()          printk(KERN_ERR "FIXME: no %s on 24xx\n", \
153                                                 __func__);
154
155 #define dma_read(reg)                                                   \
156 ({                                                                      \
157         u32 __val;                                                      \
158         if (cpu_class_is_omap1())                                       \
159                 __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg);   \
160         else                                                            \
161                 __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg);   \
162         __val;                                                          \
163 })
164
165 #define dma_write(val, reg)                                             \
166 ({                                                                      \
167         if (cpu_class_is_omap1())                                       \
168                 __raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \
169         else                                                            \
170                 __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg);   \
171 })
172
173 #ifdef CONFIG_ARCH_OMAP15XX
174 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
175 int omap_dma_in_1510_mode(void)
176 {
177         return enable_1510_mode;
178 }
179 #else
180 #define omap_dma_in_1510_mode()         0
181 #endif
182
183 #ifdef CONFIG_ARCH_OMAP1
184 static inline int get_gdma_dev(int req)
185 {
186         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
187         int shift = ((req - 1) % 5) * 6;
188
189         return ((omap_readl(reg) >> shift) & 0x3f) + 1;
190 }
191
192 static inline void set_gdma_dev(int req, int dev)
193 {
194         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
195         int shift = ((req - 1) % 5) * 6;
196         u32 l;
197
198         l = omap_readl(reg);
199         l &= ~(0x3f << shift);
200         l |= (dev - 1) << shift;
201         omap_writel(l, reg);
202 }
203 #else
204 #define set_gdma_dev(req, dev)  do {} while (0)
205 #endif
206
207 /* Omap1 only */
208 static void clear_lch_regs(int lch)
209 {
210         int i;
211         void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch);
212
213         for (i = 0; i < 0x2c; i += 2)
214                 __raw_writew(0, lch_base + i);
215 }
216
217 void omap_set_dma_priority(int lch, int dst_port, int priority)
218 {
219         unsigned long reg;
220         u32 l;
221
222         if (cpu_class_is_omap1()) {
223                 switch (dst_port) {
224                 case OMAP_DMA_PORT_OCP_T1:      /* FFFECC00 */
225                         reg = OMAP_TC_OCPT1_PRIOR;
226                         break;
227                 case OMAP_DMA_PORT_OCP_T2:      /* FFFECCD0 */
228                         reg = OMAP_TC_OCPT2_PRIOR;
229                         break;
230                 case OMAP_DMA_PORT_EMIFF:       /* FFFECC08 */
231                         reg = OMAP_TC_EMIFF_PRIOR;
232                         break;
233                 case OMAP_DMA_PORT_EMIFS:       /* FFFECC04 */
234                         reg = OMAP_TC_EMIFS_PRIOR;
235                         break;
236                 default:
237                         BUG();
238                         return;
239                 }
240                 l = omap_readl(reg);
241                 l &= ~(0xf << 8);
242                 l |= (priority & 0xf) << 8;
243                 omap_writel(l, reg);
244         }
245
246         if (cpu_class_is_omap2()) {
247                 u32 ccr;
248
249                 ccr = dma_read(CCR(lch));
250                 if (priority)
251                         ccr |= (1 << 6);
252                 else
253                         ccr &= ~(1 << 6);
254                 dma_write(ccr, CCR(lch));
255         }
256 }
257 EXPORT_SYMBOL(omap_set_dma_priority);
258
259 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
260                                   int frame_count, int sync_mode,
261                                   int dma_trigger, int src_or_dst_synch)
262 {
263         u32 l;
264
265         l = dma_read(CSDP(lch));
266         l &= ~0x03;
267         l |= data_type;
268         dma_write(l, CSDP(lch));
269
270         if (cpu_class_is_omap1()) {
271                 u16 ccr;
272
273                 ccr = dma_read(CCR(lch));
274                 ccr &= ~(1 << 5);
275                 if (sync_mode == OMAP_DMA_SYNC_FRAME)
276                         ccr |= 1 << 5;
277                 dma_write(ccr, CCR(lch));
278
279                 ccr = dma_read(CCR2(lch));
280                 ccr &= ~(1 << 2);
281                 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
282                         ccr |= 1 << 2;
283                 dma_write(ccr, CCR2(lch));
284         }
285
286         if (cpu_class_is_omap2() && dma_trigger) {
287                 u32 val;
288
289                 val = dma_read(CCR(lch));
290
291                 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
292                 val &= ~((3 << 19) | 0x1f);
293                 val |= (dma_trigger & ~0x1f) << 14;
294                 val |= dma_trigger & 0x1f;
295
296                 if (sync_mode & OMAP_DMA_SYNC_FRAME)
297                         val |= 1 << 5;
298                 else
299                         val &= ~(1 << 5);
300
301                 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
302                         val |= 1 << 18;
303                 else
304                         val &= ~(1 << 18);
305
306                 if (src_or_dst_synch)
307                         val |= 1 << 24;         /* source synch */
308                 else
309                         val &= ~(1 << 24);      /* dest synch */
310
311                 dma_write(val, CCR(lch));
312         }
313
314         dma_write(elem_count, CEN(lch));
315         dma_write(frame_count, CFN(lch));
316 }
317 EXPORT_SYMBOL(omap_set_dma_transfer_params);
318
319 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
320 {
321         BUG_ON(omap_dma_in_1510_mode());
322
323         if (cpu_class_is_omap1()) {
324                 u16 w;
325
326                 w = dma_read(CCR2(lch));
327                 w &= ~0x03;
328
329                 switch (mode) {
330                 case OMAP_DMA_CONSTANT_FILL:
331                         w |= 0x01;
332                         break;
333                 case OMAP_DMA_TRANSPARENT_COPY:
334                         w |= 0x02;
335                         break;
336                 case OMAP_DMA_COLOR_DIS:
337                         break;
338                 default:
339                         BUG();
340                 }
341                 dma_write(w, CCR2(lch));
342
343                 w = dma_read(LCH_CTRL(lch));
344                 w &= ~0x0f;
345                 /* Default is channel type 2D */
346                 if (mode) {
347                         dma_write((u16)color, COLOR_L(lch));
348                         dma_write((u16)(color >> 16), COLOR_U(lch));
349                         w |= 1;         /* Channel type G */
350                 }
351                 dma_write(w, LCH_CTRL(lch));
352         }
353
354         if (cpu_class_is_omap2()) {
355                 u32 val;
356
357                 val = dma_read(CCR(lch));
358                 val &= ~((1 << 17) | (1 << 16));
359
360                 switch (mode) {
361                 case OMAP_DMA_CONSTANT_FILL:
362                         val |= 1 << 16;
363                         break;
364                 case OMAP_DMA_TRANSPARENT_COPY:
365                         val |= 1 << 17;
366                         break;
367                 case OMAP_DMA_COLOR_DIS:
368                         break;
369                 default:
370                         BUG();
371                 }
372                 dma_write(val, CCR(lch));
373
374                 color &= 0xffffff;
375                 dma_write(color, COLOR(lch));
376         }
377 }
378 EXPORT_SYMBOL(omap_set_dma_color_mode);
379
380 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
381 {
382         if (cpu_class_is_omap2()) {
383                 u32 csdp;
384
385                 csdp = dma_read(CSDP(lch));
386                 csdp &= ~(0x3 << 16);
387                 csdp |= (mode << 16);
388                 dma_write(csdp, CSDP(lch));
389         }
390 }
391 EXPORT_SYMBOL(omap_set_dma_write_mode);
392
393 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
394 {
395         if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
396                 u32 l;
397
398                 l = dma_read(LCH_CTRL(lch));
399                 l &= ~0x7;
400                 l |= mode;
401                 dma_write(l, LCH_CTRL(lch));
402         }
403 }
404 EXPORT_SYMBOL(omap_set_dma_channel_mode);
405
406 /* Note that src_port is only for omap1 */
407 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
408                              unsigned long src_start,
409                              int src_ei, int src_fi)
410 {
411         u32 l;
412
413         if (cpu_class_is_omap1()) {
414                 u16 w;
415
416                 w = dma_read(CSDP(lch));
417                 w &= ~(0x1f << 2);
418                 w |= src_port << 2;
419                 dma_write(w, CSDP(lch));
420         }
421
422         l = dma_read(CCR(lch));
423         l &= ~(0x03 << 12);
424         l |= src_amode << 12;
425         dma_write(l, CCR(lch));
426
427         if (cpu_class_is_omap1()) {
428                 dma_write(src_start >> 16, CSSA_U(lch));
429                 dma_write((u16)src_start, CSSA_L(lch));
430         }
431
432         if (cpu_class_is_omap2())
433                 dma_write(src_start, CSSA(lch));
434
435         dma_write(src_ei, CSEI(lch));
436         dma_write(src_fi, CSFI(lch));
437 }
438 EXPORT_SYMBOL(omap_set_dma_src_params);
439
440 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
441 {
442         omap_set_dma_transfer_params(lch, params->data_type,
443                                      params->elem_count, params->frame_count,
444                                      params->sync_mode, params->trigger,
445                                      params->src_or_dst_synch);
446         omap_set_dma_src_params(lch, params->src_port,
447                                 params->src_amode, params->src_start,
448                                 params->src_ei, params->src_fi);
449
450         omap_set_dma_dest_params(lch, params->dst_port,
451                                  params->dst_amode, params->dst_start,
452                                  params->dst_ei, params->dst_fi);
453         if (params->read_prio || params->write_prio)
454                 omap_dma_set_prio_lch(lch, params->read_prio,
455                                       params->write_prio);
456 }
457 EXPORT_SYMBOL(omap_set_dma_params);
458
459 void omap_set_dma_src_index(int lch, int eidx, int fidx)
460 {
461         if (cpu_class_is_omap2())
462                 return;
463
464         dma_write(eidx, CSEI(lch));
465         dma_write(fidx, CSFI(lch));
466 }
467 EXPORT_SYMBOL(omap_set_dma_src_index);
468
469 void omap_set_dma_src_data_pack(int lch, int enable)
470 {
471         u32 l;
472
473         l = dma_read(CSDP(lch));
474         l &= ~(1 << 6);
475         if (enable)
476                 l |= (1 << 6);
477         dma_write(l, CSDP(lch));
478 }
479 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
480
481 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
482 {
483         unsigned int burst = 0;
484         u32 l;
485
486         l = dma_read(CSDP(lch));
487         l &= ~(0x03 << 7);
488
489         switch (burst_mode) {
490         case OMAP_DMA_DATA_BURST_DIS:
491                 break;
492         case OMAP_DMA_DATA_BURST_4:
493                 if (cpu_class_is_omap2())
494                         burst = 0x1;
495                 else
496                         burst = 0x2;
497                 break;
498         case OMAP_DMA_DATA_BURST_8:
499                 if (cpu_class_is_omap2()) {
500                         burst = 0x2;
501                         break;
502                 }
503                 /* not supported by current hardware on OMAP1
504                  * w |= (0x03 << 7);
505                  * fall through
506                  */
507         case OMAP_DMA_DATA_BURST_16:
508                 if (cpu_class_is_omap2()) {
509                         burst = 0x3;
510                         break;
511                 }
512                 /* OMAP1 don't support burst 16
513                  * fall through
514                  */
515         default:
516                 BUG();
517         }
518
519         l |= (burst << 7);
520         dma_write(l, CSDP(lch));
521 }
522 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
523
524 /* Note that dest_port is only for OMAP1 */
525 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
526                               unsigned long dest_start,
527                               int dst_ei, int dst_fi)
528 {
529         u32 l;
530
531         if (cpu_class_is_omap1()) {
532                 l = dma_read(CSDP(lch));
533                 l &= ~(0x1f << 9);
534                 l |= dest_port << 9;
535                 dma_write(l, CSDP(lch));
536         }
537
538         l = dma_read(CCR(lch));
539         l &= ~(0x03 << 14);
540         l |= dest_amode << 14;
541         dma_write(l, CCR(lch));
542
543         if (cpu_class_is_omap1()) {
544                 dma_write(dest_start >> 16, CDSA_U(lch));
545                 dma_write(dest_start, CDSA_L(lch));
546         }
547
548         if (cpu_class_is_omap2())
549                 dma_write(dest_start, CDSA(lch));
550
551         dma_write(dst_ei, CDEI(lch));
552         dma_write(dst_fi, CDFI(lch));
553 }
554 EXPORT_SYMBOL(omap_set_dma_dest_params);
555
556 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
557 {
558         if (cpu_class_is_omap2())
559                 return;
560
561         dma_write(eidx, CDEI(lch));
562         dma_write(fidx, CDFI(lch));
563 }
564 EXPORT_SYMBOL(omap_set_dma_dest_index);
565
566 void omap_set_dma_dest_data_pack(int lch, int enable)
567 {
568         u32 l;
569
570         l = dma_read(CSDP(lch));
571         l &= ~(1 << 13);
572         if (enable)
573                 l |= 1 << 13;
574         dma_write(l, CSDP(lch));
575 }
576 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
577
578 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
579 {
580         unsigned int burst = 0;
581         u32 l;
582
583         l = dma_read(CSDP(lch));
584         l &= ~(0x03 << 14);
585
586         switch (burst_mode) {
587         case OMAP_DMA_DATA_BURST_DIS:
588                 break;
589         case OMAP_DMA_DATA_BURST_4:
590                 if (cpu_class_is_omap2())
591                         burst = 0x1;
592                 else
593                         burst = 0x2;
594                 break;
595         case OMAP_DMA_DATA_BURST_8:
596                 if (cpu_class_is_omap2())
597                         burst = 0x2;
598                 else
599                         burst = 0x3;
600                 break;
601         case OMAP_DMA_DATA_BURST_16:
602                 if (cpu_class_is_omap2()) {
603                         burst = 0x3;
604                         break;
605                 }
606                 /* OMAP1 don't support burst 16
607                  * fall through
608                  */
609         default:
610                 printk(KERN_ERR "Invalid DMA burst mode\n");
611                 BUG();
612                 return;
613         }
614         l |= (burst << 14);
615         dma_write(l, CSDP(lch));
616 }
617 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
618
619 static inline void omap_enable_channel_irq(int lch)
620 {
621         u32 status;
622
623         /* Clear CSR */
624         if (cpu_class_is_omap1())
625                 status = dma_read(CSR(lch));
626         else if (cpu_class_is_omap2())
627                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
628
629         /* Enable some nice interrupts. */
630         dma_write(dma_chan[lch].enabled_irqs, CICR(lch));
631 }
632
633 static void omap_disable_channel_irq(int lch)
634 {
635         if (cpu_class_is_omap2())
636                 dma_write(0, CICR(lch));
637 }
638
639 void omap_enable_dma_irq(int lch, u16 bits)
640 {
641         dma_chan[lch].enabled_irqs |= bits;
642 }
643 EXPORT_SYMBOL(omap_enable_dma_irq);
644
645 void omap_disable_dma_irq(int lch, u16 bits)
646 {
647         dma_chan[lch].enabled_irqs &= ~bits;
648 }
649 EXPORT_SYMBOL(omap_disable_dma_irq);
650
651 static inline void enable_lnk(int lch)
652 {
653         u32 l;
654
655         l = dma_read(CLNK_CTRL(lch));
656
657         if (cpu_class_is_omap1())
658                 l &= ~(1 << 14);
659
660         /* Set the ENABLE_LNK bits */
661         if (dma_chan[lch].next_lch != -1)
662                 l = dma_chan[lch].next_lch | (1 << 15);
663
664 #ifndef CONFIG_ARCH_OMAP1
665         if (cpu_class_is_omap2())
666                 if (dma_chan[lch].next_linked_ch != -1)
667                         l = dma_chan[lch].next_linked_ch | (1 << 15);
668 #endif
669
670         dma_write(l, CLNK_CTRL(lch));
671 }
672
673 static inline void disable_lnk(int lch)
674 {
675         u32 l;
676
677         l = dma_read(CLNK_CTRL(lch));
678
679         /* Disable interrupts */
680         if (cpu_class_is_omap1()) {
681                 dma_write(0, CICR(lch));
682                 /* Set the STOP_LNK bit */
683                 l |= 1 << 14;
684         }
685
686         if (cpu_class_is_omap2()) {
687                 omap_disable_channel_irq(lch);
688                 /* Clear the ENABLE_LNK bit */
689                 l &= ~(1 << 15);
690         }
691
692         dma_write(l, CLNK_CTRL(lch));
693         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
694 }
695
696 static inline void omap2_enable_irq_lch(int lch)
697 {
698         u32 val;
699         unsigned long flags;
700
701         if (!cpu_class_is_omap2())
702                 return;
703
704         spin_lock_irqsave(&dma_chan_lock, flags);
705         val = dma_read(IRQENABLE_L0);
706         val |= 1 << lch;
707         dma_write(val, IRQENABLE_L0);
708         spin_unlock_irqrestore(&dma_chan_lock, flags);
709 }
710
711 int omap_request_dma(int dev_id, const char *dev_name,
712                      void (*callback)(int lch, u16 ch_status, void *data),
713                      void *data, int *dma_ch_out)
714 {
715         int ch, free_ch = -1;
716         unsigned long flags;
717         struct omap_dma_lch *chan;
718
719         spin_lock_irqsave(&dma_chan_lock, flags);
720         for (ch = 0; ch < dma_chan_count; ch++) {
721                 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
722                         free_ch = ch;
723                         if (dev_id == 0)
724                                 break;
725                 }
726         }
727         if (free_ch == -1) {
728                 spin_unlock_irqrestore(&dma_chan_lock, flags);
729                 return -EBUSY;
730         }
731         chan = dma_chan + free_ch;
732         chan->dev_id = dev_id;
733
734         if (cpu_class_is_omap1())
735                 clear_lch_regs(free_ch);
736
737         if (cpu_class_is_omap2())
738                 omap_clear_dma(free_ch);
739
740         spin_unlock_irqrestore(&dma_chan_lock, flags);
741
742         chan->dev_name = dev_name;
743         chan->callback = callback;
744         chan->data = data;
745         chan->flags = 0;
746
747 #ifndef CONFIG_ARCH_OMAP1
748         if (cpu_class_is_omap2()) {
749                 chan->chain_id = -1;
750                 chan->next_linked_ch = -1;
751         }
752 #endif
753
754         chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
755
756         if (cpu_class_is_omap1())
757                 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
758         else if (cpu_class_is_omap2())
759                 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
760                         OMAP2_DMA_TRANS_ERR_IRQ;
761
762         if (cpu_is_omap16xx()) {
763                 /* If the sync device is set, configure it dynamically. */
764                 if (dev_id != 0) {
765                         set_gdma_dev(free_ch + 1, dev_id);
766                         dev_id = free_ch + 1;
767                 }
768                 /*
769                  * Disable the 1510 compatibility mode and set the sync device
770                  * id.
771                  */
772                 dma_write(dev_id | (1 << 10), CCR(free_ch));
773         } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
774                 dma_write(dev_id, CCR(free_ch));
775         }
776
777         if (cpu_class_is_omap2()) {
778                 omap2_enable_irq_lch(free_ch);
779                 omap_enable_channel_irq(free_ch);
780                 /* Clear the CSR register and IRQ status register */
781                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch));
782                 dma_write(1 << free_ch, IRQSTATUS_L0);
783         }
784
785         *dma_ch_out = free_ch;
786
787         return 0;
788 }
789 EXPORT_SYMBOL(omap_request_dma);
790
791 void omap_free_dma(int lch)
792 {
793         unsigned long flags;
794
795         if (dma_chan[lch].dev_id == -1) {
796                 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
797                        lch);
798                 return;
799         }
800
801         if (cpu_class_is_omap1()) {
802                 /* Disable all DMA interrupts for the channel. */
803                 dma_write(0, CICR(lch));
804                 /* Make sure the DMA transfer is stopped. */
805                 dma_write(0, CCR(lch));
806         }
807
808         if (cpu_class_is_omap2()) {
809                 u32 val;
810
811                 spin_lock_irqsave(&dma_chan_lock, flags);
812                 /* Disable interrupts */
813                 val = dma_read(IRQENABLE_L0);
814                 val &= ~(1 << lch);
815                 dma_write(val, IRQENABLE_L0);
816                 spin_unlock_irqrestore(&dma_chan_lock, flags);
817
818                 /* Clear the CSR register and IRQ status register */
819                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
820                 dma_write(1 << lch, IRQSTATUS_L0);
821
822                 /* Disable all DMA interrupts for the channel. */
823                 dma_write(0, CICR(lch));
824
825                 /* Make sure the DMA transfer is stopped. */
826                 dma_write(0, CCR(lch));
827                 omap_clear_dma(lch);
828         }
829
830         spin_lock_irqsave(&dma_chan_lock, flags);
831         dma_chan[lch].dev_id = -1;
832         dma_chan[lch].next_lch = -1;
833         dma_chan[lch].callback = NULL;
834         spin_unlock_irqrestore(&dma_chan_lock, flags);
835 }
836 EXPORT_SYMBOL(omap_free_dma);
837
838 /**
839  * @brief omap_dma_set_global_params : Set global priority settings for dma
840  *
841  * @param arb_rate
842  * @param max_fifo_depth
843  * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
844  *                                                 DMA_THREAD_RESERVE_ONET
845  *                                                 DMA_THREAD_RESERVE_TWOT
846  *                                                 DMA_THREAD_RESERVE_THREET
847  */
848 void
849 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
850 {
851         u32 reg;
852
853         if (!cpu_class_is_omap2()) {
854                 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
855                 return;
856         }
857
858         if (max_fifo_depth == 0)
859                 max_fifo_depth = 1;
860         if (arb_rate == 0)
861                 arb_rate = 1;
862
863         reg = 0xff & max_fifo_depth;
864         reg |= (0x3 & tparams) << 12;
865         reg |= (arb_rate & 0xff) << 16;
866
867         dma_write(reg, GCR);
868 }
869 EXPORT_SYMBOL(omap_dma_set_global_params);
870
871 /**
872  * @brief omap_dma_set_prio_lch : Set channel wise priority settings
873  *
874  * @param lch
875  * @param read_prio - Read priority
876  * @param write_prio - Write priority
877  * Both of the above can be set with one of the following values :
878  *      DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
879  */
880 int
881 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
882                       unsigned char write_prio)
883 {
884         u32 l;
885
886         if (unlikely((lch < 0 || lch >= dma_lch_count))) {
887                 printk(KERN_ERR "Invalid channel id\n");
888                 return -EINVAL;
889         }
890         l = dma_read(CCR(lch));
891         l &= ~((1 << 6) | (1 << 26));
892         if (cpu_is_omap2430() || cpu_is_omap34xx() ||  cpu_is_omap44xx())
893                 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
894         else
895                 l |= ((read_prio & 0x1) << 6);
896
897         dma_write(l, CCR(lch));
898
899         return 0;
900 }
901 EXPORT_SYMBOL(omap_dma_set_prio_lch);
902
903 /*
904  * Clears any DMA state so the DMA engine is ready to restart with new buffers
905  * through omap_start_dma(). Any buffers in flight are discarded.
906  */
907 void omap_clear_dma(int lch)
908 {
909         unsigned long flags;
910
911         local_irq_save(flags);
912
913         if (cpu_class_is_omap1()) {
914                 u32 l;
915
916                 l = dma_read(CCR(lch));
917                 l &= ~OMAP_DMA_CCR_EN;
918                 dma_write(l, CCR(lch));
919
920                 /* Clear pending interrupts */
921                 l = dma_read(CSR(lch));
922         }
923
924         if (cpu_class_is_omap2()) {
925                 int i;
926                 void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch);
927                 for (i = 0; i < 0x44; i += 4)
928                         __raw_writel(0, lch_base + i);
929         }
930
931         local_irq_restore(flags);
932 }
933 EXPORT_SYMBOL(omap_clear_dma);
934
935 void omap_start_dma(int lch)
936 {
937         u32 l;
938
939         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
940                 int next_lch, cur_lch;
941                 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
942
943                 dma_chan_link_map[lch] = 1;
944                 /* Set the link register of the first channel */
945                 enable_lnk(lch);
946
947                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
948                 cur_lch = dma_chan[lch].next_lch;
949                 do {
950                         next_lch = dma_chan[cur_lch].next_lch;
951
952                         /* The loop case: we've been here already */
953                         if (dma_chan_link_map[cur_lch])
954                                 break;
955                         /* Mark the current channel */
956                         dma_chan_link_map[cur_lch] = 1;
957
958                         enable_lnk(cur_lch);
959                         omap_enable_channel_irq(cur_lch);
960
961                         cur_lch = next_lch;
962                 } while (next_lch != -1);
963         } else if (cpu_is_omap242x() ||
964                 (cpu_is_omap243x() &&  omap_type() <= OMAP2430_REV_ES1_0)) {
965
966                 /* Errata: Need to write lch even if not using chaining */
967                 dma_write(lch, CLNK_CTRL(lch));
968         }
969
970         omap_enable_channel_irq(lch);
971
972         l = dma_read(CCR(lch));
973
974         /*
975          * Errata: On ES2.0 BUFFERING disable must be set.
976          * This will always fail on ES1.0
977          */
978         if (cpu_is_omap24xx())
979                 l |= OMAP_DMA_CCR_EN;
980
981         l |= OMAP_DMA_CCR_EN;
982         dma_write(l, CCR(lch));
983
984         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
985 }
986 EXPORT_SYMBOL(omap_start_dma);
987
988 void omap_stop_dma(int lch)
989 {
990         u32 l;
991
992         /* Disable all interrupts on the channel */
993         if (cpu_class_is_omap1())
994                 dma_write(0, CICR(lch));
995
996         l = dma_read(CCR(lch));
997         l &= ~OMAP_DMA_CCR_EN;
998         dma_write(l, CCR(lch));
999
1000         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
1001                 int next_lch, cur_lch = lch;
1002                 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
1003
1004                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
1005                 do {
1006                         /* The loop case: we've been here already */
1007                         if (dma_chan_link_map[cur_lch])
1008                                 break;
1009                         /* Mark the current channel */
1010                         dma_chan_link_map[cur_lch] = 1;
1011
1012                         disable_lnk(cur_lch);
1013
1014                         next_lch = dma_chan[cur_lch].next_lch;
1015                         cur_lch = next_lch;
1016                 } while (next_lch != -1);
1017         }
1018
1019         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
1020 }
1021 EXPORT_SYMBOL(omap_stop_dma);
1022
1023 /*
1024  * Allows changing the DMA callback function or data. This may be needed if
1025  * the driver shares a single DMA channel for multiple dma triggers.
1026  */
1027 int omap_set_dma_callback(int lch,
1028                           void (*callback)(int lch, u16 ch_status, void *data),
1029                           void *data)
1030 {
1031         unsigned long flags;
1032
1033         if (lch < 0)
1034                 return -ENODEV;
1035
1036         spin_lock_irqsave(&dma_chan_lock, flags);
1037         if (dma_chan[lch].dev_id == -1) {
1038                 printk(KERN_ERR "DMA callback for not set for free channel\n");
1039                 spin_unlock_irqrestore(&dma_chan_lock, flags);
1040                 return -EINVAL;
1041         }
1042         dma_chan[lch].callback = callback;
1043         dma_chan[lch].data = data;
1044         spin_unlock_irqrestore(&dma_chan_lock, flags);
1045
1046         return 0;
1047 }
1048 EXPORT_SYMBOL(omap_set_dma_callback);
1049
1050 /*
1051  * Returns current physical source address for the given DMA channel.
1052  * If the channel is running the caller must disable interrupts prior calling
1053  * this function and process the returned value before re-enabling interrupt to
1054  * prevent races with the interrupt handler. Note that in continuous mode there
1055  * is a chance for CSSA_L register overflow inbetween the two reads resulting
1056  * in incorrect return value.
1057  */
1058 dma_addr_t omap_get_dma_src_pos(int lch)
1059 {
1060         dma_addr_t offset = 0;
1061
1062         if (cpu_is_omap15xx())
1063                 offset = dma_read(CPC(lch));
1064         else
1065                 offset = dma_read(CSAC(lch));
1066
1067         /*
1068          * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1069          * read before the DMA controller finished disabling the channel.
1070          */
1071         if (!cpu_is_omap15xx() && offset == 0)
1072                 offset = dma_read(CSAC(lch));
1073
1074         if (cpu_class_is_omap1())
1075                 offset |= (dma_read(CSSA_U(lch)) << 16);
1076
1077         return offset;
1078 }
1079 EXPORT_SYMBOL(omap_get_dma_src_pos);
1080
1081 /*
1082  * Returns current physical destination address for the given DMA channel.
1083  * If the channel is running the caller must disable interrupts prior calling
1084  * this function and process the returned value before re-enabling interrupt to
1085  * prevent races with the interrupt handler. Note that in continuous mode there
1086  * is a chance for CDSA_L register overflow inbetween the two reads resulting
1087  * in incorrect return value.
1088  */
1089 dma_addr_t omap_get_dma_dst_pos(int lch)
1090 {
1091         dma_addr_t offset = 0;
1092
1093         if (cpu_is_omap15xx())
1094                 offset = dma_read(CPC(lch));
1095         else
1096                 offset = dma_read(CDAC(lch));
1097
1098         /*
1099          * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1100          * read before the DMA controller finished disabling the channel.
1101          */
1102         if (!cpu_is_omap15xx() && offset == 0)
1103                 offset = dma_read(CDAC(lch));
1104
1105         if (cpu_class_is_omap1())
1106                 offset |= (dma_read(CDSA_U(lch)) << 16);
1107
1108         return offset;
1109 }
1110 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1111
1112 int omap_get_dma_active_status(int lch)
1113 {
1114         return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0;
1115 }
1116 EXPORT_SYMBOL(omap_get_dma_active_status);
1117
1118 int omap_dma_running(void)
1119 {
1120         int lch;
1121
1122         if (cpu_class_is_omap1())
1123                 if (omap_lcd_dma_running())
1124                         return 1;
1125
1126         for (lch = 0; lch < dma_chan_count; lch++)
1127                 if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN)
1128                         return 1;
1129
1130         return 0;
1131 }
1132
1133 /*
1134  * lch_queue DMA will start right after lch_head one is finished.
1135  * For this DMA link to start, you still need to start (see omap_start_dma)
1136  * the first one. That will fire up the entire queue.
1137  */
1138 void omap_dma_link_lch(int lch_head, int lch_queue)
1139 {
1140         if (omap_dma_in_1510_mode()) {
1141                 if (lch_head == lch_queue) {
1142                         dma_write(dma_read(CCR(lch_head)) | (3 << 8),
1143                                                                 CCR(lch_head));
1144                         return;
1145                 }
1146                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1147                 BUG();
1148                 return;
1149         }
1150
1151         if ((dma_chan[lch_head].dev_id == -1) ||
1152             (dma_chan[lch_queue].dev_id == -1)) {
1153                 printk(KERN_ERR "omap_dma: trying to link "
1154                        "non requested channels\n");
1155                 dump_stack();
1156         }
1157
1158         dma_chan[lch_head].next_lch = lch_queue;
1159 }
1160 EXPORT_SYMBOL(omap_dma_link_lch);
1161
1162 /*
1163  * Once the DMA queue is stopped, we can destroy it.
1164  */
1165 void omap_dma_unlink_lch(int lch_head, int lch_queue)
1166 {
1167         if (omap_dma_in_1510_mode()) {
1168                 if (lch_head == lch_queue) {
1169                         dma_write(dma_read(CCR(lch_head)) & ~(3 << 8),
1170                                                                 CCR(lch_head));
1171                         return;
1172                 }
1173                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1174                 BUG();
1175                 return;
1176         }
1177
1178         if (dma_chan[lch_head].next_lch != lch_queue ||
1179             dma_chan[lch_head].next_lch == -1) {
1180                 printk(KERN_ERR "omap_dma: trying to unlink "
1181                        "non linked channels\n");
1182                 dump_stack();
1183         }
1184
1185         if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1186             (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
1187                 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1188                        "before unlinking\n");
1189                 dump_stack();
1190         }
1191
1192         dma_chan[lch_head].next_lch = -1;
1193 }
1194 EXPORT_SYMBOL(omap_dma_unlink_lch);
1195
1196 /*----------------------------------------------------------------------------*/
1197
1198 #ifndef CONFIG_ARCH_OMAP1
1199 /* Create chain of DMA channesls */
1200 static void create_dma_lch_chain(int lch_head, int lch_queue)
1201 {
1202         u32 l;
1203
1204         /* Check if this is the first link in chain */
1205         if (dma_chan[lch_head].next_linked_ch == -1) {
1206                 dma_chan[lch_head].next_linked_ch = lch_queue;
1207                 dma_chan[lch_head].prev_linked_ch = lch_queue;
1208                 dma_chan[lch_queue].next_linked_ch = lch_head;
1209                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1210         }
1211
1212         /* a link exists, link the new channel in circular chain */
1213         else {
1214                 dma_chan[lch_queue].next_linked_ch =
1215                                         dma_chan[lch_head].next_linked_ch;
1216                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1217                 dma_chan[lch_head].next_linked_ch = lch_queue;
1218                 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1219                                         lch_queue;
1220         }
1221
1222         l = dma_read(CLNK_CTRL(lch_head));
1223         l &= ~(0x1f);
1224         l |= lch_queue;
1225         dma_write(l, CLNK_CTRL(lch_head));
1226
1227         l = dma_read(CLNK_CTRL(lch_queue));
1228         l &= ~(0x1f);
1229         l |= (dma_chan[lch_queue].next_linked_ch);
1230         dma_write(l, CLNK_CTRL(lch_queue));
1231 }
1232
1233 /**
1234  * @brief omap_request_dma_chain : Request a chain of DMA channels
1235  *
1236  * @param dev_id - Device id using the dma channel
1237  * @param dev_name - Device name
1238  * @param callback - Call back function
1239  * @chain_id -
1240  * @no_of_chans - Number of channels requested
1241  * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1242  *                                            OMAP_DMA_DYNAMIC_CHAIN
1243  * @params - Channel parameters
1244  *
1245  * @return - Success : 0
1246  *           Failure: -EINVAL/-ENOMEM
1247  */
1248 int omap_request_dma_chain(int dev_id, const char *dev_name,
1249                            void (*callback) (int lch, u16 ch_status,
1250                                              void *data),
1251                            int *chain_id, int no_of_chans, int chain_mode,
1252                            struct omap_dma_channel_params params)
1253 {
1254         int *channels;
1255         int i, err;
1256
1257         /* Is the chain mode valid ? */
1258         if (chain_mode != OMAP_DMA_STATIC_CHAIN
1259                         && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1260                 printk(KERN_ERR "Invalid chain mode requested\n");
1261                 return -EINVAL;
1262         }
1263
1264         if (unlikely((no_of_chans < 1
1265                         || no_of_chans > dma_lch_count))) {
1266                 printk(KERN_ERR "Invalid Number of channels requested\n");
1267                 return -EINVAL;
1268         }
1269
1270         /* Allocate a queue to maintain the status of the channels
1271          * in the chain */
1272         channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1273         if (channels == NULL) {
1274                 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1275                 return -ENOMEM;
1276         }
1277
1278         /* request and reserve DMA channels for the chain */
1279         for (i = 0; i < no_of_chans; i++) {
1280                 err = omap_request_dma(dev_id, dev_name,
1281                                         callback, NULL, &channels[i]);
1282                 if (err < 0) {
1283                         int j;
1284                         for (j = 0; j < i; j++)
1285                                 omap_free_dma(channels[j]);
1286                         kfree(channels);
1287                         printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1288                         return err;
1289                 }
1290                 dma_chan[channels[i]].prev_linked_ch = -1;
1291                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1292
1293                 /*
1294                  * Allowing client drivers to set common parameters now,
1295                  * so that later only relevant (src_start, dest_start
1296                  * and element count) can be set
1297                  */
1298                 omap_set_dma_params(channels[i], &params);
1299         }
1300
1301         *chain_id = channels[0];
1302         dma_linked_lch[*chain_id].linked_dmach_q = channels;
1303         dma_linked_lch[*chain_id].chain_mode = chain_mode;
1304         dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1305         dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1306
1307         for (i = 0; i < no_of_chans; i++)
1308                 dma_chan[channels[i]].chain_id = *chain_id;
1309
1310         /* Reset the Queue pointers */
1311         OMAP_DMA_CHAIN_QINIT(*chain_id);
1312
1313         /* Set up the chain */
1314         if (no_of_chans == 1)
1315                 create_dma_lch_chain(channels[0], channels[0]);
1316         else {
1317                 for (i = 0; i < (no_of_chans - 1); i++)
1318                         create_dma_lch_chain(channels[i], channels[i + 1]);
1319         }
1320
1321         return 0;
1322 }
1323 EXPORT_SYMBOL(omap_request_dma_chain);
1324
1325 /**
1326  * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1327  * params after setting it. Dont do this while dma is running!!
1328  *
1329  * @param chain_id - Chained logical channel id.
1330  * @param params
1331  *
1332  * @return - Success : 0
1333  *           Failure : -EINVAL
1334  */
1335 int omap_modify_dma_chain_params(int chain_id,
1336                                 struct omap_dma_channel_params params)
1337 {
1338         int *channels;
1339         u32 i;
1340
1341         /* Check for input params */
1342         if (unlikely((chain_id < 0
1343                         || chain_id >= dma_lch_count))) {
1344                 printk(KERN_ERR "Invalid chain id\n");
1345                 return -EINVAL;
1346         }
1347
1348         /* Check if the chain exists */
1349         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1350                 printk(KERN_ERR "Chain doesn't exists\n");
1351                 return -EINVAL;
1352         }
1353         channels = dma_linked_lch[chain_id].linked_dmach_q;
1354
1355         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1356                 /*
1357                  * Allowing client drivers to set common parameters now,
1358                  * so that later only relevant (src_start, dest_start
1359                  * and element count) can be set
1360                  */
1361                 omap_set_dma_params(channels[i], &params);
1362         }
1363
1364         return 0;
1365 }
1366 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1367
1368 /**
1369  * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1370  *
1371  * @param chain_id
1372  *
1373  * @return - Success : 0
1374  *           Failure : -EINVAL
1375  */
1376 int omap_free_dma_chain(int chain_id)
1377 {
1378         int *channels;
1379         u32 i;
1380
1381         /* Check for input params */
1382         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1383                 printk(KERN_ERR "Invalid chain id\n");
1384                 return -EINVAL;
1385         }
1386
1387         /* Check if the chain exists */
1388         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1389                 printk(KERN_ERR "Chain doesn't exists\n");
1390                 return -EINVAL;
1391         }
1392
1393         channels = dma_linked_lch[chain_id].linked_dmach_q;
1394         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1395                 dma_chan[channels[i]].next_linked_ch = -1;
1396                 dma_chan[channels[i]].prev_linked_ch = -1;
1397                 dma_chan[channels[i]].chain_id = -1;
1398                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1399                 omap_free_dma(channels[i]);
1400         }
1401
1402         kfree(channels);
1403
1404         dma_linked_lch[chain_id].linked_dmach_q = NULL;
1405         dma_linked_lch[chain_id].chain_mode = -1;
1406         dma_linked_lch[chain_id].chain_state = -1;
1407
1408         return (0);
1409 }
1410 EXPORT_SYMBOL(omap_free_dma_chain);
1411
1412 /**
1413  * @brief omap_dma_chain_status - Check if the chain is in
1414  * active / inactive state.
1415  * @param chain_id
1416  *
1417  * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1418  *           Failure : -EINVAL
1419  */
1420 int omap_dma_chain_status(int chain_id)
1421 {
1422         /* Check for input params */
1423         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1424                 printk(KERN_ERR "Invalid chain id\n");
1425                 return -EINVAL;
1426         }
1427
1428         /* Check if the chain exists */
1429         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1430                 printk(KERN_ERR "Chain doesn't exists\n");
1431                 return -EINVAL;
1432         }
1433         pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1434                         dma_linked_lch[chain_id].q_count);
1435
1436         if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1437                 return OMAP_DMA_CHAIN_INACTIVE;
1438
1439         return OMAP_DMA_CHAIN_ACTIVE;
1440 }
1441 EXPORT_SYMBOL(omap_dma_chain_status);
1442
1443 /**
1444  * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1445  * set the params and start the transfer.
1446  *
1447  * @param chain_id
1448  * @param src_start - buffer start address
1449  * @param dest_start - Dest address
1450  * @param elem_count
1451  * @param frame_count
1452  * @param callbk_data - channel callback parameter data.
1453  *
1454  * @return  - Success : 0
1455  *            Failure: -EINVAL/-EBUSY
1456  */
1457 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1458                         int elem_count, int frame_count, void *callbk_data)
1459 {
1460         int *channels;
1461         u32 l, lch;
1462         int start_dma = 0;
1463
1464         /*
1465          * if buffer size is less than 1 then there is
1466          * no use of starting the chain
1467          */
1468         if (elem_count < 1) {
1469                 printk(KERN_ERR "Invalid buffer size\n");
1470                 return -EINVAL;
1471         }
1472
1473         /* Check for input params */
1474         if (unlikely((chain_id < 0
1475                         || chain_id >= dma_lch_count))) {
1476                 printk(KERN_ERR "Invalid chain id\n");
1477                 return -EINVAL;
1478         }
1479
1480         /* Check if the chain exists */
1481         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1482                 printk(KERN_ERR "Chain doesn't exist\n");
1483                 return -EINVAL;
1484         }
1485
1486         /* Check if all the channels in chain are in use */
1487         if (OMAP_DMA_CHAIN_QFULL(chain_id))
1488                 return -EBUSY;
1489
1490         /* Frame count may be negative in case of indexed transfers */
1491         channels = dma_linked_lch[chain_id].linked_dmach_q;
1492
1493         /* Get a free channel */
1494         lch = channels[dma_linked_lch[chain_id].q_tail];
1495
1496         /* Store the callback data */
1497         dma_chan[lch].data = callbk_data;
1498
1499         /* Increment the q_tail */
1500         OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1501
1502         /* Set the params to the free channel */
1503         if (src_start != 0)
1504                 dma_write(src_start, CSSA(lch));
1505         if (dest_start != 0)
1506                 dma_write(dest_start, CDSA(lch));
1507
1508         /* Write the buffer size */
1509         dma_write(elem_count, CEN(lch));
1510         dma_write(frame_count, CFN(lch));
1511
1512         /*
1513          * If the chain is dynamically linked,
1514          * then we may have to start the chain if its not active
1515          */
1516         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1517
1518                 /*
1519                  * In Dynamic chain, if the chain is not started,
1520                  * queue the channel
1521                  */
1522                 if (dma_linked_lch[chain_id].chain_state ==
1523                                                 DMA_CHAIN_NOTSTARTED) {
1524                         /* Enable the link in previous channel */
1525                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1526                                                                 DMA_CH_QUEUED)
1527                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1528                         dma_chan[lch].state = DMA_CH_QUEUED;
1529                 }
1530
1531                 /*
1532                  * Chain is already started, make sure its active,
1533                  * if not then start the chain
1534                  */
1535                 else {
1536                         start_dma = 1;
1537
1538                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1539                                                         DMA_CH_STARTED) {
1540                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1541                                 dma_chan[lch].state = DMA_CH_QUEUED;
1542                                 start_dma = 0;
1543                                 if (0 == ((1 << 7) & dma_read(
1544                                         CCR(dma_chan[lch].prev_linked_ch)))) {
1545                                         disable_lnk(dma_chan[lch].
1546                                                     prev_linked_ch);
1547                                         pr_debug("\n prev ch is stopped\n");
1548                                         start_dma = 1;
1549                                 }
1550                         }
1551
1552                         else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1553                                                         == DMA_CH_QUEUED) {
1554                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1555                                 dma_chan[lch].state = DMA_CH_QUEUED;
1556                                 start_dma = 0;
1557                         }
1558                         omap_enable_channel_irq(lch);
1559
1560                         l = dma_read(CCR(lch));
1561
1562                         if ((0 == (l & (1 << 24))))
1563                                 l &= ~(1 << 25);
1564                         else
1565                                 l |= (1 << 25);
1566                         if (start_dma == 1) {
1567                                 if (0 == (l & (1 << 7))) {
1568                                         l |= (1 << 7);
1569                                         dma_chan[lch].state = DMA_CH_STARTED;
1570                                         pr_debug("starting %d\n", lch);
1571                                         dma_write(l, CCR(lch));
1572                                 } else
1573                                         start_dma = 0;
1574                         } else {
1575                                 if (0 == (l & (1 << 7)))
1576                                         dma_write(l, CCR(lch));
1577                         }
1578                         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1579                 }
1580         }
1581
1582         return 0;
1583 }
1584 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1585
1586 /**
1587  * @brief omap_start_dma_chain_transfers - Start the chain
1588  *
1589  * @param chain_id
1590  *
1591  * @return - Success : 0
1592  *           Failure : -EINVAL/-EBUSY
1593  */
1594 int omap_start_dma_chain_transfers(int chain_id)
1595 {
1596         int *channels;
1597         u32 l, i;
1598
1599         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1600                 printk(KERN_ERR "Invalid chain id\n");
1601                 return -EINVAL;
1602         }
1603
1604         channels = dma_linked_lch[chain_id].linked_dmach_q;
1605
1606         if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1607                 printk(KERN_ERR "Chain is already started\n");
1608                 return -EBUSY;
1609         }
1610
1611         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1612                 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1613                                                                         i++) {
1614                         enable_lnk(channels[i]);
1615                         omap_enable_channel_irq(channels[i]);
1616                 }
1617         } else {
1618                 omap_enable_channel_irq(channels[0]);
1619         }
1620
1621         l = dma_read(CCR(channels[0]));
1622         l |= (1 << 7);
1623         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1624         dma_chan[channels[0]].state = DMA_CH_STARTED;
1625
1626         if ((0 == (l & (1 << 24))))
1627                 l &= ~(1 << 25);
1628         else
1629                 l |= (1 << 25);
1630         dma_write(l, CCR(channels[0]));
1631
1632         dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1633
1634         return 0;
1635 }
1636 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1637
1638 /**
1639  * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1640  *
1641  * @param chain_id
1642  *
1643  * @return - Success : 0
1644  *           Failure : EINVAL
1645  */
1646 int omap_stop_dma_chain_transfers(int chain_id)
1647 {
1648         int *channels;
1649         u32 l, i;
1650         u32 sys_cf;
1651
1652         /* Check for input params */
1653         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1654                 printk(KERN_ERR "Invalid chain id\n");
1655                 return -EINVAL;
1656         }
1657
1658         /* Check if the chain exists */
1659         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1660                 printk(KERN_ERR "Chain doesn't exists\n");
1661                 return -EINVAL;
1662         }
1663         channels = dma_linked_lch[chain_id].linked_dmach_q;
1664
1665         /*
1666          * DMA Errata:
1667          * Special programming model needed to disable DMA before end of block
1668          */
1669         sys_cf = dma_read(OCP_SYSCONFIG);
1670         l = sys_cf;
1671         /* Middle mode reg set no Standby */
1672         l &= ~((1 << 12)|(1 << 13));
1673         dma_write(l, OCP_SYSCONFIG);
1674
1675         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1676
1677                 /* Stop the Channel transmission */
1678                 l = dma_read(CCR(channels[i]));
1679                 l &= ~(1 << 7);
1680                 dma_write(l, CCR(channels[i]));
1681
1682                 /* Disable the link in all the channels */
1683                 disable_lnk(channels[i]);
1684                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1685
1686         }
1687         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1688
1689         /* Reset the Queue pointers */
1690         OMAP_DMA_CHAIN_QINIT(chain_id);
1691
1692         /* Errata - put in the old value */
1693         dma_write(sys_cf, OCP_SYSCONFIG);
1694
1695         return 0;
1696 }
1697 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1698
1699 /* Get the index of the ongoing DMA in chain */
1700 /**
1701  * @brief omap_get_dma_chain_index - Get the element and frame index
1702  * of the ongoing DMA in chain
1703  *
1704  * @param chain_id
1705  * @param ei - Element index
1706  * @param fi - Frame index
1707  *
1708  * @return - Success : 0
1709  *           Failure : -EINVAL
1710  */
1711 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1712 {
1713         int lch;
1714         int *channels;
1715
1716         /* Check for input params */
1717         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1718                 printk(KERN_ERR "Invalid chain id\n");
1719                 return -EINVAL;
1720         }
1721
1722         /* Check if the chain exists */
1723         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1724                 printk(KERN_ERR "Chain doesn't exists\n");
1725                 return -EINVAL;
1726         }
1727         if ((!ei) || (!fi))
1728                 return -EINVAL;
1729
1730         channels = dma_linked_lch[chain_id].linked_dmach_q;
1731
1732         /* Get the current channel */
1733         lch = channels[dma_linked_lch[chain_id].q_head];
1734
1735         *ei = dma_read(CCEN(lch));
1736         *fi = dma_read(CCFN(lch));
1737
1738         return 0;
1739 }
1740 EXPORT_SYMBOL(omap_get_dma_chain_index);
1741
1742 /**
1743  * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1744  * ongoing DMA in chain
1745  *
1746  * @param chain_id
1747  *
1748  * @return - Success : Destination position
1749  *           Failure : -EINVAL
1750  */
1751 int omap_get_dma_chain_dst_pos(int chain_id)
1752 {
1753         int lch;
1754         int *channels;
1755
1756         /* Check for input params */
1757         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1758                 printk(KERN_ERR "Invalid chain id\n");
1759                 return -EINVAL;
1760         }
1761
1762         /* Check if the chain exists */
1763         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1764                 printk(KERN_ERR "Chain doesn't exists\n");
1765                 return -EINVAL;
1766         }
1767
1768         channels = dma_linked_lch[chain_id].linked_dmach_q;
1769
1770         /* Get the current channel */
1771         lch = channels[dma_linked_lch[chain_id].q_head];
1772
1773         return dma_read(CDAC(lch));
1774 }
1775 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1776
1777 /**
1778  * @brief omap_get_dma_chain_src_pos - Get the source position
1779  * of the ongoing DMA in chain
1780  * @param chain_id
1781  *
1782  * @return - Success : Destination position
1783  *           Failure : -EINVAL
1784  */
1785 int omap_get_dma_chain_src_pos(int chain_id)
1786 {
1787         int lch;
1788         int *channels;
1789
1790         /* Check for input params */
1791         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1792                 printk(KERN_ERR "Invalid chain id\n");
1793                 return -EINVAL;
1794         }
1795
1796         /* Check if the chain exists */
1797         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1798                 printk(KERN_ERR "Chain doesn't exists\n");
1799                 return -EINVAL;
1800         }
1801
1802         channels = dma_linked_lch[chain_id].linked_dmach_q;
1803
1804         /* Get the current channel */
1805         lch = channels[dma_linked_lch[chain_id].q_head];
1806
1807         return dma_read(CSAC(lch));
1808 }
1809 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1810 #endif  /* ifndef CONFIG_ARCH_OMAP1 */
1811
1812 /*----------------------------------------------------------------------------*/
1813
1814 #ifdef CONFIG_ARCH_OMAP1
1815
1816 static int omap1_dma_handle_ch(int ch)
1817 {
1818         u32 csr;
1819
1820         if (enable_1510_mode && ch >= 6) {
1821                 csr = dma_chan[ch].saved_csr;
1822                 dma_chan[ch].saved_csr = 0;
1823         } else
1824                 csr = dma_read(CSR(ch));
1825         if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1826                 dma_chan[ch + 6].saved_csr = csr >> 7;
1827                 csr &= 0x7f;
1828         }
1829         if ((csr & 0x3f) == 0)
1830                 return 0;
1831         if (unlikely(dma_chan[ch].dev_id == -1)) {
1832                 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1833                        "%d (CSR %04x)\n", ch, csr);
1834                 return 0;
1835         }
1836         if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1837                 printk(KERN_WARNING "DMA timeout with device %d\n",
1838                        dma_chan[ch].dev_id);
1839         if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1840                 printk(KERN_WARNING "DMA synchronization event drop occurred "
1841                        "with device %d\n", dma_chan[ch].dev_id);
1842         if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1843                 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1844         if (likely(dma_chan[ch].callback != NULL))
1845                 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1846
1847         return 1;
1848 }
1849
1850 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1851 {
1852         int ch = ((int) dev_id) - 1;
1853         int handled = 0;
1854
1855         for (;;) {
1856                 int handled_now = 0;
1857
1858                 handled_now += omap1_dma_handle_ch(ch);
1859                 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1860                         handled_now += omap1_dma_handle_ch(ch + 6);
1861                 if (!handled_now)
1862                         break;
1863                 handled += handled_now;
1864         }
1865
1866         return handled ? IRQ_HANDLED : IRQ_NONE;
1867 }
1868
1869 #else
1870 #define omap1_dma_irq_handler   NULL
1871 #endif
1872
1873 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
1874                         defined(CONFIG_ARCH_OMAP4)
1875
1876 static int omap2_dma_handle_ch(int ch)
1877 {
1878         u32 status = dma_read(CSR(ch));
1879
1880         if (!status) {
1881                 if (printk_ratelimit())
1882                         printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1883                                 ch);
1884                 dma_write(1 << ch, IRQSTATUS_L0);
1885                 return 0;
1886         }
1887         if (unlikely(dma_chan[ch].dev_id == -1)) {
1888                 if (printk_ratelimit())
1889                         printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1890                                         "channel %d\n", status, ch);
1891                 return 0;
1892         }
1893         if (unlikely(status & OMAP_DMA_DROP_IRQ))
1894                 printk(KERN_INFO
1895                        "DMA synchronization event drop occurred with device "
1896                        "%d\n", dma_chan[ch].dev_id);
1897         if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1898                 printk(KERN_INFO "DMA transaction error with device %d\n",
1899                        dma_chan[ch].dev_id);
1900                 if (cpu_class_is_omap2()) {
1901                         /* Errata: sDMA Channel is not disabled
1902                          * after a transaction error. So we explicitely
1903                          * disable the channel
1904                          */
1905                         u32 ccr;
1906
1907                         ccr = dma_read(CCR(ch));
1908                         ccr &= ~OMAP_DMA_CCR_EN;
1909                         dma_write(ccr, CCR(ch));
1910                         dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1911                 }
1912         }
1913         if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1914                 printk(KERN_INFO "DMA secure error with device %d\n",
1915                        dma_chan[ch].dev_id);
1916         if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1917                 printk(KERN_INFO "DMA misaligned error with device %d\n",
1918                        dma_chan[ch].dev_id);
1919
1920         dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch));
1921         dma_write(1 << ch, IRQSTATUS_L0);
1922
1923         /* If the ch is not chained then chain_id will be -1 */
1924         if (dma_chan[ch].chain_id != -1) {
1925                 int chain_id = dma_chan[ch].chain_id;
1926                 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1927                 if (dma_read(CLNK_CTRL(ch)) & (1 << 15))
1928                         dma_chan[dma_chan[ch].next_linked_ch].state =
1929                                                         DMA_CH_STARTED;
1930                 if (dma_linked_lch[chain_id].chain_mode ==
1931                                                 OMAP_DMA_DYNAMIC_CHAIN)
1932                         disable_lnk(ch);
1933
1934                 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1935                         OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1936
1937                 status = dma_read(CSR(ch));
1938         }
1939
1940         dma_write(status, CSR(ch));
1941
1942         if (likely(dma_chan[ch].callback != NULL))
1943                 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1944
1945         return 0;
1946 }
1947
1948 /* STATUS register count is from 1-32 while our is 0-31 */
1949 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1950 {
1951         u32 val, enable_reg;
1952         int i;
1953
1954         val = dma_read(IRQSTATUS_L0);
1955         if (val == 0) {
1956                 if (printk_ratelimit())
1957                         printk(KERN_WARNING "Spurious DMA IRQ\n");
1958                 return IRQ_HANDLED;
1959         }
1960         enable_reg = dma_read(IRQENABLE_L0);
1961         val &= enable_reg; /* Dispatch only relevant interrupts */
1962         for (i = 0; i < dma_lch_count && val != 0; i++) {
1963                 if (val & 1)
1964                         omap2_dma_handle_ch(i);
1965                 val >>= 1;
1966         }
1967
1968         return IRQ_HANDLED;
1969 }
1970
1971 static struct irqaction omap24xx_dma_irq = {
1972         .name = "DMA",
1973         .handler = omap2_dma_irq_handler,
1974         .flags = IRQF_DISABLED
1975 };
1976
1977 #else
1978 static struct irqaction omap24xx_dma_irq;
1979 #endif
1980
1981 /*----------------------------------------------------------------------------*/
1982
1983 void omap_dma_global_context_save(void)
1984 {
1985         omap_dma_global_context.dma_irqenable_l0 =
1986                 dma_read(IRQENABLE_L0);
1987         omap_dma_global_context.dma_ocp_sysconfig =
1988                 dma_read(OCP_SYSCONFIG);
1989         omap_dma_global_context.dma_gcr = dma_read(GCR);
1990 }
1991
1992 void omap_dma_global_context_restore(void)
1993 {
1994         int ch;
1995
1996         dma_write(omap_dma_global_context.dma_gcr, GCR);
1997         dma_write(omap_dma_global_context.dma_ocp_sysconfig,
1998                 OCP_SYSCONFIG);
1999         dma_write(omap_dma_global_context.dma_irqenable_l0,
2000                 IRQENABLE_L0);
2001
2002         /*
2003          * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
2004          * after secure sram context save and restore. Hence we need to
2005          * manually clear those IRQs to avoid spurious interrupts. This
2006          * affects only secure devices.
2007          */
2008         if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
2009                 dma_write(0x3 , IRQSTATUS_L0);
2010
2011         for (ch = 0; ch < dma_chan_count; ch++)
2012                 if (dma_chan[ch].dev_id != -1)
2013                         omap_clear_dma(ch);
2014 }
2015
2016 /*----------------------------------------------------------------------------*/
2017
2018 static int __init omap_init_dma(void)
2019 {
2020         unsigned long base;
2021         int ch, r;
2022
2023         if (cpu_class_is_omap1()) {
2024                 base = OMAP1_DMA_BASE;
2025                 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
2026         } else if (cpu_is_omap24xx()) {
2027                 base = OMAP24XX_DMA4_BASE;
2028                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2029         } else if (cpu_is_omap34xx()) {
2030                 base = OMAP34XX_DMA4_BASE;
2031                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2032         } else if (cpu_is_omap44xx()) {
2033                 base = OMAP44XX_DMA4_BASE;
2034                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2035         } else {
2036                 pr_err("DMA init failed for unsupported omap\n");
2037                 return -ENODEV;
2038         }
2039
2040         omap_dma_base = ioremap(base, SZ_4K);
2041         BUG_ON(!omap_dma_base);
2042
2043         if (cpu_class_is_omap2() && omap_dma_reserve_channels
2044                         && (omap_dma_reserve_channels <= dma_lch_count))
2045                 dma_lch_count = omap_dma_reserve_channels;
2046
2047         dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
2048                                 GFP_KERNEL);
2049         if (!dma_chan) {
2050                 r = -ENOMEM;
2051                 goto out_unmap;
2052         }
2053
2054         if (cpu_class_is_omap2()) {
2055                 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2056                                                 dma_lch_count, GFP_KERNEL);
2057                 if (!dma_linked_lch) {
2058                         r = -ENOMEM;
2059                         goto out_free;
2060                 }
2061         }
2062
2063         if (cpu_is_omap15xx()) {
2064                 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
2065                 dma_chan_count = 9;
2066                 enable_1510_mode = 1;
2067         } else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2068                 printk(KERN_INFO "OMAP DMA hardware version %d\n",
2069                        dma_read(HW_ID));
2070                 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
2071                        (dma_read(CAPS_0_U) << 16) |
2072                        dma_read(CAPS_0_L),
2073                        (dma_read(CAPS_1_U) << 16) |
2074                        dma_read(CAPS_1_L),
2075                        dma_read(CAPS_2), dma_read(CAPS_3),
2076                        dma_read(CAPS_4));
2077                 if (!enable_1510_mode) {
2078                         u16 w;
2079
2080                         /* Disable OMAP 3.0/3.1 compatibility mode. */
2081                         w = dma_read(GSCR);
2082                         w |= 1 << 3;
2083                         dma_write(w, GSCR);
2084                         dma_chan_count = 16;
2085                 } else
2086                         dma_chan_count = 9;
2087         } else if (cpu_class_is_omap2()) {
2088                 u8 revision = dma_read(REVISION) & 0xff;
2089                 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
2090                        revision >> 4, revision & 0xf);
2091                 dma_chan_count = dma_lch_count;
2092         } else {
2093                 dma_chan_count = 0;
2094                 return 0;
2095         }
2096
2097         spin_lock_init(&dma_chan_lock);
2098
2099         for (ch = 0; ch < dma_chan_count; ch++) {
2100                 omap_clear_dma(ch);
2101                 dma_chan[ch].dev_id = -1;
2102                 dma_chan[ch].next_lch = -1;
2103
2104                 if (ch >= 6 && enable_1510_mode)
2105                         continue;
2106
2107                 if (cpu_class_is_omap1()) {
2108                         /*
2109                          * request_irq() doesn't like dev_id (ie. ch) being
2110                          * zero, so we have to kludge around this.
2111                          */
2112                         r = request_irq(omap1_dma_irq[ch],
2113                                         omap1_dma_irq_handler, 0, "DMA",
2114                                         (void *) (ch + 1));
2115                         if (r != 0) {
2116                                 int i;
2117
2118                                 printk(KERN_ERR "unable to request IRQ %d "
2119                                        "for DMA (error %d)\n",
2120                                        omap1_dma_irq[ch], r);
2121                                 for (i = 0; i < ch; i++)
2122                                         free_irq(omap1_dma_irq[i],
2123                                                  (void *) (i + 1));
2124                                 goto out_free;
2125                         }
2126                 }
2127         }
2128
2129         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
2130                 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2131                                 DMA_DEFAULT_FIFO_DEPTH, 0);
2132
2133         if (cpu_class_is_omap2()) {
2134                 int irq;
2135                 if (cpu_is_omap44xx())
2136                         irq = INT_44XX_SDMA_IRQ0;
2137                 else
2138                         irq = INT_24XX_SDMA_IRQ0;
2139                 setup_irq(irq, &omap24xx_dma_irq);
2140         }
2141
2142         if (cpu_is_omap34xx()) {
2143                 /* Enable smartidle idlemodes and autoidle */
2144                 u32 v = dma_read(OCP_SYSCONFIG);
2145                 v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK |
2146                                 DMA_SYSCONFIG_SIDLEMODE_MASK |
2147                                 DMA_SYSCONFIG_AUTOIDLE);
2148                 v |= (DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
2149                         DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
2150                         DMA_SYSCONFIG_AUTOIDLE);
2151                 dma_write(v , OCP_SYSCONFIG);
2152                 /* reserve dma channels 0 and 1 in high security devices */
2153                 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
2154                         printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
2155                                         "HS ROM code\n");
2156                         dma_chan[0].dev_id = 0;
2157                         dma_chan[1].dev_id = 1;
2158                 }
2159         }
2160
2161         return 0;
2162
2163 out_free:
2164         kfree(dma_chan);
2165
2166 out_unmap:
2167         iounmap(omap_dma_base);
2168
2169         return r;
2170 }
2171
2172 arch_initcall(omap_init_dma);
2173
2174 /*
2175  * Reserve the omap SDMA channels using cmdline bootarg
2176  * "omap_dma_reserve_ch=". The valid range is 1 to 32
2177  */
2178 static int __init omap_dma_cmdline_reserve_ch(char *str)
2179 {
2180         if (get_option(&str, &omap_dma_reserve_channels) != 1)
2181                 omap_dma_reserve_channels = 0;
2182         return 1;
2183 }
2184
2185 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);
2186
2187