ARM: add size argument to __cpuc_flush_dcache_page
[linux-2.6.git] / arch / arm / mm / proc-xscale.S
1 /*
2  *  linux/arch/arm/mm/proc-xscale.S
3  *
4  *  Author:     Nicolas Pitre
5  *  Created:    November 2000
6  *  Copyright:  (C) 2000, 2001 MontaVista Software Inc.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  *
12  * MMU functions for the Intel XScale CPUs
13  *
14  * 2001 Aug 21:
15  *      some contributions by Brett Gaines <brett.w.gaines@intel.com>
16  *      Copyright 2001 by Intel Corp.
17  *
18  * 2001 Sep 08:
19  *      Completely revisited, many important fixes
20  *      Nicolas Pitre <nico@fluxnic.net>
21  */
22
23 #include <linux/linkage.h>
24 #include <linux/init.h>
25 #include <asm/assembler.h>
26 #include <asm/hwcap.h>
27 #include <asm/pgtable.h>
28 #include <asm/pgtable-hwdef.h>
29 #include <asm/page.h>
30 #include <asm/ptrace.h>
31 #include "proc-macros.S"
32
33 /*
34  * This is the maximum size of an area which will be flushed.  If the area
35  * is larger than this, then we flush the whole cache
36  */
37 #define MAX_AREA_SIZE   32768
38
39 /*
40  * the cache line size of the I and D cache
41  */
42 #define CACHELINESIZE   32
43
44 /*
45  * the size of the data cache
46  */
47 #define CACHESIZE       32768
48
49 /*
50  * Virtual address used to allocate the cache when flushed
51  *
52  * This must be an address range which is _never_ used.  It should
53  * apparently have a mapping in the corresponding page table for
54  * compatibility with future CPUs that _could_ require it.  For instance we
55  * don't care.
56  *
57  * This must be aligned on a 2*CACHESIZE boundary.  The code selects one of
58  * the 2 areas in alternance each time the clean_d_cache macro is used.
59  * Without this the XScale core exhibits cache eviction problems and no one
60  * knows why.
61  *
62  * Reminder: the vector table is located at 0xffff0000-0xffff0fff.
63  */
64 #define CLEAN_ADDR      0xfffe0000
65
66 /*
67  * This macro is used to wait for a CP15 write and is needed
68  * when we have to ensure that the last operation to the co-pro
69  * was completed before continuing with operation.
70  */
71         .macro  cpwait, rd
72         mrc     p15, 0, \rd, c2, c0, 0          @ arbitrary read of cp15
73         mov     \rd, \rd                        @ wait for completion
74         sub     pc, pc, #4                      @ flush instruction pipeline
75         .endm
76
77         .macro  cpwait_ret, lr, rd
78         mrc     p15, 0, \rd, c2, c0, 0          @ arbitrary read of cp15
79         sub     pc, \lr, \rd, LSR #32           @ wait for completion and
80                                                 @ flush instruction pipeline
81         .endm
82
83 /*
84  * This macro cleans the entire dcache using line allocate.
85  * The main loop has been unrolled to reduce loop overhead.
86  * rd and rs are two scratch registers.
87  */
88         .macro  clean_d_cache, rd, rs
89         ldr     \rs, =clean_addr
90         ldr     \rd, [\rs]
91         eor     \rd, \rd, #CACHESIZE
92         str     \rd, [\rs]
93         add     \rs, \rd, #CACHESIZE
94 1:      mcr     p15, 0, \rd, c7, c2, 5          @ allocate D cache line
95         add     \rd, \rd, #CACHELINESIZE
96         mcr     p15, 0, \rd, c7, c2, 5          @ allocate D cache line
97         add     \rd, \rd, #CACHELINESIZE
98         mcr     p15, 0, \rd, c7, c2, 5          @ allocate D cache line
99         add     \rd, \rd, #CACHELINESIZE
100         mcr     p15, 0, \rd, c7, c2, 5          @ allocate D cache line
101         add     \rd, \rd, #CACHELINESIZE
102         teq     \rd, \rs
103         bne     1b
104         .endm
105
106         .data
107 clean_addr:     .word   CLEAN_ADDR
108
109         .text
110
111 /*
112  * cpu_xscale_proc_init()
113  *
114  * Nothing too exciting at the moment
115  */
116 ENTRY(cpu_xscale_proc_init)
117         @ enable write buffer coalescing. Some bootloader disable it
118         mrc     p15, 0, r1, c1, c0, 1
119         bic     r1, r1, #1
120         mcr     p15, 0, r1, c1, c0, 1
121         mov     pc, lr
122
123 /*
124  * cpu_xscale_proc_fin()
125  */
126 ENTRY(cpu_xscale_proc_fin)
127         str     lr, [sp, #-4]!
128         mov     r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
129         msr     cpsr_c, r0
130         bl      xscale_flush_kern_cache_all     @ clean caches
131         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
132         bic     r0, r0, #0x1800                 @ ...IZ...........
133         bic     r0, r0, #0x0006                 @ .............CA.
134         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
135         ldr     pc, [sp], #4
136
137 /*
138  * cpu_xscale_reset(loc)
139  *
140  * Perform a soft reset of the system.  Put the CPU into the
141  * same state as it would be if it had been reset, and branch
142  * to what would be the reset vector.
143  *
144  * loc: location to jump to for soft reset
145  *
146  * Beware PXA270 erratum E7.
147  */
148         .align  5
149 ENTRY(cpu_xscale_reset)
150         mov     r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
151         msr     cpsr_c, r1                      @ reset CPSR
152         mcr     p15, 0, r1, c10, c4, 1          @ unlock I-TLB
153         mcr     p15, 0, r1, c8, c5, 0           @ invalidate I-TLB
154         mrc     p15, 0, r1, c1, c0, 0           @ ctrl register
155         bic     r1, r1, #0x0086                 @ ........B....CA.
156         bic     r1, r1, #0x3900                 @ ..VIZ..S........
157         sub     pc, pc, #4                      @ flush pipeline
158         @ *** cache line aligned ***
159         mcr     p15, 0, r1, c1, c0, 0           @ ctrl register
160         bic     r1, r1, #0x0001                 @ ...............M
161         mcr     p15, 0, ip, c7, c7, 0           @ invalidate I,D caches & BTB
162         mcr     p15, 0, r1, c1, c0, 0           @ ctrl register
163         @ CAUTION: MMU turned off from this point. We count on the pipeline
164         @ already containing those two last instructions to survive.
165         mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
166         mov     pc, r0
167
168 /*
169  * cpu_xscale_do_idle()
170  *
171  * Cause the processor to idle
172  *
173  * For now we do nothing but go to idle mode for every case
174  *
175  * XScale supports clock switching, but using idle mode support
176  * allows external hardware to react to system state changes.
177  */
178         .align  5
179
180 ENTRY(cpu_xscale_do_idle)
181         mov     r0, #1
182         mcr     p14, 0, r0, c7, c0, 0           @ Go to IDLE
183         mov     pc, lr
184
185 /* ================================= CACHE ================================ */
186
187 /*
188  *      flush_user_cache_all()
189  *
190  *      Invalidate all cache entries in a particular address
191  *      space.
192  */
193 ENTRY(xscale_flush_user_cache_all)
194         /* FALLTHROUGH */
195
196 /*
197  *      flush_kern_cache_all()
198  *
199  *      Clean and invalidate the entire cache.
200  */
201 ENTRY(xscale_flush_kern_cache_all)
202         mov     r2, #VM_EXEC
203         mov     ip, #0
204 __flush_whole_cache:
205         clean_d_cache r0, r1
206         tst     r2, #VM_EXEC
207         mcrne   p15, 0, ip, c7, c5, 0           @ Invalidate I cache & BTB
208         mcrne   p15, 0, ip, c7, c10, 4          @ Drain Write (& Fill) Buffer
209         mov     pc, lr
210
211 /*
212  *      flush_user_cache_range(start, end, vm_flags)
213  *
214  *      Invalidate a range of cache entries in the specified
215  *      address space.
216  *
217  *      - start - start address (may not be aligned)
218  *      - end   - end address (exclusive, may not be aligned)
219  *      - vma   - vma_area_struct describing address space
220  */
221         .align  5
222 ENTRY(xscale_flush_user_cache_range)
223         mov     ip, #0
224         sub     r3, r1, r0                      @ calculate total size
225         cmp     r3, #MAX_AREA_SIZE
226         bhs     __flush_whole_cache
227
228 1:      tst     r2, #VM_EXEC
229         mcrne   p15, 0, r0, c7, c5, 1           @ Invalidate I cache line
230         mcr     p15, 0, r0, c7, c10, 1          @ Clean D cache line
231         mcr     p15, 0, r0, c7, c6, 1           @ Invalidate D cache line
232         add     r0, r0, #CACHELINESIZE
233         cmp     r0, r1
234         blo     1b
235         tst     r2, #VM_EXEC
236         mcrne   p15, 0, ip, c7, c5, 6           @ Invalidate BTB
237         mcrne   p15, 0, ip, c7, c10, 4          @ Drain Write (& Fill) Buffer
238         mov     pc, lr
239
240 /*
241  *      coherent_kern_range(start, end)
242  *
243  *      Ensure coherency between the Icache and the Dcache in the
244  *      region described by start.  If you have non-snooping
245  *      Harvard caches, you need to implement this function.
246  *
247  *      - start  - virtual start address
248  *      - end    - virtual end address
249  *
250  *      Note: single I-cache line invalidation isn't used here since
251  *      it also trashes the mini I-cache used by JTAG debuggers.
252  */
253 ENTRY(xscale_coherent_kern_range)
254         bic     r0, r0, #CACHELINESIZE - 1
255 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
256         add     r0, r0, #CACHELINESIZE
257         cmp     r0, r1
258         blo     1b
259         mov     r0, #0
260         mcr     p15, 0, r0, c7, c5, 0           @ Invalidate I cache & BTB
261         mcr     p15, 0, r0, c7, c10, 4          @ Drain Write (& Fill) Buffer
262         mov     pc, lr
263
264 /*
265  *      coherent_user_range(start, end)
266  *
267  *      Ensure coherency between the Icache and the Dcache in the
268  *      region described by start.  If you have non-snooping
269  *      Harvard caches, you need to implement this function.
270  *
271  *      - start  - virtual start address
272  *      - end    - virtual end address
273  */
274 ENTRY(xscale_coherent_user_range)
275         bic     r0, r0, #CACHELINESIZE - 1
276 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
277         mcr     p15, 0, r0, c7, c5, 1           @ Invalidate I cache entry
278         add     r0, r0, #CACHELINESIZE
279         cmp     r0, r1
280         blo     1b
281         mov     r0, #0
282         mcr     p15, 0, r0, c7, c5, 6           @ Invalidate BTB
283         mcr     p15, 0, r0, c7, c10, 4          @ Drain Write (& Fill) Buffer
284         mov     pc, lr
285
286 /*
287  *      flush_kern_dcache_area(void *addr, size_t size)
288  *
289  *      Ensure no D cache aliasing occurs, either with itself or
290  *      the I cache
291  *
292  *      - addr  - kernel address
293  *      - size  - region size
294  */
295 ENTRY(xscale_flush_kern_dcache_area)
296         add     r1, r0, r1
297 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
298         mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
299         add     r0, r0, #CACHELINESIZE
300         cmp     r0, r1
301         blo     1b
302         mov     r0, #0
303         mcr     p15, 0, r0, c7, c5, 0           @ Invalidate I cache & BTB
304         mcr     p15, 0, r0, c7, c10, 4          @ Drain Write (& Fill) Buffer
305         mov     pc, lr
306
307 /*
308  *      dma_inv_range(start, end)
309  *
310  *      Invalidate (discard) the specified virtual address range.
311  *      May not write back any entries.  If 'start' or 'end'
312  *      are not cache line aligned, those lines must be written
313  *      back.
314  *
315  *      - start  - virtual start address
316  *      - end    - virtual end address
317  */
318 ENTRY(xscale_dma_inv_range)
319         tst     r0, #CACHELINESIZE - 1
320         bic     r0, r0, #CACHELINESIZE - 1
321         mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
322         tst     r1, #CACHELINESIZE - 1
323         mcrne   p15, 0, r1, c7, c10, 1          @ clean D entry
324 1:      mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
325         add     r0, r0, #CACHELINESIZE
326         cmp     r0, r1
327         blo     1b
328         mcr     p15, 0, r0, c7, c10, 4          @ Drain Write (& Fill) Buffer
329         mov     pc, lr
330
331 /*
332  *      dma_clean_range(start, end)
333  *
334  *      Clean the specified virtual address range.
335  *
336  *      - start  - virtual start address
337  *      - end    - virtual end address
338  */
339 ENTRY(xscale_dma_clean_range)
340         bic     r0, r0, #CACHELINESIZE - 1
341 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
342         add     r0, r0, #CACHELINESIZE
343         cmp     r0, r1
344         blo     1b
345         mcr     p15, 0, r0, c7, c10, 4          @ Drain Write (& Fill) Buffer
346         mov     pc, lr
347
348 /*
349  *      dma_flush_range(start, end)
350  *
351  *      Clean and invalidate the specified virtual address range.
352  *
353  *      - start  - virtual start address
354  *      - end    - virtual end address
355  */
356 ENTRY(xscale_dma_flush_range)
357         bic     r0, r0, #CACHELINESIZE - 1
358 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
359         mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
360         add     r0, r0, #CACHELINESIZE
361         cmp     r0, r1
362         blo     1b
363         mcr     p15, 0, r0, c7, c10, 4          @ Drain Write (& Fill) Buffer
364         mov     pc, lr
365
366 ENTRY(xscale_cache_fns)
367         .long   xscale_flush_kern_cache_all
368         .long   xscale_flush_user_cache_all
369         .long   xscale_flush_user_cache_range
370         .long   xscale_coherent_kern_range
371         .long   xscale_coherent_user_range
372         .long   xscale_flush_kern_dcache_area
373         .long   xscale_dma_inv_range
374         .long   xscale_dma_clean_range
375         .long   xscale_dma_flush_range
376
377 /*
378  * On stepping A0/A1 of the 80200, invalidating D-cache by line doesn't
379  * clear the dirty bits, which means that if we invalidate a dirty line,
380  * the dirty data can still be written back to external memory later on.
381  *
382  * The recommended workaround is to always do a clean D-cache line before
383  * doing an invalidate D-cache line, so on the affected processors,
384  * dma_inv_range() is implemented as dma_flush_range().
385  *
386  * See erratum #25 of "Intel 80200 Processor Specification Update",
387  * revision January 22, 2003, available at:
388  *     http://www.intel.com/design/iio/specupdt/273415.htm
389  */
390 ENTRY(xscale_80200_A0_A1_cache_fns)
391         .long   xscale_flush_kern_cache_all
392         .long   xscale_flush_user_cache_all
393         .long   xscale_flush_user_cache_range
394         .long   xscale_coherent_kern_range
395         .long   xscale_coherent_user_range
396         .long   xscale_flush_kern_dcache_area
397         .long   xscale_dma_flush_range
398         .long   xscale_dma_clean_range
399         .long   xscale_dma_flush_range
400
401 ENTRY(cpu_xscale_dcache_clean_area)
402 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
403         add     r0, r0, #CACHELINESIZE
404         subs    r1, r1, #CACHELINESIZE
405         bhi     1b
406         mov     pc, lr
407
408 /* =============================== PageTable ============================== */
409
410 /*
411  * cpu_xscale_switch_mm(pgd)
412  *
413  * Set the translation base pointer to be as described by pgd.
414  *
415  * pgd: new page tables
416  */
417         .align  5
418 ENTRY(cpu_xscale_switch_mm)
419         clean_d_cache r1, r2
420         mcr     p15, 0, ip, c7, c5, 0           @ Invalidate I cache & BTB
421         mcr     p15, 0, ip, c7, c10, 4          @ Drain Write (& Fill) Buffer
422         mcr     p15, 0, r0, c2, c0, 0           @ load page table pointer
423         mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
424         cpwait_ret lr, ip
425
426 /*
427  * cpu_xscale_set_pte_ext(ptep, pte, ext)
428  *
429  * Set a PTE and flush it out
430  *
431  * Errata 40: must set memory to write-through for user read-only pages.
432  */
433 cpu_xscale_mt_table:
434         .long   0x00                                            @ L_PTE_MT_UNCACHED
435         .long   PTE_BUFFERABLE                                  @ L_PTE_MT_BUFFERABLE
436         .long   PTE_CACHEABLE                                   @ L_PTE_MT_WRITETHROUGH
437         .long   PTE_CACHEABLE | PTE_BUFFERABLE                  @ L_PTE_MT_WRITEBACK
438         .long   PTE_EXT_TEX(1) | PTE_BUFFERABLE                 @ L_PTE_MT_DEV_SHARED
439         .long   0x00                                            @ unused
440         .long   PTE_EXT_TEX(1) | PTE_CACHEABLE                  @ L_PTE_MT_MINICACHE
441         .long   PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC
442         .long   0x00                                            @ unused
443         .long   PTE_BUFFERABLE                                  @ L_PTE_MT_DEV_WC
444         .long   0x00                                            @ unused
445         .long   PTE_CACHEABLE | PTE_BUFFERABLE                  @ L_PTE_MT_DEV_CACHED
446         .long   0x00                                            @ L_PTE_MT_DEV_NONSHARED
447         .long   0x00                                            @ unused
448         .long   0x00                                            @ unused
449         .long   0x00                                            @ unused
450
451         .align  5
452 ENTRY(cpu_xscale_set_pte_ext)
453         xscale_set_pte_ext_prologue
454
455         @
456         @ Erratum 40: must set memory to write-through for user read-only pages
457         @
458         and     ip, r1, #(L_PTE_MT_MASK | L_PTE_USER | L_PTE_WRITE) & ~(4 << 2)
459         teq     ip, #L_PTE_MT_WRITEBACK | L_PTE_USER
460
461         moveq   r1, #L_PTE_MT_WRITETHROUGH
462         and     r1, r1, #L_PTE_MT_MASK
463         adr     ip, cpu_xscale_mt_table
464         ldr     ip, [ip, r1]
465         bic     r2, r2, #0x0c
466         orr     r2, r2, ip
467
468         xscale_set_pte_ext_epilogue
469         mov     pc, lr
470
471
472         .ltorg
473
474         .align
475
476         __INIT
477
478         .type   __xscale_setup, #function
479 __xscale_setup:
480         mcr     p15, 0, ip, c7, c7, 0           @ invalidate I, D caches & BTB
481         mcr     p15, 0, ip, c7, c10, 4          @ Drain Write (& Fill) Buffer
482         mcr     p15, 0, ip, c8, c7, 0           @ invalidate I, D TLBs
483         mov     r0, #1 << 6                     @ cp6 for IOP3xx and Bulverde
484         orr     r0, r0, #1 << 13                @ Its undefined whether this
485         mcr     p15, 0, r0, c15, c1, 0          @ affects USR or SVC modes
486
487         adr     r5, xscale_crval
488         ldmia   r5, {r5, r6}
489         mrc     p15, 0, r0, c1, c0, 0           @ get control register
490         bic     r0, r0, r5
491         orr     r0, r0, r6
492         mov     pc, lr
493         .size   __xscale_setup, . - __xscale_setup
494
495         /*
496          *  R
497          * .RVI ZFRS BLDP WCAM
498          * ..11 1.01 .... .101
499          * 
500          */
501         .type   xscale_crval, #object
502 xscale_crval:
503         crval   clear=0x00003b07, mmuset=0x00003905, ucset=0x00001900
504
505         __INITDATA
506
507 /*
508  * Purpose : Function pointers used to access above functions - all calls
509  *           come through these
510  */
511
512         .type   xscale_processor_functions, #object
513 ENTRY(xscale_processor_functions)
514         .word   v5t_early_abort
515         .word   legacy_pabort
516         .word   cpu_xscale_proc_init
517         .word   cpu_xscale_proc_fin
518         .word   cpu_xscale_reset
519         .word   cpu_xscale_do_idle
520         .word   cpu_xscale_dcache_clean_area
521         .word   cpu_xscale_switch_mm
522         .word   cpu_xscale_set_pte_ext
523         .size   xscale_processor_functions, . - xscale_processor_functions
524
525         .section ".rodata"
526
527         .type   cpu_arch_name, #object
528 cpu_arch_name:
529         .asciz  "armv5te"
530         .size   cpu_arch_name, . - cpu_arch_name
531
532         .type   cpu_elf_name, #object
533 cpu_elf_name:
534         .asciz  "v5"
535         .size   cpu_elf_name, . - cpu_elf_name
536
537         .type   cpu_80200_A0_A1_name, #object
538 cpu_80200_A0_A1_name:
539         .asciz  "XScale-80200 A0/A1"
540         .size   cpu_80200_A0_A1_name, . - cpu_80200_A0_A1_name
541
542         .type   cpu_80200_name, #object
543 cpu_80200_name:
544         .asciz  "XScale-80200"
545         .size   cpu_80200_name, . - cpu_80200_name
546
547         .type   cpu_80219_name, #object
548 cpu_80219_name:
549         .asciz  "XScale-80219"
550         .size   cpu_80219_name, . - cpu_80219_name
551
552         .type   cpu_8032x_name, #object
553 cpu_8032x_name:
554         .asciz  "XScale-IOP8032x Family"
555         .size   cpu_8032x_name, . - cpu_8032x_name
556
557         .type   cpu_8033x_name, #object
558 cpu_8033x_name:
559         .asciz  "XScale-IOP8033x Family"
560         .size   cpu_8033x_name, . - cpu_8033x_name
561
562         .type   cpu_pxa250_name, #object
563 cpu_pxa250_name:
564         .asciz  "XScale-PXA250"
565         .size   cpu_pxa250_name, . - cpu_pxa250_name
566
567         .type   cpu_pxa210_name, #object
568 cpu_pxa210_name:
569         .asciz  "XScale-PXA210"
570         .size   cpu_pxa210_name, . - cpu_pxa210_name
571
572         .type   cpu_ixp42x_name, #object
573 cpu_ixp42x_name:
574         .asciz  "XScale-IXP42x Family"
575         .size   cpu_ixp42x_name, . - cpu_ixp42x_name
576
577         .type   cpu_ixp43x_name, #object
578 cpu_ixp43x_name:
579         .asciz  "XScale-IXP43x Family"
580         .size   cpu_ixp43x_name, . - cpu_ixp43x_name
581
582         .type   cpu_ixp46x_name, #object
583 cpu_ixp46x_name:
584         .asciz  "XScale-IXP46x Family"
585         .size   cpu_ixp46x_name, . - cpu_ixp46x_name
586
587         .type   cpu_ixp2400_name, #object
588 cpu_ixp2400_name:
589         .asciz  "XScale-IXP2400"
590         .size   cpu_ixp2400_name, . - cpu_ixp2400_name
591
592         .type   cpu_ixp2800_name, #object
593 cpu_ixp2800_name:
594         .asciz  "XScale-IXP2800"
595         .size   cpu_ixp2800_name, . - cpu_ixp2800_name
596
597         .type   cpu_pxa255_name, #object
598 cpu_pxa255_name:
599         .asciz  "XScale-PXA255"
600         .size   cpu_pxa255_name, . - cpu_pxa255_name
601
602         .type   cpu_pxa270_name, #object
603 cpu_pxa270_name:
604         .asciz  "XScale-PXA270"
605         .size   cpu_pxa270_name, . - cpu_pxa270_name
606
607         .align
608
609         .section ".proc.info.init", #alloc, #execinstr
610
611         .type   __80200_A0_A1_proc_info,#object
612 __80200_A0_A1_proc_info:
613         .long   0x69052000
614         .long   0xfffffffe
615         .long   PMD_TYPE_SECT | \
616                 PMD_SECT_BUFFERABLE | \
617                 PMD_SECT_CACHEABLE | \
618                 PMD_SECT_AP_WRITE | \
619                 PMD_SECT_AP_READ
620         .long   PMD_TYPE_SECT | \
621                 PMD_SECT_AP_WRITE | \
622                 PMD_SECT_AP_READ
623         b       __xscale_setup
624         .long   cpu_arch_name
625         .long   cpu_elf_name
626         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
627         .long   cpu_80200_name
628         .long   xscale_processor_functions
629         .long   v4wbi_tlb_fns
630         .long   xscale_mc_user_fns
631         .long   xscale_80200_A0_A1_cache_fns
632         .size   __80200_A0_A1_proc_info, . - __80200_A0_A1_proc_info
633
634         .type   __80200_proc_info,#object
635 __80200_proc_info:
636         .long   0x69052000
637         .long   0xfffffff0
638         .long   PMD_TYPE_SECT | \
639                 PMD_SECT_BUFFERABLE | \
640                 PMD_SECT_CACHEABLE | \
641                 PMD_SECT_AP_WRITE | \
642                 PMD_SECT_AP_READ
643         .long   PMD_TYPE_SECT | \
644                 PMD_SECT_AP_WRITE | \
645                 PMD_SECT_AP_READ
646         b       __xscale_setup
647         .long   cpu_arch_name
648         .long   cpu_elf_name
649         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
650         .long   cpu_80200_name
651         .long   xscale_processor_functions
652         .long   v4wbi_tlb_fns
653         .long   xscale_mc_user_fns
654         .long   xscale_cache_fns
655         .size   __80200_proc_info, . - __80200_proc_info
656
657         .type   __80219_proc_info,#object
658 __80219_proc_info:
659         .long   0x69052e20
660         .long   0xffffffe0
661         .long   PMD_TYPE_SECT | \
662                 PMD_SECT_BUFFERABLE | \
663                 PMD_SECT_CACHEABLE | \
664                 PMD_SECT_AP_WRITE | \
665                 PMD_SECT_AP_READ
666         .long   PMD_TYPE_SECT | \
667                 PMD_SECT_AP_WRITE | \
668                 PMD_SECT_AP_READ
669         b       __xscale_setup
670         .long   cpu_arch_name
671         .long   cpu_elf_name
672         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
673         .long   cpu_80219_name
674         .long   xscale_processor_functions
675         .long   v4wbi_tlb_fns
676         .long   xscale_mc_user_fns
677         .long   xscale_cache_fns
678         .size   __80219_proc_info, . - __80219_proc_info
679
680         .type   __8032x_proc_info,#object
681 __8032x_proc_info:
682         .long   0x69052420
683         .long   0xfffff7e0
684         .long   PMD_TYPE_SECT | \
685                 PMD_SECT_BUFFERABLE | \
686                 PMD_SECT_CACHEABLE | \
687                 PMD_SECT_AP_WRITE | \
688                 PMD_SECT_AP_READ
689         .long   PMD_TYPE_SECT | \
690                 PMD_SECT_AP_WRITE | \
691                 PMD_SECT_AP_READ
692         b       __xscale_setup
693         .long   cpu_arch_name
694         .long   cpu_elf_name
695         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
696         .long   cpu_8032x_name
697         .long   xscale_processor_functions
698         .long   v4wbi_tlb_fns
699         .long   xscale_mc_user_fns
700         .long   xscale_cache_fns
701         .size   __8032x_proc_info, . - __8032x_proc_info
702
703         .type   __8033x_proc_info,#object
704 __8033x_proc_info:
705         .long   0x69054010
706         .long   0xfffffd30
707         .long   PMD_TYPE_SECT | \
708                 PMD_SECT_BUFFERABLE | \
709                 PMD_SECT_CACHEABLE | \
710                 PMD_SECT_AP_WRITE | \
711                 PMD_SECT_AP_READ
712         .long   PMD_TYPE_SECT | \
713                 PMD_SECT_AP_WRITE | \
714                 PMD_SECT_AP_READ
715         b       __xscale_setup
716         .long   cpu_arch_name
717         .long   cpu_elf_name
718         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
719         .long   cpu_8033x_name
720         .long   xscale_processor_functions
721         .long   v4wbi_tlb_fns
722         .long   xscale_mc_user_fns
723         .long   xscale_cache_fns
724         .size   __8033x_proc_info, . - __8033x_proc_info
725
726         .type   __pxa250_proc_info,#object
727 __pxa250_proc_info:
728         .long   0x69052100
729         .long   0xfffff7f0
730         .long   PMD_TYPE_SECT | \
731                 PMD_SECT_BUFFERABLE | \
732                 PMD_SECT_CACHEABLE | \
733                 PMD_SECT_AP_WRITE | \
734                 PMD_SECT_AP_READ
735         .long   PMD_TYPE_SECT | \
736                 PMD_SECT_AP_WRITE | \
737                 PMD_SECT_AP_READ
738         b       __xscale_setup
739         .long   cpu_arch_name
740         .long   cpu_elf_name
741         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
742         .long   cpu_pxa250_name
743         .long   xscale_processor_functions
744         .long   v4wbi_tlb_fns
745         .long   xscale_mc_user_fns
746         .long   xscale_cache_fns
747         .size   __pxa250_proc_info, . - __pxa250_proc_info
748
749         .type   __pxa210_proc_info,#object
750 __pxa210_proc_info:
751         .long   0x69052120
752         .long   0xfffff3f0
753         .long   PMD_TYPE_SECT | \
754                 PMD_SECT_BUFFERABLE | \
755                 PMD_SECT_CACHEABLE | \
756                 PMD_SECT_AP_WRITE | \
757                 PMD_SECT_AP_READ
758         .long   PMD_TYPE_SECT | \
759                 PMD_SECT_AP_WRITE | \
760                 PMD_SECT_AP_READ
761         b       __xscale_setup
762         .long   cpu_arch_name
763         .long   cpu_elf_name
764         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
765         .long   cpu_pxa210_name
766         .long   xscale_processor_functions
767         .long   v4wbi_tlb_fns
768         .long   xscale_mc_user_fns
769         .long   xscale_cache_fns
770         .size   __pxa210_proc_info, . - __pxa210_proc_info
771
772         .type   __ixp2400_proc_info, #object
773 __ixp2400_proc_info:
774         .long   0x69054190
775         .long   0xfffffff0
776         .long   PMD_TYPE_SECT | \
777                 PMD_SECT_BUFFERABLE | \
778                 PMD_SECT_CACHEABLE | \
779                 PMD_SECT_AP_WRITE | \
780                 PMD_SECT_AP_READ
781         .long   PMD_TYPE_SECT | \
782                 PMD_SECT_AP_WRITE | \
783                 PMD_SECT_AP_READ
784         b       __xscale_setup
785         .long   cpu_arch_name
786         .long   cpu_elf_name
787         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
788         .long   cpu_ixp2400_name
789         .long   xscale_processor_functions
790         .long   v4wbi_tlb_fns
791         .long   xscale_mc_user_fns
792         .long   xscale_cache_fns
793         .size   __ixp2400_proc_info, . - __ixp2400_proc_info                
794
795         .type   __ixp2800_proc_info, #object
796 __ixp2800_proc_info:
797         .long   0x690541a0
798         .long   0xfffffff0
799         .long   PMD_TYPE_SECT | \
800                 PMD_SECT_BUFFERABLE | \
801                 PMD_SECT_CACHEABLE | \
802                 PMD_SECT_AP_WRITE | \
803                 PMD_SECT_AP_READ
804         .long   PMD_TYPE_SECT | \
805                 PMD_SECT_AP_WRITE | \
806                 PMD_SECT_AP_READ
807         b       __xscale_setup
808         .long   cpu_arch_name
809         .long   cpu_elf_name
810         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
811         .long   cpu_ixp2800_name
812         .long   xscale_processor_functions
813         .long   v4wbi_tlb_fns
814         .long   xscale_mc_user_fns
815         .long   xscale_cache_fns
816         .size   __ixp2800_proc_info, . - __ixp2800_proc_info                
817
818         .type   __ixp42x_proc_info, #object
819 __ixp42x_proc_info:
820         .long   0x690541c0
821         .long   0xffffffc0
822         .long   PMD_TYPE_SECT | \
823                 PMD_SECT_BUFFERABLE | \
824                 PMD_SECT_CACHEABLE | \
825                 PMD_SECT_AP_WRITE | \
826                 PMD_SECT_AP_READ
827         .long   PMD_TYPE_SECT | \
828                 PMD_SECT_AP_WRITE | \
829                 PMD_SECT_AP_READ
830         b       __xscale_setup
831         .long   cpu_arch_name
832         .long   cpu_elf_name
833         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
834         .long   cpu_ixp42x_name
835         .long   xscale_processor_functions
836         .long   v4wbi_tlb_fns
837         .long   xscale_mc_user_fns
838         .long   xscale_cache_fns
839         .size   __ixp42x_proc_info, . - __ixp42x_proc_info                
840
841         .type   __ixp43x_proc_info, #object
842 __ixp43x_proc_info:
843         .long   0x69054040
844         .long   0xfffffff0
845         .long   PMD_TYPE_SECT | \
846                 PMD_SECT_BUFFERABLE | \
847                 PMD_SECT_CACHEABLE | \
848                 PMD_SECT_AP_WRITE | \
849                 PMD_SECT_AP_READ
850         .long   PMD_TYPE_SECT | \
851                 PMD_SECT_AP_WRITE | \
852                 PMD_SECT_AP_READ
853         b       __xscale_setup
854         .long   cpu_arch_name
855         .long   cpu_elf_name
856         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
857         .long   cpu_ixp43x_name
858         .long   xscale_processor_functions
859         .long   v4wbi_tlb_fns
860         .long   xscale_mc_user_fns
861         .long   xscale_cache_fns
862         .size   __ixp43x_proc_info, . - __ixp43x_proc_info
863
864         .type   __ixp46x_proc_info, #object
865 __ixp46x_proc_info:
866         .long   0x69054200
867         .long   0xffffff00
868         .long   PMD_TYPE_SECT | \
869                 PMD_SECT_BUFFERABLE | \
870                 PMD_SECT_CACHEABLE | \
871                 PMD_SECT_AP_WRITE | \
872                 PMD_SECT_AP_READ
873         .long   PMD_TYPE_SECT | \
874                 PMD_SECT_AP_WRITE | \
875                 PMD_SECT_AP_READ
876         b       __xscale_setup
877         .long   cpu_arch_name
878         .long   cpu_elf_name
879         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
880         .long   cpu_ixp46x_name
881         .long   xscale_processor_functions
882         .long   v4wbi_tlb_fns
883         .long   xscale_mc_user_fns
884         .long   xscale_cache_fns
885         .size   __ixp46x_proc_info, . - __ixp46x_proc_info
886
887         .type   __pxa255_proc_info,#object
888 __pxa255_proc_info:
889         .long   0x69052d00
890         .long   0xfffffff0
891         .long   PMD_TYPE_SECT | \
892                 PMD_SECT_BUFFERABLE | \
893                 PMD_SECT_CACHEABLE | \
894                 PMD_SECT_AP_WRITE | \
895                 PMD_SECT_AP_READ
896         .long   PMD_TYPE_SECT | \
897                 PMD_SECT_AP_WRITE | \
898                 PMD_SECT_AP_READ
899         b       __xscale_setup
900         .long   cpu_arch_name
901         .long   cpu_elf_name
902         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
903         .long   cpu_pxa255_name
904         .long   xscale_processor_functions
905         .long   v4wbi_tlb_fns
906         .long   xscale_mc_user_fns
907         .long   xscale_cache_fns
908         .size   __pxa255_proc_info, . - __pxa255_proc_info
909
910         .type   __pxa270_proc_info,#object
911 __pxa270_proc_info:
912         .long   0x69054110
913         .long   0xfffffff0
914         .long   PMD_TYPE_SECT | \
915                 PMD_SECT_BUFFERABLE | \
916                 PMD_SECT_CACHEABLE | \
917                 PMD_SECT_AP_WRITE | \
918                 PMD_SECT_AP_READ
919         .long   PMD_TYPE_SECT | \
920                 PMD_SECT_AP_WRITE | \
921                 PMD_SECT_AP_READ
922         b       __xscale_setup
923         .long   cpu_arch_name
924         .long   cpu_elf_name
925         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
926         .long   cpu_pxa270_name
927         .long   xscale_processor_functions
928         .long   v4wbi_tlb_fns
929         .long   xscale_mc_user_fns
930         .long   xscale_cache_fns
931         .size   __pxa270_proc_info, . - __pxa270_proc_info
932