80d6e1de069ada45c74cf6b665b91292d5990019
[linux-2.6.git] / arch / arm / mm / proc-arm6_7.S
1 /*
2  *  linux/arch/arm/mm/proc-arm6,7.S
3  *
4  *  Copyright (C) 1997-2000 Russell King
5  *  hacked for non-paged-MM by Hyok S. Choi, 2003.
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  *
11  *  These are the low level assembler for performing cache and TLB
12  *  functions on the ARM610 & ARM710.
13  */
14 #include <linux/linkage.h>
15 #include <linux/init.h>
16 #include <asm/assembler.h>
17 #include <asm/asm-offsets.h>
18 #include <asm/hwcap.h>
19 #include <asm/pgtable-hwdef.h>
20 #include <asm/pgtable.h>
21 #include <asm/ptrace.h>
22
23 #include "proc-macros.S"
24
25 ENTRY(cpu_arm6_dcache_clean_area)
26 ENTRY(cpu_arm7_dcache_clean_area)
27                 mov     pc, lr
28
29 /*
30  * Function: arm6_7_data_abort ()
31  *
32  * Params  : r2 = address of aborted instruction
33  *         : sp = pointer to registers
34  *
35  * Purpose : obtain information about current aborted instruction
36  *
37  * Returns : r0 = address of abort
38  *         : r1 = FSR
39  */
40
41 ENTRY(cpu_arm7_data_abort)
42         mrc     p15, 0, r1, c5, c0, 0           @ get FSR
43         mrc     p15, 0, r0, c6, c0, 0           @ get FAR
44         ldr     r8, [r0]                        @ read arm instruction
45         tst     r8, #1 << 20                    @ L = 0 -> write?
46         orreq   r1, r1, #1 << 11                @ yes.
47         and     r7, r8, #15 << 24
48         add     pc, pc, r7, lsr #22             @ Now branch to the relevant processing routine
49         nop
50
51 /* 0 */ b       .data_unknown
52 /* 1 */ mov     pc, lr                          @ swp
53 /* 2 */ b       .data_unknown
54 /* 3 */ b       .data_unknown
55 /* 4 */ b       .data_arm_lateldrpostconst      @ ldr   rd, [rn], #m
56 /* 5 */ b       .data_arm_lateldrpreconst       @ ldr   rd, [rn, #m]
57 /* 6 */ b       .data_arm_lateldrpostreg        @ ldr   rd, [rn], rm
58 /* 7 */ b       .data_arm_lateldrprereg         @ ldr   rd, [rn, rm]
59 /* 8 */ b       .data_arm_ldmstm                @ ldm*a rn, <rlist>
60 /* 9 */ b       .data_arm_ldmstm                @ ldm*b rn, <rlist>
61 /* a */ b       .data_unknown
62 /* b */ b       .data_unknown
63 /* c */ mov     pc, lr                          @ ldc   rd, [rn], #m    @ Same as ldr   rd, [rn], #m
64 /* d */ mov     pc, lr                          @ ldc   rd, [rn, #m]
65 /* e */ b       .data_unknown
66 /* f */
67 .data_unknown:  @ Part of jumptable
68         mov     r0, r2
69         mov     r1, r8
70         mov     r2, sp
71         bl      baddataabort
72         b       ret_from_exception
73
74 ENTRY(cpu_arm6_data_abort)
75         mrc     p15, 0, r1, c5, c0, 0           @ get FSR
76         mrc     p15, 0, r0, c6, c0, 0           @ get FAR
77         ldr     r8, [r2]                        @ read arm instruction
78         tst     r8, #1 << 20                    @ L = 0 -> write?
79         orreq   r1, r1, #1 << 11                @ yes.
80         and     r7, r8, #14 << 24
81         teq     r7, #8 << 24                    @ was it ldm/stm
82         movne   pc, lr
83
84 .data_arm_ldmstm:
85         tst     r8, #1 << 21                    @ check writeback bit
86         moveq   pc, lr                          @ no writeback -> no fixup
87         mov     r7, #0x11
88         orr     r7, r7, #0x1100
89         and     r6, r8, r7
90         and     r2, r8, r7, lsl #1
91         add     r6, r6, r2, lsr #1
92         and     r2, r8, r7, lsl #2
93         add     r6, r6, r2, lsr #2
94         and     r2, r8, r7, lsl #3
95         add     r6, r6, r2, lsr #3
96         add     r6, r6, r6, lsr #8
97         add     r6, r6, r6, lsr #4
98         and     r6, r6, #15                     @ r6 = no. of registers to transfer.
99         and     r5, r8, #15 << 16               @ Extract 'n' from instruction
100         ldr     r7, [sp, r5, lsr #14]           @ Get register 'Rn'
101         tst     r8, #1 << 23                    @ Check U bit
102         subne   r7, r7, r6, lsl #2              @ Undo increment
103         addeq   r7, r7, r6, lsl #2              @ Undo decrement
104         str     r7, [sp, r5, lsr #14]           @ Put register 'Rn'
105         mov     pc, lr
106
107 .data_arm_apply_r6_and_rn:
108         and     r5, r8, #15 << 16               @ Extract 'n' from instruction
109         ldr     r7, [sp, r5, lsr #14]           @ Get register 'Rn'
110         tst     r8, #1 << 23                    @ Check U bit
111         subne   r7, r7, r6                      @ Undo incrmenet
112         addeq   r7, r7, r6                      @ Undo decrement
113         str     r7, [sp, r5, lsr #14]           @ Put register 'Rn'
114         mov     pc, lr
115
116 .data_arm_lateldrpreconst:
117         tst     r8, #1 << 21                    @ check writeback bit
118         moveq   pc, lr                          @ no writeback -> no fixup
119 .data_arm_lateldrpostconst:
120         movs    r2, r8, lsl #20                 @ Get offset
121         moveq   pc, lr                          @ zero -> no fixup
122         and     r5, r8, #15 << 16               @ Extract 'n' from instruction
123         ldr     r7, [sp, r5, lsr #14]           @ Get register 'Rn'
124         tst     r8, #1 << 23                    @ Check U bit
125         subne   r7, r7, r2, lsr #20             @ Undo increment
126         addeq   r7, r7, r2, lsr #20             @ Undo decrement
127         str     r7, [sp, r5, lsr #14]           @ Put register 'Rn'
128         mov     pc, lr
129
130 .data_arm_lateldrprereg:
131         tst     r8, #1 << 21                    @ check writeback bit
132         moveq   pc, lr                          @ no writeback -> no fixup
133 .data_arm_lateldrpostreg:
134         and     r7, r8, #15                     @ Extract 'm' from instruction
135         ldr     r6, [sp, r7, lsl #2]            @ Get register 'Rm'
136         mov     r5, r8, lsr #7                  @ get shift count
137         ands    r5, r5, #31
138         and     r7, r8, #0x70                   @ get shift type
139         orreq   r7, r7, #8                      @ shift count = 0
140         add     pc, pc, r7
141         nop
142
143         mov     r6, r6, lsl r5                  @ 0: LSL #!0
144         b       .data_arm_apply_r6_and_rn
145         b       .data_arm_apply_r6_and_rn       @ 1: LSL #0
146         nop
147         b       .data_unknown                   @ 2: MUL?
148         nop
149         b       .data_unknown                   @ 3: MUL?
150         nop
151         mov     r6, r6, lsr r5                  @ 4: LSR #!0
152         b       .data_arm_apply_r6_and_rn
153         mov     r6, r6, lsr #32                 @ 5: LSR #32
154         b       .data_arm_apply_r6_and_rn
155         b       .data_unknown                   @ 6: MUL?
156         nop
157         b       .data_unknown                   @ 7: MUL?
158         nop
159         mov     r6, r6, asr r5                  @ 8: ASR #!0
160         b       .data_arm_apply_r6_and_rn
161         mov     r6, r6, asr #32                 @ 9: ASR #32
162         b       .data_arm_apply_r6_and_rn
163         b       .data_unknown                   @ A: MUL?
164         nop
165         b       .data_unknown                   @ B: MUL?
166         nop
167         mov     r6, r6, ror r5                  @ C: ROR #!0
168         b       .data_arm_apply_r6_and_rn
169         mov     r6, r6, rrx                     @ D: RRX
170         b       .data_arm_apply_r6_and_rn
171         b       .data_unknown                   @ E: MUL?
172         nop
173         b       .data_unknown                   @ F: MUL?
174
175 /*
176  * Function: arm6_7_proc_init (void)
177  *         : arm6_7_proc_fin (void)
178  *
179  * Notes   : This processor does not require these
180  */
181 ENTRY(cpu_arm6_proc_init)
182 ENTRY(cpu_arm7_proc_init)
183                 mov     pc, lr
184
185 ENTRY(cpu_arm6_proc_fin)
186 ENTRY(cpu_arm7_proc_fin)
187                 mov     r0, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
188                 msr     cpsr_c, r0
189                 mov     r0, #0x31                       @ ....S..DP...M
190                 mcr     p15, 0, r0, c1, c0, 0           @ disable caches
191                 mov     pc, lr
192
193 ENTRY(cpu_arm6_do_idle)
194 ENTRY(cpu_arm7_do_idle)
195                 mov     pc, lr
196
197 /*
198  * Function: arm6_7_switch_mm(unsigned long pgd_phys)
199  * Params  : pgd_phys   Physical address of page table
200  * Purpose : Perform a task switch, saving the old processes state, and restoring
201  *           the new.
202  */
203 ENTRY(cpu_arm6_switch_mm)
204 ENTRY(cpu_arm7_switch_mm)
205 #ifdef CONFIG_MMU
206                 mov     r1, #0
207                 mcr     p15, 0, r1, c7, c0, 0           @ flush cache
208                 mcr     p15, 0, r0, c2, c0, 0           @ update page table ptr
209                 mcr     p15, 0, r1, c5, c0, 0           @ flush TLBs
210 #endif
211                 mov     pc, lr
212
213 /*
214  * Function: arm6_7_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext)
215  * Params  : r0 = Address to set
216  *         : r1 = value to set
217  * Purpose : Set a PTE and flush it out of any WB cache
218  */
219         .align  5
220 ENTRY(cpu_arm6_set_pte_ext)
221 ENTRY(cpu_arm7_set_pte_ext)
222 #ifdef CONFIG_MMU
223         armv3_set_pte_ext wc_disable=0
224 #endif /* CONFIG_MMU */
225         mov     pc, lr
226
227 /*
228  * Function: _arm6_7_reset
229  * Params  : r0 = address to jump to
230  * Notes   : This sets up everything for a reset
231  */
232 ENTRY(cpu_arm6_reset)
233 ENTRY(cpu_arm7_reset)
234                 mov     r1, #0
235                 mcr     p15, 0, r1, c7, c0, 0           @ flush cache
236 #ifdef CONFIG_MMU
237                 mcr     p15, 0, r1, c5, c0, 0           @ flush TLB
238 #endif
239                 mov     r1, #0x30
240                 mcr     p15, 0, r1, c1, c0, 0           @ turn off MMU etc
241                 mov     pc, r0
242
243                 __INIT
244
245                 .type   __arm6_setup, #function
246 __arm6_setup:   mov     r0, #0
247                 mcr     p15, 0, r0, c7, c0              @ flush caches on v3
248 #ifdef CONFIG_MMU
249                 mcr     p15, 0, r0, c5, c0              @ flush TLBs on v3
250                 mov     r0, #0x3d                       @ . ..RS BLDP WCAM
251                 orr     r0, r0, #0x100                  @ . ..01 0011 1101
252 #else
253                 mov     r0, #0x3c                       @ . ..RS BLDP WCA.
254 #endif
255                 mov     pc, lr
256                 .size   __arm6_setup, . - __arm6_setup
257
258                 .type   __arm7_setup, #function
259 __arm7_setup:   mov     r0, #0
260                 mcr     p15, 0, r0, c7, c0              @ flush caches on v3
261 #ifdef CONFIG_MMU
262                 mcr     p15, 0, r0, c5, c0              @ flush TLBs on v3
263                 mcr     p15, 0, r0, c3, c0              @ load domain access register
264                 mov     r0, #0x7d                       @ . ..RS BLDP WCAM
265                 orr     r0, r0, #0x100                  @ . ..01 0111 1101
266 #else
267                 mov     r0, #0x7c                       @ . ..RS BLDP WCA.
268 #endif
269                 mov     pc, lr
270                 .size   __arm7_setup, . - __arm7_setup
271
272                 __INITDATA
273
274 /*
275  * Purpose : Function pointers used to access above functions - all calls
276  *           come through these
277  */
278                 .type   arm6_processor_functions, #object
279 ENTRY(arm6_processor_functions)
280                 .word   cpu_arm6_data_abort
281                 .word   pabort_noifar
282                 .word   cpu_arm6_proc_init
283                 .word   cpu_arm6_proc_fin
284                 .word   cpu_arm6_reset
285                 .word   cpu_arm6_do_idle
286                 .word   cpu_arm6_dcache_clean_area
287                 .word   cpu_arm6_switch_mm
288                 .word   cpu_arm6_set_pte_ext
289                 .size   arm6_processor_functions, . - arm6_processor_functions
290
291 /*
292  * Purpose : Function pointers used to access above functions - all calls
293  *           come through these
294  */
295                 .type   arm7_processor_functions, #object
296 ENTRY(arm7_processor_functions)
297                 .word   cpu_arm7_data_abort
298                 .word   pabort_noifar
299                 .word   cpu_arm7_proc_init
300                 .word   cpu_arm7_proc_fin
301                 .word   cpu_arm7_reset
302                 .word   cpu_arm7_do_idle
303                 .word   cpu_arm7_dcache_clean_area
304                 .word   cpu_arm7_switch_mm
305                 .word   cpu_arm7_set_pte_ext
306                 .size   arm7_processor_functions, . - arm7_processor_functions
307
308                 .section ".rodata"
309
310                 .type   cpu_arch_name, #object
311 cpu_arch_name:  .asciz  "armv3"
312                 .size   cpu_arch_name, . - cpu_arch_name
313
314                 .type   cpu_elf_name, #object
315 cpu_elf_name:   .asciz  "v3"
316                 .size   cpu_elf_name, . - cpu_elf_name
317
318                 .type   cpu_arm6_name, #object
319 cpu_arm6_name:  .asciz  "ARM6"
320                 .size   cpu_arm6_name, . - cpu_arm6_name
321
322                 .type   cpu_arm610_name, #object
323 cpu_arm610_name:
324                 .asciz  "ARM610"
325                 .size   cpu_arm610_name, . - cpu_arm610_name
326
327                 .type   cpu_arm7_name, #object
328 cpu_arm7_name:  .asciz  "ARM7"
329                 .size   cpu_arm7_name, . - cpu_arm7_name
330
331                 .type   cpu_arm710_name, #object
332 cpu_arm710_name:
333                 .asciz  "ARM710"
334                 .size   cpu_arm710_name, . - cpu_arm710_name
335
336                 .align
337
338                 .section ".proc.info.init", #alloc, #execinstr
339
340                 .type   __arm6_proc_info, #object
341 __arm6_proc_info:
342                 .long   0x41560600
343                 .long   0xfffffff0
344                 .long   0x00000c1e
345                 .long   PMD_TYPE_SECT | \
346                         PMD_BIT4 | \
347                         PMD_SECT_AP_WRITE | \
348                         PMD_SECT_AP_READ
349                 b       __arm6_setup
350                 .long   cpu_arch_name
351                 .long   cpu_elf_name
352                 .long   HWCAP_SWP | HWCAP_26BIT
353                 .long   cpu_arm6_name
354                 .long   arm6_processor_functions
355                 .long   v3_tlb_fns
356                 .long   v3_user_fns
357                 .long   v3_cache_fns
358                 .size   __arm6_proc_info, . - __arm6_proc_info
359
360                 .type   __arm610_proc_info, #object
361 __arm610_proc_info:
362                 .long   0x41560610
363                 .long   0xfffffff0
364                 .long   0x00000c1e
365                 .long   PMD_TYPE_SECT | \
366                         PMD_BIT4 | \
367                         PMD_SECT_AP_WRITE | \
368                         PMD_SECT_AP_READ
369                 b       __arm6_setup
370                 .long   cpu_arch_name
371                 .long   cpu_elf_name
372                 .long   HWCAP_SWP | HWCAP_26BIT
373                 .long   cpu_arm610_name
374                 .long   arm6_processor_functions
375                 .long   v3_tlb_fns
376                 .long   v3_user_fns
377                 .long   v3_cache_fns
378                 .size   __arm610_proc_info, . - __arm610_proc_info
379
380                 .type   __arm7_proc_info, #object
381 __arm7_proc_info:
382                 .long   0x41007000
383                 .long   0xffffff00
384                 .long   0x00000c1e
385                 .long   PMD_TYPE_SECT | \
386                         PMD_BIT4 | \
387                         PMD_SECT_AP_WRITE | \
388                         PMD_SECT_AP_READ
389                 b       __arm7_setup
390                 .long   cpu_arch_name
391                 .long   cpu_elf_name
392                 .long   HWCAP_SWP | HWCAP_26BIT
393                 .long   cpu_arm7_name
394                 .long   arm7_processor_functions
395                 .long   v3_tlb_fns
396                 .long   v3_user_fns
397                 .long   v3_cache_fns
398                 .size   __arm7_proc_info, . - __arm7_proc_info
399
400                 .type   __arm710_proc_info, #object
401 __arm710_proc_info:
402                 .long   0x41007100
403                 .long   0xfff8ff00
404                 .long   PMD_TYPE_SECT | \
405                         PMD_SECT_BUFFERABLE | \
406                         PMD_SECT_CACHEABLE | \
407                         PMD_BIT4 | \
408                         PMD_SECT_AP_WRITE | \
409                         PMD_SECT_AP_READ
410                 .long   PMD_TYPE_SECT | \
411                         PMD_BIT4 | \
412                         PMD_SECT_AP_WRITE | \
413                         PMD_SECT_AP_READ
414                 b       __arm7_setup
415                 .long   cpu_arch_name
416                 .long   cpu_elf_name
417                 .long   HWCAP_SWP | HWCAP_26BIT
418                 .long   cpu_arm710_name
419                 .long   arm7_processor_functions
420                 .long   v3_tlb_fns
421                 .long   v3_user_fns
422                 .long   v3_cache_fns
423                 .size   __arm710_proc_info, . - __arm710_proc_info