1708da82da96c127267b8edc59f916a0bec6a286
[linux-2.6.git] / arch / arm / mm / mmu.c
1 /*
2  *  linux/arch/arm/mm/mmu.c
3  *
4  *  Copyright (C) 1995-2005 Russell King
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  */
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/errno.h>
13 #include <linux/init.h>
14 #include <linux/bootmem.h>
15 #include <linux/mman.h>
16 #include <linux/nodemask.h>
17
18 #include <asm/cputype.h>
19 #include <asm/mach-types.h>
20 #include <asm/sections.h>
21 #include <asm/cachetype.h>
22 #include <asm/setup.h>
23 #include <asm/sizes.h>
24 #include <asm/smp_plat.h>
25 #include <asm/tlb.h>
26 #include <asm/highmem.h>
27
28 #include <asm/mach/arch.h>
29 #include <asm/mach/map.h>
30
31 #include "mm.h"
32
33 DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
34
35 /*
36  * empty_zero_page is a special page that is used for
37  * zero-initialized data and COW.
38  */
39 struct page *empty_zero_page;
40 EXPORT_SYMBOL(empty_zero_page);
41
42 /*
43  * The pmd table for the upper-most set of pages.
44  */
45 pmd_t *top_pmd;
46
47 #define CPOLICY_UNCACHED        0
48 #define CPOLICY_BUFFERED        1
49 #define CPOLICY_WRITETHROUGH    2
50 #define CPOLICY_WRITEBACK       3
51 #define CPOLICY_WRITEALLOC      4
52
53 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
54 static unsigned int ecc_mask __initdata = 0;
55 pgprot_t pgprot_user;
56 pgprot_t pgprot_kernel;
57
58 EXPORT_SYMBOL(pgprot_user);
59 EXPORT_SYMBOL(pgprot_kernel);
60
61 struct cachepolicy {
62         const char      policy[16];
63         unsigned int    cr_mask;
64         unsigned int    pmd;
65         unsigned int    pte;
66 };
67
68 static struct cachepolicy cache_policies[] __initdata = {
69         {
70                 .policy         = "uncached",
71                 .cr_mask        = CR_W|CR_C,
72                 .pmd            = PMD_SECT_UNCACHED,
73                 .pte            = L_PTE_MT_UNCACHED,
74         }, {
75                 .policy         = "buffered",
76                 .cr_mask        = CR_C,
77                 .pmd            = PMD_SECT_BUFFERED,
78                 .pte            = L_PTE_MT_BUFFERABLE,
79         }, {
80                 .policy         = "writethrough",
81                 .cr_mask        = 0,
82                 .pmd            = PMD_SECT_WT,
83                 .pte            = L_PTE_MT_WRITETHROUGH,
84         }, {
85                 .policy         = "writeback",
86                 .cr_mask        = 0,
87                 .pmd            = PMD_SECT_WB,
88                 .pte            = L_PTE_MT_WRITEBACK,
89         }, {
90                 .policy         = "writealloc",
91                 .cr_mask        = 0,
92                 .pmd            = PMD_SECT_WBWA,
93                 .pte            = L_PTE_MT_WRITEALLOC,
94         }
95 };
96
97 /*
98  * These are useful for identifying cache coherency
99  * problems by allowing the cache or the cache and
100  * writebuffer to be turned off.  (Note: the write
101  * buffer should not be on and the cache off).
102  */
103 static void __init early_cachepolicy(char **p)
104 {
105         int i;
106
107         for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
108                 int len = strlen(cache_policies[i].policy);
109
110                 if (memcmp(*p, cache_policies[i].policy, len) == 0) {
111                         cachepolicy = i;
112                         cr_alignment &= ~cache_policies[i].cr_mask;
113                         cr_no_alignment &= ~cache_policies[i].cr_mask;
114                         *p += len;
115                         break;
116                 }
117         }
118         if (i == ARRAY_SIZE(cache_policies))
119                 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
120         /*
121          * This restriction is partly to do with the way we boot; it is
122          * unpredictable to have memory mapped using two different sets of
123          * memory attributes (shared, type, and cache attribs).  We can not
124          * change these attributes once the initial assembly has setup the
125          * page tables.
126          */
127         if (cpu_architecture() >= CPU_ARCH_ARMv6) {
128                 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
129                 cachepolicy = CPOLICY_WRITEBACK;
130         }
131         flush_cache_all();
132         set_cr(cr_alignment);
133 }
134 __early_param("cachepolicy=", early_cachepolicy);
135
136 static void __init early_nocache(char **__unused)
137 {
138         char *p = "buffered";
139         printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
140         early_cachepolicy(&p);
141 }
142 __early_param("nocache", early_nocache);
143
144 static void __init early_nowrite(char **__unused)
145 {
146         char *p = "uncached";
147         printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
148         early_cachepolicy(&p);
149 }
150 __early_param("nowb", early_nowrite);
151
152 static void __init early_ecc(char **p)
153 {
154         if (memcmp(*p, "on", 2) == 0) {
155                 ecc_mask = PMD_PROTECTION;
156                 *p += 2;
157         } else if (memcmp(*p, "off", 3) == 0) {
158                 ecc_mask = 0;
159                 *p += 3;
160         }
161 }
162 __early_param("ecc=", early_ecc);
163
164 static int __init noalign_setup(char *__unused)
165 {
166         cr_alignment &= ~CR_A;
167         cr_no_alignment &= ~CR_A;
168         set_cr(cr_alignment);
169         return 1;
170 }
171 __setup("noalign", noalign_setup);
172
173 #ifndef CONFIG_SMP
174 void adjust_cr(unsigned long mask, unsigned long set)
175 {
176         unsigned long flags;
177
178         mask &= ~CR_A;
179
180         set &= mask;
181
182         local_irq_save(flags);
183
184         cr_no_alignment = (cr_no_alignment & ~mask) | set;
185         cr_alignment = (cr_alignment & ~mask) | set;
186
187         set_cr((get_cr() & ~mask) | set);
188
189         local_irq_restore(flags);
190 }
191 #endif
192
193 #define PROT_PTE_DEVICE         L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_WRITE
194 #define PROT_SECT_DEVICE        PMD_TYPE_SECT|PMD_SECT_AP_WRITE
195
196 static struct mem_type mem_types[] = {
197         [MT_DEVICE] = {           /* Strongly ordered / ARMv6 shared device */
198                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
199                                   L_PTE_SHARED,
200                 .prot_l1        = PMD_TYPE_TABLE,
201                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_S,
202                 .domain         = DOMAIN_IO,
203         },
204         [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
205                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
206                 .prot_l1        = PMD_TYPE_TABLE,
207                 .prot_sect      = PROT_SECT_DEVICE,
208                 .domain         = DOMAIN_IO,
209         },
210         [MT_DEVICE_CACHED] = {    /* ioremap_cached */
211                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
212                 .prot_l1        = PMD_TYPE_TABLE,
213                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_WB,
214                 .domain         = DOMAIN_IO,
215         },      
216         [MT_DEVICE_WC] = {      /* ioremap_wc */
217                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
218                 .prot_l1        = PMD_TYPE_TABLE,
219                 .prot_sect      = PROT_SECT_DEVICE,
220                 .domain         = DOMAIN_IO,
221         },
222         [MT_UNCACHED] = {
223                 .prot_pte       = PROT_PTE_DEVICE,
224                 .prot_l1        = PMD_TYPE_TABLE,
225                 .prot_sect      = PMD_TYPE_SECT | PMD_SECT_XN,
226                 .domain         = DOMAIN_IO,
227         },
228         [MT_CACHECLEAN] = {
229                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
230                 .domain    = DOMAIN_KERNEL,
231         },
232         [MT_MINICLEAN] = {
233                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
234                 .domain    = DOMAIN_KERNEL,
235         },
236         [MT_LOW_VECTORS] = {
237                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
238                                 L_PTE_EXEC,
239                 .prot_l1   = PMD_TYPE_TABLE,
240                 .domain    = DOMAIN_USER,
241         },
242         [MT_HIGH_VECTORS] = {
243                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
244                                 L_PTE_USER | L_PTE_EXEC,
245                 .prot_l1   = PMD_TYPE_TABLE,
246                 .domain    = DOMAIN_USER,
247         },
248         [MT_MEMORY] = {
249                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
250                 .domain    = DOMAIN_KERNEL,
251         },
252         [MT_ROM] = {
253                 .prot_sect = PMD_TYPE_SECT,
254                 .domain    = DOMAIN_KERNEL,
255         },
256         [MT_MEMORY_NONCACHED] = {
257                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
258                 .domain    = DOMAIN_KERNEL,
259         },
260 };
261
262 const struct mem_type *get_mem_type(unsigned int type)
263 {
264         return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
265 }
266 EXPORT_SYMBOL(get_mem_type);
267
268 /*
269  * Adjust the PMD section entries according to the CPU in use.
270  */
271 static void __init build_mem_type_table(void)
272 {
273         struct cachepolicy *cp;
274         unsigned int cr = get_cr();
275         unsigned int user_pgprot, kern_pgprot, vecs_pgprot;
276         int cpu_arch = cpu_architecture();
277         int i;
278
279         if (cpu_arch < CPU_ARCH_ARMv6) {
280 #if defined(CONFIG_CPU_DCACHE_DISABLE)
281                 if (cachepolicy > CPOLICY_BUFFERED)
282                         cachepolicy = CPOLICY_BUFFERED;
283 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
284                 if (cachepolicy > CPOLICY_WRITETHROUGH)
285                         cachepolicy = CPOLICY_WRITETHROUGH;
286 #endif
287         }
288         if (cpu_arch < CPU_ARCH_ARMv5) {
289                 if (cachepolicy >= CPOLICY_WRITEALLOC)
290                         cachepolicy = CPOLICY_WRITEBACK;
291                 ecc_mask = 0;
292         }
293 #ifdef CONFIG_SMP
294         cachepolicy = CPOLICY_WRITEALLOC;
295 #endif
296
297         /*
298          * Strip out features not present on earlier architectures.
299          * Pre-ARMv5 CPUs don't have TEX bits.  Pre-ARMv6 CPUs or those
300          * without extended page tables don't have the 'Shared' bit.
301          */
302         if (cpu_arch < CPU_ARCH_ARMv5)
303                 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
304                         mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
305         if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
306                 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
307                         mem_types[i].prot_sect &= ~PMD_SECT_S;
308
309         /*
310          * ARMv5 and lower, bit 4 must be set for page tables (was: cache
311          * "update-able on write" bit on ARM610).  However, Xscale and
312          * Xscale3 require this bit to be cleared.
313          */
314         if (cpu_is_xscale() || cpu_is_xsc3()) {
315                 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
316                         mem_types[i].prot_sect &= ~PMD_BIT4;
317                         mem_types[i].prot_l1 &= ~PMD_BIT4;
318                 }
319         } else if (cpu_arch < CPU_ARCH_ARMv6) {
320                 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
321                         if (mem_types[i].prot_l1)
322                                 mem_types[i].prot_l1 |= PMD_BIT4;
323                         if (mem_types[i].prot_sect)
324                                 mem_types[i].prot_sect |= PMD_BIT4;
325                 }
326         }
327
328         /*
329          * Mark the device areas according to the CPU/architecture.
330          */
331         if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
332                 if (!cpu_is_xsc3()) {
333                         /*
334                          * Mark device regions on ARMv6+ as execute-never
335                          * to prevent speculative instruction fetches.
336                          */
337                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
338                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
339                         mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
340                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
341                 }
342                 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
343                         /*
344                          * For ARMv7 with TEX remapping,
345                          * - shared device is SXCB=1100
346                          * - nonshared device is SXCB=0100
347                          * - write combine device mem is SXCB=0001
348                          * (Uncached Normal memory)
349                          */
350                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
351                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
352                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
353                 } else if (cpu_is_xsc3()) {
354                         /*
355                          * For Xscale3,
356                          * - shared device is TEXCB=00101
357                          * - nonshared device is TEXCB=01000
358                          * - write combine device mem is TEXCB=00100
359                          * (Inner/Outer Uncacheable in xsc3 parlance)
360                          */
361                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
362                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
363                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
364                 } else {
365                         /*
366                          * For ARMv6 and ARMv7 without TEX remapping,
367                          * - shared device is TEXCB=00001
368                          * - nonshared device is TEXCB=01000
369                          * - write combine device mem is TEXCB=00100
370                          * (Uncached Normal in ARMv6 parlance).
371                          */
372                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
373                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
374                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
375                 }
376         } else {
377                 /*
378                  * On others, write combining is "Uncached/Buffered"
379                  */
380                 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
381         }
382
383         /*
384          * Now deal with the memory-type mappings
385          */
386         cp = &cache_policies[cachepolicy];
387         vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
388
389 #ifndef CONFIG_SMP
390         /*
391          * Only use write-through for non-SMP systems
392          */
393         if (cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
394                 vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;
395 #endif
396
397         /*
398          * Enable CPU-specific coherency if supported.
399          * (Only available on XSC3 at the moment.)
400          */
401         if (arch_is_coherent() && cpu_is_xsc3())
402                 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
403
404         /*
405          * ARMv6 and above have extended page tables.
406          */
407         if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
408                 /*
409                  * Mark cache clean areas and XIP ROM read only
410                  * from SVC mode and no access from userspace.
411                  */
412                 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
413                 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
414                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
415
416 #ifdef CONFIG_SMP
417                 /*
418                  * Mark memory with the "shared" attribute for SMP systems
419                  */
420                 user_pgprot |= L_PTE_SHARED;
421                 kern_pgprot |= L_PTE_SHARED;
422                 vecs_pgprot |= L_PTE_SHARED;
423                 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
424                 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
425 #endif
426         }
427
428         /*
429          * Non-cacheable Normal - intended for memory areas that must
430          * not cause dirty cache line writebacks when used
431          */
432         if (cpu_arch >= CPU_ARCH_ARMv6) {
433                 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
434                         /* Non-cacheable Normal is XCB = 001 */
435                         mem_types[MT_MEMORY_NONCACHED].prot_sect |=
436                                 PMD_SECT_BUFFERED;
437                 } else {
438                         /* For both ARMv6 and non-TEX-remapping ARMv7 */
439                         mem_types[MT_MEMORY_NONCACHED].prot_sect |=
440                                 PMD_SECT_TEX(1);
441                 }
442         } else {
443                 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
444         }
445
446         for (i = 0; i < 16; i++) {
447                 unsigned long v = pgprot_val(protection_map[i]);
448                 protection_map[i] = __pgprot(v | user_pgprot);
449         }
450
451         mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
452         mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
453
454         pgprot_user   = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
455         pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
456                                  L_PTE_DIRTY | L_PTE_WRITE | kern_pgprot);
457
458         mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
459         mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
460         mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
461         mem_types[MT_ROM].prot_sect |= cp->pmd;
462
463         switch (cp->pmd) {
464         case PMD_SECT_WT:
465                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
466                 break;
467         case PMD_SECT_WB:
468         case PMD_SECT_WBWA:
469                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
470                 break;
471         }
472         printk("Memory policy: ECC %sabled, Data cache %s\n",
473                 ecc_mask ? "en" : "dis", cp->policy);
474
475         for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
476                 struct mem_type *t = &mem_types[i];
477                 if (t->prot_l1)
478                         t->prot_l1 |= PMD_DOMAIN(t->domain);
479                 if (t->prot_sect)
480                         t->prot_sect |= PMD_DOMAIN(t->domain);
481         }
482 }
483
484 #define vectors_base()  (vectors_high() ? 0xffff0000 : 0)
485
486 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
487                                   unsigned long end, unsigned long pfn,
488                                   const struct mem_type *type)
489 {
490         pte_t *pte;
491
492         if (pmd_none(*pmd)) {
493                 pte = alloc_bootmem_low_pages(2 * PTRS_PER_PTE * sizeof(pte_t));
494                 __pmd_populate(pmd, __pa(pte) | type->prot_l1);
495         }
496
497         pte = pte_offset_kernel(pmd, addr);
498         do {
499                 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
500                 pfn++;
501         } while (pte++, addr += PAGE_SIZE, addr != end);
502 }
503
504 static void __init alloc_init_section(pgd_t *pgd, unsigned long addr,
505                                       unsigned long end, unsigned long phys,
506                                       const struct mem_type *type)
507 {
508         pmd_t *pmd = pmd_offset(pgd, addr);
509
510         /*
511          * Try a section mapping - end, addr and phys must all be aligned
512          * to a section boundary.  Note that PMDs refer to the individual
513          * L1 entries, whereas PGDs refer to a group of L1 entries making
514          * up one logical pointer to an L2 table.
515          */
516         if (((addr | end | phys) & ~SECTION_MASK) == 0) {
517                 pmd_t *p = pmd;
518
519                 if (addr & SECTION_SIZE)
520                         pmd++;
521
522                 do {
523                         *pmd = __pmd(phys | type->prot_sect);
524                         phys += SECTION_SIZE;
525                 } while (pmd++, addr += SECTION_SIZE, addr != end);
526
527                 flush_pmd_entry(p);
528         } else {
529                 /*
530                  * No need to loop; pte's aren't interested in the
531                  * individual L1 entries.
532                  */
533                 alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type);
534         }
535 }
536
537 static void __init create_36bit_mapping(struct map_desc *md,
538                                         const struct mem_type *type)
539 {
540         unsigned long phys, addr, length, end;
541         pgd_t *pgd;
542
543         addr = md->virtual;
544         phys = (unsigned long)__pfn_to_phys(md->pfn);
545         length = PAGE_ALIGN(md->length);
546
547         if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
548                 printk(KERN_ERR "MM: CPU does not support supersection "
549                        "mapping for 0x%08llx at 0x%08lx\n",
550                        __pfn_to_phys((u64)md->pfn), addr);
551                 return;
552         }
553
554         /* N.B. ARMv6 supersections are only defined to work with domain 0.
555          *      Since domain assignments can in fact be arbitrary, the
556          *      'domain == 0' check below is required to insure that ARMv6
557          *      supersections are only allocated for domain 0 regardless
558          *      of the actual domain assignments in use.
559          */
560         if (type->domain) {
561                 printk(KERN_ERR "MM: invalid domain in supersection "
562                        "mapping for 0x%08llx at 0x%08lx\n",
563                        __pfn_to_phys((u64)md->pfn), addr);
564                 return;
565         }
566
567         if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
568                 printk(KERN_ERR "MM: cannot create mapping for "
569                        "0x%08llx at 0x%08lx invalid alignment\n",
570                        __pfn_to_phys((u64)md->pfn), addr);
571                 return;
572         }
573
574         /*
575          * Shift bits [35:32] of address into bits [23:20] of PMD
576          * (See ARMv6 spec).
577          */
578         phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
579
580         pgd = pgd_offset_k(addr);
581         end = addr + length;
582         do {
583                 pmd_t *pmd = pmd_offset(pgd, addr);
584                 int i;
585
586                 for (i = 0; i < 16; i++)
587                         *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
588
589                 addr += SUPERSECTION_SIZE;
590                 phys += SUPERSECTION_SIZE;
591                 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
592         } while (addr != end);
593 }
594
595 /*
596  * Create the page directory entries and any necessary
597  * page tables for the mapping specified by `md'.  We
598  * are able to cope here with varying sizes and address
599  * offsets, and we take full advantage of sections and
600  * supersections.
601  */
602 void __init create_mapping(struct map_desc *md)
603 {
604         unsigned long phys, addr, length, end;
605         const struct mem_type *type;
606         pgd_t *pgd;
607
608         if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
609                 printk(KERN_WARNING "BUG: not creating mapping for "
610                        "0x%08llx at 0x%08lx in user region\n",
611                        __pfn_to_phys((u64)md->pfn), md->virtual);
612                 return;
613         }
614
615         if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
616             md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
617                 printk(KERN_WARNING "BUG: mapping for 0x%08llx at 0x%08lx "
618                        "overlaps vmalloc space\n",
619                        __pfn_to_phys((u64)md->pfn), md->virtual);
620         }
621
622         type = &mem_types[md->type];
623
624         /*
625          * Catch 36-bit addresses
626          */
627         if (md->pfn >= 0x100000) {
628                 create_36bit_mapping(md, type);
629                 return;
630         }
631
632         addr = md->virtual & PAGE_MASK;
633         phys = (unsigned long)__pfn_to_phys(md->pfn);
634         length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
635
636         if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
637                 printk(KERN_WARNING "BUG: map for 0x%08lx at 0x%08lx can not "
638                        "be mapped using pages, ignoring.\n",
639                        __pfn_to_phys(md->pfn), addr);
640                 return;
641         }
642
643         pgd = pgd_offset_k(addr);
644         end = addr + length;
645         do {
646                 unsigned long next = pgd_addr_end(addr, end);
647
648                 alloc_init_section(pgd, addr, next, phys, type);
649
650                 phys += next - addr;
651                 addr = next;
652         } while (pgd++, addr != end);
653 }
654
655 /*
656  * Create the architecture specific mappings
657  */
658 void __init iotable_init(struct map_desc *io_desc, int nr)
659 {
660         int i;
661
662         for (i = 0; i < nr; i++)
663                 create_mapping(io_desc + i);
664 }
665
666 static unsigned long __initdata vmalloc_reserve = SZ_128M;
667
668 /*
669  * vmalloc=size forces the vmalloc area to be exactly 'size'
670  * bytes. This can be used to increase (or decrease) the vmalloc
671  * area - the default is 128m.
672  */
673 static void __init early_vmalloc(char **arg)
674 {
675         vmalloc_reserve = memparse(*arg, arg);
676
677         if (vmalloc_reserve < SZ_16M) {
678                 vmalloc_reserve = SZ_16M;
679                 printk(KERN_WARNING
680                         "vmalloc area too small, limiting to %luMB\n",
681                         vmalloc_reserve >> 20);
682         }
683
684         if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
685                 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
686                 printk(KERN_WARNING
687                         "vmalloc area is too big, limiting to %luMB\n",
688                         vmalloc_reserve >> 20);
689         }
690 }
691 __early_param("vmalloc=", early_vmalloc);
692
693 #define VMALLOC_MIN     (void *)(VMALLOC_END - vmalloc_reserve)
694
695 static void __init sanity_check_meminfo(void)
696 {
697         int i, j, highmem = 0;
698
699         for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
700                 struct membank *bank = &meminfo.bank[j];
701                 *bank = meminfo.bank[i];
702
703 #ifdef CONFIG_HIGHMEM
704                 if (__va(bank->start) > VMALLOC_MIN ||
705                     __va(bank->start) < (void *)PAGE_OFFSET)
706                         highmem = 1;
707
708                 bank->highmem = highmem;
709
710                 /*
711                  * Split those memory banks which are partially overlapping
712                  * the vmalloc area greatly simplifying things later.
713                  */
714                 if (__va(bank->start) < VMALLOC_MIN &&
715                     bank->size > VMALLOC_MIN - __va(bank->start)) {
716                         if (meminfo.nr_banks >= NR_BANKS) {
717                                 printk(KERN_CRIT "NR_BANKS too low, "
718                                                  "ignoring high memory\n");
719                         } else {
720                                 memmove(bank + 1, bank,
721                                         (meminfo.nr_banks - i) * sizeof(*bank));
722                                 meminfo.nr_banks++;
723                                 i++;
724                                 bank[1].size -= VMALLOC_MIN - __va(bank->start);
725                                 bank[1].start = __pa(VMALLOC_MIN - 1) + 1;
726                                 bank[1].highmem = highmem = 1;
727                                 j++;
728                         }
729                         bank->size = VMALLOC_MIN - __va(bank->start);
730                 }
731 #else
732                 bank->highmem = highmem;
733
734                 /*
735                  * Check whether this memory bank would entirely overlap
736                  * the vmalloc area.
737                  */
738                 if (__va(bank->start) >= VMALLOC_MIN ||
739                     __va(bank->start) < (void *)PAGE_OFFSET) {
740                         printk(KERN_NOTICE "Ignoring RAM at %.8lx-%.8lx "
741                                "(vmalloc region overlap).\n",
742                                bank->start, bank->start + bank->size - 1);
743                         continue;
744                 }
745
746                 /*
747                  * Check whether this memory bank would partially overlap
748                  * the vmalloc area.
749                  */
750                 if (__va(bank->start + bank->size) > VMALLOC_MIN ||
751                     __va(bank->start + bank->size) < __va(bank->start)) {
752                         unsigned long newsize = VMALLOC_MIN - __va(bank->start);
753                         printk(KERN_NOTICE "Truncating RAM at %.8lx-%.8lx "
754                                "to -%.8lx (vmalloc region overlap).\n",
755                                bank->start, bank->start + bank->size - 1,
756                                bank->start + newsize - 1);
757                         bank->size = newsize;
758                 }
759 #endif
760                 j++;
761         }
762 #ifdef CONFIG_HIGHMEM
763         if (highmem) {
764                 const char *reason = NULL;
765
766                 if (cache_is_vipt_aliasing()) {
767                         /*
768                          * Interactions between kmap and other mappings
769                          * make highmem support with aliasing VIPT caches
770                          * rather difficult.
771                          */
772                         reason = "with VIPT aliasing cache";
773 #ifdef CONFIG_SMP
774                 } else if (tlb_ops_need_broadcast()) {
775                         /*
776                          * kmap_high needs to occasionally flush TLB entries,
777                          * however, if the TLB entries need to be broadcast
778                          * we may deadlock:
779                          *  kmap_high(irqs off)->flush_all_zero_pkmaps->
780                          *  flush_tlb_kernel_range->smp_call_function_many
781                          *   (must not be called with irqs off)
782                          */
783                         reason = "without hardware TLB ops broadcasting";
784 #endif
785                 }
786                 if (reason) {
787                         printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
788                                 reason);
789                         while (j > 0 && meminfo.bank[j - 1].highmem)
790                                 j--;
791                 }
792         }
793 #endif
794         meminfo.nr_banks = j;
795 }
796
797 static inline void prepare_page_table(void)
798 {
799         unsigned long addr;
800
801         /*
802          * Clear out all the mappings below the kernel image.
803          */
804         for (addr = 0; addr < MODULES_VADDR; addr += PGDIR_SIZE)
805                 pmd_clear(pmd_off_k(addr));
806
807 #ifdef CONFIG_XIP_KERNEL
808         /* The XIP kernel is mapped in the module area -- skip over it */
809         addr = ((unsigned long)_etext + PGDIR_SIZE - 1) & PGDIR_MASK;
810 #endif
811         for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE)
812                 pmd_clear(pmd_off_k(addr));
813
814         /*
815          * Clear out all the kernel space mappings, except for the first
816          * memory bank, up to the end of the vmalloc region.
817          */
818         for (addr = __phys_to_virt(bank_phys_end(&meminfo.bank[0]));
819              addr < VMALLOC_END; addr += PGDIR_SIZE)
820                 pmd_clear(pmd_off_k(addr));
821 }
822
823 /*
824  * Reserve the various regions of node 0
825  */
826 void __init reserve_node_zero(pg_data_t *pgdat)
827 {
828         unsigned long res_size = 0;
829
830         /*
831          * Register the kernel text and data with bootmem.
832          * Note that this can only be in node 0.
833          */
834 #ifdef CONFIG_XIP_KERNEL
835         reserve_bootmem_node(pgdat, __pa(_data), _end - _data,
836                         BOOTMEM_DEFAULT);
837 #else
838         reserve_bootmem_node(pgdat, __pa(_stext), _end - _stext,
839                         BOOTMEM_DEFAULT);
840 #endif
841
842         /*
843          * Reserve the page tables.  These are already in use,
844          * and can only be in node 0.
845          */
846         reserve_bootmem_node(pgdat, __pa(swapper_pg_dir),
847                              PTRS_PER_PGD * sizeof(pgd_t), BOOTMEM_DEFAULT);
848
849         /*
850          * Hmm... This should go elsewhere, but we really really need to
851          * stop things allocating the low memory; ideally we need a better
852          * implementation of GFP_DMA which does not assume that DMA-able
853          * memory starts at zero.
854          */
855         if (machine_is_integrator() || machine_is_cintegrator())
856                 res_size = __pa(swapper_pg_dir) - PHYS_OFFSET;
857
858         /*
859          * These should likewise go elsewhere.  They pre-reserve the
860          * screen memory region at the start of main system memory.
861          */
862         if (machine_is_edb7211())
863                 res_size = 0x00020000;
864         if (machine_is_p720t())
865                 res_size = 0x00014000;
866
867         /* H1940 and RX3715 need to reserve this for suspend */
868
869         if (machine_is_h1940() || machine_is_rx3715()) {
870                 reserve_bootmem_node(pgdat, 0x30003000, 0x1000,
871                                 BOOTMEM_DEFAULT);
872                 reserve_bootmem_node(pgdat, 0x30081000, 0x1000,
873                                 BOOTMEM_DEFAULT);
874         }
875
876         if (machine_is_palmld() || machine_is_palmtx()) {
877                 reserve_bootmem_node(pgdat, 0xa0000000, 0x1000,
878                                 BOOTMEM_EXCLUSIVE);
879                 reserve_bootmem_node(pgdat, 0xa0200000, 0x1000,
880                                 BOOTMEM_EXCLUSIVE);
881         }
882
883         if (machine_is_treo680() || machine_is_centro()) {
884                 reserve_bootmem_node(pgdat, 0xa0000000, 0x1000,
885                                 BOOTMEM_EXCLUSIVE);
886                 reserve_bootmem_node(pgdat, 0xa2000000, 0x1000,
887                                 BOOTMEM_EXCLUSIVE);
888         }
889
890         if (machine_is_palmt5())
891                 reserve_bootmem_node(pgdat, 0xa0200000, 0x1000,
892                                 BOOTMEM_EXCLUSIVE);
893
894         /*
895          * U300 - This platform family can share physical memory
896          * between two ARM cpus, one running Linux and the other
897          * running another OS.
898          */
899         if (machine_is_u300()) {
900 #ifdef CONFIG_MACH_U300_SINGLE_RAM
901 #if ((CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1) == 1) &&    \
902         CONFIG_MACH_U300_2MB_ALIGNMENT_FIX
903                 res_size = 0x00100000;
904 #endif
905 #endif
906         }
907
908 #ifdef CONFIG_SA1111
909         /*
910          * Because of the SA1111 DMA bug, we want to preserve our
911          * precious DMA-able memory...
912          */
913         res_size = __pa(swapper_pg_dir) - PHYS_OFFSET;
914 #endif
915         if (res_size)
916                 reserve_bootmem_node(pgdat, PHYS_OFFSET, res_size,
917                                 BOOTMEM_DEFAULT);
918 }
919
920 /*
921  * Set up device the mappings.  Since we clear out the page tables for all
922  * mappings above VMALLOC_END, we will remove any debug device mappings.
923  * This means you have to be careful how you debug this function, or any
924  * called function.  This means you can't use any function or debugging
925  * method which may touch any device, otherwise the kernel _will_ crash.
926  */
927 static void __init devicemaps_init(struct machine_desc *mdesc)
928 {
929         struct map_desc map;
930         unsigned long addr;
931         void *vectors;
932
933         /*
934          * Allocate the vector page early.
935          */
936         vectors = alloc_bootmem_low_pages(PAGE_SIZE);
937
938         for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE)
939                 pmd_clear(pmd_off_k(addr));
940
941         /*
942          * Map the kernel if it is XIP.
943          * It is always first in the modulearea.
944          */
945 #ifdef CONFIG_XIP_KERNEL
946         map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
947         map.virtual = MODULES_VADDR;
948         map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
949         map.type = MT_ROM;
950         create_mapping(&map);
951 #endif
952
953         /*
954          * Map the cache flushing regions.
955          */
956 #ifdef FLUSH_BASE
957         map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
958         map.virtual = FLUSH_BASE;
959         map.length = SZ_1M;
960         map.type = MT_CACHECLEAN;
961         create_mapping(&map);
962 #endif
963 #ifdef FLUSH_BASE_MINICACHE
964         map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
965         map.virtual = FLUSH_BASE_MINICACHE;
966         map.length = SZ_1M;
967         map.type = MT_MINICLEAN;
968         create_mapping(&map);
969 #endif
970
971         /*
972          * Create a mapping for the machine vectors at the high-vectors
973          * location (0xffff0000).  If we aren't using high-vectors, also
974          * create a mapping at the low-vectors virtual address.
975          */
976         map.pfn = __phys_to_pfn(virt_to_phys(vectors));
977         map.virtual = 0xffff0000;
978         map.length = PAGE_SIZE;
979         map.type = MT_HIGH_VECTORS;
980         create_mapping(&map);
981
982         if (!vectors_high()) {
983                 map.virtual = 0;
984                 map.type = MT_LOW_VECTORS;
985                 create_mapping(&map);
986         }
987
988         /*
989          * Ask the machine support to map in the statically mapped devices.
990          */
991         if (mdesc->map_io)
992                 mdesc->map_io();
993
994         /*
995          * Finally flush the caches and tlb to ensure that we're in a
996          * consistent state wrt the writebuffer.  This also ensures that
997          * any write-allocated cache lines in the vector page are written
998          * back.  After this point, we can start to touch devices again.
999          */
1000         local_flush_tlb_all();
1001         flush_cache_all();
1002 }
1003
1004 static void __init kmap_init(void)
1005 {
1006 #ifdef CONFIG_HIGHMEM
1007         pmd_t *pmd = pmd_off_k(PKMAP_BASE);
1008         pte_t *pte = alloc_bootmem_low_pages(2 * PTRS_PER_PTE * sizeof(pte_t));
1009         BUG_ON(!pmd_none(*pmd) || !pte);
1010         __pmd_populate(pmd, __pa(pte) | _PAGE_KERNEL_TABLE);
1011         pkmap_page_table = pte + PTRS_PER_PTE;
1012 #endif
1013 }
1014
1015 /*
1016  * paging_init() sets up the page tables, initialises the zone memory
1017  * maps, and sets up the zero page, bad page and bad page tables.
1018  */
1019 void __init paging_init(struct machine_desc *mdesc)
1020 {
1021         void *zero_page;
1022
1023         build_mem_type_table();
1024         sanity_check_meminfo();
1025         prepare_page_table();
1026         bootmem_init();
1027         devicemaps_init(mdesc);
1028         kmap_init();
1029
1030         top_pmd = pmd_off_k(0xffff0000);
1031
1032         /*
1033          * allocate the zero page.  Note that this always succeeds and
1034          * returns a zeroed result.
1035          */
1036         zero_page = alloc_bootmem_low_pages(PAGE_SIZE);
1037         empty_zero_page = virt_to_page(zero_page);
1038         __flush_dcache_page(NULL, empty_zero_page);
1039 }
1040
1041 /*
1042  * In order to soft-boot, we need to insert a 1:1 mapping in place of
1043  * the user-mode pages.  This will then ensure that we have predictable
1044  * results when turning the mmu off
1045  */
1046 void setup_mm_for_reboot(char mode)
1047 {
1048         unsigned long base_pmdval;
1049         pgd_t *pgd;
1050         int i;
1051
1052         if (current->mm && current->mm->pgd)
1053                 pgd = current->mm->pgd;
1054         else
1055                 pgd = init_mm.pgd;
1056
1057         base_pmdval = PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT;
1058         if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale())
1059                 base_pmdval |= PMD_BIT4;
1060
1061         for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++, pgd++) {
1062                 unsigned long pmdval = (i << PGDIR_SHIFT) | base_pmdval;
1063                 pmd_t *pmd;
1064
1065                 pmd = pmd_off(pgd, i << PGDIR_SHIFT);
1066                 pmd[0] = __pmd(pmdval);
1067                 pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1)));
1068                 flush_pmd_entry(pmd);
1069         }
1070 }