ARM: cache-l2x0: fix L2 maintenance for R3P1_50
[linux-2.6.git] / arch / arm / mm / cache-l2x0.c
1 /*
2  * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support
3  *
4  * Copyright (C) 2007 ARM Limited
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18  */
19 #include <linux/init.h>
20 #include <linux/spinlock.h>
21 #include <linux/io.h>
22
23 #include <asm/cacheflush.h>
24 #include <asm/hardware/cache-l2x0.h>
25
26 #define CACHE_LINE_SIZE         32
27
28 static void __iomem *l2x0_base;
29 static DEFINE_SPINLOCK(l2x0_lock);
30 static uint32_t l2x0_way_mask;  /* Bitmask of active ways */
31 static uint32_t l2x0_size;
32 static u32 l2x0_cache_id;
33 static unsigned int l2x0_sets;
34 static unsigned int l2x0_ways;
35
36 static inline bool is_pl310_rev(int rev)
37 {
38         return (l2x0_cache_id &
39                 (L2X0_CACHE_ID_PART_MASK | L2X0_CACHE_ID_REV_MASK)) ==
40                         (L2X0_CACHE_ID_PART_L310 | rev);
41 }
42
43 static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
44 {
45         /* wait for cache operation by line or way to complete */
46         while (readl_relaxed(reg) & mask)
47                 ;
48 }
49
50 #ifdef CONFIG_CACHE_PL310
51 static inline void cache_wait(void __iomem *reg, unsigned long mask)
52 {
53         /* cache operations by line are atomic on PL310 */
54 }
55 #else
56 #define cache_wait      cache_wait_way
57 #endif
58
59 static inline void cache_sync(void)
60 {
61         void __iomem *base = l2x0_base;
62
63 #ifdef CONFIG_ARM_ERRATA_753970
64         /* write to an unmmapped register */
65         writel_relaxed(0, base + L2X0_DUMMY_REG);
66 #else
67         writel_relaxed(0, base + L2X0_CACHE_SYNC);
68 #endif
69         cache_wait(base + L2X0_CACHE_SYNC, 1);
70 }
71
72 static inline void l2x0_clean_line(unsigned long addr)
73 {
74         void __iomem *base = l2x0_base;
75         cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
76         writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
77 }
78
79 static inline void l2x0_inv_line(unsigned long addr)
80 {
81         void __iomem *base = l2x0_base;
82         cache_wait(base + L2X0_INV_LINE_PA, 1);
83         writel_relaxed(addr, base + L2X0_INV_LINE_PA);
84 }
85
86 #if !defined(CONFIG_TRUSTED_FOUNDATIONS) && \
87         (defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915))
88
89 #define debug_writel(val)       outer_cache.set_debug(val)
90
91 static void l2x0_set_debug(unsigned long val)
92 {
93         writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL);
94 }
95 #else
96 /* Optimised out for non-errata case */
97 static inline void debug_writel(unsigned long val)
98 {
99 }
100
101 #define l2x0_set_debug  NULL
102 #endif
103
104 #ifdef CONFIG_PL310_ERRATA_588369
105 static inline void l2x0_flush_line(unsigned long addr)
106 {
107         void __iomem *base = l2x0_base;
108
109         /* Clean by PA followed by Invalidate by PA */
110         cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
111         writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
112         cache_wait(base + L2X0_INV_LINE_PA, 1);
113         writel_relaxed(addr, base + L2X0_INV_LINE_PA);
114 }
115 #else
116
117 static inline void l2x0_flush_line(unsigned long addr)
118 {
119         void __iomem *base = l2x0_base;
120         cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
121         writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA);
122 }
123 #endif
124
125 static void l2x0_cache_sync(void)
126 {
127         unsigned long flags;
128
129         spin_lock_irqsave(&l2x0_lock, flags);
130         cache_sync();
131         spin_unlock_irqrestore(&l2x0_lock, flags);
132 }
133
134 #ifdef CONFIG_PL310_ERRATA_727915
135 static void l2x0_for_each_set_way(void __iomem *reg)
136 {
137         int set;
138         int way;
139         unsigned long flags;
140
141         for (way = 0; way < l2x0_ways; way++) {
142                 spin_lock_irqsave(&l2x0_lock, flags);
143                 for (set = 0; set < l2x0_sets; set++)
144                         writel_relaxed((way << 28) | (set << 5), reg);
145                 cache_sync();
146                 spin_unlock_irqrestore(&l2x0_lock, flags);
147         }
148 }
149 #endif
150
151 static void __l2x0_flush_all(void)
152 {
153         debug_writel(0x03);
154         writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
155         cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
156         cache_sync();
157         debug_writel(0x00);
158 }
159
160 static void l2x0_flush_all(void)
161 {
162         unsigned long flags;
163
164 #ifdef CONFIG_PL310_ERRATA_727915
165         if (is_pl310_rev(REV_PL310_R2P0) || is_pl310_rev(REV_PL310_R3P1_50)) {
166                 l2x0_for_each_set_way(l2x0_base + L2X0_CLEAN_INV_LINE_IDX);
167                 return;
168         }
169 #endif
170
171         /* clean all ways */
172         spin_lock_irqsave(&l2x0_lock, flags);
173         __l2x0_flush_all();
174         spin_unlock_irqrestore(&l2x0_lock, flags);
175 }
176
177 static void l2x0_clean_all(void)
178 {
179         unsigned long flags;
180
181 #ifdef CONFIG_PL310_ERRATA_727915
182         if (is_pl310_rev(REV_PL310_R2P0) || is_pl310_rev(REV_PL310_R3P1_50)) {
183                 l2x0_for_each_set_way(l2x0_base + L2X0_CLEAN_LINE_IDX);
184                 return;
185         }
186 #endif
187
188         /* clean all ways */
189         spin_lock_irqsave(&l2x0_lock, flags);
190         debug_writel(0x03);
191         writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_WAY);
192         cache_wait_way(l2x0_base + L2X0_CLEAN_WAY, l2x0_way_mask);
193         cache_sync();
194         debug_writel(0x00);
195         spin_unlock_irqrestore(&l2x0_lock, flags);
196 }
197
198 static void l2x0_inv_all(void)
199 {
200         unsigned long flags;
201
202         /* invalidate all ways */
203         spin_lock_irqsave(&l2x0_lock, flags);
204         /* Invalidating when L2 is enabled is a nono */
205         BUG_ON(readl(l2x0_base + L2X0_CTRL) & 1);
206         writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
207         cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
208         cache_sync();
209         spin_unlock_irqrestore(&l2x0_lock, flags);
210 }
211
212 static void l2x0_inv_range(unsigned long start, unsigned long end)
213 {
214         void __iomem *base = l2x0_base;
215         unsigned long flags;
216
217         spin_lock_irqsave(&l2x0_lock, flags);
218         if (start & (CACHE_LINE_SIZE - 1)) {
219                 start &= ~(CACHE_LINE_SIZE - 1);
220                 debug_writel(0x03);
221                 l2x0_flush_line(start);
222                 debug_writel(0x00);
223                 start += CACHE_LINE_SIZE;
224         }
225
226         if (end & (CACHE_LINE_SIZE - 1)) {
227                 end &= ~(CACHE_LINE_SIZE - 1);
228                 debug_writel(0x03);
229                 l2x0_flush_line(end);
230                 debug_writel(0x00);
231         }
232
233         while (start < end) {
234                 unsigned long blk_end = start + min(end - start, 4096UL);
235
236                 while (start < blk_end) {
237                         l2x0_inv_line(start);
238                         start += CACHE_LINE_SIZE;
239                 }
240
241                 if (blk_end < end) {
242                         spin_unlock_irqrestore(&l2x0_lock, flags);
243                         spin_lock_irqsave(&l2x0_lock, flags);
244                 }
245         }
246         cache_wait(base + L2X0_INV_LINE_PA, 1);
247         cache_sync();
248         spin_unlock_irqrestore(&l2x0_lock, flags);
249 }
250
251 static void l2x0_clean_range(unsigned long start, unsigned long end)
252 {
253         void __iomem *base = l2x0_base;
254         unsigned long flags;
255
256         if ((end - start) >= l2x0_size) {
257                 l2x0_clean_all();
258                 return;
259         }
260
261         spin_lock_irqsave(&l2x0_lock, flags);
262         start &= ~(CACHE_LINE_SIZE - 1);
263         while (start < end) {
264                 unsigned long blk_end = start + min(end - start, 4096UL);
265
266                 while (start < blk_end) {
267                         l2x0_clean_line(start);
268                         start += CACHE_LINE_SIZE;
269                 }
270
271                 if (blk_end < end) {
272                         spin_unlock_irqrestore(&l2x0_lock, flags);
273                         spin_lock_irqsave(&l2x0_lock, flags);
274                 }
275         }
276         cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
277         cache_sync();
278         spin_unlock_irqrestore(&l2x0_lock, flags);
279 }
280
281 static void l2x0_flush_range(unsigned long start, unsigned long end)
282 {
283         void __iomem *base = l2x0_base;
284         unsigned long flags;
285
286         if ((end - start) >= l2x0_size) {
287                 l2x0_flush_all();
288                 return;
289         }
290
291         spin_lock_irqsave(&l2x0_lock, flags);
292         start &= ~(CACHE_LINE_SIZE - 1);
293         while (start < end) {
294                 unsigned long blk_end = start + min(end - start, 4096UL);
295
296                 debug_writel(0x03);
297                 while (start < blk_end) {
298                         l2x0_flush_line(start);
299                         start += CACHE_LINE_SIZE;
300                 }
301                 debug_writel(0x00);
302
303                 if (blk_end < end) {
304                         spin_unlock_irqrestore(&l2x0_lock, flags);
305                         spin_lock_irqsave(&l2x0_lock, flags);
306                 }
307         }
308         cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
309         cache_sync();
310         spin_unlock_irqrestore(&l2x0_lock, flags);
311 }
312
313 /* enables l2x0 after l2x0_disable, does not invalidate */
314 void l2x0_enable(void)
315 {
316         unsigned long flags;
317
318         spin_lock_irqsave(&l2x0_lock, flags);
319         writel_relaxed(1, l2x0_base + L2X0_CTRL);
320         spin_unlock_irqrestore(&l2x0_lock, flags);
321 }
322
323 static void l2x0_disable(void)
324 {
325         unsigned long flags;
326
327         spin_lock_irqsave(&l2x0_lock, flags);
328         __l2x0_flush_all();
329         writel_relaxed(0, l2x0_base + L2X0_CTRL);
330         dsb();
331         spin_unlock_irqrestore(&l2x0_lock, flags);
332 }
333
334 static void __init l2x0_unlock(__u32 cache_id)
335 {
336         int lockregs;
337         int i;
338
339         cache_id &= L2X0_CACHE_ID_PART_MASK;
340
341         if (cache_id == L2X0_CACHE_ID_PART_L310)
342                 lockregs = 8;
343         else
344                 /* L210 and unknown types */
345                 lockregs = 1;
346
347         for (i = 0; i < lockregs; i++) {
348                 writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
349                                i * L2X0_LOCKDOWN_STRIDE);
350                 writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
351                                i * L2X0_LOCKDOWN_STRIDE);
352         }
353 }
354
355 void l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
356 {
357         __u32 aux;
358         __u32 way_size = 0;
359         const char *type;
360
361         l2x0_base = base;
362
363         l2x0_cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
364         aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
365
366         aux &= aux_mask;
367         aux |= aux_val;
368
369         /* Determine the number of ways */
370         switch (l2x0_cache_id & L2X0_CACHE_ID_PART_MASK) {
371         case L2X0_CACHE_ID_PART_L310:
372                 if (aux & (1 << 16))
373                         l2x0_ways = 16;
374                 else
375                         l2x0_ways = 8;
376                 type = "L310";
377                 break;
378         case L2X0_CACHE_ID_PART_L210:
379                 l2x0_ways = (aux >> 13) & 0xf;
380                 type = "L210";
381                 break;
382         default:
383                 /* Assume unknown chips have 8 ways */
384                 l2x0_ways = 8;
385                 type = "L2x0 series";
386                 break;
387         }
388
389         l2x0_way_mask = (1 << l2x0_ways) - 1;
390
391         /*
392          * L2 cache Size =  Way size * Number of ways
393          */
394         way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17;
395         way_size = SZ_1K << (way_size + 3);
396         l2x0_size = l2x0_ways * way_size;
397         l2x0_sets = way_size / CACHE_LINE_SIZE;
398
399         /*
400          * Check if l2x0 controller is already enabled.
401          * If you are booting from non-secure mode
402          * accessing the below registers will fault.
403          */
404         if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
405                 /* Make sure that I&D is not locked down when starting */
406                 l2x0_unlock(l2x0_cache_id);
407
408                 /* l2x0 controller is disabled */
409                 writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL);
410
411                 l2x0_inv_all();
412
413                 /* enable L2X0 */
414                 writel_relaxed(1, l2x0_base + L2X0_CTRL);
415         }
416
417         outer_cache.inv_range = l2x0_inv_range;
418         outer_cache.clean_range = l2x0_clean_range;
419         outer_cache.flush_range = l2x0_flush_range;
420         outer_cache.sync = l2x0_cache_sync;
421         outer_cache.flush_all = l2x0_flush_all;
422         outer_cache.clean_all = l2x0_clean_all;
423         outer_cache.inv_all = l2x0_inv_all;
424         outer_cache.disable = l2x0_disable;
425         outer_cache.set_debug = l2x0_set_debug;
426
427         pr_info_once("%s cache controller enabled\n", type);
428         pr_info_once("l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
429                         l2x0_ways, l2x0_cache_id, aux, l2x0_size);
430 }