0336d47c5dd42b8702d970e885c460f364dc7d91
[linux-2.6.git] / arch / arm / mm / cache-l2x0.c
1 /*
2  * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support
3  *
4  * Copyright (C) 2007 ARM Limited
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18  */
19 #include <linux/init.h>
20 #include <linux/spinlock.h>
21 #include <linux/io.h>
22
23 #include <asm/cacheflush.h>
24 #include <asm/hardware/cache-l2x0.h>
25
26 #define CACHE_LINE_SIZE         32
27
28 static void __iomem *l2x0_base;
29 static DEFINE_SPINLOCK(l2x0_lock);
30 static uint32_t l2x0_way_mask;  /* Bitmask of active ways */
31 static uint32_t l2x0_size;
32 static u32 l2x0_cache_id;
33 static unsigned int l2x0_sets;
34 static unsigned int l2x0_ways;
35
36 static inline bool is_pl310_rev(int rev)
37 {
38         return (l2x0_cache_id &
39                 (L2X0_CACHE_ID_PART_MASK | L2X0_CACHE_ID_REV_MASK)) ==
40                         (L2X0_CACHE_ID_PART_L310 | rev);
41 }
42
43 static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
44 {
45         /* wait for cache operation by line or way to complete */
46         while (readl_relaxed(reg) & mask)
47                 ;
48 }
49
50 #ifdef CONFIG_CACHE_PL310
51 static inline void cache_wait(void __iomem *reg, unsigned long mask)
52 {
53         /* cache operations by line are atomic on PL310 */
54 }
55 #else
56 #define cache_wait      cache_wait_way
57 #endif
58
59 static inline void cache_sync(void)
60 {
61         void __iomem *base = l2x0_base;
62
63 #ifdef CONFIG_ARM_ERRATA_753970
64         /* write to an unmmapped register */
65         writel_relaxed(0, base + L2X0_DUMMY_REG);
66 #else
67         writel_relaxed(0, base + L2X0_CACHE_SYNC);
68 #endif
69         cache_wait(base + L2X0_CACHE_SYNC, 1);
70 }
71
72 static inline void l2x0_clean_line(unsigned long addr)
73 {
74         void __iomem *base = l2x0_base;
75         cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
76         writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
77 }
78
79 static inline void l2x0_inv_line(unsigned long addr)
80 {
81         void __iomem *base = l2x0_base;
82         cache_wait(base + L2X0_INV_LINE_PA, 1);
83         writel_relaxed(addr, base + L2X0_INV_LINE_PA);
84 }
85
86 #if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
87
88 #define debug_writel(val)       outer_cache.set_debug(val)
89
90 static void l2x0_set_debug(unsigned long val)
91 {
92         writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL);
93 }
94 #else
95 /* Optimised out for non-errata case */
96 static inline void debug_writel(unsigned long val)
97 {
98 }
99
100 #define l2x0_set_debug  NULL
101 #endif
102
103 #ifdef CONFIG_PL310_ERRATA_588369
104 static inline void l2x0_flush_line(unsigned long addr)
105 {
106         void __iomem *base = l2x0_base;
107
108         /* Clean by PA followed by Invalidate by PA */
109         cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
110         writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
111         cache_wait(base + L2X0_INV_LINE_PA, 1);
112         writel_relaxed(addr, base + L2X0_INV_LINE_PA);
113 }
114 #else
115
116 static inline void l2x0_flush_line(unsigned long addr)
117 {
118         void __iomem *base = l2x0_base;
119         cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
120         writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA);
121 }
122 #endif
123
124 static void l2x0_cache_sync(void)
125 {
126         unsigned long flags;
127
128         spin_lock_irqsave(&l2x0_lock, flags);
129         cache_sync();
130         spin_unlock_irqrestore(&l2x0_lock, flags);
131 }
132
133 #ifdef CONFIG_PL310_ERRATA_727915
134 static void l2x0_for_each_set_way(void __iomem *reg)
135 {
136         int set;
137         int way;
138         unsigned long flags;
139
140         for (way = 0; way < l2x0_ways; way++) {
141                 spin_lock_irqsave(&l2x0_lock, flags);
142                 for (set = 0; set < l2x0_sets; set++)
143                         writel_relaxed((way << 28) | (set << 5), reg);
144                 cache_sync();
145                 spin_unlock_irqrestore(&l2x0_lock, flags);
146         }
147 }
148 #endif
149
150 static void __l2x0_flush_all(void)
151 {
152         debug_writel(0x03);
153         writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
154         cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
155         cache_sync();
156         debug_writel(0x00);
157 }
158
159 static void l2x0_flush_all(void)
160 {
161         unsigned long flags;
162
163 #ifdef CONFIG_PL310_ERRATA_727915
164         if (is_pl310_rev(REV_PL310_R2P0)) {
165                 l2x0_for_each_set_way(l2x0_base + L2X0_CLEAN_INV_LINE_IDX);
166                 return;
167         }
168 #endif
169
170         /* clean all ways */
171         spin_lock_irqsave(&l2x0_lock, flags);
172         __l2x0_flush_all();
173         spin_unlock_irqrestore(&l2x0_lock, flags);
174 }
175
176 static void l2x0_clean_all(void)
177 {
178         unsigned long flags;
179
180 #ifdef CONFIG_PL310_ERRATA_727915
181         if (is_pl310_rev(REV_PL310_R2P0)) {
182                 l2x0_for_each_set_way(l2x0_base + L2X0_CLEAN_LINE_IDX);
183                 return;
184         }
185 #endif
186
187         /* clean all ways */
188         spin_lock_irqsave(&l2x0_lock, flags);
189         debug_writel(0x03);
190         writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_WAY);
191         cache_wait_way(l2x0_base + L2X0_CLEAN_WAY, l2x0_way_mask);
192         cache_sync();
193         debug_writel(0x00);
194         spin_unlock_irqrestore(&l2x0_lock, flags);
195 }
196
197 static void l2x0_inv_all(void)
198 {
199         unsigned long flags;
200
201         /* invalidate all ways */
202         spin_lock_irqsave(&l2x0_lock, flags);
203         /* Invalidating when L2 is enabled is a nono */
204         BUG_ON(readl(l2x0_base + L2X0_CTRL) & 1);
205         writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
206         cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
207         cache_sync();
208         spin_unlock_irqrestore(&l2x0_lock, flags);
209 }
210
211 static void l2x0_inv_range(unsigned long start, unsigned long end)
212 {
213         void __iomem *base = l2x0_base;
214         unsigned long flags;
215
216         spin_lock_irqsave(&l2x0_lock, flags);
217         if (start & (CACHE_LINE_SIZE - 1)) {
218                 start &= ~(CACHE_LINE_SIZE - 1);
219                 debug_writel(0x03);
220                 l2x0_flush_line(start);
221                 debug_writel(0x00);
222                 start += CACHE_LINE_SIZE;
223         }
224
225         if (end & (CACHE_LINE_SIZE - 1)) {
226                 end &= ~(CACHE_LINE_SIZE - 1);
227                 debug_writel(0x03);
228                 l2x0_flush_line(end);
229                 debug_writel(0x00);
230         }
231
232         while (start < end) {
233                 unsigned long blk_end = start + min(end - start, 4096UL);
234
235                 while (start < blk_end) {
236                         l2x0_inv_line(start);
237                         start += CACHE_LINE_SIZE;
238                 }
239
240                 if (blk_end < end) {
241                         spin_unlock_irqrestore(&l2x0_lock, flags);
242                         spin_lock_irqsave(&l2x0_lock, flags);
243                 }
244         }
245         cache_wait(base + L2X0_INV_LINE_PA, 1);
246         cache_sync();
247         spin_unlock_irqrestore(&l2x0_lock, flags);
248 }
249
250 static void l2x0_clean_range(unsigned long start, unsigned long end)
251 {
252         void __iomem *base = l2x0_base;
253         unsigned long flags;
254
255         if ((end - start) >= l2x0_size) {
256                 l2x0_clean_all();
257                 return;
258         }
259
260         spin_lock_irqsave(&l2x0_lock, flags);
261         start &= ~(CACHE_LINE_SIZE - 1);
262         while (start < end) {
263                 unsigned long blk_end = start + min(end - start, 4096UL);
264
265                 while (start < blk_end) {
266                         l2x0_clean_line(start);
267                         start += CACHE_LINE_SIZE;
268                 }
269
270                 if (blk_end < end) {
271                         spin_unlock_irqrestore(&l2x0_lock, flags);
272                         spin_lock_irqsave(&l2x0_lock, flags);
273                 }
274         }
275         cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
276         cache_sync();
277         spin_unlock_irqrestore(&l2x0_lock, flags);
278 }
279
280 static void l2x0_flush_range(unsigned long start, unsigned long end)
281 {
282         void __iomem *base = l2x0_base;
283         unsigned long flags;
284
285         if ((end - start) >= l2x0_size) {
286                 l2x0_flush_all();
287                 return;
288         }
289
290         spin_lock_irqsave(&l2x0_lock, flags);
291         start &= ~(CACHE_LINE_SIZE - 1);
292         while (start < end) {
293                 unsigned long blk_end = start + min(end - start, 4096UL);
294
295                 debug_writel(0x03);
296                 while (start < blk_end) {
297                         l2x0_flush_line(start);
298                         start += CACHE_LINE_SIZE;
299                 }
300                 debug_writel(0x00);
301
302                 if (blk_end < end) {
303                         spin_unlock_irqrestore(&l2x0_lock, flags);
304                         spin_lock_irqsave(&l2x0_lock, flags);
305                 }
306         }
307         cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
308         cache_sync();
309         spin_unlock_irqrestore(&l2x0_lock, flags);
310 }
311
312 /* enables l2x0 after l2x0_disable, does not invalidate */
313 void l2x0_enable(void)
314 {
315         unsigned long flags;
316
317         spin_lock_irqsave(&l2x0_lock, flags);
318         writel_relaxed(1, l2x0_base + L2X0_CTRL);
319         spin_unlock_irqrestore(&l2x0_lock, flags);
320 }
321
322 static void l2x0_disable(void)
323 {
324         unsigned long flags;
325
326         spin_lock_irqsave(&l2x0_lock, flags);
327         __l2x0_flush_all();
328         writel_relaxed(0, l2x0_base + L2X0_CTRL);
329         dsb();
330         spin_unlock_irqrestore(&l2x0_lock, flags);
331 }
332
333 static void __init l2x0_unlock(__u32 cache_id)
334 {
335         int lockregs;
336         int i;
337
338         cache_id &= L2X0_CACHE_ID_PART_MASK;
339
340         if (cache_id == L2X0_CACHE_ID_PART_L310)
341                 lockregs = 8;
342         else
343                 /* L210 and unknown types */
344                 lockregs = 1;
345
346         for (i = 0; i < lockregs; i++) {
347                 writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
348                                i * L2X0_LOCKDOWN_STRIDE);
349                 writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
350                                i * L2X0_LOCKDOWN_STRIDE);
351         }
352 }
353
354 void l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
355 {
356         __u32 aux;
357         __u32 way_size = 0;
358         const char *type;
359
360         l2x0_base = base;
361
362         l2x0_cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
363         aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
364
365         aux &= aux_mask;
366         aux |= aux_val;
367
368         /* Determine the number of ways */
369         switch (l2x0_cache_id & L2X0_CACHE_ID_PART_MASK) {
370         case L2X0_CACHE_ID_PART_L310:
371                 if (aux & (1 << 16))
372                         l2x0_ways = 16;
373                 else
374                         l2x0_ways = 8;
375                 type = "L310";
376                 break;
377         case L2X0_CACHE_ID_PART_L210:
378                 l2x0_ways = (aux >> 13) & 0xf;
379                 type = "L210";
380                 break;
381         default:
382                 /* Assume unknown chips have 8 ways */
383                 l2x0_ways = 8;
384                 type = "L2x0 series";
385                 break;
386         }
387
388         l2x0_way_mask = (1 << l2x0_ways) - 1;
389
390         /*
391          * L2 cache Size =  Way size * Number of ways
392          */
393         way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17;
394         way_size = SZ_1K << (way_size + 3);
395         l2x0_size = l2x0_ways * way_size;
396         l2x0_sets = way_size / CACHE_LINE_SIZE;
397
398         /*
399          * Check if l2x0 controller is already enabled.
400          * If you are booting from non-secure mode
401          * accessing the below registers will fault.
402          */
403         if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
404                 /* Make sure that I&D is not locked down when starting */
405                 l2x0_unlock(l2x0_cache_id);
406
407                 /* l2x0 controller is disabled */
408                 writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL);
409
410                 l2x0_inv_all();
411
412                 /* enable L2X0 */
413                 writel_relaxed(1, l2x0_base + L2X0_CTRL);
414         }
415
416         outer_cache.inv_range = l2x0_inv_range;
417         outer_cache.clean_range = l2x0_clean_range;
418         outer_cache.flush_range = l2x0_flush_range;
419         outer_cache.sync = l2x0_cache_sync;
420         outer_cache.flush_all = l2x0_flush_all;
421         outer_cache.clean_all = l2x0_clean_all;
422         outer_cache.inv_all = l2x0_inv_all;
423         outer_cache.disable = l2x0_disable;
424         outer_cache.set_debug = l2x0_set_debug;
425
426         pr_info_once("%s cache controller enabled\n", type);
427         pr_info_once("l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
428                         l2x0_ways, l2x0_cache_id, aux, l2x0_size);
429 }