arch/arm/mm/alignment.c

   1 /*
   2  *  linux/arch/arm/mm/alignment.c
   3  *
   4  *  Copyright (C) 1995  Linus Torvalds
   5  *  Modifications for ARM processor (c) 1995-2001 Russell King
   6  *  Thumb alignment fault fixups (c) 2004 MontaVista Software, Inc.
   7  *  - Adapted from gdb/sim/arm/thumbemu.c -- Thumb instruction emulation.
   8  *    Copyright (C) 1996, Cygnus Software Technologies Ltd.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14 #include <linux/moduleparam.h>
  15 #include <linux/compiler.h>
  16 #include <linux/kernel.h>
  17 #include <linux/errno.h>
  18 #include <linux/string.h>
  19 #include <linux/proc_fs.h>
  20 #include <linux/init.h>
  21 #include <linux/sched.h>
  22 #include <linux/uaccess.h>
  23
  24 #include <asm/unaligned.h>
  25
  26 #include "fault.h"
  27
  28 /*
  29  * 32-bit misaligned trap handler (c) 1998 San Mehat (CCC) -July 1998
  30  * /proc/sys/debug/alignment, modified and integrated into
  31  * Linux 2.1 by Russell King
  32  *
  33  * Speed optimisations and better fault handling by Russell King.
  34  *
  35  * *** NOTE ***
  36  * This code is not portable to processors with late data abort handling.
  37  */
  38 #define CODING_BITS(i)  (i & 0x0e000000)
  39
  40 #define LDST_I_BIT(i)   (i & (1 << 26))         /* Immediate constant   */
  41 #define LDST_P_BIT(i)   (i & (1 << 24))         /* Preindex             */
  42 #define LDST_U_BIT(i)   (i & (1 << 23))         /* Add offset           */
  43 #define LDST_W_BIT(i)   (i & (1 << 21))         /* Writeback            */
  44 #define LDST_L_BIT(i)   (i & (1 << 20))         /* Load                 */
  45
  46 #define LDST_P_EQ_U(i)  ((((i) ^ ((i) >> 1)) & (1 << 23)) == 0)
  47
  48 #define LDSTHD_I_BIT(i) (i & (1 << 22))         /* double/half-word immed */
  49 #define LDM_S_BIT(i)    (i & (1 << 22))         /* write CPSR from SPSR */
  50
  51 #define RN_BITS(i)      ((i >> 16) & 15)        /* Rn                   */
  52 #define RD_BITS(i)      ((i >> 12) & 15)        /* Rd                   */
  53 #define RM_BITS(i)      (i & 15)                /* Rm                   */
  54
  55 #define REGMASK_BITS(i) (i & 0xffff)
  56 #define OFFSET_BITS(i)  (i & 0x0fff)
  57
  58 #define IS_SHIFT(i)     (i & 0x0ff0)
  59 #define SHIFT_BITS(i)   ((i >> 7) & 0x1f)
  60 #define SHIFT_TYPE(i)   (i & 0x60)
  61 #define SHIFT_LSL       0x00
  62 #define SHIFT_LSR       0x20
  63 #define SHIFT_ASR       0x40
  64 #define SHIFT_RORRRX    0x60
  65
  66 #define BAD_INSTR       0xdeadc0de
  67
  68 /* Thumb-2 32 bit format per ARMv7 DDI0406A A6.3, either f800h,e800h,f800h */
  69 #define IS_T32(hi16) \
  70         (((hi16) & 0xe000) == 0xe000 && ((hi16) & 0x1800))
  71
  72 static unsigned long ai_user;
  73 static unsigned long ai_sys;
  74 static unsigned long ai_skipped;
  75 static unsigned long ai_half;
  76 static unsigned long ai_word;
  77 static unsigned long ai_dword;
  78 static unsigned long ai_multi;
  79 static int ai_usermode;
  80
  81 core_param(alignment, ai_usermode, int, 0600);
  82
  83 #define UM_WARN         (1 << 0)
  84 #define UM_FIXUP        (1 << 1)
  85 #define UM_SIGNAL       (1 << 2)
  86
  87 #ifdef CONFIG_PROC_FS
  88 static const char *usermode_action[] = {
  89         "ignored",
  90         "warn",
  91         "fixup",
  92         "fixup+warn",
  93         "signal",
  94         "signal+warn"
  95 };
  96
  97 static int
  98 proc_alignment_read(char *page, char **start, off_t off, int count, int *eof,
  99                     void *data)
 100 {
 101         char *p = page;
 102         int len;
 103
 104         p += sprintf(p, "User:\t\t%lu\n", ai_user);
 105         p += sprintf(p, "System:\t\t%lu\n", ai_sys);
 106         p += sprintf(p, "Skipped:\t%lu\n", ai_skipped);
 107         p += sprintf(p, "Half:\t\t%lu\n", ai_half);
 108         p += sprintf(p, "Word:\t\t%lu\n", ai_word);
 109         if (cpu_architecture() >= CPU_ARCH_ARMv5TE)
 110                 p += sprintf(p, "DWord:\t\t%lu\n", ai_dword);
 111         p += sprintf(p, "Multi:\t\t%lu\n", ai_multi);
 112         p += sprintf(p, "User faults:\t%i (%s)\n", ai_usermode,
 113                         usermode_action[ai_usermode]);
 114
 115         len = (p - page) - off;
 116         if (len < 0)
 117                 len = 0;
 118
 119         *eof = (len <= count) ? 1 : 0;
 120         *start = page + off;
 121
 122         return len;
 123 }
 124
 125 static int proc_alignment_write(struct file *file, const char __user *buffer,
 126                                 unsigned long count, void *data)
 127 {
 128         char mode;
 129
 130         if (count > 0) {
 131                 if (get_user(mode, buffer))
 132                         return -EFAULT;
 133                 if (mode >= '0' && mode <= '5')
 134                         ai_usermode = mode - '0';
 135         }
 136         return count;
 137 }
 138
 139 #endif /* CONFIG_PROC_FS */
 140
 141 union offset_union {
 142         unsigned long un;
 143           signed long sn;
 144 };
 145
 146 #define TYPE_ERROR      0
 147 #define TYPE_FAULT      1
 148 #define TYPE_LDST       2
 149 #define TYPE_DONE       3
 150
 151 #ifdef __ARMEB__
 152 #define BE              1
 153 #define FIRST_BYTE_16   "mov    %1, %1, ror #8\n"
 154 #define FIRST_BYTE_32   "mov    %1, %1, ror #24\n"
 155 #define NEXT_BYTE       "ror #24"
 156 #else
 157 #define BE              0
 158 #define FIRST_BYTE_16
 159 #define FIRST_BYTE_32
 160 #define NEXT_BYTE       "lsr #8"
 161 #endif
 162
 163 #define __get8_unaligned_check(ins,val,addr,err)        \
 164         __asm__(                                        \
 165  ARM(   "1:     "ins"   %1, [%2], #1\n" )               \
 166  THUMB( "1:     "ins"   %1, [%2]\n"     )               \
 167  THUMB( "       add     %2, %2, #1\n"   )               \
 168         "2:\n"                                          \
 169         "       .section .fixup,\"ax\"\n"               \
 170         "       .align  2\n"                            \
 171         "3:     mov     %0, #1\n"                       \
 172         "       b       2b\n"                           \
 173         "       .previous\n"                            \
 174         "       .section __ex_table,\"a\"\n"            \
 175         "       .align  3\n"                            \
 176         "       .long   1b, 3b\n"                       \
 177         "       .previous\n"                            \
 178         : "=r" (err), "=&r" (val), "=r" (addr)          \
 179         : "0" (err), "2" (addr))
 180
 181 #define __get16_unaligned_check(ins,val,addr)                   \
 182         do {                                                    \
 183                 unsigned int err = 0, v, a = addr;              \
 184                 __get8_unaligned_check(ins,v,a,err);            \
 185                 val =  v << ((BE) ? 8 : 0);                     \
 186                 __get8_unaligned_check(ins,v,a,err);            \
 187                 val |= v << ((BE) ? 0 : 8);                     \
 188                 if (err)                                        \
 189                         goto fault;                             \
 190         } while (0)
 191
 192 #define get16_unaligned_check(val,addr) \
 193         __get16_unaligned_check("ldrb",val,addr)
 194
 195 #define get16t_unaligned_check(val,addr) \
 196         __get16_unaligned_check("ldrbt",val,addr)
 197
 198 #define __get32_unaligned_check(ins,val,addr)                   \
 199         do {                                                    \
 200                 unsigned int err = 0, v, a = addr;              \
 201                 __get8_unaligned_check(ins,v,a,err);            \
 202                 val =  v << ((BE) ? 24 :  0);                   \
 203                 __get8_unaligned_check(ins,v,a,err);            \
 204                 val |= v << ((BE) ? 16 :  8);                   \
 205                 __get8_unaligned_check(ins,v,a,err);            \
 206                 val |= v << ((BE) ?  8 : 16);                   \
 207                 __get8_unaligned_check(ins,v,a,err);            \
 208                 val |= v << ((BE) ?  0 : 24);                   \
 209                 if (err)                                        \
 210                         goto fault;                             \
 211         } while (0)
 212
 213 #define get32_unaligned_check(val,addr) \
 214         __get32_unaligned_check("ldrb",val,addr)
 215
 216 #define get32t_unaligned_check(val,addr) \
 217         __get32_unaligned_check("ldrbt",val,addr)
 218
 219 #define __put16_unaligned_check(ins,val,addr)                   \
 220         do {                                                    \
 221                 unsigned int err = 0, v = val, a = addr;        \
 222                 __asm__( FIRST_BYTE_16                          \
 223          ARM(   "1:     "ins"   %1, [%2], #1\n" )               \
 224          THUMB( "1:     "ins"   %1, [%2]\n"     )               \
 225          THUMB( "       add     %2, %2, #1\n"   )               \
 226                 "       mov     %1, %1, "NEXT_BYTE"\n"          \
 227                 "2:     "ins"   %1, [%2]\n"                     \
 228                 "3:\n"                                          \
 229                 "       .section .fixup,\"ax\"\n"               \
 230                 "       .align  2\n"                            \
 231                 "4:     mov     %0, #1\n"                       \
 232                 "       b       3b\n"                           \
 233                 "       .previous\n"                            \
 234                 "       .section __ex_table,\"a\"\n"            \
 235                 "       .align  3\n"                            \
 236                 "       .long   1b, 4b\n"                       \
 237                 "       .long   2b, 4b\n"                       \
 238                 "       .previous\n"                            \
 239                 : "=r" (err), "=&r" (v), "=&r" (a)              \
 240                 : "0" (err), "1" (v), "2" (a));                 \
 241                 if (err)                                        \
 242                         goto fault;                             \
 243         } while (0)
 244
 245 #define put16_unaligned_check(val,addr)  \
 246         __put16_unaligned_check("strb",val,addr)
 247
 248 #define put16t_unaligned_check(val,addr) \
 249         __put16_unaligned_check("strbt",val,addr)
 250
 251 #define __put32_unaligned_check(ins,val,addr)                   \
 252         do {                                                    \
 253                 unsigned int err = 0, v = val, a = addr;        \
 254                 __asm__( FIRST_BYTE_32                          \
 255          ARM(   "1:     "ins"   %1, [%2], #1\n" )               \
 256          THUMB( "1:     "ins"   %1, [%2]\n"     )               \
 257          THUMB( "       add     %2, %2, #1\n"   )               \
 258                 "       mov     %1, %1, "NEXT_BYTE"\n"          \
 259          ARM(   "2:     "ins"   %1, [%2], #1\n" )               \
 260          THUMB( "2:     "ins"   %1, [%2]\n"     )               \
 261          THUMB( "       add     %2, %2, #1\n"   )               \
 262                 "       mov     %1, %1, "NEXT_BYTE"\n"          \
 263          ARM(   "3:     "ins"   %1, [%2], #1\n" )               \
 264          THUMB( "3:     "ins"   %1, [%2]\n"     )               \
 265          THUMB( "       add     %2, %2, #1\n"   )               \
 266                 "       mov     %1, %1, "NEXT_BYTE"\n"          \
 267                 "4:     "ins"   %1, [%2]\n"                     \
 268                 "5:\n"                                          \
 269                 "       .section .fixup,\"ax\"\n"               \
 270                 "       .align  2\n"                            \
 271                 "6:     mov     %0, #1\n"                       \
 272                 "       b       5b\n"                           \
 273                 "       .previous\n"                            \
 274                 "       .section __ex_table,\"a\"\n"            \
 275                 "       .align  3\n"                            \
 276                 "       .long   1b, 6b\n"                       \
 277                 "       .long   2b, 6b\n"                       \
 278                 "       .long   3b, 6b\n"                       \
 279                 "       .long   4b, 6b\n"                       \
 280                 "       .previous\n"                            \
 281                 : "=r" (err), "=&r" (v), "=&r" (a)              \
 282                 : "0" (err), "1" (v), "2" (a));                 \
 283                 if (err)                                        \
 284                         goto fault;                             \
 285         } while (0)
 286
 287 #define put32_unaligned_check(val,addr) \
 288         __put32_unaligned_check("strb", val, addr)
 289
 290 #define put32t_unaligned_check(val,addr) \
 291         __put32_unaligned_check("strbt", val, addr)
 292
 293 static void
 294 do_alignment_finish_ldst(unsigned long addr, unsigned long instr, struct pt_regs *regs, union offset_union offset)
 295 {
 296         if (!LDST_U_BIT(instr))
 297                 offset.un = -offset.un;
 298
 299         if (!LDST_P_BIT(instr))
 300                 addr += offset.un;
 301
 302         if (!LDST_P_BIT(instr) || LDST_W_BIT(instr))
 303                 regs->uregs[RN_BITS(instr)] = addr;
 304 }
 305
 306 static int
 307 do_alignment_ldrhstrh(unsigned long addr, unsigned long instr, struct pt_regs *regs)
 308 {
 309         unsigned int rd = RD_BITS(instr);
 310
 311         ai_half += 1;
 312
 313         if (user_mode(regs))
 314                 goto user;
 315
 316         if (LDST_L_BIT(instr)) {
 317                 unsigned long val;
 318                 get16_unaligned_check(val, addr);
 319
 320                 /* signed half-word? */
 321                 if (instr & 0x40)
 322                         val = (signed long)((signed short) val);
 323
 324                 regs->uregs[rd] = val;
 325         } else
 326                 put16_unaligned_check(regs->uregs[rd], addr);
 327
 328         return TYPE_LDST;
 329
 330  user:
 331         if (LDST_L_BIT(instr)) {
 332                 unsigned long val;
 333                 get16t_unaligned_check(val, addr);
 334
 335                 /* signed half-word? */
 336                 if (instr & 0x40)
 337                         val = (signed long)((signed short) val);
 338
 339                 regs->uregs[rd] = val;
 340         } else
 341                 put16t_unaligned_check(regs->uregs[rd], addr);
 342
 343         return TYPE_LDST;
 344
 345  fault:
 346         return TYPE_FAULT;
 347 }
 348
 349 static int
 350 do_alignment_ldrdstrd(unsigned long addr, unsigned long instr,
 351                       struct pt_regs *regs)
 352 {
 353         unsigned int rd = RD_BITS(instr);
 354         unsigned int rd2;
 355         int load;
 356
 357         if ((instr & 0xfe000000) == 0xe8000000) {
 358                 /* ARMv7 Thumb-2 32-bit LDRD/STRD */
 359                 rd2 = (instr >> 8) & 0xf;
 360                 load = !!(LDST_L_BIT(instr));
 361         } else if (((rd & 1) == 1) || (rd == 14))
 362                 goto bad;
 363         else {
 364                 load = ((instr & 0xf0) == 0xd0);
 365                 rd2 = rd + 1;
 366         }
 367
 368         ai_dword += 1;
 369
 370         if (user_mode(regs))
 371                 goto user;
 372
 373         if (load) {
 374                 unsigned long val;
 375                 get32_unaligned_check(val, addr);
 376                 regs->uregs[rd] = val;
 377                 get32_unaligned_check(val, addr + 4);
 378                 regs->uregs[rd2] = val;
 379         } else {
 380                 put32_unaligned_check(regs->uregs[rd], addr);
 381                 put32_unaligned_check(regs->uregs[rd2], addr + 4);
 382         }
 383
 384         return TYPE_LDST;
 385
 386  user:
 387         if (load) {
 388                 unsigned long val;
 389                 get32t_unaligned_check(val, addr);
 390                 regs->uregs[rd] = val;
 391                 get32t_unaligned_check(val, addr + 4);
 392                 regs->uregs[rd2] = val;
 393         } else {
 394                 put32t_unaligned_check(regs->uregs[rd], addr);
 395                 put32t_unaligned_check(regs->uregs[rd2], addr + 4);
 396         }
 397
 398         return TYPE_LDST;
 399  bad:
 400         return TYPE_ERROR;
 401  fault:
 402         return TYPE_FAULT;
 403 }
 404
 405 static int
 406 do_alignment_ldrstr(unsigned long addr, unsigned long instr, struct pt_regs *regs)
 407 {
 408         unsigned int rd = RD_BITS(instr);
 409
 410         ai_word += 1;
 411
 412         if ((!LDST_P_BIT(instr) && LDST_W_BIT(instr)) || user_mode(regs))
 413                 goto trans;
 414
 415         if (LDST_L_BIT(instr)) {
 416                 unsigned int val;
 417                 get32_unaligned_check(val, addr);
 418                 regs->uregs[rd] = val;
 419         } else
 420                 put32_unaligned_check(regs->uregs[rd], addr);
 421         return TYPE_LDST;
 422
 423  trans:
 424         if (LDST_L_BIT(instr)) {
 425                 unsigned int val;
 426                 get32t_unaligned_check(val, addr);
 427                 regs->uregs[rd] = val;
 428         } else
 429                 put32t_unaligned_check(regs->uregs[rd], addr);
 430         return TYPE_LDST;
 431
 432  fault:
 433         return TYPE_FAULT;
 434 }
 435
 436 /*
 437  * LDM/STM alignment handler.
 438  *
 439  * There are 4 variants of this instruction:
 440  *
 441  * B = rn pointer before instruction, A = rn pointer after instruction
 442  *              ------ increasing address ----->
 443  *              |    | r0 | r1 | ... | rx |    |
 444  * PU = 01             B                    A
 445  * PU = 11        B                    A
 446  * PU = 00        A                    B
 447  * PU = 10             A                    B
 448  */
 449 static int
 450 do_alignment_ldmstm(unsigned long addr, unsigned long instr, struct pt_regs *regs)
 451 {
 452         unsigned int rd, rn, correction, nr_regs, regbits;
 453         unsigned long eaddr, newaddr;
 454
 455         if (LDM_S_BIT(instr))
 456                 goto bad;
 457
 458         correction = 4; /* processor implementation defined */
 459         regs->ARM_pc += correction;
 460
 461         ai_multi += 1;
 462
 463         /* count the number of registers in the mask to be transferred */
 464         nr_regs = hweight16(REGMASK_BITS(instr)) * 4;
 465
 466         rn = RN_BITS(instr);
 467         newaddr = eaddr = regs->uregs[rn];
 468
 469         if (!LDST_U_BIT(instr))
 470                 nr_regs = -nr_regs;
 471         newaddr += nr_regs;
 472         if (!LDST_U_BIT(instr))
 473                 eaddr = newaddr;
 474
 475         if (LDST_P_EQ_U(instr)) /* U = P */
 476                 eaddr += 4;
 477
 478         /*
 479          * For alignment faults on the ARM922T/ARM920T the MMU  makes
 480          * the FSR (and hence addr) equal to the updated base address
 481          * of the multiple access rather than the restored value.
 482          * Switch this message off if we've got a ARM92[02], otherwise
 483          * [ls]dm alignment faults are noisy!
 484          */
 485 #if !(defined CONFIG_CPU_ARM922T)  && !(defined CONFIG_CPU_ARM920T)
 486         /*
 487          * This is a "hint" - we already have eaddr worked out by the
 488          * processor for us.
 489          */
 490         if (addr != eaddr) {
 491                 printk(KERN_ERR "LDMSTM: PC = %08lx, instr = %08lx, "
 492                         "addr = %08lx, eaddr = %08lx\n",
 493                          instruction_pointer(regs), instr, addr, eaddr);
 494                 show_regs(regs);
 495         }
 496 #endif
 497
 498         if (user_mode(regs)) {
 499                 for (regbits = REGMASK_BITS(instr), rd = 0; regbits;
 500                      regbits >>= 1, rd += 1)
 501                         if (regbits & 1) {
 502                                 if (LDST_L_BIT(instr)) {
 503                                         unsigned int val;
 504                                         get32t_unaligned_check(val, eaddr);
 505                                         regs->uregs[rd] = val;
 506                                 } else
 507                                         put32t_unaligned_check(regs->uregs[rd], eaddr);
 508                                 eaddr += 4;
 509                         }
 510         } else {
 511                 for (regbits = REGMASK_BITS(instr), rd = 0; regbits;
 512                      regbits >>= 1, rd += 1)
 513                         if (regbits & 1) {
 514                                 if (LDST_L_BIT(instr)) {
 515                                         unsigned int val;
 516                                         get32_unaligned_check(val, eaddr);
 517                                         regs->uregs[rd] = val;
 518                                 } else
 519                                         put32_unaligned_check(regs->uregs[rd], eaddr);
 520                                 eaddr += 4;
 521                         }
 522         }
 523
 524         if (LDST_W_BIT(instr))
 525                 regs->uregs[rn] = newaddr;
 526         if (!LDST_L_BIT(instr) || !(REGMASK_BITS(instr) & (1 << 15)))
 527                 regs->ARM_pc -= correction;
 528         return TYPE_DONE;
 529
 530 fault:
 531         regs->ARM_pc -= correction;
 532         return TYPE_FAULT;
 533
 534 bad:
 535         printk(KERN_ERR "Alignment trap: not handling ldm with s-bit set\n");
 536         return TYPE_ERROR;
 537 }
 538
 539 /*
 540  * Convert Thumb ld/st instruction forms to equivalent ARM instructions so
 541  * we can reuse ARM userland alignment fault fixups for Thumb.
 542  *
 543  * This implementation was initially based on the algorithm found in
 544  * gdb/sim/arm/thumbemu.c. It is basically just a code reduction of same
 545  * to convert only Thumb ld/st instruction forms to equivalent ARM forms.
 546  *
 547  * NOTES:
 548  * 1. Comments below refer to ARM ARM DDI0100E Thumb Instruction sections.
 549  * 2. If for some reason we're passed an non-ld/st Thumb instruction to
 550  *    decode, we return 0xdeadc0de. This should never happen under normal
 551  *    circumstances but if it does, we've got other problems to deal with
 552  *    elsewhere and we obviously can't fix those problems here.
 553  */
 554
 555 static unsigned long
 556 thumb2arm(u16 tinstr)
 557 {
 558         u32 L = (tinstr & (1<<11)) >> 11;
 559
 560         switch ((tinstr & 0xf800) >> 11) {
 561         /* 6.5.1 Format 1: */
 562         case 0x6000 >> 11:                              /* 7.1.52 STR(1) */
 563         case 0x6800 >> 11:                              /* 7.1.26 LDR(1) */
 564         case 0x7000 >> 11:                              /* 7.1.55 STRB(1) */
 565         case 0x7800 >> 11:                              /* 7.1.30 LDRB(1) */
 566                 return 0xe5800000 |
 567                         ((tinstr & (1<<12)) << (22-12)) |       /* fixup */
 568                         (L<<20) |                               /* L==1? */
 569                         ((tinstr & (7<<0)) << (12-0)) |         /* Rd */
 570                         ((tinstr & (7<<3)) << (16-3)) |         /* Rn */
 571                         ((tinstr & (31<<6)) >>                  /* immed_5 */
 572                                 (6 - ((tinstr & (1<<12)) ? 0 : 2)));
 573         case 0x8000 >> 11:                              /* 7.1.57 STRH(1) */
 574         case 0x8800 >> 11:                              /* 7.1.32 LDRH(1) */
 575                 return 0xe1c000b0 |
 576                         (L<<20) |                               /* L==1? */
 577                         ((tinstr & (7<<0)) << (12-0)) |         /* Rd */
 578                         ((tinstr & (7<<3)) << (16-3)) |         /* Rn */
 579                         ((tinstr & (7<<6)) >> (6-1)) |   /* immed_5[2:0] */
 580                         ((tinstr & (3<<9)) >> (9-8));    /* immed_5[4:3] */
 581
 582         /* 6.5.1 Format 2: */
 583         case 0x5000 >> 11:
 584         case 0x5800 >> 11:
 585                 {
 586                         static const u32 subset[8] = {
 587                                 0xe7800000,             /* 7.1.53 STR(2) */
 588                                 0xe18000b0,             /* 7.1.58 STRH(2) */
 589                                 0xe7c00000,             /* 7.1.56 STRB(2) */
 590                                 0xe19000d0,             /* 7.1.34 LDRSB */
 591                                 0xe7900000,             /* 7.1.27 LDR(2) */
 592                                 0xe19000b0,             /* 7.1.33 LDRH(2) */
 593                                 0xe7d00000,             /* 7.1.31 LDRB(2) */
 594                                 0xe19000f0              /* 7.1.35 LDRSH */
 595                         };
 596                         return subset[(tinstr & (7<<9)) >> 9] |
 597                             ((tinstr & (7<<0)) << (12-0)) |     /* Rd */
 598                             ((tinstr & (7<<3)) << (16-3)) |     /* Rn */
 599                             ((tinstr & (7<<6)) >> (6-0));       /* Rm */
 600                 }
 601
 602         /* 6.5.1 Format 3: */
 603         case 0x4800 >> 11:                              /* 7.1.28 LDR(3) */
 604                 /* NOTE: This case is not technically possible. We're
 605                  *       loading 32-bit memory data via PC relative
 606                  *       addressing mode. So we can and should eliminate
 607                  *       this case. But I'll leave it here for now.
 608                  */
 609                 return 0xe59f0000 |
 610                     ((tinstr & (7<<8)) << (12-8)) |             /* Rd */
 611                     ((tinstr & 255) << (2-0));                  /* immed_8 */
 612
 613         /* 6.5.1 Format 4: */
 614         case 0x9000 >> 11:                              /* 7.1.54 STR(3) */
 615         case 0x9800 >> 11:                              /* 7.1.29 LDR(4) */
 616                 return 0xe58d0000 |
 617                         (L<<20) |                               /* L==1? */
 618                         ((tinstr & (7<<8)) << (12-8)) |         /* Rd */
 619                         ((tinstr & 255) << 2);                  /* immed_8 */
 620
 621         /* 6.6.1 Format 1: */
 622         case 0xc000 >> 11:                              /* 7.1.51 STMIA */
 623         case 0xc800 >> 11:                              /* 7.1.25 LDMIA */
 624                 {
 625                         u32 Rn = (tinstr & (7<<8)) >> 8;
 626                         u32 W = ((L<<Rn) & (tinstr&255)) ? 0 : 1<<21;
 627
 628                         return 0xe8800000 | W | (L<<20) | (Rn<<16) |
 629                                 (tinstr&255);
 630                 }
 631
 632         /* 6.6.1 Format 2: */
 633         case 0xb000 >> 11:                              /* 7.1.48 PUSH */
 634         case 0xb800 >> 11:                              /* 7.1.47 POP */
 635                 if ((tinstr & (3 << 9)) == 0x0400) {
 636                         static const u32 subset[4] = {
 637                                 0xe92d0000,     /* STMDB sp!,{registers} */
 638                                 0xe92d4000,     /* STMDB sp!,{registers,lr} */
 639                                 0xe8bd0000,     /* LDMIA sp!,{registers} */
 640                                 0xe8bd8000      /* LDMIA sp!,{registers,pc} */
 641                         };
 642                         return subset[(L<<1) | ((tinstr & (1<<8)) >> 8)] |
 643                             (tinstr & 255);             /* register_list */
 644                 }
 645                 /* Else fall through for illegal instruction case */
 646
 647         default:
 648                 return BAD_INSTR;
 649         }
 650 }
 651
 652 /*
 653  * Convert Thumb-2 32 bit LDM, STM, LDRD, STRD to equivalent instruction
 654  * handlable by ARM alignment handler, also find the corresponding handler,
 655  * so that we can reuse ARM userland alignment fault fixups for Thumb.
 656  *
 657  * @pinstr: original Thumb-2 instruction; returns new handlable instruction
 658  * @regs: register context.
 659  * @poffset: return offset from faulted addr for later writeback
 660  *
 661  * NOTES:
 662  * 1. Comments below refer to ARMv7 DDI0406A Thumb Instruction sections.
 663  * 2. Register name Rt from ARMv7 is same as Rd from ARMv6 (Rd is Rt)
 664  */
 665 static void *
 666 do_alignment_t32_to_handler(unsigned long *pinstr, struct pt_regs *regs,
 667                             union offset_union *poffset)
 668 {
 669         unsigned long instr = *pinstr;
 670         u16 tinst1 = (instr >> 16) & 0xffff;
 671         u16 tinst2 = instr & 0xffff;
 672         poffset->un = 0;
 673
 674         switch (tinst1 & 0xffe0) {
 675         /* A6.3.5 Load/Store multiple */
 676         case 0xe880:            /* STM/STMIA/STMEA,LDM/LDMIA, PUSH/POP T2 */
 677         case 0xe8a0:            /* ...above writeback version */
 678         case 0xe900:            /* STMDB/STMFD, LDMDB/LDMEA */
 679         case 0xe920:            /* ...above writeback version */
 680                 /* no need offset decision since handler calculates it */
 681                 return do_alignment_ldmstm;
 682
 683         case 0xf840:            /* POP/PUSH T3 (single register) */
 684                 if (RN_BITS(instr) == 13 && (tinst2 & 0x09ff) == 0x0904) {
 685                         u32 L = !!(LDST_L_BIT(instr));
 686                         const u32 subset[2] = {
 687                                 0xe92d0000,     /* STMDB sp!,{registers} */
 688                                 0xe8bd0000,     /* LDMIA sp!,{registers} */
 689                         };
 690                         *pinstr = subset[L] | (1<<RD_BITS(instr));
 691                         return do_alignment_ldmstm;
 692                 }
 693                 /* Else fall through for illegal instruction case */
 694                 break;
 695
 696         /* A6.3.6 Load/store double, STRD/LDRD(immed, lit, reg) */
 697         case 0xe860:
 698         case 0xe960:
 699         case 0xe8e0:
 700         case 0xe9e0:
 701                 poffset->un = (tinst2 & 0xff) << 2;
 702         case 0xe940:
 703         case 0xe9c0:
 704                 return do_alignment_ldrdstrd;
 705
 706         /*
 707          * No need to handle load/store instructions up to word size
 708          * since ARMv6 and later CPUs can perform unaligned accesses.
 709          */
 710         default:
 711                 break;
 712         }
 713         return NULL;
 714 }
 715
 716 static int
 717 do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
 718 {
 719         union offset_union offset;
 720         unsigned long instr = 0, instrptr;
 721         int (*handler)(unsigned long addr, unsigned long instr, struct pt_regs *regs);
 722         unsigned int type;
 723         mm_segment_t fs;
 724         unsigned int fault;
 725         u16 tinstr = 0;
 726         int isize = 4;
 727         int thumb2_32b = 0;
 728
 729         instrptr = instruction_pointer(regs);
 730
 731         fs = get_fs();
 732         set_fs(KERNEL_DS);
 733         if (thumb_mode(regs)) {
 734                 fault = __get_user(tinstr, (u16 *)(instrptr & ~1));
 735                 if (!fault) {
 736                         if (cpu_architecture() >= CPU_ARCH_ARMv7 &&
 737                             IS_T32(tinstr)) {
 738                                 /* Thumb-2 32-bit */
 739                                 u16 tinst2 = 0;
 740                                 fault = __get_user(tinst2, (u16 *)(instrptr+2));
 741                                 instr = (tinstr << 16) | tinst2;
 742                                 thumb2_32b = 1;
 743                         } else {
 744                                 isize = 2;
 745                                 instr = thumb2arm(tinstr);
 746                         }
 747                 }
 748         } else
 749                 fault = __get_user(instr, (u32 *)instrptr);
 750         set_fs(fs);
 751
 752         if (fault) {
 753                 type = TYPE_FAULT;
 754                 goto bad_or_fault;
 755         }
 756
 757         if (user_mode(regs))
 758                 goto user;
 759
 760         ai_sys += 1;
 761
 762  fixup:
 763
 764         regs->ARM_pc += isize;
 765
 766         switch (CODING_BITS(instr)) {
 767         case 0x00000000:        /* 3.13.4 load/store instruction extensions */
 768                 if (LDSTHD_I_BIT(instr))
 769                         offset.un = (instr & 0xf00) >> 4 | (instr & 15);
 770                 else
 771                         offset.un = regs->uregs[RM_BITS(instr)];
 772
 773                 if ((instr & 0x000000f0) == 0x000000b0 || /* LDRH, STRH */
 774                     (instr & 0x001000f0) == 0x001000f0)   /* LDRSH */
 775                         handler = do_alignment_ldrhstrh;
 776                 else if ((instr & 0x001000f0) == 0x000000d0 || /* LDRD */
 777                          (instr & 0x001000f0) == 0x000000f0)   /* STRD */
 778                         handler = do_alignment_ldrdstrd;
 779                 else if ((instr & 0x01f00ff0) == 0x01000090) /* SWP */
 780                         goto swp;
 781                 else
 782                         goto bad;
 783                 break;
 784
 785         case 0x04000000:        /* ldr or str immediate */
 786                 offset.un = OFFSET_BITS(instr);
 787                 handler = do_alignment_ldrstr;
 788                 break;
 789
 790         case 0x06000000:        /* ldr or str register */
 791                 offset.un = regs->uregs[RM_BITS(instr)];
 792
 793                 if (IS_SHIFT(instr)) {
 794                         unsigned int shiftval = SHIFT_BITS(instr);
 795
 796                         switch(SHIFT_TYPE(instr)) {
 797                         case SHIFT_LSL:
 798                                 offset.un <<= shiftval;
 799                                 break;
 800
 801                         case SHIFT_LSR:
 802                                 offset.un >>= shiftval;
 803                                 break;
 804
 805                         case SHIFT_ASR:
 806                                 offset.sn >>= shiftval;
 807                                 break;
 808
 809                         case SHIFT_RORRRX:
 810                                 if (shiftval == 0) {
 811                                         offset.un >>= 1;
 812                                         if (regs->ARM_cpsr & PSR_C_BIT)
 813                                                 offset.un |= 1 << 31;
 814                                 } else
 815                                         offset.un = offset.un >> shiftval |
 816                                                           offset.un << (32 - shiftval);
 817                                 break;
 818                         }
 819                 }
 820                 handler = do_alignment_ldrstr;
 821                 break;
 822
 823         case 0x08000000:        /* ldm or stm, or thumb-2 32bit instruction */
 824                 if (thumb2_32b)
 825                         handler = do_alignment_t32_to_handler(&instr, regs, &offset);
 826                 else
 827                         handler = do_alignment_ldmstm;
 828                 break;
 829
 830         default:
 831                 goto bad;
 832         }
 833
 834         if (!handler)
 835                 goto bad;
 836         type = handler(addr, instr, regs);
 837
 838         if (type == TYPE_ERROR || type == TYPE_FAULT) {
 839                 regs->ARM_pc -= isize;
 840                 goto bad_or_fault;
 841         }
 842
 843         if (type == TYPE_LDST)
 844                 do_alignment_finish_ldst(addr, instr, regs, offset);
 845
 846         return 0;
 847
 848  bad_or_fault:
 849         if (type == TYPE_ERROR)
 850                 goto bad;
 851         /*
 852          * We got a fault - fix it up, or die.
 853          */
 854         do_bad_area(addr, fsr, regs);
 855         return 0;
 856
 857  swp:
 858         printk(KERN_ERR "Alignment trap: not handling swp instruction\n");
 859
 860  bad:
 861         /*
 862          * Oops, we didn't handle the instruction.
 863          */
 864         printk(KERN_ERR "Alignment trap: not handling instruction "
 865                 "%0*lx at [<%08lx>]\n",
 866                 isize << 1,
 867                 isize == 2 ? tinstr : instr, instrptr);
 868         ai_skipped += 1;
 869         return 1;
 870
 871  user:
 872         ai_user += 1;
 873
 874         if (ai_usermode & UM_WARN)
 875                 printk("Alignment trap: %s (%d) PC=0x%08lx Instr=0x%0*lx "
 876                        "Address=0x%08lx FSR 0x%03x\n", current->comm,
 877                         task_pid_nr(current), instrptr,
 878                         isize << 1,
 879                         isize == 2 ? tinstr : instr,
 880                         addr, fsr);
 881
 882         if (ai_usermode & UM_FIXUP)
 883                 goto fixup;
 884
 885         if (ai_usermode & UM_SIGNAL)
 886                 force_sig(SIGBUS, current);
 887         else
 888                 set_cr(cr_no_alignment);
 889
 890         return 0;
 891 }
 892
 893 /*
 894  * This needs to be done after sysctl_init, otherwise sys/ will be
 895  * overwritten.  Actually, this shouldn't be in sys/ at all since
 896  * it isn't a sysctl, and it doesn't contain sysctl information.
 897  * We now locate it in /proc/cpu/alignment instead.
 898  */
 899 static int __init alignment_init(void)
 900 {
 901 #ifdef CONFIG_PROC_FS
 902         struct proc_dir_entry *res;
 903
 904         res = proc_mkdir("cpu", NULL);
 905         if (!res)
 906                 return -ENOMEM;
 907
 908         res = create_proc_entry("alignment", S_IWUSR | S_IRUGO, res);
 909         if (!res)
 910                 return -ENOMEM;
 911
 912         res->read_proc = proc_alignment_read;
 913         res->write_proc = proc_alignment_write;
 914 #endif
 915
 916         /*
 917          * ARMv6 and later CPUs can perform unaligned accesses for
 918          * most single load and store instructions up to word size.
 919          * LDM, STM, LDRD and STRD still need to be handled.
 920          *
 921          * Ignoring the alignment fault is not an option on these
 922          * CPUs since we spin re-faulting the instruction without
 923          * making any progress.
 924          */
 925         if (cpu_architecture() >= CPU_ARCH_ARMv6 && (cr_alignment & CR_U)) {
 926                 cr_alignment &= ~CR_A;
 927                 cr_no_alignment &= ~CR_A;
 928                 set_cr(cr_alignment);
 929                 ai_usermode = UM_FIXUP;
 930         }
 931
 932         hook_fault_code(1, do_alignment, SIGILL, "alignment exception");
 933         hook_fault_code(3, do_alignment, SIGILL, "alignment exception");
 934
 935         return 0;
 936 }
 937
 938 fs_initcall(alignment_init);