[ARM] Allow Versatile to be built for AB and PB
[linux-2.6.git] / arch / arm / mach-versatile / core.c
1 /*
2  *  linux/arch/arm/mach-versatile/core.c
3  *
4  *  Copyright (C) 1999 - 2003 ARM Limited
5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
20  */
21 #include <linux/init.h>
22 #include <linux/device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/platform_device.h>
25 #include <linux/sysdev.h>
26 #include <linux/interrupt.h>
27 #include <linux/amba/bus.h>
28 #include <linux/amba/clcd.h>
29
30 #include <asm/system.h>
31 #include <asm/hardware.h>
32 #include <asm/io.h>
33 #include <asm/irq.h>
34 #include <asm/leds.h>
35 #include <asm/hardware/arm_timer.h>
36 #include <asm/hardware/icst307.h>
37 #include <asm/hardware/vic.h>
38 #include <asm/mach-types.h>
39
40 #include <asm/mach/arch.h>
41 #include <asm/mach/flash.h>
42 #include <asm/mach/irq.h>
43 #include <asm/mach/time.h>
44 #include <asm/mach/map.h>
45 #include <asm/mach/mmc.h>
46
47 #include "core.h"
48 #include "clock.h"
49
50 /*
51  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
52  * is the (PA >> 12).
53  *
54  * Setup a VA for the Versatile Vectored Interrupt Controller.
55  */
56 #define __io_address(n)         __io(IO_ADDRESS(n))
57 #define VA_VIC_BASE             __io_address(VERSATILE_VIC_BASE)
58 #define VA_SIC_BASE             __io_address(VERSATILE_SIC_BASE)
59
60 static void sic_mask_irq(unsigned int irq)
61 {
62         irq -= IRQ_SIC_START;
63         writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
64 }
65
66 static void sic_unmask_irq(unsigned int irq)
67 {
68         irq -= IRQ_SIC_START;
69         writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_SET);
70 }
71
72 static struct irqchip sic_chip = {
73         .ack    = sic_mask_irq,
74         .mask   = sic_mask_irq,
75         .unmask = sic_unmask_irq,
76 };
77
78 static void
79 sic_handle_irq(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
80 {
81         unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
82
83         if (status == 0) {
84                 do_bad_IRQ(irq, desc, regs);
85                 return;
86         }
87
88         do {
89                 irq = ffs(status) - 1;
90                 status &= ~(1 << irq);
91
92                 irq += IRQ_SIC_START;
93
94                 desc = irq_desc + irq;
95                 desc_handle_irq(irq, desc, regs);
96         } while (status);
97 }
98
99 #if 1
100 #define IRQ_MMCI0A      IRQ_VICSOURCE22
101 #define IRQ_AACI        IRQ_VICSOURCE24
102 #define IRQ_ETH         IRQ_VICSOURCE25
103 #define PIC_MASK        0xFFD00000
104 #else
105 #define IRQ_MMCI0A      IRQ_SIC_MMCI0A
106 #define IRQ_AACI        IRQ_SIC_AACI
107 #define IRQ_ETH         IRQ_SIC_ETH
108 #define PIC_MASK        0
109 #endif
110
111 void __init versatile_init_irq(void)
112 {
113         unsigned int i;
114
115         vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0);
116
117         set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq);
118
119         /* Do second interrupt controller */
120         writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
121
122         for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
123                 if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) {
124                         set_irq_chip(i, &sic_chip);
125                         set_irq_handler(i, do_level_IRQ);
126                         set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
127                 }
128         }
129
130         /*
131          * Interrupts on secondary controller from 0 to 8 are routed to
132          * source 31 on PIC.
133          * Interrupts from 21 to 31 are routed directly to the VIC on
134          * the corresponding number on primary controller. This is controlled
135          * by setting PIC_ENABLEx.
136          */
137         writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
138 }
139
140 static struct map_desc versatile_io_desc[] __initdata = {
141         {
142                 .virtual        =  IO_ADDRESS(VERSATILE_SYS_BASE),
143                 .pfn            = __phys_to_pfn(VERSATILE_SYS_BASE),
144                 .length         = SZ_4K,
145                 .type           = MT_DEVICE
146         }, {
147                 .virtual        =  IO_ADDRESS(VERSATILE_SIC_BASE),
148                 .pfn            = __phys_to_pfn(VERSATILE_SIC_BASE),
149                 .length         = SZ_4K,
150                 .type           = MT_DEVICE
151         }, {
152                 .virtual        =  IO_ADDRESS(VERSATILE_VIC_BASE),
153                 .pfn            = __phys_to_pfn(VERSATILE_VIC_BASE),
154                 .length         = SZ_4K,
155                 .type           = MT_DEVICE
156         }, {
157                 .virtual        =  IO_ADDRESS(VERSATILE_SCTL_BASE),
158                 .pfn            = __phys_to_pfn(VERSATILE_SCTL_BASE),
159                 .length         = SZ_4K * 9,
160                 .type           = MT_DEVICE
161         },
162 #ifdef CONFIG_MACH_VERSATILE_AB
163         {
164                 .virtual        =  IO_ADDRESS(VERSATILE_GPIO0_BASE),
165                 .pfn            = __phys_to_pfn(VERSATILE_GPIO0_BASE),
166                 .length         = SZ_4K,
167                 .type           = MT_DEVICE
168         }, {
169                 .virtual        =  IO_ADDRESS(VERSATILE_IB2_BASE),
170                 .pfn            = __phys_to_pfn(VERSATILE_IB2_BASE),
171                 .length         = SZ_64M,
172                 .type           = MT_DEVICE
173         },
174 #endif
175 #ifdef CONFIG_DEBUG_LL
176         {
177                 .virtual        =  IO_ADDRESS(VERSATILE_UART0_BASE),
178                 .pfn            = __phys_to_pfn(VERSATILE_UART0_BASE),
179                 .length         = SZ_4K,
180                 .type           = MT_DEVICE
181         },
182 #endif
183 #ifdef CONFIG_PCI
184         {
185                 .virtual        =  IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
186                 .pfn            = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
187                 .length         = SZ_4K,
188                 .type           = MT_DEVICE
189         }, {
190                 .virtual        =  VERSATILE_PCI_VIRT_BASE,
191                 .pfn            = __phys_to_pfn(VERSATILE_PCI_BASE),
192                 .length         = VERSATILE_PCI_BASE_SIZE,
193                 .type           = MT_DEVICE
194         }, {
195                 .virtual        =  VERSATILE_PCI_CFG_VIRT_BASE,
196                 .pfn            = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
197                 .length         = VERSATILE_PCI_CFG_BASE_SIZE,
198                 .type           = MT_DEVICE
199         },
200 #if 0
201         {
202                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE0,
203                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
204                 .length         = SZ_16M,
205                 .type           = MT_DEVICE
206         }, {
207                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE1,
208                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
209                 .length         = SZ_16M,
210                 .type           = MT_DEVICE
211         }, {
212                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE2,
213                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
214                 .length         = SZ_16M,
215                 .type           = MT_DEVICE
216         },
217 #endif
218 #endif
219 };
220
221 void __init versatile_map_io(void)
222 {
223         iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
224 }
225
226 #define VERSATILE_REFCOUNTER    (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_24MHz_OFFSET)
227
228 /*
229  * This is the Versatile sched_clock implementation.  This has
230  * a resolution of 41.7ns, and a maximum value of about 179s.
231  */
232 unsigned long long sched_clock(void)
233 {
234         unsigned long long v;
235
236         v = (unsigned long long)readl(VERSATILE_REFCOUNTER) * 125;
237         do_div(v, 3);
238
239         return v;
240 }
241
242
243 #define VERSATILE_FLASHCTRL    (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
244
245 static int versatile_flash_init(void)
246 {
247         u32 val;
248
249         val = __raw_readl(VERSATILE_FLASHCTRL);
250         val &= ~VERSATILE_FLASHPROG_FLVPPEN;
251         __raw_writel(val, VERSATILE_FLASHCTRL);
252
253         return 0;
254 }
255
256 static void versatile_flash_exit(void)
257 {
258         u32 val;
259
260         val = __raw_readl(VERSATILE_FLASHCTRL);
261         val &= ~VERSATILE_FLASHPROG_FLVPPEN;
262         __raw_writel(val, VERSATILE_FLASHCTRL);
263 }
264
265 static void versatile_flash_set_vpp(int on)
266 {
267         u32 val;
268
269         val = __raw_readl(VERSATILE_FLASHCTRL);
270         if (on)
271                 val |= VERSATILE_FLASHPROG_FLVPPEN;
272         else
273                 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
274         __raw_writel(val, VERSATILE_FLASHCTRL);
275 }
276
277 static struct flash_platform_data versatile_flash_data = {
278         .map_name               = "cfi_probe",
279         .width                  = 4,
280         .init                   = versatile_flash_init,
281         .exit                   = versatile_flash_exit,
282         .set_vpp                = versatile_flash_set_vpp,
283 };
284
285 static struct resource versatile_flash_resource = {
286         .start                  = VERSATILE_FLASH_BASE,
287         .end                    = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE,
288         .flags                  = IORESOURCE_MEM,
289 };
290
291 static struct platform_device versatile_flash_device = {
292         .name                   = "armflash",
293         .id                     = 0,
294         .dev                    = {
295                 .platform_data  = &versatile_flash_data,
296         },
297         .num_resources          = 1,
298         .resource               = &versatile_flash_resource,
299 };
300
301 static struct resource smc91x_resources[] = {
302         [0] = {
303                 .start          = VERSATILE_ETH_BASE,
304                 .end            = VERSATILE_ETH_BASE + SZ_64K - 1,
305                 .flags          = IORESOURCE_MEM,
306         },
307         [1] = {
308                 .start          = IRQ_ETH,
309                 .end            = IRQ_ETH,
310                 .flags          = IORESOURCE_IRQ,
311         },
312 };
313
314 static struct platform_device smc91x_device = {
315         .name           = "smc91x",
316         .id             = 0,
317         .num_resources  = ARRAY_SIZE(smc91x_resources),
318         .resource       = smc91x_resources,
319 };
320
321 #define VERSATILE_SYSMCI        (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
322
323 unsigned int mmc_status(struct device *dev)
324 {
325         struct amba_device *adev = container_of(dev, struct amba_device, dev);
326         u32 mask;
327
328         if (adev->res.start == VERSATILE_MMCI0_BASE)
329                 mask = 1;
330         else
331                 mask = 2;
332
333         return readl(VERSATILE_SYSMCI) & mask;
334 }
335
336 static struct mmc_platform_data mmc0_plat_data = {
337         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
338         .status         = mmc_status,
339 };
340
341 /*
342  * Clock handling
343  */
344 static const struct icst307_params versatile_oscvco_params = {
345         .ref            = 24000,
346         .vco_max        = 200000,
347         .vd_min         = 4 + 8,
348         .vd_max         = 511 + 8,
349         .rd_min         = 1 + 2,
350         .rd_max         = 127 + 2,
351 };
352
353 static void versatile_oscvco_set(struct clk *clk, struct icst307_vco vco)
354 {
355         void __iomem *sys_lock = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET;
356         void __iomem *sys_osc = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_OSCCLCD_OFFSET;
357         u32 val;
358
359         val = readl(sys_osc) & ~0x7ffff;
360         val |= vco.v | (vco.r << 9) | (vco.s << 16);
361
362         writel(0xa05f, sys_lock);
363         writel(val, sys_osc);
364         writel(0, sys_lock);
365 }
366
367 static struct clk versatile_clcd_clk = {
368         .name   = "CLCDCLK",
369         .params = &versatile_oscvco_params,
370         .setvco = versatile_oscvco_set,
371 };
372
373 /*
374  * CLCD support.
375  */
376 #define SYS_CLCD_MODE_MASK      (3 << 0)
377 #define SYS_CLCD_MODE_888       (0 << 0)
378 #define SYS_CLCD_MODE_5551      (1 << 0)
379 #define SYS_CLCD_MODE_565_RLSB  (2 << 0)
380 #define SYS_CLCD_MODE_565_BLSB  (3 << 0)
381 #define SYS_CLCD_NLCDIOON       (1 << 2)
382 #define SYS_CLCD_VDDPOSSWITCH   (1 << 3)
383 #define SYS_CLCD_PWR3V5SWITCH   (1 << 4)
384 #define SYS_CLCD_ID_MASK        (0x1f << 8)
385 #define SYS_CLCD_ID_SANYO_3_8   (0x00 << 8)
386 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
387 #define SYS_CLCD_ID_EPSON_2_2   (0x02 << 8)
388 #define SYS_CLCD_ID_SANYO_2_5   (0x07 << 8)
389 #define SYS_CLCD_ID_VGA         (0x1f << 8)
390
391 static struct clcd_panel vga = {
392         .mode           = {
393                 .name           = "VGA",
394                 .refresh        = 60,
395                 .xres           = 640,
396                 .yres           = 480,
397                 .pixclock       = 39721,
398                 .left_margin    = 40,
399                 .right_margin   = 24,
400                 .upper_margin   = 32,
401                 .lower_margin   = 11,
402                 .hsync_len      = 96,
403                 .vsync_len      = 2,
404                 .sync           = 0,
405                 .vmode          = FB_VMODE_NONINTERLACED,
406         },
407         .width          = -1,
408         .height         = -1,
409         .tim2           = TIM2_BCD | TIM2_IPC,
410         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
411         .bpp            = 16,
412 };
413
414 static struct clcd_panel sanyo_3_8_in = {
415         .mode           = {
416                 .name           = "Sanyo QVGA",
417                 .refresh        = 116,
418                 .xres           = 320,
419                 .yres           = 240,
420                 .pixclock       = 100000,
421                 .left_margin    = 6,
422                 .right_margin   = 6,
423                 .upper_margin   = 5,
424                 .lower_margin   = 5,
425                 .hsync_len      = 6,
426                 .vsync_len      = 6,
427                 .sync           = 0,
428                 .vmode          = FB_VMODE_NONINTERLACED,
429         },
430         .width          = -1,
431         .height         = -1,
432         .tim2           = TIM2_BCD,
433         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
434         .bpp            = 16,
435 };
436
437 static struct clcd_panel sanyo_2_5_in = {
438         .mode           = {
439                 .name           = "Sanyo QVGA Portrait",
440                 .refresh        = 116,
441                 .xres           = 240,
442                 .yres           = 320,
443                 .pixclock       = 100000,
444                 .left_margin    = 20,
445                 .right_margin   = 10,
446                 .upper_margin   = 2,
447                 .lower_margin   = 2,
448                 .hsync_len      = 10,
449                 .vsync_len      = 2,
450                 .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
451                 .vmode          = FB_VMODE_NONINTERLACED,
452         },
453         .width          = -1,
454         .height         = -1,
455         .tim2           = TIM2_IVS | TIM2_IHS | TIM2_IPC,
456         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
457         .bpp            = 16,
458 };
459
460 static struct clcd_panel epson_2_2_in = {
461         .mode           = {
462                 .name           = "Epson QCIF",
463                 .refresh        = 390,
464                 .xres           = 176,
465                 .yres           = 220,
466                 .pixclock       = 62500,
467                 .left_margin    = 3,
468                 .right_margin   = 2,
469                 .upper_margin   = 1,
470                 .lower_margin   = 0,
471                 .hsync_len      = 3,
472                 .vsync_len      = 2,
473                 .sync           = 0,
474                 .vmode          = FB_VMODE_NONINTERLACED,
475         },
476         .width          = -1,
477         .height         = -1,
478         .tim2           = TIM2_BCD | TIM2_IPC,
479         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
480         .bpp            = 16,
481 };
482
483 /*
484  * Detect which LCD panel is connected, and return the appropriate
485  * clcd_panel structure.  Note: we do not have any information on
486  * the required timings for the 8.4in panel, so we presently assume
487  * VGA timings.
488  */
489 static struct clcd_panel *versatile_clcd_panel(void)
490 {
491         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
492         struct clcd_panel *panel = &vga;
493         u32 val;
494
495         val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
496         if (val == SYS_CLCD_ID_SANYO_3_8)
497                 panel = &sanyo_3_8_in;
498         else if (val == SYS_CLCD_ID_SANYO_2_5)
499                 panel = &sanyo_2_5_in;
500         else if (val == SYS_CLCD_ID_EPSON_2_2)
501                 panel = &epson_2_2_in;
502         else if (val == SYS_CLCD_ID_VGA)
503                 panel = &vga;
504         else {
505                 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
506                         val);
507                 panel = &vga;
508         }
509
510         return panel;
511 }
512
513 /*
514  * Disable all display connectors on the interface module.
515  */
516 static void versatile_clcd_disable(struct clcd_fb *fb)
517 {
518         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
519         u32 val;
520
521         val = readl(sys_clcd);
522         val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
523         writel(val, sys_clcd);
524
525 #ifdef CONFIG_MACH_VERSATILE_AB
526         /*
527          * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
528          */
529         if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
530                 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
531                 unsigned long ctrl;
532
533                 ctrl = readl(versatile_ib2_ctrl);
534                 ctrl &= ~0x01;
535                 writel(ctrl, versatile_ib2_ctrl);
536         }
537 #endif
538 }
539
540 /*
541  * Enable the relevant connector on the interface module.
542  */
543 static void versatile_clcd_enable(struct clcd_fb *fb)
544 {
545         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
546         u32 val;
547
548         val = readl(sys_clcd);
549         val &= ~SYS_CLCD_MODE_MASK;
550
551         switch (fb->fb.var.green.length) {
552         case 5:
553                 val |= SYS_CLCD_MODE_5551;
554                 break;
555         case 6:
556                 val |= SYS_CLCD_MODE_565_RLSB;
557                 break;
558         case 8:
559                 val |= SYS_CLCD_MODE_888;
560                 break;
561         }
562
563         /*
564          * Set the MUX
565          */
566         writel(val, sys_clcd);
567
568         /*
569          * And now enable the PSUs
570          */
571         val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
572         writel(val, sys_clcd);
573
574 #ifdef CONFIG_MACH_VERSATILE_AB
575         /*
576          * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
577          */
578         if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
579                 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
580                 unsigned long ctrl;
581
582                 ctrl = readl(versatile_ib2_ctrl);
583                 ctrl |= 0x01;
584                 writel(ctrl, versatile_ib2_ctrl);
585         }
586 #endif
587 }
588
589 static unsigned long framesize = SZ_1M;
590
591 static int versatile_clcd_setup(struct clcd_fb *fb)
592 {
593         dma_addr_t dma;
594
595         fb->panel               = versatile_clcd_panel();
596
597         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
598                                                     &dma, GFP_KERNEL);
599         if (!fb->fb.screen_base) {
600                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
601                 return -ENOMEM;
602         }
603
604         fb->fb.fix.smem_start   = dma;
605         fb->fb.fix.smem_len     = framesize;
606
607         return 0;
608 }
609
610 static int versatile_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
611 {
612         return dma_mmap_writecombine(&fb->dev->dev, vma,
613                                      fb->fb.screen_base,
614                                      fb->fb.fix.smem_start,
615                                      fb->fb.fix.smem_len);
616 }
617
618 static void versatile_clcd_remove(struct clcd_fb *fb)
619 {
620         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
621                               fb->fb.screen_base, fb->fb.fix.smem_start);
622 }
623
624 static struct clcd_board clcd_plat_data = {
625         .name           = "Versatile",
626         .check          = clcdfb_check,
627         .decode         = clcdfb_decode,
628         .disable        = versatile_clcd_disable,
629         .enable         = versatile_clcd_enable,
630         .setup          = versatile_clcd_setup,
631         .mmap           = versatile_clcd_mmap,
632         .remove         = versatile_clcd_remove,
633 };
634
635 #define AACI_IRQ        { IRQ_AACI, NO_IRQ }
636 #define AACI_DMA        { 0x80, 0x81 }
637 #define MMCI0_IRQ       { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
638 #define MMCI0_DMA       { 0x84, 0 }
639 #define KMI0_IRQ        { IRQ_SIC_KMI0, NO_IRQ }
640 #define KMI0_DMA        { 0, 0 }
641 #define KMI1_IRQ        { IRQ_SIC_KMI1, NO_IRQ }
642 #define KMI1_DMA        { 0, 0 }
643
644 /*
645  * These devices are connected directly to the multi-layer AHB switch
646  */
647 #define SMC_IRQ         { NO_IRQ, NO_IRQ }
648 #define SMC_DMA         { 0, 0 }
649 #define MPMC_IRQ        { NO_IRQ, NO_IRQ }
650 #define MPMC_DMA        { 0, 0 }
651 #define CLCD_IRQ        { IRQ_CLCDINT, NO_IRQ }
652 #define CLCD_DMA        { 0, 0 }
653 #define DMAC_IRQ        { IRQ_DMAINT, NO_IRQ }
654 #define DMAC_DMA        { 0, 0 }
655
656 /*
657  * These devices are connected via the core APB bridge
658  */
659 #define SCTL_IRQ        { NO_IRQ, NO_IRQ }
660 #define SCTL_DMA        { 0, 0 }
661 #define WATCHDOG_IRQ    { IRQ_WDOGINT, NO_IRQ }
662 #define WATCHDOG_DMA    { 0, 0 }
663 #define GPIO0_IRQ       { IRQ_GPIOINT0, NO_IRQ }
664 #define GPIO0_DMA       { 0, 0 }
665 #define GPIO1_IRQ       { IRQ_GPIOINT1, NO_IRQ }
666 #define GPIO1_DMA       { 0, 0 }
667 #define RTC_IRQ         { IRQ_RTCINT, NO_IRQ }
668 #define RTC_DMA         { 0, 0 }
669
670 /*
671  * These devices are connected via the DMA APB bridge
672  */
673 #define SCI_IRQ         { IRQ_SCIINT, NO_IRQ }
674 #define SCI_DMA         { 7, 6 }
675 #define UART0_IRQ       { IRQ_UARTINT0, NO_IRQ }
676 #define UART0_DMA       { 15, 14 }
677 #define UART1_IRQ       { IRQ_UARTINT1, NO_IRQ }
678 #define UART1_DMA       { 13, 12 }
679 #define UART2_IRQ       { IRQ_UARTINT2, NO_IRQ }
680 #define UART2_DMA       { 11, 10 }
681 #define SSP_IRQ         { IRQ_SSPINT, NO_IRQ }
682 #define SSP_DMA         { 9, 8 }
683
684 /* FPGA Primecells */
685 AMBA_DEVICE(aaci,  "fpga:04", AACI,     NULL);
686 AMBA_DEVICE(mmc0,  "fpga:05", MMCI0,    &mmc0_plat_data);
687 AMBA_DEVICE(kmi0,  "fpga:06", KMI0,     NULL);
688 AMBA_DEVICE(kmi1,  "fpga:07", KMI1,     NULL);
689
690 /* DevChip Primecells */
691 AMBA_DEVICE(smc,   "dev:00",  SMC,      NULL);
692 AMBA_DEVICE(mpmc,  "dev:10",  MPMC,     NULL);
693 AMBA_DEVICE(clcd,  "dev:20",  CLCD,     &clcd_plat_data);
694 AMBA_DEVICE(dmac,  "dev:30",  DMAC,     NULL);
695 AMBA_DEVICE(sctl,  "dev:e0",  SCTL,     NULL);
696 AMBA_DEVICE(wdog,  "dev:e1",  WATCHDOG, NULL);
697 AMBA_DEVICE(gpio0, "dev:e4",  GPIO0,    NULL);
698 AMBA_DEVICE(gpio1, "dev:e5",  GPIO1,    NULL);
699 AMBA_DEVICE(rtc,   "dev:e8",  RTC,      NULL);
700 AMBA_DEVICE(sci0,  "dev:f0",  SCI,      NULL);
701 AMBA_DEVICE(uart0, "dev:f1",  UART0,    NULL);
702 AMBA_DEVICE(uart1, "dev:f2",  UART1,    NULL);
703 AMBA_DEVICE(uart2, "dev:f3",  UART2,    NULL);
704 AMBA_DEVICE(ssp0,  "dev:f4",  SSP,      NULL);
705
706 static struct amba_device *amba_devs[] __initdata = {
707         &dmac_device,
708         &uart0_device,
709         &uart1_device,
710         &uart2_device,
711         &smc_device,
712         &mpmc_device,
713         &clcd_device,
714         &sctl_device,
715         &wdog_device,
716         &gpio0_device,
717         &gpio1_device,
718         &rtc_device,
719         &sci0_device,
720         &ssp0_device,
721         &aaci_device,
722         &mmc0_device,
723         &kmi0_device,
724         &kmi1_device,
725 };
726
727 #ifdef CONFIG_LEDS
728 #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
729
730 static void versatile_leds_event(led_event_t ledevt)
731 {
732         unsigned long flags;
733         u32 val;
734
735         local_irq_save(flags);
736         val = readl(VA_LEDS_BASE);
737
738         switch (ledevt) {
739         case led_idle_start:
740                 val = val & ~VERSATILE_SYS_LED0;
741                 break;
742
743         case led_idle_end:
744                 val = val | VERSATILE_SYS_LED0;
745                 break;
746
747         case led_timer:
748                 val = val ^ VERSATILE_SYS_LED1;
749                 break;
750
751         case led_halted:
752                 val = 0;
753                 break;
754
755         default:
756                 break;
757         }
758
759         writel(val, VA_LEDS_BASE);
760         local_irq_restore(flags);
761 }
762 #endif  /* CONFIG_LEDS */
763
764 void __init versatile_init(void)
765 {
766         int i;
767
768         clk_register(&versatile_clcd_clk);
769
770         platform_device_register(&versatile_flash_device);
771         platform_device_register(&smc91x_device);
772
773         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
774                 struct amba_device *d = amba_devs[i];
775                 amba_device_register(d, &iomem_resource);
776         }
777
778 #ifdef CONFIG_LEDS
779         leds_event = versatile_leds_event;
780 #endif
781 }
782
783 /*
784  * Where is the timer (VA)?
785  */
786 #define TIMER0_VA_BASE           __io_address(VERSATILE_TIMER0_1_BASE)
787 #define TIMER1_VA_BASE          (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
788 #define TIMER2_VA_BASE           __io_address(VERSATILE_TIMER2_3_BASE)
789 #define TIMER3_VA_BASE          (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
790 #define VA_IC_BASE               __io_address(VERSATILE_VIC_BASE) 
791
792 /*
793  * How long is the timer interval?
794  */
795 #define TIMER_INTERVAL  (TICKS_PER_uSEC * mSEC_10)
796 #if TIMER_INTERVAL >= 0x100000
797 #define TIMER_RELOAD    (TIMER_INTERVAL >> 8)
798 #define TIMER_DIVISOR   (TIMER_CTRL_DIV256)
799 #define TICKS2USECS(x)  (256 * (x) / TICKS_PER_uSEC)
800 #elif TIMER_INTERVAL >= 0x10000
801 #define TIMER_RELOAD    (TIMER_INTERVAL >> 4)           /* Divide by 16 */
802 #define TIMER_DIVISOR   (TIMER_CTRL_DIV16)
803 #define TICKS2USECS(x)  (16 * (x) / TICKS_PER_uSEC)
804 #else
805 #define TIMER_RELOAD    (TIMER_INTERVAL)
806 #define TIMER_DIVISOR   (TIMER_CTRL_DIV1)
807 #define TICKS2USECS(x)  ((x) / TICKS_PER_uSEC)
808 #endif
809
810 /*
811  * Returns number of ms since last clock interrupt.  Note that interrupts
812  * will have been disabled by do_gettimeoffset()
813  */
814 static unsigned long versatile_gettimeoffset(void)
815 {
816         unsigned long ticks1, ticks2, status;
817
818         /*
819          * Get the current number of ticks.  Note that there is a race
820          * condition between us reading the timer and checking for
821          * an interrupt.  We get around this by ensuring that the
822          * counter has not reloaded between our two reads.
823          */
824         ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
825         do {
826                 ticks1 = ticks2;
827                 status = __raw_readl(VA_IC_BASE + VIC_RAW_STATUS);
828                 ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
829         } while (ticks2 > ticks1);
830
831         /*
832          * Number of ticks since last interrupt.
833          */
834         ticks1 = TIMER_RELOAD - ticks2;
835
836         /*
837          * Interrupt pending?  If so, we've reloaded once already.
838          *
839          * FIXME: Need to check this is effectively timer 0 that expires
840          */
841         if (status & IRQMASK_TIMERINT0_1)
842                 ticks1 += TIMER_RELOAD;
843
844         /*
845          * Convert the ticks to usecs
846          */
847         return TICKS2USECS(ticks1);
848 }
849
850 /*
851  * IRQ handler for the timer
852  */
853 static irqreturn_t versatile_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
854 {
855         write_seqlock(&xtime_lock);
856
857         // ...clear the interrupt
858         writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
859
860         timer_tick(regs);
861
862         write_sequnlock(&xtime_lock);
863
864         return IRQ_HANDLED;
865 }
866
867 static struct irqaction versatile_timer_irq = {
868         .name           = "Versatile Timer Tick",
869         .flags          = IRQF_DISABLED | IRQF_TIMER,
870         .handler        = versatile_timer_interrupt,
871 };
872
873 /*
874  * Set up timer interrupt, and return the current time in seconds.
875  */
876 static void __init versatile_timer_init(void)
877 {
878         u32 val;
879
880         /* 
881          * set clock frequency: 
882          *      VERSATILE_REFCLK is 32KHz
883          *      VERSATILE_TIMCLK is 1MHz
884          */
885         val = readl(__io_address(VERSATILE_SCTL_BASE));
886         writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
887                (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) | 
888                (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
889                (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
890                __io_address(VERSATILE_SCTL_BASE));
891
892         /*
893          * Initialise to a known state (all timers off)
894          */
895         writel(0, TIMER0_VA_BASE + TIMER_CTRL);
896         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
897         writel(0, TIMER2_VA_BASE + TIMER_CTRL);
898         writel(0, TIMER3_VA_BASE + TIMER_CTRL);
899
900         writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
901         writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_VALUE);
902         writel(TIMER_DIVISOR | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC |
903                TIMER_CTRL_IE, TIMER0_VA_BASE + TIMER_CTRL);
904
905         /* 
906          * Make irqs happen for the system timer
907          */
908         setup_irq(IRQ_TIMERINT0_1, &versatile_timer_irq);
909 }
910
911 struct sys_timer versatile_timer = {
912         .init           = versatile_timer_init,
913         .offset         = versatile_gettimeoffset,
914 };