[ARM] 3980/1: extend the ARM Versatile sched_clock implementation from 32 to 63 bit
[linux-2.6.git] / arch / arm / mach-versatile / core.c
1 /*
2  *  linux/arch/arm/mach-versatile/core.c
3  *
4  *  Copyright (C) 1999 - 2003 ARM Limited
5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
20  */
21 #include <linux/init.h>
22 #include <linux/device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/platform_device.h>
25 #include <linux/sysdev.h>
26 #include <linux/interrupt.h>
27 #include <linux/amba/bus.h>
28 #include <linux/amba/clcd.h>
29
30 #include <asm/cnt32_to_63.h>
31 #include <asm/system.h>
32 #include <asm/hardware.h>
33 #include <asm/io.h>
34 #include <asm/irq.h>
35 #include <asm/leds.h>
36 #include <asm/hardware/arm_timer.h>
37 #include <asm/hardware/icst307.h>
38 #include <asm/hardware/vic.h>
39 #include <asm/mach-types.h>
40
41 #include <asm/mach/arch.h>
42 #include <asm/mach/flash.h>
43 #include <asm/mach/irq.h>
44 #include <asm/mach/time.h>
45 #include <asm/mach/map.h>
46 #include <asm/mach/mmc.h>
47
48 #include "core.h"
49 #include "clock.h"
50
51 /*
52  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
53  * is the (PA >> 12).
54  *
55  * Setup a VA for the Versatile Vectored Interrupt Controller.
56  */
57 #define __io_address(n)         __io(IO_ADDRESS(n))
58 #define VA_VIC_BASE             __io_address(VERSATILE_VIC_BASE)
59 #define VA_SIC_BASE             __io_address(VERSATILE_SIC_BASE)
60
61 static void sic_mask_irq(unsigned int irq)
62 {
63         irq -= IRQ_SIC_START;
64         writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
65 }
66
67 static void sic_unmask_irq(unsigned int irq)
68 {
69         irq -= IRQ_SIC_START;
70         writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_SET);
71 }
72
73 static struct irq_chip sic_chip = {
74         .name   = "SIC",
75         .ack    = sic_mask_irq,
76         .mask   = sic_mask_irq,
77         .unmask = sic_unmask_irq,
78 };
79
80 static void
81 sic_handle_irq(unsigned int irq, struct irqdesc *desc)
82 {
83         unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
84
85         if (status == 0) {
86                 do_bad_IRQ(irq, desc);
87                 return;
88         }
89
90         do {
91                 irq = ffs(status) - 1;
92                 status &= ~(1 << irq);
93
94                 irq += IRQ_SIC_START;
95
96                 desc = irq_desc + irq;
97                 desc_handle_irq(irq, desc);
98         } while (status);
99 }
100
101 #if 1
102 #define IRQ_MMCI0A      IRQ_VICSOURCE22
103 #define IRQ_AACI        IRQ_VICSOURCE24
104 #define IRQ_ETH         IRQ_VICSOURCE25
105 #define PIC_MASK        0xFFD00000
106 #else
107 #define IRQ_MMCI0A      IRQ_SIC_MMCI0A
108 #define IRQ_AACI        IRQ_SIC_AACI
109 #define IRQ_ETH         IRQ_SIC_ETH
110 #define PIC_MASK        0
111 #endif
112
113 void __init versatile_init_irq(void)
114 {
115         unsigned int i;
116
117         vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0);
118
119         set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq);
120
121         /* Do second interrupt controller */
122         writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
123
124         for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
125                 if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) {
126                         set_irq_chip(i, &sic_chip);
127                         set_irq_handler(i, do_level_IRQ);
128                         set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
129                 }
130         }
131
132         /*
133          * Interrupts on secondary controller from 0 to 8 are routed to
134          * source 31 on PIC.
135          * Interrupts from 21 to 31 are routed directly to the VIC on
136          * the corresponding number on primary controller. This is controlled
137          * by setting PIC_ENABLEx.
138          */
139         writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
140 }
141
142 static struct map_desc versatile_io_desc[] __initdata = {
143         {
144                 .virtual        =  IO_ADDRESS(VERSATILE_SYS_BASE),
145                 .pfn            = __phys_to_pfn(VERSATILE_SYS_BASE),
146                 .length         = SZ_4K,
147                 .type           = MT_DEVICE
148         }, {
149                 .virtual        =  IO_ADDRESS(VERSATILE_SIC_BASE),
150                 .pfn            = __phys_to_pfn(VERSATILE_SIC_BASE),
151                 .length         = SZ_4K,
152                 .type           = MT_DEVICE
153         }, {
154                 .virtual        =  IO_ADDRESS(VERSATILE_VIC_BASE),
155                 .pfn            = __phys_to_pfn(VERSATILE_VIC_BASE),
156                 .length         = SZ_4K,
157                 .type           = MT_DEVICE
158         }, {
159                 .virtual        =  IO_ADDRESS(VERSATILE_SCTL_BASE),
160                 .pfn            = __phys_to_pfn(VERSATILE_SCTL_BASE),
161                 .length         = SZ_4K * 9,
162                 .type           = MT_DEVICE
163         },
164 #ifdef CONFIG_MACH_VERSATILE_AB
165         {
166                 .virtual        =  IO_ADDRESS(VERSATILE_GPIO0_BASE),
167                 .pfn            = __phys_to_pfn(VERSATILE_GPIO0_BASE),
168                 .length         = SZ_4K,
169                 .type           = MT_DEVICE
170         }, {
171                 .virtual        =  IO_ADDRESS(VERSATILE_IB2_BASE),
172                 .pfn            = __phys_to_pfn(VERSATILE_IB2_BASE),
173                 .length         = SZ_64M,
174                 .type           = MT_DEVICE
175         },
176 #endif
177 #ifdef CONFIG_DEBUG_LL
178         {
179                 .virtual        =  IO_ADDRESS(VERSATILE_UART0_BASE),
180                 .pfn            = __phys_to_pfn(VERSATILE_UART0_BASE),
181                 .length         = SZ_4K,
182                 .type           = MT_DEVICE
183         },
184 #endif
185 #ifdef CONFIG_PCI
186         {
187                 .virtual        =  IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
188                 .pfn            = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
189                 .length         = SZ_4K,
190                 .type           = MT_DEVICE
191         }, {
192                 .virtual        =  (unsigned long)VERSATILE_PCI_VIRT_BASE,
193                 .pfn            = __phys_to_pfn(VERSATILE_PCI_BASE),
194                 .length         = VERSATILE_PCI_BASE_SIZE,
195                 .type           = MT_DEVICE
196         }, {
197                 .virtual        =  (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE,
198                 .pfn            = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
199                 .length         = VERSATILE_PCI_CFG_BASE_SIZE,
200                 .type           = MT_DEVICE
201         },
202 #if 0
203         {
204                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE0,
205                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
206                 .length         = SZ_16M,
207                 .type           = MT_DEVICE
208         }, {
209                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE1,
210                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
211                 .length         = SZ_16M,
212                 .type           = MT_DEVICE
213         }, {
214                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE2,
215                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
216                 .length         = SZ_16M,
217                 .type           = MT_DEVICE
218         },
219 #endif
220 #endif
221 };
222
223 void __init versatile_map_io(void)
224 {
225         iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
226 }
227
228 #define VERSATILE_REFCOUNTER    (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_24MHz_OFFSET)
229
230 /*
231  * This is the Versatile sched_clock implementation.  This has
232  * a resolution of 41.7ns, and a maximum value of about 35583 days.
233  *
234  * The return value is guaranteed to be monotonic in that range as
235  * long as there is always less than 89 seconds between successive
236  * calls to this function.
237  */
238 unsigned long long sched_clock(void)
239 {
240         unsigned long long v = cnt32_to_63(readl(VERSATILE_REFCOUNTER));
241
242         /* the <<1 gets rid of the cnt_32_to_63 top bit saving on a bic insn */
243         v *= 125<<1;
244         do_div(v, 3<<1);
245
246         return v;
247 }
248
249
250 #define VERSATILE_FLASHCTRL    (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
251
252 static int versatile_flash_init(void)
253 {
254         u32 val;
255
256         val = __raw_readl(VERSATILE_FLASHCTRL);
257         val &= ~VERSATILE_FLASHPROG_FLVPPEN;
258         __raw_writel(val, VERSATILE_FLASHCTRL);
259
260         return 0;
261 }
262
263 static void versatile_flash_exit(void)
264 {
265         u32 val;
266
267         val = __raw_readl(VERSATILE_FLASHCTRL);
268         val &= ~VERSATILE_FLASHPROG_FLVPPEN;
269         __raw_writel(val, VERSATILE_FLASHCTRL);
270 }
271
272 static void versatile_flash_set_vpp(int on)
273 {
274         u32 val;
275
276         val = __raw_readl(VERSATILE_FLASHCTRL);
277         if (on)
278                 val |= VERSATILE_FLASHPROG_FLVPPEN;
279         else
280                 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
281         __raw_writel(val, VERSATILE_FLASHCTRL);
282 }
283
284 static struct flash_platform_data versatile_flash_data = {
285         .map_name               = "cfi_probe",
286         .width                  = 4,
287         .init                   = versatile_flash_init,
288         .exit                   = versatile_flash_exit,
289         .set_vpp                = versatile_flash_set_vpp,
290 };
291
292 static struct resource versatile_flash_resource = {
293         .start                  = VERSATILE_FLASH_BASE,
294         .end                    = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1,
295         .flags                  = IORESOURCE_MEM,
296 };
297
298 static struct platform_device versatile_flash_device = {
299         .name                   = "armflash",
300         .id                     = 0,
301         .dev                    = {
302                 .platform_data  = &versatile_flash_data,
303         },
304         .num_resources          = 1,
305         .resource               = &versatile_flash_resource,
306 };
307
308 static struct resource smc91x_resources[] = {
309         [0] = {
310                 .start          = VERSATILE_ETH_BASE,
311                 .end            = VERSATILE_ETH_BASE + SZ_64K - 1,
312                 .flags          = IORESOURCE_MEM,
313         },
314         [1] = {
315                 .start          = IRQ_ETH,
316                 .end            = IRQ_ETH,
317                 .flags          = IORESOURCE_IRQ,
318         },
319 };
320
321 static struct platform_device smc91x_device = {
322         .name           = "smc91x",
323         .id             = 0,
324         .num_resources  = ARRAY_SIZE(smc91x_resources),
325         .resource       = smc91x_resources,
326 };
327
328 #define VERSATILE_SYSMCI        (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
329
330 unsigned int mmc_status(struct device *dev)
331 {
332         struct amba_device *adev = container_of(dev, struct amba_device, dev);
333         u32 mask;
334
335         if (adev->res.start == VERSATILE_MMCI0_BASE)
336                 mask = 1;
337         else
338                 mask = 2;
339
340         return readl(VERSATILE_SYSMCI) & mask;
341 }
342
343 static struct mmc_platform_data mmc0_plat_data = {
344         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
345         .status         = mmc_status,
346 };
347
348 /*
349  * Clock handling
350  */
351 static const struct icst307_params versatile_oscvco_params = {
352         .ref            = 24000,
353         .vco_max        = 200000,
354         .vd_min         = 4 + 8,
355         .vd_max         = 511 + 8,
356         .rd_min         = 1 + 2,
357         .rd_max         = 127 + 2,
358 };
359
360 static void versatile_oscvco_set(struct clk *clk, struct icst307_vco vco)
361 {
362         void __iomem *sys_lock = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET;
363         void __iomem *sys_osc = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_OSCCLCD_OFFSET;
364         u32 val;
365
366         val = readl(sys_osc) & ~0x7ffff;
367         val |= vco.v | (vco.r << 9) | (vco.s << 16);
368
369         writel(0xa05f, sys_lock);
370         writel(val, sys_osc);
371         writel(0, sys_lock);
372 }
373
374 static struct clk versatile_clcd_clk = {
375         .name   = "CLCDCLK",
376         .params = &versatile_oscvco_params,
377         .setvco = versatile_oscvco_set,
378 };
379
380 /*
381  * CLCD support.
382  */
383 #define SYS_CLCD_MODE_MASK      (3 << 0)
384 #define SYS_CLCD_MODE_888       (0 << 0)
385 #define SYS_CLCD_MODE_5551      (1 << 0)
386 #define SYS_CLCD_MODE_565_RLSB  (2 << 0)
387 #define SYS_CLCD_MODE_565_BLSB  (3 << 0)
388 #define SYS_CLCD_NLCDIOON       (1 << 2)
389 #define SYS_CLCD_VDDPOSSWITCH   (1 << 3)
390 #define SYS_CLCD_PWR3V5SWITCH   (1 << 4)
391 #define SYS_CLCD_ID_MASK        (0x1f << 8)
392 #define SYS_CLCD_ID_SANYO_3_8   (0x00 << 8)
393 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
394 #define SYS_CLCD_ID_EPSON_2_2   (0x02 << 8)
395 #define SYS_CLCD_ID_SANYO_2_5   (0x07 << 8)
396 #define SYS_CLCD_ID_VGA         (0x1f << 8)
397
398 static struct clcd_panel vga = {
399         .mode           = {
400                 .name           = "VGA",
401                 .refresh        = 60,
402                 .xres           = 640,
403                 .yres           = 480,
404                 .pixclock       = 39721,
405                 .left_margin    = 40,
406                 .right_margin   = 24,
407                 .upper_margin   = 32,
408                 .lower_margin   = 11,
409                 .hsync_len      = 96,
410                 .vsync_len      = 2,
411                 .sync           = 0,
412                 .vmode          = FB_VMODE_NONINTERLACED,
413         },
414         .width          = -1,
415         .height         = -1,
416         .tim2           = TIM2_BCD | TIM2_IPC,
417         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
418         .bpp            = 16,
419 };
420
421 static struct clcd_panel sanyo_3_8_in = {
422         .mode           = {
423                 .name           = "Sanyo QVGA",
424                 .refresh        = 116,
425                 .xres           = 320,
426                 .yres           = 240,
427                 .pixclock       = 100000,
428                 .left_margin    = 6,
429                 .right_margin   = 6,
430                 .upper_margin   = 5,
431                 .lower_margin   = 5,
432                 .hsync_len      = 6,
433                 .vsync_len      = 6,
434                 .sync           = 0,
435                 .vmode          = FB_VMODE_NONINTERLACED,
436         },
437         .width          = -1,
438         .height         = -1,
439         .tim2           = TIM2_BCD,
440         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
441         .bpp            = 16,
442 };
443
444 static struct clcd_panel sanyo_2_5_in = {
445         .mode           = {
446                 .name           = "Sanyo QVGA Portrait",
447                 .refresh        = 116,
448                 .xres           = 240,
449                 .yres           = 320,
450                 .pixclock       = 100000,
451                 .left_margin    = 20,
452                 .right_margin   = 10,
453                 .upper_margin   = 2,
454                 .lower_margin   = 2,
455                 .hsync_len      = 10,
456                 .vsync_len      = 2,
457                 .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
458                 .vmode          = FB_VMODE_NONINTERLACED,
459         },
460         .width          = -1,
461         .height         = -1,
462         .tim2           = TIM2_IVS | TIM2_IHS | TIM2_IPC,
463         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
464         .bpp            = 16,
465 };
466
467 static struct clcd_panel epson_2_2_in = {
468         .mode           = {
469                 .name           = "Epson QCIF",
470                 .refresh        = 390,
471                 .xres           = 176,
472                 .yres           = 220,
473                 .pixclock       = 62500,
474                 .left_margin    = 3,
475                 .right_margin   = 2,
476                 .upper_margin   = 1,
477                 .lower_margin   = 0,
478                 .hsync_len      = 3,
479                 .vsync_len      = 2,
480                 .sync           = 0,
481                 .vmode          = FB_VMODE_NONINTERLACED,
482         },
483         .width          = -1,
484         .height         = -1,
485         .tim2           = TIM2_BCD | TIM2_IPC,
486         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
487         .bpp            = 16,
488 };
489
490 /*
491  * Detect which LCD panel is connected, and return the appropriate
492  * clcd_panel structure.  Note: we do not have any information on
493  * the required timings for the 8.4in panel, so we presently assume
494  * VGA timings.
495  */
496 static struct clcd_panel *versatile_clcd_panel(void)
497 {
498         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
499         struct clcd_panel *panel = &vga;
500         u32 val;
501
502         val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
503         if (val == SYS_CLCD_ID_SANYO_3_8)
504                 panel = &sanyo_3_8_in;
505         else if (val == SYS_CLCD_ID_SANYO_2_5)
506                 panel = &sanyo_2_5_in;
507         else if (val == SYS_CLCD_ID_EPSON_2_2)
508                 panel = &epson_2_2_in;
509         else if (val == SYS_CLCD_ID_VGA)
510                 panel = &vga;
511         else {
512                 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
513                         val);
514                 panel = &vga;
515         }
516
517         return panel;
518 }
519
520 /*
521  * Disable all display connectors on the interface module.
522  */
523 static void versatile_clcd_disable(struct clcd_fb *fb)
524 {
525         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
526         u32 val;
527
528         val = readl(sys_clcd);
529         val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
530         writel(val, sys_clcd);
531
532 #ifdef CONFIG_MACH_VERSATILE_AB
533         /*
534          * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
535          */
536         if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
537                 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
538                 unsigned long ctrl;
539
540                 ctrl = readl(versatile_ib2_ctrl);
541                 ctrl &= ~0x01;
542                 writel(ctrl, versatile_ib2_ctrl);
543         }
544 #endif
545 }
546
547 /*
548  * Enable the relevant connector on the interface module.
549  */
550 static void versatile_clcd_enable(struct clcd_fb *fb)
551 {
552         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
553         u32 val;
554
555         val = readl(sys_clcd);
556         val &= ~SYS_CLCD_MODE_MASK;
557
558         switch (fb->fb.var.green.length) {
559         case 5:
560                 val |= SYS_CLCD_MODE_5551;
561                 break;
562         case 6:
563                 val |= SYS_CLCD_MODE_565_RLSB;
564                 break;
565         case 8:
566                 val |= SYS_CLCD_MODE_888;
567                 break;
568         }
569
570         /*
571          * Set the MUX
572          */
573         writel(val, sys_clcd);
574
575         /*
576          * And now enable the PSUs
577          */
578         val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
579         writel(val, sys_clcd);
580
581 #ifdef CONFIG_MACH_VERSATILE_AB
582         /*
583          * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
584          */
585         if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
586                 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
587                 unsigned long ctrl;
588
589                 ctrl = readl(versatile_ib2_ctrl);
590                 ctrl |= 0x01;
591                 writel(ctrl, versatile_ib2_ctrl);
592         }
593 #endif
594 }
595
596 static unsigned long framesize = SZ_1M;
597
598 static int versatile_clcd_setup(struct clcd_fb *fb)
599 {
600         dma_addr_t dma;
601
602         fb->panel               = versatile_clcd_panel();
603
604         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
605                                                     &dma, GFP_KERNEL);
606         if (!fb->fb.screen_base) {
607                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
608                 return -ENOMEM;
609         }
610
611         fb->fb.fix.smem_start   = dma;
612         fb->fb.fix.smem_len     = framesize;
613
614         return 0;
615 }
616
617 static int versatile_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
618 {
619         return dma_mmap_writecombine(&fb->dev->dev, vma,
620                                      fb->fb.screen_base,
621                                      fb->fb.fix.smem_start,
622                                      fb->fb.fix.smem_len);
623 }
624
625 static void versatile_clcd_remove(struct clcd_fb *fb)
626 {
627         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
628                               fb->fb.screen_base, fb->fb.fix.smem_start);
629 }
630
631 static struct clcd_board clcd_plat_data = {
632         .name           = "Versatile",
633         .check          = clcdfb_check,
634         .decode         = clcdfb_decode,
635         .disable        = versatile_clcd_disable,
636         .enable         = versatile_clcd_enable,
637         .setup          = versatile_clcd_setup,
638         .mmap           = versatile_clcd_mmap,
639         .remove         = versatile_clcd_remove,
640 };
641
642 #define AACI_IRQ        { IRQ_AACI, NO_IRQ }
643 #define AACI_DMA        { 0x80, 0x81 }
644 #define MMCI0_IRQ       { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
645 #define MMCI0_DMA       { 0x84, 0 }
646 #define KMI0_IRQ        { IRQ_SIC_KMI0, NO_IRQ }
647 #define KMI0_DMA        { 0, 0 }
648 #define KMI1_IRQ        { IRQ_SIC_KMI1, NO_IRQ }
649 #define KMI1_DMA        { 0, 0 }
650
651 /*
652  * These devices are connected directly to the multi-layer AHB switch
653  */
654 #define SMC_IRQ         { NO_IRQ, NO_IRQ }
655 #define SMC_DMA         { 0, 0 }
656 #define MPMC_IRQ        { NO_IRQ, NO_IRQ }
657 #define MPMC_DMA        { 0, 0 }
658 #define CLCD_IRQ        { IRQ_CLCDINT, NO_IRQ }
659 #define CLCD_DMA        { 0, 0 }
660 #define DMAC_IRQ        { IRQ_DMAINT, NO_IRQ }
661 #define DMAC_DMA        { 0, 0 }
662
663 /*
664  * These devices are connected via the core APB bridge
665  */
666 #define SCTL_IRQ        { NO_IRQ, NO_IRQ }
667 #define SCTL_DMA        { 0, 0 }
668 #define WATCHDOG_IRQ    { IRQ_WDOGINT, NO_IRQ }
669 #define WATCHDOG_DMA    { 0, 0 }
670 #define GPIO0_IRQ       { IRQ_GPIOINT0, NO_IRQ }
671 #define GPIO0_DMA       { 0, 0 }
672 #define GPIO1_IRQ       { IRQ_GPIOINT1, NO_IRQ }
673 #define GPIO1_DMA       { 0, 0 }
674 #define RTC_IRQ         { IRQ_RTCINT, NO_IRQ }
675 #define RTC_DMA         { 0, 0 }
676
677 /*
678  * These devices are connected via the DMA APB bridge
679  */
680 #define SCI_IRQ         { IRQ_SCIINT, NO_IRQ }
681 #define SCI_DMA         { 7, 6 }
682 #define UART0_IRQ       { IRQ_UARTINT0, NO_IRQ }
683 #define UART0_DMA       { 15, 14 }
684 #define UART1_IRQ       { IRQ_UARTINT1, NO_IRQ }
685 #define UART1_DMA       { 13, 12 }
686 #define UART2_IRQ       { IRQ_UARTINT2, NO_IRQ }
687 #define UART2_DMA       { 11, 10 }
688 #define SSP_IRQ         { IRQ_SSPINT, NO_IRQ }
689 #define SSP_DMA         { 9, 8 }
690
691 /* FPGA Primecells */
692 AMBA_DEVICE(aaci,  "fpga:04", AACI,     NULL);
693 AMBA_DEVICE(mmc0,  "fpga:05", MMCI0,    &mmc0_plat_data);
694 AMBA_DEVICE(kmi0,  "fpga:06", KMI0,     NULL);
695 AMBA_DEVICE(kmi1,  "fpga:07", KMI1,     NULL);
696
697 /* DevChip Primecells */
698 AMBA_DEVICE(smc,   "dev:00",  SMC,      NULL);
699 AMBA_DEVICE(mpmc,  "dev:10",  MPMC,     NULL);
700 AMBA_DEVICE(clcd,  "dev:20",  CLCD,     &clcd_plat_data);
701 AMBA_DEVICE(dmac,  "dev:30",  DMAC,     NULL);
702 AMBA_DEVICE(sctl,  "dev:e0",  SCTL,     NULL);
703 AMBA_DEVICE(wdog,  "dev:e1",  WATCHDOG, NULL);
704 AMBA_DEVICE(gpio0, "dev:e4",  GPIO0,    NULL);
705 AMBA_DEVICE(gpio1, "dev:e5",  GPIO1,    NULL);
706 AMBA_DEVICE(rtc,   "dev:e8",  RTC,      NULL);
707 AMBA_DEVICE(sci0,  "dev:f0",  SCI,      NULL);
708 AMBA_DEVICE(uart0, "dev:f1",  UART0,    NULL);
709 AMBA_DEVICE(uart1, "dev:f2",  UART1,    NULL);
710 AMBA_DEVICE(uart2, "dev:f3",  UART2,    NULL);
711 AMBA_DEVICE(ssp0,  "dev:f4",  SSP,      NULL);
712
713 static struct amba_device *amba_devs[] __initdata = {
714         &dmac_device,
715         &uart0_device,
716         &uart1_device,
717         &uart2_device,
718         &smc_device,
719         &mpmc_device,
720         &clcd_device,
721         &sctl_device,
722         &wdog_device,
723         &gpio0_device,
724         &gpio1_device,
725         &rtc_device,
726         &sci0_device,
727         &ssp0_device,
728         &aaci_device,
729         &mmc0_device,
730         &kmi0_device,
731         &kmi1_device,
732 };
733
734 #ifdef CONFIG_LEDS
735 #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
736
737 static void versatile_leds_event(led_event_t ledevt)
738 {
739         unsigned long flags;
740         u32 val;
741
742         local_irq_save(flags);
743         val = readl(VA_LEDS_BASE);
744
745         switch (ledevt) {
746         case led_idle_start:
747                 val = val & ~VERSATILE_SYS_LED0;
748                 break;
749
750         case led_idle_end:
751                 val = val | VERSATILE_SYS_LED0;
752                 break;
753
754         case led_timer:
755                 val = val ^ VERSATILE_SYS_LED1;
756                 break;
757
758         case led_halted:
759                 val = 0;
760                 break;
761
762         default:
763                 break;
764         }
765
766         writel(val, VA_LEDS_BASE);
767         local_irq_restore(flags);
768 }
769 #endif  /* CONFIG_LEDS */
770
771 void __init versatile_init(void)
772 {
773         int i;
774
775         clk_register(&versatile_clcd_clk);
776
777         platform_device_register(&versatile_flash_device);
778         platform_device_register(&smc91x_device);
779
780         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
781                 struct amba_device *d = amba_devs[i];
782                 amba_device_register(d, &iomem_resource);
783         }
784
785 #ifdef CONFIG_LEDS
786         leds_event = versatile_leds_event;
787 #endif
788 }
789
790 /*
791  * Where is the timer (VA)?
792  */
793 #define TIMER0_VA_BASE           __io_address(VERSATILE_TIMER0_1_BASE)
794 #define TIMER1_VA_BASE          (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
795 #define TIMER2_VA_BASE           __io_address(VERSATILE_TIMER2_3_BASE)
796 #define TIMER3_VA_BASE          (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
797 #define VA_IC_BASE               __io_address(VERSATILE_VIC_BASE) 
798
799 /*
800  * How long is the timer interval?
801  */
802 #define TIMER_INTERVAL  (TICKS_PER_uSEC * mSEC_10)
803 #if TIMER_INTERVAL >= 0x100000
804 #define TIMER_RELOAD    (TIMER_INTERVAL >> 8)
805 #define TIMER_DIVISOR   (TIMER_CTRL_DIV256)
806 #define TICKS2USECS(x)  (256 * (x) / TICKS_PER_uSEC)
807 #elif TIMER_INTERVAL >= 0x10000
808 #define TIMER_RELOAD    (TIMER_INTERVAL >> 4)           /* Divide by 16 */
809 #define TIMER_DIVISOR   (TIMER_CTRL_DIV16)
810 #define TICKS2USECS(x)  (16 * (x) / TICKS_PER_uSEC)
811 #else
812 #define TIMER_RELOAD    (TIMER_INTERVAL)
813 #define TIMER_DIVISOR   (TIMER_CTRL_DIV1)
814 #define TICKS2USECS(x)  ((x) / TICKS_PER_uSEC)
815 #endif
816
817 /*
818  * Returns number of ms since last clock interrupt.  Note that interrupts
819  * will have been disabled by do_gettimeoffset()
820  */
821 static unsigned long versatile_gettimeoffset(void)
822 {
823         unsigned long ticks1, ticks2, status;
824
825         /*
826          * Get the current number of ticks.  Note that there is a race
827          * condition between us reading the timer and checking for
828          * an interrupt.  We get around this by ensuring that the
829          * counter has not reloaded between our two reads.
830          */
831         ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
832         do {
833                 ticks1 = ticks2;
834                 status = __raw_readl(VA_IC_BASE + VIC_RAW_STATUS);
835                 ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
836         } while (ticks2 > ticks1);
837
838         /*
839          * Number of ticks since last interrupt.
840          */
841         ticks1 = TIMER_RELOAD - ticks2;
842
843         /*
844          * Interrupt pending?  If so, we've reloaded once already.
845          *
846          * FIXME: Need to check this is effectively timer 0 that expires
847          */
848         if (status & IRQMASK_TIMERINT0_1)
849                 ticks1 += TIMER_RELOAD;
850
851         /*
852          * Convert the ticks to usecs
853          */
854         return TICKS2USECS(ticks1);
855 }
856
857 /*
858  * IRQ handler for the timer
859  */
860 static irqreturn_t versatile_timer_interrupt(int irq, void *dev_id)
861 {
862         write_seqlock(&xtime_lock);
863
864         // ...clear the interrupt
865         writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
866
867         timer_tick();
868
869         write_sequnlock(&xtime_lock);
870
871         return IRQ_HANDLED;
872 }
873
874 static struct irqaction versatile_timer_irq = {
875         .name           = "Versatile Timer Tick",
876         .flags          = IRQF_DISABLED | IRQF_TIMER,
877         .handler        = versatile_timer_interrupt,
878 };
879
880 /*
881  * Set up timer interrupt, and return the current time in seconds.
882  */
883 static void __init versatile_timer_init(void)
884 {
885         u32 val;
886
887         /* 
888          * set clock frequency: 
889          *      VERSATILE_REFCLK is 32KHz
890          *      VERSATILE_TIMCLK is 1MHz
891          */
892         val = readl(__io_address(VERSATILE_SCTL_BASE));
893         writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
894                (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) | 
895                (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
896                (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
897                __io_address(VERSATILE_SCTL_BASE));
898
899         /*
900          * Initialise to a known state (all timers off)
901          */
902         writel(0, TIMER0_VA_BASE + TIMER_CTRL);
903         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
904         writel(0, TIMER2_VA_BASE + TIMER_CTRL);
905         writel(0, TIMER3_VA_BASE + TIMER_CTRL);
906
907         writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
908         writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_VALUE);
909         writel(TIMER_DIVISOR | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC |
910                TIMER_CTRL_IE, TIMER0_VA_BASE + TIMER_CTRL);
911
912         /* 
913          * Make irqs happen for the system timer
914          */
915         setup_irq(IRQ_TIMERINT0_1, &versatile_timer_irq);
916 }
917
918 struct sys_timer versatile_timer = {
919         .init           = versatile_timer_init,
920         .offset         = versatile_gettimeoffset,
921 };