[ARM] Wrap calls to descriptor handlers
[linux-2.6.git] / arch / arm / mach-versatile / core.c
1 /*
2  *  linux/arch/arm/mach-versatile/core.c
3  *
4  *  Copyright (C) 1999 - 2003 ARM Limited
5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
20  */
21 #include <linux/config.h>
22 #include <linux/init.h>
23 #include <linux/device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/sysdev.h>
26 #include <linux/interrupt.h>
27
28 #include <asm/system.h>
29 #include <asm/hardware.h>
30 #include <asm/io.h>
31 #include <asm/irq.h>
32 #include <asm/leds.h>
33 #include <asm/mach-types.h>
34 #include <asm/hardware/amba.h>
35 #include <asm/hardware/amba_clcd.h>
36 #include <asm/hardware/arm_timer.h>
37 #include <asm/hardware/icst307.h>
38
39 #include <asm/mach/arch.h>
40 #include <asm/mach/flash.h>
41 #include <asm/mach/irq.h>
42 #include <asm/mach/time.h>
43 #include <asm/mach/map.h>
44 #include <asm/mach/mmc.h>
45
46 #include "core.h"
47 #include "clock.h"
48
49 /*
50  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
51  * is the (PA >> 12).
52  *
53  * Setup a VA for the Versatile Vectored Interrupt Controller.
54  */
55 #define VA_VIC_BASE              IO_ADDRESS(VERSATILE_VIC_BASE)
56 #define VA_SIC_BASE              IO_ADDRESS(VERSATILE_SIC_BASE)
57
58 static void vic_mask_irq(unsigned int irq)
59 {
60         irq -= IRQ_VIC_START;
61         writel(1 << irq, VA_VIC_BASE + VIC_IRQ_ENABLE_CLEAR);
62 }
63
64 static void vic_unmask_irq(unsigned int irq)
65 {
66         irq -= IRQ_VIC_START;
67         writel(1 << irq, VA_VIC_BASE + VIC_IRQ_ENABLE);
68 }
69
70 static struct irqchip vic_chip = {
71         .ack    = vic_mask_irq,
72         .mask   = vic_mask_irq,
73         .unmask = vic_unmask_irq,
74 };
75
76 static void sic_mask_irq(unsigned int irq)
77 {
78         irq -= IRQ_SIC_START;
79         writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
80 }
81
82 static void sic_unmask_irq(unsigned int irq)
83 {
84         irq -= IRQ_SIC_START;
85         writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_SET);
86 }
87
88 static struct irqchip sic_chip = {
89         .ack    = sic_mask_irq,
90         .mask   = sic_mask_irq,
91         .unmask = sic_unmask_irq,
92 };
93
94 static void
95 sic_handle_irq(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
96 {
97         unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
98
99         if (status == 0) {
100                 do_bad_IRQ(irq, desc, regs);
101                 return;
102         }
103
104         do {
105                 irq = ffs(status) - 1;
106                 status &= ~(1 << irq);
107
108                 irq += IRQ_SIC_START;
109
110                 desc = irq_desc + irq;
111                 desc_handle_irq(irq, desc, regs);
112         } while (status);
113 }
114
115 #if 1
116 #define IRQ_MMCI0A      IRQ_VICSOURCE22
117 #define IRQ_AACI        IRQ_VICSOURCE24
118 #define IRQ_ETH         IRQ_VICSOURCE25
119 #define PIC_MASK        0xFFD00000
120 #else
121 #define IRQ_MMCI0A      IRQ_SIC_MMCI0A
122 #define IRQ_AACI        IRQ_SIC_AACI
123 #define IRQ_ETH         IRQ_SIC_ETH
124 #define PIC_MASK        0
125 #endif
126
127 void __init versatile_init_irq(void)
128 {
129         unsigned int i, value;
130
131         /* Disable all interrupts initially. */
132
133         writel(0, VA_VIC_BASE + VIC_INT_SELECT);
134         writel(0, VA_VIC_BASE + VIC_IRQ_ENABLE);
135         writel(~0, VA_VIC_BASE + VIC_IRQ_ENABLE_CLEAR);
136         writel(0, VA_VIC_BASE + VIC_IRQ_STATUS);
137         writel(0, VA_VIC_BASE + VIC_ITCR);
138         writel(~0, VA_VIC_BASE + VIC_IRQ_SOFT_CLEAR);
139
140         /*
141          * Make sure we clear all existing interrupts
142          */
143         writel(0, VA_VIC_BASE + VIC_VECT_ADDR);
144         for (i = 0; i < 19; i++) {
145                 value = readl(VA_VIC_BASE + VIC_VECT_ADDR);
146                 writel(value, VA_VIC_BASE + VIC_VECT_ADDR);
147         }
148
149         for (i = 0; i < 16; i++) {
150                 value = readl(VA_VIC_BASE + VIC_VECT_CNTL0 + (i * 4));
151                 writel(value | VICVectCntl_Enable | i, VA_VIC_BASE + VIC_VECT_CNTL0 + (i * 4));
152         }
153
154         writel(32, VA_VIC_BASE + VIC_DEF_VECT_ADDR);
155
156         for (i = IRQ_VIC_START; i <= IRQ_VIC_END; i++) {
157                 if (i != IRQ_VICSOURCE31) {
158                         set_irq_chip(i, &vic_chip);
159                         set_irq_handler(i, do_level_IRQ);
160                         set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
161                 }
162         }
163
164         set_irq_handler(IRQ_VICSOURCE31, sic_handle_irq);
165         vic_unmask_irq(IRQ_VICSOURCE31);
166
167         /* Do second interrupt controller */
168         writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
169
170         for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
171                 if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) {
172                         set_irq_chip(i, &sic_chip);
173                         set_irq_handler(i, do_level_IRQ);
174                         set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
175                 }
176         }
177
178         /*
179          * Interrupts on secondary controller from 0 to 8 are routed to
180          * source 31 on PIC.
181          * Interrupts from 21 to 31 are routed directly to the VIC on
182          * the corresponding number on primary controller. This is controlled
183          * by setting PIC_ENABLEx.
184          */
185         writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
186 }
187
188 static struct map_desc versatile_io_desc[] __initdata = {
189  { IO_ADDRESS(VERSATILE_SYS_BASE),   VERSATILE_SYS_BASE,   SZ_4K,      MT_DEVICE },
190  { IO_ADDRESS(VERSATILE_SIC_BASE),   VERSATILE_SIC_BASE,   SZ_4K,      MT_DEVICE },
191  { IO_ADDRESS(VERSATILE_VIC_BASE),   VERSATILE_VIC_BASE,   SZ_4K,      MT_DEVICE },
192  { IO_ADDRESS(VERSATILE_SCTL_BASE),  VERSATILE_SCTL_BASE,  SZ_4K * 9,  MT_DEVICE },
193 #ifdef CONFIG_MACH_VERSATILE_AB
194  { IO_ADDRESS(VERSATILE_GPIO0_BASE), VERSATILE_GPIO0_BASE, SZ_4K,      MT_DEVICE },
195  { IO_ADDRESS(VERSATILE_IB2_BASE),   VERSATILE_IB2_BASE,   SZ_64M,     MT_DEVICE },
196 #endif
197 #ifdef CONFIG_DEBUG_LL
198  { IO_ADDRESS(VERSATILE_UART0_BASE), VERSATILE_UART0_BASE, SZ_4K,      MT_DEVICE },
199 #endif
200 #ifdef CONFIG_PCI
201  { IO_ADDRESS(VERSATILE_PCI_CORE_BASE), VERSATILE_PCI_CORE_BASE, SZ_4K, MT_DEVICE },
202  { VERSATILE_PCI_VIRT_BASE,          VERSATILE_PCI_BASE,   VERSATILE_PCI_BASE_SIZE, MT_DEVICE },
203  { VERSATILE_PCI_CFG_VIRT_BASE,      VERSATILE_PCI_CFG_BASE, VERSATILE_PCI_CFG_BASE_SIZE, MT_DEVICE },
204 #if 0
205  { VERSATILE_PCI_VIRT_MEM_BASE0,     VERSATILE_PCI_MEM_BASE0, SZ_16M,  MT_DEVICE },
206  { VERSATILE_PCI_VIRT_MEM_BASE1,     VERSATILE_PCI_MEM_BASE1, SZ_16M,  MT_DEVICE },
207  { VERSATILE_PCI_VIRT_MEM_BASE2,     VERSATILE_PCI_MEM_BASE2, SZ_16M,  MT_DEVICE },
208 #endif
209 #endif
210 };
211
212 void __init versatile_map_io(void)
213 {
214         iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
215 }
216
217 #define VERSATILE_REFCOUNTER    (IO_ADDRESS(VERSATILE_SYS_BASE) + VERSATILE_SYS_24MHz_OFFSET)
218
219 /*
220  * This is the Versatile sched_clock implementation.  This has
221  * a resolution of 41.7ns, and a maximum value of about 179s.
222  */
223 unsigned long long sched_clock(void)
224 {
225         unsigned long long v;
226
227         v = (unsigned long long)readl(VERSATILE_REFCOUNTER) * 125;
228         do_div(v, 3);
229
230         return v;
231 }
232
233
234 #define VERSATILE_FLASHCTRL    (IO_ADDRESS(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
235
236 static int versatile_flash_init(void)
237 {
238         u32 val;
239
240         val = __raw_readl(VERSATILE_FLASHCTRL);
241         val &= ~VERSATILE_FLASHPROG_FLVPPEN;
242         __raw_writel(val, VERSATILE_FLASHCTRL);
243
244         return 0;
245 }
246
247 static void versatile_flash_exit(void)
248 {
249         u32 val;
250
251         val = __raw_readl(VERSATILE_FLASHCTRL);
252         val &= ~VERSATILE_FLASHPROG_FLVPPEN;
253         __raw_writel(val, VERSATILE_FLASHCTRL);
254 }
255
256 static void versatile_flash_set_vpp(int on)
257 {
258         u32 val;
259
260         val = __raw_readl(VERSATILE_FLASHCTRL);
261         if (on)
262                 val |= VERSATILE_FLASHPROG_FLVPPEN;
263         else
264                 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
265         __raw_writel(val, VERSATILE_FLASHCTRL);
266 }
267
268 static struct flash_platform_data versatile_flash_data = {
269         .map_name               = "cfi_probe",
270         .width                  = 4,
271         .init                   = versatile_flash_init,
272         .exit                   = versatile_flash_exit,
273         .set_vpp                = versatile_flash_set_vpp,
274 };
275
276 static struct resource versatile_flash_resource = {
277         .start                  = VERSATILE_FLASH_BASE,
278         .end                    = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE,
279         .flags                  = IORESOURCE_MEM,
280 };
281
282 static struct platform_device versatile_flash_device = {
283         .name                   = "armflash",
284         .id                     = 0,
285         .dev                    = {
286                 .platform_data  = &versatile_flash_data,
287         },
288         .num_resources          = 1,
289         .resource               = &versatile_flash_resource,
290 };
291
292 static struct resource smc91x_resources[] = {
293         [0] = {
294                 .start          = VERSATILE_ETH_BASE,
295                 .end            = VERSATILE_ETH_BASE + SZ_64K - 1,
296                 .flags          = IORESOURCE_MEM,
297         },
298         [1] = {
299                 .start          = IRQ_ETH,
300                 .end            = IRQ_ETH,
301                 .flags          = IORESOURCE_IRQ,
302         },
303 };
304
305 static struct platform_device smc91x_device = {
306         .name           = "smc91x",
307         .id             = 0,
308         .num_resources  = ARRAY_SIZE(smc91x_resources),
309         .resource       = smc91x_resources,
310 };
311
312 #define VERSATILE_SYSMCI        (IO_ADDRESS(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
313
314 unsigned int mmc_status(struct device *dev)
315 {
316         struct amba_device *adev = container_of(dev, struct amba_device, dev);
317         u32 mask;
318
319         if (adev->res.start == VERSATILE_MMCI0_BASE)
320                 mask = 1;
321         else
322                 mask = 2;
323
324         return readl(VERSATILE_SYSMCI) & mask;
325 }
326
327 static struct mmc_platform_data mmc0_plat_data = {
328         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
329         .status         = mmc_status,
330 };
331
332 /*
333  * Clock handling
334  */
335 static const struct icst307_params versatile_oscvco_params = {
336         .ref            = 24000,
337         .vco_max        = 200000,
338         .vd_min         = 4 + 8,
339         .vd_max         = 511 + 8,
340         .rd_min         = 1 + 2,
341         .rd_max         = 127 + 2,
342 };
343
344 static void versatile_oscvco_set(struct clk *clk, struct icst307_vco vco)
345 {
346         unsigned long sys_lock = IO_ADDRESS(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET;
347 #if defined(CONFIG_ARCH_VERSATILE_PB)
348         unsigned long sys_osc = IO_ADDRESS(VERSATILE_SYS_BASE) + VERSATILE_SYS_OSC4_OFFSET;
349 #elif defined(CONFIG_MACH_VERSATILE_AB)
350         unsigned long sys_osc = IO_ADDRESS(VERSATILE_SYS_BASE) + VERSATILE_SYS_OSC1_OFFSET;
351 #endif
352         u32 val;
353
354         val = readl(sys_osc) & ~0x7ffff;
355         val |= vco.v | (vco.r << 9) | (vco.s << 16);
356
357         writel(0xa05f, sys_lock);
358         writel(val, sys_osc);
359         writel(0, sys_lock);
360 }
361
362 static struct clk versatile_clcd_clk = {
363         .name   = "CLCDCLK",
364         .params = &versatile_oscvco_params,
365         .setvco = versatile_oscvco_set,
366 };
367
368 /*
369  * CLCD support.
370  */
371 #define SYS_CLCD_MODE_MASK      (3 << 0)
372 #define SYS_CLCD_MODE_888       (0 << 0)
373 #define SYS_CLCD_MODE_5551      (1 << 0)
374 #define SYS_CLCD_MODE_565_RLSB  (2 << 0)
375 #define SYS_CLCD_MODE_565_BLSB  (3 << 0)
376 #define SYS_CLCD_NLCDIOON       (1 << 2)
377 #define SYS_CLCD_VDDPOSSWITCH   (1 << 3)
378 #define SYS_CLCD_PWR3V5SWITCH   (1 << 4)
379 #define SYS_CLCD_ID_MASK        (0x1f << 8)
380 #define SYS_CLCD_ID_SANYO_3_8   (0x00 << 8)
381 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
382 #define SYS_CLCD_ID_EPSON_2_2   (0x02 << 8)
383 #define SYS_CLCD_ID_SANYO_2_5   (0x07 << 8)
384 #define SYS_CLCD_ID_VGA         (0x1f << 8)
385
386 static struct clcd_panel vga = {
387         .mode           = {
388                 .name           = "VGA",
389                 .refresh        = 60,
390                 .xres           = 640,
391                 .yres           = 480,
392                 .pixclock       = 39721,
393                 .left_margin    = 40,
394                 .right_margin   = 24,
395                 .upper_margin   = 32,
396                 .lower_margin   = 11,
397                 .hsync_len      = 96,
398                 .vsync_len      = 2,
399                 .sync           = 0,
400                 .vmode          = FB_VMODE_NONINTERLACED,
401         },
402         .width          = -1,
403         .height         = -1,
404         .tim2           = TIM2_BCD | TIM2_IPC,
405         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
406         .bpp            = 16,
407 };
408
409 static struct clcd_panel sanyo_3_8_in = {
410         .mode           = {
411                 .name           = "Sanyo QVGA",
412                 .refresh        = 116,
413                 .xres           = 320,
414                 .yres           = 240,
415                 .pixclock       = 100000,
416                 .left_margin    = 6,
417                 .right_margin   = 6,
418                 .upper_margin   = 5,
419                 .lower_margin   = 5,
420                 .hsync_len      = 6,
421                 .vsync_len      = 6,
422                 .sync           = 0,
423                 .vmode          = FB_VMODE_NONINTERLACED,
424         },
425         .width          = -1,
426         .height         = -1,
427         .tim2           = TIM2_BCD,
428         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
429         .bpp            = 16,
430 };
431
432 static struct clcd_panel sanyo_2_5_in = {
433         .mode           = {
434                 .name           = "Sanyo QVGA Portrait",
435                 .refresh        = 116,
436                 .xres           = 240,
437                 .yres           = 320,
438                 .pixclock       = 100000,
439                 .left_margin    = 20,
440                 .right_margin   = 10,
441                 .upper_margin   = 2,
442                 .lower_margin   = 2,
443                 .hsync_len      = 10,
444                 .vsync_len      = 2,
445                 .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
446                 .vmode          = FB_VMODE_NONINTERLACED,
447         },
448         .width          = -1,
449         .height         = -1,
450         .tim2           = TIM2_IVS | TIM2_IHS | TIM2_IPC,
451         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
452         .bpp            = 16,
453 };
454
455 static struct clcd_panel epson_2_2_in = {
456         .mode           = {
457                 .name           = "Epson QCIF",
458                 .refresh        = 390,
459                 .xres           = 176,
460                 .yres           = 220,
461                 .pixclock       = 62500,
462                 .left_margin    = 3,
463                 .right_margin   = 2,
464                 .upper_margin   = 1,
465                 .lower_margin   = 0,
466                 .hsync_len      = 3,
467                 .vsync_len      = 2,
468                 .sync           = 0,
469                 .vmode          = FB_VMODE_NONINTERLACED,
470         },
471         .width          = -1,
472         .height         = -1,
473         .tim2           = TIM2_BCD | TIM2_IPC,
474         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
475         .bpp            = 16,
476 };
477
478 /*
479  * Detect which LCD panel is connected, and return the appropriate
480  * clcd_panel structure.  Note: we do not have any information on
481  * the required timings for the 8.4in panel, so we presently assume
482  * VGA timings.
483  */
484 static struct clcd_panel *versatile_clcd_panel(void)
485 {
486         unsigned long sys_clcd = IO_ADDRESS(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
487         struct clcd_panel *panel = &vga;
488         u32 val;
489
490         val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
491         if (val == SYS_CLCD_ID_SANYO_3_8)
492                 panel = &sanyo_3_8_in;
493         else if (val == SYS_CLCD_ID_SANYO_2_5)
494                 panel = &sanyo_2_5_in;
495         else if (val == SYS_CLCD_ID_EPSON_2_2)
496                 panel = &epson_2_2_in;
497         else if (val == SYS_CLCD_ID_VGA)
498                 panel = &vga;
499         else {
500                 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
501                         val);
502                 panel = &vga;
503         }
504
505         return panel;
506 }
507
508 /*
509  * Disable all display connectors on the interface module.
510  */
511 static void versatile_clcd_disable(struct clcd_fb *fb)
512 {
513         unsigned long sys_clcd = IO_ADDRESS(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
514         u32 val;
515
516         val = readl(sys_clcd);
517         val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
518         writel(val, sys_clcd);
519
520 #ifdef CONFIG_MACH_VERSATILE_AB
521         /*
522          * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
523          */
524         if (fb->panel == &sanyo_2_5_in) {
525                 unsigned long versatile_ib2_ctrl = IO_ADDRESS(VERSATILE_IB2_CTRL);
526                 unsigned long ctrl;
527
528                 ctrl = readl(versatile_ib2_ctrl);
529                 ctrl &= ~0x01;
530                 writel(ctrl, versatile_ib2_ctrl);
531         }
532 #endif
533 }
534
535 /*
536  * Enable the relevant connector on the interface module.
537  */
538 static void versatile_clcd_enable(struct clcd_fb *fb)
539 {
540         unsigned long sys_clcd = IO_ADDRESS(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
541         u32 val;
542
543         val = readl(sys_clcd);
544         val &= ~SYS_CLCD_MODE_MASK;
545
546         switch (fb->fb.var.green.length) {
547         case 5:
548                 val |= SYS_CLCD_MODE_5551;
549                 break;
550         case 6:
551                 val |= SYS_CLCD_MODE_565_RLSB;
552                 break;
553         case 8:
554                 val |= SYS_CLCD_MODE_888;
555                 break;
556         }
557
558         /*
559          * Set the MUX
560          */
561         writel(val, sys_clcd);
562
563         /*
564          * And now enable the PSUs
565          */
566         val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
567         writel(val, sys_clcd);
568
569 #ifdef CONFIG_MACH_VERSATILE_AB
570         /*
571          * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
572          */
573         if (fb->panel == &sanyo_2_5_in) {
574                 unsigned long versatile_ib2_ctrl = IO_ADDRESS(VERSATILE_IB2_CTRL);
575                 unsigned long ctrl;
576
577                 ctrl = readl(versatile_ib2_ctrl);
578                 ctrl |= 0x01;
579                 writel(ctrl, versatile_ib2_ctrl);
580         }
581 #endif
582 }
583
584 static unsigned long framesize = SZ_1M;
585
586 static int versatile_clcd_setup(struct clcd_fb *fb)
587 {
588         dma_addr_t dma;
589
590         fb->panel               = versatile_clcd_panel();
591
592         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
593                                                     &dma, GFP_KERNEL);
594         if (!fb->fb.screen_base) {
595                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
596                 return -ENOMEM;
597         }
598
599         fb->fb.fix.smem_start   = dma;
600         fb->fb.fix.smem_len     = framesize;
601
602         return 0;
603 }
604
605 static int versatile_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
606 {
607         return dma_mmap_writecombine(&fb->dev->dev, vma,
608                                      fb->fb.screen_base,
609                                      fb->fb.fix.smem_start,
610                                      fb->fb.fix.smem_len);
611 }
612
613 static void versatile_clcd_remove(struct clcd_fb *fb)
614 {
615         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
616                               fb->fb.screen_base, fb->fb.fix.smem_start);
617 }
618
619 static struct clcd_board clcd_plat_data = {
620         .name           = "Versatile",
621         .check          = clcdfb_check,
622         .decode         = clcdfb_decode,
623         .disable        = versatile_clcd_disable,
624         .enable         = versatile_clcd_enable,
625         .setup          = versatile_clcd_setup,
626         .mmap           = versatile_clcd_mmap,
627         .remove         = versatile_clcd_remove,
628 };
629
630 #define AACI_IRQ        { IRQ_AACI, NO_IRQ }
631 #define AACI_DMA        { 0x80, 0x81 }
632 #define MMCI0_IRQ       { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
633 #define MMCI0_DMA       { 0x84, 0 }
634 #define KMI0_IRQ        { IRQ_SIC_KMI0, NO_IRQ }
635 #define KMI0_DMA        { 0, 0 }
636 #define KMI1_IRQ        { IRQ_SIC_KMI1, NO_IRQ }
637 #define KMI1_DMA        { 0, 0 }
638
639 /*
640  * These devices are connected directly to the multi-layer AHB switch
641  */
642 #define SMC_IRQ         { NO_IRQ, NO_IRQ }
643 #define SMC_DMA         { 0, 0 }
644 #define MPMC_IRQ        { NO_IRQ, NO_IRQ }
645 #define MPMC_DMA        { 0, 0 }
646 #define CLCD_IRQ        { IRQ_CLCDINT, NO_IRQ }
647 #define CLCD_DMA        { 0, 0 }
648 #define DMAC_IRQ        { IRQ_DMAINT, NO_IRQ }
649 #define DMAC_DMA        { 0, 0 }
650
651 /*
652  * These devices are connected via the core APB bridge
653  */
654 #define SCTL_IRQ        { NO_IRQ, NO_IRQ }
655 #define SCTL_DMA        { 0, 0 }
656 #define WATCHDOG_IRQ    { IRQ_WDOGINT, NO_IRQ }
657 #define WATCHDOG_DMA    { 0, 0 }
658 #define GPIO0_IRQ       { IRQ_GPIOINT0, NO_IRQ }
659 #define GPIO0_DMA       { 0, 0 }
660 #define GPIO1_IRQ       { IRQ_GPIOINT1, NO_IRQ }
661 #define GPIO1_DMA       { 0, 0 }
662 #define RTC_IRQ         { IRQ_RTCINT, NO_IRQ }
663 #define RTC_DMA         { 0, 0 }
664
665 /*
666  * These devices are connected via the DMA APB bridge
667  */
668 #define SCI_IRQ         { IRQ_SCIINT, NO_IRQ }
669 #define SCI_DMA         { 7, 6 }
670 #define UART0_IRQ       { IRQ_UARTINT0, NO_IRQ }
671 #define UART0_DMA       { 15, 14 }
672 #define UART1_IRQ       { IRQ_UARTINT1, NO_IRQ }
673 #define UART1_DMA       { 13, 12 }
674 #define UART2_IRQ       { IRQ_UARTINT2, NO_IRQ }
675 #define UART2_DMA       { 11, 10 }
676 #define SSP_IRQ         { IRQ_SSPINT, NO_IRQ }
677 #define SSP_DMA         { 9, 8 }
678
679 /* FPGA Primecells */
680 AMBA_DEVICE(aaci,  "fpga:04", AACI,     NULL);
681 AMBA_DEVICE(mmc0,  "fpga:05", MMCI0,    &mmc0_plat_data);
682 AMBA_DEVICE(kmi0,  "fpga:06", KMI0,     NULL);
683 AMBA_DEVICE(kmi1,  "fpga:07", KMI1,     NULL);
684
685 /* DevChip Primecells */
686 AMBA_DEVICE(smc,   "dev:00",  SMC,      NULL);
687 AMBA_DEVICE(mpmc,  "dev:10",  MPMC,     NULL);
688 AMBA_DEVICE(clcd,  "dev:20",  CLCD,     &clcd_plat_data);
689 AMBA_DEVICE(dmac,  "dev:30",  DMAC,     NULL);
690 AMBA_DEVICE(sctl,  "dev:e0",  SCTL,     NULL);
691 AMBA_DEVICE(wdog,  "dev:e1",  WATCHDOG, NULL);
692 AMBA_DEVICE(gpio0, "dev:e4",  GPIO0,    NULL);
693 AMBA_DEVICE(gpio1, "dev:e5",  GPIO1,    NULL);
694 AMBA_DEVICE(rtc,   "dev:e8",  RTC,      NULL);
695 AMBA_DEVICE(sci0,  "dev:f0",  SCI,      NULL);
696 AMBA_DEVICE(uart0, "dev:f1",  UART0,    NULL);
697 AMBA_DEVICE(uart1, "dev:f2",  UART1,    NULL);
698 AMBA_DEVICE(uart2, "dev:f3",  UART2,    NULL);
699 AMBA_DEVICE(ssp0,  "dev:f4",  SSP,      NULL);
700
701 static struct amba_device *amba_devs[] __initdata = {
702         &dmac_device,
703         &uart0_device,
704         &uart1_device,
705         &uart2_device,
706         &smc_device,
707         &mpmc_device,
708         &clcd_device,
709         &sctl_device,
710         &wdog_device,
711         &gpio0_device,
712         &gpio1_device,
713         &rtc_device,
714         &sci0_device,
715         &ssp0_device,
716         &aaci_device,
717         &mmc0_device,
718         &kmi0_device,
719         &kmi1_device,
720 };
721
722 #ifdef CONFIG_LEDS
723 #define VA_LEDS_BASE (IO_ADDRESS(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
724
725 static void versatile_leds_event(led_event_t ledevt)
726 {
727         unsigned long flags;
728         u32 val;
729
730         local_irq_save(flags);
731         val = readl(VA_LEDS_BASE);
732
733         switch (ledevt) {
734         case led_idle_start:
735                 val = val & ~VERSATILE_SYS_LED0;
736                 break;
737
738         case led_idle_end:
739                 val = val | VERSATILE_SYS_LED0;
740                 break;
741
742         case led_timer:
743                 val = val ^ VERSATILE_SYS_LED1;
744                 break;
745
746         case led_halted:
747                 val = 0;
748                 break;
749
750         default:
751                 break;
752         }
753
754         writel(val, VA_LEDS_BASE);
755         local_irq_restore(flags);
756 }
757 #endif  /* CONFIG_LEDS */
758
759 void __init versatile_init(void)
760 {
761         int i;
762
763         clk_register(&versatile_clcd_clk);
764
765         platform_device_register(&versatile_flash_device);
766         platform_device_register(&smc91x_device);
767
768         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
769                 struct amba_device *d = amba_devs[i];
770                 amba_device_register(d, &iomem_resource);
771         }
772
773 #ifdef CONFIG_LEDS
774         leds_event = versatile_leds_event;
775 #endif
776 }
777
778 /*
779  * Where is the timer (VA)?
780  */
781 #define TIMER0_VA_BASE           IO_ADDRESS(VERSATILE_TIMER0_1_BASE)
782 #define TIMER1_VA_BASE          (IO_ADDRESS(VERSATILE_TIMER0_1_BASE) + 0x20)
783 #define TIMER2_VA_BASE           IO_ADDRESS(VERSATILE_TIMER2_3_BASE)
784 #define TIMER3_VA_BASE          (IO_ADDRESS(VERSATILE_TIMER2_3_BASE) + 0x20)
785 #define VA_IC_BASE               IO_ADDRESS(VERSATILE_VIC_BASE) 
786
787 /*
788  * How long is the timer interval?
789  */
790 #define TIMER_INTERVAL  (TICKS_PER_uSEC * mSEC_10)
791 #if TIMER_INTERVAL >= 0x100000
792 #define TIMER_RELOAD    (TIMER_INTERVAL >> 8)
793 #define TIMER_DIVISOR   (TIMER_CTRL_DIV256)
794 #define TICKS2USECS(x)  (256 * (x) / TICKS_PER_uSEC)
795 #elif TIMER_INTERVAL >= 0x10000
796 #define TIMER_RELOAD    (TIMER_INTERVAL >> 4)           /* Divide by 16 */
797 #define TIMER_DIVISOR   (TIMER_CTRL_DIV16)
798 #define TICKS2USECS(x)  (16 * (x) / TICKS_PER_uSEC)
799 #else
800 #define TIMER_RELOAD    (TIMER_INTERVAL)
801 #define TIMER_DIVISOR   (TIMER_CTRL_DIV1)
802 #define TICKS2USECS(x)  ((x) / TICKS_PER_uSEC)
803 #endif
804
805 /*
806  * Returns number of ms since last clock interrupt.  Note that interrupts
807  * will have been disabled by do_gettimeoffset()
808  */
809 static unsigned long versatile_gettimeoffset(void)
810 {
811         unsigned long ticks1, ticks2, status;
812
813         /*
814          * Get the current number of ticks.  Note that there is a race
815          * condition between us reading the timer and checking for
816          * an interrupt.  We get around this by ensuring that the
817          * counter has not reloaded between our two reads.
818          */
819         ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
820         do {
821                 ticks1 = ticks2;
822                 status = __raw_readl(VA_IC_BASE + VIC_IRQ_RAW_STATUS);
823                 ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
824         } while (ticks2 > ticks1);
825
826         /*
827          * Number of ticks since last interrupt.
828          */
829         ticks1 = TIMER_RELOAD - ticks2;
830
831         /*
832          * Interrupt pending?  If so, we've reloaded once already.
833          *
834          * FIXME: Need to check this is effectively timer 0 that expires
835          */
836         if (status & IRQMASK_TIMERINT0_1)
837                 ticks1 += TIMER_RELOAD;
838
839         /*
840          * Convert the ticks to usecs
841          */
842         return TICKS2USECS(ticks1);
843 }
844
845 /*
846  * IRQ handler for the timer
847  */
848 static irqreturn_t versatile_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
849 {
850         write_seqlock(&xtime_lock);
851
852         // ...clear the interrupt
853         writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
854
855         timer_tick(regs);
856
857         write_sequnlock(&xtime_lock);
858
859         return IRQ_HANDLED;
860 }
861
862 static struct irqaction versatile_timer_irq = {
863         .name           = "Versatile Timer Tick",
864         .flags          = SA_INTERRUPT | SA_TIMER,
865         .handler        = versatile_timer_interrupt,
866 };
867
868 /*
869  * Set up timer interrupt, and return the current time in seconds.
870  */
871 static void __init versatile_timer_init(void)
872 {
873         u32 val;
874
875         /* 
876          * set clock frequency: 
877          *      VERSATILE_REFCLK is 32KHz
878          *      VERSATILE_TIMCLK is 1MHz
879          */
880         val = readl(IO_ADDRESS(VERSATILE_SCTL_BASE));
881         writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
882                (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) | 
883                (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
884                (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
885                IO_ADDRESS(VERSATILE_SCTL_BASE));
886
887         /*
888          * Initialise to a known state (all timers off)
889          */
890         writel(0, TIMER0_VA_BASE + TIMER_CTRL);
891         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
892         writel(0, TIMER2_VA_BASE + TIMER_CTRL);
893         writel(0, TIMER3_VA_BASE + TIMER_CTRL);
894
895         writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
896         writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_VALUE);
897         writel(TIMER_DIVISOR | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC |
898                TIMER_CTRL_IE, TIMER0_VA_BASE + TIMER_CTRL);
899
900         /* 
901          * Make irqs happen for the system timer
902          */
903         setup_irq(IRQ_TIMERINT0_1, &versatile_timer_irq);
904 }
905
906 struct sys_timer versatile_timer = {
907         .init           = versatile_timer_init,
908         .offset         = versatile_gettimeoffset,
909 };