Ventana: KBC: Removing the KBC usage on ventana
[linux-2.6.git] / arch / arm / mach-tegra / usb_phy.c
1 /*
2  * arch/arm/mach-tegra/usb_phy.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Copyright (C) 2010 - 2011 NVIDIA Corporation
6  *
7  * Author:
8  *      Erik Gilling <konkers@google.com>
9  *      Benoit Goby <benoit@android.com>
10  *
11  * This software is licensed under the terms of the GNU General Public
12  * License version 2, as published by the Free Software Foundation, and
13  * may be copied, distributed, and modified under those terms.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  */
21
22 #include <linux/resource.h>
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/err.h>
27 #include <linux/platform_device.h>
28 #include <linux/io.h>
29 #include <linux/gpio.h>
30 #include <linux/usb/otg.h>
31 #include <linux/usb/ulpi.h>
32 #include <asm/mach-types.h>
33 #include <mach/usb_phy.h>
34 #include <mach/iomap.h>
35 #include <mach/pinmux.h>
36
37 #include "fuse.h"
38
39 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
40 #define USB_USBCMD              0x140
41 #define   USB_USBCMD_RS         (1 << 0)
42
43 #define USB_USBSTS              0x144
44 #define   USB_USBSTS_PCI        (1 << 2)
45 #define   USB_USBSTS_HCH        (1 << 12)
46
47 #define USB_TXFILLTUNING        0x164
48 #define USB_FIFO_TXFILL_THRES(x)   (((x) & 0x1f) << 16)
49 #define USB_FIFO_TXFILL_MASK    0x1f0000
50
51 #define ULPI_VIEWPORT           0x170
52 #define   ULPI_WAKEUP           (1 << 31)
53 #define   ULPI_RUN              (1 << 30)
54 #define   ULPI_RD_WR            (1 << 29)
55
56 #define USB_PORTSC1             0x184
57 #define   USB_PORTSC1_PTS(x)    (((x) & 0x3) << 30)
58 #define   USB_PORTSC1_PSPD(x)   (((x) & 0x3) << 26)
59 #define   USB_PORTSC1_PHCD      (1 << 23)
60 #define   USB_PORTSC1_WKOC      (1 << 22)
61 #define   USB_PORTSC1_WKDS      (1 << 21)
62 #define   USB_PORTSC1_WKCN      (1 << 20)
63 #define   USB_PORTSC1_PTC(x)    (((x) & 0xf) << 16)
64 #define   USB_PORTSC1_PP        (1 << 12)
65 #define   USB_PORTSC1_LS(x)     (((x) & 0x3) << 10)
66 #define   USB_PORTSC1_SUSP      (1 << 7)
67 #define   USB_PORTSC1_PE        (1 << 2)
68 #define   USB_PORTSC1_CCS       (1 << 0)
69
70 #define USB_SUSP_CTRL           0x400
71 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
72 #define   USB_WAKE_ON_DISCON_EN_DEV     (1 << 4)
73 #define   USB_SUSP_CLR          (1 << 5)
74 #define   USB_CLKEN             (1 << 6)
75 #define   USB_PHY_CLK_VALID     (1 << 7)
76 #define   USB_PHY_CLK_VALID_INT_ENB    (1 << 9)
77 #define   UTMIP_RESET           (1 << 11)
78 #define   UHSIC_RESET           (1 << 11)
79 #define   UTMIP_PHY_ENABLE      (1 << 12)
80 #define   UHSIC_PHY_ENABLE      (1 << 12)
81 #define   ULPI_PHY_ENABLE       (1 << 13)
82 #define   USB_SUSP_SET          (1 << 14)
83 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
84
85 #define USB_PHY_VBUS_WAKEUP_ID  0x408
86 #define   VDAT_DET_INT_EN       (1 << 16)
87 #define   VDAT_DET_CHG_DET      (1 << 17)
88 #define   VDAT_DET_STS          (1 << 18)
89
90 #define USB1_LEGACY_CTRL        0x410
91 #define   USB1_NO_LEGACY_MODE                   (1 << 0)
92 #define   USB1_VBUS_SENSE_CTL_MASK              (3 << 1)
93 #define   USB1_VBUS_SENSE_CTL_VBUS_WAKEUP       (0 << 1)
94 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
95                                                 (1 << 1)
96 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD       (2 << 1)
97 #define   USB1_VBUS_SENSE_CTL_A_SESS_VLD        (3 << 1)
98
99
100 #define UTMIP_PLL_CFG1          0x804
101 #define   UTMIP_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
102 #define   UTMIP_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 27)
103
104 #define UTMIP_XCVR_CFG0         0x808
105 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
106 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
107 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
108 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
109 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
110 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
111 #define   UTMIP_XCVR_LSBIAS_SEL                 (1 << 21)
112 #define   UTMIP_XCVR_SETUP_MSB(x)               (((x) & 0x7) << 22)
113 #define   UTMIP_XCVR_HSSLEW_MSB(x)              (((x) & 0x7f) << 25)
114
115 #define UTMIP_XCVR_MAX_OFFSET           2
116 #define UTMIP_XCVR_SETUP_MAX_VALUE      0x7f
117 #define XCVR_SETUP_MSB_CALIB(x) ((x) >> 4)
118
119 #define UTMIP_BIAS_CFG0         0x80c
120 #define   UTMIP_OTGPD                   (1 << 11)
121 #define   UTMIP_BIASPD                  (1 << 10)
122
123 #define UTMIP_HSRX_CFG0         0x810
124 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
125 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
126
127 #define UTMIP_HSRX_CFG1         0x814
128 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
129
130 #define UTMIP_TX_CFG0           0x820
131 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
132 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
133
134 #define UTMIP_MISC_CFG1         0x828
135 #define   UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18)
136 #define   UTMIP_PLLU_STABLE_COUNT(x)    (((x) & 0xfff) << 6)
137
138 #define UTMIP_DEBOUNCE_CFG0     0x82c
139 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
140
141 #define UTMIP_BAT_CHRG_CFG0     0x830
142 #define   UTMIP_PD_CHRG                 (1 << 0)
143 #define   UTMIP_ON_SINK_EN              (1 << 2)
144 #define   UTMIP_OP_SRC_EN               (1 << 3)
145
146 #define UTMIP_XCVR_CFG1         0x838
147 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
148 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
149 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
150 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
151
152 #define UTMIP_BIAS_CFG1         0x83c
153 #define   UTMIP_BIAS_PDTRK_COUNT(x)     (((x) & 0x1f) << 3)
154
155 #define UHSIC_PLL_CFG1                          0x804
156 #define   UHSIC_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
157 #define   UHSIC_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 14)
158
159 #define UHSIC_HSRX_CFG0                         0x808
160 #define   UHSIC_ELASTIC_UNDERRUN_LIMIT(x)       (((x) & 0x1f) << 2)
161 #define   UHSIC_ELASTIC_OVERRUN_LIMIT(x)        (((x) & 0x1f) << 8)
162 #define   UHSIC_IDLE_WAIT(x)                    (((x) & 0x1f) << 13)
163
164 #define UHSIC_HSRX_CFG1                         0x80c
165 #define   UHSIC_HS_SYNC_START_DLY(x)            (((x) & 0x1f) << 1)
166
167 #define UHSIC_MISC_CFG0                         0x814
168 #define   UHSIC_SUSPEND_EXIT_ON_EDGE            (1 << 7)
169 #define   UHSIC_DETECT_SHORT_CONNECT            (1 << 8)
170 #define   UHSIC_FORCE_XCVR_MODE                 (1 << 15)
171
172 #define UHSIC_MISC_CFG1                         0X818
173 #define   UHSIC_PLLU_STABLE_COUNT(x)            (((x) & 0xfff) << 2)
174
175 #define UHSIC_PADS_CFG0                         0x81c
176 #define   UHSIC_TX_RTUNEN                       0xf000
177 #define   UHSIC_TX_RTUNE(x)                     (((x) & 0xf) << 12)
178
179 #define UHSIC_PADS_CFG1                         0x820
180 #define   UHSIC_PD_BG                           (1 << 2)
181 #define   UHSIC_PD_TX                           (1 << 3)
182 #define   UHSIC_PD_TRK                          (1 << 4)
183 #define   UHSIC_PD_RX                           (1 << 5)
184 #define   UHSIC_PD_ZI                           (1 << 6)
185 #define   UHSIC_RX_SEL                          (1 << 7)
186 #define   UHSIC_RPD_DATA                        (1 << 9)
187 #define   UHSIC_RPD_STROBE                      (1 << 10)
188 #define   UHSIC_RPU_DATA                        (1 << 11)
189 #define   UHSIC_RPU_STROBE                      (1 << 12)
190
191 #define UHSIC_STAT_CFG0                         0x828
192 #define   UHSIC_CONNECT_DETECT                  (1 << 0)
193
194
195 #else
196
197 #define USB_USBCMD              0x130
198 #define   USB_USBCMD_RS         (1 << 0)
199
200 #define USB_USBSTS              0x134
201 #define   USB_USBSTS_PCI        (1 << 2)
202 #define   USB_USBSTS_SRI        (1 << 7)
203 #define   USB_USBSTS_HCH        (1 << 12)
204
205 #define ULPI_VIEWPORT           0x160
206
207 #define USB_PORTSC1             0x174
208 #define   USB_PORTSC1_WKOC      (1 << 22)
209 #define   USB_PORTSC1_WKDS      (1 << 21)
210 #define   USB_PORTSC1_WKCN      (1 << 20)
211 #define   USB_PORTSC1_PTC(x)    (((x) & 0xf) << 16)
212 #define   USB_PORTSC1_PP        (1 << 12)
213 #define   USB_PORTSC1_SUSP      (1 << 7)
214 #define   USB_PORTSC1_RESUME    (1 << 6)
215 #define   USB_PORTSC1_PE        (1 << 2)
216 #define   USB_PORTSC1_CCS       (1 << 0)
217
218 #define USB_SUSP_CTRL           0x400
219 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
220 #define   USB_WAKE_ON_DISCON_EN_DEV     (1 << 4)
221 #define   USB_SUSP_CLR                  (1 << 5)
222 #define   USB_PHY_CLK_VALID             (1 << 7)
223 #define   USB_PHY_CLK_VALID_INT_ENB    (1 << 9)
224
225
226 #define   UTMIP_RESET                   (1 << 11)
227 #define   UTMIP_PHY_ENABLE              (1 << 12)
228 #define   ULPI_PHY_ENABLE               (1 << 13)
229 #define   UHSIC_RESET                   (1 << 14)
230
231 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
232 #define   UHSIC_PHY_ENABLE              (1 << 19)
233 #define   ULPIS2S_SLV0_RESET            (1 << 20)
234 #define   ULPIS2S_SLV1_RESET            (1 << 21)
235 #define   ULPIS2S_LINE_RESET            (1 << 22)
236 #define   ULPI_PADS_RESET               (1 << 23)
237 #define   ULPI_PADS_CLKEN_RESET         (1 << 24)
238
239 #define USB_PHY_VBUS_WAKEUP_ID  0x408
240 #define   VDAT_DET_INT_EN       (1 << 16)
241 #define   VDAT_DET_CHG_DET      (1 << 17)
242 #define   VDAT_DET_STS          (1 << 18)
243
244 #define USB1_LEGACY_CTRL        0x410
245 #define   USB1_NO_LEGACY_MODE                   (1 << 0)
246 #define   USB1_VBUS_SENSE_CTL_MASK              (3 << 1)
247 #define   USB1_VBUS_SENSE_CTL_VBUS_WAKEUP       (0 << 1)
248 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
249                                                 (1 << 1)
250 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD       (2 << 1)
251 #define   USB1_VBUS_SENSE_CTL_A_SESS_VLD        (3 << 1)
252
253 #define UTMIP_PLL_CFG1          0x804
254 #define   UTMIP_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
255 #define   UTMIP_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 27)
256
257 #define UTMIP_XCVR_CFG0         0x808
258 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
259 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
260 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
261 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
262 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
263 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
264 #define   UTMIP_XCVR_LSBIAS_SEL                 (1 << 21)
265 #define   UTMIP_XCVR_SETUP_MSB(x)               (((x) & 0x7) << 22)
266 #define   UTMIP_XCVR_HSSLEW_MSB(x)              (((x) & 0x7f) << 25)
267
268 #define UTMIP_XCVR_MAX_OFFSET           5
269 #define UTMIP_XCVR_SETUP_MAX_VALUE      0x7f
270 #define XCVR_SETUP_MSB_CALIB(x) ((x) >> 4)
271
272 #define UTMIP_BIAS_CFG0         0x80c
273 #define   UTMIP_OTGPD                   (1 << 11)
274 #define   UTMIP_BIASPD                  (1 << 10)
275 #define   UTMIP_HSSQUELCH_LEVEL(x)      (((x) & 0x3) << 0)
276 #define   UTMIP_HSDISCON_LEVEL(x)       (((x) & 0x3) << 2)
277 #define   UTMIP_HSDISCON_LEVEL_MSB      (1 << 24)
278
279 #define UTMIP_HSRX_CFG0         0x810
280 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
281 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
282
283 #define UTMIP_HSRX_CFG1         0x814
284 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
285
286 #define UTMIP_TX_CFG0           0x820
287 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
288 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
289
290 #define UTMIP_MISC_CFG1         0x828
291 #define   UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18)
292 #define   UTMIP_PLLU_STABLE_COUNT(x)    (((x) & 0xfff) << 6)
293
294 #define UTMIP_DEBOUNCE_CFG0     0x82c
295 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
296
297 #define UTMIP_BAT_CHRG_CFG0     0x830
298 #define   UTMIP_PD_CHRG                 (1 << 0)
299 #define   UTMIP_ON_SINK_EN              (1 << 2)
300 #define   UTMIP_OP_SRC_EN               (1 << 3)
301
302 #define UTMIP_XCVR_CFG1         0x838
303 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
304 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
305 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
306 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
307
308 #define UTMIP_BIAS_CFG1         0x83c
309 #define   UTMIP_BIAS_PDTRK_COUNT(x)     (((x) & 0x1f) << 3)
310 #define   UTMIP_BIAS_PDTRK_POWERDOWN    (1 << 0)
311 #define   UTMIP_BIAS_PDTRK_POWERUP      (1 << 1)
312
313 #define HOSTPC1_DEVLC           0x1b4
314 #define   HOSTPC1_DEVLC_PHCD            (1 << 22)
315 #define   HOSTPC1_DEVLC_PTS(x)          (((x) & 0x7) << 29)
316 #define   HOSTPC1_DEVLC_PTS_MASK        7
317 #define   HOSTPC1_DEVLC_PTS_HSIC        4
318 #define   HOSTPC1_DEVLC_STS             (1 << 28)
319 #define   HOSTPC1_DEVLC_PSPD(x)         (((x) & 0x3) << 25)
320 #define   HOSTPC1_DEVLC_PSPD_MASK       3
321 #define   HOSTPC1_DEVLC_PSPD_HIGH_SPEED 2
322
323 #define TEGRA_USB_USBMODE_REG_OFFSET    0x1f8
324 #define   TEGRA_USB_USBMODE_HOST                (3 << 0)
325
326 #define TEGRA_PMC_USB_AO                0xf0
327 #define   TEGRA_PMC_USB_AO_VBUS_WAKEUP_PD_P0    (1 << 2)
328 #define   TEGRA_PMC_USB_AO_ID_PD_P0             (1 << 3)
329 #define   TEGRA_PMC_USB_AO_PD_P2                (0xf << 8)
330
331 #define ICUSB_CTRL              0x15c
332
333 #define UHSIC_PLL_CFG1                          0xc04
334 #define   UHSIC_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
335 #define   UHSIC_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 14)
336
337 #define UHSIC_HSRX_CFG0                         0xc08
338 #define   UHSIC_ELASTIC_UNDERRUN_LIMIT(x)       (((x) & 0x1f) << 2)
339 #define   UHSIC_ELASTIC_OVERRUN_LIMIT(x)        (((x) & 0x1f) << 8)
340 #define   UHSIC_IDLE_WAIT(x)                    (((x) & 0x1f) << 13)
341
342 #define UHSIC_HSRX_CFG1                         0xc0c
343 #define   UHSIC_HS_SYNC_START_DLY(x)            (((x) & 0x1f) << 1)
344
345 #define UHSIC_MISC_CFG0                         0xc14
346 #define   UHSIC_SUSPEND_EXIT_ON_EDGE            (1 << 7)
347 #define   UHSIC_DETECT_SHORT_CONNECT            (1 << 8)
348 #define   UHSIC_FORCE_XCVR_MODE                 (1 << 15)
349
350 #define UHSIC_MISC_CFG1                         0xc18
351 #define   UHSIC_PLLU_STABLE_COUNT(x)            (((x) & 0xfff) << 2)
352
353 #define UHSIC_PADS_CFG0                         0xc1c
354 #define   UHSIC_TX_RTUNEN                       0xf000
355 #define   UHSIC_TX_RTUNE(x)                     (((x) & 0xf) << 12)
356
357 #define UHSIC_PADS_CFG1                         0xc20
358 #define   UHSIC_PD_BG                           (1 << 2)
359 #define   UHSIC_PD_TX                           (1 << 3)
360 #define   UHSIC_PD_TRK                          (1 << 4)
361 #define   UHSIC_PD_RX                           (1 << 5)
362 #define   UHSIC_PD_ZI                           (1 << 6)
363 #define   UHSIC_RX_SEL                          (1 << 7)
364 #define   UHSIC_RPD_DATA                        (1 << 9)
365 #define   UHSIC_RPD_STROBE                      (1 << 10)
366 #define   UHSIC_RPU_DATA                        (1 << 11)
367 #define   UHSIC_RPU_STROBE                      (1 << 12)
368
369 #define UHSIC_STAT_CFG0                         0xc28
370 #define   UHSIC_CONNECT_DETECT                  (1 << 0)
371
372 #define PMC_UTMIP_MASTER_CONFIG         0x310
373 #define UTMIP_PWR(inst)                 (1 << (inst))
374
375 #define PMC_USB_DEBOUNCE                0xec
376 #define UTMIP_LINE_DEB_CNT(x)           (((x) & 0xf) << 16)
377
378 #define PMC_UTMIP_UHSIC_FAKE            0x218
379 #define USBON_VAL(inst)         (1 << ((4*(inst))+1))
380 #define USBON_VAL_P2                    (1 << 9)
381 #define USBON_VAL_P1                    (1 << 5)
382 #define USBON_VAL_P0                    (1 << 1)
383 #define USBOP_VAL(inst)         (1 << (4*(inst)))
384 #define USBOP_VAL_P2                    (1 << 8)
385 #define USBOP_VAL_P1                    (1 << 4)
386 #define USBOP_VAL_P0                    (1 << 0)
387
388 #define PMC_SLEEPWALK_CFG               0x200
389 #define UTMIP_LINEVAL_WALK_EN(inst)     (1 << ((8*(inst))+7))
390 #define UTMIP_LINEVAL_WALK_EN_P2        (1 << 23)
391 #define UTMIP_LINEVAL_WALK_EN_P1        (1 << 15)
392 #define UTMIP_LINEVAL_WALK_EN_P0        (1 << 7)
393 #define UTMIP_WAKE_VAL(inst, x) (((x) & 0xf) << ((8*(inst))+4))
394 #define UTMIP_WAKE_VAL_P2(x)            (((x) & 0xf) << 20)
395 #define UTMIP_WAKE_VAL_P1(x)            (((x) & 0xf) << 12)
396 #define UTMIP_WAKE_VAL_P0(x)            (((x) & 0xf) << 4)
397 #define WAKE_VAL_NONE                   0xc
398 #define WAKE_VAL_FSJ                    0x2
399 #define WAKE_VAL_FSK                    0x1
400 #define WAKE_VAL_SE0                    0x0
401
402 #define PMC_SLEEP_CFG                   0x1fc
403 #define UTMIP_TCTRL_USE_PMC(inst)       (1 << ((8*(inst))+3))
404 #define UTMIP_TCTRL_USE_PMC_P2          (1 << 19)
405 #define UTMIP_TCTRL_USE_PMC_P1          (1 << 11)
406 #define UTMIP_TCTRL_USE_PMC_P0          (1 << 3)
407 #define UTMIP_RCTRL_USE_PMC(inst)       (1 << ((8*(inst))+2))
408 #define UTMIP_RCTRL_USE_PMC_P2          (1 << 18)
409 #define UTMIP_RCTRL_USE_PMC_P1          (1 << 10)
410 #define UTMIP_RCTRL_USE_PMC_P0          (1 << 2)
411 #define UTMIP_FSLS_USE_PMC(inst)        (1 << ((8*(inst))+1))
412 #define UTMIP_FSLS_USE_PMC_P2           (1 << 17)
413 #define UTMIP_FSLS_USE_PMC_P1           (1 << 9)
414 #define UTMIP_FSLS_USE_PMC_P0           (1 << 1)
415 #define UTMIP_MASTER_ENABLE(inst)       (1 << (8*(inst)))
416 #define UTMIP_MASTER_ENABLE_P2          (1 << 16)
417 #define UTMIP_MASTER_ENABLE_P1          (1 << 8)
418 #define UTMIP_MASTER_ENABLE_P0          (1 << 0)
419
420 #define PMC_USB_AO                      0xf0
421 #define USBON_VAL_PD(inst)              (1 << ((4*(inst))+1))
422 #define USBON_VAL_PD_P2                 (1 << 9)
423 #define USBON_VAL_PD_P1                 (1 << 5)
424 #define USBON_VAL_PD_P0                 (1 << 1)
425 #define USBOP_VAL_PD(inst)              (1 << (4*(inst)))
426 #define USBOP_VAL_PD_P2                 (1 << 8)
427 #define USBOP_VAL_PD_P1                 (1 << 4)
428 #define USBOP_VAL_PD_P0                 (1 << 0)
429
430 #define PMC_TRIGGERS                    0x1ec
431 #define UTMIP_CLR_WALK_PTR(inst)        (1 << (inst))
432 #define UTMIP_CLR_WALK_PTR_P2           (1 << 2)
433 #define UTMIP_CLR_WALK_PTR_P1           (1 << 1)
434 #define UTMIP_CLR_WALK_PTR_P0           (1 << 0)
435 #define UTMIP_CAP_CFG(inst)             (1 << ((inst)+4))
436 #define UTMIP_CAP_CFG_P2                (1 << 6)
437 #define UTMIP_CAP_CFG_P1                (1 << 5)
438 #define UTMIP_CAP_CFG_P0                (1 << 4)
439 #define UTMIP_CLR_WAKE_ALARM(inst)              (1 << ((inst)+12))
440 #define UTMIP_CLR_WAKE_ALARM_P2         (1 << 14)
441
442 #define PMC_PAD_CFG                     (0x1f4)
443
444 #define PMC_UTMIP_BIAS_MASTER_CNTRL     0x30c
445 #define BIAS_MASTER_PROG_VAL            (1 << 1)
446
447 #define PMC_SLEEPWALK_REG(inst)         (0x204 + (4*(inst)))
448 #define PMC_SLEEPWALK_P0                0x204
449 #define PMC_SLEEPWALK_P1                0x208
450 #define PMC_SLEEPWALK_P2                0x20c
451 #define UTMIP_USBOP_RPD_A               (1 << 0)
452 #define UTMIP_USBON_RPD_A               (1 << 1)
453 #define UTMIP_AP_A                      (1 << 4)
454 #define UTMIP_AN_A                      (1 << 5)
455 #define UTMIP_HIGHZ_A                   (1 << 6)
456 #define UTMIP_USBOP_RPD_B               (1 << 8)
457 #define UTMIP_USBON_RPD_B               (1 << 9)
458 #define UTMIP_AP_B                      (1 << 12)
459 #define UTMIP_AN_B                      (1 << 13)
460 #define UTMIP_HIGHZ_B                   (1 << 14)
461 #define UTMIP_USBOP_RPD_C               (1 << 16)
462 #define UTMIP_USBON_RPD_C               (1 << 17)
463 #define UTMIP_AP_C                      (1 << 20)
464 #define UTMIP_AN_C                      (1 << 21)
465 #define UTMIP_HIGHZ_C                   (1 << 22)
466 #define UTMIP_USBOP_RPD_D               (1 << 24)
467 #define UTMIP_USBON_RPD_D               (1 << 25)
468 #define UTMIP_AP_D                      (1 << 28)
469 #define UTMIP_AN_D                      (1 << 29)
470 #define UTMIP_HIGHZ_D                   (1 << 30)
471
472 #define UTMIP_PMC_WAKEUP0               0x84c
473 #define  EVENT_INT_ENB                  (1 << 0)
474
475 #define UTMIP_UHSIC_STATUS              0x214
476 #define UTMIP_WALK_PTR_VAL(inst)        (0x3 << ((inst)*2))
477 #define UTMIP_USBOP_VAL(inst)           (1 << ((2*(inst)) + 8))
478 #define UTMIP_USBOP_VAL_P2              (1 << 12)
479 #define UTMIP_USBOP_VAL_P1              (1 << 10)
480 #define UTMIP_USBOP_VAL_P0              (1 << 8)
481 #define UTMIP_USBON_VAL(inst)           (1 << ((2*(inst)) + 9))
482 #define UTMIP_USBON_VAL_P2              (1 << 13)
483 #define UTMIP_USBON_VAL_P1              (1 << 11)
484 #define UTMIP_USBON_VAL_P0              (1 << 9)
485 #define UTMIP_WAKE_ALARM(inst)          (1 << ((inst) + 16))
486 #define UTMIP_WAKE_ALARM_P2             (1 << 18)
487 #define UTMIP_WAKE_ALARM_P1             (1 << 17)
488 #define UTMIP_WAKE_ALARM_P0             (1 << 16)
489 #define UTMIP_WALK_PTR(inst)            (1 << ((inst)*2))
490 #define UTMIP_WALK_PTR_P2               (1 << 4)
491 #define UTMIP_WALK_PTR_P1               (1 << 2)
492 #define UTMIP_WALK_PTR_P0               (1 << 0)
493
494 #define UTMIP_BIAS_STS0         0x840
495 #define UTMIP_RCTRL_VAL(x)      (((x) & 0xffff) << 0)
496 #define UTMIP_TCTRL_VAL(x)      (((x) & (0xffff << 16)) >> 16)
497
498 #define PMC_UTMIP_TERM_PAD_CFG  0x1f8
499 #define PMC_TCTRL_VAL(x)        (((x) & 0x1f) << 5)
500 #define PMC_RCTRL_VAL(x)        (((x) & 0x1f) << 0)
501
502 static u32 utmip_rctrl_val, utmip_tctrl_val;
503
504 #endif
505
506 /* Common registers */
507 #define UTMIP_MISC_CFG0         0x824
508 #define   UTMIP_DPDM_OBSERVE            (1 << 26)
509 #define   UTMIP_DPDM_OBSERVE_SEL(x)     (((x) & 0xf) << 27)
510 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J   UTMIP_DPDM_OBSERVE_SEL(0xf)
511 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K   UTMIP_DPDM_OBSERVE_SEL(0xe)
512 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
513 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
514 #define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
515 #define   FORCE_PULLDN_DM       (1 << 8)
516 #define   FORCE_PULLDN_DP       (1 << 9)
517 #define   COMB_TERMS            (1 << 0)
518 #define   ALWAYS_FREE_RUNNING_TERMS     (1 << 1)
519
520 #define ULPIS2S_CTRL            0x418
521 #define   ULPIS2S_ENA                   (1 << 0)
522 #define   ULPIS2S_SUPPORT_DISCONNECT    (1 << 2)
523 #define   ULPIS2S_PLLU_MASTER_BLASTER60 (1 << 3)
524 #define   ULPIS2S_SPARE(x)              (((x) & 0xF) << 8)
525 #define   ULPIS2S_FORCE_ULPI_CLK_OUT    (1 << 12)
526 #define   ULPIS2S_DISCON_DONT_CHECK_SE0 (1 << 13)
527 #define   ULPIS2S_SUPPORT_HS_KEEP_ALIVE (1 << 14)
528 #define   ULPIS2S_DISABLE_STP_PU        (1 << 15)
529 #define   ULPIS2S_SLV0_CLAMP_XMIT       (1 << 16)
530
531
532 #define ULPI_TIMING_CTRL_0      0x424
533 #define   ULPI_CLOCK_OUT_DELAY(x)       ((x) & 0x1F)
534 #define   ULPI_OUTPUT_PINMUX_BYP        (1 << 10)
535 #define   ULPI_CLKOUT_PINMUX_BYP        (1 << 11)
536 #define   ULPI_SHADOW_CLK_LOOPBACK_EN   (1 << 12)
537 #define   ULPI_SHADOW_CLK_SEL           (1 << 13)
538 #define   ULPI_CORE_CLK_SEL             (1 << 14)
539 #define   ULPI_SHADOW_CLK_DELAY(x)      (((x) & 0x1F) << 16)
540 #define   ULPI_LBK_PAD_EN               (1 << 26)
541 #define   ULPI_LBK_PAD_E_INPUT_OR       (1 << 27)
542 #define   ULPI_CLK_OUT_ENA              (1 << 28)
543 #define   ULPI_CLK_PADOUT_ENA           (1 << 29)
544
545 #define ULPI_TIMING_CTRL_1      0x428
546 #define   ULPI_DATA_TRIMMER_LOAD        (1 << 0)
547 #define   ULPI_DATA_TRIMMER_SEL(x)      (((x) & 0x7) << 1)
548 #define   ULPI_STPDIRNXT_TRIMMER_LOAD   (1 << 16)
549 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
550 #define   ULPI_DIR_TRIMMER_LOAD         (1 << 24)
551 #define   ULPI_DIR_TRIMMER_SEL(x)       (((x) & 0x7) << 25)
552
553 #define UTMIP_SPARE_CFG0        0x834
554 #define   FUSE_SETUP_SEL                (1 << 3)
555 #define   FUSE_ATERM_SEL                (1 << 4)
556
557 #define FUSE_USB_CALIB_0                0x1F0
558 #define FUSE_USB_CALIB_XCVR_SETUP(x)    (((x) & 0x7F) << 0)
559
560 #define UHSIC_PLL_CFG0          0x800
561
562 #define UHSIC_TX_CFG0                           0x810
563 #define   UHSIC_HS_POSTAMBLE_OUTPUT_ENABLE      (1 << 6)
564
565 #define UHSIC_CMD_CFG0                          0x824
566 #define   UHSIC_PRETEND_CONNECT_DETECT          (1 << 5)
567
568 #define UHSIC_SPARE_CFG0                        0x82c
569
570 /* These values (in milli second) are taken from the battery charging spec */
571 #define TDP_SRC_ON_MS    100
572 #define TDPSRC_CON_MS    40
573
574 static DEFINE_SPINLOCK(utmip_pad_lock);
575 static int utmip_pad_count;
576
577 struct tegra_xtal_freq {
578         int freq;
579         u8 enable_delay;
580         u8 stable_count;
581         u8 active_delay;
582         u16 xtal_freq_count;
583         u16 debounce;
584         u8 pdtrk_count;
585 };
586
587 static const struct tegra_xtal_freq tegra_freq_table[] = {
588         {
589                 .freq = 12000000,
590                 .enable_delay = 0x02,
591                 .stable_count = 0x2F,
592                 .active_delay = 0x04,
593                 .xtal_freq_count = 0x76,
594                 .debounce = 0x7530,
595                 .pdtrk_count = 5,
596         },
597         {
598                 .freq = 13000000,
599                 .enable_delay = 0x02,
600                 .stable_count = 0x33,
601                 .active_delay = 0x05,
602                 .xtal_freq_count = 0x7F,
603                 .debounce = 0x7EF4,
604                 .pdtrk_count = 5,
605         },
606         {
607                 .freq = 19200000,
608                 .enable_delay = 0x03,
609                 .stable_count = 0x4B,
610                 .active_delay = 0x06,
611                 .xtal_freq_count = 0xBB,
612                 .debounce = 0xBB80,
613                 .pdtrk_count = 7,
614         },
615         {
616                 .freq = 26000000,
617                 .enable_delay = 0x04,
618                 .stable_count = 0x66,
619                 .active_delay = 0x09,
620                 .xtal_freq_count = 0xFE,
621                 .debounce = 0xFDE8,
622                 .pdtrk_count = 9,
623         },
624 };
625
626 static const struct tegra_xtal_freq tegra_uhsic_freq_table[] = {
627         {
628                 .freq = 12000000,
629                 .enable_delay = 0x02,
630                 .stable_count = 0x2F,
631                 .active_delay = 0x0,
632                 .xtal_freq_count = 0x1CA,
633         },
634         {
635                 .freq = 13000000,
636                 .enable_delay = 0x02,
637                 .stable_count = 0x33,
638                 .active_delay = 0x0,
639                 .xtal_freq_count = 0x1F0,
640         },
641         {
642                 .freq = 19200000,
643                 .enable_delay = 0x03,
644                 .stable_count = 0x4B,
645                 .active_delay = 0x0,
646                 .xtal_freq_count = 0x2DD,
647         },
648         {
649                 .freq = 26000000,
650                 .enable_delay = 0x04,
651                 .stable_count = 0x66,
652                 .active_delay = 0x0,
653                 .xtal_freq_count = 0x3E0,
654         },
655 };
656
657 static struct tegra_utmip_config utmip_default[] = {
658         [0] = {
659                 .hssync_start_delay = 9,
660                 .idle_wait_delay = 17,
661                 .elastic_limit = 16,
662                 .term_range_adj = 6,
663                 .xcvr_setup = 9,
664                 .xcvr_setup_offset = 0,
665                 .xcvr_use_fuses = 1,
666                 .xcvr_lsfslew = 2,
667                 .xcvr_lsrslew = 2,
668         },
669         [2] = {
670                 .hssync_start_delay = 9,
671                 .idle_wait_delay = 17,
672                 .elastic_limit = 16,
673                 .term_range_adj = 6,
674                 .xcvr_setup_offset = 0,
675                 .xcvr_use_fuses = 1,
676                 .xcvr_setup = 9,
677                 .xcvr_lsfslew = 2,
678                 .xcvr_lsrslew = 2,
679         },
680 };
681
682 struct usb_phy_plat_data usb_phy_data[] = {
683         { 0, 0, -1, NULL},
684         { 0, 0, -1, NULL},
685         { 0, 0, -1, NULL},
686 };
687
688 static int utmip_pad_open(struct tegra_usb_phy *phy)
689 {
690         phy->pad_clk = clk_get_sys("utmip-pad", NULL);
691         if (IS_ERR(phy->pad_clk)) {
692                 pr_err("%s: can't get utmip pad clock\n", __func__);
693                 return PTR_ERR(phy->pad_clk);
694         }
695
696         if (phy->instance == 0) {
697                 phy->pad_regs = phy->regs;
698         } else {
699                 phy->pad_regs = ioremap(TEGRA_USB_BASE, TEGRA_USB_SIZE);
700                 if (!phy->pad_regs) {
701                         pr_err("%s: can't remap usb registers\n", __func__);
702                         clk_put(phy->pad_clk);
703                         return -ENOMEM;
704                 }
705         }
706         return 0;
707 }
708
709 static void utmip_pad_close(struct tegra_usb_phy *phy)
710 {
711         if (phy->instance != 0)
712                 iounmap(phy->pad_regs);
713         clk_put(phy->pad_clk);
714 }
715
716 static int utmip_pad_power_on(struct tegra_usb_phy *phy)
717 {
718         unsigned long val, flags;
719         void __iomem *base = phy->pad_regs;
720
721         clk_enable(phy->pad_clk);
722
723         spin_lock_irqsave(&utmip_pad_lock, flags);
724
725         utmip_pad_count++;
726         val = readl(base + UTMIP_BIAS_CFG0);
727         val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
728 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
729         val |= UTMIP_HSSQUELCH_LEVEL(0x2) | UTMIP_HSDISCON_LEVEL(0x1) |
730                 UTMIP_HSDISCON_LEVEL_MSB;
731 #endif
732         writel(val, base + UTMIP_BIAS_CFG0);
733
734         spin_unlock_irqrestore(&utmip_pad_lock, flags);
735
736         clk_disable(phy->pad_clk);
737
738         return 0;
739 }
740
741 static int utmip_pad_power_off(struct tegra_usb_phy *phy, bool is_dpd)
742 {
743         unsigned long val, flags;
744         void __iomem *base = phy->pad_regs;
745
746         if (!utmip_pad_count) {
747                 pr_err("%s: utmip pad already powered off\n", __func__);
748                 return -EINVAL;
749         }
750
751         clk_enable(phy->pad_clk);
752
753         spin_lock_irqsave(&utmip_pad_lock, flags);
754
755         if (--utmip_pad_count == 0 && is_dpd) {
756                 val = readl(base + UTMIP_BIAS_CFG0);
757                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
758 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
759                 val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) | UTMIP_HSDISCON_LEVEL(~0) |
760                         UTMIP_HSDISCON_LEVEL_MSB);
761 #endif
762                 writel(val, base + UTMIP_BIAS_CFG0);
763         }
764
765         spin_unlock_irqrestore(&utmip_pad_lock, flags);
766
767         clk_disable(phy->pad_clk);
768
769         return 0;
770 }
771
772 static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result)
773 {
774         unsigned long timeout = 2500;
775         do {
776                 if ((readl(reg) & mask) == result)
777                         return 0;
778                 udelay(1);
779                 timeout--;
780         } while (timeout);
781         return -1;
782 }
783
784 static void utmi_phy_clk_disable(struct tegra_usb_phy *phy)
785 {
786         unsigned long val;
787         void __iomem *base = phy->regs;
788 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
789         if (phy->instance == 0) {
790                 val = readl(base + USB_SUSP_CTRL);
791                 val |= USB_SUSP_SET;
792                 writel(val, base + USB_SUSP_CTRL);
793
794                 udelay(10);
795
796                 val = readl(base + USB_SUSP_CTRL);
797                 val &= ~USB_SUSP_SET;
798                 writel(val, base + USB_SUSP_CTRL);
799         }
800
801         if (phy->instance == 2) {
802                 val = readl(base + USB_PORTSC1);
803                 val |= USB_PORTSC1_PHCD;
804                 writel(val, base + USB_PORTSC1);
805         }
806 #else
807         val = readl(base + HOSTPC1_DEVLC);
808         val |= HOSTPC1_DEVLC_PHCD;
809         writel(val, base + HOSTPC1_DEVLC);
810 #endif
811
812         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0)
813                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
814 }
815
816 static void utmi_phy_clk_enable(struct tegra_usb_phy *phy)
817 {
818         unsigned long val;
819         void __iomem *base = phy->regs;
820
821         if (phy->instance == 0) {
822                 val = readl(base + USB_SUSP_CTRL);
823                 val |= USB_SUSP_CLR;
824                 writel(val, base + USB_SUSP_CTRL);
825
826                 udelay(10);
827
828                 val = readl(base + USB_SUSP_CTRL);
829                 val &= ~USB_SUSP_CLR;
830                 writel(val, base + USB_SUSP_CTRL);
831         }
832
833 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
834         if (phy->instance == 2) {
835                 val = readl(base + USB_PORTSC1);
836                 val &= ~USB_PORTSC1_PHCD;
837                 writel(val, base + USB_PORTSC1);
838         }
839 #endif
840
841         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
842                                                      USB_PHY_CLK_VALID) < 0)
843                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
844 }
845
846 static void vbus_enable(struct tegra_usb_phy *phy)
847 {
848 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
849         int gpio_status;
850         int gpio = usb_phy_data[phy->instance].vbus_gpio;
851
852         if (gpio == -1)
853                 return;
854
855         gpio_status = gpio_request(gpio,"VBUS_USB");
856         if (gpio_status < 0) {
857                 printk("VBUS_USB request GPIO FAILED\n");
858                 WARN_ON(1);
859                 return;
860         }
861         tegra_gpio_enable(gpio);
862         gpio_status = gpio_direction_output(gpio, 1);
863         if (gpio_status < 0) {
864                 printk("VBUS_USB request GPIO DIRECTION FAILED \n");
865                 WARN_ON(1);
866                 return;
867         }
868         gpio_set_value(gpio, 1);
869 #else
870         if (phy->reg_vbus)
871                 regulator_enable(phy->reg_vbus);
872 #endif
873 }
874
875 static void vbus_disable(struct tegra_usb_phy *phy)
876 {
877 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
878         int gpio = usb_phy_data[phy->instance].vbus_gpio;
879
880         if (gpio == -1)
881                 return;
882
883         gpio_set_value(gpio, 0);
884         gpio_free(gpio);
885 #else
886         if (phy->reg_vbus)
887                 regulator_disable(phy->reg_vbus);
888 #endif
889 }
890
891 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
892 static void utmip_phy_enable_trking_data(struct tegra_usb_phy *phy)
893 {
894         void __iomem *base = phy->pad_regs;
895         void __iomem *pmc_base = IO_ADDRESS(TEGRA_USB_BASE);
896         static bool init_done = false;
897         u32 val;
898
899         /* Should be done only once after system boot */
900         if (init_done)
901                 return;
902
903         clk_enable(phy->pad_clk);
904         /* Bias pad MASTER_ENABLE=1 */
905         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
906         val |= BIAS_MASTER_PROG_VAL;
907         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
908
909         /* Setting the tracking length time */
910         val = readl(base + UTMIP_BIAS_CFG1);
911         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
912         val |= UTMIP_BIAS_PDTRK_COUNT(5);
913         writel(val, base + UTMIP_BIAS_CFG1);
914
915         /* Bias PDTRK is Shared and MUST be done from USB1 ONLY, PD_TRK=0 */
916         val = readl(base + UTMIP_BIAS_CFG1);
917         val &= ~ UTMIP_BIAS_PDTRK_POWERDOWN;
918         writel(val, base + UTMIP_BIAS_CFG1);
919
920         val = readl(base + UTMIP_BIAS_CFG1);
921         val |= UTMIP_BIAS_PDTRK_POWERUP;
922         writel(val, base + UTMIP_BIAS_CFG1);
923
924         /* Wait for 25usec */
925         udelay(25);
926
927         /* Bias pad MASTER_ENABLE=0 */
928         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
929         val &= ~BIAS_MASTER_PROG_VAL;
930         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
931
932         /* Wait for 1usec */
933         udelay(1);
934
935         /* Bias pad MASTER_ENABLE=1 */
936         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
937         val |= BIAS_MASTER_PROG_VAL;
938         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
939
940         /* Read RCTRL and TCTRL from UTMIP space */
941         val = readl(base + UTMIP_BIAS_STS0);
942         utmip_rctrl_val = ffz(UTMIP_RCTRL_VAL(val));
943         utmip_tctrl_val = ffz(UTMIP_TCTRL_VAL(val));
944
945         /* PD_TRK=1 */
946         val = readl(base + UTMIP_BIAS_CFG1);
947         val |= UTMIP_BIAS_PDTRK_POWERDOWN;
948         writel(val, base + UTMIP_BIAS_CFG1);
949
950         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
951         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
952         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
953         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
954         clk_disable(phy->pad_clk);
955         init_done = true;
956 }
957 #endif
958
959 static unsigned int tegra_phy_xcvr_setup_value(struct tegra_utmip_config *cfg)
960 {
961         unsigned long val;
962
963         if (cfg->xcvr_use_fuses) {
964                 val = FUSE_USB_CALIB_XCVR_SETUP(
965                                 tegra_fuse_readl(FUSE_USB_CALIB_0));
966                 if (cfg->xcvr_setup_offset <= UTMIP_XCVR_MAX_OFFSET)
967                         val = val + cfg->xcvr_setup_offset;
968
969                 if (val > UTMIP_XCVR_SETUP_MAX_VALUE) {
970                         val = UTMIP_XCVR_SETUP_MAX_VALUE;
971                         pr_info("%s: reset XCVR_SETUP to max value\n",
972                                  __func__);
973                 }
974         } else {
975                 val = cfg->xcvr_setup;
976         }
977
978         return val;
979 }
980
981 static int utmi_phy_power_on(struct tegra_usb_phy *phy, bool is_dpd)
982 {
983         unsigned long val;
984         void __iomem *base = phy->regs;
985         unsigned int xcvr_setup_value;
986         struct tegra_utmip_config *config = phy->config;
987
988         val = readl(base + USB_SUSP_CTRL);
989         val |= UTMIP_RESET;
990         writel(val, base + USB_SUSP_CTRL);
991
992 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
993         if (phy->instance == 0) {
994                 val = readl(base + USB1_LEGACY_CTRL);
995                 val |= USB1_NO_LEGACY_MODE;
996                 writel(val, base + USB1_LEGACY_CTRL);
997         }
998 #endif
999
1000         val = readl(base + UTMIP_TX_CFG0);
1001         val |= UTMIP_FS_PREABMLE_J;
1002         writel(val, base + UTMIP_TX_CFG0);
1003
1004         val = readl(base + UTMIP_HSRX_CFG0);
1005         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
1006         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
1007         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
1008         writel(val, base + UTMIP_HSRX_CFG0);
1009
1010         val = readl(base + UTMIP_HSRX_CFG1);
1011         val &= ~UTMIP_HS_SYNC_START_DLY(~0);
1012         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
1013         writel(val, base + UTMIP_HSRX_CFG1);
1014
1015         val = readl(base + UTMIP_DEBOUNCE_CFG0);
1016         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
1017         val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
1018         writel(val, base + UTMIP_DEBOUNCE_CFG0);
1019
1020         val = readl(base + UTMIP_MISC_CFG0);
1021         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
1022         writel(val, base + UTMIP_MISC_CFG0);
1023
1024 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1025         val = readl(base + UTMIP_MISC_CFG1);
1026         val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) | UTMIP_PLLU_STABLE_COUNT(~0));
1027         val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |
1028                 UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count);
1029         writel(val, base + UTMIP_MISC_CFG1);
1030
1031         val = readl(base + UTMIP_PLL_CFG1);
1032         val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) | UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
1033         val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |
1034                 UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
1035         writel(val, base + UTMIP_PLL_CFG1);
1036 #endif
1037
1038         if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) {
1039                 val = readl(base + USB_SUSP_CTRL);
1040                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
1041                 writel(val, base + USB_SUSP_CTRL);
1042         }
1043
1044         utmip_pad_power_on(phy);
1045
1046         xcvr_setup_value = tegra_phy_xcvr_setup_value(config);
1047
1048         val = readl(base + UTMIP_XCVR_CFG0);
1049         val &= ~(UTMIP_XCVR_LSBIAS_SEL | UTMIP_FORCE_PD_POWERDOWN |
1050                  UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN |
1051                  UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_LSFSLEW(~0) |
1052                  UTMIP_XCVR_LSRSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
1053         val |= UTMIP_XCVR_SETUP(xcvr_setup_value);
1054         val |= UTMIP_XCVR_SETUP_MSB(XCVR_SETUP_MSB_CALIB(xcvr_setup_value));
1055         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
1056         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
1057 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1058         val |= UTMIP_XCVR_HSSLEW_MSB(0x8);
1059 #endif
1060         writel(val, base + UTMIP_XCVR_CFG0);
1061
1062         val = readl(base + UTMIP_XCVR_CFG1);
1063         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1064                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
1065         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
1066         writel(val, base + UTMIP_XCVR_CFG1);
1067
1068         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1069         if (phy->mode == TEGRA_USB_PHY_MODE_HOST)
1070                 val |= UTMIP_PD_CHRG;
1071         else
1072                 val &= ~UTMIP_PD_CHRG;
1073         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1074
1075         val = readl(base + UTMIP_BIAS_CFG1);
1076         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
1077         val |= UTMIP_BIAS_PDTRK_COUNT(phy->freq->pdtrk_count);
1078         writel(val, base + UTMIP_BIAS_CFG1);
1079
1080 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1081         val = readl(base + UTMIP_SPARE_CFG0);
1082         val &= ~FUSE_SETUP_SEL;
1083         writel(val, base + UTMIP_SPARE_CFG0);
1084
1085         if (phy->instance == 2) {
1086                 val = readl(base + UTMIP_SPARE_CFG0);
1087                 val |= FUSE_SETUP_SEL;
1088                 writel(val, base + UTMIP_SPARE_CFG0);
1089
1090                 val = readl(base + USB_SUSP_CTRL);
1091                 val |= UTMIP_PHY_ENABLE;
1092                 writel(val, base + USB_SUSP_CTRL);
1093         }
1094 #else
1095         val = readl(base + UTMIP_SPARE_CFG0);
1096         val &= ~FUSE_SETUP_SEL;
1097         val |= FUSE_ATERM_SEL;
1098         writel(val, base + UTMIP_SPARE_CFG0);
1099
1100         val = readl(base + USB_SUSP_CTRL);
1101         val |= UTMIP_PHY_ENABLE;
1102         writel(val, base + USB_SUSP_CTRL);
1103 #endif
1104
1105         val = readl(base + USB_SUSP_CTRL);
1106         val &= ~UTMIP_RESET;
1107         writel(val, base + USB_SUSP_CTRL);
1108
1109         if (phy->instance == 0) {
1110                 val = readl(base + USB1_LEGACY_CTRL);
1111                 val &= ~USB1_VBUS_SENSE_CTL_MASK;
1112                 val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD;
1113                 writel(val, base + USB1_LEGACY_CTRL);
1114
1115 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1116                 val = readl(base + USB_SUSP_CTRL);
1117                 val &= ~USB_SUSP_SET;
1118                 writel(val, base + USB_SUSP_CTRL);
1119 #endif
1120         }
1121
1122         utmi_phy_clk_enable(phy);
1123 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1124         if (phy->instance == 2) {
1125                 val = readl(base + USB_PORTSC1);
1126                 val &= ~USB_PORTSC1_PTS(~0);
1127                 writel(val, base + USB_PORTSC1);
1128         }
1129 #else
1130         if (phy->instance == 0)
1131                 utmip_phy_enable_trking_data(phy);
1132
1133         if(phy->instance == 2) {
1134                 writel(0, base + ICUSB_CTRL);
1135         }
1136
1137         if (phy->mode == TEGRA_USB_PHY_MODE_HOST) {
1138                 val = readl(base + TEGRA_USB_USBMODE_REG_OFFSET);
1139                 writel((val | TEGRA_USB_USBMODE_HOST),
1140                         (base + TEGRA_USB_USBMODE_REG_OFFSET));
1141         }
1142         val = readl(base + HOSTPC1_DEVLC);
1143         val &= ~HOSTPC1_DEVLC_PTS(~0);
1144         val |= HOSTPC1_DEVLC_STS;
1145         writel(val, base + HOSTPC1_DEVLC);
1146 #endif
1147
1148         return 0;
1149 }
1150
1151 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1152 static void utmip_setup_pmc_wake_detect(struct tegra_usb_phy *phy)
1153 {
1154         unsigned long val, pmc_pad_cfg_val;
1155         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1156         unsigned  int inst = phy->instance;
1157         void __iomem *base = phy->regs;
1158         bool port_connected;
1159         enum tegra_usb_phy_port_speed port_speed;
1160
1161         /* check for port connect status */
1162         val = readl(base + USB_PORTSC1);
1163         port_connected = val & USB_PORTSC1_CCS;
1164
1165         if (!port_connected)
1166                 return;
1167
1168         port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
1169                 HOSTPC1_DEVLC_PSPD_MASK;
1170         /*Set PMC MASTER bits to do the following
1171         * a. Take over the UTMI drivers
1172         * b. set up such that it will take over resume
1173         *    if remote wakeup is detected
1174         * Prepare PMC to take over suspend-wake detect-drive resume until USB
1175         * controller ready
1176         */
1177
1178         /* disable master enable in PMC */
1179         val = readl(pmc_base + PMC_SLEEP_CFG);
1180         val &= ~UTMIP_MASTER_ENABLE(inst);
1181         writel(val, pmc_base + PMC_SLEEP_CFG);
1182
1183         /* UTMIP_PWR_PX=1 for power savings mode */
1184         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
1185         val |= UTMIP_PWR(inst);
1186         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
1187
1188         /* config debouncer */
1189         val = readl(pmc_base + PMC_USB_DEBOUNCE);
1190         val &= ~UTMIP_LINE_DEB_CNT(~0);
1191         val |= UTMIP_LINE_DEB_CNT(1);
1192         writel(val, pmc_base + PMC_USB_DEBOUNCE);
1193
1194         /* Make sure nothing is happening on the line with respect to PMC */
1195         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
1196         val &= ~USBOP_VAL(inst);
1197         val &= ~USBON_VAL(inst);
1198         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
1199
1200         /* Make sure wake value for line is none */
1201         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
1202         val &= ~UTMIP_LINEVAL_WALK_EN(inst);
1203         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
1204         val = readl(pmc_base + PMC_SLEEP_CFG);
1205         val &= ~UTMIP_WAKE_VAL(inst, ~0);
1206         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
1207         writel(val, pmc_base + PMC_SLEEP_CFG);
1208
1209         /* turn off pad detectors */
1210         val = readl(pmc_base + PMC_USB_AO);
1211         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
1212         writel(val, pmc_base + PMC_USB_AO);
1213
1214         /* Remove fake values and make synchronizers work a bit */
1215         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
1216         val &= ~USBOP_VAL(inst);
1217         val &= ~USBON_VAL(inst);
1218         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
1219
1220         /* Enable which type of event can trigger a walk,
1221         in this case usb_line_wake */
1222         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
1223         val |= UTMIP_LINEVAL_WALK_EN(inst);
1224         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
1225
1226         /* Enable which type of event can trigger a walk,
1227         * in this case usb_line_wake */
1228         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
1229         val |= UTMIP_LINEVAL_WALK_EN(inst);
1230         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
1231
1232         /* Clear the walk pointers and wake alarm */
1233         val = readl(pmc_base + PMC_TRIGGERS);
1234         val |= UTMIP_CLR_WAKE_ALARM(inst) | UTMIP_CLR_WALK_PTR(inst);
1235         writel(val, pmc_base + PMC_TRIGGERS);
1236
1237
1238         /* Capture FS/LS pad configurations */
1239         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
1240         val = readl(pmc_base + PMC_TRIGGERS);
1241         val |= UTMIP_CAP_CFG(inst);
1242         writel(val, pmc_base + PMC_TRIGGERS);
1243         udelay(1);
1244         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
1245
1246         /* BIAS MASTER_ENABLE=0 */
1247         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
1248         val &= ~BIAS_MASTER_PROG_VAL;
1249         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
1250
1251         /* program walk sequence, maintain a J, followed by a driven K
1252         * to signal a resume once an wake event is detected */
1253         val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
1254         val &= ~UTMIP_AP_A;
1255         val |= UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A| UTMIP_AN_A | UTMIP_HIGHZ_A |
1256                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_AP_B |
1257                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_AP_C |
1258                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_AP_D;
1259         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
1260
1261         if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW) {
1262                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
1263                 val &= ~(UTMIP_AN_B | UTMIP_HIGHZ_B | UTMIP_AN_C |
1264                         UTMIP_HIGHZ_C | UTMIP_AN_D | UTMIP_HIGHZ_D);
1265                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
1266         } else {
1267                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
1268                 val &= ~(UTMIP_AP_B | UTMIP_HIGHZ_B | UTMIP_AP_C |
1269                         UTMIP_HIGHZ_C | UTMIP_AP_D | UTMIP_HIGHZ_D);
1270                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
1271         }
1272
1273         /* turn on pad detectors */
1274         val = readl(pmc_base + PMC_USB_AO);
1275         val &= ~(USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
1276         writel(val, pmc_base + PMC_USB_AO);
1277
1278         /* Add small delay before usb detectors provide stable line values */
1279         udelay(1);
1280
1281         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
1282         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
1283         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
1284         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
1285
1286         phy->remote_wakeup = false;
1287
1288         /* Turn over pad configuration to PMC  for line wake events*/
1289         val = readl(pmc_base + PMC_SLEEP_CFG);
1290         val &= ~UTMIP_WAKE_VAL(inst, ~0);
1291         if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
1292                 val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_FSJ);
1293         else
1294                 val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_FSK);
1295         val |= UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst);
1296         val |= UTMIP_MASTER_ENABLE(inst) | UTMIP_FSLS_USE_PMC(inst);
1297         writel(val, pmc_base + PMC_SLEEP_CFG);
1298
1299         val = readl(base + UTMIP_PMC_WAKEUP0);
1300         val |= EVENT_INT_ENB;
1301         writel(val, base + UTMIP_PMC_WAKEUP0);
1302 }
1303 #endif
1304
1305 static int utmi_phy_power_off(struct tegra_usb_phy *phy, bool is_dpd)
1306 {
1307         unsigned long val;
1308         void __iomem *base = phy->regs;
1309
1310 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1311         if (phy->mode == TEGRA_USB_PHY_MODE_HOST)
1312                 utmip_setup_pmc_wake_detect(phy);
1313 #endif
1314         if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) {
1315                 val = readl(base + USB_SUSP_CTRL);
1316                 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
1317                 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
1318                 writel(val, base + USB_SUSP_CTRL);
1319         }
1320
1321         if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) {
1322                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1323                 val |= UTMIP_PD_CHRG;
1324                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1325         }
1326
1327         if (phy->instance != 2) {
1328                 val = readl(base + UTMIP_XCVR_CFG0);
1329                 val |= (UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
1330                          UTMIP_FORCE_PDZI_POWERDOWN);
1331                 writel(val, base + UTMIP_XCVR_CFG0);
1332         }
1333         val = readl(base + UTMIP_XCVR_CFG1);
1334         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1335                UTMIP_FORCE_PDDR_POWERDOWN;
1336         writel(val, base + UTMIP_XCVR_CFG1);
1337
1338 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1339         val = readl(base + UTMIP_BIAS_CFG1);
1340         val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
1341         writel(val, base + UTMIP_BIAS_CFG1);
1342 #endif
1343
1344         if (phy->instance == 2) {
1345                 val = readl(base + USB_PORTSC1);
1346                 val |= USB_PORTSC1_WKCN;
1347                 writel(val, base + USB_PORTSC1);
1348         }
1349         if (phy->instance != 0) {
1350                 val = readl(base + UTMIP_BIAS_CFG0);
1351                 val |= UTMIP_OTGPD;
1352                 writel(val, base + UTMIP_BIAS_CFG0);
1353         }
1354
1355         utmi_phy_clk_disable(phy);
1356
1357         if (phy->instance == 2) {
1358                 val = readl(base + USB_SUSP_CTRL);
1359                 val |= USB_PHY_CLK_VALID_INT_ENB;
1360                 writel(val, base + USB_SUSP_CTRL);
1361         } else {
1362                 val = readl(base + USB_SUSP_CTRL);
1363                 val |= UTMIP_RESET;
1364                 writel(val, base + USB_SUSP_CTRL);
1365         }
1366         utmip_pad_power_off(phy, true);
1367         return 0;
1368 }
1369
1370 static void utmip_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy)
1371 {
1372 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1373         unsigned long val;
1374         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1375         unsigned  int inst = phy->instance;
1376         void __iomem *base = phy->regs;
1377
1378         val = readl(pmc_base + PMC_SLEEP_CFG);
1379         val &= ~UTMIP_WAKE_VAL(inst, 0x0);
1380         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
1381         writel(val, pmc_base + PMC_SLEEP_CFG);
1382
1383         val = readl(pmc_base + PMC_TRIGGERS);
1384         val |= UTMIP_CLR_WAKE_ALARM(inst) | UTMIP_CLR_WALK_PTR(inst);
1385         writel(val, pmc_base + PMC_TRIGGERS);
1386
1387         val = readl(base + UTMIP_PMC_WAKEUP0);
1388         val &= ~EVENT_INT_ENB;
1389         writel(val, base + UTMIP_PMC_WAKEUP0);
1390
1391         /* Disable PMC master mode by clearing MASTER_EN */
1392         val = readl(pmc_base + PMC_SLEEP_CFG);
1393         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
1394                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
1395         writel(val, pmc_base + PMC_SLEEP_CFG);
1396
1397         val = readl(pmc_base + PMC_TRIGGERS);
1398         val &= ~UTMIP_CAP_CFG(inst);
1399         writel(val, pmc_base + PMC_TRIGGERS);
1400
1401         /* turn off pad detectors */
1402         val = readl(pmc_base + PMC_USB_AO);
1403         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
1404         writel(val, pmc_base + PMC_USB_AO);
1405
1406         phy->remote_wakeup = false;
1407 #endif
1408 }
1409
1410 static int utmi_phy_preresume(struct tegra_usb_phy *phy, bool is_dpd)
1411 {
1412 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1413         unsigned long val;
1414         void __iomem *base = phy->regs;
1415         val = readl(base + UTMIP_TX_CFG0);
1416         val |= UTMIP_HS_DISCON_DISABLE;
1417         writel(val, base + UTMIP_TX_CFG0);
1418 #else
1419         utmip_phy_disable_pmc_bus_ctrl(phy);
1420 #endif
1421
1422         return 0;
1423 }
1424
1425 static int utmi_phy_postresume(struct tegra_usb_phy *phy, bool is_dpd)
1426 {
1427         unsigned long val;
1428         void __iomem *base = phy->regs;
1429
1430 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1431         /* check if OBS bus is already enabled */
1432         val = readl(base + UTMIP_MISC_CFG0);
1433         if (val & UTMIP_DPDM_OBSERVE) {
1434                 /* Change the UTMIP OBS bus to drive SE0 */
1435                 val = readl(base + UTMIP_MISC_CFG0);
1436                 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1437                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_SE0;
1438                 writel(val, base + UTMIP_MISC_CFG0);
1439
1440                 /* Wait for 3us(2 LS bit times) */
1441                 udelay (3);
1442
1443                 /* Release UTMIP OBS bus */
1444                 val = readl(base + UTMIP_MISC_CFG0);
1445                 val &= ~UTMIP_DPDM_OBSERVE;
1446                 writel(val, base + UTMIP_MISC_CFG0);
1447
1448                 /* Release DP/DM pulldown for Host mode */
1449                 val = readl(base + UTMIP_MISC_CFG0);
1450                 val &= ~(FORCE_PULLDN_DM | FORCE_PULLDN_DP |
1451                                 COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS);
1452                 writel(val, base + UTMIP_MISC_CFG0);
1453         }
1454 #else
1455         val = readl(base + UTMIP_TX_CFG0);
1456         val &= ~UTMIP_HS_DISCON_DISABLE;
1457         writel(val, base + UTMIP_TX_CFG0);
1458 #endif
1459         return 0;
1460 }
1461
1462 static int uhsic_phy_postsuspend(struct tegra_usb_phy *phy, bool is_dpd)
1463 {
1464         struct tegra_uhsic_config *uhsic_config = phy->config;
1465
1466         if (uhsic_config->postsuspend)
1467                 uhsic_config->postsuspend();
1468
1469         return 0;
1470 }
1471
1472 static int uhsic_phy_preresume(struct tegra_usb_phy *phy, bool is_dpd)
1473 {
1474         struct tegra_uhsic_config *uhsic_config = phy->config;
1475
1476         if (uhsic_config->preresume)
1477                 uhsic_config->preresume();
1478
1479         return 0;
1480 }
1481
1482 static int uhsic_phy_postresume(struct tegra_usb_phy *phy, bool is_dpd)
1483 {
1484 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1485         unsigned long val;
1486         void __iomem *base = phy->regs;
1487
1488         val = readl(base + USB_TXFILLTUNING);
1489         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
1490                 val = USB_FIFO_TXFILL_THRES(0x10);
1491                 writel(val, base + USB_TXFILLTUNING);
1492         }
1493 #endif
1494
1495         return 0;
1496 }
1497
1498 static void utmi_phy_restore_start(struct tegra_usb_phy *phy,
1499                                    enum tegra_usb_phy_port_speed port_speed)
1500 {
1501 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1502         unsigned long val;
1503         void __iomem *base = phy->regs;
1504
1505         val = readl(base + UTMIP_MISC_CFG0);
1506         val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1507         if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
1508                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
1509         else
1510                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
1511         writel(val, base + UTMIP_MISC_CFG0);
1512         udelay(1);
1513
1514         val = readl(base + UTMIP_MISC_CFG0);
1515         val |= UTMIP_DPDM_OBSERVE;
1516         writel(val, base + UTMIP_MISC_CFG0);
1517         udelay(10);
1518 #else
1519         unsigned long val;
1520         void __iomem *base = phy->regs;
1521         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1522         int inst = phy->instance;
1523
1524         val = readl(pmc_base + UTMIP_UHSIC_STATUS);
1525         /* check whether we wake up from the remote resume */
1526         if (UTMIP_WALK_PTR_VAL(inst) & val) {
1527                 phy->remote_wakeup = true;
1528         } else {
1529                 if (!((UTMIP_USBON_VAL(phy->instance) |
1530                         UTMIP_USBOP_VAL(phy->instance)) & val)) {
1531                                 utmip_phy_disable_pmc_bus_ctrl(phy);
1532                 }
1533         }
1534
1535         /* (2LS WAR)is not required for LS and FS devices and is only for HS */
1536         if ((port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW) ||
1537                 (port_speed == TEGRA_USB_PHY_PORT_SPEED_FULL)) {
1538                 /* do not enable the OBS bus */
1539                 val = readl(base + UTMIP_MISC_CFG0);
1540                 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1541                 writel(val, base + UTMIP_MISC_CFG0);
1542                 return;
1543         }
1544         /* Force DP/DM pulldown active for Host mode */
1545         val = readl(base + UTMIP_MISC_CFG0);
1546         val |= FORCE_PULLDN_DM | FORCE_PULLDN_DP |
1547                         COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS;
1548         writel(val, base + UTMIP_MISC_CFG0);
1549         val = readl(base + UTMIP_MISC_CFG0);
1550         val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1551         if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
1552                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
1553         else
1554                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
1555         writel(val, base + UTMIP_MISC_CFG0);
1556         udelay(1);
1557
1558         val = readl(base + UTMIP_MISC_CFG0);
1559         val |= UTMIP_DPDM_OBSERVE;
1560         writel(val, base + UTMIP_MISC_CFG0);
1561         udelay(10);
1562 #endif
1563 }
1564
1565 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
1566 {
1567 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1568         unsigned long val;
1569         void __iomem *base = phy->regs;
1570
1571         val = readl(base + UTMIP_MISC_CFG0);
1572         val &= ~UTMIP_DPDM_OBSERVE;
1573         writel(val, base + UTMIP_MISC_CFG0);
1574         udelay(10);
1575 #else
1576         unsigned long val;
1577         void __iomem *base = phy->regs;
1578         int wait_time_us = 3000; /* FPR should be set by this time */
1579
1580         /* check whether we wake up from the remote resume */
1581         if (phy->remote_wakeup) {
1582                 /* wait until FPR bit is set automatically on remote resume */
1583                 do {
1584                         val = readl(base + USB_PORTSC1);
1585                         udelay(1);
1586                         if (wait_time_us == 0)
1587                                 return;
1588                         wait_time_us--;
1589                 } while (!(val & USB_PORTSC1_RESUME));
1590                 /* disable PMC master control */
1591                 utmip_phy_disable_pmc_bus_ctrl(phy);
1592                 /* wait for 25 ms to port resume complete */
1593                 msleep(25);
1594
1595                 /* Clear PCI and SRI bits to avoid an interrupt upon resume */
1596                 val = readl(base + USB_USBSTS);
1597                 writel(val, base + USB_USBSTS);
1598                 /* wait to avoid SOF if there is any */
1599                 if (utmi_wait_register(base + USB_USBSTS,
1600                         USB_USBSTS_SRI, USB_USBSTS_SRI) < 0) {
1601                         pr_err("%s: timeout waiting for SOF\n", __func__);
1602                 }
1603                 tegra_usb_phy_postresume(phy, false);
1604         }
1605 #endif
1606 }
1607
1608 static void ulpi_set_tristate(bool enable)
1609 {
1610         int tristate = (enable)? TEGRA_TRI_TRISTATE : TEGRA_TRI_NORMAL;
1611
1612 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1613         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAA, tristate);
1614         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAB, tristate);
1615         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UDA, tristate);
1616 #else
1617         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA0, tristate);
1618         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA1, tristate);
1619         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA2, tristate);
1620         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA3, tristate);
1621         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA4, tristate);
1622         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA5, tristate);
1623         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA6, tristate);
1624         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA7, tristate);
1625         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_CLK, tristate);
1626         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR, tristate);
1627         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_STP, tristate);
1628         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_NXT, tristate);
1629 #endif
1630 }
1631
1632 static void ulpi_phy_reset(void __iomem *base)
1633 {
1634         unsigned long val;
1635
1636         val = readl(base + USB_SUSP_CTRL);
1637         val |= UHSIC_RESET;
1638         writel(val, base + USB_SUSP_CTRL);
1639
1640 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1641         val = readl(base + USB_SUSP_CTRL);
1642         val |= UTMIP_RESET;
1643         writel(val, base + USB_SUSP_CTRL);
1644 #endif
1645 }
1646
1647 static void ulpi_set_host(void __iomem *base)
1648 {
1649 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1650         unsigned long val;
1651
1652         val = readl(base + TEGRA_USB_USBMODE_REG_OFFSET);
1653         val |= TEGRA_USB_USBMODE_HOST;
1654         writel(val, base + TEGRA_USB_USBMODE_REG_OFFSET);
1655
1656         val = readl(base + HOSTPC1_DEVLC);
1657         val |= HOSTPC1_DEVLC_PTS(2);
1658         writel(val, base + HOSTPC1_DEVLC);
1659 #endif
1660 }
1661
1662 static void ulpi_set_trimmer(void __iomem *base, u8 data, u8 sdn, u8 dir)
1663 {
1664         unsigned long val;
1665
1666         val = ULPI_DATA_TRIMMER_SEL(data);
1667         val |= ULPI_STPDIRNXT_TRIMMER_SEL(sdn);
1668         val |= ULPI_DIR_TRIMMER_SEL(dir);
1669         writel(val, base + ULPI_TIMING_CTRL_1);
1670         udelay(10);
1671
1672         val |= ULPI_DATA_TRIMMER_LOAD;
1673         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
1674         val |= ULPI_DIR_TRIMMER_LOAD;
1675         writel(val, base + ULPI_TIMING_CTRL_1);
1676 }
1677
1678 static void ulpi_phy_restore_start(struct tegra_usb_phy *phy,
1679                                    enum tegra_usb_phy_port_speed port_speed)
1680 {
1681 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1682         unsigned long val;
1683         void __iomem *base = phy->regs;
1684
1685         /*Tristate ulpi interface before USB controller resume*/
1686         ulpi_set_tristate(true);
1687
1688         val = readl(base + ULPI_TIMING_CTRL_0);
1689         val &= ~ULPI_OUTPUT_PINMUX_BYP;
1690         writel(val, base + ULPI_TIMING_CTRL_0);
1691 #endif
1692 }
1693
1694 static void ulpi_phy_restore_end(struct tegra_usb_phy *phy)
1695 {
1696 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1697         unsigned long val;
1698         void __iomem *base = phy->regs;
1699
1700         val = readl(base + ULPI_TIMING_CTRL_0);
1701         val |= ULPI_OUTPUT_PINMUX_BYP;
1702         writel(val, base + ULPI_TIMING_CTRL_0);
1703
1704         ulpi_set_tristate(false);
1705 #endif
1706 }
1707
1708 static int ulpi_phy_power_on(struct tegra_usb_phy *phy, bool is_dpd)
1709 {
1710         int ret;
1711         unsigned long val;
1712         void __iomem *base = phy->regs;
1713 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1714         struct tegra_ulpi_config *config = phy->config;
1715 #endif
1716
1717         if (phy->clk)
1718                 clk_enable(phy->clk);
1719
1720         msleep(1);
1721
1722         if (!phy->initialized) {
1723                 phy->initialized = 1;
1724 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1725                 gpio_direction_output(config->reset_gpio, 0);
1726                 msleep(5);
1727                 gpio_direction_output(config->reset_gpio, 1);
1728 #endif
1729         }
1730
1731         ulpi_phy_reset(base);
1732         ulpi_set_host(base);
1733
1734         val = readl(base + ULPI_TIMING_CTRL_0);
1735         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
1736         writel(val, base + ULPI_TIMING_CTRL_0);
1737
1738         val = readl(base + USB_SUSP_CTRL);
1739         val |= ULPI_PHY_ENABLE;
1740         writel(val, base + USB_SUSP_CTRL);
1741
1742         val = readl(base + USB_SUSP_CTRL);
1743         val |= USB_SUSP_CLR;
1744         writel(val, base + USB_SUSP_CTRL);
1745
1746 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1747         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
1748                                                      USB_PHY_CLK_VALID) < 0)
1749                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
1750
1751         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_CLKEN, USB_CLKEN) < 0)
1752                 pr_err("%s: timeout waiting for AHB clock\n", __func__);
1753 #else
1754         udelay(100);
1755 #endif
1756
1757         val = readl(base + USB_SUSP_CTRL);
1758         val &= ~USB_SUSP_CLR;
1759         writel(val, base + USB_SUSP_CTRL);
1760
1761         val = 0;
1762         writel(val, base + ULPI_TIMING_CTRL_1);
1763
1764         ulpi_set_trimmer(base, 4, 4, 4);
1765
1766         /* Fix VbusInvalid due to floating VBUS */
1767         ret = otg_io_write(phy->ulpi, 0x40, 0x08);
1768         if (ret) {
1769                 pr_err("%s: ulpi write failed\n", __func__);
1770                 return ret;
1771         }
1772
1773         ret = otg_io_write(phy->ulpi, 0x80, 0x0B);
1774         if (ret) {
1775                 pr_err("%s: ulpi write failed\n", __func__);
1776                 return ret;
1777         }
1778
1779         val = readl(base + USB_PORTSC1);
1780         val |= USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN;
1781         writel(val, base + USB_PORTSC1);
1782
1783         return 0;
1784 }
1785
1786 static int ulpi_phy_power_off(struct tegra_usb_phy *phy, bool is_dpd)
1787 {
1788         unsigned long val;
1789         void __iomem *base = phy->regs;
1790 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1791         int ret;
1792
1793         /* Disable VbusValid, SessEnd comparators */
1794         ret = otg_io_write(phy->ulpi, 0x00, 0x0D);
1795         if (ret)
1796                 pr_err("%s: ulpi write 0x0D failed\n", __func__);
1797
1798         ret = otg_io_write(phy->ulpi, 0x00, 0x10);
1799         if (ret)
1800                 pr_err("%s: ulpi write 0x10 failed\n", __func__);
1801
1802         /* Disable IdFloat comparator */
1803         ret = otg_io_write(phy->ulpi, 0x00, 0x19);
1804         if (ret)
1805                 pr_err("%s: ulpi write 0x19 failed\n", __func__);
1806
1807         ret = otg_io_write(phy->ulpi, 0x00, 0x1D);
1808         if (ret)
1809                 pr_err("%s: ulpi write 0x1D failed\n", __func__);
1810
1811         /* Clear WKCN/WKDS/WKOC wake-on events that can cause the USB
1812          * Controller to immediately bring the ULPI PHY out of low power
1813          */
1814         val = readl(base + USB_PORTSC1);
1815         val &= ~(USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN);
1816         writel(val, base + USB_PORTSC1);
1817
1818         /* Put the PHY in the low power mode */
1819         val = readl(base + USB_PORTSC1);
1820         val |= USB_PORTSC1_PHCD;
1821         writel(val, base + USB_PORTSC1);
1822
1823         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0)
1824                 pr_err("%s: timeout waiting for phy to stop\n", __func__);
1825 #else
1826         val = readl(base + HOSTPC1_DEVLC);
1827         val &= ~(HOSTPC1_DEVLC_PHCD);
1828         writel(val, base + HOSTPC1_DEVLC);
1829 #endif
1830
1831         if(phy->clk)
1832                 clk_disable(phy->clk);
1833
1834         return 0;
1835 }
1836
1837 static int null_phy_power_on(struct tegra_usb_phy *phy, bool is_dpd)
1838 {
1839         const struct tegra_ulpi_trimmer default_trimmer = {0, 0, 4, 4};
1840         unsigned long val;
1841         void __iomem *base = phy->regs;
1842         struct tegra_ulpi_config *config = phy->config;
1843
1844         if (!config->trimmer)
1845                 config->trimmer = &default_trimmer;
1846
1847         ulpi_phy_reset(base);
1848
1849 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1850         /* remove ULPI PADS CLKEN reset */
1851         val = readl(base + USB_SUSP_CTRL);
1852         val &= ~ULPI_PADS_CLKEN_RESET;
1853         writel(val, base + USB_SUSP_CTRL);
1854         udelay(10);
1855 #endif
1856         val = readl(base + ULPI_TIMING_CTRL_0);
1857         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
1858         writel(val, base + ULPI_TIMING_CTRL_0);
1859
1860         ulpi_set_tristate(false);
1861
1862         if (config->pre_phy_on && config->pre_phy_on())
1863                 return -EAGAIN;
1864
1865         val = readl(base + USB_SUSP_CTRL);
1866         val |= ULPI_PHY_ENABLE;
1867         writel(val, base + USB_SUSP_CTRL);
1868         udelay(10);
1869
1870         /* set timming parameters */
1871         val = readl(base + ULPI_TIMING_CTRL_0);
1872         val |= ULPI_SHADOW_CLK_LOOPBACK_EN;
1873         val &= ~ULPI_SHADOW_CLK_SEL;
1874         val &= ~ULPI_LBK_PAD_EN;
1875         val |= ULPI_SHADOW_CLK_DELAY(config->trimmer->shadow_clk_delay);
1876         val |= ULPI_CLOCK_OUT_DELAY(config->trimmer->clock_out_delay);
1877         val |= ULPI_LBK_PAD_E_INPUT_OR;
1878         writel(val, base + ULPI_TIMING_CTRL_0);
1879
1880         writel(0, base + ULPI_TIMING_CTRL_1);
1881         udelay(10);
1882
1883         /* start internal 60MHz clock */
1884         val = readl(base + ULPIS2S_CTRL);
1885         val |= ULPIS2S_ENA;
1886         val |= ULPIS2S_SUPPORT_DISCONNECT;
1887         val |= ULPIS2S_SPARE((phy->mode == TEGRA_USB_PHY_MODE_HOST) ? 3 : 1);
1888         val |= ULPIS2S_PLLU_MASTER_BLASTER60;
1889         writel(val, base + ULPIS2S_CTRL);
1890
1891         /* select ULPI_CORE_CLK_SEL to SHADOW_CLK */
1892         val = readl(base + ULPI_TIMING_CTRL_0);
1893         val |= ULPI_CORE_CLK_SEL;
1894         writel(val, base + ULPI_TIMING_CTRL_0);
1895         udelay(10);
1896
1897         /* enable ULPI null phy clock - can't set the trimmers before this */
1898         val = readl(base + ULPI_TIMING_CTRL_0);
1899         val |= ULPI_CLK_OUT_ENA;
1900         writel(val, base + ULPI_TIMING_CTRL_0);
1901         udelay(10);
1902
1903         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
1904                                                      USB_PHY_CLK_VALID)) {
1905                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
1906                 return -ETIMEDOUT;
1907         }
1908
1909         /* set ULPI trimmers */
1910         ulpi_set_trimmer(base, config->trimmer->data_trimmer,
1911                          config->trimmer->stpdirnxt_trimmer, 1);
1912
1913         ulpi_set_host(base);
1914
1915 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1916         /* remove slave0 reset */
1917         val = readl(base + USB_SUSP_CTRL);
1918         val &= ~ULPIS2S_SLV0_RESET;
1919         writel(val, base + USB_SUSP_CTRL);
1920
1921         /* remove slave1 and line reset */
1922         val = readl(base + USB_SUSP_CTRL);
1923         val &= ~ULPIS2S_SLV1_RESET;
1924         val &= ~ULPIS2S_LINE_RESET;
1925
1926         /* remove ULPI PADS reset */
1927         val &= ~ULPI_PADS_RESET;
1928         writel(val, base + USB_SUSP_CTRL);
1929 #endif
1930         val = readl(base + ULPI_TIMING_CTRL_0);
1931         val |= ULPI_CLK_PADOUT_ENA;
1932         writel(val, base + ULPI_TIMING_CTRL_0);
1933
1934         udelay(10);
1935
1936         if (config->post_phy_on && config->post_phy_on())
1937                 return -EAGAIN;
1938
1939         return 0;
1940 }
1941
1942 static int null_phy_power_off(struct tegra_usb_phy *phy, bool is_dpd)
1943 {
1944         unsigned long val;
1945         void __iomem *base = phy->regs;
1946         struct tegra_ulpi_config *config = phy->config;
1947
1948         if (config->pre_phy_off && config->pre_phy_off())
1949                 return -EAGAIN;
1950
1951         ulpi_set_tristate(true);
1952
1953         if (config->post_phy_off && config->post_phy_off())
1954                 return -EAGAIN;
1955
1956         return 0;
1957 }
1958
1959 static int null_phy_pre_usbcmd_reset(struct tegra_usb_phy *phy, bool is_dpd)
1960 {
1961 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1962         unsigned long val;
1963         void __iomem *base = phy->regs;
1964
1965         val = readl(base + ULPIS2S_CTRL);
1966         val |=  ULPIS2S_SLV0_CLAMP_XMIT;
1967         writel(val, base + ULPIS2S_CTRL);
1968
1969         val = readl(base + USB_SUSP_CTRL);
1970         val |= ULPIS2S_SLV0_RESET;
1971         writel(val, base + USB_SUSP_CTRL);
1972         udelay(10);
1973 #endif
1974         return 0;
1975 }
1976
1977 static int null_phy_post_usbcmd_reset(struct tegra_usb_phy *phy, bool is_dpd)
1978 {
1979 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1980         unsigned long val;
1981         void __iomem *base = phy->regs;
1982
1983         /* remove slave0 reset */
1984         val = readl(base + USB_SUSP_CTRL);
1985         val &= ~ULPIS2S_SLV0_RESET;
1986         writel(val, base + USB_SUSP_CTRL);
1987
1988         val = readl(base + ULPIS2S_CTRL);
1989         val &=  ~ULPIS2S_SLV0_CLAMP_XMIT;
1990         writel(val, base + ULPIS2S_CTRL);
1991         udelay(10);
1992
1993         ulpi_set_host(base);
1994 #endif
1995         return 0;
1996 }
1997
1998 static int uhsic_phy_power_on(struct tegra_usb_phy *phy, bool is_dpd)
1999 {
2000         unsigned long val;
2001         void __iomem *base = phy->regs;
2002         struct tegra_uhsic_config *uhsic_config = phy->config;
2003
2004         if (uhsic_config->enable_gpio != -1) {
2005                 gpio_set_value_cansleep(uhsic_config->enable_gpio, 1);
2006                 /* keep hsic reset asserted for 1 ms */
2007                 udelay(1000);
2008         }
2009
2010         val = readl(base + UHSIC_PADS_CFG1);
2011         val &= ~(UHSIC_PD_BG | UHSIC_PD_TX | UHSIC_PD_TRK | UHSIC_PD_RX |
2012                         UHSIC_PD_ZI | UHSIC_RPD_DATA | UHSIC_RPD_STROBE);
2013         val |= UHSIC_RX_SEL;
2014         writel(val, base + UHSIC_PADS_CFG1);
2015         udelay(2);
2016
2017         val = readl(base + USB_SUSP_CTRL);
2018         val |= UHSIC_RESET;
2019         writel(val, base + USB_SUSP_CTRL);
2020         udelay(30);
2021
2022         val = readl(base + USB_SUSP_CTRL);
2023         val |= UHSIC_PHY_ENABLE;
2024         writel(val, base + USB_SUSP_CTRL);
2025
2026         val = readl(base + UHSIC_HSRX_CFG0);
2027         val |= UHSIC_IDLE_WAIT(uhsic_config->idle_wait_delay);
2028         val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(uhsic_config->elastic_underrun_limit);
2029         val |= UHSIC_ELASTIC_OVERRUN_LIMIT(uhsic_config->elastic_overrun_limit);
2030         writel(val, base + UHSIC_HSRX_CFG0);
2031
2032         val = readl(base + UHSIC_HSRX_CFG1);
2033         val |= UHSIC_HS_SYNC_START_DLY(uhsic_config->sync_start_delay);
2034         writel(val, base + UHSIC_HSRX_CFG1);
2035
2036         val = readl(base + UHSIC_MISC_CFG0);
2037         val |= UHSIC_SUSPEND_EXIT_ON_EDGE;
2038         writel(val, base + UHSIC_MISC_CFG0);
2039
2040         val = readl(base + UHSIC_MISC_CFG1);
2041         val |= UHSIC_PLLU_STABLE_COUNT(phy->freq->stable_count);
2042         writel(val, base + UHSIC_MISC_CFG1);
2043
2044         val = readl(base + UHSIC_PLL_CFG1);
2045         val |= UHSIC_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
2046         val |= UHSIC_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count);
2047         writel(val, base + UHSIC_PLL_CFG1);
2048
2049         val = readl(base + USB_SUSP_CTRL);
2050         val &= ~(UHSIC_RESET);
2051         writel(val, base + USB_SUSP_CTRL);
2052         udelay(2);
2053
2054 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2055         val = readl(base + USB_PORTSC1);
2056         val &= ~USB_PORTSC1_PTS(~0);
2057         writel(val, base + USB_PORTSC1);
2058
2059         val = readl(base + USB_TXFILLTUNING);
2060         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
2061                 val = USB_FIFO_TXFILL_THRES(0x10);
2062                 writel(val, base + USB_TXFILLTUNING);
2063         }
2064 #endif
2065
2066         val = readl(base + USB_PORTSC1);
2067         val &= ~(USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN);
2068         writel(val, base + USB_PORTSC1);
2069
2070         val = readl(base + UHSIC_PADS_CFG0);
2071         val &= ~(UHSIC_TX_RTUNEN);
2072         /* set Rtune impedance to 40 ohm */
2073         val |= UHSIC_TX_RTUNE(0);
2074         writel(val, base + UHSIC_PADS_CFG0);
2075
2076         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
2077                                                         USB_PHY_CLK_VALID)) {
2078                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2079                 return -ETIMEDOUT;
2080         }
2081
2082         return 0;
2083 }
2084
2085 static int uhsic_phy_power_off(struct tegra_usb_phy *phy, bool is_dpd)
2086 {
2087         unsigned long val;
2088         void __iomem *base = phy->regs;
2089         struct tegra_uhsic_config *uhsic_config = phy->config;
2090
2091         val = readl(base + UHSIC_PADS_CFG1);
2092         val &= ~UHSIC_RPU_STROBE;
2093         val |= UHSIC_RPD_STROBE;
2094         writel(val, base + UHSIC_PADS_CFG1);
2095
2096         val = readl(base + USB_SUSP_CTRL);
2097         val |= UHSIC_RESET;
2098         writel(val, base + USB_SUSP_CTRL);
2099         udelay(30);
2100
2101         val = readl(base + USB_SUSP_CTRL);
2102         val &= ~UHSIC_PHY_ENABLE;
2103         writel(val, base + USB_SUSP_CTRL);
2104
2105         if (uhsic_config->enable_gpio != -1) {
2106                 gpio_set_value_cansleep(uhsic_config->enable_gpio, 0);
2107                 /* keep hsic reset de-asserted for 1 ms */
2108                 udelay(1000);
2109         }
2110
2111         return 0;
2112 }
2113
2114 #ifdef CONFIG_USB_TEGRA_OTG
2115 extern void tegra_otg_check_vbus_detection(void);
2116 #endif
2117
2118 static irqreturn_t usb_phy_vbus_irq_thr(int irq, void *pdata)
2119 {
2120         struct tegra_usb_phy *phy = pdata;
2121
2122         if (!phy->regulator_on) {
2123                 regulator_enable(phy->reg_vdd);
2124                 phy->regulator_on = 1;
2125                 /*
2126                  * Optimal time to get the regulator turned on
2127                  * before detecting vbus interrupt.
2128                  */
2129                 mdelay(15);
2130         }
2131
2132 #ifdef CONFIG_USB_TEGRA_OTG
2133         tegra_otg_check_vbus_detection();
2134 #endif
2135
2136         return IRQ_HANDLED;
2137 }
2138
2139 struct tegra_usb_phy *tegra_usb_phy_open(int instance, void __iomem *regs,
2140                         void *config, enum tegra_usb_phy_mode phy_mode,
2141                         enum tegra_usb_phy_type usb_phy_type)
2142 {
2143         struct tegra_usb_phy *phy;
2144         struct tegra_ulpi_config *ulpi_config;
2145         unsigned long parent_rate;
2146         int i;
2147         int err;
2148 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2149         struct tegra_ulpi_config *uhsic_config;
2150         int reset_gpio, enable_gpio;
2151 #endif
2152
2153         phy = kzalloc(sizeof(struct tegra_usb_phy), GFP_KERNEL);
2154         if (!phy)
2155                 return ERR_PTR(-ENOMEM);
2156
2157         phy->instance = instance;
2158         phy->regs = regs;
2159         phy->config = config;
2160         phy->mode = phy_mode;
2161         phy->usb_phy_type = usb_phy_type;
2162         phy->initialized = 0;
2163         phy->regulator_on = 0;
2164         phy->power_on = 0;
2165         phy->remote_wakeup = false;
2166
2167         if (!phy->config) {
2168                 if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_LINK_ULPI ||
2169                     phy->usb_phy_type == TEGRA_USB_PHY_TYPE_NULL_ULPI) {
2170                         pr_err("%s: ulpi phy configuration missing", __func__);
2171                         err = -EINVAL;
2172                         goto err0;
2173                 } else {
2174                         phy->config = &utmip_default[instance];
2175                 }
2176         }
2177
2178         phy->pll_u = clk_get_sys(NULL, "pll_u");
2179         if (IS_ERR(phy->pll_u)) {
2180                 pr_err("Can't get pll_u clock\n");
2181                 err = PTR_ERR(phy->pll_u);
2182                 goto err0;
2183         }
2184         clk_enable(phy->pll_u);
2185
2186         parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
2187         if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_HSIC) {
2188                 for (i = 0; i < ARRAY_SIZE(tegra_uhsic_freq_table); i++) {
2189                         if (tegra_uhsic_freq_table[i].freq == parent_rate) {
2190                                 phy->freq = &tegra_uhsic_freq_table[i];
2191                                 break;
2192                         }
2193                 }
2194         } else {
2195                 for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) {
2196                         if (tegra_freq_table[i].freq == parent_rate) {
2197                                 phy->freq = &tegra_freq_table[i];
2198                                 break;
2199                         }
2200                 }
2201         }
2202         if (!phy->freq) {
2203                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
2204                 err = -EINVAL;
2205                 goto err1;
2206         }
2207
2208         if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) {
2209                 err = utmip_pad_open(phy);
2210                 if (err < 0)
2211                         goto err1;
2212         } else if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_LINK_ULPI) {
2213                 ulpi_config = config;
2214
2215                 if (ulpi_config->clk) {
2216                         phy->clk = clk_get_sys(NULL, ulpi_config->clk);
2217                         if (IS_ERR(phy->clk)) {
2218                                 pr_err("%s: can't get ulpi clock\n", __func__);
2219                                 err = -ENXIO;
2220                                 goto err1;
2221                         }
2222                 } else {
2223                         /* Some USB ULPI chips are not driven by Tegra clocks or PLL */
2224                         phy->clk = NULL;
2225                 }
2226                 tegra_gpio_enable(ulpi_config->reset_gpio);
2227                 gpio_request(ulpi_config->reset_gpio, "ulpi_phy_reset_b");
2228                 gpio_direction_output(ulpi_config->reset_gpio, 0);
2229                 phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
2230                 phy->ulpi->io_priv = regs + ULPI_VIEWPORT;
2231         }
2232 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2233         else if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_HSIC) {
2234                 uhsic_config = config;
2235                 enable_gpio = gpio_request(uhsic_config->enable_gpio,
2236                         "uhsic_enable");
2237                 reset_gpio = gpio_request(uhsic_config->reset_gpio,
2238                                 "uhsic_reset");
2239                 /* hsic enable signal deasserted, hsic reset asserted */
2240                 if (!enable_gpio)
2241                         gpio_direction_output(uhsic_config->enable_gpio,
2242                         0 /* deasserted */);
2243                 if (!reset_gpio)
2244                         gpio_direction_output(uhsic_config->reset_gpio,
2245                                 0 /* asserted */);
2246                 if (!enable_gpio)
2247                         tegra_gpio_enable(uhsic_config->enable_gpio);
2248                 if (!reset_gpio)
2249                         tegra_gpio_enable(uhsic_config->reset_gpio);
2250                 /* keep hsic reset asserted for 1 ms */
2251                 udelay(1000);
2252                 /* enable (power on) hsic */
2253                 if (!enable_gpio)
2254                         gpio_set_value_cansleep(uhsic_config->enable_gpio, 1);
2255                 udelay(1000);
2256                 /* deassert reset */
2257                 if (!reset_gpio)
2258                         gpio_set_value_cansleep(uhsic_config->reset_gpio, 1);
2259         }
2260 #endif
2261
2262         phy->reg_vdd = regulator_get(NULL, "avdd_usb");
2263         if (WARN_ON(IS_ERR_OR_NULL(phy->reg_vdd))) {
2264                 pr_err("couldn't get regulator avdd_usb: %ld \n",
2265                          PTR_ERR(phy->reg_vdd));
2266                 err = PTR_ERR(phy->reg_vdd);
2267                 goto err1;
2268         }
2269
2270         if (instance == 0 && usb_phy_data[0].vbus_irq) {
2271                 err = request_threaded_irq(usb_phy_data[0].vbus_irq, NULL, usb_phy_vbus_irq_thr, IRQF_SHARED,
2272                         "usb_phy_vbus", phy);
2273                 if (err) {
2274                         pr_err("Failed to register IRQ\n");
2275                         goto err1;
2276                 }
2277         }
2278
2279 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2280         /* Power-up the VBUS detector for UTMIP PHY */
2281         if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) {
2282                 writel(readl((IO_ADDRESS(TEGRA_PMC_BASE) + TEGRA_PMC_USB_AO)) &
2283                         ~(TEGRA_PMC_USB_AO_VBUS_WAKEUP_PD_P0 | TEGRA_PMC_USB_AO_ID_PD_P0),
2284                         (IO_ADDRESS(TEGRA_PMC_BASE) + TEGRA_PMC_USB_AO));
2285
2286                 if (usb_phy_data[phy->instance].vbus_reg_supply) {
2287                         phy->reg_vbus = regulator_get(NULL, usb_phy_data[phy->instance].vbus_reg_supply);
2288                         if (WARN_ON(IS_ERR_OR_NULL(phy->reg_vbus))) {
2289                                 pr_err("couldn't get regulator vdd_vbus_usb: %ld, instance : %d\n",
2290                                         PTR_ERR(phy->reg_vbus), phy->instance);
2291                                 err = PTR_ERR(phy->reg_vbus);
2292                                 goto err1;
2293                         }
2294                 }
2295         }
2296         if (instance == 2) {
2297                 writel(readl((IO_ADDRESS(TEGRA_PMC_BASE) + TEGRA_PMC_USB_AO)) &
2298                         (TEGRA_PMC_USB_AO_PD_P2),
2299                         (IO_ADDRESS(TEGRA_PMC_BASE) + TEGRA_PMC_USB_AO));
2300         }
2301 #endif
2302         if (((instance == 2) || (instance == 0)) &&
2303                 (phy->mode == TEGRA_USB_PHY_MODE_HOST)) {
2304                         vbus_enable(phy);
2305         }
2306         return phy;
2307
2308 err1:
2309         clk_disable(phy->pll_u);
2310         clk_put(phy->pll_u);
2311 err0:
2312         kfree(phy);
2313         return ERR_PTR(err);
2314 }
2315
2316 int tegra_usb_phy_power_on(struct tegra_usb_phy *phy, bool is_dpd)
2317 {
2318         int ret = 0;
2319
2320         const tegra_phy_fp power_on[] = {
2321                 utmi_phy_power_on,
2322                 ulpi_phy_power_on,
2323                 null_phy_power_on,
2324                 uhsic_phy_power_on,
2325         };
2326
2327         if (phy->power_on)
2328                 return ret;
2329
2330         if (phy->reg_vdd && !phy->regulator_on) {
2331                 regulator_enable(phy->reg_vdd);
2332                 phy->regulator_on = 1;
2333         }
2334
2335         if (power_on[phy->usb_phy_type])
2336                 ret = power_on[phy->usb_phy_type](phy, is_dpd);
2337
2338         phy->power_on = true;
2339         return ret;
2340 }
2341
2342 void tegra_usb_phy_power_off(struct tegra_usb_phy *phy, bool is_dpd)
2343 {
2344         const tegra_phy_fp power_off[] = {
2345                 utmi_phy_power_off,
2346                 ulpi_phy_power_off,
2347                 null_phy_power_off,
2348                 uhsic_phy_power_off,
2349         };
2350
2351         if (!phy->power_on)
2352                 return;
2353
2354         if (power_off[phy->usb_phy_type])
2355                 power_off[phy->usb_phy_type](phy, is_dpd);
2356
2357         if (phy->reg_vdd && phy->regulator_on && is_dpd) {
2358 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2359                 if (tegra_get_revision() >= TEGRA_REVISION_A03)
2360 #endif
2361                 regulator_disable(phy->reg_vdd);
2362                 phy->regulator_on = 0;
2363         }
2364         phy->power_on = false;
2365 }
2366
2367 void tegra_usb_phy_preresume(struct tegra_usb_phy *phy, bool is_dpd)
2368 {
2369         const tegra_phy_fp preresume[] = {
2370                 utmi_phy_preresume,
2371                 NULL,
2372                 NULL,
2373                 uhsic_phy_preresume,
2374         };
2375
2376         if (preresume[phy->usb_phy_type])
2377                 preresume[phy->usb_phy_type](phy, is_dpd);
2378 }
2379
2380 void tegra_usb_phy_postsuspend(struct tegra_usb_phy *phy, bool is_dpd)
2381
2382 {
2383         const tegra_phy_fp postsuspend[] = {
2384                 NULL,
2385                 NULL,
2386                 NULL,
2387                 uhsic_phy_postsuspend,
2388         };
2389
2390         if (postsuspend[phy->usb_phy_type])
2391                 postsuspend[phy->usb_phy_type](phy, is_dpd);
2392 }
2393
2394 void tegra_usb_phy_postresume(struct tegra_usb_phy *phy, bool is_dpd)
2395 {
2396         const tegra_phy_fp postresume[] = {
2397                 utmi_phy_postresume,
2398                 NULL,
2399                 NULL,
2400                 uhsic_phy_postresume,
2401         };
2402
2403         if (postresume[phy->usb_phy_type])
2404                 postresume[phy->usb_phy_type](phy, is_dpd);
2405 }
2406
2407 void tegra_ehci_pre_reset(struct tegra_usb_phy *phy, bool is_dpd)
2408 {
2409         const tegra_phy_fp pre_reset[] = {
2410                 NULL,
2411                 NULL,
2412                 null_phy_pre_usbcmd_reset,
2413                 NULL,
2414         };
2415
2416         if (pre_reset[phy->usb_phy_type])
2417                 pre_reset[phy->usb_phy_type](phy, is_dpd);
2418 }
2419
2420 void tegra_ehci_post_reset(struct tegra_usb_phy *phy, bool is_dpd)
2421 {
2422         const tegra_phy_fp post_reset[] = {
2423                 NULL,
2424                 NULL,
2425                 null_phy_post_usbcmd_reset,
2426                 NULL,
2427         };
2428
2429         if (post_reset[phy->usb_phy_type])
2430                 post_reset[phy->usb_phy_type](phy, is_dpd);
2431 }
2432
2433 void tegra_ehci_phy_restore_start(struct tegra_usb_phy *phy,
2434                                  enum tegra_usb_phy_port_speed port_speed)
2435 {
2436         if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP)
2437                 utmi_phy_restore_start(phy, port_speed);
2438         else
2439                 ulpi_phy_restore_start(phy, port_speed);
2440 }
2441
2442 void tegra_ehci_phy_restore_end(struct tegra_usb_phy *phy)
2443 {
2444         if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP)
2445                 utmi_phy_restore_end(phy);
2446         else
2447                 ulpi_phy_restore_end(phy);
2448 }
2449
2450 void tegra_usb_phy_clk_disable(struct tegra_usb_phy *phy)
2451 {
2452         if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP)
2453                 utmi_phy_clk_disable(phy);
2454 }
2455
2456 void tegra_usb_phy_clk_enable(struct tegra_usb_phy *phy)
2457 {
2458         if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP)
2459                 utmi_phy_clk_enable(phy);
2460 }
2461
2462 void tegra_usb_phy_close(struct tegra_usb_phy *phy)
2463 {
2464         if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) {
2465                 utmip_pad_close(phy);
2466                 utmip_phy_disable_pmc_bus_ctrl(phy);
2467         }
2468         else if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_LINK_ULPI && phy->clk)
2469                 clk_put(phy->clk);
2470         if (phy->mode == TEGRA_USB_PHY_MODE_HOST) {
2471                 vbus_disable(phy);
2472         }
2473         clk_disable(phy->pll_u);
2474         clk_put(phy->pll_u);
2475         if (phy->reg_vbus)
2476                 regulator_put(phy->reg_vbus);
2477         if (phy->reg_vdd)
2478                 regulator_put(phy->reg_vdd);
2479         if (phy->instance == 0 && usb_phy_data[0].vbus_irq)
2480                 free_irq(usb_phy_data[0].vbus_irq, phy);
2481         kfree(phy);
2482 }
2483
2484 int tegra_usb_phy_bus_connect(struct tegra_usb_phy *phy)
2485 {
2486         unsigned long val;
2487         void __iomem *base = phy->regs;
2488
2489         if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_HSIC) {
2490 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2491                 /* Change the USB controller PHY type to HSIC */
2492                 val = readl(base + HOSTPC1_DEVLC);
2493                 val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
2494                 val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2495                 val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
2496                 val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2497                 writel(val, base + HOSTPC1_DEVLC);
2498 #endif
2499                 val = readl(base + UHSIC_MISC_CFG0);
2500                 val |= UHSIC_DETECT_SHORT_CONNECT;
2501                 writel(val, base + UHSIC_MISC_CFG0);
2502                 udelay(1);
2503
2504                 val = readl(base + UHSIC_MISC_CFG0);
2505                 val |= UHSIC_FORCE_XCVR_MODE;
2506                 writel(val, base + UHSIC_MISC_CFG0);
2507
2508                 val = readl(base + UHSIC_PADS_CFG1);
2509                 val &= ~UHSIC_RPD_STROBE;
2510 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2511                 val |= UHSIC_RPU_STROBE;
2512 #endif
2513                 writel(val, base + UHSIC_PADS_CFG1);
2514
2515                 if (utmi_wait_register(base + UHSIC_STAT_CFG0, UHSIC_CONNECT_DETECT, UHSIC_CONNECT_DETECT) < 0) {
2516                         pr_err("%s: timeout waiting for hsic connect detect\n", __func__);
2517                         return -ETIMEDOUT;
2518                 }
2519
2520 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2521                 if (utmi_wait_register(base + USB_PORTSC1, USB_PORTSC1_LS(2), USB_PORTSC1_LS(2)) < 0) {
2522                         pr_err("%s: timeout waiting for dplus state\n", __func__);
2523                         return -ETIMEDOUT;
2524                 }
2525 #endif
2526         }
2527
2528         return 0;
2529 }
2530
2531 int tegra_usb_phy_bus_reset(struct tegra_usb_phy *phy)
2532 {
2533         unsigned long val;
2534         void __iomem *base = phy->regs;
2535
2536         if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_HSIC) {
2537 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2538                 val = readl(base + USB_PORTSC1);
2539                 val |= USB_PORTSC1_PTC(5);
2540                 writel(val, base + USB_PORTSC1);
2541                 udelay(2);
2542
2543                 val = readl(base + USB_PORTSC1);
2544                 val &= ~USB_PORTSC1_PTC(~0);
2545                 writel(val, base + USB_PORTSC1);
2546                 udelay(2);
2547 #endif
2548
2549 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2550                 if (utmi_wait_register(base + USB_PORTSC1, USB_PORTSC1_LS(0), 0) < 0) {
2551                         pr_err("%s: timeout waiting for SE0\n", __func__);
2552                         return -ETIMEDOUT;
2553                 }
2554 #endif
2555                 if (utmi_wait_register(base + USB_PORTSC1, USB_PORTSC1_CCS, USB_PORTSC1_CCS) < 0) {
2556                         pr_err("%s: timeout waiting for connection status\n", __func__);
2557                         return -ETIMEDOUT;
2558                 }
2559
2560 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2561                 if (utmi_wait_register(base + USB_PORTSC1, USB_PORTSC1_PSPD(2), USB_PORTSC1_PSPD(2)) < 0) {
2562                         pr_err("%s: timeout waiting hsic high speed configuration\n", __func__);
2563                         return -ETIMEDOUT;
2564                 }
2565 #endif
2566                 val = readl(base + USB_USBCMD);
2567                 val &= ~USB_USBCMD_RS;
2568                 writel(val, base + USB_USBCMD);
2569
2570                 if (utmi_wait_register(base + USB_USBSTS, USB_USBSTS_HCH, USB_USBSTS_HCH) < 0) {
2571                         pr_err("%s: timeout waiting for stopping the controller\n", __func__);
2572                         return -ETIMEDOUT;
2573                 }
2574
2575                 val = readl(base + UHSIC_PADS_CFG1);
2576                 val &= ~UHSIC_RPU_STROBE;
2577                 val |= UHSIC_RPD_STROBE;
2578                 writel(val, base + UHSIC_PADS_CFG1);
2579
2580                 mdelay(50);
2581
2582                 val = readl(base + UHSIC_PADS_CFG1);
2583                 val &= ~UHSIC_RPD_STROBE;
2584                 val |= UHSIC_RPU_STROBE;
2585                 writel(val, base + UHSIC_PADS_CFG1);
2586
2587                 val = readl(base + USB_USBCMD);
2588                 val |= USB_USBCMD_RS;
2589                 writel(val, base + USB_USBCMD);
2590
2591                 val = readl(base + UHSIC_PADS_CFG1);
2592                 val &= ~UHSIC_RPU_STROBE;
2593                 writel(val, base + UHSIC_PADS_CFG1);
2594
2595                 if (utmi_wait_register(base + USB_USBCMD, USB_USBCMD_RS, USB_USBCMD_RS) < 0) {
2596                         pr_err("%s: timeout waiting for starting the controller\n", __func__);
2597                         return -ETIMEDOUT;
2598                 }
2599         }
2600
2601         return 0;
2602 }
2603
2604 int tegra_usb_phy_bus_idle(struct tegra_usb_phy *phy)
2605 {
2606         unsigned long val;
2607         void __iomem *base = phy->regs;
2608
2609         if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_HSIC) {
2610 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2611                 /* Change the USB controller PHY type to HSIC */
2612                 val = readl(base + HOSTPC1_DEVLC);
2613                 val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
2614                 val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2615                 val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
2616                 val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2617                 writel(val, base + HOSTPC1_DEVLC);
2618 #endif
2619                 val = readl(base + UHSIC_MISC_CFG0);
2620                 val |= UHSIC_DETECT_SHORT_CONNECT;
2621                 writel(val, base + UHSIC_MISC_CFG0);
2622                 udelay(1);
2623
2624                 val = readl(base + UHSIC_MISC_CFG0);
2625                 val |= UHSIC_FORCE_XCVR_MODE;
2626                 writel(val, base + UHSIC_MISC_CFG0);
2627
2628                 val = readl(base + UHSIC_PADS_CFG1);
2629                 val &= ~UHSIC_RPD_STROBE;
2630 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2631                 val |= UHSIC_RPU_STROBE;
2632 #endif
2633                 writel(val, base + UHSIC_PADS_CFG1);
2634         }
2635         return 0;
2636 }
2637
2638 bool tegra_usb_phy_is_device_connected(struct tegra_usb_phy *phy)
2639 {
2640         void __iomem *base = phy->regs;
2641
2642         if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_HSIC) {
2643                 if (!((readl(base + UHSIC_STAT_CFG0) & UHSIC_CONNECT_DETECT) == UHSIC_CONNECT_DETECT)) {
2644                         pr_err("%s: hsic no device connection\n", __func__);
2645                         return false;
2646                 }
2647 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2648                 if (utmi_wait_register(base + USB_PORTSC1, USB_PORTSC1_LS(2), USB_PORTSC1_LS(2)) < 0) {
2649                         pr_err("%s: timeout waiting for dplus state\n", __func__);
2650                         return false;
2651                 }
2652 #endif
2653         }
2654         return true;
2655 }
2656
2657 bool tegra_usb_phy_charger_detect(struct tegra_usb_phy *phy)
2658 {
2659         unsigned long val;
2660         void __iomem *base = phy->regs;
2661         bool status;
2662
2663         if (phy->usb_phy_type != TEGRA_USB_PHY_TYPE_UTMIP)
2664         {
2665                 /* Charger detection is not there for ULPI
2666                  * return Charger not available */
2667                 return false;
2668         }
2669
2670         /* Enable charger detection logic */
2671         val = readl(base + UTMIP_BAT_CHRG_CFG0);
2672         val |= UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN;
2673         writel(val, base + UTMIP_BAT_CHRG_CFG0);
2674
2675         /* Source should be on for 100 ms as per USB charging spec */
2676         msleep(TDP_SRC_ON_MS);
2677
2678         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
2679         /* If charger is not connected disable the interrupt */
2680         val &= ~VDAT_DET_INT_EN;
2681         val |= VDAT_DET_CHG_DET;
2682         writel(val,base + USB_PHY_VBUS_WAKEUP_ID);
2683
2684         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
2685         if (val & VDAT_DET_STS)
2686                 status = true;
2687         else
2688                 status = false;
2689
2690         /* Disable charger detection logic */
2691         val = readl(base + UTMIP_BAT_CHRG_CFG0);
2692         val &= ~(UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN);
2693         writel(val, base + UTMIP_BAT_CHRG_CFG0);
2694
2695         /* Delay of 40 ms before we pull the D+ as per battery charger spec */
2696         msleep(TDPSRC_CON_MS);
2697
2698         return status;
2699 }
2700
2701 int __init tegra_usb_phy_init(struct usb_phy_plat_data *pdata, int size)
2702 {
2703         if (pdata) {
2704                 int i;
2705
2706                 for (i = 0; i < size; i++, pdata++) {
2707                         usb_phy_data[pdata->instance].instance = pdata->instance;
2708                         usb_phy_data[pdata->instance].vbus_irq = pdata->vbus_irq;
2709                         usb_phy_data[pdata->instance].vbus_gpio = pdata->vbus_gpio;
2710                         usb_phy_data[pdata->instance].vbus_reg_supply = pdata->vbus_reg_supply;
2711                 }
2712         }
2713
2714         return 0;
2715 }
2716
2717 /* disable walk and wake events after resume from LP0 */
2718 bool tegra_usb_phy_is_remotewake_detected(struct tegra_usb_phy *phy)
2719 {
2720 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2721         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
2722         void __iomem *base = phy->regs;
2723         unsigned  int inst = phy->instance;
2724         u32 val;
2725
2726         val = readl(base + UTMIP_PMC_WAKEUP0);
2727         if (val & EVENT_INT_ENB) {
2728                 val = readl(pmc_base + UTMIP_UHSIC_STATUS);
2729                 if (UTMIP_WAKE_ALARM(inst) & val) {
2730                         val = readl(pmc_base + PMC_SLEEP_CFG);
2731                         val &= ~UTMIP_WAKE_VAL(inst, 0x0);
2732                         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
2733                         writel(val, pmc_base + PMC_SLEEP_CFG);
2734
2735                         val = readl(pmc_base + PMC_TRIGGERS);
2736                         val |= UTMIP_CLR_WAKE_ALARM(inst) |
2737                                 UTMIP_CLR_WALK_PTR(inst);
2738                         writel(val, pmc_base + PMC_TRIGGERS);
2739
2740                         val = readl(base + UTMIP_PMC_WAKEUP0);
2741                         val &= ~EVENT_INT_ENB;
2742                         writel(val, base + UTMIP_PMC_WAKEUP0);
2743                         phy->remote_wakeup = true;
2744                         return true;
2745                 }
2746         }
2747 #endif
2748         return false;
2749 }
2750