ARM: tegra: usb: AHB prefetch support calls
[linux-2.6.git] / arch / arm / mach-tegra / usb_phy.c
1 /*
2  * arch/arm/mach-tegra/usb_phy.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Copyright (C) 2010 - 2011 NVIDIA Corporation
6  *
7  * Author:
8  *      Erik Gilling <konkers@google.com>
9  *      Benoit Goby <benoit@android.com>
10  *
11  * This software is licensed under the terms of the GNU General Public
12  * License version 2, as published by the Free Software Foundation, and
13  * may be copied, distributed, and modified under those terms.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  */
21
22 #include <linux/resource.h>
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/err.h>
27 #include <linux/platform_device.h>
28 #include <linux/io.h>
29 #include <linux/gpio.h>
30 #include <linux/usb/otg.h>
31 #include <linux/usb/ulpi.h>
32 #include <asm/mach-types.h>
33 #include <mach/usb_phy.h>
34 #include <mach/iomap.h>
35 #include <mach/pinmux.h>
36 #include "fuse.h"
37
38
39 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
40 #define USB_USBCMD              0x140
41 #define   USB_USBCMD_RS         (1 << 0)
42
43 #define USB_USBSTS              0x144
44 #define   USB_USBSTS_PCI        (1 << 2)
45 #define   USB_USBSTS_HCH        (1 << 12)
46
47 #define USB_TXFILLTUNING        0x164
48 #define USB_FIFO_TXFILL_THRES(x)   (((x) & 0x1f) << 16)
49 #define USB_FIFO_TXFILL_MASK    0x1f0000
50
51 #define ULPI_VIEWPORT           0x170
52 #define   ULPI_WAKEUP           (1 << 31)
53 #define   ULPI_RUN              (1 << 30)
54 #define   ULPI_RD_WR            (1 << 29)
55
56 #define USB_PORTSC1             0x184
57 #define   USB_PORTSC1_PTS(x)    (((x) & 0x3) << 30)
58 #define   USB_PORTSC1_PSPD(x)   (((x) & 0x3) << 26)
59 #define   USB_PORTSC1_PHCD      (1 << 23)
60 #define   USB_PORTSC1_WKOC      (1 << 22)
61 #define   USB_PORTSC1_WKDS      (1 << 21)
62 #define   USB_PORTSC1_WKCN      (1 << 20)
63 #define   USB_PORTSC1_PTC(x)    (((x) & 0xf) << 16)
64 #define   USB_PORTSC1_PP        (1 << 12)
65 #define   USB_PORTSC1_LS(x)     (((x) & 0x3) << 10)
66 #define   USB_PORTSC1_SUSP      (1 << 7)
67 #define   USB_PORTSC1_PE        (1 << 2)
68 #define   USB_PORTSC1_CCS       (1 << 0)
69
70 #define USB_SUSP_CTRL           0x400
71 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
72 #define   USB_WAKE_ON_DISCON_EN_DEV     (1 << 4)
73 #define   USB_SUSP_CLR          (1 << 5)
74 #define   USB_CLKEN             (1 << 6)
75 #define   USB_PHY_CLK_VALID     (1 << 7)
76 #define   USB_PHY_CLK_VALID_INT_ENB    (1 << 9)
77 #define   UTMIP_RESET           (1 << 11)
78 #define   UHSIC_RESET           (1 << 11)
79 #define   UTMIP_PHY_ENABLE      (1 << 12)
80 #define   UHSIC_PHY_ENABLE      (1 << 12)
81 #define   ULPI_PHY_ENABLE       (1 << 13)
82 #define   USB_SUSP_SET          (1 << 14)
83 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
84
85 #define USB_PHY_VBUS_WAKEUP_ID  0x408
86 #define   VDAT_DET_INT_EN       (1 << 16)
87 #define   VDAT_DET_CHG_DET      (1 << 17)
88 #define   VDAT_DET_STS          (1 << 18)
89
90 #define USB1_LEGACY_CTRL        0x410
91 #define   USB1_NO_LEGACY_MODE                   (1 << 0)
92 #define   USB1_VBUS_SENSE_CTL_MASK              (3 << 1)
93 #define   USB1_VBUS_SENSE_CTL_VBUS_WAKEUP       (0 << 1)
94 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
95                                                 (1 << 1)
96 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD       (2 << 1)
97 #define   USB1_VBUS_SENSE_CTL_A_SESS_VLD        (3 << 1)
98
99
100 #define UTMIP_PLL_CFG1          0x804
101 #define   UTMIP_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
102 #define   UTMIP_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 27)
103
104 #define UTMIP_XCVR_CFG0         0x808
105 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
106 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
107 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
108 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
109 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
110 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
111 #define   UTMIP_XCVR_LSBIAS_SEL                 (1 << 21)
112 #define   UTMIP_XCVR_SETUP_MSB(x)               (((x) & 0x7) << 22)
113 #define   UTMIP_XCVR_HSSLEW_MSB(x)              (((x) & 0x7f) << 25)
114
115 #define UTMIP_XCVR_MAX_OFFSET           2
116 #define UTMIP_XCVR_SETUP_MAX_VALUE      0x7f
117 #define UTMIP_XCVR_SETUP_MIN_VALUE      0
118 #define XCVR_SETUP_MSB_CALIB(x) ((x) >> 4)
119
120 #define UTMIP_BIAS_CFG0         0x80c
121 #define   UTMIP_OTGPD                   (1 << 11)
122 #define   UTMIP_BIASPD                  (1 << 10)
123
124 #define UTMIP_HSRX_CFG0         0x810
125 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
126 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
127
128 #define UTMIP_HSRX_CFG1         0x814
129 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
130
131 #define UTMIP_TX_CFG0           0x820
132 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
133 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
134
135 #define UTMIP_MISC_CFG1         0x828
136 #define   UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18)
137 #define   UTMIP_PLLU_STABLE_COUNT(x)    (((x) & 0xfff) << 6)
138
139 #define UTMIP_DEBOUNCE_CFG0     0x82c
140 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
141
142 #define UTMIP_BAT_CHRG_CFG0     0x830
143 #define   UTMIP_PD_CHRG                 (1 << 0)
144 #define   UTMIP_ON_SINK_EN              (1 << 2)
145 #define   UTMIP_OP_SRC_EN               (1 << 3)
146
147 #define UTMIP_XCVR_CFG1         0x838
148 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
149 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
150 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
151 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
152
153 #define UTMIP_BIAS_CFG1         0x83c
154 #define   UTMIP_BIAS_PDTRK_COUNT(x)     (((x) & 0x1f) << 3)
155
156 #define UHSIC_PLL_CFG1                          0x804
157 #define   UHSIC_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
158 #define   UHSIC_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 14)
159
160 #define UHSIC_HSRX_CFG0                         0x808
161 #define   UHSIC_ELASTIC_UNDERRUN_LIMIT(x)       (((x) & 0x1f) << 2)
162 #define   UHSIC_ELASTIC_OVERRUN_LIMIT(x)        (((x) & 0x1f) << 8)
163 #define   UHSIC_IDLE_WAIT(x)                    (((x) & 0x1f) << 13)
164
165 #define UHSIC_HSRX_CFG1                         0x80c
166 #define   UHSIC_HS_SYNC_START_DLY(x)            (((x) & 0x1f) << 1)
167
168 #define UHSIC_TX_CFG0                           0x810
169 #define   UHSIC_HS_POSTAMBLE_OUTPUT_ENABLE      (1 << 6)
170
171 #define UHSIC_MISC_CFG0                         0x814
172 #define   UHSIC_SUSPEND_EXIT_ON_EDGE            (1 << 7)
173 #define   UHSIC_DETECT_SHORT_CONNECT            (1 << 8)
174 #define   UHSIC_FORCE_XCVR_MODE                 (1 << 15)
175
176 #define UHSIC_MISC_CFG1                         0X818
177 #define   UHSIC_PLLU_STABLE_COUNT(x)            (((x) & 0xfff) << 2)
178
179 #define UHSIC_PADS_CFG0                         0x81c
180 #define   UHSIC_TX_RTUNEN                       0xf000
181 #define   UHSIC_TX_RTUNE(x)                     (((x) & 0xf) << 12)
182
183 #define UHSIC_PADS_CFG1                         0x820
184 #define   UHSIC_PD_BG                           (1 << 2)
185 #define   UHSIC_PD_TX                           (1 << 3)
186 #define   UHSIC_PD_TRK                          (1 << 4)
187 #define   UHSIC_PD_RX                           (1 << 5)
188 #define   UHSIC_PD_ZI                           (1 << 6)
189 #define   UHSIC_RX_SEL                          (1 << 7)
190 #define   UHSIC_RPD_DATA                        (1 << 9)
191 #define   UHSIC_RPD_STROBE                      (1 << 10)
192 #define   UHSIC_RPU_DATA                        (1 << 11)
193 #define   UHSIC_RPU_STROBE                      (1 << 12)
194
195 #define UHSIC_STAT_CFG0                         0x828
196 #define   UHSIC_CONNECT_DETECT                  (1 << 0)
197
198
199 #else
200
201 #define USB_USBCMD              0x130
202 #define   USB_USBCMD_RS         (1 << 0)
203
204 #define USB_USBSTS              0x134
205 #define   USB_USBSTS_PCI        (1 << 2)
206 #define   USB_USBSTS_SRI        (1 << 7)
207 #define   USB_USBSTS_HCH        (1 << 12)
208
209 #define USB_TXFILLTUNING        0x154
210 #define USB_FIFO_TXFILL_THRES(x)   (((x) & 0x1f) << 16)
211 #define USB_FIFO_TXFILL_MASK    0x1f0000
212
213 #define ULPI_VIEWPORT           0x160
214
215 #define USB_PORTSC1             0x174
216 #define   USB_PORTSC1_WKOC      (1 << 22)
217 #define   USB_PORTSC1_WKDS      (1 << 21)
218 #define   USB_PORTSC1_WKCN      (1 << 20)
219 #define   USB_PORTSC1_PTC(x)    (((x) & 0xf) << 16)
220 #define   USB_PORTSC1_PP        (1 << 12)
221 #define   USB_PORTSC1_LS(x)     (((x) & 0x3) << 10)
222 #define   USB_PORTSC1_SUSP      (1 << 7)
223 #define   USB_PORTSC1_RESUME    (1 << 6)
224 #define   USB_PORTSC1_PE        (1 << 2)
225 #define   USB_PORTSC1_CCS       (1 << 0)
226
227 #define USB_SUSP_CTRL           0x400
228 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
229 #define   USB_WAKE_ON_DISCON_EN_DEV     (1 << 4)
230 #define   USB_SUSP_CLR                  (1 << 5)
231 #define   USB_PHY_CLK_VALID             (1 << 7)
232 #define   USB_PHY_CLK_VALID_INT_ENB    (1 << 9)
233
234
235 #define   UTMIP_RESET                   (1 << 11)
236 #define   UTMIP_PHY_ENABLE              (1 << 12)
237 #define   ULPI_PHY_ENABLE               (1 << 13)
238 #define   UHSIC_RESET                   (1 << 14)
239
240 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
241 #define   UHSIC_PHY_ENABLE              (1 << 19)
242 #define   ULPIS2S_SLV0_RESET            (1 << 20)
243 #define   ULPIS2S_SLV1_RESET            (1 << 21)
244 #define   ULPIS2S_LINE_RESET            (1 << 22)
245 #define   ULPI_PADS_RESET               (1 << 23)
246 #define   ULPI_PADS_CLKEN_RESET         (1 << 24)
247
248 #define USB_PHY_VBUS_WAKEUP_ID  0x408
249 #define   VDAT_DET_INT_EN       (1 << 16)
250 #define   VDAT_DET_CHG_DET      (1 << 17)
251 #define   VDAT_DET_STS          (1 << 18)
252
253 #define USB1_LEGACY_CTRL        0x410
254 #define   USB1_NO_LEGACY_MODE                   (1 << 0)
255 #define   USB1_VBUS_SENSE_CTL_MASK              (3 << 1)
256 #define   USB1_VBUS_SENSE_CTL_VBUS_WAKEUP       (0 << 1)
257 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
258                                                 (1 << 1)
259 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD       (2 << 1)
260 #define   USB1_VBUS_SENSE_CTL_A_SESS_VLD        (3 << 1)
261
262 #define UTMIP_PLL_CFG1          0x804
263 #define   UTMIP_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
264 #define   UTMIP_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 27)
265
266 #define UTMIP_XCVR_CFG0         0x808
267 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
268 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
269 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
270 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
271 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
272 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
273 #define   UTMIP_XCVR_LSBIAS_SEL                 (1 << 21)
274 #define   UTMIP_XCVR_SETUP_MSB(x)               (((x) & 0x7) << 22)
275 #define   UTMIP_XCVR_HSSLEW_MSB(x)              (((x) & 0x7f) << 25)
276
277 #define UTMIP_XCVR_MAX_OFFSET           2
278 #define UTMIP_XCVR_SETUP_MAX_VALUE      0x7f
279 #define UTMIP_XCVR_SETUP_MIN_VALUE      0
280 #define XCVR_SETUP_MSB_CALIB(x) ((x) >> 4)
281
282 #define UTMIP_BIAS_CFG0         0x80c
283 #define   UTMIP_OTGPD                   (1 << 11)
284 #define   UTMIP_BIASPD                  (1 << 10)
285 #define   UTMIP_HSSQUELCH_LEVEL(x)      (((x) & 0x3) << 0)
286 #define   UTMIP_HSDISCON_LEVEL(x)       (((x) & 0x3) << 2)
287 #define   UTMIP_HSDISCON_LEVEL_MSB      (1 << 24)
288
289 #define UTMIP_HSRX_CFG0         0x810
290 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
291 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
292
293 #define UTMIP_HSRX_CFG1         0x814
294 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
295
296 #define UTMIP_TX_CFG0           0x820
297 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
298 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
299
300 #define UTMIP_MISC_CFG1         0x828
301 #define   UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18)
302 #define   UTMIP_PLLU_STABLE_COUNT(x)    (((x) & 0xfff) << 6)
303
304 #define UTMIP_DEBOUNCE_CFG0     0x82c
305 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
306
307 #define UTMIP_BAT_CHRG_CFG0     0x830
308 #define   UTMIP_PD_CHRG                 (1 << 0)
309 #define   UTMIP_ON_SINK_EN              (1 << 2)
310 #define   UTMIP_OP_SRC_EN               (1 << 3)
311
312 #define UTMIP_XCVR_CFG1         0x838
313 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
314 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
315 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
316 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
317
318 #define UTMIP_BIAS_CFG1         0x83c
319 #define   UTMIP_BIAS_PDTRK_COUNT(x)     (((x) & 0x1f) << 3)
320 #define   UTMIP_BIAS_PDTRK_POWERDOWN    (1 << 0)
321 #define   UTMIP_BIAS_PDTRK_POWERUP      (1 << 1)
322
323 #define HOSTPC1_DEVLC           0x1b4
324 #define   HOSTPC1_DEVLC_PHCD            (1 << 22)
325 #define   HOSTPC1_DEVLC_PTS(x)          (((x) & 0x7) << 29)
326 #define   HOSTPC1_DEVLC_PTS_MASK        7
327 #define   HOSTPC1_DEVLC_PTS_HSIC        4
328 #define   HOSTPC1_DEVLC_STS             (1 << 28)
329 #define   HOSTPC1_DEVLC_PSPD(x)         (((x) & 0x3) << 25)
330 #define   HOSTPC1_DEVLC_PSPD_MASK       3
331 #define   HOSTPC1_DEVLC_PSPD_HIGH_SPEED 2
332
333 #define TEGRA_USB_USBMODE_REG_OFFSET    0x1f8
334 #define   TEGRA_USB_USBMODE_HOST                (3 << 0)
335
336 #define TEGRA_PMC_USB_AO                0xf0
337 #define   TEGRA_PMC_USB_AO_VBUS_WAKEUP_PD_P0    (1 << 2)
338 #define   TEGRA_PMC_USB_AO_ID_PD_P0             (1 << 3)
339 #define   TEGRA_PMC_USB_AO_PD_P2                (0xf << 8)
340
341 #define ICUSB_CTRL              0x15c
342
343 #define UHSIC_PLL_CFG1                          0xc04
344 #define   UHSIC_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
345 #define   UHSIC_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 14)
346
347 #define UHSIC_HSRX_CFG0                         0xc08
348 #define   UHSIC_ELASTIC_UNDERRUN_LIMIT(x)       (((x) & 0x1f) << 2)
349 #define   UHSIC_ELASTIC_OVERRUN_LIMIT(x)        (((x) & 0x1f) << 8)
350 #define   UHSIC_IDLE_WAIT(x)                    (((x) & 0x1f) << 13)
351
352 #define UHSIC_HSRX_CFG1                         0xc0c
353 #define   UHSIC_HS_SYNC_START_DLY(x)            (((x) & 0x1f) << 1)
354
355 #define UHSIC_TX_CFG0                           0xc10
356 #define   UHSIC_HS_READY_WAIT_FOR_VALID         (1 << 9)
357
358 #define UHSIC_MISC_CFG0                         0xc14
359 #define   UHSIC_SUSPEND_EXIT_ON_EDGE            (1 << 7)
360 #define   UHSIC_DETECT_SHORT_CONNECT            (1 << 8)
361 #define   UHSIC_FORCE_XCVR_MODE                 (1 << 15)
362 #define   UHSIC_DISABLE_BUSRESET                (1 << 20)
363
364 #define UHSIC_MISC_CFG1                         0xc18
365 #define   UHSIC_PLLU_STABLE_COUNT(x)            (((x) & 0xfff) << 2)
366
367 #define UHSIC_PADS_CFG0                         0xc1c
368 #define   UHSIC_TX_RTUNEN                       0xf000
369 #define   UHSIC_TX_RTUNE(x)                     (((x) & 0xf) << 12)
370
371 #define UHSIC_PADS_CFG1                         0xc20
372 #define   UHSIC_PD_BG                           (1 << 2)
373 #define   UHSIC_PD_TX                           (1 << 3)
374 #define   UHSIC_PD_TRK                          (1 << 4)
375 #define   UHSIC_PD_RX                           (1 << 5)
376 #define   UHSIC_PD_ZI                           (1 << 6)
377 #define   UHSIC_RX_SEL                          (1 << 7)
378 #define   UHSIC_RPD_DATA                        (1 << 9)
379 #define   UHSIC_RPD_STROBE                      (1 << 10)
380 #define   UHSIC_RPU_DATA                        (1 << 11)
381 #define   UHSIC_RPU_STROBE                      (1 << 12)
382
383 #define UHSIC_STAT_CFG0                         0xc28
384 #define   UHSIC_CONNECT_DETECT                  (1 << 0)
385
386 #define PMC_UTMIP_MASTER_CONFIG         0x310
387 #define UTMIP_PWR(inst)                 (1 << (inst))
388
389 #define PMC_USB_DEBOUNCE                0xec
390 #define UTMIP_LINE_DEB_CNT(x)           (((x) & 0xf) << 16)
391
392 #define PMC_UTMIP_UHSIC_FAKE            0x218
393 #define USBON_VAL(inst)         (1 << ((4*(inst))+1))
394 #define USBON_VAL_P2                    (1 << 9)
395 #define USBON_VAL_P1                    (1 << 5)
396 #define USBON_VAL_P0                    (1 << 1)
397 #define USBOP_VAL(inst)         (1 << (4*(inst)))
398 #define USBOP_VAL_P2                    (1 << 8)
399 #define USBOP_VAL_P1                    (1 << 4)
400 #define USBOP_VAL_P0                    (1 << 0)
401
402 #define PMC_SLEEPWALK_CFG               0x200
403 #define UTMIP_LINEVAL_WALK_EN(inst)     (1 << ((8*(inst))+7))
404 #define UTMIP_LINEVAL_WALK_EN_P2        (1 << 23)
405 #define UTMIP_LINEVAL_WALK_EN_P1        (1 << 15)
406 #define UTMIP_LINEVAL_WALK_EN_P0        (1 << 7)
407 #define UTMIP_WAKE_VAL(inst, x) (((x) & 0xf) << ((8*(inst))+4))
408 #define UTMIP_WAKE_VAL_P2(x)            (((x) & 0xf) << 20)
409 #define UTMIP_WAKE_VAL_P1(x)            (((x) & 0xf) << 12)
410 #define UTMIP_WAKE_VAL_P0(x)            (((x) & 0xf) << 4)
411 #define WAKE_VAL_NONE                   0xc
412 #define WAKE_VAL_FSJ                    0x2
413 #define WAKE_VAL_FSK                    0x1
414 #define WAKE_VAL_SE0                    0x0
415 #define WAKE_VAL_ANY                    0xf
416
417 #define PMC_SLEEP_CFG                   0x1fc
418 #define UTMIP_TCTRL_USE_PMC(inst)       (1 << ((8*(inst))+3))
419 #define UTMIP_TCTRL_USE_PMC_P2          (1 << 19)
420 #define UTMIP_TCTRL_USE_PMC_P1          (1 << 11)
421 #define UTMIP_TCTRL_USE_PMC_P0          (1 << 3)
422 #define UTMIP_RCTRL_USE_PMC(inst)       (1 << ((8*(inst))+2))
423 #define UTMIP_RCTRL_USE_PMC_P2          (1 << 18)
424 #define UTMIP_RCTRL_USE_PMC_P1          (1 << 10)
425 #define UTMIP_RCTRL_USE_PMC_P0          (1 << 2)
426 #define UTMIP_FSLS_USE_PMC(inst)        (1 << ((8*(inst))+1))
427 #define UTMIP_FSLS_USE_PMC_P2           (1 << 17)
428 #define UTMIP_FSLS_USE_PMC_P1           (1 << 9)
429 #define UTMIP_FSLS_USE_PMC_P0           (1 << 1)
430 #define UTMIP_MASTER_ENABLE(inst)       (1 << (8*(inst)))
431 #define UTMIP_MASTER_ENABLE_P2          (1 << 16)
432 #define UTMIP_MASTER_ENABLE_P1          (1 << 8)
433 #define UTMIP_MASTER_ENABLE_P0          (1 << 0)
434 #define UHSIC_MASTER_ENABLE_P0          (1 << 24)
435 #define UHSIC_WAKE_VAL_P0(x)            (((x) & 0xf) << 28)
436
437 #define PMC_USB_AO                      0xf0
438 #define PMC_POWER_DOWN_MASK             0xffff
439 #define HSIC_RESERVED_P0                (3 << 14)
440 #define HSIC_STOBE_VAL_PD_P0    (1 << 13)
441 #define HSIC_DATA_VAL_PD_P0     (1 << 12)
442 #define USB_ID_PD(inst)                 (1 << ((4*(inst))+3))
443 #define VBUS_WAKEUP_PD(inst)            (1 << ((4*(inst))+2))
444 #define USBON_VAL_PD(inst)              (1 << ((4*(inst))+1))
445 #define USBON_VAL_PD_P2                 (1 << 9)
446 #define USBON_VAL_PD_P1                 (1 << 5)
447 #define USBON_VAL_PD_P0                 (1 << 1)
448 #define USBOP_VAL_PD(inst)              (1 << (4*(inst)))
449 #define USBOP_VAL_PD_P2                 (1 << 8)
450 #define USBOP_VAL_PD_P1                 (1 << 4)
451 #define USBOP_VAL_PD_P0                 (1 << 0)
452
453 #define PMC_TRIGGERS                    0x1ec
454 #define UTMIP_CLR_WALK_PTR(inst)        (1 << (inst))
455 #define UTMIP_CLR_WALK_PTR_P2           (1 << 2)
456 #define UTMIP_CLR_WALK_PTR_P1           (1 << 1)
457 #define UTMIP_CLR_WALK_PTR_P0           (1 << 0)
458 #define UTMIP_CAP_CFG(inst)             (1 << ((inst)+4))
459 #define UTMIP_CAP_CFG_P2                (1 << 6)
460 #define UTMIP_CAP_CFG_P1                (1 << 5)
461 #define UTMIP_CAP_CFG_P0                (1 << 4)
462 #define UTMIP_CLR_WAKE_ALARM(inst)              (1 << ((inst)+12))
463 #define UTMIP_CLR_WAKE_ALARM_P2         (1 << 14)
464
465 #define PMC_PAD_CFG                     (0x1f4)
466
467 #define PMC_UTMIP_BIAS_MASTER_CNTRL     0x30c
468 #define BIAS_MASTER_PROG_VAL            (1 << 1)
469
470 #define PMC_SLEEPWALK_REG(inst)         (0x204 + (4*(inst)))
471 #define PMC_SLEEPWALK_P0                0x204
472 #define PMC_SLEEPWALK_P1                0x208
473 #define PMC_SLEEPWALK_P2                0x20c
474 #define UTMIP_USBOP_RPD_A               (1 << 0)
475 #define UTMIP_USBON_RPD_A               (1 << 1)
476 #define UTMIP_AP_A                      (1 << 4)
477 #define UTMIP_AN_A                      (1 << 5)
478 #define UTMIP_HIGHZ_A                   (1 << 6)
479 #define UTMIP_USBOP_RPD_B               (1 << 8)
480 #define UTMIP_USBON_RPD_B               (1 << 9)
481 #define UTMIP_AP_B                      (1 << 12)
482 #define UTMIP_AN_B                      (1 << 13)
483 #define UTMIP_HIGHZ_B                   (1 << 14)
484 #define UTMIP_USBOP_RPD_C               (1 << 16)
485 #define UTMIP_USBON_RPD_C               (1 << 17)
486 #define UTMIP_AP_C                      (1 << 20)
487 #define UTMIP_AN_C                      (1 << 21)
488 #define UTMIP_HIGHZ_C                   (1 << 22)
489 #define UTMIP_USBOP_RPD_D               (1 << 24)
490 #define UTMIP_USBON_RPD_D               (1 << 25)
491 #define UTMIP_AP_D                      (1 << 28)
492 #define UTMIP_AN_D                      (1 << 29)
493 #define UTMIP_HIGHZ_D                   (1 << 30)
494
495 #define UTMIP_PMC_WAKEUP0               0x84c
496 #define  EVENT_INT_ENB                  (1 << 0)
497
498 #define UTMIP_UHSIC_STATUS              0x214
499 #define UTMIP_WALK_PTR_VAL(inst)        (0x3 << ((inst)*2))
500 #define UTMIP_USBOP_VAL(inst)           (1 << ((2*(inst)) + 8))
501 #define UTMIP_USBOP_VAL_P2              (1 << 12)
502 #define UTMIP_USBOP_VAL_P1              (1 << 10)
503 #define UTMIP_USBOP_VAL_P0              (1 << 8)
504 #define UTMIP_USBON_VAL(inst)           (1 << ((2*(inst)) + 9))
505 #define UTMIP_USBON_VAL_P2              (1 << 13)
506 #define UTMIP_USBON_VAL_P1              (1 << 11)
507 #define UTMIP_USBON_VAL_P0              (1 << 9)
508 #define UTMIP_WAKE_ALARM(inst)          (1 << ((inst) + 16))
509 #define UTMIP_WAKE_ALARM_P2             (1 << 18)
510 #define UTMIP_WAKE_ALARM_P1             (1 << 17)
511 #define UTMIP_WAKE_ALARM_P0             (1 << 16)
512 #define UTMIP_WALK_PTR(inst)            (1 << ((inst)*2))
513 #define UTMIP_WALK_PTR_P2               (1 << 4)
514 #define UTMIP_WALK_PTR_P1               (1 << 2)
515 #define UTMIP_WALK_PTR_P0               (1 << 0)
516
517 #define UTMIP_BIAS_STS0         0x840
518 #define UTMIP_RCTRL_VAL(x)      (((x) & 0xffff) << 0)
519 #define UTMIP_TCTRL_VAL(x)      (((x) & (0xffff << 16)) >> 16)
520
521 #define PMC_UTMIP_TERM_PAD_CFG  0x1f8
522 #define PMC_TCTRL_VAL(x)        (((x) & 0x1f) << 5)
523 #define PMC_RCTRL_VAL(x)        (((x) & 0x1f) << 0)
524
525 #define UHSIC_SLEEPWALK_REG     0x210
526 #define UHSIC_DATA_RPD_D                (1 << 25)
527 #define UHSIC_STRB_RPD_D                (1 << 24)
528 #define UHSIC_DATA_RPD_C                (1 << 17)
529 #define UHSIC_STRB_RPD_C                (1 << 16)
530 #define UHSIC_DATA_RPD_B                (1 << 9)
531 #define UHSIC_STRB_RPD_B                (1 << 8)
532 #define UHSIC_DATA_RPD_A                (1 << 1)
533 #define UHSIC_STRB_RPD_A                (1 << 0)
534
535 static u32 utmip_rctrl_val, utmip_tctrl_val;
536
537 #endif
538
539 /* Common registers */
540 #define UTMIP_MISC_CFG0         0x824
541 #define   UTMIP_DPDM_OBSERVE            (1 << 26)
542 #define   UTMIP_DPDM_OBSERVE_SEL(x)     (((x) & 0xf) << 27)
543 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J   UTMIP_DPDM_OBSERVE_SEL(0xf)
544 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K   UTMIP_DPDM_OBSERVE_SEL(0xe)
545 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
546 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
547 #define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
548 #define   FORCE_PULLDN_DM       (1 << 8)
549 #define   FORCE_PULLDN_DP       (1 << 9)
550 #define   COMB_TERMS            (1 << 0)
551 #define   ALWAYS_FREE_RUNNING_TERMS     (1 << 1)
552
553 #define ULPIS2S_CTRL            0x418
554 #define   ULPIS2S_ENA                   (1 << 0)
555 #define   ULPIS2S_SUPPORT_DISCONNECT    (1 << 2)
556 #define   ULPIS2S_PLLU_MASTER_BLASTER60 (1 << 3)
557 #define   ULPIS2S_SPARE(x)              (((x) & 0xF) << 8)
558 #define   ULPIS2S_FORCE_ULPI_CLK_OUT    (1 << 12)
559 #define   ULPIS2S_DISCON_DONT_CHECK_SE0 (1 << 13)
560 #define   ULPIS2S_SUPPORT_HS_KEEP_ALIVE (1 << 14)
561 #define   ULPIS2S_DISABLE_STP_PU        (1 << 15)
562 #define   ULPIS2S_SLV0_CLAMP_XMIT       (1 << 16)
563
564
565 #define ULPI_TIMING_CTRL_0      0x424
566 #define   ULPI_CLOCK_OUT_DELAY(x)       ((x) & 0x1F)
567 #define   ULPI_OUTPUT_PINMUX_BYP        (1 << 10)
568 #define   ULPI_CLKOUT_PINMUX_BYP        (1 << 11)
569 #define   ULPI_SHADOW_CLK_LOOPBACK_EN   (1 << 12)
570 #define   ULPI_SHADOW_CLK_SEL           (1 << 13)
571 #define   ULPI_CORE_CLK_SEL             (1 << 14)
572 #define   ULPI_SHADOW_CLK_DELAY(x)      (((x) & 0x1F) << 16)
573 #define   ULPI_LBK_PAD_EN               (1 << 26)
574 #define   ULPI_LBK_PAD_E_INPUT_OR       (1 << 27)
575 #define   ULPI_CLK_OUT_ENA              (1 << 28)
576 #define   ULPI_CLK_PADOUT_ENA           (1 << 29)
577
578 #define ULPI_TIMING_CTRL_1      0x428
579 #define   ULPI_DATA_TRIMMER_LOAD        (1 << 0)
580 #define   ULPI_DATA_TRIMMER_SEL(x)      (((x) & 0x7) << 1)
581 #define   ULPI_STPDIRNXT_TRIMMER_LOAD   (1 << 16)
582 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
583 #define   ULPI_DIR_TRIMMER_LOAD         (1 << 24)
584 #define   ULPI_DIR_TRIMMER_SEL(x)       (((x) & 0x7) << 25)
585
586 #define UTMIP_SPARE_CFG0        0x834
587 #define   FUSE_SETUP_SEL                (1 << 3)
588 #define   FUSE_ATERM_SEL                (1 << 4)
589
590 #define FUSE_USB_CALIB_0                0x1F0
591 #define FUSE_USB_CALIB_XCVR_SETUP(x)    (((x) & 0x7F) << 0)
592
593 #define UHSIC_PLL_CFG0          0x800
594
595 #define UHSIC_CMD_CFG0                          0x824
596 #define   UHSIC_PRETEND_CONNECT_DETECT          (1 << 5)
597
598 #define UHSIC_SPARE_CFG0                        0x82c
599
600 /* These values (in milli second) are taken from the battery charging spec */
601 #define TDP_SRC_ON_MS    100
602 #define TDPSRC_CON_MS    40
603
604 #define CONNECT_DETECT_TIMEOUT          25000
605
606 #define AHB_MEM_PREFETCH_CFG3           0xe0
607 #define AHB_MEM_PREFETCH_CFG4           0xe4
608 #define AHB_MEM_PREFETCH_CFG1           0xec
609 #define AHB_MEM_PREFETCH_CFG2           0xf0
610 #define PREFETCH_ENB                    (1 << 31)
611
612 static DEFINE_SPINLOCK(utmip_pad_lock);
613 static int utmip_pad_count;
614
615 struct tegra_xtal_freq {
616         int freq;
617         u8 enable_delay;
618         u8 stable_count;
619         u8 active_delay;
620         u16 xtal_freq_count;
621         u16 debounce;
622         u8 pdtrk_count;
623 };
624
625 static const struct tegra_xtal_freq tegra_freq_table[] = {
626         {
627                 .freq = 12000000,
628                 .enable_delay = 0x02,
629                 .stable_count = 0x2F,
630                 .active_delay = 0x04,
631                 .xtal_freq_count = 0x76,
632                 .debounce = 0x7530,
633                 .pdtrk_count = 5,
634         },
635         {
636                 .freq = 13000000,
637                 .enable_delay = 0x02,
638                 .stable_count = 0x33,
639                 .active_delay = 0x05,
640                 .xtal_freq_count = 0x7F,
641                 .debounce = 0x7EF4,
642                 .pdtrk_count = 5,
643         },
644         {
645                 .freq = 19200000,
646                 .enable_delay = 0x03,
647                 .stable_count = 0x4B,
648                 .active_delay = 0x06,
649                 .xtal_freq_count = 0xBB,
650                 .debounce = 0xBB80,
651                 .pdtrk_count = 7,
652         },
653         {
654                 .freq = 26000000,
655                 .enable_delay = 0x04,
656                 .stable_count = 0x66,
657                 .active_delay = 0x09,
658                 .xtal_freq_count = 0xFE,
659                 .debounce = 0xFDE8,
660                 .pdtrk_count = 9,
661         },
662 };
663
664 static const struct tegra_xtal_freq tegra_uhsic_freq_table[] = {
665         {
666                 .freq = 12000000,
667                 .enable_delay = 0x02,
668                 .stable_count = 0x2F,
669                 .active_delay = 0x0,
670                 .xtal_freq_count = 0x1CA,
671         },
672         {
673                 .freq = 13000000,
674                 .enable_delay = 0x02,
675                 .stable_count = 0x33,
676                 .active_delay = 0x0,
677                 .xtal_freq_count = 0x1F0,
678         },
679         {
680                 .freq = 19200000,
681                 .enable_delay = 0x03,
682                 .stable_count = 0x4B,
683                 .active_delay = 0x0,
684                 .xtal_freq_count = 0x2DD,
685         },
686         {
687                 .freq = 26000000,
688                 .enable_delay = 0x04,
689                 .stable_count = 0x66,
690                 .active_delay = 0x0,
691                 .xtal_freq_count = 0x3E0,
692         },
693 };
694
695 static struct tegra_utmip_config utmip_default[] = {
696         [0] = {
697                 .hssync_start_delay = 9,
698                 .idle_wait_delay = 17,
699                 .elastic_limit = 16,
700                 .term_range_adj = 6,
701                 .xcvr_setup = 9,
702                 .xcvr_setup_offset = 0,
703                 .xcvr_use_fuses = 1,
704                 .xcvr_lsfslew = 2,
705                 .xcvr_lsrslew = 2,
706         },
707         [2] = {
708                 .hssync_start_delay = 9,
709                 .idle_wait_delay = 17,
710                 .elastic_limit = 16,
711                 .term_range_adj = 6,
712                 .xcvr_setup_offset = 0,
713                 .xcvr_use_fuses = 1,
714                 .xcvr_setup = 9,
715                 .xcvr_lsfslew = 2,
716                 .xcvr_lsrslew = 2,
717         },
718 };
719
720 struct usb_phy_plat_data usb_phy_data[] = {
721         { 0, 0, -1, NULL},
722         { 0, 0, -1, NULL},
723         { 0, 0, -1, NULL},
724 };
725
726 static int utmip_pad_open(struct tegra_usb_phy *phy)
727 {
728         phy->pad_clk = clk_get_sys("utmip-pad", NULL);
729         if (IS_ERR(phy->pad_clk)) {
730                 pr_err("%s: can't get utmip pad clock\n", __func__);
731                 return PTR_ERR(phy->pad_clk);
732         }
733
734         if (phy->instance == 0) {
735                 phy->pad_regs = phy->regs;
736         } else {
737                 phy->pad_regs = ioremap(TEGRA_USB_BASE, TEGRA_USB_SIZE);
738                 if (!phy->pad_regs) {
739                         pr_err("%s: can't remap usb registers\n", __func__);
740                         clk_put(phy->pad_clk);
741                         return -ENOMEM;
742                 }
743         }
744         return 0;
745 }
746
747 static void utmip_pad_close(struct tegra_usb_phy *phy)
748 {
749         if (phy->instance != 0)
750                 iounmap(phy->pad_regs);
751         clk_put(phy->pad_clk);
752 }
753
754 static int utmip_pad_power_on(struct tegra_usb_phy *phy)
755 {
756         unsigned long val, flags;
757         void __iomem *base = phy->pad_regs;
758
759         clk_enable(phy->pad_clk);
760
761         spin_lock_irqsave(&utmip_pad_lock, flags);
762
763         utmip_pad_count++;
764         val = readl(base + UTMIP_BIAS_CFG0);
765         val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
766 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
767         val |= UTMIP_HSSQUELCH_LEVEL(0x2) | UTMIP_HSDISCON_LEVEL(0x1) |
768                 UTMIP_HSDISCON_LEVEL_MSB;
769 #endif
770         writel(val, base + UTMIP_BIAS_CFG0);
771
772         spin_unlock_irqrestore(&utmip_pad_lock, flags);
773
774         clk_disable(phy->pad_clk);
775
776         return 0;
777 }
778
779 static int utmip_pad_power_off(struct tegra_usb_phy *phy, bool is_dpd)
780 {
781         unsigned long val, flags;
782         void __iomem *base = phy->pad_regs;
783
784         if (!utmip_pad_count) {
785                 pr_err("%s: utmip pad already powered off\n", __func__);
786                 return -EINVAL;
787         }
788
789         clk_enable(phy->pad_clk);
790
791         spin_lock_irqsave(&utmip_pad_lock, flags);
792
793         if (--utmip_pad_count == 0 && is_dpd) {
794                 val = readl(base + UTMIP_BIAS_CFG0);
795                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
796 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
797                 val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) | UTMIP_HSDISCON_LEVEL(~0) |
798                         UTMIP_HSDISCON_LEVEL_MSB);
799 #endif
800                 writel(val, base + UTMIP_BIAS_CFG0);
801         }
802
803         spin_unlock_irqrestore(&utmip_pad_lock, flags);
804
805         clk_disable(phy->pad_clk);
806
807         return 0;
808 }
809
810 static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result)
811 {
812         unsigned long timeout = 2500;
813         do {
814                 if ((readl(reg) & mask) == result)
815                         return 0;
816                 udelay(1);
817                 timeout--;
818         } while (timeout);
819         return -1;
820 }
821
822 static int utmi_wait_register_timeout(void __iomem *reg, u32 mask, u32 result,
823         unsigned long timeout)
824 {
825         do {
826                 if ((readl(reg) & mask) == result)
827                         return 0;
828                 udelay(1);
829                 timeout--;
830         } while (timeout);
831         return -1;
832 }
833
834 static void utmi_phy_clk_disable(struct tegra_usb_phy *phy)
835 {
836         unsigned long val;
837         void __iomem *base = phy->regs;
838
839 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
840         if (phy->instance == 0) {
841                 val = readl(base + USB_SUSP_CTRL);
842                 val |= USB_SUSP_SET;
843                 writel(val, base + USB_SUSP_CTRL);
844
845                 udelay(10);
846
847                 val = readl(base + USB_SUSP_CTRL);
848                 val &= ~USB_SUSP_SET;
849                 writel(val, base + USB_SUSP_CTRL);
850         }
851
852         if (phy->instance == 2) {
853                 val = readl(base + USB_PORTSC1);
854                 val |= USB_PORTSC1_PHCD;
855                 writel(val, base + USB_PORTSC1);
856         }
857 #else
858         val = readl(base + HOSTPC1_DEVLC);
859         val |= HOSTPC1_DEVLC_PHCD;
860         writel(val, base + HOSTPC1_DEVLC);
861 #endif
862         if (phy->instance == 2) {
863                 val = readl(base + USB_SUSP_CTRL);
864                 val |= USB_PHY_CLK_VALID_INT_ENB;
865                 writel(val, base + USB_SUSP_CTRL);
866         } else {
867                 val = readl(base + USB_SUSP_CTRL);
868                 val |= UTMIP_RESET;
869                 writel(val, base + USB_SUSP_CTRL);
870         }
871
872         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0)
873                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
874 }
875
876 static void utmi_phy_clk_enable(struct tegra_usb_phy *phy)
877 {
878         unsigned long val;
879         void __iomem *base = phy->regs;
880
881         if (phy->instance == 0) {
882                 val = readl(base + USB_SUSP_CTRL);
883                 val |= USB_SUSP_CLR;
884                 writel(val, base + USB_SUSP_CTRL);
885
886                 udelay(10);
887
888                 val = readl(base + USB_SUSP_CTRL);
889                 val &= ~USB_SUSP_CLR;
890                 writel(val, base + USB_SUSP_CTRL);
891         }
892
893 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
894         if (phy->instance == 2) {
895                 val = readl(base + USB_PORTSC1);
896                 val &= ~USB_PORTSC1_PHCD;
897                 writel(val, base + USB_PORTSC1);
898         }
899 #endif
900
901         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
902                                                      USB_PHY_CLK_VALID) < 0)
903                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
904 }
905
906 static void vbus_enable(struct tegra_usb_phy *phy)
907 {
908 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
909         int gpio_status;
910         int gpio = usb_phy_data[phy->instance].vbus_gpio;
911
912         if (gpio == -1)
913                 return;
914
915         gpio_status = gpio_request(gpio,"VBUS_USB");
916         if (gpio_status < 0) {
917                 printk("VBUS_USB request GPIO FAILED\n");
918                 WARN_ON(1);
919                 return;
920         }
921         if (gpio < TEGRA_NR_GPIOS) tegra_gpio_enable(gpio);
922         gpio_status = gpio_direction_output(gpio, 1);
923         if (gpio_status < 0) {
924                 printk("VBUS_USB request GPIO DIRECTION FAILED \n");
925                 WARN_ON(1);
926                 return;
927         }
928         gpio_set_value_cansleep(gpio, 1);
929 #else
930         if (phy->reg_vbus)
931                 regulator_enable(phy->reg_vbus);
932 #endif
933 }
934
935 static void vbus_disable(struct tegra_usb_phy *phy)
936 {
937 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
938         int gpio = usb_phy_data[phy->instance].vbus_gpio;
939
940         if (gpio == -1)
941                 return;
942
943         gpio_set_value_cansleep(gpio, 0);
944         gpio_free(gpio);
945 #else
946         if (phy->reg_vbus)
947                 regulator_disable(phy->reg_vbus);
948 #endif
949 }
950
951 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
952 static void utmip_phy_enable_trking_data(struct tegra_usb_phy *phy)
953 {
954         void __iomem *base = phy->pad_regs;
955         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
956         static bool init_done = false;
957         u32 val;
958
959         /* Should be done only once after system boot */
960         if (init_done)
961                 return;
962
963         clk_enable(phy->pad_clk);
964         /* Bias pad MASTER_ENABLE=1 */
965         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
966         val |= BIAS_MASTER_PROG_VAL;
967         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
968
969         /* Setting the tracking length time */
970         val = readl(base + UTMIP_BIAS_CFG1);
971         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
972         val |= UTMIP_BIAS_PDTRK_COUNT(5);
973         writel(val, base + UTMIP_BIAS_CFG1);
974
975         /* Bias PDTRK is Shared and MUST be done from USB1 ONLY, PD_TRK=0 */
976         val = readl(base + UTMIP_BIAS_CFG1);
977         val &= ~ UTMIP_BIAS_PDTRK_POWERDOWN;
978         writel(val, base + UTMIP_BIAS_CFG1);
979
980         val = readl(base + UTMIP_BIAS_CFG1);
981         val |= UTMIP_BIAS_PDTRK_POWERUP;
982         writel(val, base + UTMIP_BIAS_CFG1);
983
984         /* Wait for 25usec */
985         udelay(25);
986
987         /* Bias pad MASTER_ENABLE=0 */
988         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
989         val &= ~BIAS_MASTER_PROG_VAL;
990         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
991
992         /* Wait for 1usec */
993         udelay(1);
994
995         /* Bias pad MASTER_ENABLE=1 */
996         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
997         val |= BIAS_MASTER_PROG_VAL;
998         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
999
1000         /* Read RCTRL and TCTRL from UTMIP space */
1001         val = readl(base + UTMIP_BIAS_STS0);
1002         utmip_rctrl_val = ffz(UTMIP_RCTRL_VAL(val));
1003         utmip_tctrl_val = ffz(UTMIP_TCTRL_VAL(val));
1004
1005         /* PD_TRK=1 */
1006         val = readl(base + UTMIP_BIAS_CFG1);
1007         val |= UTMIP_BIAS_PDTRK_POWERDOWN;
1008         writel(val, base + UTMIP_BIAS_CFG1);
1009
1010         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
1011         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
1012         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
1013         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
1014         clk_disable(phy->pad_clk);
1015         init_done = true;
1016 }
1017
1018 static void utmip_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy)
1019 {
1020         unsigned long val;
1021         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1022         unsigned  int inst = phy->instance;
1023
1024         /* power down UTMIP interfaces */
1025         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
1026         val |= UTMIP_PWR(inst);
1027         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
1028
1029         /* setup sleep walk usb controller */
1030         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
1031                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
1032                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
1033                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
1034         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
1035
1036         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
1037         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
1038         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
1039         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
1040
1041         /* Turn over pad configuration to PMC */
1042         val = readl(pmc_base + PMC_SLEEP_CFG);
1043         val &= ~UTMIP_WAKE_VAL(inst, ~0);
1044         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE) |
1045                 UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
1046                 UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst);
1047         writel(val, pmc_base + PMC_SLEEP_CFG);
1048 }
1049
1050 static void utmip_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
1051 {
1052         unsigned long val;
1053         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1054         unsigned  int inst = phy->instance;
1055
1056         /* Disable PMC master mode by clearing MASTER_EN */
1057         val = readl(pmc_base + PMC_SLEEP_CFG);
1058         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
1059                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
1060         writel(val, pmc_base + PMC_SLEEP_CFG);
1061         mdelay(1);
1062 }
1063
1064 static void uhsic_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy)
1065 {
1066         unsigned long val;
1067         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1068
1069         /* turn on pad detectors for HSIC*/
1070         val = readl(pmc_base + PMC_USB_AO);
1071         val |= (HSIC_RESERVED_P0 | HSIC_STOBE_VAL_PD_P0 | HSIC_DATA_VAL_PD_P0);
1072         writel(val, pmc_base + PMC_USB_AO);
1073
1074         /* enable pull downs on HSIC PMC */
1075         val = UHSIC_STRB_RPD_A | UHSIC_DATA_RPD_A | UHSIC_STRB_RPD_B |
1076                 UHSIC_DATA_RPD_B | UHSIC_STRB_RPD_C | UHSIC_DATA_RPD_C |
1077                 UHSIC_STRB_RPD_D | UHSIC_DATA_RPD_D;
1078         writel(val, pmc_base + UHSIC_SLEEPWALK_REG);
1079
1080         /* Turn over pad configuration to PMC */
1081         val = readl(pmc_base + PMC_SLEEP_CFG);
1082         val &= ~UHSIC_WAKE_VAL_P0(~0);
1083         val |= UHSIC_WAKE_VAL_P0(WAKE_VAL_NONE) | UHSIC_MASTER_ENABLE_P0;
1084         writel(val, pmc_base + PMC_SLEEP_CFG);
1085 }
1086
1087 static void uhsic_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
1088 {
1089         unsigned long val;
1090         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1091
1092         /* turn on pad detectors for HSIC*/
1093         val = readl(pmc_base + PMC_USB_AO);
1094         val &= ~(HSIC_RESERVED_P0 | HSIC_STOBE_VAL_PD_P0 | HSIC_DATA_VAL_PD_P0);
1095         writel(val, pmc_base + PMC_USB_AO);
1096
1097         /* Disable PMC master mode by clearing MASTER_EN */
1098         val = readl(pmc_base + PMC_SLEEP_CFG);
1099         val &= ~(UHSIC_MASTER_ENABLE_P0);
1100         writel(val, pmc_base + PMC_SLEEP_CFG);
1101         mdelay(1);
1102 }
1103 #endif
1104
1105 static unsigned int tegra_phy_xcvr_setup_value(struct tegra_utmip_config *cfg)
1106 {
1107         signed long val;
1108
1109         if (cfg->xcvr_use_fuses) {
1110                 val = FUSE_USB_CALIB_XCVR_SETUP(
1111                                 tegra_fuse_readl(FUSE_USB_CALIB_0));
1112                 if (cfg->xcvr_setup_offset <= UTMIP_XCVR_MAX_OFFSET)
1113                         val = val + cfg->xcvr_setup_offset;
1114
1115                 if (val > UTMIP_XCVR_SETUP_MAX_VALUE) {
1116                         val = UTMIP_XCVR_SETUP_MAX_VALUE;
1117                         pr_info("%s: reset XCVR_SETUP to max value\n",
1118                                  __func__);
1119                 } else if (val < UTMIP_XCVR_SETUP_MIN_VALUE) {
1120                         val = UTMIP_XCVR_SETUP_MIN_VALUE;
1121                         pr_info("%s: reset XCVR_SETUP to min value\n",
1122                                  __func__);
1123                 }
1124         } else {
1125                 val = cfg->xcvr_setup;
1126         }
1127
1128         return (unsigned int)val;
1129 }
1130
1131 static int utmi_phy_power_on(struct tegra_usb_phy *phy, bool is_dpd)
1132 {
1133         unsigned long val;
1134         void __iomem *base = phy->regs;
1135         unsigned int xcvr_setup_value;
1136         struct tegra_utmip_config *config = phy->config;
1137
1138         val = readl(base + USB_SUSP_CTRL);
1139         val |= UTMIP_RESET;
1140         writel(val, base + USB_SUSP_CTRL);
1141
1142 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1143         if (phy->instance == 0) {
1144                 val = readl(base + USB1_LEGACY_CTRL);
1145                 val |= USB1_NO_LEGACY_MODE;
1146                 writel(val, base + USB1_LEGACY_CTRL);
1147         }
1148 #endif
1149
1150         val = readl(base + UTMIP_TX_CFG0);
1151         val |= UTMIP_FS_PREABMLE_J;
1152         writel(val, base + UTMIP_TX_CFG0);
1153
1154         val = readl(base + UTMIP_HSRX_CFG0);
1155         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
1156         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
1157         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
1158         writel(val, base + UTMIP_HSRX_CFG0);
1159
1160         val = readl(base + UTMIP_HSRX_CFG1);
1161         val &= ~UTMIP_HS_SYNC_START_DLY(~0);
1162         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
1163         writel(val, base + UTMIP_HSRX_CFG1);
1164
1165         val = readl(base + UTMIP_DEBOUNCE_CFG0);
1166         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
1167         val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
1168         writel(val, base + UTMIP_DEBOUNCE_CFG0);
1169
1170         val = readl(base + UTMIP_MISC_CFG0);
1171         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
1172         writel(val, base + UTMIP_MISC_CFG0);
1173
1174 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1175         val = readl(base + UTMIP_MISC_CFG1);
1176         val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) | UTMIP_PLLU_STABLE_COUNT(~0));
1177         val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |
1178                 UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count);
1179         writel(val, base + UTMIP_MISC_CFG1);
1180
1181         val = readl(base + UTMIP_PLL_CFG1);
1182         val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) | UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
1183         val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |
1184                 UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
1185         writel(val, base + UTMIP_PLL_CFG1);
1186 #endif
1187
1188         if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) {
1189                 val = readl(base + USB_SUSP_CTRL);
1190                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
1191                 writel(val, base + USB_SUSP_CTRL);
1192         }
1193
1194         utmip_pad_power_on(phy);
1195
1196         xcvr_setup_value = phy->xcvr_setup_value;
1197
1198         val = readl(base + UTMIP_XCVR_CFG0);
1199         val &= ~(UTMIP_XCVR_LSBIAS_SEL | UTMIP_FORCE_PD_POWERDOWN |
1200                  UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN |
1201                  UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_LSFSLEW(~0) |
1202                  UTMIP_XCVR_LSRSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
1203         val |= UTMIP_XCVR_SETUP(xcvr_setup_value);
1204         val |= UTMIP_XCVR_SETUP_MSB(XCVR_SETUP_MSB_CALIB(xcvr_setup_value));
1205         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
1206         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
1207 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1208         val |= UTMIP_XCVR_HSSLEW_MSB(0x8);
1209 #endif
1210         writel(val, base + UTMIP_XCVR_CFG0);
1211
1212         val = readl(base + UTMIP_XCVR_CFG1);
1213         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1214                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
1215         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
1216         writel(val, base + UTMIP_XCVR_CFG1);
1217
1218         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1219         if (phy->mode == TEGRA_USB_PHY_MODE_HOST)
1220                 val |= UTMIP_PD_CHRG;
1221         else
1222                 val &= ~UTMIP_PD_CHRG;
1223         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1224
1225         val = readl(base + UTMIP_BIAS_CFG1);
1226         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
1227         val |= UTMIP_BIAS_PDTRK_COUNT(phy->freq->pdtrk_count);
1228         writel(val, base + UTMIP_BIAS_CFG1);
1229
1230 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1231         val = readl(base + UTMIP_SPARE_CFG0);
1232         val &= ~FUSE_SETUP_SEL;
1233         writel(val, base + UTMIP_SPARE_CFG0);
1234
1235         if (phy->instance == 2) {
1236                 val = readl(base + UTMIP_SPARE_CFG0);
1237                 val |= FUSE_SETUP_SEL;
1238                 writel(val, base + UTMIP_SPARE_CFG0);
1239
1240                 val = readl(base + USB_SUSP_CTRL);
1241                 val |= UTMIP_PHY_ENABLE;
1242                 writel(val, base + USB_SUSP_CTRL);
1243         }
1244 #else
1245         val = readl(base + UTMIP_SPARE_CFG0);
1246         val &= ~FUSE_SETUP_SEL;
1247         val |= FUSE_ATERM_SEL;
1248         writel(val, base + UTMIP_SPARE_CFG0);
1249
1250         val = readl(base + USB_SUSP_CTRL);
1251         val |= UTMIP_PHY_ENABLE;
1252         writel(val, base + USB_SUSP_CTRL);
1253 #endif
1254
1255         val = readl(base + USB_SUSP_CTRL);
1256         val &= ~UTMIP_RESET;
1257         writel(val, base + USB_SUSP_CTRL);
1258
1259         if (phy->instance == 0) {
1260                 val = readl(base + USB1_LEGACY_CTRL);
1261                 val &= ~USB1_VBUS_SENSE_CTL_MASK;
1262                 val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD;
1263                 writel(val, base + USB1_LEGACY_CTRL);
1264
1265 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1266                 val = readl(base + USB_SUSP_CTRL);
1267                 val &= ~USB_SUSP_SET;
1268                 writel(val, base + USB_SUSP_CTRL);
1269 #endif
1270         }
1271
1272         utmi_phy_clk_enable(phy);
1273 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1274         if (phy->instance == 2) {
1275                 val = readl(base + USB_PORTSC1);
1276                 val &= ~USB_PORTSC1_PTS(~0);
1277                 writel(val, base + USB_PORTSC1);
1278         }
1279 #else
1280         if (phy->instance == 0)
1281                 utmip_phy_enable_trking_data(phy);
1282
1283         if(phy->instance == 2) {
1284                 writel(0, base + ICUSB_CTRL);
1285         }
1286
1287         if (phy->mode == TEGRA_USB_PHY_MODE_HOST) {
1288                 val = readl(base + TEGRA_USB_USBMODE_REG_OFFSET);
1289                 writel((val | TEGRA_USB_USBMODE_HOST),
1290                         (base + TEGRA_USB_USBMODE_REG_OFFSET));
1291         }
1292         val = readl(base + HOSTPC1_DEVLC);
1293         val &= ~HOSTPC1_DEVLC_PTS(~0);
1294         val |= HOSTPC1_DEVLC_STS;
1295         writel(val, base + HOSTPC1_DEVLC);
1296
1297         if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE)
1298                 utmip_powerup_pmc_wake_detect(phy);
1299 #endif
1300
1301         return 0;
1302 }
1303
1304 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1305 static void utmip_setup_pmc_wake_detect(struct tegra_usb_phy *phy)
1306 {
1307         unsigned long val, pmc_pad_cfg_val;
1308         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1309         unsigned  int inst = phy->instance;
1310         void __iomem *base = phy->regs;
1311         bool port_connected;
1312         enum tegra_usb_phy_port_speed port_speed;
1313
1314         /* check for port connect status */
1315         val = readl(base + USB_PORTSC1);
1316         port_connected = val & USB_PORTSC1_CCS;
1317
1318         if (!port_connected)
1319                 return;
1320
1321         port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
1322                 HOSTPC1_DEVLC_PSPD_MASK;
1323         /*Set PMC MASTER bits to do the following
1324         * a. Take over the UTMI drivers
1325         * b. set up such that it will take over resume
1326         *    if remote wakeup is detected
1327         * Prepare PMC to take over suspend-wake detect-drive resume until USB
1328         * controller ready
1329         */
1330
1331         /* disable master enable in PMC */
1332         val = readl(pmc_base + PMC_SLEEP_CFG);
1333         val &= ~UTMIP_MASTER_ENABLE(inst);
1334         writel(val, pmc_base + PMC_SLEEP_CFG);
1335
1336         /* UTMIP_PWR_PX=1 for power savings mode */
1337         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
1338         val |= UTMIP_PWR(inst);
1339         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
1340
1341         /* config debouncer */
1342         val = readl(pmc_base + PMC_USB_DEBOUNCE);
1343         val &= ~UTMIP_LINE_DEB_CNT(~0);
1344         val |= UTMIP_LINE_DEB_CNT(1);
1345         writel(val, pmc_base + PMC_USB_DEBOUNCE);
1346
1347         /* Make sure nothing is happening on the line with respect to PMC */
1348         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
1349         val &= ~USBOP_VAL(inst);
1350         val &= ~USBON_VAL(inst);
1351         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
1352
1353         /* Make sure wake value for line is none */
1354         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
1355         val &= ~UTMIP_LINEVAL_WALK_EN(inst);
1356         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
1357         val = readl(pmc_base + PMC_SLEEP_CFG);
1358         val &= ~UTMIP_WAKE_VAL(inst, ~0);
1359         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
1360         writel(val, pmc_base + PMC_SLEEP_CFG);
1361
1362         /* turn off pad detectors */
1363         val = readl(pmc_base + PMC_USB_AO);
1364         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
1365         writel(val, pmc_base + PMC_USB_AO);
1366
1367         /* Remove fake values and make synchronizers work a bit */
1368         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
1369         val &= ~USBOP_VAL(inst);
1370         val &= ~USBON_VAL(inst);
1371         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
1372
1373         /* Enable which type of event can trigger a walk,
1374         in this case usb_line_wake */
1375         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
1376         val |= UTMIP_LINEVAL_WALK_EN(inst);
1377         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
1378
1379         /* Enable which type of event can trigger a walk,
1380         * in this case usb_line_wake */
1381         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
1382         val |= UTMIP_LINEVAL_WALK_EN(inst);
1383         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
1384
1385         /* Clear the walk pointers and wake alarm */
1386         val = readl(pmc_base + PMC_TRIGGERS);
1387         val |= UTMIP_CLR_WAKE_ALARM(inst) | UTMIP_CLR_WALK_PTR(inst);
1388         writel(val, pmc_base + PMC_TRIGGERS);
1389
1390
1391         /* Capture FS/LS pad configurations */
1392         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
1393         val = readl(pmc_base + PMC_TRIGGERS);
1394         val |= UTMIP_CAP_CFG(inst);
1395         writel(val, pmc_base + PMC_TRIGGERS);
1396         udelay(1);
1397         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
1398
1399         /* BIAS MASTER_ENABLE=0 */
1400         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
1401         val &= ~BIAS_MASTER_PROG_VAL;
1402         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
1403
1404         /* program walk sequence, maintain a J, followed by a driven K
1405         * to signal a resume once an wake event is detected */
1406         val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
1407         val &= ~UTMIP_AP_A;
1408         val |= UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A| UTMIP_AN_A | UTMIP_HIGHZ_A |
1409                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_AP_B |
1410                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_AP_C |
1411                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_AP_D;
1412         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
1413
1414         if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW) {
1415                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
1416                 val &= ~(UTMIP_AN_B | UTMIP_HIGHZ_B | UTMIP_AN_C |
1417                         UTMIP_HIGHZ_C | UTMIP_AN_D | UTMIP_HIGHZ_D);
1418                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
1419         } else {
1420                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
1421                 val &= ~(UTMIP_AP_B | UTMIP_HIGHZ_B | UTMIP_AP_C |
1422                         UTMIP_HIGHZ_C | UTMIP_AP_D | UTMIP_HIGHZ_D);
1423                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
1424         }
1425
1426         /* turn on pad detectors */
1427         val = readl(pmc_base + PMC_USB_AO);
1428         val &= ~(USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
1429         writel(val, pmc_base + PMC_USB_AO);
1430
1431         /* Add small delay before usb detectors provide stable line values */
1432         mdelay(1);
1433
1434         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
1435         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
1436         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
1437         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
1438
1439         phy->remote_wakeup = false;
1440
1441         /* Turn over pad configuration to PMC  for line wake events*/
1442         val = readl(pmc_base + PMC_SLEEP_CFG);
1443         val &= ~UTMIP_WAKE_VAL(inst, ~0);
1444         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_ANY);
1445         val |= UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst);
1446         val |= UTMIP_MASTER_ENABLE(inst) | UTMIP_FSLS_USE_PMC(inst);
1447         writel(val, pmc_base + PMC_SLEEP_CFG);
1448
1449         val = readl(base + UTMIP_PMC_WAKEUP0);
1450         val |= EVENT_INT_ENB;
1451         writel(val, base + UTMIP_PMC_WAKEUP0);
1452 }
1453 #endif
1454
1455 static int utmi_phy_power_off(struct tegra_usb_phy *phy, bool is_dpd)
1456 {
1457         unsigned long val;
1458         void __iomem *base = phy->regs;
1459
1460 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1461         if (phy->mode == TEGRA_USB_PHY_MODE_HOST)
1462                 utmip_setup_pmc_wake_detect(phy);
1463         else
1464                 utmip_powerdown_pmc_wake_detect(phy);
1465 #endif
1466         if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) {
1467                 val = readl(base + USB_SUSP_CTRL);
1468                 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
1469                 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
1470                 writel(val, base + USB_SUSP_CTRL);
1471         }
1472
1473         if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) {
1474                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1475                 val |= UTMIP_PD_CHRG;
1476                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1477         }
1478
1479         if (phy->instance != 2) {
1480                 val = readl(base + UTMIP_XCVR_CFG0);
1481                 val |= (UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
1482                          UTMIP_FORCE_PDZI_POWERDOWN);
1483                 writel(val, base + UTMIP_XCVR_CFG0);
1484         }
1485         val = readl(base + UTMIP_XCVR_CFG1);
1486         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1487                UTMIP_FORCE_PDDR_POWERDOWN;
1488         writel(val, base + UTMIP_XCVR_CFG1);
1489
1490 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1491         val = readl(base + UTMIP_BIAS_CFG1);
1492         val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
1493         writel(val, base + UTMIP_BIAS_CFG1);
1494 #endif
1495
1496         if (phy->hotplug) {
1497                 val = readl(base + USB_PORTSC1);
1498                 val |= USB_PORTSC1_WKCN;
1499                 writel(val, base + USB_PORTSC1);
1500         }
1501         if (phy->instance != 0) {
1502                 val = readl(base + UTMIP_BIAS_CFG0);
1503                 val |= UTMIP_OTGPD;
1504                 writel(val, base + UTMIP_BIAS_CFG0);
1505         }
1506
1507         utmi_phy_clk_disable(phy);
1508
1509         utmip_pad_power_off(phy, true);
1510         return 0;
1511 }
1512
1513 static void utmip_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy)
1514 {
1515 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1516         unsigned long val;
1517         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1518         unsigned  int inst = phy->instance;
1519         void __iomem *base = phy->regs;
1520
1521         val = readl(pmc_base + PMC_SLEEP_CFG);
1522         val &= ~UTMIP_WAKE_VAL(inst, 0x0);
1523         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
1524         writel(val, pmc_base + PMC_SLEEP_CFG);
1525
1526         val = readl(pmc_base + PMC_TRIGGERS);
1527         val |= UTMIP_CLR_WAKE_ALARM(inst) | UTMIP_CLR_WALK_PTR(inst);
1528         writel(val, pmc_base + PMC_TRIGGERS);
1529
1530         val = readl(base + UTMIP_PMC_WAKEUP0);
1531         val &= ~EVENT_INT_ENB;
1532         writel(val, base + UTMIP_PMC_WAKEUP0);
1533
1534         /* Disable PMC master mode by clearing MASTER_EN */
1535         val = readl(pmc_base + PMC_SLEEP_CFG);
1536         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
1537                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
1538         writel(val, pmc_base + PMC_SLEEP_CFG);
1539
1540         val = readl(pmc_base + PMC_TRIGGERS);
1541         val &= ~UTMIP_CAP_CFG(inst);
1542         writel(val, pmc_base + PMC_TRIGGERS);
1543
1544         /* turn off pad detectors */
1545         val = readl(pmc_base + PMC_USB_AO);
1546         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
1547         writel(val, pmc_base + PMC_USB_AO);
1548
1549         phy->remote_wakeup = false;
1550 #endif
1551 }
1552
1553 static void utmi_phy_enable_obs_bus(struct tegra_usb_phy *phy,
1554                                 enum tegra_usb_phy_port_speed port_speed)
1555 {
1556         unsigned long val;
1557         void __iomem *base = phy->regs;
1558
1559         /* (2LS WAR)is not required for LS and FS devices and is only for HS */
1560         if (port_speed != TEGRA_USB_PHY_PORT_SPEED_HIGH) {
1561                 /* do not enable the OBS bus */
1562                 val = readl(base + UTMIP_MISC_CFG0);
1563                 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1564                 writel(val, base + UTMIP_MISC_CFG0);
1565                 return;
1566         }
1567         /* Force DP/DM pulldown active for Host mode */
1568         val = readl(base + UTMIP_MISC_CFG0);
1569         val |= FORCE_PULLDN_DM | FORCE_PULLDN_DP |
1570                         COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS;
1571         writel(val, base + UTMIP_MISC_CFG0);
1572         val = readl(base + UTMIP_MISC_CFG0);
1573         val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1574         if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
1575                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
1576         else
1577                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
1578         writel(val, base + UTMIP_MISC_CFG0);
1579         udelay(1);
1580
1581         val = readl(base + UTMIP_MISC_CFG0);
1582         val |= UTMIP_DPDM_OBSERVE;
1583         writel(val, base + UTMIP_MISC_CFG0);
1584         udelay(10);
1585 }
1586
1587 static void utmi_phy_disable_obs_bus(struct tegra_usb_phy *phy)
1588 {
1589         unsigned long val;
1590         void __iomem *base = phy->regs;
1591
1592         /* check if OBS bus is already enabled */
1593         val = readl(base + UTMIP_MISC_CFG0);
1594         if (val & UTMIP_DPDM_OBSERVE) {
1595                 /* Change the UTMIP OBS bus to drive SE0 */
1596                 val = readl(base + UTMIP_MISC_CFG0);
1597                 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1598                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_SE0;
1599                 writel(val, base + UTMIP_MISC_CFG0);
1600
1601                 /* Wait for 3us(2 LS bit times) */
1602                 udelay (3);
1603
1604                 /* Release UTMIP OBS bus */
1605                 val = readl(base + UTMIP_MISC_CFG0);
1606                 val &= ~UTMIP_DPDM_OBSERVE;
1607                 writel(val, base + UTMIP_MISC_CFG0);
1608
1609                 /* Release DP/DM pulldown for Host mode */
1610                 val = readl(base + UTMIP_MISC_CFG0);
1611                 val &= ~(FORCE_PULLDN_DM | FORCE_PULLDN_DP |
1612                                 COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS);
1613                 writel(val, base + UTMIP_MISC_CFG0);
1614         }
1615 }
1616
1617
1618 static int utmi_phy_preresume(struct tegra_usb_phy *phy, bool remote_wakeup)
1619 {
1620 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1621         unsigned long val;
1622         void __iomem *base = phy->regs;
1623         enum tegra_usb_phy_port_speed port_speed;
1624
1625         val = readl(base + UTMIP_TX_CFG0);
1626         val |= UTMIP_HS_DISCON_DISABLE;
1627         writel(val, base + UTMIP_TX_CFG0);
1628
1629         port_speed = (readl(base + USB_PORTSC1) >> 26) & 0x3;
1630         utmi_phy_enable_obs_bus(phy, port_speed);
1631
1632 #else
1633         unsigned long val;
1634         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1635         unsigned  int inst = phy->instance;
1636         void __iomem *base = phy->regs;
1637         enum tegra_usb_phy_port_speed port_speed;
1638
1639         val = readl(pmc_base + PMC_SLEEP_CFG);
1640         if (val & UTMIP_MASTER_ENABLE(inst)) {
1641                 if (!remote_wakeup)
1642                         utmip_phy_disable_pmc_bus_ctrl(phy);
1643         } else {
1644                 port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
1645                         HOSTPC1_DEVLC_PSPD_MASK;
1646                 utmi_phy_enable_obs_bus(phy, port_speed);
1647         }
1648 #endif
1649
1650         return 0;
1651 }
1652
1653 static int utmi_phy_postresume(struct tegra_usb_phy *phy, bool is_dpd)
1654 {
1655         unsigned long val;
1656         void __iomem *base = phy->regs;
1657         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1658         unsigned  int inst = phy->instance;
1659
1660 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1661         val = readl(pmc_base + PMC_SLEEP_CFG);
1662         /* if PMC is not disabled by now then disable it */
1663         if (val & UTMIP_MASTER_ENABLE(inst)) {
1664                 utmip_phy_disable_pmc_bus_ctrl(phy);
1665         }
1666 #else
1667         val = readl(base + UTMIP_TX_CFG0);
1668         val &= ~UTMIP_HS_DISCON_DISABLE;
1669         writel(val, base + UTMIP_TX_CFG0);
1670 #endif
1671
1672         utmi_phy_disable_obs_bus(phy);
1673
1674         return 0;
1675 }
1676
1677 static int uhsic_phy_postsuspend(struct tegra_usb_phy *phy, bool is_dpd)
1678 {
1679         struct tegra_uhsic_config *uhsic_config = phy->config;
1680
1681         if (uhsic_config->postsuspend)
1682                 uhsic_config->postsuspend();
1683
1684         return 0;
1685 }
1686
1687 static int uhsic_phy_preresume(struct tegra_usb_phy *phy, bool remote_wakeup)
1688 {
1689         struct tegra_uhsic_config *uhsic_config = phy->config;
1690
1691         if (uhsic_config->preresume)
1692                 uhsic_config->preresume();
1693
1694         return 0;
1695 }
1696
1697 static int uhsic_phy_postresume(struct tegra_usb_phy *phy, bool is_dpd)
1698 {
1699         unsigned long val;
1700         void __iomem *base = phy->regs;
1701
1702         val = readl(base + USB_TXFILLTUNING);
1703         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
1704                 val = USB_FIFO_TXFILL_THRES(0x10);
1705                 writel(val, base + USB_TXFILLTUNING);
1706         }
1707
1708         return 0;
1709 }
1710
1711 static void utmi_phy_restore_start(struct tegra_usb_phy *phy,
1712                                    enum tegra_usb_phy_port_speed port_speed)
1713 {
1714 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1715         unsigned long val;
1716         void __iomem *base = phy->regs;
1717
1718         val = readl(base + UTMIP_MISC_CFG0);
1719         val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1720         if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
1721                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
1722         else
1723                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
1724         writel(val, base + UTMIP_MISC_CFG0);
1725         udelay(1);
1726
1727         val = readl(base + UTMIP_MISC_CFG0);
1728         val |= UTMIP_DPDM_OBSERVE;
1729         writel(val, base + UTMIP_MISC_CFG0);
1730         udelay(10);
1731 #else
1732         unsigned long val;
1733         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1734         int inst = phy->instance;
1735
1736         val = readl(pmc_base + UTMIP_UHSIC_STATUS);
1737         /* check whether we wake up from the remote resume */
1738         if (UTMIP_WALK_PTR_VAL(inst) & val) {
1739                 phy->remote_wakeup = true;
1740         } else {
1741                 if (!((UTMIP_USBON_VAL(phy->instance) |
1742                         UTMIP_USBOP_VAL(phy->instance)) & val)) {
1743                                 utmip_phy_disable_pmc_bus_ctrl(phy);
1744                 }
1745         }
1746         utmi_phy_enable_obs_bus(phy, port_speed);
1747 #endif
1748 }
1749
1750 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
1751 {
1752 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1753         unsigned long val;
1754         void __iomem *base = phy->regs;
1755
1756         val = readl(base + UTMIP_MISC_CFG0);
1757         val &= ~UTMIP_DPDM_OBSERVE;
1758         writel(val, base + UTMIP_MISC_CFG0);
1759         udelay(10);
1760 #else
1761         unsigned long val;
1762         void __iomem *base = phy->regs;
1763         int wait_time_us = 3000; /* FPR should be set by this time */
1764
1765         /* check whether we wake up from the remote resume */
1766         if (phy->remote_wakeup) {
1767                 /* wait until FPR bit is set automatically on remote resume */
1768                 do {
1769                         val = readl(base + USB_PORTSC1);
1770                         udelay(1);
1771                         if (wait_time_us == 0) {
1772                                 utmip_phy_disable_pmc_bus_ctrl(phy);
1773                                 tegra_usb_phy_postresume(phy, false);
1774                                 return;
1775                         }
1776                         wait_time_us--;
1777                 } while (!(val & USB_PORTSC1_RESUME));
1778                 /* wait for 25 ms to port resume complete */
1779                 msleep(25);
1780                 /* disable PMC master control */
1781                 utmip_phy_disable_pmc_bus_ctrl(phy);
1782
1783                 /* Clear PCI and SRI bits to avoid an interrupt upon resume */
1784                 val = readl(base + USB_USBSTS);
1785                 writel(val, base + USB_USBSTS);
1786                 /* wait to avoid SOF if there is any */
1787                 if (utmi_wait_register(base + USB_USBSTS,
1788                         USB_USBSTS_SRI, USB_USBSTS_SRI) < 0) {
1789                         pr_err("%s: timeout waiting for SOF\n", __func__);
1790                 }
1791                 tegra_usb_phy_postresume(phy, false);
1792         }
1793 #endif
1794 }
1795
1796 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1797 static void ulpi_set_tristate(bool enable)
1798 {
1799         int tristate = (enable)? TEGRA_TRI_TRISTATE : TEGRA_TRI_NORMAL;
1800
1801         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAA, tristate);
1802         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAB, tristate);
1803         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UDA, tristate);
1804 }
1805 #endif
1806
1807 static void ulpi_phy_reset(void __iomem *base)
1808 {
1809         unsigned long val;
1810
1811         val = readl(base + USB_SUSP_CTRL);
1812         val |= UHSIC_RESET;
1813         writel(val, base + USB_SUSP_CTRL);
1814
1815 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1816         val = readl(base + USB_SUSP_CTRL);
1817         val |= UTMIP_RESET;
1818         writel(val, base + USB_SUSP_CTRL);
1819 #endif
1820 }
1821
1822 static void ulpi_set_host(void __iomem *base)
1823 {
1824 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1825         unsigned long val;
1826
1827         val = readl(base + TEGRA_USB_USBMODE_REG_OFFSET);
1828         val |= TEGRA_USB_USBMODE_HOST;
1829         writel(val, base + TEGRA_USB_USBMODE_REG_OFFSET);
1830
1831         val = readl(base + HOSTPC1_DEVLC);
1832         val |= HOSTPC1_DEVLC_PTS(2);
1833         writel(val, base + HOSTPC1_DEVLC);
1834 #endif
1835 }
1836
1837 static void ulpi_set_trimmer(void __iomem *base, u8 data, u8 sdn, u8 dir)
1838 {
1839         unsigned long val;
1840
1841         val = ULPI_DATA_TRIMMER_SEL(data);
1842         val |= ULPI_STPDIRNXT_TRIMMER_SEL(sdn);
1843         val |= ULPI_DIR_TRIMMER_SEL(dir);
1844         writel(val, base + ULPI_TIMING_CTRL_1);
1845         udelay(10);
1846
1847         val |= ULPI_DATA_TRIMMER_LOAD;
1848         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
1849         val |= ULPI_DIR_TRIMMER_LOAD;
1850         writel(val, base + ULPI_TIMING_CTRL_1);
1851 }
1852
1853 static inline void ulpi_pinmux_bypass(struct tegra_usb_phy *phy, bool enable)
1854 {
1855         unsigned long val;
1856         void __iomem *base = phy->regs;
1857
1858         val = readl(base + ULPI_TIMING_CTRL_0);
1859
1860         if (enable)
1861                 val |= ULPI_OUTPUT_PINMUX_BYP;
1862         else
1863                 val &= ~ULPI_OUTPUT_PINMUX_BYP;
1864
1865         writel(val, base + ULPI_TIMING_CTRL_0);
1866 }
1867
1868 static void ulpi_phy_restore_start(struct tegra_usb_phy *phy,
1869                                    enum tegra_usb_phy_port_speed port_speed)
1870 {
1871 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1872         unsigned long val;
1873         void __iomem *base = phy->regs;
1874
1875         /*Tristate ulpi interface before USB controller resume*/
1876         ulpi_set_tristate(true);
1877
1878         val = readl(base + ULPI_TIMING_CTRL_0);
1879         val &= ~ULPI_OUTPUT_PINMUX_BYP;
1880         writel(val, base + ULPI_TIMING_CTRL_0);
1881 #endif
1882 }
1883
1884 static void ulpi_phy_restore_end(struct tegra_usb_phy *phy)
1885 {
1886 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1887         unsigned long val;
1888         void __iomem *base = phy->regs;
1889
1890         val = readl(base + ULPI_TIMING_CTRL_0);
1891         val |= ULPI_OUTPUT_PINMUX_BYP;
1892         writel(val, base + ULPI_TIMING_CTRL_0);
1893
1894         ulpi_set_tristate(false);
1895 #endif
1896 }
1897
1898 static int ulpi_phy_power_on(struct tegra_usb_phy *phy, bool is_dpd)
1899 {
1900         int ret;
1901         unsigned long val;
1902         void __iomem *base = phy->regs;
1903 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1904         struct tegra_ulpi_config *config = phy->config;
1905 #endif
1906
1907         if (phy->clk)
1908                 clk_enable(phy->clk);
1909
1910         msleep(1);
1911
1912         if (!phy->initialized) {
1913                 phy->initialized = 1;
1914 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1915                 gpio_direction_output(config->reset_gpio, 0);
1916                 msleep(5);
1917                 gpio_direction_output(config->reset_gpio, 1);
1918 #endif
1919         }
1920
1921         ulpi_phy_reset(base);
1922         ulpi_set_host(base);
1923
1924         val = readl(base + ULPI_TIMING_CTRL_0);
1925         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
1926         writel(val, base + ULPI_TIMING_CTRL_0);
1927
1928         val = readl(base + USB_SUSP_CTRL);
1929         val |= ULPI_PHY_ENABLE;
1930         writel(val, base + USB_SUSP_CTRL);
1931
1932         val = readl(base + USB_SUSP_CTRL);
1933         val |= USB_SUSP_CLR;
1934         writel(val, base + USB_SUSP_CTRL);
1935
1936 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1937         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
1938                                                      USB_PHY_CLK_VALID) < 0)
1939                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
1940
1941         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_CLKEN, USB_CLKEN) < 0)
1942                 pr_err("%s: timeout waiting for AHB clock\n", __func__);
1943 #else
1944         udelay(100);
1945 #endif
1946
1947         val = readl(base + USB_SUSP_CTRL);
1948         val &= ~USB_SUSP_CLR;
1949         writel(val, base + USB_SUSP_CTRL);
1950
1951         val = 0;
1952         writel(val, base + ULPI_TIMING_CTRL_1);
1953
1954         ulpi_set_trimmer(base, 4, 4, 4);
1955
1956         /* Fix VbusInvalid due to floating VBUS */
1957         ret = otg_io_write(phy->ulpi, 0x40, 0x08);
1958         if (ret) {
1959                 pr_err("%s: ulpi write failed\n", __func__);
1960                 return ret;
1961         }
1962
1963         ret = otg_io_write(phy->ulpi, 0x80, 0x0B);
1964         if (ret) {
1965                 pr_err("%s: ulpi write failed\n", __func__);
1966                 return ret;
1967         }
1968
1969         val = readl(base + USB_PORTSC1);
1970         val |= USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN;
1971         writel(val, base + USB_PORTSC1);
1972
1973         return 0;
1974 }
1975
1976 static int ulpi_phy_power_off(struct tegra_usb_phy *phy, bool is_dpd)
1977 {
1978         unsigned long val;
1979         void __iomem *base = phy->regs;
1980 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1981         int ret;
1982
1983         /* Disable VbusValid, SessEnd comparators */
1984         ret = otg_io_write(phy->ulpi, 0x00, 0x0D);
1985         if (ret)
1986                 pr_err("%s: ulpi write 0x0D failed\n", __func__);
1987
1988         ret = otg_io_write(phy->ulpi, 0x00, 0x10);
1989         if (ret)
1990                 pr_err("%s: ulpi write 0x10 failed\n", __func__);
1991
1992         /* Disable IdFloat comparator */
1993         ret = otg_io_write(phy->ulpi, 0x00, 0x19);
1994         if (ret)
1995                 pr_err("%s: ulpi write 0x19 failed\n", __func__);
1996
1997         ret = otg_io_write(phy->ulpi, 0x00, 0x1D);
1998         if (ret)
1999                 pr_err("%s: ulpi write 0x1D failed\n", __func__);
2000
2001         /* Clear WKCN/WKDS/WKOC wake-on events that can cause the USB
2002          * Controller to immediately bring the ULPI PHY out of low power
2003          */
2004         val = readl(base + USB_PORTSC1);
2005         val &= ~(USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN);
2006         writel(val, base + USB_PORTSC1);
2007
2008         /* Put the PHY in the low power mode */
2009         val = readl(base + USB_PORTSC1);
2010         val |= USB_PORTSC1_PHCD;
2011         writel(val, base + USB_PORTSC1);
2012
2013         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0)
2014                 pr_err("%s: timeout waiting for phy to stop\n", __func__);
2015 #else
2016         val = readl(base + HOSTPC1_DEVLC);
2017         val &= ~(HOSTPC1_DEVLC_PHCD);
2018         writel(val, base + HOSTPC1_DEVLC);
2019 #endif
2020
2021         if(phy->clk)
2022                 clk_disable(phy->clk);
2023
2024         return 0;
2025 }
2026
2027 static inline void null_phy_set_tristate(bool enable)
2028 {
2029         int tristate = (enable) ? TEGRA_TRI_TRISTATE : TEGRA_TRI_NORMAL;
2030
2031 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2032         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UDA, tristate);
2033         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAA, tristate);
2034         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAB, tristate);
2035 #else
2036         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA0, tristate);
2037         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA1, tristate);
2038         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA2, tristate);
2039         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA3, tristate);
2040         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA4, tristate);
2041         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA5, tristate);
2042         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA6, tristate);
2043         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA7, tristate);
2044         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_NXT, tristate);
2045
2046         if (enable)
2047                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR, tristate);
2048 #endif
2049 }
2050
2051 static void null_phy_restore_start(struct tegra_usb_phy *phy,
2052                                    enum tegra_usb_phy_port_speed port_speed)
2053 {
2054         struct tegra_ulpi_config *config = phy->config;
2055
2056         if (config->phy_restore_start)
2057                 config->phy_restore_start();
2058 }
2059
2060 static void null_phy_restore_end(struct tegra_usb_phy *phy)
2061 {
2062         unsigned long val;
2063         void __iomem *base = phy->regs;
2064         struct tegra_ulpi_config *config = phy->config;
2065
2066         /* disable ULPI pinmux bypass */
2067         ulpi_pinmux_bypass(phy, false);
2068
2069         /* driving linestate using GPIO */
2070         gpio_set_value(config->ulpi_d0_gpio, 0);
2071         gpio_set_value(config->ulpi_d1_gpio, 0);
2072
2073 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2074         /* driving DIR high */
2075         gpio_set_value(config->ulpi_dir_gpio, 1);
2076 #endif
2077
2078         /* remove ULPI tristate */
2079         null_phy_set_tristate(false);
2080
2081         if (config->phy_restore_end)
2082                 config->phy_restore_end();
2083
2084         if (gpio_is_valid(config->phy_restore_gpio)) {
2085                 int phy_restore_gpio = config->phy_restore_gpio;
2086                 int retry = 20000;
2087
2088                 while (retry) {
2089                         /* poll phy_restore_gpio high */
2090                         if (gpio_get_value(phy_restore_gpio))
2091                                 break;
2092                         retry--;
2093                 }
2094
2095                 if (retry == 0)
2096                         pr_info("phy_restore_gpio timeout\n");
2097         }
2098
2099         /* enable ULPI CLK output pad */
2100         val = readl(base + ULPI_TIMING_CTRL_0);
2101         val |= ULPI_CLK_PADOUT_ENA;
2102         writel(val, base + ULPI_TIMING_CTRL_0);
2103
2104 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2105         udelay(5); /* wait for CLK stabilize */
2106
2107         /* enable ULPI pinmux bypass */
2108         ulpi_pinmux_bypass(phy, true);
2109 #else
2110         /* enable ULPI pinmux bypass */
2111         ulpi_pinmux_bypass(phy, true);
2112         udelay(5);
2113
2114         /* remove DIR tristate */
2115         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR, TEGRA_TRI_NORMAL);
2116 #endif
2117 }
2118
2119 static int null_phy_power_on(struct tegra_usb_phy *phy, bool is_dpd)
2120 {
2121         const struct tegra_ulpi_trimmer default_trimmer = {0, 0, 4, 4};
2122         unsigned long val;
2123         void __iomem *base = phy->regs;
2124         struct tegra_ulpi_config *config = phy->config;
2125         static bool cold_boot = true;
2126
2127         if (!config->trimmer)
2128                 config->trimmer = &default_trimmer;
2129
2130         ulpi_phy_reset(base);
2131
2132 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2133         /* remove ULPI PADS CLKEN reset */
2134         val = readl(base + USB_SUSP_CTRL);
2135         val &= ~ULPI_PADS_CLKEN_RESET;
2136         writel(val, base + USB_SUSP_CTRL);
2137         udelay(10);
2138 #endif
2139         val = readl(base + ULPI_TIMING_CTRL_0);
2140         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
2141         writel(val, base + ULPI_TIMING_CTRL_0);
2142
2143         if (config->pre_phy_on && config->pre_phy_on())
2144                 return -EAGAIN;
2145
2146         val = readl(base + USB_SUSP_CTRL);
2147         val |= ULPI_PHY_ENABLE;
2148         writel(val, base + USB_SUSP_CTRL);
2149         udelay(10);
2150
2151         /* set timming parameters */
2152         val = readl(base + ULPI_TIMING_CTRL_0);
2153         val |= ULPI_SHADOW_CLK_LOOPBACK_EN;
2154 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2155         val &= ~ULPI_SHADOW_CLK_SEL;
2156         val &= ~ULPI_LBK_PAD_EN;
2157 #else
2158         val |= ULPI_SHADOW_CLK_SEL;
2159         val |= ULPI_LBK_PAD_EN;
2160 #endif
2161         val |= ULPI_SHADOW_CLK_DELAY(config->trimmer->shadow_clk_delay);
2162         val |= ULPI_CLOCK_OUT_DELAY(config->trimmer->clock_out_delay);
2163         val |= ULPI_LBK_PAD_E_INPUT_OR;
2164         writel(val, base + ULPI_TIMING_CTRL_0);
2165
2166         writel(0, base + ULPI_TIMING_CTRL_1);
2167         udelay(10);
2168
2169         /* start internal 60MHz clock */
2170         val = readl(base + ULPIS2S_CTRL);
2171         val |= ULPIS2S_ENA;
2172         val |= ULPIS2S_SUPPORT_DISCONNECT;
2173         val |= ULPIS2S_SPARE((phy->mode == TEGRA_USB_PHY_MODE_HOST) ? 3 : 1);
2174         val |= ULPIS2S_PLLU_MASTER_BLASTER60;
2175         writel(val, base + ULPIS2S_CTRL);
2176
2177         /* select ULPI_CORE_CLK_SEL to SHADOW_CLK */
2178         val = readl(base + ULPI_TIMING_CTRL_0);
2179         val |= ULPI_CORE_CLK_SEL;
2180         writel(val, base + ULPI_TIMING_CTRL_0);
2181         udelay(10);
2182
2183         /* enable ULPI null phy clock - can't set the trimmers before this */
2184         val = readl(base + ULPI_TIMING_CTRL_0);
2185         val |= ULPI_CLK_OUT_ENA;
2186         writel(val, base + ULPI_TIMING_CTRL_0);
2187         udelay(10);
2188
2189         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
2190                                                      USB_PHY_CLK_VALID)) {
2191                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2192                 return -ETIMEDOUT;
2193         }
2194
2195         /* set ULPI trimmers */
2196         ulpi_set_trimmer(base, config->trimmer->data_trimmer,
2197                          config->trimmer->stpdirnxt_trimmer, 1);
2198
2199         ulpi_set_host(base);
2200
2201 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2202         /* remove slave0 reset */
2203         val = readl(base + USB_SUSP_CTRL);
2204         val &= ~ULPIS2S_SLV0_RESET;
2205         writel(val, base + USB_SUSP_CTRL);
2206
2207         /* remove slave1 and line reset */
2208         val = readl(base + USB_SUSP_CTRL);
2209         val &= ~ULPIS2S_SLV1_RESET;
2210         val &= ~ULPIS2S_LINE_RESET;
2211
2212         /* remove ULPI PADS reset */
2213         val &= ~ULPI_PADS_RESET;
2214         writel(val, base + USB_SUSP_CTRL);
2215 #endif
2216         if (cold_boot) {
2217                 val = readl(base + ULPI_TIMING_CTRL_0);
2218                 val |= ULPI_CLK_PADOUT_ENA;
2219                 writel(val, base + ULPI_TIMING_CTRL_0);
2220                 cold_boot = false;
2221         }
2222
2223         udelay(10);
2224
2225         if (config->post_phy_on && config->post_phy_on())
2226                 return -EAGAIN;
2227
2228         return 0;
2229 }
2230
2231 static int null_phy_power_off(struct tegra_usb_phy *phy, bool is_dpd)
2232 {
2233         struct tegra_ulpi_config *config = phy->config;
2234
2235         if (config->pre_phy_off && config->pre_phy_off())
2236                 return -EAGAIN;
2237
2238         null_phy_set_tristate(true);
2239
2240         if (config->post_phy_off && config->post_phy_off())
2241                 return -EAGAIN;
2242
2243         return 0;
2244 }
2245
2246 static int null_phy_pre_usbcmd_reset(struct tegra_usb_phy *phy, bool is_dpd)
2247 {
2248 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2249         unsigned long val;
2250         void __iomem *base = phy->regs;
2251
2252         val = readl(base + ULPIS2S_CTRL);
2253         val |=  ULPIS2S_SLV0_CLAMP_XMIT;
2254         writel(val, base + ULPIS2S_CTRL);
2255
2256         val = readl(base + USB_SUSP_CTRL);
2257         val |= ULPIS2S_SLV0_RESET;
2258         writel(val, base + USB_SUSP_CTRL);
2259         udelay(10);
2260 #endif
2261         return 0;
2262 }
2263
2264 static int null_phy_post_usbcmd_reset(struct tegra_usb_phy *phy, bool is_dpd)
2265 {
2266 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2267         unsigned long val;
2268         void __iomem *base = phy->regs;
2269
2270         ulpi_set_host(base);
2271
2272         /* remove slave0 reset */
2273         val = readl(base + USB_SUSP_CTRL);
2274         val &= ~ULPIS2S_SLV0_RESET;
2275         writel(val, base + USB_SUSP_CTRL);
2276
2277         val = readl(base + ULPIS2S_CTRL);
2278         val &=  ~ULPIS2S_SLV0_CLAMP_XMIT;
2279         writel(val, base + ULPIS2S_CTRL);
2280         udelay(10);
2281 #endif
2282         return 0;
2283 }
2284
2285 static int uhsic_phy_power_on(struct tegra_usb_phy *phy, bool is_dpd)
2286 {
2287         unsigned long val;
2288         void __iomem *base = phy->regs;
2289         struct tegra_uhsic_config *uhsic_config = phy->config;
2290
2291 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2292         uhsic_powerup_pmc_wake_detect(phy);
2293 #endif
2294
2295         if (uhsic_config->enable_gpio != -1) {
2296                 gpio_set_value_cansleep(uhsic_config->enable_gpio, 1);
2297                 /* keep hsic reset asserted for 1 ms */
2298                 udelay(1000);
2299         }
2300
2301         val = readl(base + UHSIC_PADS_CFG1);
2302         val &= ~(UHSIC_PD_BG | UHSIC_PD_TX | UHSIC_PD_TRK | UHSIC_PD_RX |
2303                         UHSIC_PD_ZI | UHSIC_RPD_DATA | UHSIC_RPD_STROBE);
2304         val |= UHSIC_RX_SEL;
2305         writel(val, base + UHSIC_PADS_CFG1);
2306         udelay(2);
2307
2308         val = readl(base + USB_SUSP_CTRL);
2309         val |= UHSIC_RESET;
2310         writel(val, base + USB_SUSP_CTRL);
2311         udelay(30);
2312
2313         val = readl(base + USB_SUSP_CTRL);
2314         val |= UHSIC_PHY_ENABLE;
2315         writel(val, base + USB_SUSP_CTRL);
2316
2317         val = readl(base + UHSIC_HSRX_CFG0);
2318         val |= UHSIC_IDLE_WAIT(uhsic_config->idle_wait_delay);
2319         val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(uhsic_config->elastic_underrun_limit);
2320         val |= UHSIC_ELASTIC_OVERRUN_LIMIT(uhsic_config->elastic_overrun_limit);
2321         writel(val, base + UHSIC_HSRX_CFG0);
2322
2323         val = readl(base + UHSIC_HSRX_CFG1);
2324         val |= UHSIC_HS_SYNC_START_DLY(uhsic_config->sync_start_delay);
2325         writel(val, base + UHSIC_HSRX_CFG1);
2326
2327 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
2328         /* WAR HSIC TX */
2329         val = readl(base + UHSIC_TX_CFG0);
2330         val &= ~UHSIC_HS_READY_WAIT_FOR_VALID;
2331         writel(val, base + UHSIC_TX_CFG0);
2332 #endif
2333
2334         val = readl(base + UHSIC_MISC_CFG0);
2335         val |= UHSIC_SUSPEND_EXIT_ON_EDGE;
2336 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
2337         /* Disable generic bus reset, to allow AP30 specific bus reset*/
2338         val |= UHSIC_DISABLE_BUSRESET;
2339 #endif
2340         writel(val, base + UHSIC_MISC_CFG0);
2341
2342         val = readl(base + UHSIC_MISC_CFG1);
2343         val |= UHSIC_PLLU_STABLE_COUNT(phy->freq->stable_count);
2344         writel(val, base + UHSIC_MISC_CFG1);
2345
2346         val = readl(base + UHSIC_PLL_CFG1);
2347         val |= UHSIC_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
2348         val |= UHSIC_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count);
2349         writel(val, base + UHSIC_PLL_CFG1);
2350
2351         val = readl(base + USB_SUSP_CTRL);
2352         val &= ~(UHSIC_RESET);
2353         writel(val, base + USB_SUSP_CTRL);
2354         udelay(2);
2355
2356 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2357         val = readl(base + USB_PORTSC1);
2358         val &= ~USB_PORTSC1_PTS(~0);
2359         writel(val, base + USB_PORTSC1);
2360
2361 #endif
2362 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2363         val = readl(base + TEGRA_USB_USBMODE_REG_OFFSET);
2364         val |= TEGRA_USB_USBMODE_HOST;
2365         writel(val, base + TEGRA_USB_USBMODE_REG_OFFSET);
2366
2367         /* Change the USB controller PHY type to HSIC */
2368         val = readl(base + HOSTPC1_DEVLC);
2369         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
2370         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2371         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
2372         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2373         writel(val, base + HOSTPC1_DEVLC);
2374 #endif
2375         val = readl(base + USB_TXFILLTUNING);
2376         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
2377                 val = USB_FIFO_TXFILL_THRES(0x10);
2378                 writel(val, base + USB_TXFILLTUNING);
2379         }
2380
2381         val = readl(base + USB_PORTSC1);
2382         val &= ~(USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN);
2383         writel(val, base + USB_PORTSC1);
2384
2385         val = readl(base + UHSIC_PADS_CFG0);
2386         val &= ~(UHSIC_TX_RTUNEN);
2387 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2388         /* set Rtune impedance to 40 ohm */
2389         val |= UHSIC_TX_RTUNE(0);
2390 #else
2391         /* set Rtune impedance to 50 ohm */
2392         val |= UHSIC_TX_RTUNE(8);
2393 #endif
2394         writel(val, base + UHSIC_PADS_CFG0);
2395
2396         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
2397                                                         USB_PHY_CLK_VALID)) {
2398                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2399                 return -ETIMEDOUT;
2400         }
2401
2402         return 0;
2403 }
2404
2405 static int uhsic_phy_power_off(struct tegra_usb_phy *phy, bool is_dpd)
2406 {
2407         unsigned long val;
2408         void __iomem *base = phy->regs;
2409         struct tegra_uhsic_config *uhsic_config = phy->config;
2410
2411         val = readl(base + UHSIC_PADS_CFG1);
2412         val &= ~UHSIC_RPU_STROBE;
2413         val |= UHSIC_RPD_STROBE;
2414         writel(val, base + UHSIC_PADS_CFG1);
2415
2416         val = readl(base + USB_SUSP_CTRL);
2417         val |= UHSIC_RESET;
2418         writel(val, base + USB_SUSP_CTRL);
2419         udelay(30);
2420
2421         if (uhsic_config->enable_gpio != -1) {
2422                 gpio_set_value_cansleep(uhsic_config->enable_gpio, 0);
2423                 /* keep hsic reset de-asserted for 1 ms */
2424                 udelay(1000);
2425         }
2426         if (uhsic_config->post_phy_off && uhsic_config->post_phy_off())
2427                 return -EAGAIN;
2428
2429 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2430         uhsic_powerdown_pmc_wake_detect(phy);
2431 #endif
2432
2433         return 0;
2434 }
2435
2436 #ifdef CONFIG_USB_TEGRA_OTG
2437 extern void tegra_otg_check_vbus_detection(void);
2438 #endif
2439
2440 static irqreturn_t usb_phy_vbus_irq_thr(int irq, void *pdata)
2441 {
2442         struct tegra_usb_phy *phy = pdata;
2443
2444         if (phy->reg_vdd && !phy->regulator_on) {
2445                 regulator_enable(phy->reg_vdd);
2446                 phy->regulator_on = 1;
2447                 /*
2448                  * Optimal time to get the regulator turned on
2449                  * before detecting vbus interrupt.
2450                  */
2451                 mdelay(15);
2452         }
2453
2454 #ifdef CONFIG_USB_TEGRA_OTG
2455         tegra_otg_check_vbus_detection();
2456 #endif
2457
2458         return IRQ_HANDLED;
2459 }
2460
2461 struct tegra_usb_phy *tegra_usb_phy_open(int instance, void __iomem *regs,
2462                         void *config, enum tegra_usb_phy_mode phy_mode,
2463                         enum tegra_usb_phy_type usb_phy_type)
2464 {
2465         struct tegra_usb_phy *phy;
2466         struct tegra_ulpi_config *ulpi_config;
2467         unsigned long parent_rate;
2468         int i;
2469         int err;
2470 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2471         struct tegra_ulpi_config *uhsic_config;
2472         int reset_gpio, enable_gpio;
2473 #endif
2474
2475         phy = kzalloc(sizeof(struct tegra_usb_phy), GFP_KERNEL);
2476         if (!phy)
2477                 return ERR_PTR(-ENOMEM);
2478
2479         phy->instance = instance;
2480         phy->regs = regs;
2481         phy->config = config;
2482         phy->mode = phy_mode;
2483         phy->usb_phy_type = usb_phy_type;
2484         phy->initialized = 0;
2485         phy->regulator_on = 0;
2486         phy->power_on = 0;
2487         phy->remote_wakeup = false;
2488         phy->hotplug = 0;
2489         phy->xcvr_setup_value = 0;
2490
2491         if (!phy->config) {
2492                 if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_LINK_ULPI ||
2493                     phy->usb_phy_type == TEGRA_USB_PHY_TYPE_NULL_ULPI) {
2494                         pr_err("%s: ulpi phy configuration missing", __func__);
2495                         err = -EINVAL;
2496                         goto err0;
2497                 } else {
2498                         phy->config = &utmip_default[instance];
2499                 }
2500         }
2501
2502         phy->pll_u = clk_get_sys(NULL, "pll_u");
2503         if (IS_ERR(phy->pll_u)) {
2504                 pr_err("Can't get pll_u clock\n");
2505                 err = PTR_ERR(phy->pll_u);
2506                 goto err0;
2507         }
2508         clk_enable(phy->pll_u);
2509
2510         parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
2511         if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_HSIC) {
2512                 for (i = 0; i < ARRAY_SIZE(tegra_uhsic_freq_table); i++) {
2513                         if (tegra_uhsic_freq_table[i].freq == parent_rate) {
2514                                 phy->freq = &tegra_uhsic_freq_table[i];
2515                                 break;
2516                         }
2517                 }
2518         } else {
2519                 for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) {
2520                         if (tegra_freq_table[i].freq == parent_rate) {
2521                                 phy->freq = &tegra_freq_table[i];
2522                                 break;
2523                         }
2524                 }
2525         }
2526         if (!phy->freq) {
2527                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
2528                 err = -EINVAL;
2529                 goto err1;
2530         }
2531
2532         if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) {
2533                 err = utmip_pad_open(phy);
2534                 phy->xcvr_setup_value = tegra_phy_xcvr_setup_value(phy->config);
2535                 if (err < 0)
2536                         goto err1;
2537         } else if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_LINK_ULPI) {
2538                 ulpi_config = config;
2539
2540                 if (ulpi_config->clk) {
2541                         phy->clk = clk_get_sys(NULL, ulpi_config->clk);
2542                         if (IS_ERR(phy->clk)) {
2543                                 pr_err("%s: can't get ulpi clock\n", __func__);
2544                                 err = -ENXIO;
2545                                 goto err1;
2546                         }
2547                 } else {
2548                         /* Some USB ULPI chips are not driven by Tegra clocks or PLL */
2549                         phy->clk = NULL;
2550                 }
2551                 tegra_gpio_enable(ulpi_config->reset_gpio);
2552                 gpio_request(ulpi_config->reset_gpio, "ulpi_phy_reset_b");
2553                 gpio_direction_output(ulpi_config->reset_gpio, 0);
2554                 phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
2555                 phy->ulpi->io_priv = regs + ULPI_VIEWPORT;
2556         }
2557 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2558         else if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_HSIC) {
2559                 uhsic_config = config;
2560                 enable_gpio = gpio_request(uhsic_config->enable_gpio,
2561                         "uhsic_enable");
2562                 reset_gpio = gpio_request(uhsic_config->reset_gpio,
2563                                 "uhsic_reset");
2564                 /* hsic enable signal deasserted, hsic reset asserted */
2565                 if (!enable_gpio)
2566                         gpio_direction_output(uhsic_config->enable_gpio,
2567                         0 /* deasserted */);
2568                 if (!reset_gpio)
2569                         gpio_direction_output(uhsic_config->reset_gpio,
2570                                 0 /* asserted */);
2571                 if (!enable_gpio)
2572                         tegra_gpio_enable(uhsic_config->enable_gpio);
2573                 if (!reset_gpio)
2574                         tegra_gpio_enable(uhsic_config->reset_gpio);
2575                 /* keep hsic reset asserted for 1 ms */
2576                 udelay(1000);
2577                 /* enable (power on) hsic */
2578                 if (!enable_gpio)
2579                         gpio_set_value_cansleep(uhsic_config->enable_gpio, 1);
2580                 udelay(1000);
2581                 /* deassert reset */
2582                 if (!reset_gpio)
2583                         gpio_set_value_cansleep(uhsic_config->reset_gpio, 1);
2584         }
2585 #endif
2586
2587         phy->reg_vdd = regulator_get(NULL, "avdd_usb");
2588         if (IS_ERR_OR_NULL(phy->reg_vdd)) {
2589                 pr_err("couldn't get regulator avdd_usb: %ld \n",
2590                          PTR_ERR(phy->reg_vdd));
2591                 phy->reg_vdd = NULL;
2592         }
2593
2594         if (instance == 0 && usb_phy_data[0].vbus_irq) {
2595                 err = request_threaded_irq(usb_phy_data[0].vbus_irq, NULL, usb_phy_vbus_irq_thr, IRQF_SHARED,
2596                         "usb_phy_vbus", phy);
2597                 if (err) {
2598                         pr_err("Failed to register IRQ\n");
2599                         goto err1;
2600                 }
2601         }
2602
2603 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2604         /* Power-up the VBUS detector for UTMIP PHY */
2605         if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) {
2606                 unsigned long val;
2607                 void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
2608
2609                 /* turn on pad detectors for HSIC*/
2610                 val = readl(pmc_base + PMC_USB_AO);
2611                 val &= ~(TEGRA_PMC_USB_AO_VBUS_WAKEUP_PD_P0 | TEGRA_PMC_USB_AO_ID_PD_P0);
2612                 writel(val, pmc_base + PMC_USB_AO);
2613
2614                 utmip_powerup_pmc_wake_detect(phy);
2615
2616                 if (usb_phy_data[phy->instance].vbus_reg_supply) {
2617                         phy->reg_vbus = regulator_get(NULL, usb_phy_data[phy->instance].vbus_reg_supply);
2618                         if (WARN_ON(IS_ERR_OR_NULL(phy->reg_vbus))) {
2619                                 pr_err("couldn't get regulator vdd_vbus_usb: %ld, instance : %d\n",
2620                                         PTR_ERR(phy->reg_vbus), phy->instance);
2621                                 err = PTR_ERR(phy->reg_vbus);
2622                                 goto err1;
2623                         }
2624                 }
2625         }
2626         if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_HSIC) {
2627                 uhsic_powerup_pmc_wake_detect(phy);
2628         }
2629
2630 #endif
2631         if (((instance == 2) || (instance == 0)) &&
2632                 (phy->mode == TEGRA_USB_PHY_MODE_HOST)) {
2633                         vbus_enable(phy);
2634         }
2635         return phy;
2636
2637 err1:
2638         clk_disable(phy->pll_u);
2639         clk_put(phy->pll_u);
2640 err0:
2641         kfree(phy);
2642         return ERR_PTR(err);
2643 }
2644
2645 int tegra_usb_phy_power_on(struct tegra_usb_phy *phy, bool is_dpd)
2646 {
2647         int ret = 0;
2648
2649         const tegra_phy_fp power_on[] = {
2650                 utmi_phy_power_on,
2651                 ulpi_phy_power_on,
2652                 null_phy_power_on,
2653                 uhsic_phy_power_on,
2654         };
2655
2656         if (phy->power_on)
2657                 return ret;
2658
2659         if ((phy->instance == 0) && usb_phy_data[0].vbus_irq &&
2660                 (phy->mode == TEGRA_USB_PHY_MODE_DEVICE))
2661                 is_dpd = true;
2662
2663         if (phy->reg_vdd && !phy->regulator_on) {
2664                 regulator_enable(phy->reg_vdd);
2665                 phy->regulator_on = 1;
2666         }
2667
2668         if (power_on[phy->usb_phy_type])
2669                 ret = power_on[phy->usb_phy_type](phy, is_dpd);
2670
2671         phy->power_on = true;
2672         return ret;
2673 }
2674
2675 void tegra_usb_phy_power_off(struct tegra_usb_phy *phy, bool is_dpd)
2676 {
2677         const tegra_phy_fp power_off[] = {
2678                 utmi_phy_power_off,
2679                 ulpi_phy_power_off,
2680                 null_phy_power_off,
2681                 uhsic_phy_power_off,
2682         };
2683
2684         if (!phy->power_on)
2685                 return;
2686
2687         if ((phy->instance == 0) && usb_phy_data[0].vbus_irq &&
2688                 (phy->mode == TEGRA_USB_PHY_MODE_DEVICE))
2689                 is_dpd = true;
2690
2691         if (power_off[phy->usb_phy_type])
2692                 power_off[phy->usb_phy_type](phy, is_dpd);
2693
2694         if (phy->reg_vdd && phy->regulator_on && is_dpd) {
2695 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2696                 if (tegra_get_revision() >= TEGRA_REVISION_A03)
2697 #endif
2698                 regulator_disable(phy->reg_vdd);
2699                 phy->regulator_on = 0;
2700         }
2701         phy->power_on = false;
2702 }
2703
2704 void tegra_usb_phy_preresume(struct tegra_usb_phy *phy, bool remote_wakeup)
2705 {
2706         const tegra_phy_fp preresume[] = {
2707                 utmi_phy_preresume,
2708                 NULL,
2709                 NULL,
2710                 uhsic_phy_preresume,
2711         };
2712
2713         if (preresume[phy->usb_phy_type])
2714                 preresume[phy->usb_phy_type](phy, remote_wakeup);
2715 }
2716
2717 void tegra_usb_phy_postsuspend(struct tegra_usb_phy *phy, bool is_dpd)
2718
2719 {
2720         const tegra_phy_fp postsuspend[] = {
2721                 NULL,
2722                 NULL,
2723                 NULL,
2724                 uhsic_phy_postsuspend,
2725         };
2726
2727         if (postsuspend[phy->usb_phy_type])
2728                 postsuspend[phy->usb_phy_type](phy, is_dpd);
2729 }
2730
2731 void tegra_usb_phy_postresume(struct tegra_usb_phy *phy, bool is_dpd)
2732 {
2733         const tegra_phy_fp postresume[] = {
2734                 utmi_phy_postresume,
2735                 NULL,
2736                 NULL,
2737                 uhsic_phy_postresume,
2738         };
2739
2740         if (postresume[phy->usb_phy_type])
2741                 postresume[phy->usb_phy_type](phy, is_dpd);
2742 }
2743
2744 void tegra_ehci_pre_reset(struct tegra_usb_phy *phy, bool is_dpd)
2745 {
2746         const tegra_phy_fp pre_reset[] = {
2747                 NULL,
2748                 NULL,
2749                 null_phy_pre_usbcmd_reset,
2750                 NULL,
2751         };
2752
2753         if (pre_reset[phy->usb_phy_type])
2754                 pre_reset[phy->usb_phy_type](phy, is_dpd);
2755 }
2756
2757 void tegra_ehci_post_reset(struct tegra_usb_phy *phy, bool is_dpd)
2758 {
2759         const tegra_phy_fp post_reset[] = {
2760                 NULL,
2761                 NULL,
2762                 null_phy_post_usbcmd_reset,
2763                 NULL,
2764         };
2765
2766         if (post_reset[phy->usb_phy_type])
2767                 post_reset[phy->usb_phy_type](phy, is_dpd);
2768 }
2769
2770 void tegra_ehci_phy_restore_start(struct tegra_usb_phy *phy,
2771                                  enum tegra_usb_phy_port_speed port_speed)
2772 {
2773         const tegra_phy_restore_start_fp phy_restore_start[] = {
2774                 utmi_phy_restore_start,
2775                 ulpi_phy_restore_start,
2776                 null_phy_restore_start,
2777                 NULL,
2778         };
2779
2780         if (phy_restore_start[phy->usb_phy_type])
2781                 phy_restore_start[phy->usb_phy_type](phy, port_speed);
2782 }
2783
2784 void tegra_ehci_phy_restore_end(struct tegra_usb_phy *phy)
2785 {
2786         const tegra_phy_restore_end_fp phy_restore_end[] = {
2787                 utmi_phy_restore_end,
2788                 ulpi_phy_restore_end,
2789                 null_phy_restore_end,
2790                 NULL,
2791         };
2792
2793         if (phy_restore_end[phy->usb_phy_type])
2794                 phy_restore_end[phy->usb_phy_type](phy);
2795 }
2796
2797 void tegra_usb_phy_clk_disable(struct tegra_usb_phy *phy)
2798 {
2799         if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP)
2800                 utmi_phy_clk_disable(phy);
2801 }
2802
2803 void tegra_usb_phy_clk_enable(struct tegra_usb_phy *phy)
2804 {
2805         if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP)
2806                 utmi_phy_clk_enable(phy);
2807 }
2808
2809 void tegra_usb_phy_close(struct tegra_usb_phy *phy)
2810 {
2811         if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) {
2812                 utmip_pad_close(phy);
2813                 utmip_phy_disable_pmc_bus_ctrl(phy);
2814         }
2815         else if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_LINK_ULPI && phy->clk)
2816                 clk_put(phy->clk);
2817         if (phy->mode == TEGRA_USB_PHY_MODE_HOST) {
2818                 vbus_disable(phy);
2819         }
2820         clk_disable(phy->pll_u);
2821         clk_put(phy->pll_u);
2822         if (phy->reg_vbus)
2823                 regulator_put(phy->reg_vbus);
2824         if (phy->reg_vdd)
2825                 regulator_put(phy->reg_vdd);
2826         if (phy->instance == 0 && usb_phy_data[0].vbus_irq)
2827                 free_irq(usb_phy_data[0].vbus_irq, phy);
2828         kfree(phy);
2829 }
2830
2831 int tegra_usb_phy_bus_connect(struct tegra_usb_phy *phy)
2832 {
2833         unsigned long val;
2834         void __iomem *base = phy->regs;
2835         struct tegra_uhsic_config *uhsic_config = phy->config;
2836
2837         if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_HSIC) {
2838 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2839                 val = readl(base + TEGRA_USB_USBMODE_REG_OFFSET);
2840                 val |= TEGRA_USB_USBMODE_HOST;
2841                 writel(val, base + TEGRA_USB_USBMODE_REG_OFFSET);
2842
2843                 /* Change the USB controller PHY type to HSIC */
2844                 val = readl(base + HOSTPC1_DEVLC);
2845                 val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
2846                 val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2847                 val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
2848                 val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2849                 writel(val, base + HOSTPC1_DEVLC);
2850 #endif
2851                 val = readl(base + UHSIC_MISC_CFG0);
2852                 val |= UHSIC_DETECT_SHORT_CONNECT;
2853                 writel(val, base + UHSIC_MISC_CFG0);
2854                 udelay(1);
2855
2856                 val = readl(base + UHSIC_MISC_CFG0);
2857                 val |= UHSIC_FORCE_XCVR_MODE;
2858                 writel(val, base + UHSIC_MISC_CFG0);
2859
2860                 val = readl(base + UHSIC_PADS_CFG1);
2861                 val &= ~UHSIC_RPD_STROBE;
2862 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2863                 val |= UHSIC_RPU_STROBE;
2864 #endif
2865                 writel(val, base + UHSIC_PADS_CFG1);
2866
2867                 if (uhsic_config->usb_phy_ready &&
2868                                         uhsic_config->usb_phy_ready())
2869                         return -EAGAIN;
2870
2871                 /* connect detect on T30 requires extra wait */
2872                 if (utmi_wait_register_timeout(base + UHSIC_STAT_CFG0,
2873                             UHSIC_CONNECT_DETECT, UHSIC_CONNECT_DETECT,
2874                             CONNECT_DETECT_TIMEOUT) < 0) {
2875                         pr_err("%s: timeout waiting for hsic connect detect\n", __func__);
2876                         return -ETIMEDOUT;
2877                 }
2878
2879 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2880                 if (utmi_wait_register(base + USB_PORTSC1, USB_PORTSC1_LS(2), USB_PORTSC1_LS(2)) < 0) {
2881                         pr_err("%s: timeout waiting for dplus state\n", __func__);
2882                         return -ETIMEDOUT;
2883                 }
2884 #endif
2885         }
2886
2887         return 0;
2888 }
2889
2890 int tegra_usb_phy_bus_reset(struct tegra_usb_phy *phy)
2891 {
2892         unsigned long val;
2893         void __iomem *base = phy->regs;
2894
2895         if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_HSIC) {
2896 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2897                 /* Change the USB controller PHY type to HSIC */
2898                 val = readl(base + HOSTPC1_DEVLC);
2899                 val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
2900                 val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2901                 val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
2902                 val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2903                 writel(val, base + HOSTPC1_DEVLC);
2904                 /* wait here, otherwise HOSTPC1_DEVLC_PSPD will timeout */
2905                 mdelay(5);
2906 #endif
2907                 val = readl(base + USB_PORTSC1);
2908                 val |= USB_PORTSC1_PTC(5);
2909                 writel(val, base + USB_PORTSC1);
2910                 udelay(2);
2911
2912                 val = readl(base + USB_PORTSC1);
2913                 val &= ~USB_PORTSC1_PTC(~0);
2914                 writel(val, base + USB_PORTSC1);
2915                 udelay(2);
2916
2917                 if (utmi_wait_register(base + USB_PORTSC1, USB_PORTSC1_LS(0), 0) < 0) {
2918                         pr_err("%s: timeout waiting for SE0\n", __func__);
2919                         return -ETIMEDOUT;
2920                 }
2921
2922                 if (utmi_wait_register(base + USB_PORTSC1, USB_PORTSC1_CCS, USB_PORTSC1_CCS) < 0) {
2923                         pr_err("%s: timeout waiting for connection status\n", __func__);
2924                         return -ETIMEDOUT;
2925                 }
2926
2927 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
2928                 if (utmi_wait_register(base + USB_PORTSC1, USB_PORTSC1_PSPD(2), USB_PORTSC1_PSPD(2)) < 0) {
2929                         pr_err("%s: timeout waiting hsic high speed configuration\n", __func__);
2930                         return -ETIMEDOUT;
2931                 }
2932 #elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
2933                 if (utmi_wait_register(base + HOSTPC1_DEVLC,
2934                                 HOSTPC1_DEVLC_PSPD(2),
2935                                 HOSTPC1_DEVLC_PSPD(2)) < 0) {
2936                         pr_err("%s: timeout waiting hsic high speed configuration\n", __func__);
2937                         return -ETIMEDOUT;
2938                 }
2939 #endif
2940                 val = readl(base + USB_USBCMD);
2941                 val &= ~USB_USBCMD_RS;
2942                 writel(val, base + USB_USBCMD);
2943
2944                 if (utmi_wait_register(base + USB_USBSTS, USB_USBSTS_HCH, USB_USBSTS_HCH) < 0) {
2945                         pr_err("%s: timeout waiting for stopping the controller\n", __func__);
2946                         return -ETIMEDOUT;
2947                 }
2948
2949                 val = readl(base + UHSIC_PADS_CFG1);
2950                 val &= ~UHSIC_RPU_STROBE;
2951                 val |= UHSIC_RPD_STROBE;
2952                 writel(val, base + UHSIC_PADS_CFG1);
2953
2954                 mdelay(50);
2955
2956                 val = readl(base + UHSIC_PADS_CFG1);
2957                 val &= ~UHSIC_RPD_STROBE;
2958                 val |= UHSIC_RPU_STROBE;
2959                 writel(val, base + UHSIC_PADS_CFG1);
2960
2961                 val = readl(base + USB_USBCMD);
2962                 val |= USB_USBCMD_RS;
2963                 writel(val, base + USB_USBCMD);
2964
2965                 val = readl(base + UHSIC_PADS_CFG1);
2966                 val &= ~UHSIC_RPU_STROBE;
2967                 writel(val, base + UHSIC_PADS_CFG1);
2968
2969                 if (utmi_wait_register(base + USB_USBCMD, USB_USBCMD_RS, USB_USBCMD_RS) < 0) {
2970                         pr_err("%s: timeout waiting for starting the controller\n", __func__);
2971                         return -ETIMEDOUT;
2972                 }
2973         }
2974
2975         return 0;
2976 }
2977
2978 int tegra_usb_phy_bus_idle(struct tegra_usb_phy *phy)
2979 {
2980         unsigned long val;
2981         void __iomem *base = phy->regs;
2982         struct tegra_uhsic_config *uhsic_config = phy->config;
2983
2984         if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_HSIC) {
2985
2986 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2987                 val = readl(base + TEGRA_USB_USBMODE_REG_OFFSET);
2988                 val |= TEGRA_USB_USBMODE_HOST;
2989                 writel(val, base + TEGRA_USB_USBMODE_REG_OFFSET);
2990
2991                 /* Change the USB controller PHY type to HSIC */
2992                 val = readl(base + HOSTPC1_DEVLC);
2993                 val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
2994                 val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2995                 val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
2996                 val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2997                 writel(val, base + HOSTPC1_DEVLC);
2998 #endif
2999                 val = readl(base + UHSIC_MISC_CFG0);
3000                 val |= UHSIC_DETECT_SHORT_CONNECT;
3001                 writel(val, base + UHSIC_MISC_CFG0);
3002                 udelay(1);
3003
3004                 val = readl(base + UHSIC_MISC_CFG0);
3005                 val |= UHSIC_FORCE_XCVR_MODE;
3006                 writel(val, base + UHSIC_MISC_CFG0);
3007
3008                 val = readl(base + UHSIC_PADS_CFG1);
3009                 val &= ~UHSIC_RPD_STROBE;
3010                 /* safe to enable RPU on STROBE at all times during idle */
3011                 val |= UHSIC_RPU_STROBE;
3012                 writel(val, base + UHSIC_PADS_CFG1);
3013
3014                 val = readl(base + USB_USBCMD);
3015                 val &= ~USB_USBCMD_RS;
3016                 writel(val, base + USB_USBCMD);
3017
3018                 if (uhsic_config->usb_phy_ready &&
3019                                         uhsic_config->usb_phy_ready())
3020                         return -EAGAIN;
3021
3022                 /* connect detect on T30 requires extra wait */
3023                 if (utmi_wait_register_timeout(base + UHSIC_STAT_CFG0,
3024                             UHSIC_CONNECT_DETECT, UHSIC_CONNECT_DETECT,
3025                             CONNECT_DETECT_TIMEOUT) < 0) {
3026                         pr_err("%s: timeout waiting for hsic connect detect\n",
3027                                 __func__);
3028                         return -ETIMEDOUT;
3029                 }
3030         }
3031         return 0;
3032 }
3033
3034 bool tegra_usb_phy_is_device_connected(struct tegra_usb_phy *phy)
3035 {
3036         void __iomem *base = phy->regs;
3037
3038         if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_HSIC) {
3039                 if (utmi_wait_register(base + UHSIC_STAT_CFG0,
3040                         UHSIC_CONNECT_DETECT, UHSIC_CONNECT_DETECT) < 0) {
3041                         pr_err("%s: no hsic connection\n", __func__);
3042                         return false;
3043                 }
3044 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
3045                 if (utmi_wait_register(base + USB_PORTSC1, USB_PORTSC1_LS(2), USB_PORTSC1_LS(2)) < 0) {
3046                         pr_err("%s: timeout waiting for dplus state\n", __func__);
3047                         return false;
3048                 }
3049 #endif
3050         }
3051         return true;
3052 }
3053
3054 bool tegra_usb_phy_charger_detect(struct tegra_usb_phy *phy)
3055 {
3056         unsigned long val;
3057         void __iomem *base = phy->regs;
3058         bool status;
3059
3060         if (phy->usb_phy_type != TEGRA_USB_PHY_TYPE_UTMIP)
3061         {
3062                 /* Charger detection is not there for ULPI
3063                  * return Charger not available */
3064                 return false;
3065         }
3066
3067         /* Enable charger detection logic */
3068         val = readl(base + UTMIP_BAT_CHRG_CFG0);
3069         val |= UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN;
3070         writel(val, base + UTMIP_BAT_CHRG_CFG0);
3071
3072         /* Source should be on for 100 ms as per USB charging spec */
3073         msleep(TDP_SRC_ON_MS);
3074
3075         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
3076         /* If charger is not connected disable the interrupt */
3077         val &= ~VDAT_DET_INT_EN;
3078         val |= VDAT_DET_CHG_DET;
3079         writel(val,base + USB_PHY_VBUS_WAKEUP_ID);
3080
3081         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
3082         if (val & VDAT_DET_STS)
3083                 status = true;
3084         else
3085                 status = false;
3086
3087         /* Disable charger detection logic */
3088         val = readl(base + UTMIP_BAT_CHRG_CFG0);
3089         val &= ~(UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN);
3090         writel(val, base + UTMIP_BAT_CHRG_CFG0);
3091
3092         /* Delay of 40 ms before we pull the D+ as per battery charger spec */
3093         msleep(TDPSRC_CON_MS);
3094
3095         return status;
3096 }
3097
3098 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
3099 void tegra_usb_phy_power_down_pmc(void)
3100 {
3101         unsigned long val;
3102         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
3103
3104         /* power down all 3 UTMIP interfaces */
3105         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
3106         val |= UTMIP_PWR(0) | UTMIP_PWR(1) | UTMIP_PWR(2);
3107         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
3108
3109         /* turn on pad detectors */
3110         writel(PMC_POWER_DOWN_MASK, pmc_base + PMC_USB_AO);
3111
3112         /* setup sleep walk fl all 3 usb controllers */
3113         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
3114                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
3115                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
3116                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
3117         writel(val, pmc_base + PMC_SLEEPWALK_REG(0));
3118         writel(val, pmc_base + PMC_SLEEPWALK_REG(1));
3119         writel(val, pmc_base + PMC_SLEEPWALK_REG(2));
3120
3121         /* enable pull downs on HSIC PMC */
3122         val = UHSIC_STRB_RPD_A | UHSIC_DATA_RPD_A | UHSIC_STRB_RPD_B |
3123                 UHSIC_DATA_RPD_B | UHSIC_STRB_RPD_C | UHSIC_DATA_RPD_C |
3124                 UHSIC_STRB_RPD_D | UHSIC_DATA_RPD_D;
3125         writel(val, pmc_base + UHSIC_SLEEPWALK_REG);
3126
3127         /* Turn over pad configuration to PMC */
3128         val = readl(pmc_base + PMC_SLEEP_CFG);
3129         val &= ~UTMIP_WAKE_VAL(0, ~0);
3130         val &= ~UTMIP_WAKE_VAL(1, ~0);
3131         val &= ~UTMIP_WAKE_VAL(2, ~0);
3132         val &= ~UHSIC_WAKE_VAL_P0(~0);
3133         val |= UTMIP_WAKE_VAL(0, WAKE_VAL_NONE) | UHSIC_WAKE_VAL_P0(WAKE_VAL_NONE) |
3134         UTMIP_WAKE_VAL(1, WAKE_VAL_NONE) | UTMIP_WAKE_VAL(2, WAKE_VAL_NONE) |
3135         UTMIP_RCTRL_USE_PMC(0) | UTMIP_RCTRL_USE_PMC(1) | UTMIP_RCTRL_USE_PMC(2) |
3136         UTMIP_TCTRL_USE_PMC(0) | UTMIP_TCTRL_USE_PMC(1) | UTMIP_TCTRL_USE_PMC(2) |
3137         UTMIP_FSLS_USE_PMC(0) | UTMIP_FSLS_USE_PMC(1) | UTMIP_FSLS_USE_PMC(2) |
3138         UTMIP_MASTER_ENABLE(0) | UTMIP_MASTER_ENABLE(1) | UTMIP_MASTER_ENABLE(2) |
3139         UHSIC_MASTER_ENABLE_P0;
3140         writel(val, pmc_base + PMC_SLEEP_CFG);
3141 }
3142 #endif
3143
3144 int __init tegra_usb_phy_init(struct usb_phy_plat_data *pdata, int size)
3145 {
3146         if (pdata) {
3147                 int i;
3148
3149                 for (i = 0; i < size; i++, pdata++) {
3150                         usb_phy_data[pdata->instance].instance = pdata->instance;
3151                         usb_phy_data[pdata->instance].vbus_irq = pdata->vbus_irq;
3152                         usb_phy_data[pdata->instance].vbus_gpio = pdata->vbus_gpio;
3153                         usb_phy_data[pdata->instance].vbus_reg_supply = pdata->vbus_reg_supply;
3154                 }
3155         }
3156
3157 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
3158         tegra_usb_phy_power_down_pmc();
3159 #endif
3160
3161         return 0;
3162 }
3163
3164 void tegra_usb_phy_memory_prefetch_on(struct tegra_usb_phy *phy)
3165 {
3166         void __iomem *ahb_gizmo = IO_ADDRESS(TEGRA_AHB_GIZMO_BASE);
3167         unsigned long val;
3168
3169         if (phy->instance == 0 && phy->mode == TEGRA_USB_PHY_MODE_DEVICE) {
3170                 val = readl(ahb_gizmo + AHB_MEM_PREFETCH_CFG1);
3171                 val |= PREFETCH_ENB;
3172                 writel(val, ahb_gizmo + AHB_MEM_PREFETCH_CFG1);
3173                 val = readl(ahb_gizmo + AHB_MEM_PREFETCH_CFG2);
3174                 val |= PREFETCH_ENB;
3175                 writel(val, ahb_gizmo + AHB_MEM_PREFETCH_CFG2);
3176         }
3177 }
3178
3179 void tegra_usb_phy_memory_prefetch_off(struct tegra_usb_phy *phy)
3180 {
3181         void __iomem *ahb_gizmo = IO_ADDRESS(TEGRA_AHB_GIZMO_BASE);
3182         unsigned long val;
3183
3184         if (phy->instance == 0 && phy->mode == TEGRA_USB_PHY_MODE_DEVICE) {
3185                 val = readl(ahb_gizmo + AHB_MEM_PREFETCH_CFG1);
3186                 val &= ~(PREFETCH_ENB);
3187                 writel(val, ahb_gizmo + AHB_MEM_PREFETCH_CFG1);
3188                 val = readl(ahb_gizmo + AHB_MEM_PREFETCH_CFG2);
3189                 val &= ~(PREFETCH_ENB);
3190                 writel(val, ahb_gizmo + AHB_MEM_PREFETCH_CFG2);
3191         }
3192 }
3193
3194 /* disable walk and wake events after resume from LP0 */
3195 bool tegra_usb_phy_is_remotewake_detected(struct tegra_usb_phy *phy)
3196 {
3197 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
3198         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
3199         void __iomem *base = phy->regs;
3200         unsigned  int inst = phy->instance;
3201         u32 val;
3202
3203         val = readl(base + UTMIP_PMC_WAKEUP0);
3204         if (val & EVENT_INT_ENB) {
3205                 val = readl(pmc_base + UTMIP_UHSIC_STATUS);
3206                 if (UTMIP_WAKE_ALARM(inst) & val) {
3207                         val = readl(pmc_base + PMC_SLEEP_CFG);
3208                         val &= ~UTMIP_WAKE_VAL(inst, 0x0);
3209                         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
3210                         writel(val, pmc_base + PMC_SLEEP_CFG);
3211
3212                         val = readl(pmc_base + PMC_TRIGGERS);
3213                         val |= UTMIP_CLR_WAKE_ALARM(inst) |
3214                                 UTMIP_CLR_WALK_PTR(inst);
3215                         writel(val, pmc_base + PMC_TRIGGERS);
3216
3217                         val = readl(base + UTMIP_PMC_WAKEUP0);
3218                         val &= ~EVENT_INT_ENB;
3219                         writel(val, base + UTMIP_PMC_WAKEUP0);
3220                         phy->remote_wakeup = true;
3221                         return true;
3222                 }
3223         }
3224 #endif
3225         return false;
3226 }
3227