arm: tegra: usb_phy: vddio_hsic power rail control
[linux-2.6.git] / arch / arm / mach-tegra / usb_phy.c
1 /*
2  * arch/arm/mach-tegra/usb_phy.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Copyright (C) 2010 - 2011 NVIDIA Corporation
6  *
7  * Author:
8  *      Erik Gilling <konkers@google.com>
9  *      Benoit Goby <benoit@android.com>
10  *
11  * This software is licensed under the terms of the GNU General Public
12  * License version 2, as published by the Free Software Foundation, and
13  * may be copied, distributed, and modified under those terms.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  */
21
22 #include <linux/resource.h>
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/err.h>
27 #include <linux/platform_device.h>
28 #include <linux/io.h>
29 #include <linux/gpio.h>
30 #include <linux/usb/otg.h>
31 #include <linux/usb/ulpi.h>
32 #include <asm/mach-types.h>
33 #include <mach/usb_phy.h>
34 #include <mach/iomap.h>
35 #include <mach/pinmux.h>
36
37 #include "fuse.h"
38
39 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
40 #define USB_USBCMD              0x140
41 #define   USB_USBCMD_RS         (1 << 0)
42
43 #define USB_USBSTS              0x144
44 #define   USB_USBSTS_PCI        (1 << 2)
45 #define   USB_USBSTS_HCH        (1 << 12)
46
47 #define USB_TXFILLTUNING        0x164
48 #define USB_FIFO_TXFILL_THRES(x)   (((x) & 0x1f) << 16)
49 #define USB_FIFO_TXFILL_MASK    0x1f0000
50
51 #define ULPI_VIEWPORT           0x170
52 #define   ULPI_WAKEUP           (1 << 31)
53 #define   ULPI_RUN              (1 << 30)
54 #define   ULPI_RD_WR            (1 << 29)
55
56 #define USB_PORTSC1             0x184
57 #define   USB_PORTSC1_PTS(x)    (((x) & 0x3) << 30)
58 #define   USB_PORTSC1_PSPD(x)   (((x) & 0x3) << 26)
59 #define   USB_PORTSC1_PHCD      (1 << 23)
60 #define   USB_PORTSC1_WKOC      (1 << 22)
61 #define   USB_PORTSC1_WKDS      (1 << 21)
62 #define   USB_PORTSC1_WKCN      (1 << 20)
63 #define   USB_PORTSC1_PTC(x)    (((x) & 0xf) << 16)
64 #define   USB_PORTSC1_PP        (1 << 12)
65 #define   USB_PORTSC1_LS(x)     (((x) & 0x3) << 10)
66 #define   USB_PORTSC1_SUSP      (1 << 7)
67 #define   USB_PORTSC1_PE        (1 << 2)
68 #define   USB_PORTSC1_CCS       (1 << 0)
69
70 #define USB_SUSP_CTRL           0x400
71 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
72 #define   USB_WAKE_ON_DISCON_EN_DEV     (1 << 4)
73 #define   USB_SUSP_CLR          (1 << 5)
74 #define   USB_CLKEN             (1 << 6)
75 #define   USB_PHY_CLK_VALID     (1 << 7)
76 #define   USB_PHY_CLK_VALID_INT_ENB    (1 << 9)
77 #define   UTMIP_RESET           (1 << 11)
78 #define   UHSIC_RESET           (1 << 11)
79 #define   UTMIP_PHY_ENABLE      (1 << 12)
80 #define   UHSIC_PHY_ENABLE      (1 << 12)
81 #define   ULPI_PHY_ENABLE       (1 << 13)
82 #define   USB_SUSP_SET          (1 << 14)
83 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
84
85 #define USB1_LEGACY_CTRL        0x410
86 #define   USB1_NO_LEGACY_MODE                   (1 << 0)
87 #define   USB1_VBUS_SENSE_CTL_MASK              (3 << 1)
88 #define   USB1_VBUS_SENSE_CTL_VBUS_WAKEUP       (0 << 1)
89 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
90                                                 (1 << 1)
91 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD       (2 << 1)
92 #define   USB1_VBUS_SENSE_CTL_A_SESS_VLD        (3 << 1)
93
94
95 #define UTMIP_PLL_CFG1          0x804
96 #define   UTMIP_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
97 #define   UTMIP_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 27)
98
99 #define UTMIP_XCVR_CFG0         0x808
100 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
101 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
102 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
103 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
104 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
105 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
106 #define   UTMIP_XCVR_LSBIAS_SEL                 (1 << 21)
107 #define   UTMIP_XCVR_HSSLEW_MSB(x)              (((x) & 0x7f) << 25)
108
109 #define UTMIP_BIAS_CFG0         0x80c
110 #define   UTMIP_OTGPD                   (1 << 11)
111 #define   UTMIP_BIASPD                  (1 << 10)
112
113 #define UTMIP_HSRX_CFG0         0x810
114 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
115 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
116
117 #define UTMIP_HSRX_CFG1         0x814
118 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
119
120 #define UTMIP_TX_CFG0           0x820
121 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
122 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
123
124 #define UTMIP_MISC_CFG0         0x824
125 #define   UTMIP_DPDM_OBSERVE            (1 << 26)
126 #define   UTMIP_DPDM_OBSERVE_SEL(x)     (((x) & 0xf) << 27)
127 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J   UTMIP_DPDM_OBSERVE_SEL(0xf)
128 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K   UTMIP_DPDM_OBSERVE_SEL(0xe)
129 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
130 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
131 #define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
132
133 #define UTMIP_MISC_CFG1         0x828
134 #define   UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18)
135 #define   UTMIP_PLLU_STABLE_COUNT(x)    (((x) & 0xfff) << 6)
136
137 #define UTMIP_DEBOUNCE_CFG0     0x82c
138 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
139
140 #define UTMIP_BAT_CHRG_CFG0     0x830
141 #define   UTMIP_PD_CHRG                 (1 << 0)
142
143 #define UTMIP_XCVR_CFG1         0x838
144 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
145 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
146 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
147 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
148
149 #define UTMIP_BIAS_CFG1         0x83c
150 #define   UTMIP_BIAS_PDTRK_COUNT(x)     (((x) & 0x1f) << 3)
151
152 #define UHSIC_PLL_CFG1                          0x804
153 #define   UHSIC_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
154 #define   UHSIC_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 14)
155
156 #define UHSIC_HSRX_CFG0                         0x808
157 #define   UHSIC_ELASTIC_UNDERRUN_LIMIT(x)       (((x) & 0x1f) << 2)
158 #define   UHSIC_ELASTIC_OVERRUN_LIMIT(x)        (((x) & 0x1f) << 8)
159 #define   UHSIC_IDLE_WAIT(x)                    (((x) & 0x1f) << 13)
160
161 #define UHSIC_HSRX_CFG1                         0x80c
162 #define   UHSIC_HS_SYNC_START_DLY(x)            (((x) & 0x1f) << 1)
163
164 #define UHSIC_MISC_CFG0                         0x814
165 #define   UHSIC_SUSPEND_EXIT_ON_EDGE            (1 << 7)
166 #define   UHSIC_DETECT_SHORT_CONNECT            (1 << 8)
167 #define   UHSIC_FORCE_XCVR_MODE                 (1 << 15)
168
169 #define UHSIC_MISC_CFG1                         0X818
170 #define   UHSIC_PLLU_STABLE_COUNT(x)            (((x) & 0xfff) << 2)
171
172 #define UHSIC_PADS_CFG0                         0x81c
173 #define   UHSIC_TX_RTUNEN                       0xf000
174 #define   UHSIC_TX_RTUNE(x)                     (((x) & 0xf) << 12)
175
176 #define UHSIC_PADS_CFG1                         0x820
177 #define   UHSIC_PD_BG                           (1 << 2)
178 #define   UHSIC_PD_TX                           (1 << 3)
179 #define   UHSIC_PD_TRK                          (1 << 4)
180 #define   UHSIC_PD_RX                           (1 << 5)
181 #define   UHSIC_PD_ZI                           (1 << 6)
182 #define   UHSIC_RX_SEL                          (1 << 7)
183 #define   UHSIC_RPD_DATA                        (1 << 9)
184 #define   UHSIC_RPD_STROBE                      (1 << 10)
185 #define   UHSIC_RPU_DATA                        (1 << 11)
186 #define   UHSIC_RPU_STROBE                      (1 << 12)
187
188 #define UHSIC_STAT_CFG0                         0x828
189 #define   UHSIC_CONNECT_DETECT                  (1 << 0)
190
191
192 #else
193
194 #define USB_USBCMD              0x130
195 #define   USB_USBCMD_RS         (1 << 0)
196
197 #define USB_USBSTS              0x134
198 #define   USB_USBSTS_PCI        (1 << 2)
199 #define   USB_USBSTS_HCH        (1 << 12)
200
201 #define ULPI_VIEWPORT           0x160
202
203 #define USB_PORTSC1             0x174
204 #define   USB_PORTSC1_WKOC      (1 << 22)
205 #define   USB_PORTSC1_WKDS      (1 << 21)
206 #define   USB_PORTSC1_WKCN      (1 << 20)
207 #define   USB_PORTSC1_PTC(x)    (((x) & 0xf) << 16)
208 #define   USB_PORTSC1_PP        (1 << 12)
209 #define   USB_PORTSC1_SUSP      (1 << 7)
210 #define   USB_PORTSC1_PE        (1 << 2)
211 #define   USB_PORTSC1_CCS       (1 << 0)
212
213 #define USB_SUSP_CTRL           0x400
214 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
215 #define   USB_WAKE_ON_DISCON_EN_DEV     (1 << 4)
216 #define   USB_SUSP_CLR                  (1 << 5)
217 #define   USB_PHY_CLK_VALID             (1 << 7)
218 #define   USB_PHY_CLK_VALID_INT_ENB    (1 << 9)
219
220
221 #define   UTMIP_RESET                   (1 << 11)
222 #define   UTMIP_PHY_ENABLE              (1 << 12)
223 #define   ULPI_PHY_ENABLE               (1 << 13)
224 #define   UHSIC_RESET                   (1 << 14)
225
226 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
227 #define   UHSIC_PHY_ENABLE              (1 << 19)
228 #define   ULPIS2S_SLV0_RESET            (1 << 20)
229 #define   ULPIS2S_SLV1_RESET            (1 << 21)
230 #define   ULPIS2S_LINE_RESET            (1 << 22)
231 #define   ULPI_PADS_RESET               (1 << 23)
232 #define   ULPI_PADS_CLKEN_RESET         (1 << 24)
233
234 #define USB1_LEGACY_CTRL        0x410
235 #define   USB1_NO_LEGACY_MODE                   (1 << 0)
236 #define   USB1_VBUS_SENSE_CTL_MASK              (3 << 1)
237 #define   USB1_VBUS_SENSE_CTL_VBUS_WAKEUP       (0 << 1)
238 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
239                                                 (1 << 1)
240 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD       (2 << 1)
241 #define   USB1_VBUS_SENSE_CTL_A_SESS_VLD        (3 << 1)
242
243 #define UTMIP_PLL_CFG1          0x804
244 #define   UTMIP_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
245 #define   UTMIP_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 27)
246
247 #define UTMIP_XCVR_CFG0         0x808
248 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
249 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
250 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
251 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
252 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
253 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
254 #define   UTMIP_XCVR_LSBIAS_SEL                 (1 << 21)
255 #define   UTMIP_XCVR_HSSLEW_MSB(x)              (((x) & 0x7f) << 25)
256
257 #define UTMIP_BIAS_CFG0         0x80c
258 #define   UTMIP_OTGPD                   (1 << 11)
259 #define   UTMIP_BIASPD                  (1 << 10)
260 #define   UTMIP_HSSQUELCH_LEVEL(x)      (((x) & 0x2) << 0)
261 #define   UTMIP_HSDISCON_LEVEL(x)       (((x) & 0x2) << 2)
262 #define   UTMIP_HSDISCON_LEVEL_MSB      (1 << 24)
263
264 #define UTMIP_HSRX_CFG0         0x810
265 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
266 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
267
268 #define UTMIP_HSRX_CFG1         0x814
269 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
270
271 #define UTMIP_TX_CFG0           0x820
272 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
273 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
274
275 #define UTMIP_MISC_CFG0         0x824
276 #define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
277
278 #define UTMIP_MISC_CFG1         0x828
279 #define   UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18)
280 #define   UTMIP_PLLU_STABLE_COUNT(x)    (((x) & 0xfff) << 6)
281
282 #define UTMIP_DEBOUNCE_CFG0     0x82c
283 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
284
285 #define UTMIP_BAT_CHRG_CFG0     0x830
286 #define   UTMIP_PD_CHRG                 (1 << 0)
287
288 #define UTMIP_XCVR_CFG1         0x838
289 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
290 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
291 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
292 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
293
294 #define UTMIP_BIAS_CFG1         0x83c
295 #define   UTMIP_BIAS_PDTRK_COUNT(x)     (((x) & 0x1f) << 3)
296
297 #define HOSTPC1_DEVLC           0x1b4
298 #define   HOSTPC1_DEVLC_PHCD            (1 << 22)
299 #define   HOSTPC1_DEVLC_PTS(x)          (((x) & 0x7) << 29)
300 #define   HOSTPC1_DEVLC_PTS_MASK        7
301 #define   HOSTPC1_DEVLC_PTS_HSIC        4
302 #define   HOSTPC1_DEVLC_STS             (1 << 28)
303 #define   HOSTPC1_DEVLC_PSPD(x)         (((x) & 0x3) << 25)
304 #define   HOSTPC1_DEVLC_PSPD_MASK       3
305 #define   HOSTPC1_DEVLC_PSPD_HIGH_SPEED 2
306
307 #define TEGRA_USB_USBMODE_REG_OFFSET    0x1f8
308 #define   TEGRA_USB_USBMODE_HOST                (3 << 0)
309
310 #define TEGRA_PMC_USB_AO                0xf0
311 #define   TEGRA_PMC_USB_AO_VBUS_WAKEUP_PD_P0    (1 << 2)
312 #define   TEGRA_PMC_USB_AO_ID_PD_P0             (1 << 3)
313 #define   TEGRA_PMC_USB_AO_PD_P2                (0xf << 8)
314
315 #define ICUSB_CTRL              0x15c
316
317 #define UHSIC_PLL_CFG1                          0xc04
318 #define   UHSIC_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
319 #define   UHSIC_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 14)
320
321 #define UHSIC_HSRX_CFG0                         0xc08
322 #define   UHSIC_ELASTIC_UNDERRUN_LIMIT(x)       (((x) & 0x1f) << 2)
323 #define   UHSIC_ELASTIC_OVERRUN_LIMIT(x)        (((x) & 0x1f) << 8)
324 #define   UHSIC_IDLE_WAIT(x)                    (((x) & 0x1f) << 13)
325
326 #define UHSIC_HSRX_CFG1                         0xc0c
327 #define   UHSIC_HS_SYNC_START_DLY(x)            (((x) & 0x1f) << 1)
328
329 #define UHSIC_MISC_CFG0                         0xc14
330 #define   UHSIC_SUSPEND_EXIT_ON_EDGE            (1 << 7)
331 #define   UHSIC_DETECT_SHORT_CONNECT            (1 << 8)
332 #define   UHSIC_FORCE_XCVR_MODE                 (1 << 15)
333
334 #define UHSIC_MISC_CFG1                         0xc18
335 #define   UHSIC_PLLU_STABLE_COUNT(x)            (((x) & 0xfff) << 2)
336
337 #define UHSIC_PADS_CFG0                         0xc1c
338 #define   UHSIC_TX_RTUNEN                       0xf000
339 #define   UHSIC_TX_RTUNE(x)                     (((x) & 0xf) << 12)
340
341 #define UHSIC_PADS_CFG1                         0xc20
342 #define   UHSIC_PD_BG                           (1 << 2)
343 #define   UHSIC_PD_TX                           (1 << 3)
344 #define   UHSIC_PD_TRK                          (1 << 4)
345 #define   UHSIC_PD_RX                           (1 << 5)
346 #define   UHSIC_PD_ZI                           (1 << 6)
347 #define   UHSIC_RX_SEL                          (1 << 7)
348 #define   UHSIC_RPD_DATA                        (1 << 9)
349 #define   UHSIC_RPD_STROBE                      (1 << 10)
350 #define   UHSIC_RPU_DATA                        (1 << 11)
351 #define   UHSIC_RPU_STROBE                      (1 << 12)
352
353 #define UHSIC_STAT_CFG0                         0xc28
354 #define   UHSIC_CONNECT_DETECT                  (1 << 0)
355 #endif
356
357 /* Common registers */
358
359 #define ULPIS2S_CTRL            0x418
360 #define   ULPIS2S_ENA                   (1 << 0)
361 #define   ULPIS2S_SUPPORT_DISCONNECT    (1 << 2)
362 #define   ULPIS2S_PLLU_MASTER_BLASTER60 (1 << 3)
363 #define   ULPIS2S_SPARE(x)              (((x) & 0xF) << 8)
364 #define   ULPIS2S_FORCE_ULPI_CLK_OUT    (1 << 12)
365 #define   ULPIS2S_DISCON_DONT_CHECK_SE0 (1 << 13)
366 #define   ULPIS2S_SUPPORT_HS_KEEP_ALIVE (1 << 14)
367 #define   ULPIS2S_DISABLE_STP_PU        (1 << 15)
368 #define   ULPIS2S_SLV0_CLAMP_XMIT       (1 << 16)
369
370
371 #define ULPI_TIMING_CTRL_0      0x424
372 #define   ULPI_CLOCK_OUT_DELAY(x)       ((x) & 0x1F)
373 #define   ULPI_OUTPUT_PINMUX_BYP        (1 << 10)
374 #define   ULPI_CLKOUT_PINMUX_BYP        (1 << 11)
375 #define   ULPI_SHADOW_CLK_LOOPBACK_EN   (1 << 12)
376 #define   ULPI_SHADOW_CLK_SEL           (1 << 13)
377 #define   ULPI_CORE_CLK_SEL             (1 << 14)
378 #define   ULPI_SHADOW_CLK_DELAY(x)      (((x) & 0x1F) << 16)
379 #define   ULPI_LBK_PAD_EN               (1 << 26)
380 #define   ULPI_LBK_PAD_E_INPUT_OR       (1 << 27)
381 #define   ULPI_CLK_OUT_ENA              (1 << 28)
382 #define   ULPI_CLK_PADOUT_ENA           (1 << 29)
383
384 #define ULPI_TIMING_CTRL_1      0x428
385 #define   ULPI_DATA_TRIMMER_LOAD        (1 << 0)
386 #define   ULPI_DATA_TRIMMER_SEL(x)      (((x) & 0x7) << 1)
387 #define   ULPI_STPDIRNXT_TRIMMER_LOAD   (1 << 16)
388 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
389 #define   ULPI_DIR_TRIMMER_LOAD         (1 << 24)
390 #define   ULPI_DIR_TRIMMER_SEL(x)       (((x) & 0x7) << 25)
391
392
393
394 #define UTMIP_SPARE_CFG0        0x834
395 #define   FUSE_SETUP_SEL                (1 << 3)
396
397 #define UHSIC_PLL_CFG0                          0x800
398
399 #define UHSIC_TX_CFG0                           0x810
400 #define   UHSIC_HS_POSTAMBLE_OUTPUT_ENABLE      (1 << 6)
401
402 #define UHSIC_CMD_CFG0                          0x824
403 #define   UHSIC_PRETEND_CONNECT_DETECT          (1 << 5)
404
405 #define UHSIC_SPARE_CFG0                        0x82c
406
407
408
409 static DEFINE_SPINLOCK(utmip_pad_lock);
410 static int utmip_pad_count;
411
412 struct tegra_xtal_freq {
413         int freq;
414         u8 enable_delay;
415         u8 stable_count;
416         u8 active_delay;
417         u16 xtal_freq_count;
418         u16 debounce;
419         u8 pdtrk_count;
420 };
421
422 static const struct tegra_xtal_freq tegra_freq_table[] = {
423         {
424                 .freq = 12000000,
425                 .enable_delay = 0x02,
426                 .stable_count = 0x2F,
427                 .active_delay = 0x04,
428                 .xtal_freq_count = 0x76,
429                 .debounce = 0x7530,
430                 .pdtrk_count = 5,
431         },
432         {
433                 .freq = 13000000,
434                 .enable_delay = 0x02,
435                 .stable_count = 0x33,
436                 .active_delay = 0x05,
437                 .xtal_freq_count = 0x7F,
438                 .debounce = 0x7EF4,
439                 .pdtrk_count = 5,
440         },
441         {
442                 .freq = 19200000,
443                 .enable_delay = 0x03,
444                 .stable_count = 0x4B,
445                 .active_delay = 0x06,
446                 .xtal_freq_count = 0xBB,
447                 .debounce = 0xBB80,
448                 .pdtrk_count = 7,
449         },
450         {
451                 .freq = 26000000,
452                 .enable_delay = 0x04,
453                 .stable_count = 0x66,
454                 .active_delay = 0x09,
455                 .xtal_freq_count = 0xFE,
456                 .debounce = 0xFDE8,
457                 .pdtrk_count = 9,
458         },
459 };
460
461 static const struct tegra_xtal_freq tegra_uhsic_freq_table[] = {
462         {
463                 .freq = 12000000,
464                 .enable_delay = 0x02,
465                 .stable_count = 0x2F,
466                 .active_delay = 0x0,
467                 .xtal_freq_count = 0x1CA,
468         },
469         {
470                 .freq = 13000000,
471                 .enable_delay = 0x02,
472                 .stable_count = 0x33,
473                 .active_delay = 0x0,
474                 .xtal_freq_count = 0x1F0,
475         },
476         {
477                 .freq = 19200000,
478                 .enable_delay = 0x03,
479                 .stable_count = 0x4B,
480                 .active_delay = 0x0,
481                 .xtal_freq_count = 0x2DD,
482         },
483         {
484                 .freq = 26000000,
485                 .enable_delay = 0x04,
486                 .stable_count = 0x66,
487                 .active_delay = 0x0,
488                 .xtal_freq_count = 0x3E0,
489         },
490 };
491
492 static struct tegra_utmip_config utmip_default[] = {
493         [0] = {
494                 .hssync_start_delay = 9,
495                 .idle_wait_delay = 17,
496                 .elastic_limit = 16,
497                 .term_range_adj = 6,
498                 .xcvr_setup = 9,
499                 .xcvr_lsfslew = 2,
500                 .xcvr_lsrslew = 2,
501         },
502         [2] = {
503                 .hssync_start_delay = 9,
504                 .idle_wait_delay = 17,
505                 .elastic_limit = 16,
506                 .term_range_adj = 6,
507                 .xcvr_setup = 9,
508                 .xcvr_lsfslew = 2,
509                 .xcvr_lsrslew = 2,
510         },
511 };
512
513 struct usb_phy_plat_data usb_phy_data[] = {
514         { 0, 0, -1, NULL},
515         { 0, 0, -1, NULL},
516         { 0, 0, -1, NULL},
517 };
518
519 static int utmip_pad_open(struct tegra_usb_phy *phy)
520 {
521         phy->pad_clk = clk_get_sys("utmip-pad", NULL);
522         if (IS_ERR(phy->pad_clk)) {
523                 pr_err("%s: can't get utmip pad clock\n", __func__);
524                 return PTR_ERR(phy->pad_clk);
525         }
526
527         if (phy->instance == 0) {
528                 phy->pad_regs = phy->regs;
529         } else {
530                 phy->pad_regs = ioremap(TEGRA_USB_BASE, TEGRA_USB_SIZE);
531                 if (!phy->pad_regs) {
532                         pr_err("%s: can't remap usb registers\n", __func__);
533                         clk_put(phy->pad_clk);
534                         return -ENOMEM;
535                 }
536         }
537         return 0;
538 }
539
540 static void utmip_pad_close(struct tegra_usb_phy *phy)
541 {
542         if (phy->instance != 0)
543                 iounmap(phy->pad_regs);
544         clk_put(phy->pad_clk);
545 }
546
547 static int utmip_pad_power_on(struct tegra_usb_phy *phy)
548 {
549         unsigned long val, flags;
550         void __iomem *base = phy->pad_regs;
551
552         clk_enable(phy->pad_clk);
553
554         spin_lock_irqsave(&utmip_pad_lock, flags);
555
556         utmip_pad_count++;
557         val = readl(base + UTMIP_BIAS_CFG0);
558         val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
559 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
560         val |= UTMIP_HSSQUELCH_LEVEL(0x2) | UTMIP_HSDISCON_LEVEL(0x2) |
561                 UTMIP_HSDISCON_LEVEL_MSB;
562 #endif
563         writel(val, base + UTMIP_BIAS_CFG0);
564
565         spin_unlock_irqrestore(&utmip_pad_lock, flags);
566
567         clk_disable(phy->pad_clk);
568
569         return 0;
570 }
571
572 static int utmip_pad_power_off(struct tegra_usb_phy *phy, bool is_dpd)
573 {
574         unsigned long val, flags;
575         void __iomem *base = phy->pad_regs;
576
577         if (!utmip_pad_count) {
578                 pr_err("%s: utmip pad already powered off\n", __func__);
579                 return -EINVAL;
580         }
581
582         clk_enable(phy->pad_clk);
583
584         spin_lock_irqsave(&utmip_pad_lock, flags);
585
586         if (--utmip_pad_count == 0 && is_dpd) {
587                 val = readl(base + UTMIP_BIAS_CFG0);
588                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
589 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
590                 val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) | UTMIP_HSDISCON_LEVEL(~0) |
591                         UTMIP_HSDISCON_LEVEL_MSB);
592 #endif
593                 writel(val, base + UTMIP_BIAS_CFG0);
594         }
595
596         spin_unlock_irqrestore(&utmip_pad_lock, flags);
597
598         clk_disable(phy->pad_clk);
599
600         return 0;
601 }
602
603 static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result)
604 {
605         unsigned long timeout = 2500;
606         do {
607                 if ((readl(reg) & mask) == result)
608                         return 0;
609                 udelay(1);
610                 timeout--;
611         } while (timeout);
612         return -1;
613 }
614
615 static void utmi_phy_clk_disable(struct tegra_usb_phy *phy)
616 {
617         unsigned long val;
618         void __iomem *base = phy->regs;
619 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
620         if (phy->instance == 0) {
621                 val = readl(base + USB_SUSP_CTRL);
622                 val |= USB_SUSP_SET;
623                 writel(val, base + USB_SUSP_CTRL);
624
625                 udelay(10);
626
627                 val = readl(base + USB_SUSP_CTRL);
628                 val &= ~USB_SUSP_SET;
629                 writel(val, base + USB_SUSP_CTRL);
630         }
631
632         if (phy->instance == 2) {
633                 val = readl(base + USB_PORTSC1);
634                 val |= USB_PORTSC1_PHCD;
635                 writel(val, base + USB_PORTSC1);
636         }
637 #else
638         val = readl(base + HOSTPC1_DEVLC);
639         val |= HOSTPC1_DEVLC_PHCD;
640         writel(val, base + HOSTPC1_DEVLC);
641 #endif
642
643         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0)
644                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
645 }
646
647 static void utmi_phy_clk_enable(struct tegra_usb_phy *phy)
648 {
649         unsigned long val;
650         void __iomem *base = phy->regs;
651
652         if (phy->instance == 0) {
653                 val = readl(base + USB_SUSP_CTRL);
654                 val |= USB_SUSP_CLR;
655                 writel(val, base + USB_SUSP_CTRL);
656
657                 udelay(10);
658
659                 val = readl(base + USB_SUSP_CTRL);
660                 val &= ~USB_SUSP_CLR;
661                 writel(val, base + USB_SUSP_CTRL);
662         }
663
664 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
665         if (phy->instance == 2) {
666                 val = readl(base + USB_PORTSC1);
667                 val &= ~USB_PORTSC1_PHCD;
668                 writel(val, base + USB_PORTSC1);
669         }
670 #endif
671
672         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
673                                                      USB_PHY_CLK_VALID) < 0)
674                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
675 }
676
677 static void vbus_enable(struct tegra_usb_phy *phy)
678 {
679 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
680         int gpio_status;
681         int gpio = usb_phy_data[phy->instance].vbus_gpio;
682
683         if (gpio == -1)
684                 return;
685
686         gpio_status = gpio_request(gpio,"VBUS_USB");
687         if (gpio_status < 0) {
688                 printk("VBUS_USB request GPIO FAILED\n");
689                 WARN_ON(1);
690                 return;
691         }
692         tegra_gpio_enable(gpio);
693         gpio_status = gpio_direction_output(gpio, 1);
694         if (gpio_status < 0) {
695                 printk("VBUS_USB request GPIO DIRECTION FAILED \n");
696                 WARN_ON(1);
697                 return;
698         }
699         gpio_set_value(gpio, 1);
700 #else
701         if (phy->reg_vbus)
702                 regulator_enable(phy->reg_vbus);
703 #endif
704 }
705
706 static void vbus_disable(struct tegra_usb_phy *phy)
707 {
708 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
709         int gpio = usb_phy_data[phy->instance].vbus_gpio;
710
711         if (gpio == -1)
712                 return;
713
714         gpio_set_value(gpio, 0);
715         gpio_free(gpio);
716 #else
717         if (phy->reg_vbus)
718                 regulator_disable(phy->reg_vbus);
719 #endif
720 }
721
722 static int utmi_phy_power_on(struct tegra_usb_phy *phy, bool is_dpd)
723 {
724         unsigned long val;
725         void __iomem *base = phy->regs;
726         struct tegra_utmip_config *config = phy->config;
727
728         val = readl(base + USB_SUSP_CTRL);
729         val |= UTMIP_RESET;
730         writel(val, base + USB_SUSP_CTRL);
731
732 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
733         if (phy->instance == 0) {
734                 val = readl(base + USB1_LEGACY_CTRL);
735                 val |= USB1_NO_LEGACY_MODE;
736                 writel(val, base + USB1_LEGACY_CTRL);
737         }
738 #endif
739
740         val = readl(base + UTMIP_TX_CFG0);
741         val |= UTMIP_FS_PREABMLE_J;
742         writel(val, base + UTMIP_TX_CFG0);
743
744         val = readl(base + UTMIP_HSRX_CFG0);
745         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
746         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
747         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
748         writel(val, base + UTMIP_HSRX_CFG0);
749
750         val = readl(base + UTMIP_HSRX_CFG1);
751         val &= ~UTMIP_HS_SYNC_START_DLY(~0);
752         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
753         writel(val, base + UTMIP_HSRX_CFG1);
754
755         val = readl(base + UTMIP_DEBOUNCE_CFG0);
756         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
757         val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
758         writel(val, base + UTMIP_DEBOUNCE_CFG0);
759
760         val = readl(base + UTMIP_MISC_CFG0);
761         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
762         writel(val, base + UTMIP_MISC_CFG0);
763
764 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
765         val = readl(base + UTMIP_MISC_CFG1);
766         val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) | UTMIP_PLLU_STABLE_COUNT(~0));
767         val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |
768                 UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count);
769         writel(val, base + UTMIP_MISC_CFG1);
770
771         val = readl(base + UTMIP_PLL_CFG1);
772         val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) | UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
773         val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |
774                 UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
775         writel(val, base + UTMIP_PLL_CFG1);
776 #endif
777
778         if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) {
779                 val = readl(base + USB_SUSP_CTRL);
780                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
781                 writel(val, base + USB_SUSP_CTRL);
782         }
783
784         utmip_pad_power_on(phy);
785
786         val = readl(base + UTMIP_XCVR_CFG0);
787         val &= ~(UTMIP_XCVR_LSBIAS_SEL | UTMIP_FORCE_PD_POWERDOWN |
788                  UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN |
789                  UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_LSFSLEW(~0) |
790                  UTMIP_XCVR_LSRSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
791         val |= UTMIP_XCVR_SETUP(config->xcvr_setup);
792         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
793         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
794 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
795         if (phy->instance == 0)
796                 val |= UTMIP_XCVR_HSSLEW_MSB(0x8);
797 #endif
798         writel(val, base + UTMIP_XCVR_CFG0);
799
800         val = readl(base + UTMIP_XCVR_CFG1);
801         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
802                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
803         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
804         writel(val, base + UTMIP_XCVR_CFG1);
805
806         val = readl(base + UTMIP_BAT_CHRG_CFG0);
807         if (phy->mode == TEGRA_USB_PHY_MODE_HOST)
808                 val |= UTMIP_PD_CHRG;
809         else
810                 val &= ~UTMIP_PD_CHRG;
811         writel(val, base + UTMIP_BAT_CHRG_CFG0);
812
813         val = readl(base + UTMIP_BIAS_CFG1);
814         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
815         val |= UTMIP_BIAS_PDTRK_COUNT(phy->freq->pdtrk_count);
816         writel(val, base + UTMIP_BIAS_CFG1);
817
818         if (phy->instance == 0) {
819                 val = readl(base + UTMIP_SPARE_CFG0);
820                 if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE)
821                         val &= ~FUSE_SETUP_SEL;
822                 else
823                         val |= FUSE_SETUP_SEL;
824                 writel(val, base + UTMIP_SPARE_CFG0);
825         }
826 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
827         if (phy->instance == 2) {
828                 val = readl(base + UTMIP_SPARE_CFG0);
829                 val |= FUSE_SETUP_SEL;
830                 writel(val, base + UTMIP_SPARE_CFG0);
831
832                 val = readl(base + USB_SUSP_CTRL);
833                 val |= UTMIP_PHY_ENABLE;
834                 writel(val, base + USB_SUSP_CTRL);
835         }
836 #else
837         val = readl(base + USB_SUSP_CTRL);
838         val |= UTMIP_PHY_ENABLE;
839         writel(val, base + USB_SUSP_CTRL);
840 #endif
841
842         val = readl(base + USB_SUSP_CTRL);
843         val &= ~UTMIP_RESET;
844         writel(val, base + USB_SUSP_CTRL);
845
846         if (phy->instance == 0) {
847                 val = readl(base + USB1_LEGACY_CTRL);
848                 val &= ~USB1_VBUS_SENSE_CTL_MASK;
849                 val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD;
850                 writel(val, base + USB1_LEGACY_CTRL);
851
852 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
853                 val = readl(base + USB_SUSP_CTRL);
854                 val &= ~USB_SUSP_SET;
855                 writel(val, base + USB_SUSP_CTRL);
856 #endif
857         }
858
859         utmi_phy_clk_enable(phy);
860 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
861         if (phy->instance == 2) {
862                 val = readl(base + USB_PORTSC1);
863                 val &= ~USB_PORTSC1_PTS(~0);
864                 writel(val, base + USB_PORTSC1);
865         }
866 #else
867         if(phy->instance == 2) {
868                 writel(0, base + ICUSB_CTRL);
869
870                 val = readl(base + TEGRA_USB_USBMODE_REG_OFFSET);
871                 writel((val | TEGRA_USB_USBMODE_HOST),
872                         (base + TEGRA_USB_USBMODE_REG_OFFSET));
873         }
874         val = readl(base + HOSTPC1_DEVLC);
875         val &= ~HOSTPC1_DEVLC_PTS(~0);
876         val |= HOSTPC1_DEVLC_STS;
877         writel(val, base + HOSTPC1_DEVLC);
878 #endif
879
880         return 0;
881 }
882
883 static int utmi_phy_power_off(struct tegra_usb_phy *phy, bool is_dpd)
884 {
885         unsigned long val;
886         void __iomem *base = phy->regs;
887
888         if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) {
889                 val = readl(base + USB_SUSP_CTRL);
890                 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
891                 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
892                 writel(val, base + USB_SUSP_CTRL);
893         }
894
895         if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) {
896                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
897                 val |= UTMIP_PD_CHRG;
898                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
899         }
900
901         if (phy->instance != 2) {
902                 val = readl(base + UTMIP_XCVR_CFG0);
903                 val |= (UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
904                          UTMIP_FORCE_PDZI_POWERDOWN);
905                 writel(val, base + UTMIP_XCVR_CFG0);
906         }
907         val = readl(base + UTMIP_XCVR_CFG1);
908         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
909                UTMIP_FORCE_PDDR_POWERDOWN;
910         writel(val, base + UTMIP_XCVR_CFG1);
911
912 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
913         val = readl(base + UTMIP_BIAS_CFG1);
914         val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
915         writel(val, base + UTMIP_BIAS_CFG1);
916 #endif
917
918         if (phy->instance == 2) {
919                 val = readl(base + USB_PORTSC1);
920                 val |= USB_PORTSC1_WKCN;
921                 writel(val, base + USB_PORTSC1);
922         }
923         if (phy->instance != 0) {
924                 val = readl(base + UTMIP_BIAS_CFG0);
925                 val |= UTMIP_OTGPD;
926                 writel(val, base + UTMIP_BIAS_CFG0);
927         }
928
929         utmi_phy_clk_disable(phy);
930
931         if (phy->instance == 2) {
932                 val = readl(base + USB_SUSP_CTRL);
933                 val |= USB_PHY_CLK_VALID_INT_ENB;
934                 writel(val, base + USB_SUSP_CTRL);
935         } else {
936                 val = readl(base + USB_SUSP_CTRL);
937                 val |= UTMIP_RESET;
938                 writel(val, base + USB_SUSP_CTRL);
939         }
940 #ifdef CONFIG_USB_HOTPLUG
941         utmip_pad_power_off(phy, is_dpd);
942 #else
943         utmip_pad_power_off(phy, true);
944 #endif
945         return 0;
946 }
947
948 static int utmi_phy_preresume(struct tegra_usb_phy *phy, bool is_dpd)
949 {
950         unsigned long val;
951         void __iomem *base = phy->regs;
952
953         val = readl(base + UTMIP_TX_CFG0);
954         val |= UTMIP_HS_DISCON_DISABLE;
955         writel(val, base + UTMIP_TX_CFG0);
956
957         return 0;
958 }
959
960 static int utmi_phy_postresume(struct tegra_usb_phy *phy, bool is_dpd)
961 {
962         unsigned long val;
963         void __iomem *base = phy->regs;
964
965         val = readl(base + UTMIP_TX_CFG0);
966         val &= ~UTMIP_HS_DISCON_DISABLE;
967         writel(val, base + UTMIP_TX_CFG0);
968
969         return 0;
970 }
971
972 static int uhsic_phy_postsuspend(struct tegra_usb_phy *phy, bool is_dpd)
973 {
974         struct tegra_uhsic_config *uhsic_config = phy->config;
975
976         if (uhsic_config->postsuspend)
977                 uhsic_config->postsuspend();
978
979         return 0;
980 }
981
982 static int uhsic_phy_postresume(struct tegra_usb_phy *phy, bool is_dpd)
983 {
984 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
985         unsigned long val;
986         void __iomem *base = phy->regs;
987
988         val = readl(base + USB_TXFILLTUNING);
989         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
990                 val = USB_FIFO_TXFILL_THRES(0x10);
991                 writel(val, base + USB_TXFILLTUNING);
992         }
993 #endif
994
995         return 0;
996 }
997
998 static void utmi_phy_restore_start(struct tegra_usb_phy *phy,
999                                    enum tegra_usb_phy_port_speed port_speed)
1000 {
1001 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1002         unsigned long val;
1003         void __iomem *base = phy->regs;
1004
1005         val = readl(base + UTMIP_MISC_CFG0);
1006         val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1007         if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
1008                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
1009         else
1010                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
1011         writel(val, base + UTMIP_MISC_CFG0);
1012         udelay(1);
1013
1014         val = readl(base + UTMIP_MISC_CFG0);
1015         val |= UTMIP_DPDM_OBSERVE;
1016         writel(val, base + UTMIP_MISC_CFG0);
1017         udelay(10);
1018 #endif
1019 }
1020
1021 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
1022 {
1023 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1024         unsigned long val;
1025         void __iomem *base = phy->regs;
1026
1027         val = readl(base + UTMIP_MISC_CFG0);
1028         val &= ~UTMIP_DPDM_OBSERVE;
1029         writel(val, base + UTMIP_MISC_CFG0);
1030         udelay(10);
1031 #endif
1032 }
1033
1034 static void ulpi_set_tristate(bool enable)
1035 {
1036         int tristate = (enable)? TEGRA_TRI_TRISTATE : TEGRA_TRI_NORMAL;
1037
1038 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1039         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAA, tristate);
1040         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAB, tristate);
1041         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UDA, tristate);
1042 #else
1043         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA0, tristate);
1044         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA1, tristate);
1045         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA2, tristate);
1046         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA3, tristate);
1047         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA4, tristate);
1048         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA5, tristate);
1049         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA6, tristate);
1050         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA7, tristate);
1051         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_CLK, tristate);
1052         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR, tristate);
1053         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_STP, tristate);
1054         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_NXT, tristate);
1055 #endif
1056 }
1057
1058 static void ulpi_phy_reset(void __iomem *base)
1059 {
1060         unsigned long val;
1061
1062         val = readl(base + USB_SUSP_CTRL);
1063         val |= UHSIC_RESET;
1064         writel(val, base + USB_SUSP_CTRL);
1065
1066 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1067         val = readl(base + USB_SUSP_CTRL);
1068         val |= UTMIP_RESET;
1069         writel(val, base + USB_SUSP_CTRL);
1070 #endif
1071 }
1072
1073 static void ulpi_set_host(void __iomem *base)
1074 {
1075 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1076         unsigned long val;
1077
1078         val = readl(base + TEGRA_USB_USBMODE_REG_OFFSET);
1079         val |= TEGRA_USB_USBMODE_HOST;
1080         writel(val, base + TEGRA_USB_USBMODE_REG_OFFSET);
1081
1082         val = readl(base + HOSTPC1_DEVLC);
1083         val |= HOSTPC1_DEVLC_PTS(2);
1084         writel(val, base + HOSTPC1_DEVLC);
1085 #endif
1086 }
1087
1088 static void ulpi_set_trimmer(void __iomem *base, u8 data, u8 sdn, u8 dir)
1089 {
1090         unsigned long val;
1091
1092         val = ULPI_DATA_TRIMMER_SEL(data);
1093         val |= ULPI_STPDIRNXT_TRIMMER_SEL(sdn);
1094         val |= ULPI_DIR_TRIMMER_SEL(dir);
1095         writel(val, base + ULPI_TIMING_CTRL_1);
1096         udelay(10);
1097
1098         val |= ULPI_DATA_TRIMMER_LOAD;
1099         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
1100         val |= ULPI_DIR_TRIMMER_LOAD;
1101         writel(val, base + ULPI_TIMING_CTRL_1);
1102 }
1103
1104 static void ulpi_phy_restore_start(struct tegra_usb_phy *phy,
1105                                    enum tegra_usb_phy_port_speed port_speed)
1106 {
1107 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1108         unsigned long val;
1109         void __iomem *base = phy->regs;
1110
1111         /*Tristate ulpi interface before USB controller resume*/
1112         ulpi_set_tristate(true);
1113
1114         val = readl(base + ULPI_TIMING_CTRL_0);
1115         val &= ~ULPI_OUTPUT_PINMUX_BYP;
1116         writel(val, base + ULPI_TIMING_CTRL_0);
1117 #endif
1118 }
1119
1120 static void ulpi_phy_restore_end(struct tegra_usb_phy *phy)
1121 {
1122 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1123         unsigned long val;
1124         void __iomem *base = phy->regs;
1125
1126         val = readl(base + ULPI_TIMING_CTRL_0);
1127         val |= ULPI_OUTPUT_PINMUX_BYP;
1128         writel(val, base + ULPI_TIMING_CTRL_0);
1129
1130         ulpi_set_tristate(false);
1131 #endif
1132 }
1133
1134 static int ulpi_phy_power_on(struct tegra_usb_phy *phy, bool is_dpd)
1135 {
1136         int ret;
1137         unsigned long val;
1138         void __iomem *base = phy->regs;
1139 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1140         struct tegra_ulpi_config *config = phy->config;
1141 #endif
1142
1143         if (phy->clk)
1144                 clk_enable(phy->clk);
1145
1146         msleep(1);
1147
1148         if (!phy->initialized) {
1149                 phy->initialized = 1;
1150 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1151                 gpio_direction_output(config->reset_gpio, 0);
1152                 msleep(5);
1153                 gpio_direction_output(config->reset_gpio, 1);
1154 #endif
1155         }
1156
1157         ulpi_phy_reset(base);
1158         ulpi_set_host(base);
1159
1160         val = readl(base + ULPI_TIMING_CTRL_0);
1161         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
1162         writel(val, base + ULPI_TIMING_CTRL_0);
1163
1164         val = readl(base + USB_SUSP_CTRL);
1165         val |= ULPI_PHY_ENABLE;
1166         writel(val, base + USB_SUSP_CTRL);
1167
1168         val = readl(base + USB_SUSP_CTRL);
1169         val |= USB_SUSP_CLR;
1170         writel(val, base + USB_SUSP_CTRL);
1171
1172 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1173         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
1174                                                      USB_PHY_CLK_VALID) < 0)
1175                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
1176
1177         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_CLKEN, USB_CLKEN) < 0)
1178                 pr_err("%s: timeout waiting for AHB clock\n", __func__);
1179 #else
1180         udelay(100);
1181 #endif
1182
1183         val = readl(base + USB_SUSP_CTRL);
1184         val &= ~USB_SUSP_CLR;
1185         writel(val, base + USB_SUSP_CTRL);
1186
1187         val = 0;
1188         writel(val, base + ULPI_TIMING_CTRL_1);
1189
1190         ulpi_set_trimmer(base, 4, 4, 4);
1191
1192         /* Fix VbusInvalid due to floating VBUS */
1193         ret = otg_io_write(phy->ulpi, 0x40, 0x08);
1194         if (ret) {
1195                 pr_err("%s: ulpi write failed\n", __func__);
1196                 return ret;
1197         }
1198
1199         ret = otg_io_write(phy->ulpi, 0x80, 0x0B);
1200         if (ret) {
1201                 pr_err("%s: ulpi write failed\n", __func__);
1202                 return ret;
1203         }
1204
1205         val = readl(base + USB_PORTSC1);
1206         val |= USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN;
1207         writel(val, base + USB_PORTSC1);
1208
1209         return 0;
1210 }
1211
1212 static int ulpi_phy_power_off(struct tegra_usb_phy *phy, bool is_dpd)
1213 {
1214         unsigned long val;
1215         void __iomem *base = phy->regs;
1216 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1217         int ret;
1218
1219         /* Disable VbusValid, SessEnd comparators */
1220         ret = otg_io_write(phy->ulpi, 0x00, 0x0D);
1221         if (ret)
1222                 pr_err("%s: ulpi write 0x0D failed\n", __func__);
1223
1224         ret = otg_io_write(phy->ulpi, 0x00, 0x10);
1225         if (ret)
1226                 pr_err("%s: ulpi write 0x10 failed\n", __func__);
1227
1228         /* Disable IdFloat comparator */
1229         ret = otg_io_write(phy->ulpi, 0x00, 0x19);
1230         if (ret)
1231                 pr_err("%s: ulpi write 0x19 failed\n", __func__);
1232
1233         ret = otg_io_write(phy->ulpi, 0x00, 0x1D);
1234         if (ret)
1235                 pr_err("%s: ulpi write 0x1D failed\n", __func__);
1236
1237         /* Clear WKCN/WKDS/WKOC wake-on events that can cause the USB
1238          * Controller to immediately bring the ULPI PHY out of low power
1239          */
1240         val = readl(base + USB_PORTSC1);
1241         val &= ~(USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN);
1242         writel(val, base + USB_PORTSC1);
1243
1244         /* Put the PHY in the low power mode */
1245         val = readl(base + USB_PORTSC1);
1246         val |= USB_PORTSC1_PHCD;
1247         writel(val, base + USB_PORTSC1);
1248
1249         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0)
1250                 pr_err("%s: timeout waiting for phy to stop\n", __func__);
1251 #else
1252         val = readl(base + HOSTPC1_DEVLC);
1253         val &= ~(HOSTPC1_DEVLC_PHCD);
1254         writel(val, base + HOSTPC1_DEVLC);
1255 #endif
1256
1257         if(phy->clk)
1258                 clk_disable(phy->clk);
1259
1260         return 0;
1261 }
1262
1263 static int null_phy_power_on(struct tegra_usb_phy *phy, bool is_dpd)
1264 {
1265         const struct tegra_ulpi_trimmer default_trimmer = {0, 0, 4, 4};
1266         unsigned long val;
1267         void __iomem *base = phy->regs;
1268         struct tegra_ulpi_config *config = phy->config;
1269
1270         if (!config->trimmer)
1271                 config->trimmer = &default_trimmer;
1272
1273         ulpi_phy_reset(base);
1274
1275         val = readl(base + ULPI_TIMING_CTRL_0);
1276         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
1277         writel(val, base + ULPI_TIMING_CTRL_0);
1278
1279         ulpi_set_host(base);
1280
1281         if (config->pre_phy_on && config->pre_phy_on())
1282                 return -EAGAIN;
1283
1284         val = readl(base + USB_SUSP_CTRL);
1285         val |= ULPI_PHY_ENABLE;
1286         writel(val, base + USB_SUSP_CTRL);
1287         udelay(10);
1288
1289         /* set timming parameters */
1290         val = readl(base + ULPI_TIMING_CTRL_0);
1291         val |= ULPI_SHADOW_CLK_LOOPBACK_EN;
1292         val |= ULPI_SHADOW_CLK_SEL;
1293         val &= ~ULPI_LBK_PAD_EN;
1294         val |= ULPI_SHADOW_CLK_DELAY(config->trimmer->shadow_clk_delay);
1295         val |= ULPI_CLOCK_OUT_DELAY(config->trimmer->clock_out_delay);
1296         val |= ULPI_LBK_PAD_E_INPUT_OR;
1297         writel(val, base + ULPI_TIMING_CTRL_0);
1298
1299         writel(0, base + ULPI_TIMING_CTRL_1);
1300         udelay(10);
1301
1302         /* start internal 60MHz clock */
1303         val = ULPIS2S_PLLU_MASTER_BLASTER60;
1304         writel(val, base + ULPIS2S_CTRL);
1305
1306         /* select ULPI_CORE_CLK_SEL to SHADOW_CLK */
1307         val = readl(base + ULPI_TIMING_CTRL_0);
1308         val |= ULPI_CORE_CLK_SEL;
1309         writel(val, base + ULPI_TIMING_CTRL_0);
1310         udelay(10);
1311
1312 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1313         /* remove slave0 reset */
1314         val = readl(base + USB_SUSP_CTRL);
1315         val &= ~ULPIS2S_SLV0_RESET;
1316         writel(val, base + USB_SUSP_CTRL);
1317         udelay(10);
1318 #endif
1319         /* enable ULPI null phy clock - can't set the trimmers before this */
1320         val = readl(base + ULPI_TIMING_CTRL_0);
1321         val |= ULPI_CLK_OUT_ENA;
1322         writel(val, base + ULPI_TIMING_CTRL_0);
1323         udelay(10);
1324
1325         /* set trimmers */
1326         ulpi_set_trimmer(base, config->trimmer->data_trimmer,
1327                          config->trimmer->stpdirnxt_trimmer, 1);
1328
1329 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1330         /* remove various ULPIS2S resets */
1331         val = readl(base + USB_SUSP_CTRL);
1332         val &= ~ULPIS2S_LINE_RESET;
1333         val &= ~ULPIS2S_SLV1_RESET;
1334         val &= ~ULPI_PADS_RESET;
1335         val &= ~ULPI_PADS_CLKEN_RESET;
1336         writel(val, base + USB_SUSP_CTRL);
1337 #endif
1338
1339         val = readl(base + ULPIS2S_CTRL);
1340         val |= ULPIS2S_ENA;
1341         val |= ULPIS2S_SUPPORT_DISCONNECT;
1342         val |= ULPIS2S_SPARE((phy->mode == TEGRA_USB_PHY_MODE_HOST)? 3 : 1);
1343         writel(val, base + ULPIS2S_CTRL);
1344
1345 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1346         val = readl(base + USB_SUSP_CTRL);
1347         val |= USB_SUSP_CLR;
1348         writel(val, base + USB_SUSP_CTRL);
1349         udelay(100);
1350         val = readl(base + USB_SUSP_CTRL);
1351         val &= ~USB_SUSP_CLR;
1352         writel(val, base + USB_SUSP_CTRL);
1353 #endif
1354         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
1355                                                      USB_PHY_CLK_VALID)) {
1356                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
1357                 return -ETIMEDOUT;
1358         }
1359
1360         val = readl(base + ULPI_TIMING_CTRL_0);
1361         val |= ULPI_CLK_PADOUT_ENA;
1362         writel(val, base + ULPI_TIMING_CTRL_0);
1363         udelay(10);
1364
1365         if (config->post_phy_on && config->post_phy_on())
1366                 return -EAGAIN;
1367
1368         return 0;
1369 }
1370
1371 static int null_phy_power_off(struct tegra_usb_phy *phy, bool is_dpd)
1372 {
1373         unsigned long val;
1374         void __iomem *base = phy->regs;
1375         struct tegra_ulpi_config *config = phy->config;
1376
1377         if (config->pre_phy_off && config->pre_phy_off())
1378                 return -EAGAIN;
1379
1380         val = readl(base + ULPI_TIMING_CTRL_0);
1381         val &= ~ULPI_CLK_PADOUT_ENA;
1382         writel(val, base + ULPI_TIMING_CTRL_0);
1383
1384         ulpi_set_tristate(true);
1385
1386         if (config->post_phy_off && config->post_phy_off())
1387                 return -EAGAIN;
1388
1389         return 0;
1390 }
1391
1392 static int null_phy_post_usbcmd_reset(struct tegra_usb_phy *phy, bool is_dpd)
1393 {
1394 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1395         unsigned long val;
1396         void __iomem *base = phy->regs;
1397
1398         val = readl(base + ULPIS2S_CTRL);
1399         val |=  ULPIS2S_SLV0_CLAMP_XMIT;
1400         writel(val, base + ULPIS2S_CTRL);
1401
1402         val = readl(base + USB_SUSP_CTRL);
1403         val |= ULPIS2S_SLV0_RESET;
1404         writel(val, base + USB_SUSP_CTRL);
1405         udelay(10);
1406
1407         /* remove slave0 reset */
1408         val = readl(base + USB_SUSP_CTRL);
1409         val &= ~ULPIS2S_SLV0_RESET;
1410         writel(val, base + USB_SUSP_CTRL);
1411         udelay(10);
1412
1413         val = readl(base + ULPIS2S_CTRL);
1414         val &=  ~ULPIS2S_SLV0_CLAMP_XMIT;
1415         writel(val, base + ULPIS2S_CTRL);
1416
1417         ulpi_set_host(base);
1418 #endif
1419         return 0;
1420 }
1421
1422 static int uhsic_phy_power_on(struct tegra_usb_phy *phy, bool is_dpd)
1423 {
1424         unsigned long val;
1425         void __iomem *base = phy->regs;
1426         struct tegra_uhsic_config *uhsic_config = phy->config;
1427
1428         if (uhsic_config->enable_gpio != -1) {
1429                 gpio_set_value_cansleep(uhsic_config->enable_gpio, 1);
1430                 /* keep hsic reset asserted for 1 ms */
1431                 udelay(1000);
1432         }
1433
1434         val = readl(base + UHSIC_PADS_CFG1);
1435         val &= ~(UHSIC_PD_BG | UHSIC_PD_TX | UHSIC_PD_TRK | UHSIC_PD_RX |
1436                         UHSIC_PD_ZI | UHSIC_RPD_DATA | UHSIC_RPD_STROBE);
1437         val |= UHSIC_RX_SEL;
1438         writel(val, base + UHSIC_PADS_CFG1);
1439         udelay(2);
1440
1441         val = readl(base + USB_SUSP_CTRL);
1442         val |= UHSIC_RESET;
1443         writel(val, base + USB_SUSP_CTRL);
1444         udelay(30);
1445
1446         val = readl(base + USB_SUSP_CTRL);
1447         val |= UHSIC_PHY_ENABLE;
1448         writel(val, base + USB_SUSP_CTRL);
1449
1450         val = readl(base + UHSIC_HSRX_CFG0);
1451         val |= UHSIC_IDLE_WAIT(uhsic_config->idle_wait_delay);
1452         val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(uhsic_config->elastic_underrun_limit);
1453         val |= UHSIC_ELASTIC_OVERRUN_LIMIT(uhsic_config->elastic_overrun_limit);
1454         writel(val, base + UHSIC_HSRX_CFG0);
1455
1456         val = readl(base + UHSIC_HSRX_CFG1);
1457         val |= UHSIC_HS_SYNC_START_DLY(uhsic_config->sync_start_delay);
1458         writel(val, base + UHSIC_HSRX_CFG1);
1459
1460         val = readl(base + UHSIC_MISC_CFG0);
1461         val |= UHSIC_SUSPEND_EXIT_ON_EDGE;
1462         writel(val, base + UHSIC_MISC_CFG0);
1463
1464         val = readl(base + UHSIC_MISC_CFG1);
1465         val |= UHSIC_PLLU_STABLE_COUNT(phy->freq->stable_count);
1466         writel(val, base + UHSIC_MISC_CFG1);
1467
1468         val = readl(base + UHSIC_PLL_CFG1);
1469         val |= UHSIC_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
1470         val |= UHSIC_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count);
1471         writel(val, base + UHSIC_PLL_CFG1);
1472
1473         val = readl(base + USB_SUSP_CTRL);
1474         val &= ~(UHSIC_RESET);
1475         writel(val, base + USB_SUSP_CTRL);
1476         udelay(2);
1477
1478 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1479         val = readl(base + USB_PORTSC1);
1480         val &= ~USB_PORTSC1_PTS(~0);
1481         writel(val, base + USB_PORTSC1);
1482
1483         val = readl(base + USB_TXFILLTUNING);
1484         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
1485                 val = USB_FIFO_TXFILL_THRES(0x10);
1486                 writel(val, base + USB_TXFILLTUNING);
1487         }
1488 #endif
1489
1490         val = readl(base + USB_PORTSC1);
1491         val &= ~(USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN);
1492         writel(val, base + USB_PORTSC1);
1493
1494         val = readl(base + UHSIC_PADS_CFG0);
1495         val &= ~(UHSIC_TX_RTUNEN);
1496         /* set Rtune impedance to 40 ohm */
1497         val |= UHSIC_TX_RTUNE(0);
1498         writel(val, base + UHSIC_PADS_CFG0);
1499
1500         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
1501                                                         USB_PHY_CLK_VALID)) {
1502                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
1503                 return -ETIMEDOUT;
1504         }
1505
1506         return 0;
1507 }
1508
1509 static int uhsic_phy_power_off(struct tegra_usb_phy *phy, bool is_dpd)
1510 {
1511         unsigned long val;
1512         void __iomem *base = phy->regs;
1513         struct tegra_uhsic_config *uhsic_config = phy->config;
1514
1515         val = readl(base + UHSIC_PADS_CFG1);
1516         val &= ~UHSIC_RPU_STROBE;
1517         val |= UHSIC_RPD_STROBE;
1518         writel(val, base + UHSIC_PADS_CFG1);
1519
1520         val = readl(base + USB_SUSP_CTRL);
1521         val |= UHSIC_RESET;
1522         writel(val, base + USB_SUSP_CTRL);
1523         udelay(30);
1524
1525         val = readl(base + USB_SUSP_CTRL);
1526         val &= ~UHSIC_PHY_ENABLE;
1527         writel(val, base + USB_SUSP_CTRL);
1528
1529         if (uhsic_config->enable_gpio != -1) {
1530                 gpio_set_value_cansleep(uhsic_config->enable_gpio, 0);
1531                 /* keep hsic reset de-asserted for 1 ms */
1532                 udelay(1000);
1533         }
1534
1535         return 0;
1536 }
1537
1538 #ifdef CONFIG_USB_TEGRA_OTG
1539 extern void tegra_otg_check_vbus_detection(void);
1540 #endif
1541
1542 static irqreturn_t usb_phy_vbus_irq_thr(int irq, void *pdata)
1543 {
1544         struct tegra_usb_phy *phy = pdata;
1545
1546         if (!phy->regulator_on) {
1547                 regulator_enable(phy->reg_vdd);
1548                 phy->regulator_on = 1;
1549                 /*
1550                  * Optimal time to get the regulator turned on
1551                  * before detecting vbus interrupt.
1552                  */
1553                 mdelay(15);
1554         }
1555
1556 #ifdef CONFIG_USB_TEGRA_OTG
1557         tegra_otg_check_vbus_detection();
1558 #endif
1559
1560         return IRQ_HANDLED;
1561 }
1562
1563 struct tegra_usb_phy *tegra_usb_phy_open(int instance, void __iomem *regs,
1564                         void *config, enum tegra_usb_phy_mode phy_mode,
1565                         enum tegra_usb_phy_type usb_phy_type)
1566 {
1567         struct tegra_usb_phy *phy;
1568         struct tegra_ulpi_config *ulpi_config;
1569         struct tegra_ulpi_config *uhsic_config;
1570         unsigned long parent_rate;
1571         int i;
1572         int err;
1573
1574         phy = kzalloc(sizeof(struct tegra_usb_phy), GFP_KERNEL);
1575         if (!phy)
1576                 return ERR_PTR(-ENOMEM);
1577
1578         phy->instance = instance;
1579         phy->regs = regs;
1580         phy->config = config;
1581         phy->mode = phy_mode;
1582         phy->usb_phy_type = usb_phy_type;
1583         phy->initialized = 0;
1584         phy->regulator_on = 0;
1585
1586         if (!phy->config) {
1587                 if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_LINK_ULPI ||
1588                     phy->usb_phy_type == TEGRA_USB_PHY_TYPE_NULL_ULPI) {
1589                         pr_err("%s: ulpi phy configuration missing", __func__);
1590                         err = -EINVAL;
1591                         goto err0;
1592                 } else {
1593                         phy->config = &utmip_default[instance];
1594                 }
1595         }
1596
1597         phy->pll_u = clk_get_sys(NULL, "pll_u");
1598         if (IS_ERR(phy->pll_u)) {
1599                 pr_err("Can't get pll_u clock\n");
1600                 err = PTR_ERR(phy->pll_u);
1601                 goto err0;
1602         }
1603         clk_enable(phy->pll_u);
1604
1605         parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
1606         if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_HSIC) {
1607                 for (i = 0; i < ARRAY_SIZE(tegra_uhsic_freq_table); i++) {
1608                         if (tegra_uhsic_freq_table[i].freq == parent_rate) {
1609                                 phy->freq = &tegra_uhsic_freq_table[i];
1610                                 break;
1611                         }
1612                 }
1613         } else {
1614                 for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) {
1615                         if (tegra_freq_table[i].freq == parent_rate) {
1616                                 phy->freq = &tegra_freq_table[i];
1617                                 break;
1618                         }
1619                 }
1620         }
1621         if (!phy->freq) {
1622                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
1623                 err = -EINVAL;
1624                 goto err1;
1625         }
1626
1627         if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) {
1628                 err = utmip_pad_open(phy);
1629                 if (err < 0)
1630                         goto err1;
1631         } else if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_LINK_ULPI) {
1632                 ulpi_config = config;
1633
1634                 if (ulpi_config->clk) {
1635                         phy->clk = clk_get_sys(NULL, ulpi_config->clk);
1636                         if (IS_ERR(phy->clk)) {
1637                                 pr_err("%s: can't get ulpi clock\n", __func__);
1638                                 err = -ENXIO;
1639                                 goto err1;
1640                         }
1641                 } else {
1642                         /* Some USB ULPI chips are not driven by Tegra clocks or PLL */
1643                         phy->clk = NULL;
1644                 }
1645                 tegra_gpio_enable(ulpi_config->reset_gpio);
1646                 gpio_request(ulpi_config->reset_gpio, "ulpi_phy_reset_b");
1647                 gpio_direction_output(ulpi_config->reset_gpio, 0);
1648                 phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
1649                 phy->ulpi->io_priv = regs + ULPI_VIEWPORT;
1650         }
1651 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1652         else if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_HSIC) {
1653                 uhsic_config = config;
1654                 gpio_request(uhsic_config->enable_gpio,
1655                         "uhsic_enable");
1656                 if (uhsic_config->reset_gpio != -1)
1657                         gpio_request(uhsic_config->reset_gpio,
1658                                 "uhsic_reset");
1659                 /* hsic enable signal deasserted, hsic reset asserted */
1660                 gpio_direction_output(uhsic_config->enable_gpio,
1661                         0 /* deasserted */);
1662                 if (uhsic_config->reset_gpio != -1)
1663                         gpio_direction_output(uhsic_config->reset_gpio,
1664                                 0 /* asserted */);
1665                 tegra_gpio_enable(uhsic_config->enable_gpio);
1666                 if (uhsic_config->reset_gpio != -1)
1667                         tegra_gpio_enable(uhsic_config->reset_gpio);
1668                 /* keep hsic reset asserted for 1 ms */
1669                 udelay(1000);
1670                 /* enable (power on) hsic */
1671                 gpio_set_value_cansleep(uhsic_config->enable_gpio, 1);
1672                 udelay(1000);
1673                 /* deassert reset */
1674                 if (uhsic_config->reset_gpio != -1)
1675                         gpio_set_value_cansleep(uhsic_config->reset_gpio, 1);
1676         }
1677 #endif
1678
1679         phy->reg_vdd = regulator_get(NULL, "avdd_usb");
1680         if (WARN_ON(IS_ERR_OR_NULL(phy->reg_vdd))) {
1681                 pr_err("couldn't get regulator avdd_usb: %ld \n",
1682                          PTR_ERR(phy->reg_vdd));
1683                 err = PTR_ERR(phy->reg_vdd);
1684                 goto err1;
1685         }
1686
1687         if (instance == 0 && usb_phy_data[0].vbus_irq) {
1688                 err = request_threaded_irq(usb_phy_data[0].vbus_irq, NULL, usb_phy_vbus_irq_thr, IRQF_SHARED,
1689                         "usb_phy_vbus", phy);
1690                 if (err) {
1691                         pr_err("Failed to register IRQ\n");
1692                         goto err1;
1693                 }
1694         }
1695
1696 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1697         /* Power-up the VBUS detector for UTMIP PHY */
1698         if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) {
1699                 writel(readl((IO_ADDRESS(TEGRA_PMC_BASE) + TEGRA_PMC_USB_AO)) &
1700                         ~(TEGRA_PMC_USB_AO_VBUS_WAKEUP_PD_P0 | TEGRA_PMC_USB_AO_ID_PD_P0),
1701                         (IO_ADDRESS(TEGRA_PMC_BASE) + TEGRA_PMC_USB_AO));
1702
1703                 if (usb_phy_data[phy->instance].vbus_reg_supply) {
1704                         phy->reg_vbus = regulator_get(NULL, usb_phy_data[phy->instance].vbus_reg_supply);
1705                         if (WARN_ON(IS_ERR_OR_NULL(phy->reg_vbus))) {
1706                                 pr_err("couldn't get regulator vdd_vbus_usb: %ld, instance : %d\n",
1707                                         PTR_ERR(phy->reg_vbus), phy->instance);
1708                                 err = PTR_ERR(phy->reg_vbus);
1709                                 goto err1;
1710                         }
1711                 }
1712         }
1713         if (instance == 2) {
1714                 writel(readl((IO_ADDRESS(TEGRA_PMC_BASE) + TEGRA_PMC_USB_AO)) &
1715                         (TEGRA_PMC_USB_AO_PD_P2),
1716                         (IO_ADDRESS(TEGRA_PMC_BASE) + TEGRA_PMC_USB_AO));
1717         }
1718 #endif
1719         if (((instance == 2) || (instance == 0)) &&
1720                 (phy->mode == TEGRA_USB_PHY_MODE_HOST)) {
1721                         vbus_enable(phy);
1722         }
1723         return phy;
1724
1725 err1:
1726         clk_disable(phy->pll_u);
1727         clk_put(phy->pll_u);
1728 err0:
1729         kfree(phy);
1730         return ERR_PTR(err);
1731 }
1732
1733 int tegra_usb_phy_power_on(struct tegra_usb_phy *phy, bool is_dpd)
1734 {
1735         int ret = 0;
1736
1737         const tegra_phy_fp power_on[] = {
1738                 utmi_phy_power_on,
1739                 ulpi_phy_power_on,
1740                 null_phy_power_on,
1741                 uhsic_phy_power_on,
1742         };
1743
1744         if (phy->reg_vdd && !phy->regulator_on) {
1745                 regulator_enable(phy->reg_vdd);
1746                 phy->regulator_on = 1;
1747         }
1748
1749         if (power_on[phy->usb_phy_type])
1750                 ret = power_on[phy->usb_phy_type](phy, is_dpd);
1751
1752         return ret;
1753 }
1754
1755 void tegra_usb_phy_power_off(struct tegra_usb_phy *phy, bool is_dpd)
1756 {
1757         const tegra_phy_fp power_off[] = {
1758                 utmi_phy_power_off,
1759                 ulpi_phy_power_off,
1760                 null_phy_power_off,
1761                 uhsic_phy_power_off,
1762         };
1763
1764         if (power_off[phy->usb_phy_type])
1765                 power_off[phy->usb_phy_type](phy, is_dpd);
1766
1767         if (phy->reg_vdd && phy->regulator_on && is_dpd) {
1768 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1769                 if (tegra_get_revision() >= TEGRA_REVISION_A03)
1770 #endif
1771                 regulator_disable(phy->reg_vdd);
1772                 phy->regulator_on = 0;
1773         }
1774 }
1775
1776 void tegra_usb_phy_preresume(struct tegra_usb_phy *phy, bool is_dpd)
1777 {
1778         const tegra_phy_fp preresume[] = {
1779                 utmi_phy_preresume,
1780                 NULL,
1781                 NULL,
1782                 NULL,
1783         };
1784
1785         if (preresume[phy->usb_phy_type])
1786                 preresume[phy->usb_phy_type](phy, is_dpd);
1787 }
1788
1789 void tegra_usb_phy_postsuspend(struct tegra_usb_phy *phy, bool is_dpd)
1790
1791 {
1792         const tegra_phy_fp postsuspend[] = {
1793                 NULL,
1794                 NULL,
1795                 NULL,
1796                 uhsic_phy_postsuspend,
1797         };
1798
1799         if (postsuspend[phy->usb_phy_type])
1800                 postsuspend[phy->usb_phy_type](phy, is_dpd);
1801 }
1802
1803 void tegra_usb_phy_postresume(struct tegra_usb_phy *phy, bool is_dpd)
1804 {
1805         const tegra_phy_fp postresume[] = {
1806                 utmi_phy_postresume,
1807                 NULL,
1808                 NULL,
1809                 uhsic_phy_postresume,
1810         };
1811
1812         if (postresume[phy->usb_phy_type])
1813                 postresume[phy->usb_phy_type](phy, is_dpd);
1814 }
1815
1816 void tegra_ehci_post_reset(struct tegra_usb_phy *phy, bool is_dpd)
1817 {
1818         const tegra_phy_fp post_reset[] = {
1819                 NULL,
1820                 NULL,
1821                 null_phy_post_usbcmd_reset,
1822                 NULL,
1823         };
1824
1825         if (post_reset[phy->usb_phy_type])
1826                 post_reset[phy->usb_phy_type](phy, is_dpd);
1827 }
1828
1829 void tegra_ehci_phy_restore_start(struct tegra_usb_phy *phy,
1830                                  enum tegra_usb_phy_port_speed port_speed)
1831 {
1832         if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP)
1833                 utmi_phy_restore_start(phy, port_speed);
1834         else
1835                 ulpi_phy_restore_start(phy, port_speed);
1836 }
1837
1838 void tegra_ehci_phy_restore_end(struct tegra_usb_phy *phy)
1839 {
1840         if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP)
1841                 utmi_phy_restore_end(phy);
1842         else
1843                 ulpi_phy_restore_end(phy);
1844 }
1845
1846 void tegra_usb_phy_clk_disable(struct tegra_usb_phy *phy)
1847 {
1848         if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP)
1849                 utmi_phy_clk_disable(phy);
1850 }
1851
1852 void tegra_usb_phy_clk_enable(struct tegra_usb_phy *phy)
1853 {
1854         if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP)
1855                 utmi_phy_clk_enable(phy);
1856 }
1857
1858 void tegra_usb_phy_close(struct tegra_usb_phy *phy)
1859 {
1860         if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP)
1861                 utmip_pad_close(phy);
1862         else if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_LINK_ULPI && phy->clk)
1863                 clk_put(phy->clk);
1864         if (phy->mode == TEGRA_USB_PHY_MODE_HOST) {
1865                 vbus_disable(phy);
1866         }
1867         clk_disable(phy->pll_u);
1868         clk_put(phy->pll_u);
1869         if (phy->reg_vbus)
1870                 regulator_put(phy->reg_vbus);
1871         if (phy->reg_vdd)
1872                 regulator_put(phy->reg_vdd);
1873         if (phy->instance == 0 && usb_phy_data[0].vbus_irq)
1874                 free_irq(usb_phy_data[0].vbus_irq, phy);
1875         kfree(phy);
1876 }
1877
1878 int tegra_usb_phy_bus_connect(struct tegra_usb_phy *phy)
1879 {
1880         unsigned long val;
1881         void __iomem *base = phy->regs;
1882
1883         if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_HSIC) {
1884 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1885                 /* Change the USB controller PHY type to HSIC */
1886                 val = readl(base + HOSTPC1_DEVLC);
1887                 val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
1888                 val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
1889                 val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
1890                 val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
1891                 writel(val, base + HOSTPC1_DEVLC);
1892 #endif
1893                 val = readl(base + UHSIC_MISC_CFG0);
1894                 val |= UHSIC_DETECT_SHORT_CONNECT;
1895                 writel(val, base + UHSIC_MISC_CFG0);
1896                 udelay(1);
1897
1898                 val = readl(base + UHSIC_MISC_CFG0);
1899                 val |= UHSIC_FORCE_XCVR_MODE;
1900                 writel(val, base + UHSIC_MISC_CFG0);
1901
1902                 val = readl(base + UHSIC_PADS_CFG1);
1903                 val &= ~UHSIC_RPD_STROBE;
1904 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1905                 val |= UHSIC_RPU_STROBE;
1906 #endif
1907                 writel(val, base + UHSIC_PADS_CFG1);
1908
1909                 if (utmi_wait_register(base + UHSIC_STAT_CFG0, UHSIC_CONNECT_DETECT, UHSIC_CONNECT_DETECT) < 0) {
1910                         pr_err("%s: timeout waiting for hsic connect detect\n", __func__);
1911                         return -ETIMEDOUT;
1912                 }
1913
1914 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1915                 if (utmi_wait_register(base + USB_PORTSC1, USB_PORTSC1_LS(2), USB_PORTSC1_LS(2)) < 0) {
1916                         pr_err("%s: timeout waiting for dplus state\n", __func__);
1917                         return -ETIMEDOUT;
1918                 }
1919 #endif
1920         }
1921
1922         return 0;
1923 }
1924
1925 int tegra_usb_phy_bus_reset(struct tegra_usb_phy *phy)
1926 {
1927         unsigned long val;
1928         void __iomem *base = phy->regs;
1929
1930         if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_HSIC) {
1931 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1932                 val = readl(base + USB_PORTSC1);
1933                 val |= USB_PORTSC1_PTC(5);
1934                 writel(val, base + USB_PORTSC1);
1935                 udelay(2);
1936
1937                 val = readl(base + USB_PORTSC1);
1938                 val &= ~USB_PORTSC1_PTC(~0);
1939                 writel(val, base + USB_PORTSC1);
1940                 udelay(2);
1941 #endif
1942
1943 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1944                 if (utmi_wait_register(base + USB_PORTSC1, USB_PORTSC1_LS(0), 0) < 0) {
1945                         pr_err("%s: timeout waiting for SE0\n", __func__);
1946                         return -ETIMEDOUT;
1947                 }
1948 #endif
1949                 if (utmi_wait_register(base + USB_PORTSC1, USB_PORTSC1_CCS, USB_PORTSC1_CCS) < 0) {
1950                         pr_err("%s: timeout waiting for connection status\n", __func__);
1951                         return -ETIMEDOUT;
1952                 }
1953
1954 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1955                 if (utmi_wait_register(base + USB_PORTSC1, USB_PORTSC1_PSPD(2), USB_PORTSC1_PSPD(2)) < 0) {
1956                         pr_err("%s: timeout waiting hsic high speed configuration\n", __func__);
1957                         return -ETIMEDOUT;
1958                 }
1959 #endif
1960                 val = readl(base + USB_USBCMD);
1961                 val &= ~USB_USBCMD_RS;
1962                 writel(val, base + USB_USBCMD);
1963
1964                 if (utmi_wait_register(base + USB_USBSTS, USB_USBSTS_HCH, USB_USBSTS_HCH) < 0) {
1965                         pr_err("%s: timeout waiting for stopping the controller\n", __func__);
1966                         return -ETIMEDOUT;
1967                 }
1968
1969                 val = readl(base + UHSIC_PADS_CFG1);
1970                 val &= ~UHSIC_RPU_STROBE;
1971                 val |= UHSIC_RPD_STROBE;
1972                 writel(val, base + UHSIC_PADS_CFG1);
1973
1974                 mdelay(50);
1975
1976                 val = readl(base + UHSIC_PADS_CFG1);
1977                 val &= ~UHSIC_RPD_STROBE;
1978                 val |= UHSIC_RPU_STROBE;
1979                 writel(val, base + UHSIC_PADS_CFG1);
1980
1981                 val = readl(base + USB_USBCMD);
1982                 val |= USB_USBCMD_RS;
1983                 writel(val, base + USB_USBCMD);
1984
1985                 val = readl(base + UHSIC_PADS_CFG1);
1986                 val &= ~UHSIC_RPU_STROBE;
1987                 writel(val, base + UHSIC_PADS_CFG1);
1988
1989                 if (utmi_wait_register(base + USB_USBCMD, USB_USBCMD_RS, USB_USBCMD_RS) < 0) {
1990                         pr_err("%s: timeout waiting for starting the controller\n", __func__);
1991                         return -ETIMEDOUT;
1992                 }
1993         }
1994
1995         return 0;
1996 }
1997
1998 int tegra_usb_phy_bus_idle(struct tegra_usb_phy *phy)
1999 {
2000         unsigned long val;
2001         void __iomem *base = phy->regs;
2002
2003         if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_HSIC) {
2004                 val = readl(base + UHSIC_MISC_CFG0);
2005                 val |= UHSIC_DETECT_SHORT_CONNECT;
2006                 writel(val, base + UHSIC_MISC_CFG0);
2007                 udelay(1);
2008
2009                 val = readl(base + UHSIC_MISC_CFG0);
2010                 val |= UHSIC_FORCE_XCVR_MODE;
2011                 writel(val, base + UHSIC_MISC_CFG0);
2012
2013                 val = readl(base + UHSIC_PADS_CFG1);
2014                 val &= ~UHSIC_RPD_STROBE;
2015                 val |= UHSIC_RPU_STROBE;
2016                 writel(val, base + UHSIC_PADS_CFG1);
2017         }
2018         return 0;
2019 }
2020
2021 bool tegra_usb_phy_is_device_connected(struct tegra_usb_phy *phy)
2022 {
2023         void __iomem *base = phy->regs;
2024
2025         if (phy->usb_phy_type == TEGRA_USB_PHY_TYPE_HSIC) {
2026                 if (!((readl(base + UHSIC_STAT_CFG0) & UHSIC_CONNECT_DETECT) == UHSIC_CONNECT_DETECT)) {
2027                         pr_err("%s: hsic no device connection\n", __func__);
2028                         return false;
2029                 }
2030 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2031                 if (utmi_wait_register(base + USB_PORTSC1, USB_PORTSC1_LS(2), USB_PORTSC1_LS(2)) < 0) {
2032                         pr_err("%s: timeout waiting for dplus state\n", __func__);
2033                         return false;
2034                 }
2035 #endif
2036         }
2037         return true;
2038 }
2039
2040 int __init tegra_usb_phy_init(struct usb_phy_plat_data *pdata, int size)
2041 {
2042         if (pdata) {
2043                 int i;
2044
2045                 for (i = 0; i < size; i++, pdata++) {
2046                         usb_phy_data[pdata->instance].instance = pdata->instance;
2047                         usb_phy_data[pdata->instance].vbus_irq = pdata->vbus_irq;
2048                         usb_phy_data[pdata->instance].vbus_gpio = pdata->vbus_gpio;
2049                         usb_phy_data[pdata->instance].vbus_reg_supply = pdata->vbus_reg_supply;
2050                 }
2051         }
2052
2053         return 0;
2054 }