ARM: tegra: dvfs: Invalidate CL-DVFS request when disabled
[linux-2.6.git] / arch / arm / mach-tegra / tegra_cl_dvfs.c
1 /*
2  * arch/arm/mach-tegra/tegra_cl_dvfs.c
3  *
4  * Copyright (c) 2012-2013 NVIDIA CORPORATION. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/kernel.h>
20 #include <linux/spinlock.h>
21 #include <linux/delay.h>
22 #include <linux/err.h>
23 #include <linux/io.h>
24 #include <linux/clk.h>
25 #include <linux/interrupt.h>
26 #include <linux/suspend.h>
27 #include <linux/debugfs.h>
28 #include <linux/seq_file.h>
29 #include <linux/uaccess.h>
30 #include <linux/module.h>
31 #include <linux/platform_device.h>
32
33 #include <mach/iomap.h>
34 #include <mach/irqs.h>
35 #include <mach/hardware.h>
36
37 #include "tegra_cl_dvfs.h"
38 #include "clock.h"
39 #include "dvfs.h"
40
41 #define OUT_MASK                        0x3f
42
43 #define CL_DVFS_CTRL                    0x00
44 #define CL_DVFS_CONFIG                  0x04
45 #define CL_DVFS_CONFIG_DIV_MASK         0xff
46
47 #define CL_DVFS_PARAMS                  0x08
48 #define CL_DVFS_PARAMS_CG_SCALE         (0x1 << 24)
49 #define CL_DVFS_PARAMS_FORCE_MODE_SHIFT 22
50 #define CL_DVFS_PARAMS_FORCE_MODE_MASK  (0x3 << CL_DVFS_PARAMS_FORCE_MODE_SHIFT)
51 #define CL_DVFS_PARAMS_CF_PARAM_SHIFT   16
52 #define CL_DVFS_PARAMS_CF_PARAM_MASK    (0x3f << CL_DVFS_PARAMS_CF_PARAM_SHIFT)
53 #define CL_DVFS_PARAMS_CI_PARAM_SHIFT   8
54 #define CL_DVFS_PARAMS_CI_PARAM_MASK    (0x7 << CL_DVFS_PARAMS_CI_PARAM_SHIFT)
55 #define CL_DVFS_PARAMS_CG_PARAM_SHIFT   0
56 #define CL_DVFS_PARAMS_CG_PARAM_MASK    (0xff << CL_DVFS_PARAMS_CG_PARAM_SHIFT)
57
58 #define CL_DVFS_TUNE0                   0x0c
59 #define CL_DVFS_TUNE1                   0x10
60
61 #define CL_DVFS_FREQ_REQ                0x14
62 #define CL_DVFS_FREQ_REQ_FORCE_ENABLE   (0x1 << 28)
63 #define CL_DVFS_FREQ_REQ_FORCE_SHIFT    16
64 #define CL_DVFS_FREQ_REQ_FORCE_MASK     (0xfff << CL_DVFS_FREQ_REQ_FORCE_SHIFT)
65 #define FORCE_MAX                       2047
66 #define FORCE_MIN                       -2048
67 #define CL_DVFS_FREQ_REQ_SCALE_SHIFT    8
68 #define CL_DVFS_FREQ_REQ_SCALE_MASK     (0xff << CL_DVFS_FREQ_REQ_SCALE_SHIFT)
69 #define SCALE_MAX                       256
70 #define CL_DVFS_FREQ_REQ_FREQ_VALID     (0x1 << 7)
71 #define CL_DVFS_FREQ_REQ_FREQ_SHIFT     0
72 #define CL_DVFS_FREQ_REQ_FREQ_MASK      (0x7f << CL_DVFS_FREQ_REQ_FREQ_SHIFT)
73 #define FREQ_MAX                        127
74
75 #define CL_DVFS_SCALE_RAMP              0x18
76
77 #define CL_DVFS_DROOP_CTRL              0x1c
78 #define CL_DVFS_DROOP_CTRL_MIN_FREQ_SHIFT 16
79 #define CL_DVFS_DROOP_CTRL_MIN_FREQ_MASK  \
80                 (0xff << CL_DVFS_DROOP_CTRL_MIN_FREQ_SHIFT)
81 #define CL_DVFS_DROOP_CTRL_CUT_SHIFT    8
82 #define CL_DVFS_DROOP_CTRL_CUT_MASK     (0xf << CL_DVFS_DROOP_CTRL_CUT_SHIFT)
83 #define CL_DVFS_DROOP_CTRL_RAMP_SHIFT   0
84 #define CL_DVFS_DROOP_CTRL_RAMP_MASK    (0xff << CL_DVFS_DROOP_CTRL_RAMP_SHIFT)
85
86 #define CL_DVFS_OUTPUT_CFG              0x20
87 #define CL_DVFS_OUTPUT_CFG_I2C_ENABLE   (0x1 << 30)
88 #define CL_DVFS_OUTPUT_CFG_SAFE_SHIFT   24
89 #define CL_DVFS_OUTPUT_CFG_SAFE_MASK    \
90                 (OUT_MASK << CL_DVFS_OUTPUT_CFG_SAFE_SHIFT)
91 #define CL_DVFS_OUTPUT_CFG_MAX_SHIFT    16
92 #define CL_DVFS_OUTPUT_CFG_MAX_MASK     \
93                 (OUT_MASK << CL_DVFS_OUTPUT_CFG_MAX_SHIFT)
94 #define CL_DVFS_OUTPUT_CFG_MIN_SHIFT    8
95 #define CL_DVFS_OUTPUT_CFG_MIN_MASK     \
96                 (OUT_MASK << CL_DVFS_OUTPUT_CFG_MIN_SHIFT)
97
98 #define CL_DVFS_OUTPUT_FORCE            0x24
99 #define CL_DVFS_MONITOR_CTRL            0x28
100 #define CL_DVFS_MONITOR_CTRL_DISABLE    0
101 #define CL_DVFS_MONITOR_CTRL_FREQ       6
102 #define CL_DVFS_MONITOR_DATA            0x2c
103 #define CL_DVFS_MONITOR_DATA_NEW        (0x1 << 16)
104 #define CL_DVFS_MONITOR_DATA_MASK       0xFFFF
105
106 #define CL_DVFS_I2C_CFG                 0x40
107 #define CL_DVFS_I2C_CFG_ARB_ENABLE      (0x1 << 20)
108 #define CL_DVFS_I2C_CFG_HS_CODE_SHIFT   16
109 #define CL_DVFS_I2C_CFG_HS_CODE_MASK    (0x7 << CL_DVFS_I2C_CFG_HS_CODE_SHIFT)
110 #define CL_DVFS_I2C_CFG_PACKET_ENABLE   (0x1 << 15)
111 #define CL_DVFS_I2C_CFG_SIZE_SHIFT      12
112 #define CL_DVFS_I2C_CFG_SIZE_MASK       (0x7 << CL_DVFS_I2C_CFG_SIZE_SHIFT)
113 #define CL_DVFS_I2C_CFG_SLAVE_ADDR_10   (0x1 << 10)
114 #define CL_DVFS_I2C_CFG_SLAVE_ADDR_SHIFT 0
115 #define CL_DVFS_I2C_CFG_SLAVE_ADDR_MASK \
116                 (0x3ff << CL_DVFS_I2C_CFG_SLAVE_ADDR_SHIFT)
117
118 #define CL_DVFS_I2C_VDD_REG_ADDR        0x44
119 #define CL_DVFS_I2C_STS                 0x48
120 #define CL_DVFS_I2C_STS_I2C_LAST_SHIFT  1
121 #define CL_DVFS_I2C_STS_I2C_REQ_PENDING 0x1
122
123 #define CL_DVFS_INTR_STS                0x5c
124 #define CL_DVFS_INTR_EN                 0x60
125 #define CL_DVFS_INTR_MIN_MASK           0x1
126 #define CL_DVFS_INTR_MAX_MASK           0x2
127
128 #define CL_DVFS_I2C_CLK_DIVISOR         0x16c
129 #define CL_DVFS_I2C_CLK_DIVISOR_MASK    0xffff
130 #define CL_DVFS_I2C_CLK_DIVISOR_FS_SHIFT 16
131 #define CL_DVFS_I2C_CLK_DIVISOR_HS_SHIFT 0
132
133 #define CL_DVFS_OUTPUT_LUT              0x200
134
135 #define CL_DVFS_CALIBR_TIME             40000
136 #define CL_DVFS_OUTPUT_PENDING_TIMEOUT  1000
137 #define CL_DVFS_OUTPUT_RAMP_DELAY       100
138 #define CL_DVFS_TUNE_HIGH_DELAY         2000
139
140 #define CL_DVFS_TUNE_HIGH_MARGIN_MV     20
141
142 #define CL_DVFS_DYNAMIC_OUTPUT_CFG      0
143
144 enum tegra_cl_dvfs_ctrl_mode {
145         TEGRA_CL_DVFS_UNINITIALIZED = 0,
146         TEGRA_CL_DVFS_DISABLED = 1,
147         TEGRA_CL_DVFS_OPEN_LOOP = 2,
148         TEGRA_CL_DVFS_CLOSED_LOOP = 3,
149 };
150
151 enum tegra_cl_dvfs_tune_state {
152         TEGRA_CL_DVFS_TUNE_LOW = 0,
153         TEGRA_CL_DVFS_TUNE_HIGH_REQUEST,
154         TEGRA_CL_DVFS_TUNE_HIGH,
155 };
156
157 struct dfll_rate_req {
158         u8      freq;
159         u8      scale;
160         u8      output;
161         u8      cap;
162         unsigned long rate;
163 };
164
165 struct tegra_cl_dvfs {
166         u32                                     cl_base;
167         struct tegra_cl_dvfs_platform_data      *p_data;
168
169         struct dvfs                     *safe_dvfs;
170         struct thermal_cooling_device   *vmax_cdev;
171         struct thermal_cooling_device   *vmin_cdev;
172         struct work_struct              init_cdev_work;
173
174         struct clk                      *soc_clk;
175         struct clk                      *ref_clk;
176         struct clk                      *i2c_clk;
177         struct clk                      *dfll_clk;
178         unsigned long                   ref_rate;
179         unsigned long                   i2c_rate;
180
181         /* output voltage mapping:
182          * legacy dvfs table index -to- cl_dvfs output LUT index
183          * cl_dvfs output LUT index -to- PMU value/voltage pair ptr
184          */
185         u8                              clk_dvfs_map[MAX_DVFS_FREQS];
186         struct voltage_reg_map          *out_map[MAX_CL_DVFS_VOLTAGES];
187         u8                              num_voltages;
188         u8                              safe_output;
189         u8                              tune_high_out_start;
190         u8                              tune_high_out_min;
191         u8                              minimax_output;
192         u8                              thermal_out_caps[MAX_THERMAL_LIMITS];
193         u8                              thermal_out_floors[MAX_THERMAL_LIMITS];
194         int                             therm_caps_num;
195         int                             therm_floors_num;
196         unsigned long                   dvco_rate_min;
197
198         u8                              lut_min;
199         u8                              lut_max;
200         u8                              force_out_min;
201         int                             therm_cap_idx;
202         int                             therm_floor_idx;
203         struct dfll_rate_req            last_req;
204         enum tegra_cl_dvfs_tune_state   tune_state;
205         enum tegra_cl_dvfs_ctrl_mode    mode;
206
207         struct timer_list               tune_timer;
208         unsigned long                   tune_delay;
209         struct timer_list               calibration_timer;
210         unsigned long                   calibration_delay;
211         ktime_t                         last_calibration;
212         unsigned long                   calibration_range_min;
213         unsigned long                   calibration_range_max;
214 };
215
216 /* Conversion macros (different scales for frequency request, and monitored
217    rate is not a typo) */
218 #define RATE_STEP(cld)                          ((cld)->ref_rate / 2)
219 #define GET_REQUEST_FREQ(rate, ref_rate)        ((rate) / ((ref_rate) / 2))
220 #define GET_REQUEST_RATE(freq, ref_rate)        ((freq) * ((ref_rate) / 2))
221 #define GET_MONITORED_RATE(freq, ref_rate)      ((freq) * ((ref_rate) / 4))
222 #define GET_DROOP_FREQ(rate, ref_rate)          ((rate) / ((ref_rate) / 4))
223 #define ROUND_MIN_RATE(rate, ref_rate)          \
224                 (DIV_ROUND_UP(rate, (ref_rate) / 2) * ((ref_rate) / 2))
225 #define GET_DIV(ref_rate, out_rate, scale)      \
226                 DIV_ROUND_UP((ref_rate), (out_rate) * (scale))
227
228 static const char *mode_name[] = {
229         [TEGRA_CL_DVFS_UNINITIALIZED] = "uninitialized",
230         [TEGRA_CL_DVFS_DISABLED] = "disabled",
231         [TEGRA_CL_DVFS_OPEN_LOOP] = "open_loop",
232         [TEGRA_CL_DVFS_CLOSED_LOOP] = "closed_loop",
233 };
234
235 static inline u32 cl_dvfs_readl(struct tegra_cl_dvfs *cld, u32 offs)
236 {
237         return __raw_readl(cld->cl_base + offs);
238 }
239 static inline void cl_dvfs_writel(struct tegra_cl_dvfs *cld, u32 val, u32 offs)
240 {
241         __raw_writel(val, cld->cl_base + offs);
242 }
243 static inline void cl_dvfs_wmb(struct tegra_cl_dvfs *cld)
244 {
245         wmb();
246         cl_dvfs_readl(cld, CL_DVFS_CTRL);
247 }
248
249 static inline void invalidate_request(struct tegra_cl_dvfs *cld)
250 {
251         u32 val = cl_dvfs_readl(cld, CL_DVFS_FREQ_REQ);
252         val &= ~CL_DVFS_FREQ_REQ_FREQ_VALID;
253         cl_dvfs_writel(cld, val, CL_DVFS_FREQ_REQ);
254         cl_dvfs_wmb(cld);
255 }
256
257 static inline int output_enable(struct tegra_cl_dvfs *cld)
258 {
259         u32 val = cl_dvfs_readl(cld, CL_DVFS_OUTPUT_CFG);
260
261         /* FIXME: PWM output control */
262         val |= CL_DVFS_OUTPUT_CFG_I2C_ENABLE;
263         cl_dvfs_writel(cld, val, CL_DVFS_OUTPUT_CFG);
264         cl_dvfs_wmb(cld);
265         return  0;
266 }
267
268 static noinline int output_flush_disable(struct tegra_cl_dvfs *cld)
269 {
270         int i;
271         u32 sts;
272         u32 val = cl_dvfs_readl(cld, CL_DVFS_OUTPUT_CFG);
273
274         /* Flush transactions in flight, and then disable */
275         for (i = 0; i < CL_DVFS_OUTPUT_PENDING_TIMEOUT / 2; i++) {
276                 sts = cl_dvfs_readl(cld, CL_DVFS_I2C_STS);
277                 udelay(2);
278                 if (!(sts & CL_DVFS_I2C_STS_I2C_REQ_PENDING)) {
279                         sts = cl_dvfs_readl(cld, CL_DVFS_I2C_STS);
280                         if (!(sts & CL_DVFS_I2C_STS_I2C_REQ_PENDING)) {
281                                 val &= ~CL_DVFS_OUTPUT_CFG_I2C_ENABLE;
282                                 cl_dvfs_writel(cld, val, CL_DVFS_OUTPUT_CFG);
283                                 wmb();
284                                 sts = cl_dvfs_readl(cld, CL_DVFS_I2C_STS);
285                                 if (!(sts & CL_DVFS_I2C_STS_I2C_REQ_PENDING))
286                                         return 0; /* no pending rqst */
287
288                                 /* Re-enable, continue wait */
289                                 val |= CL_DVFS_OUTPUT_CFG_I2C_ENABLE;
290                                 cl_dvfs_writel(cld, val, CL_DVFS_OUTPUT_CFG);
291                                 wmb();
292                         }
293                 }
294         }
295
296         /* I2C request is still pending - disable, anyway, but report error */
297         val &= ~CL_DVFS_OUTPUT_CFG_I2C_ENABLE;
298         cl_dvfs_writel(cld, val, CL_DVFS_OUTPUT_CFG);
299         cl_dvfs_wmb(cld);
300         return -ETIMEDOUT;
301 }
302
303 static noinline int output_disable_flush(struct tegra_cl_dvfs *cld)
304 {
305         int i;
306         u32 sts;
307         u32 val = cl_dvfs_readl(cld, CL_DVFS_OUTPUT_CFG);
308
309         /* Disable output interface right away */
310         val &= ~CL_DVFS_OUTPUT_CFG_I2C_ENABLE;
311         cl_dvfs_writel(cld, val, CL_DVFS_OUTPUT_CFG);
312         cl_dvfs_wmb(cld);
313
314         /* Flush possible transaction in flight */
315         for (i = 0; i < CL_DVFS_OUTPUT_PENDING_TIMEOUT / 2; i++) {
316                 sts = cl_dvfs_readl(cld, CL_DVFS_I2C_STS);
317                 udelay(2);
318                 if (!(sts & CL_DVFS_I2C_STS_I2C_REQ_PENDING)) {
319                         sts = cl_dvfs_readl(cld, CL_DVFS_I2C_STS);
320                         if (!(sts & CL_DVFS_I2C_STS_I2C_REQ_PENDING))
321                                 return 0;
322                 }
323         }
324
325         /* I2C request is still pending - report error */
326         return -ETIMEDOUT;
327 }
328
329 static inline int output_disable_ol_prepare(struct tegra_cl_dvfs *cld)
330 {
331         /* FIXME: PWM output control */
332         /*
333          * If cl-dvfs h/w does not require output to be quiet before disable,
334          * s/w can stop I2C communications at any time (including operations
335          * in closed loop mode), and I2C bus integrity is guaranteed even in
336          * case of flush timeout.
337          */
338         if (!(cld->p_data->flags & TEGRA_CL_DVFS_FLAGS_I2C_WAIT_QUIET)) {
339                 int ret = output_disable_flush(cld);
340                 if (ret)
341                         pr_debug("cl_dvfs: I2C pending timeout ol_prepare\n");
342                 return ret;
343         }
344         return 0;
345 }
346
347 static inline int output_disable_post_ol(struct tegra_cl_dvfs *cld)
348 {
349         /* FIXME: PWM output control */
350         /*
351          * If cl-dvfs h/w requires output to be quiet before disable, s/w
352          * should stop I2C communications only after the switch to open loop
353          * mode, and I2C bus integrity is not guaranteed in case of flush
354          * timeout
355         */
356         if (cld->p_data->flags & TEGRA_CL_DVFS_FLAGS_I2C_WAIT_QUIET) {
357                 int ret = output_flush_disable(cld);
358                 if (ret)
359                         pr_err("cl_dvfs: I2C pending timeout post_ol\n");
360                 return ret;
361         }
362         return 0;
363 }
364
365 static inline void set_mode(struct tegra_cl_dvfs *cld,
366                             enum tegra_cl_dvfs_ctrl_mode mode)
367 {
368         cld->mode = mode;
369         cl_dvfs_writel(cld, mode - 1, CL_DVFS_CTRL);
370         cl_dvfs_wmb(cld);
371 }
372
373 static inline u8 get_output_cap(struct tegra_cl_dvfs *cld,
374                                 struct dfll_rate_req *req)
375 {
376         u32 thermal_cap = cld->num_voltages - 1;
377
378         if (cld->therm_cap_idx && (cld->therm_cap_idx <= cld->therm_caps_num))
379                 thermal_cap = cld->thermal_out_caps[cld->therm_cap_idx - 1];
380         if (req && (req->cap < thermal_cap))
381                 return req->cap;
382         return thermal_cap;
383 }
384
385 static inline u8 get_output_min(struct tegra_cl_dvfs *cld)
386 {
387         u32 tune_min, thermal_min;
388
389         tune_min = cld->tune_state == TEGRA_CL_DVFS_TUNE_LOW ?
390                 0 : cld->tune_high_out_min;
391         thermal_min = 0;
392         if (cld->therm_floor_idx < cld->therm_floors_num)
393                 thermal_min = cld->thermal_out_floors[cld->therm_floor_idx];
394
395         return max(tune_min, thermal_min);
396 }
397
398 static inline void _load_lut(struct tegra_cl_dvfs *cld)
399 {
400         int i;
401         u32 val;
402
403         val = cld->out_map[cld->lut_min]->reg_value;
404         for (i = 0; i <= cld->lut_min; i++)
405                 cl_dvfs_writel(cld, val, CL_DVFS_OUTPUT_LUT + i * 4);
406
407         for (; i < cld->lut_max; i++) {
408                 val = cld->out_map[i]->reg_value;
409                 cl_dvfs_writel(cld, val, CL_DVFS_OUTPUT_LUT + i * 4);
410         }
411
412         val = cld->out_map[cld->lut_max]->reg_value;
413         for (; i < cld->num_voltages; i++)
414                 cl_dvfs_writel(cld, val, CL_DVFS_OUTPUT_LUT + i * 4);
415
416         cl_dvfs_wmb(cld);
417 }
418
419 static void cl_dvfs_load_lut(struct tegra_cl_dvfs *cld)
420 {
421         u32 val = cl_dvfs_readl(cld, CL_DVFS_OUTPUT_CFG);
422         bool disable_out_for_load =
423                 !(cld->p_data->flags & TEGRA_CL_DVFS_FLAGS_I2C_WAIT_QUIET) &&
424                 (val & CL_DVFS_OUTPUT_CFG_I2C_ENABLE);
425
426         if (disable_out_for_load) {
427                 val &= ~CL_DVFS_OUTPUT_CFG_I2C_ENABLE;
428                 cl_dvfs_writel(cld, val, CL_DVFS_OUTPUT_CFG);
429                 cl_dvfs_wmb(cld);
430                 udelay(2); /* 2us (big margin) window for disable propafation */
431         }
432
433         _load_lut(cld);
434
435         if (disable_out_for_load) {
436                 val |= CL_DVFS_OUTPUT_CFG_I2C_ENABLE;
437                 cl_dvfs_writel(cld, val, CL_DVFS_OUTPUT_CFG);
438                 cl_dvfs_wmb(cld);
439         }
440 }
441
442 #define set_tune_state(cld, state) \
443         do {                                                            \
444                 cld->tune_state = state;                                \
445                 pr_debug("%s: set tune state %d\n", __func__, state);   \
446         } while (0)
447
448 static inline void tune_low(struct tegra_cl_dvfs *cld)
449 {
450         if (cld->safe_dvfs->dfll_data.tune_trimmers)
451                 cld->safe_dvfs->dfll_data.tune_trimmers(false);
452         cl_dvfs_writel(cld, cld->safe_dvfs->dfll_data.tune0, CL_DVFS_TUNE0);
453         cl_dvfs_wmb(cld);
454 }
455
456 static inline void tune_high(struct tegra_cl_dvfs *cld)
457 {
458         cl_dvfs_writel(cld, cld->safe_dvfs->dfll_data.tune0_high_mv,
459                        CL_DVFS_TUNE0);
460         cl_dvfs_wmb(cld);
461         if (cld->safe_dvfs->dfll_data.tune_trimmers)
462                 cld->safe_dvfs->dfll_data.tune_trimmers(true);
463 }
464
465 static void set_ol_config(struct tegra_cl_dvfs *cld)
466 {
467         u32 val, out_min;
468
469         /* always tune low (safe) in open loop */
470         if (cld->tune_state != TEGRA_CL_DVFS_TUNE_LOW) {
471                 set_tune_state(cld, TEGRA_CL_DVFS_TUNE_LOW);
472                 tune_low(cld);
473
474                 out_min = get_output_min(cld);
475 #if CL_DVFS_DYNAMIC_OUTPUT_CFG
476                 val = cl_dvfs_readl(cld, CL_DVFS_OUTPUT_CFG);
477                 val &= ~CL_DVFS_OUTPUT_CFG_MIN_MASK;
478                 val |= out_min << CL_DVFS_OUTPUT_CFG_MIN_SHIFT;
479                 cl_dvfs_writel(cld, val, CL_DVFS_OUTPUT_CFG);
480 #else
481                 if (cld->lut_min != out_min) {
482                         cld->lut_min = out_min;
483                         cl_dvfs_load_lut(cld);
484                 }
485 #endif
486         }
487
488         /* 1:1 scaling in open loop */
489         val = cl_dvfs_readl(cld, CL_DVFS_FREQ_REQ);
490         val |= (SCALE_MAX - 1) << CL_DVFS_FREQ_REQ_SCALE_SHIFT;
491         val &= ~CL_DVFS_FREQ_REQ_FORCE_ENABLE;
492         cl_dvfs_writel(cld, val, CL_DVFS_FREQ_REQ);
493 }
494
495 static void set_cl_config(struct tegra_cl_dvfs *cld, struct dfll_rate_req *req)
496 {
497 #if CL_DVFS_DYNAMIC_OUTPUT_CFG
498         u32 val;
499 #endif
500         u32 out_max, out_min;
501         u32 out_cap = get_output_cap(cld, req);
502
503         switch (cld->tune_state) {
504         case TEGRA_CL_DVFS_TUNE_LOW:
505                 if (out_cap > cld->tune_high_out_start) {
506                         set_tune_state(cld, TEGRA_CL_DVFS_TUNE_HIGH_REQUEST);
507                         mod_timer(&cld->tune_timer, jiffies + cld->tune_delay);
508                 }
509                 break;
510
511         case TEGRA_CL_DVFS_TUNE_HIGH:
512         case TEGRA_CL_DVFS_TUNE_HIGH_REQUEST:
513                 if (out_cap <= cld->tune_high_out_start) {
514                         set_tune_state(cld, TEGRA_CL_DVFS_TUNE_LOW);
515                         tune_low(cld);
516                 }
517                 break;
518         default:
519                 BUG();
520         }
521
522         out_min = get_output_min(cld);
523         if (out_cap > (out_min + 1))
524                 req->output = out_cap - 1;
525         else
526                 req->output = out_min + 1;
527         if (req->output == cld->safe_output)
528                 req->output++;
529         out_max = max((u8)(req->output + 1), cld->minimax_output);
530         out_max = max((u8)(out_max), cld->force_out_min);
531
532 #if CL_DVFS_DYNAMIC_OUTPUT_CFG
533         val = cl_dvfs_readl(cld, CL_DVFS_OUTPUT_CFG);
534         val &= ~(CL_DVFS_OUTPUT_CFG_MAX_MASK | CL_DVFS_OUTPUT_CFG_MIN_MASK);
535         val |= out_max << CL_DVFS_OUTPUT_CFG_MAX_SHIFT;
536         val |= out_min << CL_DVFS_OUTPUT_CFG_MIN_SHIFT;
537         cl_dvfs_writel(cld, val, CL_DVFS_OUTPUT_CFG);
538 #else
539         if ((cld->lut_min != out_min) || (cld->lut_max != out_max)) {
540                 cld->lut_min = out_min;
541                 cld->lut_max = out_max;
542                 cl_dvfs_load_lut(cld);
543         }
544 #endif
545 }
546
547 static void tune_timer_cb(unsigned long data)
548 {
549         unsigned long flags;
550         u32 val, out_min, out_last;
551         struct tegra_cl_dvfs *cld = (struct tegra_cl_dvfs *)data;
552
553         clk_lock_save(cld->dfll_clk, &flags);
554
555         /* FIXME: PWM output control */
556         if (cld->tune_state == TEGRA_CL_DVFS_TUNE_HIGH_REQUEST) {
557 #if CL_DVFS_DYNAMIC_OUTPUT_CFG
558                 val = cl_dvfs_readl(cld, CL_DVFS_OUTPUT_CFG);
559                 out_min = (val >> CL_DVFS_OUTPUT_CFG_MIN_SHIFT) & OUT_MASK;
560 #else
561                 out_min = cld->lut_min;
562 #endif
563                 val = cl_dvfs_readl(cld, CL_DVFS_I2C_STS);
564                 out_last = (val >> CL_DVFS_I2C_STS_I2C_LAST_SHIFT) & OUT_MASK;
565
566                 if (!(val & CL_DVFS_I2C_STS_I2C_REQ_PENDING) &&
567                     (out_last >= cld->tune_high_out_min)  &&
568                     (out_min >= cld->tune_high_out_min)) {
569                         udelay(CL_DVFS_OUTPUT_RAMP_DELAY);
570                         set_tune_state(cld, TEGRA_CL_DVFS_TUNE_HIGH);
571                         tune_high(cld);
572                 } else {
573                         mod_timer(&cld->tune_timer, jiffies + cld->tune_delay);
574                 }
575         }
576         clk_unlock_restore(cld->dfll_clk, &flags);
577 }
578
579 static inline void calibration_timer_update(struct tegra_cl_dvfs *cld)
580 {
581         if (!cld->calibration_delay)
582                 return;
583         mod_timer(&cld->calibration_timer, jiffies + cld->calibration_delay);
584 }
585
586 static void cl_dvfs_calibrate(struct tegra_cl_dvfs *cld)
587 {
588         u32 val;
589         ktime_t now;
590         unsigned long data;
591         u8 out_min = get_output_min(cld);
592
593         /*
594          *  Enter calibration procedure only if
595          *  - closed loop operations
596          *  - last request engaged clock skipper
597          *  - at least specified time after the last calibration attempt
598          */
599         if ((cld->mode != TEGRA_CL_DVFS_CLOSED_LOOP) ||
600             (cld->last_req.rate > cld->dvco_rate_min))
601                 return;
602
603         now = ktime_get();
604         if (ktime_us_delta(now, cld->last_calibration) < CL_DVFS_CALIBR_TIME)
605                 return;
606         cld->last_calibration = now;
607
608         if (cl_dvfs_readl(cld, CL_DVFS_MONITOR_CTRL) !=
609             CL_DVFS_MONITOR_CTRL_FREQ)
610                 cl_dvfs_writel(cld, CL_DVFS_MONITOR_CTRL_FREQ,
611                                 CL_DVFS_MONITOR_CTRL);
612
613         /* Synchronize with sample period, and get rate measurements */
614         data = cl_dvfs_readl(cld, CL_DVFS_MONITOR_DATA);
615         do {
616                 data = cl_dvfs_readl(cld, CL_DVFS_MONITOR_DATA);
617         } while (!(data & CL_DVFS_MONITOR_DATA_NEW));
618         do {
619                 data = cl_dvfs_readl(cld, CL_DVFS_MONITOR_DATA);
620         } while (!(data & CL_DVFS_MONITOR_DATA_NEW));
621
622         /* Skip calibration if I2C transaction is pending */
623         /* FIXME: PWM output control */
624         val = cl_dvfs_readl(cld, CL_DVFS_I2C_STS);
625         if (val & CL_DVFS_I2C_STS_I2C_REQ_PENDING)
626                 return;
627
628         /* Adjust minimum rate */
629         data &= CL_DVFS_MONITOR_DATA_MASK;
630         data = GET_MONITORED_RATE(data, cld->ref_rate);
631         if ((val > out_min) || (data < (cld->dvco_rate_min - RATE_STEP(cld))))
632                 cld->dvco_rate_min -= RATE_STEP(cld);
633         else if (data > (cld->dvco_rate_min + RATE_STEP(cld)))
634                 cld->dvco_rate_min += RATE_STEP(cld);
635         else
636                 return;
637
638         cld->dvco_rate_min = clamp(cld->dvco_rate_min,
639                         cld->calibration_range_min, cld->calibration_range_max);
640         calibration_timer_update(cld);
641         pr_debug("%s: calibrated dvco_rate_min %lu\n",
642                  __func__, cld->dvco_rate_min);
643 }
644
645 static void calibration_timer_cb(unsigned long data)
646 {
647         unsigned long flags;
648         struct tegra_cl_dvfs *cld = (struct tegra_cl_dvfs *)data;
649
650         pr_debug("%s\n", __func__);
651
652         clk_lock_save(cld->dfll_clk, &flags);
653         cl_dvfs_calibrate(cld);
654         clk_unlock_restore(cld->dfll_clk, &flags);
655 }
656
657 static void set_request(struct tegra_cl_dvfs *cld, struct dfll_rate_req *req)
658 {
659         u32 val, f;
660         int force_val = req->output - cld->safe_output;
661         int coef = 128; /* FIXME: cld->p_data->cfg_param->cg_scale? */;
662
663         /* If going down apply force output floor */
664         val = cl_dvfs_readl(cld, CL_DVFS_FREQ_REQ);
665         f = (val & CL_DVFS_FREQ_REQ_FREQ_MASK) >> CL_DVFS_FREQ_REQ_FREQ_SHIFT;
666         if ((!(val & CL_DVFS_FREQ_REQ_FREQ_VALID) || (f > req->freq)) &&
667             (cld->force_out_min > req->output))
668                 force_val = cld->force_out_min - cld->safe_output;
669
670         force_val = force_val * coef / cld->p_data->cfg_param->cg;
671         force_val = clamp(force_val, FORCE_MIN, FORCE_MAX);
672
673         /*
674          * 1st set new frequency request and force values, then set force enable
675          * bit (if not set already). Use same CL_DVFS_FREQ_REQ register read
676          * (not other cl_dvfs register) plus explicit delay as a fence.
677          */
678         val &= CL_DVFS_FREQ_REQ_FORCE_ENABLE;
679         val |= req->freq << CL_DVFS_FREQ_REQ_FREQ_SHIFT;
680         val |= req->scale << CL_DVFS_FREQ_REQ_SCALE_SHIFT;
681         val |= ((u32)force_val << CL_DVFS_FREQ_REQ_FORCE_SHIFT) &
682                 CL_DVFS_FREQ_REQ_FORCE_MASK;
683         val |= CL_DVFS_FREQ_REQ_FREQ_VALID;
684         cl_dvfs_writel(cld, val, CL_DVFS_FREQ_REQ);
685         wmb();
686         val = cl_dvfs_readl(cld, CL_DVFS_FREQ_REQ);
687
688         if (!(val & CL_DVFS_FREQ_REQ_FORCE_ENABLE)) {
689                 udelay(1);  /* 1us (big margin) window for force value settle */
690                 val |= CL_DVFS_FREQ_REQ_FORCE_ENABLE;
691                 cl_dvfs_writel(cld, val, CL_DVFS_FREQ_REQ);
692                 cl_dvfs_wmb(cld);
693         }
694 }
695
696 static u8 find_mv_out_cap(struct tegra_cl_dvfs *cld, int mv)
697 {
698         u8 cap;
699         int uv;
700
701         for (cap = 0; cap < cld->num_voltages; cap++) {
702                 uv = cld->out_map[cap]->reg_uV;
703                 if (uv >= mv * 1000)
704                         return cap;
705         }
706         return cap - 1; /* maximum possible output */
707 }
708
709 static u8 find_mv_out_floor(struct tegra_cl_dvfs *cld, int mv)
710 {
711         u8 floor;
712         int uv;
713
714         for (floor = 0; floor < cld->num_voltages; floor++) {
715                 uv = cld->out_map[floor]->reg_uV;
716                 if (uv > mv * 1000) {
717                         if (!floor)
718                                 return 0; /* minimum possible output */
719                         break;
720                 }
721         }
722         return floor - 1;
723 }
724
725 static int find_safe_output(
726         struct tegra_cl_dvfs *cld, unsigned long rate, u8 *safe_output)
727 {
728         int i;
729         int n = cld->safe_dvfs->num_freqs;
730         unsigned long *freqs = cld->safe_dvfs->freqs;
731
732         for (i = 0; i < n; i++) {
733                 if (freqs[i] >= rate) {
734                         *safe_output = cld->clk_dvfs_map[i];
735                         return 0;
736                 }
737         }
738         return -EINVAL;
739 }
740
741 static unsigned long find_dvco_rate_min(struct tegra_cl_dvfs *cld, u8 out_min)
742 {
743         int i;
744
745         for (i = 0; i < cld->safe_dvfs->num_freqs; i++) {
746                 if (cld->clk_dvfs_map[i] > out_min)
747                         break;
748         }
749         i = i ? i-1 : 0;
750         return cld->safe_dvfs->freqs[i];
751 }
752
753 static void cl_dvfs_set_dvco_rate_min(struct tegra_cl_dvfs *cld)
754 {
755         unsigned long rate = cld->safe_dvfs->dfll_data.out_rate_min;
756         if (cld->therm_floor_idx < cld->therm_floors_num)
757                 rate = find_dvco_rate_min(
758                         cld, cld->thermal_out_floors[cld->therm_floor_idx]);
759
760         /* round minimum rate to request unit (ref_rate/2) boundary */
761         cld->dvco_rate_min = ROUND_MIN_RATE(rate, cld->ref_rate);
762
763         /* dvco min rate is under-estimated - skewed range up */
764         cld->calibration_range_min = cld->dvco_rate_min - 2 * RATE_STEP(cld);
765         cld->calibration_range_max = cld->dvco_rate_min + 8 * RATE_STEP(cld);
766 }
767
768 static void cl_dvfs_set_force_out_min(struct tegra_cl_dvfs *cld)
769 {
770         u8 force_out_min = 0;
771         int force_mv_min = cld->p_data->pmu_undershoot_gb;
772
773         if (!force_mv_min) {
774                 cld->force_out_min = 0;
775                 return;
776         }
777
778         if (cld->therm_floor_idx < cld->therm_floors_num)
779                 force_out_min = cld->thermal_out_floors[cld->therm_floor_idx];
780         force_mv_min += cld->out_map[force_out_min]->reg_uV / 1000;
781         force_out_min = find_mv_out_cap(cld, force_mv_min);
782         if (force_out_min == cld->safe_output)
783                 force_out_min++;
784         cld->force_out_min = force_out_min;
785 }
786
787 static struct voltage_reg_map *find_vdd_map_entry(
788         struct tegra_cl_dvfs *cld, int mV, bool exact)
789 {
790         int i, reg_mV;
791
792         for (i = 0; i < cld->p_data->vdd_map_size; i++) {
793                 /* round down to 1mV */
794                 reg_mV = cld->p_data->vdd_map[i].reg_uV / 1000;
795                 if (mV <= reg_mV)
796                         break;
797         }
798
799         if (i < cld->p_data->vdd_map_size) {
800                 if (!exact || (mV == reg_mV))
801                         return &cld->p_data->vdd_map[i];
802         }
803         return NULL;
804 }
805
806 static void cl_dvfs_init_maps(struct tegra_cl_dvfs *cld)
807 {
808         int i, j, v, v_max, n;
809         const int *millivolts;
810         struct voltage_reg_map *m;
811
812         BUILD_BUG_ON(MAX_CL_DVFS_VOLTAGES > OUT_MASK + 1);
813
814         n = cld->safe_dvfs->num_freqs;
815         BUG_ON(n >= MAX_CL_DVFS_VOLTAGES);
816
817         millivolts = cld->safe_dvfs->dfll_millivolts;
818         v_max = millivolts[n - 1];
819
820         v = cld->safe_dvfs->dfll_data.min_millivolts;
821         BUG_ON(v > millivolts[0]);
822
823         cld->out_map[0] = find_vdd_map_entry(cld, v, true);
824         BUG_ON(!cld->out_map[0]);
825
826         for (i = 0, j = 1; i < n; i++) {
827                 for (;;) {
828                         v += max(1, (v_max - v) / (MAX_CL_DVFS_VOLTAGES - j));
829                         if (v >= millivolts[i])
830                                 break;
831
832                         m = find_vdd_map_entry(cld, v, false);
833                         BUG_ON(!m);
834                         if (m != cld->out_map[j - 1])
835                                 cld->out_map[j++] = m;
836                 }
837
838                 v = millivolts[i];
839                 m = find_vdd_map_entry(cld, v, true);
840                 BUG_ON(!m);
841                 if (m != cld->out_map[j - 1])
842                         cld->out_map[j++] = m;
843                 cld->clk_dvfs_map[i] = j - 1;
844         }
845         BUG_ON(j > MAX_CL_DVFS_VOLTAGES);
846         cld->num_voltages = j;
847 }
848
849 static void cl_dvfs_init_tuning_thresholds(struct tegra_cl_dvfs *cld)
850 {
851         int mv;
852
853         /*
854          * Convert high tuning voltage threshold into output LUT index, and
855          * add necessary margin.  If voltage threshold is outside operating
856          * range set it at maximum output level to effectively disable tuning
857          * parameters adjustment.
858          */
859         cld->tune_high_out_min = cld->num_voltages - 1;
860         cld->tune_high_out_start = cld->num_voltages - 1;
861         mv = cld->safe_dvfs->dfll_data.tune_high_min_millivolts;
862         if (mv >= cld->safe_dvfs->dfll_data.min_millivolts) {
863                 u8 out_min = find_mv_out_cap(cld, mv);
864                 u8 out_start = find_mv_out_cap(
865                         cld, mv + CL_DVFS_TUNE_HIGH_MARGIN_MV);
866                 out_start = max(out_start, (u8)(out_min + 1));
867                 if ((out_start + 1) < cld->num_voltages) {
868                         cld->tune_high_out_min = out_min;
869                         cld->tune_high_out_start = out_start;
870                         if (cld->minimax_output <= out_start)
871                                 cld->minimax_output = out_start + 1;
872                 }
873         }
874 }
875
876 static void cl_dvfs_init_hot_output_cap(struct tegra_cl_dvfs *cld)
877 {
878         int i;
879         if (!cld->safe_dvfs->dvfs_rail->therm_mv_caps ||
880             !cld->safe_dvfs->dvfs_rail->therm_mv_caps_num)
881                 return;
882
883         if (!cld->safe_dvfs->dvfs_rail->vmax_cdev)
884                 WARN(1, "%s: missing dfll cap cooling device\n",
885                      cld->safe_dvfs->dvfs_rail->reg_id);
886         /*
887          * Convert monotonically decreasing thermal caps at high temperature
888          * into output LUT indexes; make sure there is a room for regulation
889          * below minimum thermal cap.
890          */
891         cld->therm_caps_num = cld->safe_dvfs->dvfs_rail->therm_mv_caps_num;
892         for (i = 0; i < cld->therm_caps_num; i++) {
893                 cld->thermal_out_caps[i] = find_mv_out_floor(
894                         cld, cld->safe_dvfs->dvfs_rail->therm_mv_caps[i]);
895         }
896         BUG_ON(cld->thermal_out_caps[cld->therm_caps_num - 1] <
897                cld->minimax_output);
898 }
899
900 static void cl_dvfs_init_cold_output_floor(struct tegra_cl_dvfs *cld)
901 {
902         int i;
903         if (!cld->safe_dvfs->dvfs_rail->therm_mv_floors ||
904             !cld->safe_dvfs->dvfs_rail->therm_mv_floors_num)
905                 return;
906
907         if (!cld->safe_dvfs->dvfs_rail->vmin_cdev)
908                 WARN(1, "%s: missing dfll floor cooling device\n",
909                      cld->safe_dvfs->dvfs_rail->reg_id);
910         /*
911          * Convert monotonically decreasing thermal floors at low temperature
912          * into output LUT indexes; make sure there is a room for regulation
913          * above maximum thermal floor.
914          */
915         cld->therm_floors_num = cld->safe_dvfs->dvfs_rail->therm_mv_floors_num;
916         for (i = 0; i < cld->therm_floors_num; i++) {
917                 cld->thermal_out_floors[i] = find_mv_out_cap(
918                         cld, cld->safe_dvfs->dvfs_rail->therm_mv_floors[i]);
919         }
920         BUG_ON(cld->thermal_out_floors[0] + 2 >= cld->num_voltages);
921         if (cld->minimax_output <= cld->thermal_out_floors[0])
922                 cld->minimax_output = cld->thermal_out_floors[0] + 1;
923 }
924
925 static void cl_dvfs_init_output_thresholds(struct tegra_cl_dvfs *cld)
926 {
927         cld->minimax_output = 0;
928         cl_dvfs_init_tuning_thresholds(cld);
929         cl_dvfs_init_cold_output_floor(cld);
930
931         /* make sure safe output is safe at any temperature */
932         cld->safe_output = cld->thermal_out_floors[0] ? : 1;
933         if (cld->minimax_output <= cld->safe_output)
934                 cld->minimax_output = cld->safe_output + 1;
935
936         /* init caps after minimax output is determined */
937         cl_dvfs_init_hot_output_cap(cld);
938 }
939
940 static void cl_dvfs_init_pwm_if(struct tegra_cl_dvfs *cld)
941 {
942         /* FIXME: not supported */
943 }
944
945 static void cl_dvfs_init_i2c_if(struct tegra_cl_dvfs *cld)
946 {
947         u32 val, div;
948         struct tegra_cl_dvfs_platform_data *p_data = cld->p_data;
949         bool hs_mode = p_data->u.pmu_i2c.hs_rate;
950
951         /* PMU slave address, vdd register offset, and transfer mode */
952         val = p_data->u.pmu_i2c.slave_addr << CL_DVFS_I2C_CFG_SLAVE_ADDR_SHIFT;
953         if (p_data->u.pmu_i2c.addr_10)
954                 val |= CL_DVFS_I2C_CFG_SLAVE_ADDR_10;
955         if (hs_mode) {
956                 val |= p_data->u.pmu_i2c.hs_master_code <<
957                         CL_DVFS_I2C_CFG_HS_CODE_SHIFT;
958                 val |= CL_DVFS_I2C_CFG_PACKET_ENABLE;
959         }
960         val |= CL_DVFS_I2C_CFG_SIZE_MASK;
961         val |= CL_DVFS_I2C_CFG_ARB_ENABLE;
962         cl_dvfs_writel(cld, val, CL_DVFS_I2C_CFG);
963         cl_dvfs_writel(cld, p_data->u.pmu_i2c.reg, CL_DVFS_I2C_VDD_REG_ADDR);
964
965
966         val = GET_DIV(cld->i2c_rate, p_data->u.pmu_i2c.fs_rate, 8);
967         BUG_ON(!val || (val > CL_DVFS_I2C_CLK_DIVISOR_MASK));
968         val = (val - 1) << CL_DVFS_I2C_CLK_DIVISOR_FS_SHIFT;
969         if (hs_mode) {
970                 div = GET_DIV(cld->i2c_rate, p_data->u.pmu_i2c.hs_rate, 12);
971                 BUG_ON(!div || (div > CL_DVFS_I2C_CLK_DIVISOR_MASK));
972         } else {
973                 div = 2;        /* default hs divisor just in case */
974         }
975         val |= (div - 1) << CL_DVFS_I2C_CLK_DIVISOR_HS_SHIFT;
976         cl_dvfs_writel(cld, val, CL_DVFS_I2C_CLK_DIVISOR);
977         cl_dvfs_wmb(cld);
978 }
979
980 static void cl_dvfs_init_out_if(struct tegra_cl_dvfs *cld)
981 {
982         u32 val, out_min, out_max;
983
984         /*
985          * Disable output, and set safe voltage and output limits;
986          * disable and clear limit interrupts.
987          */
988         cld->tune_state = TEGRA_CL_DVFS_TUNE_LOW;
989         cld->therm_cap_idx = cld->therm_caps_num;
990         cld->therm_floor_idx = 0;
991         cl_dvfs_set_dvco_rate_min(cld);
992         cl_dvfs_set_force_out_min(cld);
993 #if CL_DVFS_DYNAMIC_OUTPUT_CFG
994         out_min = get_output_min(cld);
995         out_max = get_output_cap(cld, NULL);
996         cld->lut_min = 0;
997         cld->lut_max = cld->num_voltages - 1;
998 #else
999         /*
1000          * Allow the entire range of LUT indexes, but limit output voltage in
1001          * LUT mapping (this "indirect" application of limits is used, because
1002          * h/w does not support dynamic change of index limits, but dynamic
1003          * reload of LUT is fine).
1004          */
1005         out_min = 0;
1006         out_max = cld->num_voltages - 1;
1007         cld->lut_min = get_output_min(cld);
1008         cld->lut_max = get_output_cap(cld, NULL);
1009 #endif
1010
1011         val = (cld->safe_output << CL_DVFS_OUTPUT_CFG_SAFE_SHIFT) |
1012                 (out_max << CL_DVFS_OUTPUT_CFG_MAX_SHIFT) |
1013                 (out_min << CL_DVFS_OUTPUT_CFG_MIN_SHIFT);
1014         cl_dvfs_writel(cld, val, CL_DVFS_OUTPUT_CFG);
1015         cl_dvfs_wmb(cld);
1016
1017         cl_dvfs_writel(cld, 0, CL_DVFS_OUTPUT_FORCE);
1018         cl_dvfs_writel(cld, 0, CL_DVFS_INTR_EN);
1019         cl_dvfs_writel(cld, CL_DVFS_INTR_MAX_MASK | CL_DVFS_INTR_MIN_MASK,
1020                        CL_DVFS_INTR_STS);
1021
1022         /* fill in LUT table */
1023         cl_dvfs_load_lut(cld);
1024
1025         /* configure transport */
1026         if (cld->p_data->pmu_if == TEGRA_CL_DVFS_PMU_I2C)
1027                 cl_dvfs_init_i2c_if(cld);
1028         else
1029                 cl_dvfs_init_pwm_if(cld);
1030 }
1031
1032 static void cl_dvfs_init_cntrl_logic(struct tegra_cl_dvfs *cld)
1033 {
1034         u32 val;
1035         struct tegra_cl_dvfs_cfg_param *param = cld->p_data->cfg_param;
1036
1037         /* configure mode, control loop parameters, DFLL tuning */
1038         set_mode(cld, TEGRA_CL_DVFS_DISABLED);
1039
1040         val = GET_DIV(cld->ref_rate, param->sample_rate, 32);
1041         BUG_ON(val > CL_DVFS_CONFIG_DIV_MASK);
1042         cl_dvfs_writel(cld, val, CL_DVFS_CONFIG);
1043
1044         val = (param->force_mode << CL_DVFS_PARAMS_FORCE_MODE_SHIFT) |
1045                 (param->cf << CL_DVFS_PARAMS_CF_PARAM_SHIFT) |
1046                 (param->ci << CL_DVFS_PARAMS_CI_PARAM_SHIFT) |
1047                 ((u8)param->cg << CL_DVFS_PARAMS_CG_PARAM_SHIFT) |
1048                 (param->cg_scale ? CL_DVFS_PARAMS_CG_SCALE : 0);
1049         cl_dvfs_writel(cld, val, CL_DVFS_PARAMS);
1050
1051         if (cld->safe_dvfs->dfll_data.tune_trimmers)
1052                 cld->safe_dvfs->dfll_data.tune_trimmers(false);
1053         cl_dvfs_writel(cld, cld->safe_dvfs->dfll_data.tune0, CL_DVFS_TUNE0);
1054         cl_dvfs_writel(cld, cld->safe_dvfs->dfll_data.tune1, CL_DVFS_TUNE1);
1055
1056         /* configure droop (skipper 1) and scale (skipper 2) */
1057         val = GET_DROOP_FREQ(cld->safe_dvfs->dfll_data.droop_rate_min,
1058                         cld->ref_rate) << CL_DVFS_DROOP_CTRL_MIN_FREQ_SHIFT;
1059         BUG_ON(val > CL_DVFS_DROOP_CTRL_MIN_FREQ_MASK);
1060         val |= (param->droop_cut_value << CL_DVFS_DROOP_CTRL_CUT_SHIFT);
1061         val |= (param->droop_restore_ramp << CL_DVFS_DROOP_CTRL_RAMP_SHIFT);
1062         cl_dvfs_writel(cld, val, CL_DVFS_DROOP_CTRL);
1063
1064         cld->last_req.cap = 0;
1065         cld->last_req.freq = 0;
1066         cld->last_req.output = 0;
1067         cld->last_req.scale = SCALE_MAX - 1;
1068         cl_dvfs_writel(cld, CL_DVFS_FREQ_REQ_SCALE_MASK, CL_DVFS_FREQ_REQ);
1069         cl_dvfs_writel(cld, param->scale_out_ramp, CL_DVFS_SCALE_RAMP);
1070
1071         /* select frequency for monitoring */
1072         cl_dvfs_writel(cld, CL_DVFS_MONITOR_CTRL_FREQ, CL_DVFS_MONITOR_CTRL);
1073         cl_dvfs_wmb(cld);
1074 }
1075
1076 static int cl_dvfs_enable_clocks(struct tegra_cl_dvfs *cld)
1077 {
1078         if (cld->p_data->pmu_if == TEGRA_CL_DVFS_PMU_I2C)
1079                 clk_enable(cld->i2c_clk);
1080
1081         clk_enable(cld->ref_clk);
1082         clk_enable(cld->soc_clk);
1083         return 0;
1084 }
1085
1086 static void cl_dvfs_disable_clocks(struct tegra_cl_dvfs *cld)
1087 {
1088         if (cld->p_data->pmu_if == TEGRA_CL_DVFS_PMU_I2C)
1089                 clk_disable(cld->i2c_clk);
1090
1091         clk_disable(cld->ref_clk);
1092         clk_disable(cld->soc_clk);
1093 }
1094
1095 static int cl_dvfs_init(struct tegra_cl_dvfs *cld)
1096 {
1097         int ret;
1098
1099         /* Enable output inerface clock */
1100         if (cld->p_data->pmu_if == TEGRA_CL_DVFS_PMU_I2C) {
1101                 ret = clk_enable(cld->i2c_clk);
1102                 if (ret) {
1103                         pr_err("%s: Failed to enable %s\n",
1104                                __func__, cld->i2c_clk->name);
1105                         return ret;
1106                 }
1107                 cld->i2c_rate = clk_get_rate(cld->i2c_clk);
1108         } else {
1109                 pr_err("%s: PMU interface is not I2C\n", __func__);
1110                 return -EINVAL;
1111         }
1112
1113         /* Enable module clocks, release control logic reset */
1114         ret = clk_enable(cld->ref_clk);
1115         if (ret) {
1116                 pr_err("%s: Failed to enable %s\n",
1117                        __func__, cld->ref_clk->name);
1118                 return ret;
1119         }
1120         ret = clk_enable(cld->soc_clk);
1121         if (ret) {
1122                 pr_err("%s: Failed to enable %s\n",
1123                        __func__, cld->ref_clk->name);
1124                 return ret;
1125         }
1126         cld->ref_rate = clk_get_rate(cld->ref_clk);
1127         BUG_ON(!cld->ref_rate);
1128
1129         /* init tuning timer */
1130         init_timer(&cld->tune_timer);
1131         cld->tune_timer.function = tune_timer_cb;
1132         cld->tune_timer.data = (unsigned long)cld;
1133         cld->tune_delay = usecs_to_jiffies(CL_DVFS_TUNE_HIGH_DELAY);
1134
1135         /* init calibration timer */
1136         init_timer(&cld->calibration_timer);
1137         cld->calibration_timer.function = calibration_timer_cb;
1138         cld->calibration_timer.data = (unsigned long)cld;
1139         cld->calibration_delay = usecs_to_jiffies(CL_DVFS_CALIBR_TIME);
1140
1141         /* Get ready ouput voltage mapping*/
1142         cl_dvfs_init_maps(cld);
1143
1144         /* Setup output range thresholds */
1145         cl_dvfs_init_output_thresholds(cld);
1146
1147         /* Setup PMU interface */
1148         cl_dvfs_init_out_if(cld);
1149
1150         /* Configure control registers in disabled mode and disable clocks */
1151         cl_dvfs_init_cntrl_logic(cld);
1152         cl_dvfs_disable_clocks(cld);
1153
1154         return 0;
1155 }
1156
1157 /*
1158  * Re-initialize and enable target device clock in open loop mode. Called
1159  * directly from SoC clock resume syscore operation. Closed loop will be
1160  * re-entered in platform syscore ops as well.
1161  */
1162 void tegra_cl_dvfs_resume(struct tegra_cl_dvfs *cld)
1163 {
1164         enum tegra_cl_dvfs_ctrl_mode mode = cld->mode;
1165         struct dfll_rate_req req = cld->last_req;
1166
1167         cl_dvfs_enable_clocks(cld);
1168
1169         /* Setup PMU interface, and configure controls in disabled mode */
1170         cl_dvfs_init_out_if(cld);
1171         cl_dvfs_init_cntrl_logic(cld);
1172
1173         cl_dvfs_disable_clocks(cld);
1174
1175         /* Restore last request and mode */
1176         cld->last_req = req;
1177         if (mode != TEGRA_CL_DVFS_DISABLED) {
1178                 set_mode(cld, TEGRA_CL_DVFS_OPEN_LOOP);
1179                 WARN(mode > TEGRA_CL_DVFS_OPEN_LOOP,
1180                      "DFLL was left locked in suspend\n");
1181         }
1182 }
1183
1184 #ifdef CONFIG_THERMAL
1185 /* cl_dvfs cap cooling device */
1186 static int tegra_cl_dvfs_get_vmax_cdev_max_state(
1187         struct thermal_cooling_device *cdev, unsigned long *max_state)
1188 {
1189         struct tegra_cl_dvfs *cld = (struct tegra_cl_dvfs *)cdev->devdata;
1190         *max_state = cld->therm_caps_num;
1191         return 0;
1192 }
1193
1194 static int tegra_cl_dvfs_get_vmax_cdev_cur_state(
1195         struct thermal_cooling_device *cdev, unsigned long *cur_state)
1196 {
1197         struct tegra_cl_dvfs *cld = (struct tegra_cl_dvfs *)cdev->devdata;
1198         *cur_state = cld->therm_cap_idx;
1199         return 0;
1200 }
1201
1202 static int tegra_cl_dvfs_set_vmax_cdev_state(
1203         struct thermal_cooling_device *cdev, unsigned long cur_state)
1204 {
1205         unsigned long flags;
1206         struct tegra_cl_dvfs *cld = (struct tegra_cl_dvfs *)cdev->devdata;
1207
1208         clk_lock_save(cld->dfll_clk, &flags);
1209
1210         if (cld->therm_cap_idx != cur_state) {
1211                 cld->therm_cap_idx = cur_state;
1212                 if (cld->mode == TEGRA_CL_DVFS_CLOSED_LOOP) {
1213                         tegra_cl_dvfs_request_rate(cld,
1214                                 tegra_cl_dvfs_request_get(cld));
1215                 }
1216         }
1217         clk_unlock_restore(cld->dfll_clk, &flags);
1218         return 0;
1219 }
1220
1221 static struct thermal_cooling_device_ops tegra_cl_dvfs_vmax_cool_ops = {
1222         .get_max_state = tegra_cl_dvfs_get_vmax_cdev_max_state,
1223         .get_cur_state = tegra_cl_dvfs_get_vmax_cdev_cur_state,
1224         .set_cur_state = tegra_cl_dvfs_set_vmax_cdev_state,
1225 };
1226
1227 /* cl_dvfs vmin cooling device */
1228 static int tegra_cl_dvfs_get_vmin_cdev_max_state(
1229         struct thermal_cooling_device *cdev, unsigned long *max_state)
1230 {
1231         struct tegra_cl_dvfs *cld = (struct tegra_cl_dvfs *)cdev->devdata;
1232         *max_state = cld->therm_floors_num;
1233         return 0;
1234 }
1235
1236 static int tegra_cl_dvfs_get_vmin_cdev_cur_state(
1237         struct thermal_cooling_device *cdev, unsigned long *cur_state)
1238 {
1239         struct tegra_cl_dvfs *cld = (struct tegra_cl_dvfs *)cdev->devdata;
1240         *cur_state = cld->therm_floor_idx;
1241         return 0;
1242 }
1243
1244 static int tegra_cl_dvfs_set_vmin_cdev_state(
1245         struct thermal_cooling_device *cdev, unsigned long cur_state)
1246 {
1247         unsigned long flags;
1248         struct tegra_cl_dvfs *cld = (struct tegra_cl_dvfs *)cdev->devdata;
1249
1250         clk_lock_save(cld->dfll_clk, &flags);
1251
1252         if (cld->therm_floor_idx != cur_state) {
1253                 cld->therm_floor_idx = cur_state;
1254                 cl_dvfs_set_dvco_rate_min(cld);
1255                 cl_dvfs_set_force_out_min(cld);
1256                 if (cld->mode == TEGRA_CL_DVFS_CLOSED_LOOP) {
1257                         tegra_cl_dvfs_request_rate(cld,
1258                                 tegra_cl_dvfs_request_get(cld));
1259                 }
1260         }
1261         clk_unlock_restore(cld->dfll_clk, &flags);
1262         return 0;
1263 }
1264
1265 static struct thermal_cooling_device_ops tegra_cl_dvfs_vmin_cool_ops = {
1266         .get_max_state = tegra_cl_dvfs_get_vmin_cdev_max_state,
1267         .get_cur_state = tegra_cl_dvfs_get_vmin_cdev_cur_state,
1268         .set_cur_state = tegra_cl_dvfs_set_vmin_cdev_state,
1269 };
1270
1271 static void tegra_cl_dvfs_init_cdev(struct work_struct *work)
1272 {
1273         struct tegra_cl_dvfs *cld = container_of(
1274                 work, struct tegra_cl_dvfs, init_cdev_work);
1275
1276         /* just report error - initialized at WC temperature, anyway */
1277         if (cld->safe_dvfs->dvfs_rail->vmin_cdev) {
1278                 char *type = cld->safe_dvfs->dvfs_rail->vmin_cdev->cdev_type;
1279                 cld->vmin_cdev = thermal_cooling_device_register(
1280                         type, (void *)cld, &tegra_cl_dvfs_vmin_cool_ops);
1281                 if (IS_ERR_OR_NULL(cld->vmin_cdev)) {
1282                         cld->vmin_cdev = NULL;
1283                         pr_err("tegra cooling device %s failed to register\n",
1284                                type);
1285                         return;
1286                 }
1287                 pr_info("%s cooling device is registered\n", type);
1288         }
1289
1290         if (cld->safe_dvfs->dvfs_rail->vmax_cdev) {
1291                 char *type = cld->safe_dvfs->dvfs_rail->vmax_cdev->cdev_type;
1292                 cld->vmax_cdev = thermal_cooling_device_register(
1293                         type, (void *)cld, &tegra_cl_dvfs_vmax_cool_ops);
1294                 if (IS_ERR_OR_NULL(cld->vmax_cdev)) {
1295                         cld->vmax_cdev = NULL;
1296                         pr_err("tegra cooling device %s failed to register\n",
1297                                type);
1298                         return;
1299                 }
1300                 pr_info("%s cooling device is registered\n", type);
1301         }
1302 }
1303 #endif
1304
1305 #ifdef CONFIG_PM_SLEEP
1306 /*
1307  * cl_dvfs controls clock/voltage to other devices, including CPU. Therefore,
1308  * cl_dvfs driver pm suspend callback does not stop cl-dvfs operations. It is
1309  * only used to enforce cold/hot volatge limit, since temperature may change in
1310  * suspend without waking up. The correct temperature zone after supend will
1311  * be updated via cl_dvfs cooling device interface during resume of temperature
1312  * sensor.
1313  */
1314 static int tegra_cl_dvfs_suspend_cl(struct device *dev)
1315 {
1316         unsigned long flags;
1317         struct tegra_cl_dvfs *cld = dev_get_drvdata(dev);
1318
1319         clk_lock_save(cld->dfll_clk, &flags);
1320         if (cld->vmax_cdev)
1321                 cld->vmax_cdev->updated = false;
1322         cld->therm_cap_idx = cld->therm_caps_num;
1323         if (cld->vmin_cdev)
1324                 cld->vmin_cdev->updated = false;
1325         cld->therm_floor_idx = 0;
1326         cl_dvfs_set_dvco_rate_min(cld);
1327         cl_dvfs_set_force_out_min(cld);
1328         if (cld->mode == TEGRA_CL_DVFS_CLOSED_LOOP) {
1329                 set_cl_config(cld, &cld->last_req);
1330                 set_request(cld, &cld->last_req);
1331         }
1332         clk_unlock_restore(cld->dfll_clk, &flags);
1333
1334         return 0;
1335 }
1336
1337 static const struct dev_pm_ops tegra_cl_dvfs_pm_ops = {
1338         .suspend = tegra_cl_dvfs_suspend_cl,
1339 };
1340 #endif
1341
1342 static int __init tegra_cl_dvfs_probe(struct platform_device *pdev)
1343 {
1344         int ret;
1345         struct tegra_cl_dvfs_platform_data *p_data;
1346         struct resource *res;
1347         struct tegra_cl_dvfs *cld;
1348         struct clk *ref_clk, *soc_clk, *i2c_clk, *safe_dvfs_clk, *dfll_clk;
1349
1350         /* Get resources */
1351         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1352         if (!res) {
1353                 dev_err(&pdev->dev, "missing register base\n");
1354                 return -ENOMEM;
1355         }
1356
1357         p_data = pdev->dev.platform_data;
1358         if (!p_data || !p_data->cfg_param || !p_data->vdd_map) {
1359                 dev_err(&pdev->dev, "missing platform data\n");
1360                 return -ENODATA;
1361         }
1362
1363         ref_clk = clk_get(&pdev->dev, "ref");
1364         soc_clk = clk_get(&pdev->dev, "soc");
1365         i2c_clk = clk_get(&pdev->dev, "i2c");
1366         safe_dvfs_clk = clk_get(&pdev->dev, "safe_dvfs");
1367         dfll_clk = clk_get(&pdev->dev, p_data->dfll_clk_name);
1368         if (IS_ERR(ref_clk) || IS_ERR(soc_clk) || IS_ERR(i2c_clk)) {
1369                 dev_err(&pdev->dev, "missing control clock\n");
1370                 return -ENODEV;
1371         }
1372         if (IS_ERR(safe_dvfs_clk)) {
1373                 dev_err(&pdev->dev, "missing safe dvfs source clock\n");
1374                 return PTR_ERR(safe_dvfs_clk);
1375         }
1376         if (IS_ERR(dfll_clk)) {
1377                 dev_err(&pdev->dev, "missing target dfll clock\n");
1378                 return PTR_ERR(dfll_clk);
1379         }
1380         if (!safe_dvfs_clk->dvfs || !safe_dvfs_clk->dvfs->dvfs_rail) {
1381                 dev_err(&pdev->dev, "invalid safe dvfs source\n");
1382                 return -EINVAL;
1383         }
1384
1385         /* Allocate cl_dvfs object and populate resource accessors */
1386         cld = kzalloc(sizeof(*cld), GFP_KERNEL);
1387         if (!cld) {
1388                 dev_err(&pdev->dev, "failed to allocate cl_dvfs object\n");
1389                 return -ENOMEM;
1390         }
1391
1392         cld->cl_base = (u32)IO_ADDRESS(res->start);
1393         cld->p_data = p_data;
1394         cld->ref_clk = ref_clk;
1395         cld->soc_clk = soc_clk;
1396         cld->i2c_clk = i2c_clk;
1397         cld->dfll_clk = dfll_clk;
1398         cld->safe_dvfs = safe_dvfs_clk->dvfs;
1399 #ifdef CONFIG_THERMAL
1400         INIT_WORK(&cld->init_cdev_work, tegra_cl_dvfs_init_cdev);
1401 #endif
1402         /* Initialize cl_dvfs */
1403         ret = cl_dvfs_init(cld);
1404         if (ret) {
1405                 kfree(cld);
1406                 return ret;
1407         }
1408
1409         platform_set_drvdata(pdev, cld);
1410
1411         /*
1412          * Schedule cooling device registration as a separate work to address
1413          * the following race: when cl_dvfs is probed the DFLL child clock
1414          * (e.g., CPU) cannot be changed; on the other hand cooling device
1415          * registration will update the entire thermal zone, and may trigger
1416          * rate change of the target clock
1417          */
1418         if (cld->safe_dvfs->dvfs_rail->vmin_cdev ||
1419             cld->safe_dvfs->dvfs_rail->vmax_cdev)
1420                 schedule_work(&cld->init_cdev_work);
1421         return 0;
1422 }
1423
1424 static struct platform_driver tegra_cl_dvfs_driver = {
1425         .driver         = {
1426                 .name   = "tegra_cl_dvfs",
1427                 .owner  = THIS_MODULE,
1428 #ifdef CONFIG_PM_SLEEP
1429                 .pm = &tegra_cl_dvfs_pm_ops,
1430 #endif
1431         },
1432 };
1433
1434 int __init tegra_init_cl_dvfs(void)
1435 {
1436         return platform_driver_probe(&tegra_cl_dvfs_driver,
1437                                      tegra_cl_dvfs_probe);
1438 }
1439
1440 /*
1441  * CL_DVFS states:
1442  *
1443  * - DISABLED: control logic mode - DISABLED, output interface disabled,
1444  *   dfll in reset
1445  * - OPEN_LOOP: control logic mode - OPEN_LOOP, output interface disabled,
1446  *   dfll is running "unlocked"
1447  * - CLOSED_LOOP: control logic mode - CLOSED_LOOP, output interface enabled,
1448  *   dfll is running "locked"
1449  */
1450
1451 /* Switch from any other state to DISABLED state */
1452 void tegra_cl_dvfs_disable(struct tegra_cl_dvfs *cld)
1453 {
1454         switch (cld->mode) {
1455         case TEGRA_CL_DVFS_CLOSED_LOOP:
1456                 WARN(1, "DFLL is disabled directly from closed loop mode\n");
1457                 set_ol_config(cld);
1458                 output_disable_ol_prepare(cld);
1459                 set_mode(cld, TEGRA_CL_DVFS_DISABLED);
1460                 output_disable_post_ol(cld);
1461                 invalidate_request(cld);
1462                 cl_dvfs_disable_clocks(cld);
1463                 return;
1464
1465         case TEGRA_CL_DVFS_OPEN_LOOP:
1466                 set_mode(cld, TEGRA_CL_DVFS_DISABLED);
1467                 invalidate_request(cld);
1468                 cl_dvfs_disable_clocks(cld);
1469                 return;
1470
1471         default:
1472                 BUG_ON(cld->mode > TEGRA_CL_DVFS_CLOSED_LOOP);
1473                 return;
1474         }
1475 }
1476
1477 /* Switch from DISABLE state to OPEN_LOOP state */
1478 int tegra_cl_dvfs_enable(struct tegra_cl_dvfs *cld)
1479 {
1480         if (cld->mode == TEGRA_CL_DVFS_UNINITIALIZED) {
1481                 pr_err("%s: Cannot enable DFLL in %s mode\n",
1482                        __func__, mode_name[cld->mode]);
1483                 return -EPERM;
1484         }
1485
1486         if (cld->mode != TEGRA_CL_DVFS_DISABLED)
1487                 return 0;
1488
1489         cl_dvfs_enable_clocks(cld);
1490         set_mode(cld, TEGRA_CL_DVFS_OPEN_LOOP);
1491         return 0;
1492 }
1493
1494 /* Switch from OPEN_LOOP state to CLOSED_LOOP state */
1495 int tegra_cl_dvfs_lock(struct tegra_cl_dvfs *cld)
1496 {
1497         struct dfll_rate_req *req = &cld->last_req;
1498
1499         switch (cld->mode) {
1500         case TEGRA_CL_DVFS_CLOSED_LOOP:
1501                 return 0;
1502
1503         case TEGRA_CL_DVFS_OPEN_LOOP:
1504                 if (req->freq == 0) {
1505                         pr_err("%s: Cannot lock DFLL at rate 0\n", __func__);
1506                         return -EINVAL;
1507                 }
1508
1509                 /*
1510                  * Update control logic setting with last rate request;
1511                  * sync output limits with current tuning and thermal state,
1512                  * enable output and switch to closed loop mode.
1513                  */
1514                 set_cl_config(cld, req);
1515                 output_enable(cld);
1516                 set_mode(cld, TEGRA_CL_DVFS_CLOSED_LOOP);
1517                 set_request(cld, req);
1518                 calibration_timer_update(cld);
1519                 return 0;
1520
1521         default:
1522                 BUG_ON(cld->mode > TEGRA_CL_DVFS_CLOSED_LOOP);
1523                 pr_err("%s: Cannot lock DFLL in %s mode\n",
1524                        __func__, mode_name[cld->mode]);
1525                 return -EPERM;
1526         }
1527 }
1528
1529 /* Switch from CLOSED_LOOP state to OPEN_LOOP state */
1530 int tegra_cl_dvfs_unlock(struct tegra_cl_dvfs *cld)
1531 {
1532         int ret;
1533
1534         switch (cld->mode) {
1535         case TEGRA_CL_DVFS_CLOSED_LOOP:
1536                 set_ol_config(cld);
1537                 ret = output_disable_ol_prepare(cld);
1538                 set_mode(cld, TEGRA_CL_DVFS_OPEN_LOOP);
1539                 if (!ret)
1540                         ret = output_disable_post_ol(cld);
1541                 return ret;
1542
1543         case TEGRA_CL_DVFS_OPEN_LOOP:
1544                 return 0;
1545
1546         default:
1547                 BUG_ON(cld->mode > TEGRA_CL_DVFS_CLOSED_LOOP);
1548                 pr_err("%s: Cannot unlock DFLL in %s mode\n",
1549                        __func__, mode_name[cld->mode]);
1550                 return -EPERM;
1551         }
1552 }
1553
1554 /*
1555  * Convert requested rate into the control logic settings. In CLOSED_LOOP mode,
1556  * update new settings immediately to adjust DFLL output rate accordingly.
1557  * Otherwise, just save them until next switch to closed loop.
1558  */
1559 int tegra_cl_dvfs_request_rate(struct tegra_cl_dvfs *cld, unsigned long rate)
1560 {
1561         u32 val;
1562         struct dfll_rate_req req;
1563         req.rate = rate;
1564
1565         if (cld->mode == TEGRA_CL_DVFS_UNINITIALIZED) {
1566                 pr_err("%s: Cannot set DFLL rate in %s mode\n",
1567                        __func__, mode_name[cld->mode]);
1568                 return -EPERM;
1569         }
1570
1571         /* Calibrate dfll minimum rate */
1572         cl_dvfs_calibrate(cld);
1573
1574         /* Determine DFLL output scale */
1575         req.scale = SCALE_MAX - 1;
1576         if (rate < cld->dvco_rate_min) {
1577                 int scale = DIV_ROUND_CLOSEST((rate / 1000 * SCALE_MAX),
1578                         (cld->dvco_rate_min / 1000));
1579                 if (!scale) {
1580                         pr_err("%s: Rate %lu is below scalable range\n",
1581                                __func__, rate);
1582                         return -EINVAL;
1583                 }
1584                 req.scale = scale - 1;
1585                 rate = cld->dvco_rate_min;
1586         }
1587
1588         /* Convert requested rate into frequency request and scale settings */
1589         val = GET_REQUEST_FREQ(rate, cld->ref_rate);
1590         if (val > FREQ_MAX) {
1591                 pr_err("%s: Rate %lu is above dfll range\n", __func__, rate);
1592                 return -EINVAL;
1593         }
1594         req.freq = val;
1595         rate = GET_REQUEST_RATE(val, cld->ref_rate);
1596
1597         /* Find safe voltage for requested rate */
1598         if (find_safe_output(cld, rate, &req.output)) {
1599                 pr_err("%s: Failed to find safe output for rate %lu\n",
1600                        __func__, rate);
1601                 return -EINVAL;
1602         }
1603         req.cap = req.output;
1604
1605         /*
1606          * Save validated request, and in CLOSED_LOOP mode actually update
1607          * control logic settings; use request output to set maximum voltage
1608          * limit, but keep one LUT step room above safe voltage
1609          */
1610         cld->last_req = req;
1611
1612         if (cld->mode == TEGRA_CL_DVFS_CLOSED_LOOP) {
1613                 set_cl_config(cld, &cld->last_req);
1614                 set_request(cld, &cld->last_req);
1615         }
1616         return 0;
1617 }
1618
1619 unsigned long tegra_cl_dvfs_request_get(struct tegra_cl_dvfs *cld)
1620 {
1621         struct dfll_rate_req *req = &cld->last_req;
1622
1623         /*
1624          * If running below dvco minimum rate with skipper resolution:
1625          * dvco min rate / 256 - return last requested rate rounded to 1kHz.
1626          * If running above dvco minimum, with closed loop resolution:
1627          * ref rate / 2 - return cl_dvfs target rate.
1628          */
1629         if ((req->scale + 1) < SCALE_MAX)
1630                 return req->rate / 1000 * 1000;
1631
1632         return GET_REQUEST_RATE(req->freq, cld->ref_rate);
1633 }
1634
1635 #ifdef CONFIG_DEBUG_FS
1636
1637 static int lock_get(void *data, u64 *val)
1638 {
1639         struct tegra_cl_dvfs *cld = ((struct clk *)data)->u.dfll.cl_dvfs;
1640         *val = cld->mode == TEGRA_CL_DVFS_CLOSED_LOOP;
1641         return 0;
1642 }
1643 static int lock_set(void *data, u64 val)
1644 {
1645         struct clk *c = (struct clk *)data;
1646         return tegra_clk_cfg_ex(c, TEGRA_CLK_DFLL_LOCK, val);
1647 }
1648 DEFINE_SIMPLE_ATTRIBUTE(lock_fops, lock_get, lock_set, "%llu\n");
1649
1650 static int monitor_get(void *data, u64 *val)
1651 {
1652         u32 v, s;
1653         unsigned long flags;
1654         struct clk *c = (struct clk *)data;
1655         struct tegra_cl_dvfs *cld = ((struct clk *)data)->u.dfll.cl_dvfs;
1656
1657         clk_enable(cld->soc_clk);
1658
1659         clk_lock_save(c, &flags);
1660         v = cl_dvfs_readl(cld, CL_DVFS_MONITOR_DATA) &
1661                 CL_DVFS_MONITOR_DATA_MASK;
1662
1663         if (cl_dvfs_readl(cld, CL_DVFS_MONITOR_CTRL) ==
1664             CL_DVFS_MONITOR_CTRL_FREQ) {
1665                 v = GET_MONITORED_RATE(v, cld->ref_rate);
1666                 s = cl_dvfs_readl(cld, CL_DVFS_FREQ_REQ);
1667                 s = (s & CL_DVFS_FREQ_REQ_SCALE_MASK) >>
1668                         CL_DVFS_FREQ_REQ_SCALE_SHIFT;
1669                 *val = (u64)v * (s + 1) / 256;
1670
1671                 clk_unlock_restore(c, &flags);
1672                 clk_disable(cld->soc_clk);
1673                 return 0;
1674         }
1675         *val = v;
1676
1677         clk_unlock_restore(c, &flags);
1678         clk_disable(cld->soc_clk);
1679         return 0;
1680 }
1681 DEFINE_SIMPLE_ATTRIBUTE(monitor_fops, monitor_get, NULL, "%llu\n");
1682
1683 static int vmax_get(void *data, u64 *val)
1684 {
1685         u32 v;
1686         struct tegra_cl_dvfs *cld = ((struct clk *)data)->u.dfll.cl_dvfs;
1687
1688 #if CL_DVFS_DYNAMIC_OUTPUT_CFG
1689         clk_enable(cld->soc_clk);
1690         v = cl_dvfs_readl(cld, CL_DVFS_OUTPUT_CFG);
1691         v = (v & CL_DVFS_OUTPUT_CFG_MAX_MASK) >> CL_DVFS_OUTPUT_CFG_MAX_SHIFT;
1692         clk_disable(cld->soc_clk);
1693 #else
1694         v = cld->lut_max;
1695 #endif
1696         *val = cld->out_map[v]->reg_uV / 1000;
1697         return 0;
1698 }
1699 DEFINE_SIMPLE_ATTRIBUTE(vmax_fops, vmax_get, NULL, "%llu\n");
1700
1701 static int vmin_get(void *data, u64 *val)
1702 {
1703         u32 v;
1704         struct tegra_cl_dvfs *cld = ((struct clk *)data)->u.dfll.cl_dvfs;
1705
1706 #if CL_DVFS_DYNAMIC_OUTPUT_CFG
1707         clk_enable(cld->soc_clk);
1708         v = cl_dvfs_readl(cld, CL_DVFS_OUTPUT_CFG);
1709         v = (v & CL_DVFS_OUTPUT_CFG_MIN_MASK) >> CL_DVFS_OUTPUT_CFG_MIN_SHIFT;
1710         clk_disable(cld->soc_clk);
1711 #else
1712         v = cld->lut_min;
1713 #endif
1714         *val = cld->out_map[v]->reg_uV / 1000;
1715         return 0;
1716 }
1717 DEFINE_SIMPLE_ATTRIBUTE(vmin_fops, vmin_get, NULL, "%llu\n");
1718
1719 static int tune_high_mv_get(void *data, u64 *val)
1720 {
1721         struct tegra_cl_dvfs *cld = ((struct clk *)data)->u.dfll.cl_dvfs;
1722         *val = cld->safe_dvfs->dfll_data.tune_high_min_millivolts;
1723         return 0;
1724 }
1725 static int tune_high_mv_set(void *data, u64 val)
1726 {
1727         unsigned long flags;
1728         struct clk *c = (struct clk *)data;
1729         struct tegra_cl_dvfs *cld = c->u.dfll.cl_dvfs;
1730
1731         clk_lock_save(c, &flags);
1732
1733         cld->safe_dvfs->dfll_data.tune_high_min_millivolts = val;
1734         cl_dvfs_init_output_thresholds(cld);
1735         if (cld->mode == TEGRA_CL_DVFS_CLOSED_LOOP) {
1736                 set_cl_config(cld, &cld->last_req);
1737                 set_request(cld, &cld->last_req);
1738         }
1739
1740         clk_unlock_restore(c, &flags);
1741         return 0;
1742 }
1743 DEFINE_SIMPLE_ATTRIBUTE(tune_high_mv_fops, tune_high_mv_get, tune_high_mv_set,
1744                         "%llu\n");
1745 static int fmin_get(void *data, u64 *val)
1746 {
1747         struct tegra_cl_dvfs *cld = ((struct clk *)data)->u.dfll.cl_dvfs;
1748         *val = cld->dvco_rate_min;
1749         return 0;
1750 }
1751 DEFINE_SIMPLE_ATTRIBUTE(dvco_rate_min_fops, fmin_get, NULL, "%llu\n");
1752
1753 static int calibr_delay_get(void *data, u64 *val)
1754 {
1755         struct tegra_cl_dvfs *cld = ((struct clk *)data)->u.dfll.cl_dvfs;
1756         *val = jiffies_to_msecs(cld->calibration_delay);
1757         return 0;
1758 }
1759 static int calibr_delay_set(void *data, u64 val)
1760 {
1761         unsigned long flags;
1762         struct clk *c = (struct clk *)data;
1763         struct tegra_cl_dvfs *cld = c->u.dfll.cl_dvfs;
1764
1765         clk_lock_save(c, &flags);
1766         cld->calibration_delay = msecs_to_jiffies(val);
1767         clk_unlock_restore(c, &flags);
1768         return 0;
1769 }
1770 DEFINE_SIMPLE_ATTRIBUTE(calibr_delay_fops, calibr_delay_get, calibr_delay_set,
1771                         "%llu\n");
1772
1773 static int undershoot_get(void *data, u64 *val)
1774 {
1775         struct tegra_cl_dvfs *cld = ((struct clk *)data)->u.dfll.cl_dvfs;
1776         *val = cld->p_data->pmu_undershoot_gb;
1777         return 0;
1778 }
1779 static int undershoot_set(void *data, u64 val)
1780 {
1781         unsigned long flags;
1782         struct clk *c = (struct clk *)data;
1783         struct tegra_cl_dvfs *cld = c->u.dfll.cl_dvfs;
1784
1785         clk_lock_save(c, &flags);
1786         cld->p_data->pmu_undershoot_gb = val;
1787         cl_dvfs_set_force_out_min(cld);
1788         clk_unlock_restore(c, &flags);
1789         return 0;
1790 }
1791 DEFINE_SIMPLE_ATTRIBUTE(undershoot_fops, undershoot_get, undershoot_set,
1792                         "%llu\n");
1793
1794 static int cl_register_show(struct seq_file *s, void *data)
1795 {
1796         u32 offs;
1797         struct clk *c = s->private;
1798         struct tegra_cl_dvfs *cld = c->u.dfll.cl_dvfs;
1799
1800         clk_enable(cld->soc_clk);
1801
1802         seq_printf(s, "CONTROL REGISTERS:\n");
1803         for (offs = 0; offs <= CL_DVFS_MONITOR_DATA; offs += 4)
1804                 seq_printf(s, "[0x%02x] = 0x%08x\n",
1805                            offs, cl_dvfs_readl(cld, offs));
1806
1807         seq_printf(s, "\nI2C and INTR REGISTERS:\n");
1808         for (offs = CL_DVFS_I2C_CFG; offs <= CL_DVFS_I2C_STS; offs += 4)
1809                 seq_printf(s, "[0x%02x] = 0x%08x\n",
1810                            offs, cl_dvfs_readl(cld, offs));
1811
1812         offs = CL_DVFS_INTR_STS;
1813         seq_printf(s, "[0x%02x] = 0x%08x\n", offs, cl_dvfs_readl(cld, offs));
1814         offs = CL_DVFS_INTR_EN;
1815         seq_printf(s, "[0x%02x] = 0x%08x\n", offs, cl_dvfs_readl(cld, offs));
1816
1817         seq_printf(s, "\nLUT:\n");
1818         for (offs = CL_DVFS_OUTPUT_LUT;
1819              offs < CL_DVFS_OUTPUT_LUT + 4 * MAX_CL_DVFS_VOLTAGES;
1820              offs += 4)
1821                 seq_printf(s, "[0x%02x] = 0x%08x\n",
1822                            offs, cl_dvfs_readl(cld, offs));
1823
1824         clk_disable(cld->soc_clk);
1825         return 0;
1826 }
1827
1828 static int cl_register_open(struct inode *inode, struct file *file)
1829 {
1830         return single_open(file, cl_register_show, inode->i_private);
1831 }
1832
1833 static ssize_t cl_register_write(struct file *file,
1834         const char __user *userbuf, size_t count, loff_t *ppos)
1835 {
1836         char buf[80];
1837         u32 offs;
1838         u32 val;
1839         struct clk *c = file->f_path.dentry->d_inode->i_private;
1840         struct tegra_cl_dvfs *cld = c->u.dfll.cl_dvfs;
1841
1842         if (sizeof(buf) <= count)
1843                 return -EINVAL;
1844
1845         if (copy_from_user(buf, userbuf, count))
1846                 return -EFAULT;
1847
1848         /* terminate buffer and trim - white spaces may be appended
1849          *  at the end when invoked from shell command line */
1850         buf[count] = '\0';
1851         strim(buf);
1852
1853         if (sscanf(buf, "[0x%x] = 0x%x", &offs, &val) != 2)
1854                 return -1;
1855
1856         clk_enable(cld->soc_clk);
1857         cl_dvfs_writel(cld, val, offs & (~0x3));
1858         clk_disable(cld->soc_clk);
1859         return count;
1860 }
1861
1862 static const struct file_operations cl_register_fops = {
1863         .open           = cl_register_open,
1864         .read           = seq_read,
1865         .write          = cl_register_write,
1866         .llseek         = seq_lseek,
1867         .release        = single_release,
1868 };
1869
1870 int __init tegra_cl_dvfs_debug_init(struct clk *dfll_clk)
1871 {
1872         struct dentry *cl_dvfs_dentry;
1873
1874         if (!dfll_clk || !dfll_clk->dent || (dfll_clk->state == UNINITIALIZED))
1875                 return 0;
1876
1877         if (!debugfs_create_file("lock", S_IRUGO | S_IWUSR,
1878                 dfll_clk->dent, dfll_clk, &lock_fops))
1879                 goto err_out;
1880
1881         cl_dvfs_dentry = debugfs_create_dir("cl_dvfs", dfll_clk->dent);
1882         if (!cl_dvfs_dentry)
1883                 goto err_out;
1884
1885         if (!debugfs_create_file("monitor", S_IRUGO,
1886                 cl_dvfs_dentry, dfll_clk, &monitor_fops))
1887                 goto err_out;
1888
1889         if (!debugfs_create_file("vmax_mv", S_IRUGO,
1890                 cl_dvfs_dentry, dfll_clk, &vmax_fops))
1891                 goto err_out;
1892
1893         if (!debugfs_create_file("vmin_mv", S_IRUGO,
1894                 cl_dvfs_dentry, dfll_clk, &vmin_fops))
1895                 goto err_out;
1896
1897         if (!debugfs_create_file("tune_high_mv", S_IRUGO | S_IWUSR,
1898                 cl_dvfs_dentry, dfll_clk, &tune_high_mv_fops))
1899                 goto err_out;
1900
1901         if (!debugfs_create_file("dvco_min", S_IRUGO,
1902                 cl_dvfs_dentry, dfll_clk, &dvco_rate_min_fops))
1903                 goto err_out;
1904
1905         if (!debugfs_create_file("calibr_delay", S_IRUGO,
1906                 cl_dvfs_dentry, dfll_clk, &calibr_delay_fops))
1907                 goto err_out;
1908
1909         if (!debugfs_create_file("pmu_undershoot_gb", S_IRUGO,
1910                 cl_dvfs_dentry, dfll_clk, &undershoot_fops))
1911                 goto err_out;
1912
1913         if (!debugfs_create_file("registers", S_IRUGO | S_IWUSR,
1914                 cl_dvfs_dentry, dfll_clk, &cl_register_fops))
1915                 goto err_out;
1916
1917         return 0;
1918
1919 err_out:
1920         debugfs_remove_recursive(dfll_clk->dent);
1921         return -ENOMEM;
1922 }
1923 #endif