arm: tegra: usb_phy: fix remote wakeup issues
[linux-2.6.git] / arch / arm / mach-tegra / tegra3_usb_phy.c
1 /*
2  * arch/arm/mach-tegra/tegra3_usb_phy.c
3  *
4  * Copyright (C) 2011 NVIDIA Corporation
5  *
6  *
7  * This software is licensed under the terms of the GNU General Public
8  * License version 2, as published by the Free Software Foundation, and
9  * may be copied, distributed, and modified under those terms.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17 #include <linux/resource.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/slab.h>
21 #include <linux/err.h>
22 #include <linux/platform_device.h>
23 #include <linux/io.h>
24 #include <linux/gpio.h>
25 #include <linux/interrupt.h>
26 #include <linux/clk.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <mach/iomap.h>
30 #include <mach/pinmux.h>
31 #include <mach/pinmux-tegra30.h>
32 #include "tegra_usb_phy.h"
33 #include "fuse.h"
34
35 #define USB_USBCMD              0x130
36 #define   USB_USBCMD_RS         (1 << 0)
37 #define   USB_CMD_RESET (1<<1)
38
39 #define USB_USBSTS              0x134
40 #define   USB_USBSTS_PCI        (1 << 2)
41 #define   USB_USBSTS_SRI        (1 << 7)
42 #define   USB_USBSTS_HCH        (1 << 12)
43
44 #define USB_USBINTR             0x138
45
46 #define USB_TXFILLTUNING        0x154
47 #define USB_FIFO_TXFILL_THRES(x)   (((x) & 0x1f) << 16)
48 #define USB_FIFO_TXFILL_MASK    0x1f0000
49
50 #define USB_ASYNCLISTADDR       0x148
51
52 #define ICUSB_CTRL              0x15c
53
54 #define USB_PORTSC              0x174
55 #define   USB_PORTSC_WKOC       (1 << 22)
56 #define   USB_PORTSC_WKDS       (1 << 21)
57 #define   USB_PORTSC_WKCN       (1 << 20)
58 #define   USB_PORTSC_PTC(x)     (((x) & 0xf) << 16)
59 #define   USB_PORTSC_PP (1 << 12)
60 #define   USB_PORTSC_LS(x) (((x) & 0x3) << 10)
61 #define   USB_PORTSC_SUSP       (1 << 7)
62 #define   USB_PORTSC_RESUME     (1 << 6)
63 #define   USB_PORTSC_OCC        (1 << 5)
64 #define   USB_PORTSC_PEC        (1 << 3)
65 #define   USB_PORTSC_PE         (1 << 2)
66 #define   USB_PORTSC_CSC        (1 << 1)
67 #define   USB_PORTSC_CCS        (1 << 0)
68 #define   USB_PORTSC_RWC_BITS (USB_PORTSC_CSC | USB_PORTSC_PEC | USB_PORTSC_OCC)
69
70 #define HOSTPC1_DEVLC           0x1b4
71 #define   HOSTPC1_DEVLC_PHCD            (1 << 22)
72 #define   HOSTPC1_DEVLC_PTS(x)          (((x) & 0x7) << 29)
73 #define   HOSTPC1_DEVLC_PTS_MASK        7
74 #define   HOSTPC1_DEVLC_PTS_HSIC        4
75 #define   HOSTPC1_DEVLC_STS             (1 << 28)
76 #define   HOSTPC1_DEVLC_PSPD(x)         (((x) & 0x3) << 25)
77 #define   HOSTPC1_DEVLC_PSPD_MASK       3
78 #define   HOSTPC1_DEVLC_PSPD_HIGH_SPEED 2
79
80 #define USB_USBMODE             0x1f8
81 #define   USB_USBMODE_MASK              (3 << 0)
82 #define   USB_USBMODE_HOST              (3 << 0)
83 #define   USB_USBMODE_DEVICE            (2 << 0)
84
85 #define USB_SUSP_CTRL           0x400
86 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
87 #define   USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
88 #define   USB_SUSP_CLR                  (1 << 5)
89 #define   USB_PHY_CLK_VALID             (1 << 7)
90 #define   USB_PHY_CLK_VALID_INT_ENB     (1 << 9)
91 #define   USB_PHY_CLK_VALID_INT_STS     (1 << 8)
92 #define   UTMIP_RESET                   (1 << 11)
93 #define   UTMIP_PHY_ENABLE              (1 << 12)
94 #define   ULPI_PHY_ENABLE               (1 << 13)
95 #define   UHSIC_RESET                   (1 << 14)
96 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
97 #define   UHSIC_PHY_ENABLE              (1 << 19)
98 #define   ULPIS2S_SLV0_RESET            (1 << 20)
99 #define   ULPIS2S_SLV1_RESET            (1 << 21)
100 #define   ULPIS2S_LINE_RESET            (1 << 22)
101 #define   ULPI_PADS_RESET               (1 << 23)
102 #define   ULPI_PADS_CLKEN_RESET         (1 << 24)
103
104 #define USB_PHY_VBUS_WAKEUP_ID  0x408
105 #define   VDAT_DET_INT_EN       (1 << 16)
106 #define   VDAT_DET_CHG_DET      (1 << 17)
107 #define   VDAT_DET_STS          (1 << 18)
108 #define   USB_ID_STATUS         (1 << 2)
109
110 #define ULPIS2S_CTRL            0x418
111 #define   ULPIS2S_ENA                   (1 << 0)
112 #define   ULPIS2S_SUPPORT_DISCONNECT    (1 << 2)
113 #define   ULPIS2S_PLLU_MASTER_BLASTER60 (1 << 3)
114 #define   ULPIS2S_SPARE(x)              (((x) & 0xF) << 8)
115 #define   ULPIS2S_FORCE_ULPI_CLK_OUT    (1 << 12)
116 #define   ULPIS2S_DISCON_DONT_CHECK_SE0 (1 << 13)
117 #define   ULPIS2S_SUPPORT_HS_KEEP_ALIVE (1 << 14)
118 #define   ULPIS2S_DISABLE_STP_PU        (1 << 15)
119 #define   ULPIS2S_SLV0_CLAMP_XMIT       (1 << 16)
120
121 #define ULPI_TIMING_CTRL_0      0x424
122 #define   ULPI_CLOCK_OUT_DELAY(x)       ((x) & 0x1F)
123 #define   ULPI_OUTPUT_PINMUX_BYP        (1 << 10)
124 #define   ULPI_CLKOUT_PINMUX_BYP        (1 << 11)
125 #define   ULPI_SHADOW_CLK_LOOPBACK_EN   (1 << 12)
126 #define   ULPI_SHADOW_CLK_SEL           (1 << 13)
127 #define   ULPI_CORE_CLK_SEL             (1 << 14)
128 #define   ULPI_SHADOW_CLK_DELAY(x)      (((x) & 0x1F) << 16)
129 #define   ULPI_LBK_PAD_EN               (1 << 26)
130 #define   ULPI_LBK_PAD_E_INPUT_OR       (1 << 27)
131 #define   ULPI_CLK_OUT_ENA              (1 << 28)
132 #define   ULPI_CLK_PADOUT_ENA           (1 << 29)
133
134 #define ULPI_TIMING_CTRL_1      0x428
135 #define   ULPI_DATA_TRIMMER_LOAD        (1 << 0)
136 #define   ULPI_DATA_TRIMMER_SEL(x)      (((x) & 0x7) << 1)
137 #define   ULPI_STPDIRNXT_TRIMMER_LOAD   (1 << 16)
138 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
139 #define   ULPI_DIR_TRIMMER_LOAD         (1 << 24)
140 #define   ULPI_DIR_TRIMMER_SEL(x)       (((x) & 0x7) << 25)
141
142 #define UTMIP_XCVR_CFG0         0x808
143 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
144 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
145 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
146 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
147 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
148 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
149 #define   UTMIP_XCVR_LSBIAS_SEL                 (1 << 21)
150 #define   UTMIP_XCVR_SETUP_MSB(x)               (((x) & 0x7) << 22)
151 #define   UTMIP_XCVR_HSSLEW_MSB(x)              (((x) & 0x7f) << 25)
152 #define   UTMIP_XCVR_MAX_OFFSET         2
153 #define   UTMIP_XCVR_SETUP_MAX_VALUE    0x7f
154 #define   UTMIP_XCVR_SETUP_MIN_VALUE    0
155 #define   XCVR_SETUP_MSB_CALIB(x) ((x) >> 4)
156
157 #define UTMIP_BIAS_CFG0         0x80c
158 #define   UTMIP_OTGPD                   (1 << 11)
159 #define   UTMIP_BIASPD                  (1 << 10)
160 #define   UTMIP_HSSQUELCH_LEVEL(x)      (((x) & 0x3) << 0)
161 #define   UTMIP_HSDISCON_LEVEL(x)       (((x) & 0x3) << 2)
162 #define   UTMIP_HSDISCON_LEVEL_MSB      (1 << 24)
163
164 #define UTMIP_HSRX_CFG0         0x810
165 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
166 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
167
168 #define UTMIP_HSRX_CFG1         0x814
169 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
170
171 #define UTMIP_TX_CFG0           0x820
172 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
173 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
174
175 #define UTMIP_DEBOUNCE_CFG0 0x82c
176 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
177
178 #define UTMIP_BAT_CHRG_CFG0 0x830
179 #define   UTMIP_PD_CHRG                 (1 << 0)
180 #define   UTMIP_ON_SINK_EN              (1 << 2)
181 #define   UTMIP_OP_SRC_EN               (1 << 3)
182
183 #define UTMIP_XCVR_CFG1         0x838
184 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
185 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
186 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
187 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
188
189 #define UTMIP_BIAS_CFG1         0x83c
190 #define   UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
191 #define   UTMIP_BIAS_PDTRK_POWERDOWN    (1 << 0)
192 #define   UTMIP_BIAS_PDTRK_POWERUP      (1 << 1)
193
194 #define UTMIP_MISC_CFG0         0x824
195 #define   UTMIP_DPDM_OBSERVE            (1 << 26)
196 #define   UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
197 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J   UTMIP_DPDM_OBSERVE_SEL(0xf)
198 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K   UTMIP_DPDM_OBSERVE_SEL(0xe)
199 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
200 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
201 #define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
202 #define   FORCE_PULLDN_DM       (1 << 8)
203 #define   FORCE_PULLDN_DP       (1 << 9)
204 #define   COMB_TERMS            (1 << 0)
205 #define   ALWAYS_FREE_RUNNING_TERMS (1 << 1)
206
207 #define UTMIP_SPARE_CFG0        0x834
208 #define   FUSE_SETUP_SEL                (1 << 3)
209 #define   FUSE_ATERM_SEL                (1 << 4)
210
211 #define UTMIP_PMC_WAKEUP0               0x84c
212 #define   EVENT_INT_ENB                 (1 << 0)
213
214 #define UTMIP_BIAS_STS0                 0x840
215 #define   UTMIP_RCTRL_VAL(x)            (((x) & 0xffff) << 0)
216 #define   UTMIP_TCTRL_VAL(x)            (((x) & (0xffff << 16)) >> 16)
217
218 #define UHSIC_PLL_CFG1                          0xc04
219 #define   UHSIC_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
220 #define   UHSIC_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 14)
221
222 #define UHSIC_HSRX_CFG0                         0xc08
223 #define   UHSIC_ELASTIC_UNDERRUN_LIMIT(x)       (((x) & 0x1f) << 2)
224 #define   UHSIC_ELASTIC_OVERRUN_LIMIT(x)        (((x) & 0x1f) << 8)
225 #define   UHSIC_IDLE_WAIT(x)                    (((x) & 0x1f) << 13)
226
227 #define UHSIC_HSRX_CFG1                         0xc0c
228 #define   UHSIC_HS_SYNC_START_DLY(x)            (((x) & 0x1f) << 1)
229
230 #define UHSIC_TX_CFG0                           0xc10
231 #define UHSIC_HS_READY_WAIT_FOR_VALID   (1 << 9)
232 #define UHSIC_MISC_CFG0                         0xc14
233 #define   UHSIC_SUSPEND_EXIT_ON_EDGE            (1 << 7)
234 #define   UHSIC_DETECT_SHORT_CONNECT            (1 << 8)
235 #define   UHSIC_FORCE_XCVR_MODE                 (1 << 15)
236 #define   UHSIC_DISABLE_BUSRESET                (1 << 20)
237 #define UHSIC_MISC_CFG1                         0xc18
238 #define   UHSIC_PLLU_STABLE_COUNT(x)            (((x) & 0xfff) << 2)
239
240 #define UHSIC_PADS_CFG0                         0xc1c
241 #define   UHSIC_TX_RTUNEN                       0xf000
242 #define   UHSIC_TX_RTUNE(x)                     (((x) & 0xf) << 12)
243
244 #define UHSIC_PADS_CFG1                         0xc20
245 #define   UHSIC_PD_BG                           (1 << 2)
246 #define   UHSIC_PD_TX                           (1 << 3)
247 #define   UHSIC_PD_TRK                          (1 << 4)
248 #define   UHSIC_PD_RX                           (1 << 5)
249 #define   UHSIC_PD_ZI                           (1 << 6)
250 #define   UHSIC_RX_SEL                          (1 << 7)
251 #define   UHSIC_RPD_DATA                        (1 << 9)
252 #define   UHSIC_RPD_STROBE                      (1 << 10)
253 #define   UHSIC_RPU_DATA                        (1 << 11)
254 #define   UHSIC_RPU_STROBE                      (1 << 12)
255
256 #define UHSIC_STAT_CFG0                 0xc28
257 #define   UHSIC_CONNECT_DETECT                  (1 << 0)
258
259 #define PMC_USB_DEBOUNCE                        0xec
260 #define   UTMIP_LINE_DEB_CNT(x)                 (((x) & 0xf) << 16)
261
262 #define PMC_USB_AO                              0xf0
263 #define PMC_POWER_DOWN_MASK                     0xffff
264 #define HSIC_RESERVED_P0                        (3 << 14)
265 #define HSIC_STOBE_VAL_PD_P0                    (1 << 13)
266 #define HSIC_DATA_VAL_PD_P0                     (1 << 12)
267 #define USB_ID_PD(inst)                         (1 << ((4*(inst))+3))
268 #define VBUS_WAKEUP_PD(inst)                    (1 << ((4*(inst))+2))
269 #define   USBON_VAL_PD(inst)                    (1 << ((4*(inst))+1))
270 #define   USBON_VAL_PD_P2                       (1 << 9)
271 #define   USBON_VAL_PD_P1                       (1 << 5)
272 #define   USBON_VAL_PD_P0                       (1 << 1)
273 #define   USBOP_VAL_PD(inst)                    (1 << (4*(inst)))
274 #define   USBOP_VAL_PD_P2                       (1 << 8)
275 #define   USBOP_VAL_PD_P1                       (1 << 4)
276 #define   USBOP_VAL_PD_P0                       (1 << 0)
277 #define   PMC_USB_AO_PD_P2                      (0xf << 8)
278 #define   PMC_USB_AO_ID_PD_P0                   (1 << 3)
279 #define   PMC_USB_AO_VBUS_WAKEUP_PD_P0  (1 << 2)
280
281 #define PMC_TRIGGERS                    0x1ec
282 #define   UTMIP_CLR_WALK_PTR(inst)      (1 << (inst))
283 #define   UTMIP_CLR_WALK_PTR_P2         (1 << 2)
284 #define   UTMIP_CLR_WALK_PTR_P1         (1 << 1)
285 #define   UTMIP_CLR_WALK_PTR_P0         (1 << 0)
286 #define   UTMIP_CAP_CFG(inst)   (1 << ((inst)+4))
287 #define   UTMIP_CAP_CFG_P2              (1 << 6)
288 #define   UTMIP_CAP_CFG_P1              (1 << 5)
289 #define   UTMIP_CAP_CFG_P0              (1 << 4)
290 #define   UTMIP_CLR_WAKE_ALARM(inst)            (1 << ((inst)+12))
291 #define   UTMIP_CLR_WAKE_ALARM_P2       (1 << 14)
292
293 #define PMC_PAD_CFG             (0x1f4)
294
295 #define PMC_UTMIP_TERM_PAD_CFG  0x1f8
296 #define   PMC_TCTRL_VAL(x)      (((x) & 0x1f) << 5)
297 #define   PMC_RCTRL_VAL(x)      (((x) & 0x1f) << 0)
298
299 #define UHSIC_SLEEPWALK_REG             0x210
300 #define UHSIC_DATA_RPD_D                (1 << 25)
301 #define UHSIC_STRB_RPD_D                (1 << 24)
302 #define UHSIC_DATA_RPD_C                (1 << 17)
303 #define UHSIC_STRB_RPD_C                (1 << 16)
304 #define UHSIC_DATA_RPD_B                (1 << 9)
305 #define UHSIC_STRB_RPD_B                (1 << 8)
306 #define UHSIC_DATA_RPD_A                (1 << 1)
307 #define UHSIC_STRB_RPD_A                (1 << 0)
308
309 #define PMC_SLEEP_CFG                   0x1fc
310 #define   UTMIP_TCTRL_USE_PMC(inst) (1 << ((8*(inst))+3))
311 #define   UTMIP_TCTRL_USE_PMC_P2                (1 << 19)
312 #define   UTMIP_TCTRL_USE_PMC_P1                (1 << 11)
313 #define   UTMIP_TCTRL_USE_PMC_P0                (1 << 3)
314 #define   UTMIP_RCTRL_USE_PMC(inst) (1 << ((8*(inst))+2))
315 #define   UTMIP_RCTRL_USE_PMC_P2                (1 << 18)
316 #define   UTMIP_RCTRL_USE_PMC_P1                (1 << 10)
317 #define   UTMIP_RCTRL_USE_PMC_P0                (1 << 2)
318 #define   UTMIP_FSLS_USE_PMC(inst)      (1 << ((8*(inst))+1))
319 #define   UTMIP_FSLS_USE_PMC_P2         (1 << 17)
320 #define   UTMIP_FSLS_USE_PMC_P1         (1 << 9)
321 #define   UTMIP_FSLS_USE_PMC_P0         (1 << 1)
322 #define   UTMIP_MASTER_ENABLE(inst) (1 << (8*(inst)))
323 #define   UTMIP_MASTER_ENABLE_P2                (1 << 16)
324 #define   UTMIP_MASTER_ENABLE_P1                (1 << 8)
325 #define   UTMIP_MASTER_ENABLE_P0                (1 << 0)
326 #define UHSIC_MASTER_ENABLE_P0          (1 << 24)
327 #define UHSIC_WAKE_VAL_P0(x)            (((x) & 0xf) << 28)
328
329 #define PMC_SLEEPWALK_CFG               0x200
330 #define   UTMIP_LINEVAL_WALK_EN(inst) (1 << ((8*(inst))+7))
331 #define   UTMIP_LINEVAL_WALK_EN_P2      (1 << 23)
332 #define   UTMIP_LINEVAL_WALK_EN_P1      (1 << 15)
333 #define   UTMIP_LINEVAL_WALK_EN_P0      (1 << 7)
334 #define   UTMIP_WAKE_VAL(inst, x) (((x) & 0xf) << ((8*(inst))+4))
335 #define   UTMIP_WAKE_VAL_P2(x)          (((x) & 0xf) << 20)
336 #define   UTMIP_WAKE_VAL_P1(x)          (((x) & 0xf) << 12)
337 #define   UTMIP_WAKE_VAL_P0(x)          (((x) & 0xf) << 4)
338 #define   WAKE_VAL_NONE         0xc
339 #define   WAKE_VAL_ANY                  0xF
340 #define   WAKE_VAL_FSJ                  0x2
341 #define   WAKE_VAL_FSK                  0x1
342 #define   WAKE_VAL_SE0                  0x0
343
344 #define PMC_SLEEPWALK_REG(inst)         (0x204 + (4*(inst)))
345 #define   UTMIP_USBOP_RPD_A     (1 << 0)
346 #define   UTMIP_USBON_RPD_A     (1 << 1)
347 #define   UTMIP_AP_A                    (1 << 4)
348 #define   UTMIP_AN_A                    (1 << 5)
349 #define   UTMIP_HIGHZ_A         (1 << 6)
350 #define   UTMIP_USBOP_RPD_B     (1 << 8)
351 #define   UTMIP_USBON_RPD_B     (1 << 9)
352 #define   UTMIP_AP_B                    (1 << 12)
353 #define   UTMIP_AN_B                    (1 << 13)
354 #define   UTMIP_HIGHZ_B         (1 << 14)
355 #define   UTMIP_USBOP_RPD_C     (1 << 16)
356 #define   UTMIP_USBON_RPD_C     (1 << 17)
357 #define   UTMIP_AP_C            (1 << 20)
358 #define   UTMIP_AN_C            (1 << 21)
359 #define   UTMIP_HIGHZ_C         (1 << 22)
360 #define   UTMIP_USBOP_RPD_D     (1 << 24)
361 #define   UTMIP_USBON_RPD_D     (1 << 25)
362 #define   UTMIP_AP_D            (1 << 28)
363 #define   UTMIP_AN_D            (1 << 29)
364 #define   UTMIP_HIGHZ_D         (1 << 30)
365
366 #define UTMIP_UHSIC_STATUS              0x214
367 #define   UTMIP_WALK_PTR_VAL(inst)      (0x3 << ((inst)*2))
368 #define   UTMIP_USBOP_VAL(inst)         (1 << ((2*(inst)) + 8))
369 #define   UTMIP_USBOP_VAL_P2            (1 << 12)
370 #define   UTMIP_USBOP_VAL_P1            (1 << 10)
371 #define   UTMIP_USBOP_VAL_P0            (1 << 8)
372 #define   UTMIP_USBON_VAL(inst)         (1 << ((2*(inst)) + 9))
373 #define   UTMIP_USBON_VAL_P2            (1 << 13)
374 #define   UTMIP_USBON_VAL_P1            (1 << 11)
375 #define   UTMIP_USBON_VAL_P0            (1 << 9)
376 #define   UTMIP_WAKE_ALARM(inst)                (1 << ((inst) + 16))
377 #define   UTMIP_WAKE_ALARM_P2   (1 << 18)
378 #define   UTMIP_WAKE_ALARM_P1   (1 << 17)
379 #define   UTMIP_WAKE_ALARM_P0   (1 << 16)
380 #define   UTMIP_WALK_PTR(inst)  (1 << ((inst)*2))
381 #define   UTMIP_WALK_PTR_P2     (1 << 4)
382 #define   UTMIP_WALK_PTR_P1     (1 << 2)
383 #define   UTMIP_WALK_PTR_P0     (1 << 0)
384
385 #define USB1_PREFETCH_ID               6
386 #define USB2_PREFETCH_ID               18
387 #define USB3_PREFETCH_ID               17
388
389 #define PMC_UTMIP_UHSIC_FAKE            0x218
390 #define   USBON_VAL(inst)       (1 << ((4*(inst))+1))
391 #define   USBON_VAL_P2                  (1 << 9)
392 #define   USBON_VAL_P1                  (1 << 5)
393 #define   USBON_VAL_P0                  (1 << 1)
394 #define   USBOP_VAL(inst)       (1 << (4*(inst)))
395 #define   USBOP_VAL_P2                  (1 << 8)
396 #define   USBOP_VAL_P1                  (1 << 4)
397 #define   USBOP_VAL_P0                  (1 << 0)
398
399 #define PMC_UTMIP_BIAS_MASTER_CNTRL 0x30c
400 #define   BIAS_MASTER_PROG_VAL          (1 << 1)
401
402 #define PMC_UTMIP_MASTER_CONFIG         0x310
403 #define   UTMIP_PWR(inst)               (1 << (inst))
404
405 #define FUSE_USB_CALIB_0                0x1F0
406 #define   FUSE_USB_CALIB_XCVR_SETUP(x)  (((x) & 0x7F) << 0)
407
408 /* These values (in milli second) are taken from the battery charging spec */
409 #define TDP_SRC_ON_MS    100
410 #define TDPSRC_CON_MS    40
411
412 #ifdef DEBUG
413 #define DBG(stuff...)   pr_info("tegra3_usb_phy: " stuff)
414 #else
415 #define DBG(stuff...)   do {} while (0)
416 #endif
417
418 #if 0
419 #define PHY_DBG(stuff...)       pr_info("tegra3_usb_phy: " stuff)
420 #else
421 #define PHY_DBG(stuff...)       do {} while (0)
422 #endif
423
424 static u32 utmip_rctrl_val, utmip_tctrl_val;
425 static DEFINE_SPINLOCK(utmip_pad_lock);
426 static int utmip_pad_count;
427
428 static struct tegra_xtal_freq utmip_freq_table[] = {
429         {
430                 .freq = 12000000,
431                 .enable_delay = 0x02,
432                 .stable_count = 0x2F,
433                 .active_delay = 0x04,
434                 .xtal_freq_count = 0x76,
435                 .debounce = 0x7530,
436                 .pdtrk_count = 5,
437         },
438         {
439                 .freq = 13000000,
440                 .enable_delay = 0x02,
441                 .stable_count = 0x33,
442                 .active_delay = 0x05,
443                 .xtal_freq_count = 0x7F,
444                 .debounce = 0x7EF4,
445                 .pdtrk_count = 5,
446         },
447         {
448                 .freq = 19200000,
449                 .enable_delay = 0x03,
450                 .stable_count = 0x4B,
451                 .active_delay = 0x06,
452                 .xtal_freq_count = 0xBB,
453                 .debounce = 0xBB80,
454                 .pdtrk_count = 7,
455         },
456         {
457                 .freq = 26000000,
458                 .enable_delay = 0x04,
459                 .stable_count = 0x66,
460                 .active_delay = 0x09,
461                 .xtal_freq_count = 0xFE,
462                 .debounce = 0xFDE8,
463                 .pdtrk_count = 9,
464         },
465 };
466
467 static struct tegra_xtal_freq uhsic_freq_table[] = {
468         {
469                 .freq = 12000000,
470                 .enable_delay = 0x02,
471                 .stable_count = 0x2F,
472                 .active_delay = 0x0,
473                 .xtal_freq_count = 0x1CA,
474         },
475         {
476                 .freq = 13000000,
477                 .enable_delay = 0x02,
478                 .stable_count = 0x33,
479                 .active_delay = 0x0,
480                 .xtal_freq_count = 0x1F0,
481         },
482         {
483                 .freq = 19200000,
484                 .enable_delay = 0x03,
485                 .stable_count = 0x4B,
486                 .active_delay = 0x0,
487                 .xtal_freq_count = 0x2DD,
488         },
489         {
490                 .freq = 26000000,
491                 .enable_delay = 0x04,
492                 .stable_count = 0x66,
493                 .active_delay = 0x0,
494                 .xtal_freq_count = 0x3E0,
495         },
496 };
497
498 static void usb_phy_fence_read(struct tegra_usb_phy *phy)
499 {
500         /* Fence read for coherency of AHB master intiated writes */
501         if (phy->inst == 0)
502                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB1_PREFETCH_ID));
503         else if (phy->inst == 1)
504                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB2_PREFETCH_ID));
505         else if (phy->inst == 2)
506                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB3_PREFETCH_ID));
507
508         return;
509 }
510
511 static void utmip_setup_pmc_wake_detect(struct tegra_usb_phy *phy)
512 {
513         unsigned long val, pmc_pad_cfg_val;
514         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
515         unsigned  int inst = phy->inst;
516         void __iomem *base = phy->regs;
517         bool port_connected;
518         enum usb_phy_port_speed port_speed;
519
520         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
521
522         /* check for port connect status */
523         val = readl(base + USB_PORTSC);
524         port_connected = val & USB_PORTSC_CCS;
525
526         if (!port_connected)
527                 return;
528
529         port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
530                 HOSTPC1_DEVLC_PSPD_MASK;
531         /*Set PMC MASTER bits to do the following
532         * a. Take over the UTMI drivers
533         * b. set up such that it will take over resume
534         *        if remote wakeup is detected
535         * Prepare PMC to take over suspend-wake detect-drive resume until USB
536         * controller ready
537         */
538
539         /* disable master enable in PMC */
540         val = readl(pmc_base + PMC_SLEEP_CFG);
541         val &= ~UTMIP_MASTER_ENABLE(inst);
542         writel(val, pmc_base + PMC_SLEEP_CFG);
543
544         /* UTMIP_PWR_PX=1 for power savings mode */
545         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
546         val |= UTMIP_PWR(inst);
547         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
548
549         /* config debouncer */
550         val = readl(pmc_base + PMC_USB_DEBOUNCE);
551         val &= ~UTMIP_LINE_DEB_CNT(~0);
552         val |= UTMIP_LINE_DEB_CNT(4);
553         writel(val, pmc_base + PMC_USB_DEBOUNCE);
554
555         /* Make sure nothing is happening on the line with respect to PMC */
556         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
557         val &= ~USBOP_VAL(inst);
558         val &= ~USBON_VAL(inst);
559         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
560
561         /* Make sure wake value for line is none */
562         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
563         val &= ~UTMIP_LINEVAL_WALK_EN(inst);
564         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
565         val = readl(pmc_base + PMC_SLEEP_CFG);
566         val &= ~UTMIP_WAKE_VAL(inst, ~0);
567         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
568         writel(val, pmc_base + PMC_SLEEP_CFG);
569
570         /* turn off pad detectors */
571         val = readl(pmc_base + PMC_USB_AO);
572         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
573         writel(val, pmc_base + PMC_USB_AO);
574
575         /* Remove fake values and make synchronizers work a bit */
576         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
577         val &= ~USBOP_VAL(inst);
578         val &= ~USBON_VAL(inst);
579         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
580
581         /* Enable which type of event can trigger a walk,
582         in this case usb_line_wake */
583         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
584         val |= UTMIP_LINEVAL_WALK_EN(inst);
585         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
586
587         /* Enable which type of event can trigger a walk,
588         * in this case usb_line_wake */
589         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
590         val |= UTMIP_LINEVAL_WALK_EN(inst);
591         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
592
593         /* Clear the walk pointers and wake alarm */
594         val = readl(pmc_base + PMC_TRIGGERS);
595         val |= UTMIP_CLR_WAKE_ALARM(inst) | UTMIP_CLR_WALK_PTR(inst);
596         writel(val, pmc_base + PMC_TRIGGERS);
597
598
599         /* Capture FS/LS pad configurations */
600         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
601         val = readl(pmc_base + PMC_TRIGGERS);
602         val |= UTMIP_CAP_CFG(inst);
603         writel(val, pmc_base + PMC_TRIGGERS);
604         udelay(1);
605         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
606
607         /* BIAS MASTER_ENABLE=0 */
608         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
609         val &= ~BIAS_MASTER_PROG_VAL;
610         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
611
612         /* program walk sequence, maintain a J, followed by a driven K
613         * to signal a resume once an wake event is detected */
614         val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
615         val &= ~UTMIP_AP_A;
616         val |= UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_AN_A |UTMIP_HIGHZ_A |
617                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_AP_B | UTMIP_AN_B |
618                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_AP_C | UTMIP_AN_C |
619                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_AP_D | UTMIP_AN_D;
620         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
621
622         if (port_speed == USB_PHY_PORT_SPEED_LOW) {
623                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
624                 val &= ~(UTMIP_AN_B | UTMIP_HIGHZ_B | UTMIP_AN_C |
625                         UTMIP_HIGHZ_C | UTMIP_AN_D | UTMIP_HIGHZ_D);
626                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
627         } else {
628                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
629                 val &= ~(UTMIP_AP_B | UTMIP_HIGHZ_B | UTMIP_AP_C |
630                         UTMIP_HIGHZ_C | UTMIP_AP_D | UTMIP_HIGHZ_D);
631                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
632         }
633
634         /* turn on pad detectors */
635         val = readl(pmc_base + PMC_USB_AO);
636         val &= ~(USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
637         writel(val, pmc_base + PMC_USB_AO);
638
639         /* Add small delay before usb detectors provide stable line values */
640         mdelay(1);
641
642         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
643         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
644         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
645         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
646
647         phy->remote_wakeup = false;
648
649         /* Turn over pad configuration to PMC  for line wake events*/
650         val = readl(pmc_base + PMC_SLEEP_CFG);
651         val &= ~UTMIP_WAKE_VAL(inst, ~0);
652         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_ANY);
653         val |= UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst);
654         val |= UTMIP_MASTER_ENABLE(inst) | UTMIP_FSLS_USE_PMC(inst);
655         writel(val, pmc_base + PMC_SLEEP_CFG);
656
657         val = readl(base + UTMIP_PMC_WAKEUP0);
658         val |= EVENT_INT_ENB;
659         writel(val, base + UTMIP_PMC_WAKEUP0);
660         PHY_DBG("%s ENABLE_PMC inst = %d\n", __func__, inst);
661 }
662
663 static void utmip_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy)
664 {
665         unsigned long val;
666         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
667         unsigned  int inst = phy->inst;
668         void __iomem *base = phy->regs;
669
670         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
671
672         val = readl(pmc_base + PMC_SLEEP_CFG);
673         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
674         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
675         writel(val, pmc_base + PMC_SLEEP_CFG);
676
677         val = readl(pmc_base + PMC_TRIGGERS);
678         val |= UTMIP_CLR_WAKE_ALARM(inst) | UTMIP_CLR_WALK_PTR(inst);
679         writel(val, pmc_base + PMC_TRIGGERS);
680
681         val = readl(base + UTMIP_PMC_WAKEUP0);
682         val &= ~EVENT_INT_ENB;
683         writel(val, base + UTMIP_PMC_WAKEUP0);
684
685         /* Disable PMC master mode by clearing MASTER_EN */
686         val = readl(pmc_base + PMC_SLEEP_CFG);
687         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
688                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
689         writel(val, pmc_base + PMC_SLEEP_CFG);
690
691         val = readl(pmc_base + PMC_TRIGGERS);
692         val &= ~UTMIP_CAP_CFG(inst);
693         writel(val, pmc_base + PMC_TRIGGERS);
694
695         /* turn off pad detectors */
696         val = readl(pmc_base + PMC_USB_AO);
697         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
698         writel(val, pmc_base + PMC_USB_AO);
699
700         phy->remote_wakeup = false;
701         PHY_DBG("%s DISABLE_PMC inst = %d\n", __func__, inst);
702 }
703
704 bool utmi_phy_remotewake_detected(struct tegra_usb_phy *phy)
705 {
706         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
707         void __iomem *base = phy->regs;
708         unsigned  int inst = phy->inst;
709         u32 val;
710
711         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
712         val = readl(base + UTMIP_PMC_WAKEUP0);
713         if (val & EVENT_INT_ENB) {
714                 val = readl(pmc_base + UTMIP_UHSIC_STATUS);
715                 if (UTMIP_WAKE_ALARM(inst) & val) {
716                         val = readl(pmc_base + PMC_SLEEP_CFG);
717                         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
718                         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
719                         writel(val, pmc_base + PMC_SLEEP_CFG);
720
721                         val = readl(pmc_base + PMC_TRIGGERS);
722                         val |= UTMIP_CLR_WAKE_ALARM(inst) |
723                                 UTMIP_CLR_WALK_PTR(inst);
724                         writel(val, pmc_base + PMC_TRIGGERS);
725
726                         val = readl(base + UTMIP_PMC_WAKEUP0);
727                         val &= ~EVENT_INT_ENB;
728                         writel(val, base + UTMIP_PMC_WAKEUP0);
729                         phy->remote_wakeup = true;
730                         return true;
731                 }
732         }
733         return false;
734 }
735
736 static void utmi_phy_enable_trking_data(struct tegra_usb_phy *phy)
737 {
738         void __iomem *base = IO_ADDRESS(TEGRA_USB_BASE);
739         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
740         static bool init_done = false;
741         u32 val;
742
743         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
744
745         /* Should be done only once after system boot */
746         if (init_done)
747                 return;
748
749         clk_enable(phy->utmi_pad_clk);
750         /* Bias pad MASTER_ENABLE=1 */
751         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
752         val |= BIAS_MASTER_PROG_VAL;
753         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
754
755         /* Setting the tracking length time */
756         val = readl(base + UTMIP_BIAS_CFG1);
757         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
758         val |= UTMIP_BIAS_PDTRK_COUNT(5);
759         writel(val, base + UTMIP_BIAS_CFG1);
760
761         /* Bias PDTRK is Shared and MUST be done from USB1 ONLY, PD_TRK=0 */
762         val = readl(base + UTMIP_BIAS_CFG1);
763         val &= ~UTMIP_BIAS_PDTRK_POWERDOWN;
764         writel(val, base + UTMIP_BIAS_CFG1);
765
766         val = readl(base + UTMIP_BIAS_CFG1);
767         val |= UTMIP_BIAS_PDTRK_POWERUP;
768         writel(val, base + UTMIP_BIAS_CFG1);
769
770         /* Wait for 25usec */
771         udelay(25);
772
773         /* Bias pad MASTER_ENABLE=0 */
774         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
775         val &= ~BIAS_MASTER_PROG_VAL;
776         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
777
778         /* Wait for 1usec */
779         udelay(1);
780
781         /* Bias pad MASTER_ENABLE=1 */
782         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
783         val |= BIAS_MASTER_PROG_VAL;
784         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
785
786         /* Read RCTRL and TCTRL from UTMIP space */
787         val = readl(base + UTMIP_BIAS_STS0);
788         utmip_rctrl_val = ffz(UTMIP_RCTRL_VAL(val));
789         utmip_tctrl_val = ffz(UTMIP_TCTRL_VAL(val));
790
791         /* PD_TRK=1 */
792         val = readl(base + UTMIP_BIAS_CFG1);
793         val |= UTMIP_BIAS_PDTRK_POWERDOWN;
794         writel(val, base + UTMIP_BIAS_CFG1);
795
796         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
797         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
798         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
799         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
800         clk_disable(phy->utmi_pad_clk);
801         init_done = true;
802 }
803
804 static void utmip_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy)
805 {
806         unsigned long val;
807         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
808         unsigned  int inst = phy->inst;
809
810         /* power down UTMIP interfaces */
811         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
812         val |= UTMIP_PWR(inst);
813         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
814
815         /* setup sleep walk usb controller */
816         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
817                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
818                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
819                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
820         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
821
822         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
823         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
824         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
825         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
826
827         /* Turn over pad configuration to PMC */
828         val = readl(pmc_base + PMC_SLEEP_CFG);
829         val &= ~UTMIP_WAKE_VAL(inst, ~0);
830         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE) |
831                 UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
832                 UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst);
833         writel(val, pmc_base + PMC_SLEEP_CFG);
834         PHY_DBG("%s ENABLE_PMC inst = %d\n", __func__, inst);
835 }
836
837 static void utmip_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
838 {
839         unsigned long val;
840         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
841         unsigned  int inst = phy->inst;
842
843         /* Disable PMC master mode by clearing MASTER_EN */
844         val = readl(pmc_base + PMC_SLEEP_CFG);
845         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
846                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
847         writel(val, pmc_base + PMC_SLEEP_CFG);
848         mdelay(1);
849         PHY_DBG("%s DISABLE_PMC inst = %d\n", __func__, inst);
850 }
851
852 static void uhsic_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy)
853 {
854         unsigned long val;
855         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
856
857         /* turn on pad detectors for HSIC*/
858         val = readl(pmc_base + PMC_USB_AO);
859         val |= (HSIC_RESERVED_P0 | HSIC_STOBE_VAL_PD_P0 | HSIC_DATA_VAL_PD_P0);
860         writel(val, pmc_base + PMC_USB_AO);
861
862         /* enable pull downs on HSIC PMC */
863         val = UHSIC_STRB_RPD_A | UHSIC_DATA_RPD_A | UHSIC_STRB_RPD_B |
864                 UHSIC_DATA_RPD_B | UHSIC_STRB_RPD_C | UHSIC_DATA_RPD_C |
865                 UHSIC_STRB_RPD_D | UHSIC_DATA_RPD_D;
866         writel(val, pmc_base + UHSIC_SLEEPWALK_REG);
867
868         /* Turn over pad configuration to PMC */
869         val = readl(pmc_base + PMC_SLEEP_CFG);
870         val &= ~UHSIC_WAKE_VAL_P0(~0);
871         val |= UHSIC_WAKE_VAL_P0(WAKE_VAL_NONE) | UHSIC_MASTER_ENABLE_P0;
872         writel(val, pmc_base + PMC_SLEEP_CFG);
873 }
874
875 static void uhsic_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
876 {
877         unsigned long val;
878         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
879
880         /* turn on pad detectors for HSIC*/
881         val = readl(pmc_base + PMC_USB_AO);
882         val &= ~(HSIC_RESERVED_P0 | HSIC_STOBE_VAL_PD_P0 | HSIC_DATA_VAL_PD_P0);
883         writel(val, pmc_base + PMC_USB_AO);
884
885         /* Disable PMC master mode by clearing MASTER_EN */
886         val = readl(pmc_base + PMC_SLEEP_CFG);
887         val &= ~(UHSIC_MASTER_ENABLE_P0);
888         writel(val, pmc_base + PMC_SLEEP_CFG);
889         mdelay(1);
890 }
891
892 static void usb_phy_power_down_pmc(void)
893 {
894         unsigned long val;
895         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
896
897         /* power down all 3 UTMIP interfaces */
898         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
899         val |= UTMIP_PWR(0) | UTMIP_PWR(1) | UTMIP_PWR(2);
900         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
901
902         /* turn on pad detectors */
903         writel(PMC_POWER_DOWN_MASK, pmc_base + PMC_USB_AO);
904
905         /* setup sleep walk fl all 3 usb controllers */
906         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
907                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
908                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
909                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
910         writel(val, pmc_base + PMC_SLEEPWALK_REG(0));
911         writel(val, pmc_base + PMC_SLEEPWALK_REG(1));
912         writel(val, pmc_base + PMC_SLEEPWALK_REG(2));
913
914         /* enable pull downs on HSIC PMC */
915         val = UHSIC_STRB_RPD_A | UHSIC_DATA_RPD_A | UHSIC_STRB_RPD_B |
916                 UHSIC_DATA_RPD_B | UHSIC_STRB_RPD_C | UHSIC_DATA_RPD_C |
917                 UHSIC_STRB_RPD_D | UHSIC_DATA_RPD_D;
918         writel(val, pmc_base + UHSIC_SLEEPWALK_REG);
919
920         /* Turn over pad configuration to PMC */
921         val = readl(pmc_base + PMC_SLEEP_CFG);
922         val &= ~UTMIP_WAKE_VAL(0, ~0);
923         val &= ~UTMIP_WAKE_VAL(1, ~0);
924         val &= ~UTMIP_WAKE_VAL(2, ~0);
925         val &= ~UHSIC_WAKE_VAL_P0(~0);
926         val |= UTMIP_WAKE_VAL(0, WAKE_VAL_NONE) | UHSIC_WAKE_VAL_P0(WAKE_VAL_NONE) |
927         UTMIP_WAKE_VAL(1, WAKE_VAL_NONE) | UTMIP_WAKE_VAL(2, WAKE_VAL_NONE) |
928         UTMIP_RCTRL_USE_PMC(0) | UTMIP_RCTRL_USE_PMC(1) | UTMIP_RCTRL_USE_PMC(2) |
929         UTMIP_TCTRL_USE_PMC(0) | UTMIP_TCTRL_USE_PMC(1) | UTMIP_TCTRL_USE_PMC(2) |
930         UTMIP_FSLS_USE_PMC(0) | UTMIP_FSLS_USE_PMC(1) | UTMIP_FSLS_USE_PMC(2) |
931         UTMIP_MASTER_ENABLE(0) | UTMIP_MASTER_ENABLE(1) | UTMIP_MASTER_ENABLE(2) |
932         UHSIC_MASTER_ENABLE_P0;
933         writel(val, pmc_base + PMC_SLEEP_CFG);
934 }
935
936 static int usb_phy_bringup_host_controller(struct tegra_usb_phy *phy)
937 {
938         unsigned long val;
939         void __iomem *base = phy->regs;
940
941         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
942         PHY_DBG("[%d] USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n", __LINE__,
943                 readl(base + USB_USBSTS), readl(base + USB_PORTSC),
944                                                         phy->port_speed);
945
946         /* Device is plugged in when system is in LP0 */
947         /* Bring up the controller from LP0*/
948         val = readl(base + USB_USBCMD);
949         val |= USB_CMD_RESET;
950         writel(val, base + USB_USBCMD);
951
952         if (usb_phy_reg_status_wait(base + USB_USBCMD,
953                 USB_CMD_RESET, 0, 2500) < 0) {
954                 pr_err("%s: timeout waiting for reset\n", __func__);
955         }
956
957         val = readl(base + USB_USBMODE);
958         val &= ~USB_USBMODE_MASK;
959         val |= USB_USBMODE_HOST;
960         writel(val, base + USB_USBMODE);
961
962         val = readl(base + HOSTPC1_DEVLC);
963         val &= ~HOSTPC1_DEVLC_PTS(~0);
964         val |= HOSTPC1_DEVLC_STS;
965         writel(val, base + HOSTPC1_DEVLC);
966
967         /* Enable Port Power */
968         val = readl(base + USB_PORTSC);
969         val |= USB_PORTSC_PP;
970         writel(val, base + USB_PORTSC);
971         udelay(10);
972
973         /* Check if the phy resume from LP0. When the phy resume from LP0
974          * USB register will be reset.to zero */
975         if (!readl(base + USB_ASYNCLISTADDR)) {
976                 /* Program the field PTC based on the saved speed mode */
977                 val = readl(base + USB_PORTSC);
978                 val &= ~USB_PORTSC_PTC(~0);
979                 if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH)
980                         val |= USB_PORTSC_PTC(5);
981                 else if (phy->port_speed == USB_PHY_PORT_SPEED_FULL)
982                         val |= USB_PORTSC_PTC(6);
983                 else if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
984                         val |= USB_PORTSC_PTC(7);
985                 writel(val, base + USB_PORTSC);
986                 udelay(10);
987
988                 /* Disable test mode by setting PTC field to NORMAL_OP */
989                 val = readl(base + USB_PORTSC);
990                 val &= ~USB_PORTSC_PTC(~0);
991                 writel(val, base + USB_PORTSC);
992                 udelay(10);
993         }
994
995         /* Poll until CCS is enabled */
996         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
997                                                  USB_PORTSC_CCS, 2000)) {
998                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
999         }
1000
1001         /* Poll until PE is enabled */
1002         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_PE,
1003                                                  USB_PORTSC_PE, 2000)) {
1004                 pr_err("%s: timeout waiting for USB_PORTSC_PE\n", __func__);
1005         }
1006
1007         /* Clear the PCI status, to avoid an interrupt taken upon resume */
1008         val = readl(base + USB_USBSTS);
1009         val |= USB_USBSTS_PCI;
1010         writel(val, base + USB_USBSTS);
1011
1012         if (!phy->remote_wakeup) {
1013                 /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
1014                 val = readl(base + USB_PORTSC);
1015                 if ((val & USB_PORTSC_PP) && (val & USB_PORTSC_PE)) {
1016                         val |= USB_PORTSC_SUSP;
1017                         writel(val, base + USB_PORTSC);
1018                         /* Need a 4ms delay before the controller goes to suspend */
1019                         mdelay(4);
1020
1021                         /* Wait until port suspend completes */
1022                         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_SUSP,
1023                                                          USB_PORTSC_SUSP, 1000)) {
1024                                 pr_err("%s: timeout waiting for PORT_SUSPEND\n",
1025                                                                         __func__);
1026                         }
1027                 }
1028         }
1029         PHY_DBG("[%d] USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n", __LINE__,
1030                 readl(base + USB_USBSTS), readl(base + USB_PORTSC),
1031                                                         phy->port_speed);
1032
1033         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1034                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1035         return 0;
1036 }
1037
1038 static void usb_phy_wait_for_sof(struct tegra_usb_phy *phy)
1039 {
1040         unsigned long val;
1041         void __iomem *base = phy->regs;
1042
1043         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1044
1045         val = readl(base + USB_USBSTS);
1046         writel(val, base + USB_USBSTS);
1047         udelay(20);
1048         /* wait for two SOFs */
1049         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1050                 USB_USBSTS_SRI, 2500))
1051                 pr_err("%s: timeout waiting for SOF\n", __func__);
1052
1053         val = readl(base + USB_USBSTS);
1054         writel(val, base + USB_USBSTS);
1055         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI, 0, 2500))
1056                 pr_err("%s: timeout waiting for SOF\n", __func__);
1057
1058         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1059                         USB_USBSTS_SRI, 2500))
1060                 pr_err("%s: timeout waiting for SOF\n", __func__);
1061
1062         udelay(20);
1063 }
1064
1065 static unsigned int utmi_phy_xcvr_setup_value(struct tegra_usb_phy *phy)
1066 {
1067         struct tegra_utmi_config *cfg = &phy->pdata->u_cfg.utmi;
1068         signed long val;
1069
1070         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1071
1072         if (cfg->xcvr_use_fuses) {
1073                 val = FUSE_USB_CALIB_XCVR_SETUP(
1074                                 tegra_fuse_readl(FUSE_USB_CALIB_0));
1075                 if (cfg->xcvr_setup_offset <= UTMIP_XCVR_MAX_OFFSET)
1076                         val = val + cfg->xcvr_setup_offset;
1077
1078                 if (val > UTMIP_XCVR_SETUP_MAX_VALUE) {
1079                         val = UTMIP_XCVR_SETUP_MAX_VALUE;
1080                         pr_info("%s: reset XCVR_SETUP to max value\n",
1081                                  __func__);
1082                 } else if (val < UTMIP_XCVR_SETUP_MIN_VALUE) {
1083                         val = UTMIP_XCVR_SETUP_MIN_VALUE;
1084                         pr_info("%s: reset XCVR_SETUP to min value\n",
1085                                  __func__);
1086                 }
1087         } else {
1088                 val = cfg->xcvr_setup;
1089         }
1090
1091         return (unsigned int) val;
1092 }
1093
1094 static int utmi_phy_open(struct tegra_usb_phy *phy)
1095 {
1096         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1097         unsigned long parent_rate, val;
1098         int i;
1099
1100         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1101
1102         phy->utmi_pad_clk = clk_get_sys("utmip-pad", NULL);
1103         if (IS_ERR(phy->utmi_pad_clk)) {
1104                 pr_err("%s: can't get utmip pad clock\n", __func__);
1105                 return PTR_ERR(phy->utmi_pad_clk);
1106         }
1107
1108         phy->utmi_xcvr_setup = utmi_phy_xcvr_setup_value(phy);
1109
1110         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
1111         for (i = 0; i < ARRAY_SIZE(utmip_freq_table); i++) {
1112                 if (utmip_freq_table[i].freq == parent_rate) {
1113                         phy->freq = &utmip_freq_table[i];
1114                         break;
1115                 }
1116         }
1117         if (!phy->freq) {
1118                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
1119                 return -EINVAL;
1120         }
1121
1122         /* Power-up the VBUS detector for UTMIP PHY */
1123         val = readl(pmc_base + PMC_USB_AO);
1124         val &= ~(PMC_USB_AO_VBUS_WAKEUP_PD_P0 | PMC_USB_AO_ID_PD_P0);
1125         writel((val | PMC_USB_AO_PD_P2), (pmc_base + PMC_USB_AO));
1126
1127         utmip_powerup_pmc_wake_detect(phy);
1128
1129         return 0;
1130 }
1131
1132 static void utmi_phy_close(struct tegra_usb_phy *phy)
1133 {
1134         unsigned long val;
1135         void __iomem *base = phy->regs;
1136
1137         DBG("%s inst:[%d]\n", __func__, phy->inst);
1138
1139         /* Disable PHY clock valid interrupts while going into suspend*/
1140         if (phy->pdata->u_data.host.hot_plug) {
1141                 val = readl(base + USB_SUSP_CTRL);
1142                 val &= ~USB_PHY_CLK_VALID_INT_ENB;
1143                 writel(val, base + USB_SUSP_CTRL);
1144         }
1145
1146         val = readl(base + USB_PORTSC);
1147         val |= USB_PORTSC_WKCN;
1148         writel(val, base + USB_PORTSC);
1149
1150         clk_put(phy->utmi_pad_clk);
1151 }
1152
1153 static int utmi_phy_pad_power_on(struct tegra_usb_phy *phy)
1154 {
1155         unsigned long val, flags;
1156         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1157
1158         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1159
1160         clk_enable(phy->utmi_pad_clk);
1161
1162         spin_lock_irqsave(&utmip_pad_lock, flags);
1163         utmip_pad_count++;
1164
1165         val = readl(pad_base + UTMIP_BIAS_CFG0);
1166         val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
1167         val |= UTMIP_HSSQUELCH_LEVEL(0x2) | UTMIP_HSDISCON_LEVEL(0x1) |
1168                 UTMIP_HSDISCON_LEVEL_MSB;
1169         writel(val, pad_base + UTMIP_BIAS_CFG0);
1170
1171         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1172
1173         clk_disable(phy->utmi_pad_clk);
1174
1175         return 0;
1176 }
1177
1178 static int utmi_phy_pad_power_off(struct tegra_usb_phy *phy)
1179 {
1180         unsigned long val, flags;
1181         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1182
1183         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1184
1185         clk_enable(phy->utmi_pad_clk);
1186         spin_lock_irqsave(&utmip_pad_lock, flags);
1187
1188         if (!utmip_pad_count) {
1189                 pr_err("%s: utmip pad already powered off\n", __func__);
1190                 goto out;
1191         }
1192         if (--utmip_pad_count == 0) {
1193                 val = readl(pad_base + UTMIP_BIAS_CFG0);
1194                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
1195                 val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) | UTMIP_HSDISCON_LEVEL(~0) |
1196                         UTMIP_HSDISCON_LEVEL_MSB);
1197                 writel(val, pad_base + UTMIP_BIAS_CFG0);
1198         }
1199 out:
1200         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1201         clk_disable(phy->utmi_pad_clk);
1202
1203         return 0;
1204 }
1205
1206 static int utmi_phy_irq(struct tegra_usb_phy *phy)
1207 {
1208         void __iomem *base = phy->regs;
1209         unsigned long val = 0;
1210
1211         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1212         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1213                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1214         DBG("USB_USBMODE[0x%x] USB_USBCMD[0x%x]\n",
1215                         readl(base + USB_USBMODE), readl(base + USB_USBCMD));
1216
1217         usb_phy_fence_read(phy);
1218         /* check if there is any remote wake event */
1219         if (utmi_phy_remotewake_detected(phy))
1220                 pr_info("%s: utmip remote wake detected\n", __func__);
1221
1222         if (phy->pdata->u_data.host.hot_plug) {
1223                 val = readl(base + USB_SUSP_CTRL);
1224                 if ((val  & USB_PHY_CLK_VALID_INT_STS)) {
1225                         val &= ~USB_PHY_CLK_VALID_INT_ENB |
1226                                         USB_PHY_CLK_VALID_INT_STS;
1227                         writel(val , (base + USB_SUSP_CTRL));
1228                         pr_info("%s: usb device plugged-in\n", __func__);
1229                         val = readl(base + USB_USBSTS);
1230                         if (!(val  & USB_USBSTS_PCI))
1231                                 return IRQ_NONE;
1232                         val = readl(base + USB_PORTSC);
1233                         val &= ~(USB_PORTSC_WKCN | USB_PORTSC_RWC_BITS);
1234                         writel(val , (base + USB_PORTSC));
1235                 }
1236         }
1237
1238         return IRQ_HANDLED;
1239 }
1240
1241 static void utmi_phy_enable_obs_bus(struct tegra_usb_phy *phy)
1242 {
1243         unsigned long val;
1244         void __iomem *base = phy->regs;
1245
1246         /* (2LS WAR)is not required for LS and FS devices and is only for HS */
1247         if ((phy->port_speed == USB_PHY_PORT_SPEED_LOW) ||
1248                 (phy->port_speed == USB_PHY_PORT_SPEED_FULL)) {
1249                 /* do not enable the OBS bus */
1250                 val = readl(base + UTMIP_MISC_CFG0);
1251                 val &= ~(UTMIP_DPDM_OBSERVE_SEL(~0));
1252                 writel(val, base + UTMIP_MISC_CFG0);
1253                 DBG("%s(%d) Disable OBS bus\n", __func__, __LINE__);
1254                 return;
1255         }
1256         /* Force DP/DM pulldown active for Host mode */
1257         val = readl(base + UTMIP_MISC_CFG0);
1258         val |= FORCE_PULLDN_DM | FORCE_PULLDN_DP |
1259                         COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS;
1260         writel(val, base + UTMIP_MISC_CFG0);
1261         val = readl(base + UTMIP_MISC_CFG0);
1262         val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1263         if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
1264                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
1265         else
1266                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
1267         writel(val, base + UTMIP_MISC_CFG0);
1268         udelay(1);
1269
1270         val = readl(base + UTMIP_MISC_CFG0);
1271         val |= UTMIP_DPDM_OBSERVE;
1272         writel(val, base + UTMIP_MISC_CFG0);
1273         udelay(10);
1274         DBG("%s(%d) Enable OBS bus\n", __func__, __LINE__);
1275         PHY_DBG("ENABLE_OBS_BUS\n");
1276 }
1277
1278 static int utmi_phy_disable_obs_bus(struct tegra_usb_phy *phy)
1279 {
1280         unsigned long val;
1281         void __iomem *base = phy->regs;
1282
1283         /* check if OBS bus is already enabled */
1284         val = readl(base + UTMIP_MISC_CFG0);
1285         if (val & UTMIP_DPDM_OBSERVE) {
1286                 PHY_DBG("DISABLE_OBS_BUS\n");
1287                 /* Change the UTMIP OBS bus to drive SE0 */
1288                 val = readl(base + UTMIP_MISC_CFG0);
1289                 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1290                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_SE0;
1291                 writel(val, base + UTMIP_MISC_CFG0);
1292
1293                 /* Wait for 3us(2 LS bit times) */
1294                 udelay(3);
1295
1296                 /* Release UTMIP OBS bus */
1297                 val = readl(base + UTMIP_MISC_CFG0);
1298                 val &= ~UTMIP_DPDM_OBSERVE;
1299                 writel(val, base + UTMIP_MISC_CFG0);
1300
1301                 /* Release DP/DM pulldown for Host mode */
1302                 val = readl(base + UTMIP_MISC_CFG0);
1303                 val &= ~(FORCE_PULLDN_DM | FORCE_PULLDN_DP |
1304                                 COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS);
1305                 writel(val, base + UTMIP_MISC_CFG0);
1306
1307                 val = readl(base + USB_USBCMD);
1308                 val |= USB_USBCMD_RS;
1309                 writel(val, base + USB_USBCMD);
1310                 if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
1311                                                          USB_USBCMD_RS, 2000)) {
1312                         pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
1313                         return -ETIMEDOUT;
1314                 }
1315         }
1316         return 0;
1317 }
1318
1319 static int utmi_phy_post_resume(struct tegra_usb_phy *phy)
1320 {
1321         unsigned long val;
1322         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1323         unsigned  int inst = phy->inst;
1324
1325         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1326         val = readl(pmc_base + PMC_SLEEP_CFG);
1327         /* if PMC is not disabled by now then disable it */
1328         if (val & UTMIP_MASTER_ENABLE(inst)) {
1329                 utmip_phy_disable_pmc_bus_ctrl(phy);
1330         }
1331
1332         utmi_phy_disable_obs_bus(phy);
1333
1334         return 0;
1335 }
1336
1337 static int utmi_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1338 {
1339         unsigned long val;
1340         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1341         void __iomem *base = phy->regs;
1342         unsigned  int inst = phy->inst;
1343
1344         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1345
1346         val = (readl(base + HOSTPC1_DEVLC) >> 25) &
1347                         HOSTPC1_DEVLC_PSPD_MASK;
1348         if (val == USB_PHY_PORT_SPEED_HIGH) {
1349                 /* Disable interrupts */
1350                 writel(0, base + USB_USBINTR);
1351                 /* Clear the run bit to stop SOFs - 2LS WAR */
1352                 val = readl(base + USB_USBCMD);
1353                 val &= ~USB_USBCMD_RS;
1354                 writel(val, base + USB_USBCMD);
1355         }
1356
1357         val = readl(pmc_base + PMC_SLEEP_CFG);
1358         if (val & UTMIP_MASTER_ENABLE(inst)) {
1359                 if (!remote_wakeup)
1360                         utmip_phy_disable_pmc_bus_ctrl(phy);
1361         } else {
1362                 utmi_phy_enable_obs_bus(phy);
1363         }
1364
1365         return 0;
1366 }
1367
1368 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
1369 {
1370         unsigned long val;
1371         void __iomem *base = phy->regs;
1372
1373         PHY_DBG("%s(%d) inst:[%d] BEGIN\n", __func__, __LINE__, phy->inst);
1374         if (!phy->phy_clk_on) {
1375                 PHY_DBG("%s(%d) inst:[%d] phy clk is already off\n",
1376                                         __func__, __LINE__, phy->inst);
1377                 return 0;
1378         }
1379
1380         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1381                 utmip_powerdown_pmc_wake_detect(phy);
1382
1383                 val = readl(base + USB_SUSP_CTRL);
1384                 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
1385                 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
1386                 writel(val, base + USB_SUSP_CTRL);
1387
1388                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1389                 val |= UTMIP_PD_CHRG;
1390                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1391         } else {
1392                 utmip_setup_pmc_wake_detect(phy);
1393         }
1394
1395         if (!phy->pdata->u_data.host.hot_plug) {
1396                 val = readl(base + UTMIP_XCVR_CFG0);
1397                 val |= (UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
1398                          UTMIP_FORCE_PDZI_POWERDOWN);
1399                 writel(val, base + UTMIP_XCVR_CFG0);
1400         }
1401
1402         val = readl(base + UTMIP_XCVR_CFG1);
1403         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1404                    UTMIP_FORCE_PDDR_POWERDOWN;
1405         writel(val, base + UTMIP_XCVR_CFG1);
1406
1407         val = readl(base + UTMIP_BIAS_CFG1);
1408         val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
1409         writel(val, base + UTMIP_BIAS_CFG1);
1410
1411         utmi_phy_pad_power_off(phy);
1412
1413         phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
1414                         HOSTPC1_DEVLC_PSPD_MASK;
1415
1416         if (phy->pdata->u_data.host.hot_plug) {
1417                 bool enable_hotplug = true;
1418                 /* if it is OTG port then make sure to enable hot-plug feature
1419                    only if host adaptor is connected, i.e id is low */
1420                 if (phy->pdata->port_otg) {
1421                         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1422                         enable_hotplug = (val & USB_ID_STATUS) ? false : true;
1423                 }
1424                 if (enable_hotplug) {
1425                         val = readl(base + USB_PORTSC);
1426                         val |= USB_PORTSC_WKCN;
1427                         writel(val, base + USB_PORTSC);
1428
1429                         val = readl(base + USB_SUSP_CTRL);
1430                         val |= USB_PHY_CLK_VALID_INT_ENB;
1431                         writel(val, base + USB_SUSP_CTRL);
1432                 } else {
1433                         /* Disable PHY clock valid interrupts while going into suspend*/
1434                         val = readl(base + USB_SUSP_CTRL);
1435                         val &= ~USB_PHY_CLK_VALID_INT_ENB;
1436                         writel(val, base + USB_SUSP_CTRL);
1437                 }
1438         }
1439
1440         val = readl(base + HOSTPC1_DEVLC);
1441         val |= HOSTPC1_DEVLC_PHCD;
1442         writel(val, base + HOSTPC1_DEVLC);
1443
1444         if (!phy->pdata->u_data.host.hot_plug) {
1445                 val = readl(base + USB_SUSP_CTRL);
1446                 val |= UTMIP_RESET;
1447                 writel(val, base + USB_SUSP_CTRL);
1448         }
1449
1450         phy->phy_clk_on = false;
1451         phy->hw_accessible = false;
1452
1453         PHY_DBG("%s(%d) inst:[%d] END\n", __func__, __LINE__, phy->inst);
1454
1455         return 0;
1456 }
1457
1458
1459 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
1460 {
1461         unsigned long val;
1462         void __iomem *base = phy->regs;
1463         struct tegra_utmi_config *config = &phy->pdata->u_cfg.utmi;
1464
1465         PHY_DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1466         if (phy->phy_clk_on) {
1467                 PHY_DBG("%s(%d) inst:[%d] phy clk is already On\n",
1468                                         __func__, __LINE__, phy->inst);
1469                 return 0;
1470         }
1471         val = readl(base + USB_SUSP_CTRL);
1472         val |= UTMIP_RESET;
1473         writel(val, base + USB_SUSP_CTRL);
1474
1475         val = readl(base + UTMIP_TX_CFG0);
1476         val |= UTMIP_FS_PREABMLE_J;
1477         writel(val, base + UTMIP_TX_CFG0);
1478
1479         val = readl(base + UTMIP_HSRX_CFG0);
1480         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
1481         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
1482         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
1483         writel(val, base + UTMIP_HSRX_CFG0);
1484
1485         val = readl(base + UTMIP_HSRX_CFG1);
1486         val &= ~UTMIP_HS_SYNC_START_DLY(~0);
1487         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
1488         writel(val, base + UTMIP_HSRX_CFG1);
1489
1490         val = readl(base + UTMIP_DEBOUNCE_CFG0);
1491         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
1492         val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
1493         writel(val, base + UTMIP_DEBOUNCE_CFG0);
1494
1495         val = readl(base + UTMIP_MISC_CFG0);
1496         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
1497         writel(val, base + UTMIP_MISC_CFG0);
1498
1499         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1500                 val = readl(base + USB_SUSP_CTRL);
1501                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
1502                 writel(val, base + USB_SUSP_CTRL);
1503
1504                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1505                 val &= ~UTMIP_PD_CHRG;
1506                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1507         } else {
1508                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1509                 val |= UTMIP_PD_CHRG;
1510                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1511         }
1512
1513         utmi_phy_pad_power_on(phy);
1514
1515         val = readl(base + UTMIP_XCVR_CFG0);
1516         val &= ~(UTMIP_XCVR_LSBIAS_SEL | UTMIP_FORCE_PD_POWERDOWN |
1517                  UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN |
1518                  UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_LSFSLEW(~0) |
1519                  UTMIP_XCVR_LSRSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
1520         val |= UTMIP_XCVR_SETUP(phy->utmi_xcvr_setup);
1521         val |= UTMIP_XCVR_SETUP_MSB(XCVR_SETUP_MSB_CALIB(phy->utmi_xcvr_setup));
1522         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
1523         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
1524         val |= UTMIP_XCVR_HSSLEW_MSB(0x8);
1525         writel(val, base + UTMIP_XCVR_CFG0);
1526
1527         val = readl(base + UTMIP_XCVR_CFG1);
1528         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1529                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
1530         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
1531         writel(val, base + UTMIP_XCVR_CFG1);
1532
1533         val = readl(base + UTMIP_BIAS_CFG1);
1534         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
1535         val |= UTMIP_BIAS_PDTRK_COUNT(phy->freq->pdtrk_count);
1536         writel(val, base + UTMIP_BIAS_CFG1);
1537
1538         val = readl(base + UTMIP_SPARE_CFG0);
1539         val &= ~FUSE_SETUP_SEL;
1540         val |= FUSE_ATERM_SEL;
1541         writel(val, base + UTMIP_SPARE_CFG0);
1542
1543         val = readl(base + USB_SUSP_CTRL);
1544         val |= UTMIP_PHY_ENABLE;
1545         writel(val, base + USB_SUSP_CTRL);
1546
1547         val = readl(base + USB_SUSP_CTRL);
1548         val &= ~UTMIP_RESET;
1549         writel(val, base + USB_SUSP_CTRL);
1550
1551         val = readl(base + HOSTPC1_DEVLC);
1552         val &= ~HOSTPC1_DEVLC_PHCD;
1553         writel(val, base + HOSTPC1_DEVLC);
1554
1555         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1556                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500))
1557                 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
1558
1559         utmi_phy_enable_trking_data(phy);
1560
1561         if (phy->inst == 2)
1562                 writel(0, base + ICUSB_CTRL);
1563
1564         val = readl(base + USB_USBMODE);
1565         val &= ~USB_USBMODE_MASK;
1566         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST)
1567                 val |= USB_USBMODE_HOST;
1568         else
1569                 val |= USB_USBMODE_DEVICE;
1570         writel(val, base + USB_USBMODE);
1571
1572         val = readl(base + HOSTPC1_DEVLC);
1573         val &= ~HOSTPC1_DEVLC_PTS(~0);
1574         val |= HOSTPC1_DEVLC_STS;
1575         writel(val, base + HOSTPC1_DEVLC);
1576
1577         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE)
1578                 utmip_powerup_pmc_wake_detect(phy);
1579         phy->phy_clk_on = true;
1580         phy->hw_accessible = true;
1581         PHY_DBG("%s(%d) End inst:[%d]\n", __func__, __LINE__, phy->inst);
1582         return 0;
1583 }
1584
1585 static void utmi_phy_restore_start(struct tegra_usb_phy *phy)
1586 {
1587         unsigned long val;
1588         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1589         int inst = phy->inst;
1590
1591         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1592         val = readl(pmc_base + UTMIP_UHSIC_STATUS);
1593         /* check whether we wake up from the remote resume */
1594         if (UTMIP_WALK_PTR_VAL(inst) & val) {
1595                 phy->remote_wakeup = true;
1596         } else {
1597                 if (!((UTMIP_USBON_VAL(phy->inst) |
1598                         UTMIP_USBOP_VAL(phy->inst)) & val)) {
1599                                 utmip_phy_disable_pmc_bus_ctrl(phy);
1600                 }
1601         }
1602         utmi_phy_enable_obs_bus(phy);
1603 }
1604
1605 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
1606 {
1607         unsigned long val;
1608         void __iomem *base = phy->regs;
1609         int wait_time_us = 25000; /* FPR should be set by this time */
1610
1611         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1612         /* check whether we wake up from the remote resume */
1613         if (phy->remote_wakeup) {
1614                 /* wait until SUSPEND and RESUME bit is cleared on remote resume */
1615                 do {
1616                         val = readl(base + USB_PORTSC);
1617                         udelay(1);
1618                         if (wait_time_us == 0) {
1619                                 PHY_DBG("%s PMC REMOTE WAKEUP FPR timeout val = 0x%x instance = %d\n", __func__, val, phy->inst);
1620                                 utmip_phy_disable_pmc_bus_ctrl(phy);
1621                                 utmi_phy_post_resume(phy);
1622                                 return;
1623                         }
1624                         wait_time_us--;
1625                 } while (val & (USB_PORTSC_RESUME | USB_PORTSC_SUSP));
1626
1627                 /* wait for 25 ms to port resume complete */
1628                 msleep(25);
1629                 /* disable PMC master control */
1630                 utmip_phy_disable_pmc_bus_ctrl(phy);
1631
1632                 /* Clear PCI and SRI bits to avoid an interrupt upon resume */
1633                 val = readl(base + USB_USBSTS);
1634                 writel(val, base + USB_USBSTS);
1635                 /* wait to avoid SOF if there is any */
1636                 if (usb_phy_reg_status_wait(base + USB_USBSTS,
1637                         USB_USBSTS_SRI, USB_USBSTS_SRI, 2500) < 0) {
1638                         pr_err("%s: timeout waiting for SOF\n", __func__);
1639                 }
1640                 utmi_phy_post_resume(phy);
1641         }
1642 }
1643
1644 static int utmi_phy_resume(struct tegra_usb_phy *phy)
1645 {
1646         int status = 0;
1647         unsigned long val;
1648         void __iomem *base = phy->regs;
1649
1650         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1651         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) {
1652                 if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
1653                         utmi_phy_restore_start(phy);
1654                         usb_phy_bringup_host_controller(phy);
1655                         utmi_phy_restore_end(phy);
1656                 } else {
1657                         /* device is plugged in when system is in LP0 */
1658                         /* bring up the controller from LP0*/
1659                         val = readl(base + USB_USBCMD);
1660                         val |= USB_CMD_RESET;
1661                         writel(val, base + USB_USBCMD);
1662
1663                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1664                                 USB_CMD_RESET, 0, 2500) < 0) {
1665                                 pr_err("%s: timeout waiting for reset\n", __func__);
1666                         }
1667
1668                         val = readl(base + USB_USBMODE);
1669                         val &= ~USB_USBMODE_MASK;
1670                         val |= USB_USBMODE_HOST;
1671                         writel(val, base + USB_USBMODE);
1672
1673                         val = readl(base + HOSTPC1_DEVLC);
1674                         val &= ~HOSTPC1_DEVLC_PTS(~0);
1675                         val |= HOSTPC1_DEVLC_STS;
1676                         writel(val, base + HOSTPC1_DEVLC);
1677
1678                         writel(USB_USBCMD_RS, base + USB_USBCMD);
1679
1680                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1681                                 USB_USBCMD_RS, USB_USBCMD_RS, 2500) < 0) {
1682                                 pr_err("%s: timeout waiting for run bit\n", __func__);
1683                         }
1684
1685                         /* Enable Port Power */
1686                         val = readl(base + USB_PORTSC);
1687                         val |= USB_PORTSC_PP;
1688                         writel(val, base + USB_PORTSC);
1689                         udelay(10);
1690
1691                         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1692                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1693                 }
1694         }
1695
1696         return status;
1697 }
1698
1699 bool utmi_phy_charger_detect(struct tegra_usb_phy *phy)
1700 {
1701         unsigned long val;
1702         void __iomem *base = phy->regs;
1703         bool status;
1704
1705         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1706         if (phy->pdata->op_mode != TEGRA_USB_OPMODE_DEVICE) {
1707                 /* Charger detection is not there for ULPI
1708                  * return Charger not available */
1709                 return false;
1710         }
1711
1712         /* Enable charger detection logic */
1713         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1714         val |= UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN;
1715         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1716
1717         /* Source should be on for 100 ms as per USB charging spec */
1718         msleep(TDP_SRC_ON_MS);
1719
1720         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1721         /* If charger is not connected disable the interrupt */
1722         val &= ~VDAT_DET_INT_EN;
1723         val |= VDAT_DET_CHG_DET;
1724         writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
1725
1726         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1727         if (val & VDAT_DET_STS)
1728                 status = true;
1729         else
1730                 status = false;
1731
1732         /* Disable charger detection logic */
1733         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1734         val &= ~(UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN);
1735         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1736
1737         /* Delay of 40 ms before we pull the D+ as per battery charger spec */
1738         msleep(TDPSRC_CON_MS);
1739
1740         return status;
1741 }
1742
1743 static int uhsic_phy_open(struct tegra_usb_phy *phy)
1744 {
1745         unsigned long parent_rate;
1746         int i;
1747
1748         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1749         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
1750         for (i = 0; i < ARRAY_SIZE(uhsic_freq_table); i++) {
1751                 if (uhsic_freq_table[i].freq == parent_rate) {
1752                         phy->freq = &uhsic_freq_table[i];
1753                         break;
1754                 }
1755         }
1756         if (!phy->freq) {
1757                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
1758                 return -EINVAL;
1759         }
1760
1761         utmip_powerup_pmc_wake_detect(phy);
1762
1763         return 0;
1764 }
1765
1766 static int uhsic_phy_irq(struct tegra_usb_phy *phy)
1767 {
1768         usb_phy_fence_read(phy);
1769         return IRQ_HANDLED;
1770 }
1771
1772 static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
1773 {
1774         unsigned long val;
1775         void __iomem *base = phy->regs;
1776         struct tegra_hsic_config *config = &phy->pdata->u_cfg.hsic;
1777
1778         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1779
1780         utmip_powerup_pmc_wake_detect(phy);
1781
1782         if (phy->phy_clk_on) {
1783                 DBG("%s(%d) inst:[%d] phy clk is already On\n",
1784                                         __func__, __LINE__, phy->inst);
1785                 return 0;
1786         }
1787
1788         val = readl(base + UHSIC_PADS_CFG1);
1789         val &= ~(UHSIC_PD_BG | UHSIC_PD_TX | UHSIC_PD_TRK | UHSIC_PD_RX |
1790                         UHSIC_PD_ZI | UHSIC_RPD_DATA | UHSIC_RPD_STROBE);
1791         val |= UHSIC_RX_SEL;
1792         writel(val, base + UHSIC_PADS_CFG1);
1793         udelay(2);
1794
1795         val = readl(base + USB_SUSP_CTRL);
1796         val |= UHSIC_RESET;
1797         writel(val, base + USB_SUSP_CTRL);
1798         udelay(30);
1799
1800         val = readl(base + USB_SUSP_CTRL);
1801         val |= UHSIC_PHY_ENABLE;
1802         writel(val, base + USB_SUSP_CTRL);
1803
1804         val = readl(base + UHSIC_HSRX_CFG0);
1805         val |= UHSIC_IDLE_WAIT(config->idle_wait_delay);
1806         val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(config->elastic_underrun_limit);
1807         val |= UHSIC_ELASTIC_OVERRUN_LIMIT(config->elastic_overrun_limit);
1808         writel(val, base + UHSIC_HSRX_CFG0);
1809
1810         val = readl(base + UHSIC_HSRX_CFG1);
1811         val |= UHSIC_HS_SYNC_START_DLY(config->sync_start_delay);
1812         writel(val, base + UHSIC_HSRX_CFG1);
1813
1814         /* WAR HSIC TX */
1815         val = readl(base + UHSIC_TX_CFG0);
1816         val &= ~UHSIC_HS_READY_WAIT_FOR_VALID;
1817         writel(val, base + UHSIC_TX_CFG0);
1818
1819         val = readl(base + UHSIC_MISC_CFG0);
1820         val |= UHSIC_SUSPEND_EXIT_ON_EDGE;
1821         /* Disable generic bus reset, to allow AP30 specific bus reset*/
1822         val |= UHSIC_DISABLE_BUSRESET;
1823         writel(val, base + UHSIC_MISC_CFG0);
1824
1825         val = readl(base + UHSIC_MISC_CFG1);
1826         val |= UHSIC_PLLU_STABLE_COUNT(phy->freq->stable_count);
1827         writel(val, base + UHSIC_MISC_CFG1);
1828
1829         val = readl(base + UHSIC_PLL_CFG1);
1830         val |= UHSIC_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
1831         val |= UHSIC_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count);
1832         writel(val, base + UHSIC_PLL_CFG1);
1833
1834         val = readl(base + USB_SUSP_CTRL);
1835         val &= ~(UHSIC_RESET);
1836         writel(val, base + USB_SUSP_CTRL);
1837         udelay(2);
1838
1839         val = readl(base + USB_USBMODE);
1840         val |= USB_USBMODE_HOST;
1841         writel(val, base + USB_USBMODE);
1842
1843         /* Change the USB controller PHY type to HSIC */
1844         val = readl(base + HOSTPC1_DEVLC);
1845         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
1846         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
1847         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
1848         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
1849         writel(val, base + HOSTPC1_DEVLC);
1850
1851         val = readl(base + USB_TXFILLTUNING);
1852         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
1853                 val = USB_FIFO_TXFILL_THRES(0x10);
1854                 writel(val, base + USB_TXFILLTUNING);
1855         }
1856
1857         val = readl(base + USB_PORTSC);
1858         val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN);
1859         writel(val, base + USB_PORTSC);
1860
1861         val = readl(base + UHSIC_PADS_CFG0);
1862         val &= ~(UHSIC_TX_RTUNEN);
1863         /* set Rtune impedance to 50 ohm */
1864         val |= UHSIC_TX_RTUNE(8);
1865         writel(val, base + UHSIC_PADS_CFG0);
1866
1867         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1868                                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500)) {
1869                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
1870                 return -ETIMEDOUT;
1871         }
1872
1873         phy->phy_clk_on = true;
1874         phy->hw_accessible = true;
1875
1876         return 0;
1877 }
1878
1879 static int uhsic_phy_power_off(struct tegra_usb_phy *phy)
1880 {
1881         unsigned long val;
1882         void __iomem *base = phy->regs;
1883
1884         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1885         if (!phy->phy_clk_on) {
1886                 DBG("%s(%d) inst:[%d] phy clk is already off\n",
1887                                         __func__, __LINE__, phy->inst);
1888                 return 0;
1889         }
1890
1891         val = readl(base + UHSIC_PADS_CFG1);
1892         val &= ~UHSIC_RPU_STROBE;
1893         val |= UHSIC_RPD_STROBE;
1894         writel(val, base + UHSIC_PADS_CFG1);
1895
1896         val = readl(base + USB_SUSP_CTRL);
1897         val |= UHSIC_RESET;
1898         writel(val, base + USB_SUSP_CTRL);
1899         udelay(30);
1900
1901         utmip_powerdown_pmc_wake_detect(phy);
1902
1903         phy->phy_clk_on = false;
1904         phy->hw_accessible = false;
1905
1906         return 0;
1907 }
1908
1909 int uhsic_phy_bus_port_power(struct tegra_usb_phy *phy)
1910 {
1911         unsigned long val;
1912         void __iomem *base = phy->regs;
1913
1914         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1915         val = readl(base + UHSIC_STAT_CFG0);
1916         val &= ~UHSIC_CONNECT_DETECT;
1917         writel(val, base + UHSIC_STAT_CFG0);
1918
1919         val = readl(base + USB_USBMODE);
1920         val |= USB_USBMODE_HOST;
1921         writel(val, base + USB_USBMODE);
1922
1923         /* Change the USB controller PHY type to HSIC */
1924         val = readl(base + HOSTPC1_DEVLC);
1925         val &= ~(HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK));
1926         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
1927         val &= ~(HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK));
1928         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
1929         writel(val, base + HOSTPC1_DEVLC);
1930
1931         val = readl(base + UHSIC_MISC_CFG0);
1932         val |= UHSIC_DETECT_SHORT_CONNECT;
1933         writel(val, base + UHSIC_MISC_CFG0);
1934         udelay(1);
1935
1936         val = readl(base + UHSIC_MISC_CFG0);
1937         val |= UHSIC_FORCE_XCVR_MODE;
1938         writel(val, base + UHSIC_MISC_CFG0);
1939
1940         val = readl(base + UHSIC_PADS_CFG1);
1941         val &= ~UHSIC_RPD_STROBE;
1942         /* safe to enable RPU on STROBE at all times during idle */
1943         val |= UHSIC_RPU_STROBE;
1944         writel(val, base + UHSIC_PADS_CFG1);
1945
1946         val = readl(base + USB_USBCMD);
1947         val &= ~USB_USBCMD_RS;
1948         writel(val, base + USB_USBCMD);
1949
1950         if (usb_phy_reg_status_wait(base + UHSIC_STAT_CFG0,
1951                         UHSIC_CONNECT_DETECT, UHSIC_CONNECT_DETECT, 25000)) {
1952                 pr_err("%s: timeout waiting for UHSIC_CONNECT_DETECT\n",
1953                                                                 __func__);
1954                 return -ETIMEDOUT;
1955         }
1956
1957         return 0;
1958 }
1959
1960 static int uhsic_phy_bus_reset(struct tegra_usb_phy *phy)
1961 {
1962         unsigned long val;
1963         void __iomem *base = phy->regs;
1964
1965         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1966
1967         /* Change the USB controller PHY type to HSIC */
1968         val = readl(base + HOSTPC1_DEVLC);
1969         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
1970         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
1971         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
1972         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
1973         writel(val, base + HOSTPC1_DEVLC);
1974         /* wait here, otherwise HOSTPC1_DEVLC_PSPD will timeout */
1975         mdelay(5);
1976
1977         val = readl(base + USB_PORTSC);
1978         val |= USB_PORTSC_PTC(5);
1979         writel(val, base + USB_PORTSC);
1980         udelay(2);
1981
1982         val = readl(base + USB_PORTSC);
1983         val &= ~(USB_PORTSC_PTC(~0));
1984         writel(val, base + USB_PORTSC);
1985         udelay(2);
1986
1987         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_LS(0),
1988                                                  0, 2000)) {
1989                 pr_err("%s: timeout waiting for USB_PORTSC_LS\n", __func__);
1990                 return -ETIMEDOUT;
1991         }
1992
1993         /* Poll until CCS is enabled */
1994         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
1995                                                  USB_PORTSC_CCS, 2000)) {
1996                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
1997                 return -ETIMEDOUT;
1998         }
1999
2000         if (usb_phy_reg_status_wait(base + HOSTPC1_DEVLC,
2001                         HOSTPC1_DEVLC_PSPD(2),
2002                         HOSTPC1_DEVLC_PSPD(2), 2000) < 0) {
2003                 pr_err("%s: timeout waiting hsic high speed configuration\n",
2004                                                 __func__);
2005                         return -ETIMEDOUT;
2006         }
2007
2008         val = readl(base + USB_USBCMD);
2009         val &= ~USB_USBCMD_RS;
2010         writel(val, base + USB_USBCMD);
2011
2012         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
2013                                                  USB_USBSTS_HCH, 2000)) {
2014                 pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
2015                 return -ETIMEDOUT;
2016         }
2017
2018         val = readl(base + UHSIC_PADS_CFG1);
2019         val &= ~UHSIC_RPU_STROBE;
2020         val |= UHSIC_RPD_STROBE;
2021         writel(val, base + UHSIC_PADS_CFG1);
2022
2023         mdelay(50);
2024
2025         val = readl(base + UHSIC_PADS_CFG1);
2026         val &= ~UHSIC_RPD_STROBE;
2027         val |= UHSIC_RPU_STROBE;
2028         writel(val, base + UHSIC_PADS_CFG1);
2029
2030         val = readl(base + USB_USBCMD);
2031         val |= USB_USBCMD_RS;
2032         writel(val, base + USB_USBCMD);
2033
2034         val = readl(base + UHSIC_PADS_CFG1);
2035         val &= ~UHSIC_RPU_STROBE;
2036         writel(val, base + UHSIC_PADS_CFG1);
2037
2038         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2039                                                  USB_USBCMD_RS, 2000)) {
2040                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2041                 return -ETIMEDOUT;
2042         }
2043
2044         return 0;
2045 }
2046
2047
2048 int uhsic_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
2049 {
2050         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2051
2052         usb_phy_wait_for_sof(phy);
2053
2054         return 0;
2055 }
2056
2057 int uhsic_phy_resume(struct tegra_usb_phy *phy)
2058 {
2059         void __iomem *base = phy->regs;
2060         unsigned long val;
2061
2062         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2063
2064         /* Check if the phy resume from LP0. When the phy resume from LP0
2065          * USB register will be reset.to zero */
2066         if (!readl(base + USB_ASYNCLISTADDR)) {
2067
2068                 val = readl(base + USB_USBCMD);
2069                 val |= USB_CMD_RESET;
2070                 writel(val, base + USB_USBCMD);
2071
2072                 if (usb_phy_reg_status_wait(base + USB_USBCMD,
2073                         USB_CMD_RESET, 0, 2500) < 0) {
2074                         pr_err("%s: timeout waiting for reset\n", __func__);
2075                 }
2076
2077                 val = readl(base + USB_USBMODE);
2078                 val &= ~USB_USBMODE_MASK;
2079                 val |= USB_USBMODE_HOST;
2080                 writel(val, base + USB_USBMODE);
2081
2082                 /* Enable Port Power */
2083                 val = readl(base + USB_PORTSC);
2084                 val |= USB_PORTSC_PP;
2085                 writel(val, base + USB_PORTSC);
2086                 udelay(10);
2087
2088                 DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
2089                 readl(base + USB_USBSTS), readl(base + USB_PORTSC));
2090
2091                 uhsic_phy_bus_port_power(phy);
2092         }
2093
2094         return 0;
2095 }
2096
2097 static int uhsic_phy_post_resume(struct tegra_usb_phy *phy)
2098 {
2099         unsigned long val;
2100         void __iomem *base = phy->regs;
2101
2102         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2103         val = readl(base + USB_TXFILLTUNING);
2104         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
2105                 val = USB_FIFO_TXFILL_THRES(0x10);
2106                 writel(val, base + USB_TXFILLTUNING);
2107         }
2108
2109         return 0;
2110 }
2111
2112 static void ulpi_set_trimmer(struct tegra_usb_phy *phy)
2113 {
2114         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2115         void __iomem *base = phy->regs;
2116         unsigned long val;
2117
2118         val = ULPI_DATA_TRIMMER_SEL(config->data_trimmer);
2119         val |= ULPI_STPDIRNXT_TRIMMER_SEL(config->stpdirnxt_trimmer);
2120         val |= ULPI_DIR_TRIMMER_SEL(config->dir_trimmer);
2121         writel(val, base + ULPI_TIMING_CTRL_1);
2122         udelay(10);
2123
2124         val |= ULPI_DATA_TRIMMER_LOAD;
2125         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
2126         val |= ULPI_DIR_TRIMMER_LOAD;
2127         writel(val, base + ULPI_TIMING_CTRL_1);
2128 }
2129
2130 static void reset_utmip_uhsic(void __iomem *base)
2131 {
2132         unsigned long val;
2133
2134         val = readl(base + USB_SUSP_CTRL);
2135         val |= UHSIC_RESET;
2136         writel(val, base + USB_SUSP_CTRL);
2137
2138         val = readl(base + USB_SUSP_CTRL);
2139         val |= UTMIP_RESET;
2140         writel(val, base + USB_SUSP_CTRL);
2141 }
2142
2143 static void ulpi_set_host(void __iomem *base)
2144 {
2145         unsigned long val;
2146
2147         val = readl(base + USB_USBMODE);
2148         val |= USB_USBMODE_HOST;
2149         writel(val, base + USB_USBMODE);
2150
2151         val = readl(base + HOSTPC1_DEVLC);
2152         val |= HOSTPC1_DEVLC_PTS(2);
2153         writel(val, base + HOSTPC1_DEVLC);
2154 }
2155
2156
2157
2158 static inline void null_phy_set_tristate(bool enable)
2159 {
2160 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2161         int tristate = (enable) ? TEGRA_TRI_TRISTATE : TEGRA_TRI_NORMAL;
2162         DBG("%s(%d) inst:[%s] FIXME enable pin group +++\n", __func__,
2163                                 __LINE__, enable ? "TRISTATE" : "NORMAL");
2164
2165         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA0, tristate);
2166         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA1, tristate);
2167         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA2, tristate);
2168         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA3, tristate);
2169         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA4, tristate);
2170         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA5, tristate);
2171         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA6, tristate);
2172         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA7, tristate);
2173         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_NXT, tristate);
2174
2175         if (enable)
2176                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR, tristate);
2177 #endif
2178
2179 }
2180
2181
2182 static int ulpi_null_phy_power_off(struct tegra_usb_phy *phy)
2183 {
2184         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2185
2186         if (!phy->phy_clk_on) {
2187                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
2188                                                         __LINE__, phy->inst);
2189                 return 0;
2190         }
2191
2192         null_phy_set_tristate(true);
2193
2194         phy->phy_clk_on = false;
2195         phy->hw_accessible = false;
2196
2197         return 0;
2198 }
2199
2200 static int ulpi_null_phy_init(struct tegra_usb_phy *phy)
2201 {
2202         unsigned long val;
2203         void __iomem *base = phy->regs;
2204
2205         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2206         val = readl(base + ULPIS2S_CTRL);
2207         val |=  ULPIS2S_SLV0_CLAMP_XMIT;
2208         writel(val, base + ULPIS2S_CTRL);
2209
2210         val = readl(base + USB_SUSP_CTRL);
2211         val |= ULPIS2S_SLV0_RESET;
2212         writel(val, base + USB_SUSP_CTRL);
2213         udelay(10);
2214
2215         return 0;
2216 }
2217
2218 static int ulpi_null_phy_irq(struct tegra_usb_phy *phy)
2219 {
2220         usb_phy_fence_read(phy);
2221         return IRQ_HANDLED;
2222 }
2223
2224 static int ulpi_null_phy_cmd_reset(struct tegra_usb_phy *phy)
2225 {
2226         unsigned long val;
2227         void __iomem *base = phy->regs;
2228
2229         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2230         ulpi_set_host(base);
2231
2232         /* remove slave0 reset */
2233         val = readl(base + USB_SUSP_CTRL);
2234         val &= ~ULPIS2S_SLV0_RESET;
2235         writel(val, base + USB_SUSP_CTRL);
2236
2237         val = readl(base + ULPIS2S_CTRL);
2238         val &=  ~ULPIS2S_SLV0_CLAMP_XMIT;
2239         writel(val, base + ULPIS2S_CTRL);
2240         udelay(10);
2241
2242         return 0;
2243 }
2244
2245 static int ulpi_null_phy_power_on(struct tegra_usb_phy *phy)
2246 {
2247         unsigned long val;
2248         void __iomem *base = phy->regs;
2249         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2250         static bool cold_boot = true;
2251
2252         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2253         if (phy->phy_clk_on) {
2254                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
2255                                                         __LINE__, phy->inst);
2256                 return 0;
2257         }
2258         reset_utmip_uhsic(base);
2259
2260         /* remove ULPI PADS CLKEN reset */
2261         val = readl(base + USB_SUSP_CTRL);
2262         val &= ~ULPI_PADS_CLKEN_RESET;
2263         writel(val, base + USB_SUSP_CTRL);
2264         udelay(10);
2265
2266         val = readl(base + ULPI_TIMING_CTRL_0);
2267         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
2268         writel(val, base + ULPI_TIMING_CTRL_0);
2269
2270         val = readl(base + USB_SUSP_CTRL);
2271         val |= ULPI_PHY_ENABLE;
2272         writel(val, base + USB_SUSP_CTRL);
2273         udelay(10);
2274
2275         /* set timming parameters */
2276         val = readl(base + ULPI_TIMING_CTRL_0);
2277         val |= ULPI_SHADOW_CLK_LOOPBACK_EN;
2278         val &= ~ULPI_SHADOW_CLK_SEL;
2279         val &= ~ULPI_LBK_PAD_EN;
2280         val |= ULPI_SHADOW_CLK_DELAY(config->shadow_clk_delay);
2281         val |= ULPI_CLOCK_OUT_DELAY(config->clock_out_delay);
2282         val |= ULPI_LBK_PAD_E_INPUT_OR;
2283         writel(val, base + ULPI_TIMING_CTRL_0);
2284
2285         writel(0, base + ULPI_TIMING_CTRL_1);
2286         udelay(10);
2287
2288         /* start internal 60MHz clock */
2289         val = readl(base + ULPIS2S_CTRL);
2290         val |= ULPIS2S_ENA;
2291         val |= ULPIS2S_SUPPORT_DISCONNECT;
2292         val |= ULPIS2S_SPARE((phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) ? 3 : 1);
2293         val |= ULPIS2S_PLLU_MASTER_BLASTER60;
2294         writel(val, base + ULPIS2S_CTRL);
2295
2296         /* select ULPI_CORE_CLK_SEL to SHADOW_CLK */
2297         val = readl(base + ULPI_TIMING_CTRL_0);
2298         val |= ULPI_CORE_CLK_SEL;
2299         writel(val, base + ULPI_TIMING_CTRL_0);
2300         udelay(10);
2301
2302         /* enable ULPI null phy clock - can't set the trimmers before this */
2303         val = readl(base + ULPI_TIMING_CTRL_0);
2304         val |= ULPI_CLK_OUT_ENA;
2305         writel(val, base + ULPI_TIMING_CTRL_0);
2306         udelay(10);
2307
2308         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
2309                                                  USB_PHY_CLK_VALID, 2500)) {
2310                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2311                 return -ETIMEDOUT;
2312         }
2313
2314         /* set ULPI trimmers */
2315         ulpi_set_trimmer(phy);
2316
2317         ulpi_set_host(base);
2318
2319         /* remove slave0 reset */
2320         val = readl(base + USB_SUSP_CTRL);
2321         val &= ~ULPIS2S_SLV0_RESET;
2322         writel(val, base + USB_SUSP_CTRL);
2323
2324         /* remove slave1 and line reset */
2325         val = readl(base + USB_SUSP_CTRL);
2326         val &= ~ULPIS2S_SLV1_RESET;
2327         val &= ~ULPIS2S_LINE_RESET;
2328
2329         /* remove ULPI PADS reset */
2330         val &= ~ULPI_PADS_RESET;
2331         writel(val, base + USB_SUSP_CTRL);
2332
2333         if (cold_boot) {
2334                 val = readl(base + ULPI_TIMING_CTRL_0);
2335                 val |= ULPI_CLK_PADOUT_ENA;
2336                 writel(val, base + ULPI_TIMING_CTRL_0);
2337                 cold_boot = false;
2338         }
2339         udelay(10);
2340
2341         phy->phy_clk_on = true;
2342         phy->hw_accessible = true;
2343
2344         return 0;
2345 }
2346
2347
2348 int ulpi_null_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
2349 {
2350         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2351
2352         usb_phy_wait_for_sof(phy);
2353         return 0;
2354 }
2355
2356 static struct tegra_usb_phy_ops utmi_phy_ops = {
2357         .open           = utmi_phy_open,
2358         .close          = utmi_phy_close,
2359         .irq            = utmi_phy_irq,
2360         .power_on       = utmi_phy_power_on,
2361         .power_off      = utmi_phy_power_off,
2362         .pre_resume = utmi_phy_pre_resume,
2363         .resume = utmi_phy_resume,
2364         .post_resume    = utmi_phy_post_resume,
2365         .charger_detect = utmi_phy_charger_detect,
2366 };
2367
2368 static struct tegra_usb_phy_ops uhsic_phy_ops = {
2369         .open           = uhsic_phy_open,
2370         .irq            = uhsic_phy_irq,
2371         .power_on       = uhsic_phy_power_on,
2372         .power_off      = uhsic_phy_power_off,
2373         .pre_resume = uhsic_phy_pre_resume,
2374         .resume = uhsic_phy_resume,
2375         .post_resume = uhsic_phy_post_resume,
2376         .port_power = uhsic_phy_bus_port_power,
2377         .bus_reset      = uhsic_phy_bus_reset,
2378 };
2379
2380 static struct tegra_usb_phy_ops ulpi_null_phy_ops = {
2381         .init           = ulpi_null_phy_init,
2382         .irq            = ulpi_null_phy_irq,
2383         .power_on       = ulpi_null_phy_power_on,
2384         .power_off      = ulpi_null_phy_power_off,
2385         .pre_resume = ulpi_null_phy_pre_resume,
2386         .reset          = ulpi_null_phy_cmd_reset,
2387 };
2388
2389 static struct tegra_usb_phy_ops ulpi_link_phy_ops;
2390 static struct tegra_usb_phy_ops icusb_phy_ops;
2391
2392 static struct tegra_usb_phy_ops *phy_ops[] = {
2393         [TEGRA_USB_PHY_INTF_UTMI] = &utmi_phy_ops,
2394         [TEGRA_USB_PHY_INTF_ULPI_LINK] = &ulpi_link_phy_ops,
2395         [TEGRA_USB_PHY_INTF_ULPI_NULL] = &ulpi_null_phy_ops,
2396         [TEGRA_USB_PHY_INTF_HSIC] = &uhsic_phy_ops,
2397         [TEGRA_USB_PHY_INTF_ICUSB] = &icusb_phy_ops,
2398 };
2399
2400 int tegra3_usb_phy_init_ops(struct tegra_usb_phy *phy)
2401 {
2402         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2403
2404         phy->ops = phy_ops[phy->pdata->phy_intf];
2405
2406         /* FIXME: uncommenting below line to make USB host mode fail*/
2407         /* usb_phy_power_down_pmc(); */
2408
2409         return 0;
2410 }