arm: tegra3: usb_phy: HSIC rail consumes 4mA in suspend
[linux-2.6.git] / arch / arm / mach-tegra / tegra3_usb_phy.c
1 /*
2  * arch/arm/mach-tegra/tegra3_usb_phy.c
3  *
4  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
5  *
6  *
7  * This software is licensed under the terms of the GNU General Public
8  * License version 2, as published by the Free Software Foundation, and
9  * may be copied, distributed, and modified under those terms.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17 #include <linux/resource.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/slab.h>
21 #include <linux/err.h>
22 #include <linux/platform_device.h>
23 #include <linux/io.h>
24 #include <linux/gpio.h>
25 #include <linux/interrupt.h>
26 #include <linux/clk.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <mach/clk.h>
30 #include <mach/iomap.h>
31 #include <mach/pinmux.h>
32 #include <mach/pinmux-tegra30.h>
33 #include "tegra_usb_phy.h"
34 #include "gpio-names.h"
35 #include "fuse.h"
36
37 #define USB_USBCMD              0x130
38 #define   USB_USBCMD_RS         (1 << 0)
39 #define   USB_CMD_RESET (1<<1)
40
41 #define USB_USBSTS              0x134
42 #define   USB_USBSTS_PCI        (1 << 2)
43 #define   USB_USBSTS_SRI        (1 << 7)
44 #define   USB_USBSTS_HCH        (1 << 12)
45
46 #define USB_USBINTR             0x138
47
48 #define USB_TXFILLTUNING        0x154
49 #define USB_FIFO_TXFILL_THRES(x)   (((x) & 0x1f) << 16)
50 #define USB_FIFO_TXFILL_MASK    0x1f0000
51
52 #define USB_ASYNCLISTADDR       0x148
53
54 #define ICUSB_CTRL              0x15c
55
56 #define USB_PORTSC              0x174
57 #define   USB_PORTSC_WKOC       (1 << 22)
58 #define   USB_PORTSC_WKDS       (1 << 21)
59 #define   USB_PORTSC_WKCN       (1 << 20)
60 #define   USB_PORTSC_PTC(x)     (((x) & 0xf) << 16)
61 #define   USB_PORTSC_PP (1 << 12)
62 #define   USB_PORTSC_LS(x) (((x) & 0x3) << 10)
63 #define   USB_PORTSC_SUSP       (1 << 7)
64 #define   USB_PORTSC_RESUME     (1 << 6)
65 #define   USB_PORTSC_OCC        (1 << 5)
66 #define   USB_PORTSC_PEC        (1 << 3)
67 #define   USB_PORTSC_PE         (1 << 2)
68 #define   USB_PORTSC_CSC        (1 << 1)
69 #define   USB_PORTSC_CCS        (1 << 0)
70 #define   USB_PORTSC_RWC_BITS (USB_PORTSC_CSC | USB_PORTSC_PEC | USB_PORTSC_OCC)
71
72 #define HOSTPC1_DEVLC           0x1b4
73 #define   HOSTPC1_DEVLC_PHCD            (1 << 22)
74 #define   HOSTPC1_DEVLC_PTS(x)          (((x) & 0x7) << 29)
75 #define   HOSTPC1_DEVLC_PTS_MASK        7
76 #define   HOSTPC1_DEVLC_PTS_HSIC        4
77 #define   HOSTPC1_DEVLC_STS             (1 << 28)
78 #define   HOSTPC1_DEVLC_PSPD(x)         (((x) & 0x3) << 25)
79 #define   HOSTPC1_DEVLC_PSPD_MASK       3
80 #define   HOSTPC1_DEVLC_PSPD_HIGH_SPEED 2
81
82 #define USB_USBMODE             0x1f8
83 #define   USB_USBMODE_MASK              (3 << 0)
84 #define   USB_USBMODE_HOST              (3 << 0)
85 #define   USB_USBMODE_DEVICE            (2 << 0)
86
87 #define USB_SUSP_CTRL           0x400
88 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
89 #define   USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
90 #define   USB_SUSP_CLR                  (1 << 5)
91 #define   USB_PHY_CLK_VALID             (1 << 7)
92 #define   USB_PHY_CLK_VALID_INT_ENB     (1 << 9)
93 #define   USB_PHY_CLK_VALID_INT_STS     (1 << 8)
94 #define   UTMIP_RESET                   (1 << 11)
95 #define   UTMIP_PHY_ENABLE              (1 << 12)
96 #define   ULPI_PHY_ENABLE               (1 << 13)
97 #define   UHSIC_RESET                   (1 << 14)
98 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
99 #define   UHSIC_PHY_ENABLE              (1 << 19)
100 #define   ULPIS2S_SLV0_RESET            (1 << 20)
101 #define   ULPIS2S_SLV1_RESET            (1 << 21)
102 #define   ULPIS2S_LINE_RESET            (1 << 22)
103 #define   ULPI_PADS_RESET               (1 << 23)
104 #define   ULPI_PADS_CLKEN_RESET         (1 << 24)
105
106 #define USB_PHY_VBUS_WAKEUP_ID  0x408
107 #define   VDAT_DET_INT_EN       (1 << 16)
108 #define   VDAT_DET_CHG_DET      (1 << 17)
109 #define   VDAT_DET_STS          (1 << 18)
110 #define   USB_ID_STATUS         (1 << 2)
111
112 #define ULPIS2S_CTRL            0x418
113 #define   ULPIS2S_ENA                   (1 << 0)
114 #define   ULPIS2S_SUPPORT_DISCONNECT    (1 << 2)
115 #define   ULPIS2S_PLLU_MASTER_BLASTER60 (1 << 3)
116 #define   ULPIS2S_SPARE(x)              (((x) & 0xF) << 8)
117 #define   ULPIS2S_FORCE_ULPI_CLK_OUT    (1 << 12)
118 #define   ULPIS2S_DISCON_DONT_CHECK_SE0 (1 << 13)
119 #define   ULPIS2S_SUPPORT_HS_KEEP_ALIVE (1 << 14)
120 #define   ULPIS2S_DISABLE_STP_PU        (1 << 15)
121 #define   ULPIS2S_SLV0_CLAMP_XMIT       (1 << 16)
122
123 #define ULPI_TIMING_CTRL_0      0x424
124 #define   ULPI_CLOCK_OUT_DELAY(x)       ((x) & 0x1F)
125 #define   ULPI_OUTPUT_PINMUX_BYP        (1 << 10)
126 #define   ULPI_CLKOUT_PINMUX_BYP        (1 << 11)
127 #define   ULPI_SHADOW_CLK_LOOPBACK_EN   (1 << 12)
128 #define   ULPI_SHADOW_CLK_SEL           (1 << 13)
129 #define   ULPI_CORE_CLK_SEL             (1 << 14)
130 #define   ULPI_SHADOW_CLK_DELAY(x)      (((x) & 0x1F) << 16)
131 #define   ULPI_LBK_PAD_EN               (1 << 26)
132 #define   ULPI_LBK_PAD_E_INPUT_OR       (1 << 27)
133 #define   ULPI_CLK_OUT_ENA              (1 << 28)
134 #define   ULPI_CLK_PADOUT_ENA           (1 << 29)
135
136 #define ULPI_TIMING_CTRL_1      0x428
137 #define   ULPI_DATA_TRIMMER_LOAD        (1 << 0)
138 #define   ULPI_DATA_TRIMMER_SEL(x)      (((x) & 0x7) << 1)
139 #define   ULPI_STPDIRNXT_TRIMMER_LOAD   (1 << 16)
140 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
141 #define   ULPI_DIR_TRIMMER_LOAD         (1 << 24)
142 #define   ULPI_DIR_TRIMMER_SEL(x)       (((x) & 0x7) << 25)
143
144 #define UTMIP_XCVR_CFG0         0x808
145 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
146 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
147 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
148 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
149 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
150 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
151 #define   UTMIP_XCVR_LSBIAS_SEL                 (1 << 21)
152 #define   UTMIP_XCVR_SETUP_MSB(x)               (((x) & 0x7) << 22)
153 #define   UTMIP_XCVR_HSSLEW_MSB(x)              (((x) & 0x7f) << 25)
154 #define   UTMIP_XCVR_MAX_OFFSET         2
155 #define   UTMIP_XCVR_SETUP_MAX_VALUE    0x7f
156 #define   UTMIP_XCVR_SETUP_MIN_VALUE    0
157 #define   XCVR_SETUP_MSB_CALIB(x) ((x) >> 4)
158
159 #define UTMIP_BIAS_CFG0         0x80c
160 #define   UTMIP_OTGPD                   (1 << 11)
161 #define   UTMIP_BIASPD                  (1 << 10)
162 #define   UTMIP_HSSQUELCH_LEVEL(x)      (((x) & 0x3) << 0)
163 #define   UTMIP_HSDISCON_LEVEL(x)       (((x) & 0x3) << 2)
164 #define   UTMIP_HSDISCON_LEVEL_MSB      (1 << 24)
165
166 #define UTMIP_HSRX_CFG0         0x810
167 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
168 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
169
170 #define UTMIP_HSRX_CFG1         0x814
171 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
172
173 #define UTMIP_TX_CFG0           0x820
174 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
175 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
176
177 #define UTMIP_DEBOUNCE_CFG0 0x82c
178 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
179
180 #define UTMIP_BAT_CHRG_CFG0 0x830
181 #define   UTMIP_PD_CHRG                 (1 << 0)
182 #define   UTMIP_ON_SINK_EN              (1 << 2)
183 #define   UTMIP_OP_SRC_EN               (1 << 3)
184
185 #define UTMIP_XCVR_CFG1         0x838
186 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
187 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
188 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
189 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
190
191 #define UTMIP_BIAS_CFG1         0x83c
192 #define   UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
193 #define   UTMIP_BIAS_PDTRK_POWERDOWN    (1 << 0)
194 #define   UTMIP_BIAS_PDTRK_POWERUP      (1 << 1)
195
196 #define UTMIP_MISC_CFG0         0x824
197 #define   UTMIP_DPDM_OBSERVE            (1 << 26)
198 #define   UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
199 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J   UTMIP_DPDM_OBSERVE_SEL(0xf)
200 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K   UTMIP_DPDM_OBSERVE_SEL(0xe)
201 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
202 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
203 #define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
204 #define   FORCE_PULLDN_DM       (1 << 8)
205 #define   FORCE_PULLDN_DP       (1 << 9)
206 #define   COMB_TERMS            (1 << 0)
207 #define   ALWAYS_FREE_RUNNING_TERMS (1 << 1)
208
209 #define UTMIP_SPARE_CFG0        0x834
210 #define   FUSE_SETUP_SEL                (1 << 3)
211 #define   FUSE_ATERM_SEL                (1 << 4)
212
213 #define UTMIP_PMC_WAKEUP0               0x84c
214 #define   EVENT_INT_ENB                 (1 << 0)
215
216 #define UHSIC_PMC_WAKEUP0               0xc34
217
218 #define UTMIP_BIAS_STS0                 0x840
219 #define   UTMIP_RCTRL_VAL(x)            (((x) & 0xffff) << 0)
220 #define   UTMIP_TCTRL_VAL(x)            (((x) & (0xffff << 16)) >> 16)
221
222 #define UHSIC_PLL_CFG1                          0xc04
223 #define   UHSIC_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
224 #define   UHSIC_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 14)
225
226 #define UHSIC_HSRX_CFG0                         0xc08
227 #define   UHSIC_ELASTIC_UNDERRUN_LIMIT(x)       (((x) & 0x1f) << 2)
228 #define   UHSIC_ELASTIC_OVERRUN_LIMIT(x)        (((x) & 0x1f) << 8)
229 #define   UHSIC_IDLE_WAIT(x)                    (((x) & 0x1f) << 13)
230
231 #define UHSIC_HSRX_CFG1                         0xc0c
232 #define   UHSIC_HS_SYNC_START_DLY(x)            (((x) & 0x1f) << 1)
233
234 #define UHSIC_TX_CFG0                           0xc10
235 #define UHSIC_HS_READY_WAIT_FOR_VALID   (1 << 9)
236 #define UHSIC_MISC_CFG0                         0xc14
237 #define   UHSIC_SUSPEND_EXIT_ON_EDGE            (1 << 7)
238 #define   UHSIC_DETECT_SHORT_CONNECT            (1 << 8)
239 #define   UHSIC_FORCE_XCVR_MODE                 (1 << 15)
240 #define   UHSIC_DISABLE_BUSRESET                (1 << 20)
241 #define UHSIC_MISC_CFG1                         0xc18
242 #define   UHSIC_PLLU_STABLE_COUNT(x)            (((x) & 0xfff) << 2)
243
244 #define UHSIC_PADS_CFG0                         0xc1c
245 #define   UHSIC_TX_RTUNEN                       0xf000
246 #define   UHSIC_TX_RTUNE(x)                     (((x) & 0xf) << 12)
247
248 #define UHSIC_PADS_CFG1                         0xc20
249 #define   UHSIC_PD_BG                           (1 << 2)
250 #define   UHSIC_PD_TX                           (1 << 3)
251 #define   UHSIC_PD_TRK                          (1 << 4)
252 #define   UHSIC_PD_RX                           (1 << 5)
253 #define   UHSIC_PD_ZI                           (1 << 6)
254 #define   UHSIC_RX_SEL                          (1 << 7)
255 #define   UHSIC_RPD_DATA                        (1 << 9)
256 #define   UHSIC_RPD_STROBE                      (1 << 10)
257 #define   UHSIC_RPU_DATA                        (1 << 11)
258 #define   UHSIC_RPU_STROBE                      (1 << 12)
259
260 #define UHSIC_CMD_CFG0                  0xc24
261 #define UHSIC_PRETEND_CONNECT_DETECT    (1 << 5)
262
263 #define UHSIC_STAT_CFG0         0xc28
264 #define UHSIC_CONNECT_DETECT            (1 << 0)
265
266 #define PMC_USB_DEBOUNCE                        0xec
267 #define UTMIP_LINE_DEB_CNT(x)           (((x) & 0xf) << 16)
268 #define UHSIC_LINE_DEB_CNT(x)           (((x) & 0xf) << 20)
269
270 #define PMC_USB_AO                              0xf0
271
272 #define PMC_POWER_DOWN_MASK                     0xffff
273 #define HSIC_RESERVED_P0                        (3 << 14)
274 #define STROBE_VAL_PD_P0                        (1 << 12)
275 #define DATA_VAL_PD_P0                          (1 << 13)
276
277 #define USB_ID_PD(inst)                 (1 << ((4*(inst))+3))
278 #define VBUS_WAKEUP_PD(inst)                    (1 << ((4*(inst))+2))
279 #define   USBON_VAL_PD(inst)                    (1 << ((4*(inst))+1))
280 #define   USBON_VAL_PD_P2                       (1 << 9)
281 #define   USBON_VAL_PD_P1                       (1 << 5)
282 #define   USBON_VAL_PD_P0                       (1 << 1)
283 #define   USBOP_VAL_PD(inst)                    (1 << (4*(inst)))
284 #define   USBOP_VAL_PD_P2                       (1 << 8)
285 #define   USBOP_VAL_PD_P1                       (1 << 4)
286 #define   USBOP_VAL_PD_P0                       (1 << 0)
287 #define   PMC_USB_AO_PD_P2                      (0xf << 8)
288 #define   PMC_USB_AO_ID_PD_P0                   (1 << 3)
289 #define   PMC_USB_AO_VBUS_WAKEUP_PD_P0  (1 << 2)
290
291 #define PMC_TRIGGERS                    0x1ec
292
293 #define   UHSIC_CLR_WALK_PTR_P0         (1 << 3)
294 #define   UTMIP_CLR_WALK_PTR(inst)      (1 << (inst))
295 #define   UTMIP_CLR_WALK_PTR_P2         (1 << 2)
296 #define   UTMIP_CLR_WALK_PTR_P1         (1 << 1)
297 #define   UTMIP_CLR_WALK_PTR_P0         (1 << 0)
298 #define   UTMIP_CAP_CFG(inst)   (1 << ((inst)+4))
299 #define   UTMIP_CAP_CFG_P2              (1 << 6)
300 #define   UTMIP_CAP_CFG_P1              (1 << 5)
301 #define   UTMIP_CAP_CFG_P0              (1 << 4)
302 #define   UTMIP_CLR_WAKE_ALARM(inst)    (1 << ((inst)+12))
303 #define   UHSIC_CLR_WAKE_ALARM_P0       (1 << 15)
304 #define   UTMIP_CLR_WAKE_ALARM_P2       (1 << 14)
305
306 #define PMC_PAD_CFG             (0x1f4)
307
308 #define PMC_UTMIP_TERM_PAD_CFG  0x1f8
309 #define   PMC_TCTRL_VAL(x)      (((x) & 0x1f) << 5)
310 #define   PMC_RCTRL_VAL(x)      (((x) & 0x1f) << 0)
311
312 #define PMC_SLEEP_CFG                   0x1fc
313
314 #define   UHSIC_MASTER_ENABLE                   (1 << 24)
315 #define   UHSIC_WAKE_VAL(x)             (((x) & 0xf) << 28)
316 #define   WAKE_VAL_SD10                 0x2
317 #define   UTMIP_TCTRL_USE_PMC(inst) (1 << ((8*(inst))+3))
318 #define   UTMIP_TCTRL_USE_PMC_P2                (1 << 19)
319 #define   UTMIP_TCTRL_USE_PMC_P1                (1 << 11)
320 #define   UTMIP_TCTRL_USE_PMC_P0                (1 << 3)
321 #define   UTMIP_RCTRL_USE_PMC(inst) (1 << ((8*(inst))+2))
322 #define   UTMIP_RCTRL_USE_PMC_P2                (1 << 18)
323 #define   UTMIP_RCTRL_USE_PMC_P1                (1 << 10)
324 #define   UTMIP_RCTRL_USE_PMC_P0                (1 << 2)
325 #define   UTMIP_FSLS_USE_PMC(inst)      (1 << ((8*(inst))+1))
326 #define   UTMIP_FSLS_USE_PMC_P2         (1 << 17)
327 #define   UTMIP_FSLS_USE_PMC_P1         (1 << 9)
328 #define   UTMIP_FSLS_USE_PMC_P0         (1 << 1)
329 #define   UTMIP_MASTER_ENABLE(inst) (1 << (8*(inst)))
330 #define   UTMIP_MASTER_ENABLE_P2                (1 << 16)
331 #define   UTMIP_MASTER_ENABLE_P1                (1 << 8)
332 #define   UTMIP_MASTER_ENABLE_P0                (1 << 0)
333 #define UHSIC_MASTER_ENABLE_P0          (1 << 24)
334 #define UHSIC_WAKE_VAL_P0(x)            (((x) & 0xf) << 28)
335
336 #define PMC_SLEEPWALK_CFG               0x200
337
338 #define   UHSIC_WAKE_WALK_EN_P0 (1 << 30)
339 #define   UHSIC_LINEVAL_WALK_EN (1 << 31)
340 #define   UTMIP_LINEVAL_WALK_EN(inst) (1 << ((8*(inst))+7))
341 #define   UTMIP_LINEVAL_WALK_EN_P2      (1 << 23)
342 #define   UTMIP_LINEVAL_WALK_EN_P1      (1 << 15)
343 #define   UTMIP_LINEVAL_WALK_EN_P0      (1 << 7)
344 #define   UTMIP_WAKE_VAL(inst, x) (((x) & 0xf) << ((8*(inst))+4))
345 #define   UTMIP_WAKE_VAL_P2(x)          (((x) & 0xf) << 20)
346 #define   UTMIP_WAKE_VAL_P1(x)          (((x) & 0xf) << 12)
347 #define   UTMIP_WAKE_VAL_P0(x)          (((x) & 0xf) << 4)
348 #define   WAKE_VAL_NONE         0xc
349 #define   WAKE_VAL_ANY                  0xF
350 #define   WAKE_VAL_FSJ                  0x2
351 #define   WAKE_VAL_FSK                  0x1
352 #define   WAKE_VAL_SE0                  0x0
353
354 #define PMC_SLEEPWALK_REG(inst)         (0x204 + (4*(inst)))
355 #define   UTMIP_USBOP_RPD_A     (1 << 0)
356 #define   UTMIP_USBON_RPD_A     (1 << 1)
357 #define   UTMIP_AP_A                    (1 << 4)
358 #define   UTMIP_AN_A                    (1 << 5)
359 #define   UTMIP_HIGHZ_A         (1 << 6)
360 #define   UTMIP_USBOP_RPD_B     (1 << 8)
361 #define   UTMIP_USBON_RPD_B     (1 << 9)
362 #define   UTMIP_AP_B                    (1 << 12)
363 #define   UTMIP_AN_B                    (1 << 13)
364 #define   UTMIP_HIGHZ_B         (1 << 14)
365 #define   UTMIP_USBOP_RPD_C     (1 << 16)
366 #define   UTMIP_USBON_RPD_C     (1 << 17)
367 #define   UTMIP_AP_C            (1 << 20)
368 #define   UTMIP_AN_C            (1 << 21)
369 #define   UTMIP_HIGHZ_C         (1 << 22)
370 #define   UTMIP_USBOP_RPD_D     (1 << 24)
371 #define   UTMIP_USBON_RPD_D     (1 << 25)
372 #define   UTMIP_AP_D            (1 << 28)
373 #define   UTMIP_AN_D            (1 << 29)
374 #define   UTMIP_HIGHZ_D         (1 << 30)
375
376 #define PMC_SLEEPWALK_UHSIC             0x210
377
378 #define UHSIC_STROBE_RPD_A              (1 << 0)
379 #define UHSIC_DATA_RPD_A                (1 << 1)
380 #define UHSIC_STROBE_RPU_A              (1 << 2)
381 #define UHSIC_DATA_RPU_A                (1 << 3)
382 #define UHSIC_STROBE_RPD_B              (1 << 8)
383 #define UHSIC_DATA_RPD_B                (1 << 9)
384 #define UHSIC_STROBE_RPU_B              (1 << 10)
385 #define UHSIC_DATA_RPU_B                (1 << 11)
386 #define UHSIC_STROBE_RPD_C              (1 << 16)
387 #define UHSIC_DATA_RPD_C                (1 << 17)
388 #define UHSIC_STROBE_RPU_C              (1 << 18)
389 #define UHSIC_DATA_RPU_C                (1 << 19)
390 #define UHSIC_STROBE_RPD_D              (1 << 24)
391 #define UHSIC_DATA_RPD_D                (1 << 25)
392 #define UHSIC_STROBE_RPU_D              (1 << 26)
393 #define UHSIC_DATA_RPU_D                (1 << 27)
394
395 #define UTMIP_UHSIC_STATUS              0x214
396
397 #define UTMIP_USBOP_VAL(inst)           (1 << ((2*(inst)) + 8))
398 #define UTMIP_USBOP_VAL_P2              (1 << 12)
399 #define UTMIP_USBOP_VAL_P1              (1 << 10)
400 #define UTMIP_USBOP_VAL_P0              (1 << 8)
401 #define UTMIP_USBON_VAL(inst)           (1 << ((2*(inst)) + 9))
402 #define UTMIP_USBON_VAL_P2              (1 << 13)
403 #define UTMIP_USBON_VAL_P1              (1 << 11)
404 #define UTMIP_USBON_VAL_P0              (1 << 9)
405 #define UHSIC_WAKE_ALARM                (1 << 19)
406 #define UTMIP_WAKE_ALARM(inst)          (1 << ((inst) + 16))
407 #define UTMIP_WAKE_ALARM_P2             (1 << 18)
408 #define UTMIP_WAKE_ALARM_P1             (1 << 17)
409 #define UTMIP_WAKE_ALARM_P0             (1 << 16)
410 #define UHSIC_DATA_VAL_P0               (1 << 15)
411 #define UHSIC_STROBE_VAL_P0             (1 << 14)
412 #define UTMIP_WALK_PTR_VAL(inst)        (0x3 << ((inst)*2))
413 #define UHSIC_WALK_PTR_VAL              (0x3 << 6)
414 #define UTMIP_WALK_PTR(inst)            (1 << ((inst)*2))
415 #define UTMIP_WALK_PTR_P2               (1 << 4)
416 #define UTMIP_WALK_PTR_P1               (1 << 2)
417 #define UTMIP_WALK_PTR_P0               (1 << 0)
418
419 #define USB1_PREFETCH_ID                           6
420 #define USB2_PREFETCH_ID                           18
421 #define USB3_PREFETCH_ID                           17
422
423 #define PMC_UTMIP_UHSIC_FAKE            0x218
424
425 #define UHSIC_STROBE_VAL                (1 << 12)
426 #define UHSIC_DATA_VAL                  (1 << 13)
427 #define UHSIC_STROBE_ENB                (1 << 14)
428 #define UHSIC_DATA_ENB                  (1 << 15)
429 #define   USBON_VAL(inst)       (1 << ((4*(inst))+1))
430 #define   USBON_VAL_P2                  (1 << 9)
431 #define   USBON_VAL_P1                  (1 << 5)
432 #define   USBON_VAL_P0                  (1 << 1)
433 #define   USBOP_VAL(inst)       (1 << (4*(inst)))
434 #define   USBOP_VAL_P2                  (1 << 8)
435 #define   USBOP_VAL_P1                  (1 << 4)
436 #define   USBOP_VAL_P0                  (1 << 0)
437
438 #define PMC_UTMIP_BIAS_MASTER_CNTRL 0x30c
439 #define   BIAS_MASTER_PROG_VAL          (1 << 1)
440
441 #define PMC_UTMIP_MASTER_CONFIG 0x310
442
443 #define UTMIP_PWR(inst)         (1 << (inst))
444 #define UHSIC_PWR                       (1 << 3)
445
446 #define FUSE_USB_CALIB_0                0x1F0
447 #define   XCVR_SETUP(x) (((x) & 0x7F) << 0)
448 #define   XCVR_SETUP_LSB_MASK   0xF
449 #define   XCVR_SETUP_MSB_MASK   0x70
450 #define   XCVR_SETUP_LSB_MAX_VAL        0xF
451
452 #define APB_MISC_GP_OBSCTRL_0   0x818
453 #define APB_MISC_GP_OBSDATA_0   0x81c
454
455 /* ULPI GPIO */
456 #define ULPI_STP        TEGRA_GPIO_PY3
457 #define ULPI_DIR        TEGRA_GPIO_PY1
458 #define ULPI_D0         TEGRA_GPIO_PO1
459 #define ULPI_D1         TEGRA_GPIO_PO2
460
461 /* These values (in milli second) are taken from the battery charging spec */
462 #define TDP_SRC_ON_MS    100
463 #define TDPSRC_CON_MS    40
464
465 #ifdef DEBUG
466 #define DBG(stuff...)   pr_info("tegra3_usb_phy: " stuff)
467 #else
468 #define DBG(stuff...)   do {} while (0)
469 #endif
470
471 #if 0
472 #define PHY_DBG(stuff...)       pr_info("tegra3_usb_phy: " stuff)
473 #else
474 #define PHY_DBG(stuff...)       do {} while (0)
475 #endif
476
477
478 static u32 utmip_rctrl_val, utmip_tctrl_val;
479 static DEFINE_SPINLOCK(utmip_pad_lock);
480 static int utmip_pad_count;
481
482 static struct tegra_xtal_freq utmip_freq_table[] = {
483         {
484                 .freq = 12000000,
485                 .enable_delay = 0x02,
486                 .stable_count = 0x2F,
487                 .active_delay = 0x04,
488                 .xtal_freq_count = 0x76,
489                 .debounce = 0x7530,
490                 .pdtrk_count = 5,
491         },
492         {
493                 .freq = 13000000,
494                 .enable_delay = 0x02,
495                 .stable_count = 0x33,
496                 .active_delay = 0x05,
497                 .xtal_freq_count = 0x7F,
498                 .debounce = 0x7EF4,
499                 .pdtrk_count = 5,
500         },
501         {
502                 .freq = 19200000,
503                 .enable_delay = 0x03,
504                 .stable_count = 0x4B,
505                 .active_delay = 0x06,
506                 .xtal_freq_count = 0xBB,
507                 .debounce = 0xBB80,
508                 .pdtrk_count = 7,
509         },
510         {
511                 .freq = 26000000,
512                 .enable_delay = 0x04,
513                 .stable_count = 0x66,
514                 .active_delay = 0x09,
515                 .xtal_freq_count = 0xFE,
516                 .debounce = 0xFDE8,
517                 .pdtrk_count = 9,
518         },
519 };
520
521 static struct tegra_xtal_freq uhsic_freq_table[] = {
522         {
523                 .freq = 12000000,
524                 .enable_delay = 0x02,
525                 .stable_count = 0x2F,
526                 .active_delay = 0x0,
527                 .xtal_freq_count = 0x1CA,
528         },
529         {
530                 .freq = 13000000,
531                 .enable_delay = 0x02,
532                 .stable_count = 0x33,
533                 .active_delay = 0x0,
534                 .xtal_freq_count = 0x1F0,
535         },
536         {
537                 .freq = 19200000,
538                 .enable_delay = 0x03,
539                 .stable_count = 0x4B,
540                 .active_delay = 0x0,
541                 .xtal_freq_count = 0x2DD,
542         },
543         {
544                 .freq = 26000000,
545                 .enable_delay = 0x04,
546                 .stable_count = 0x66,
547                 .active_delay = 0x0,
548                 .xtal_freq_count = 0x3E0,
549         },
550 };
551
552 static void usb_phy_fence_read(struct tegra_usb_phy *phy)
553 {
554         /* Fence read for coherency of AHB master intiated writes */
555         if (phy->inst == 0)
556                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB1_PREFETCH_ID));
557         else if (phy->inst == 1)
558                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB2_PREFETCH_ID));
559         else if (phy->inst == 2)
560                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB3_PREFETCH_ID));
561
562         return;
563 }
564
565 static void utmip_setup_pmc_wake_detect(struct tegra_usb_phy *phy)
566 {
567         unsigned long val, pmc_pad_cfg_val;
568         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
569         unsigned  int inst = phy->inst;
570         void __iomem *base = phy->regs;
571         bool port_connected;
572         enum usb_phy_port_speed port_speed;
573
574         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
575
576         /* check for port connect status */
577         val = readl(base + USB_PORTSC);
578         port_connected = val & USB_PORTSC_CCS;
579
580         if (!port_connected)
581                 return;
582
583         port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
584                 HOSTPC1_DEVLC_PSPD_MASK;
585         /*Set PMC MASTER bits to do the following
586         * a. Take over the UTMI drivers
587         * b. set up such that it will take over resume
588         *        if remote wakeup is detected
589         * Prepare PMC to take over suspend-wake detect-drive resume until USB
590         * controller ready
591         */
592
593         /* disable master enable in PMC */
594         val = readl(pmc_base + PMC_SLEEP_CFG);
595         val &= ~UTMIP_MASTER_ENABLE(inst);
596         writel(val, pmc_base + PMC_SLEEP_CFG);
597
598         /* UTMIP_PWR_PX=1 for power savings mode */
599         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
600         val |= UTMIP_PWR(inst);
601         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
602
603         /* config debouncer */
604         val = readl(pmc_base + PMC_USB_DEBOUNCE);
605         val &= ~UTMIP_LINE_DEB_CNT(~0);
606         val |= UTMIP_LINE_DEB_CNT(4);
607         writel(val, pmc_base + PMC_USB_DEBOUNCE);
608
609         /* Make sure nothing is happening on the line with respect to PMC */
610         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
611         val &= ~USBOP_VAL(inst);
612         val &= ~USBON_VAL(inst);
613         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
614
615         /* Make sure wake value for line is none */
616         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
617         val &= ~UTMIP_LINEVAL_WALK_EN(inst);
618         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
619         val = readl(pmc_base + PMC_SLEEP_CFG);
620         val &= ~UTMIP_WAKE_VAL(inst, ~0);
621         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
622         writel(val, pmc_base + PMC_SLEEP_CFG);
623
624         /* turn off pad detectors */
625         val = readl(pmc_base + PMC_USB_AO);
626         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
627         writel(val, pmc_base + PMC_USB_AO);
628
629         /* Remove fake values and make synchronizers work a bit */
630         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
631         val &= ~USBOP_VAL(inst);
632         val &= ~USBON_VAL(inst);
633         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
634
635         /* Enable which type of event can trigger a walk,
636         in this case usb_line_wake */
637         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
638         val |= UTMIP_LINEVAL_WALK_EN(inst);
639         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
640
641         /* Enable which type of event can trigger a walk,
642         * in this case usb_line_wake */
643         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
644         val |= UTMIP_LINEVAL_WALK_EN(inst);
645         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
646
647         /* Capture FS/LS pad configurations */
648         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
649         val = readl(pmc_base + PMC_TRIGGERS);
650         val |= UTMIP_CAP_CFG(inst);
651         writel(val, pmc_base + PMC_TRIGGERS);
652         udelay(1);
653         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
654
655         /* BIAS MASTER_ENABLE=0 */
656         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
657         val &= ~BIAS_MASTER_PROG_VAL;
658         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
659
660         /* program walk sequence, maintain a J, followed by a driven K
661         * to signal a resume once an wake event is detected */
662         val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
663         val &= ~UTMIP_AP_A;
664         val |= UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_AN_A |UTMIP_HIGHZ_A |
665                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_AP_B | UTMIP_AN_B |
666                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_AP_C | UTMIP_AN_C |
667                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_AP_D | UTMIP_AN_D;
668         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
669
670         if (port_speed == USB_PHY_PORT_SPEED_LOW) {
671                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
672                 val &= ~(UTMIP_AN_B | UTMIP_HIGHZ_B | UTMIP_AN_C |
673                         UTMIP_HIGHZ_C | UTMIP_AN_D | UTMIP_HIGHZ_D);
674                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
675         } else {
676                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
677                 val &= ~(UTMIP_AP_B | UTMIP_HIGHZ_B | UTMIP_AP_C |
678                         UTMIP_HIGHZ_C | UTMIP_AP_D | UTMIP_HIGHZ_D);
679                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
680         }
681
682         /* turn on pad detectors */
683         val = readl(pmc_base + PMC_USB_AO);
684         val &= ~(USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
685         writel(val, pmc_base + PMC_USB_AO);
686
687         /* Add small delay before usb detectors provide stable line values */
688         mdelay(1);
689
690         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
691         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
692         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
693         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
694
695         phy->remote_wakeup = false;
696
697         /* Turn over pad configuration to PMC  for line wake events*/
698         val = readl(pmc_base + PMC_SLEEP_CFG);
699         val &= ~UTMIP_WAKE_VAL(inst, ~0);
700         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_ANY);
701         val |= UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst);
702         val |= UTMIP_MASTER_ENABLE(inst) | UTMIP_FSLS_USE_PMC(inst);
703         writel(val, pmc_base + PMC_SLEEP_CFG);
704
705         val = readl(base + UTMIP_PMC_WAKEUP0);
706         val |= EVENT_INT_ENB;
707         writel(val, base + UTMIP_PMC_WAKEUP0);
708         PHY_DBG("%s ENABLE_PMC inst = %d\n", __func__, inst);
709 }
710
711 static void utmip_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy)
712 {
713         unsigned long val;
714         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
715         unsigned  int inst = phy->inst;
716         void __iomem *base = phy->regs;
717
718         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
719
720         val = readl(pmc_base + PMC_SLEEP_CFG);
721         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
722         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
723         writel(val, pmc_base + PMC_SLEEP_CFG);
724
725         val = readl(base + UTMIP_PMC_WAKEUP0);
726         val &= ~EVENT_INT_ENB;
727         writel(val, base + UTMIP_PMC_WAKEUP0);
728
729         /* Disable PMC master mode by clearing MASTER_EN */
730         val = readl(pmc_base + PMC_SLEEP_CFG);
731         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
732                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
733         writel(val, pmc_base + PMC_SLEEP_CFG);
734
735         val = readl(pmc_base + PMC_TRIGGERS);
736         val &= ~UTMIP_CAP_CFG(inst);
737         writel(val, pmc_base + PMC_TRIGGERS);
738
739         /* turn off pad detectors */
740         val = readl(pmc_base + PMC_USB_AO);
741         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
742         writel(val, pmc_base + PMC_USB_AO);
743
744         val = readl(pmc_base + PMC_TRIGGERS);
745         val |= UTMIP_CLR_WALK_PTR(inst);
746         writel(val, pmc_base + PMC_TRIGGERS);
747
748         phy->remote_wakeup = false;
749         PHY_DBG("%s DISABLE_PMC inst = %d\n", __func__, inst);
750 }
751
752 static bool utmi_phy_remotewake_detected(struct tegra_usb_phy *phy)
753 {
754         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
755         void __iomem *base = phy->regs;
756         unsigned  int inst = phy->inst;
757         u32 val;
758
759         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
760         val = readl(base + UTMIP_PMC_WAKEUP0);
761         if (val & EVENT_INT_ENB) {
762                 val = readl(pmc_base + UTMIP_UHSIC_STATUS);
763                 if (UTMIP_WAKE_ALARM(inst) & val) {
764                         val = readl(pmc_base + PMC_SLEEP_CFG);
765                         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
766                         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
767                         writel(val, pmc_base + PMC_SLEEP_CFG);
768
769                         val = readl(pmc_base + PMC_TRIGGERS);
770                         val |= UTMIP_CLR_WAKE_ALARM(inst);
771                         writel(val, pmc_base + PMC_TRIGGERS);
772
773                         val = readl(base + UTMIP_PMC_WAKEUP0);
774                         val &= ~EVENT_INT_ENB;
775                         writel(val, base + UTMIP_PMC_WAKEUP0);
776                         phy->remote_wakeup = true;
777                         return true;
778                 }
779         }
780         return false;
781 }
782
783 static void utmi_phy_enable_trking_data(struct tegra_usb_phy *phy)
784 {
785         void __iomem *base = IO_ADDRESS(TEGRA_USB_BASE);
786         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
787         static bool init_done = false;
788         u32 val;
789
790         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
791
792         /* Should be done only once after system boot */
793         if (init_done)
794                 return;
795
796         clk_enable(phy->utmi_pad_clk);
797         /* Bias pad MASTER_ENABLE=1 */
798         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
799         val |= BIAS_MASTER_PROG_VAL;
800         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
801
802         /* Setting the tracking length time */
803         val = readl(base + UTMIP_BIAS_CFG1);
804         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
805         val |= UTMIP_BIAS_PDTRK_COUNT(5);
806         writel(val, base + UTMIP_BIAS_CFG1);
807
808         /* Bias PDTRK is Shared and MUST be done from USB1 ONLY, PD_TRK=0 */
809         val = readl(base + UTMIP_BIAS_CFG1);
810         val &= ~UTMIP_BIAS_PDTRK_POWERDOWN;
811         writel(val, base + UTMIP_BIAS_CFG1);
812
813         val = readl(base + UTMIP_BIAS_CFG1);
814         val |= UTMIP_BIAS_PDTRK_POWERUP;
815         writel(val, base + UTMIP_BIAS_CFG1);
816
817         /* Wait for 25usec */
818         udelay(25);
819
820         /* Bias pad MASTER_ENABLE=0 */
821         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
822         val &= ~BIAS_MASTER_PROG_VAL;
823         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
824
825         /* Wait for 1usec */
826         udelay(1);
827
828         /* Bias pad MASTER_ENABLE=1 */
829         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
830         val |= BIAS_MASTER_PROG_VAL;
831         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
832
833         /* Read RCTRL and TCTRL from UTMIP space */
834         val = readl(base + UTMIP_BIAS_STS0);
835         utmip_rctrl_val = ffz(UTMIP_RCTRL_VAL(val));
836         utmip_tctrl_val = ffz(UTMIP_TCTRL_VAL(val));
837
838         /* PD_TRK=1 */
839         val = readl(base + UTMIP_BIAS_CFG1);
840         val |= UTMIP_BIAS_PDTRK_POWERDOWN;
841         writel(val, base + UTMIP_BIAS_CFG1);
842
843         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
844         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
845         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
846         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
847         clk_disable(phy->utmi_pad_clk);
848         init_done = true;
849 }
850
851 static void utmip_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy)
852 {
853         unsigned long val;
854         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
855         unsigned  int inst = phy->inst;
856
857         /* power down UTMIP interfaces */
858         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
859         val |= UTMIP_PWR(inst);
860         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
861
862         /* setup sleep walk usb controller */
863         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
864                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
865                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
866                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
867         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
868
869         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
870         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
871         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
872         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
873
874         /* Turn over pad configuration to PMC */
875         val = readl(pmc_base + PMC_SLEEP_CFG);
876         val &= ~UTMIP_WAKE_VAL(inst, ~0);
877         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE) |
878                 UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
879                 UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst);
880         writel(val, pmc_base + PMC_SLEEP_CFG);
881         PHY_DBG("%s ENABLE_PMC inst = %d\n", __func__, inst);
882 }
883
884 static void utmip_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
885 {
886         unsigned long val;
887         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
888         unsigned  int inst = phy->inst;
889
890         /* Disable PMC master mode by clearing MASTER_EN */
891         val = readl(pmc_base + PMC_SLEEP_CFG);
892         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
893                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
894         writel(val, pmc_base + PMC_SLEEP_CFG);
895         mdelay(1);
896         PHY_DBG("%s DISABLE_PMC inst = %d\n", __func__, inst);
897 }
898
899
900 #ifdef KERNEL_WARNING
901 static void usb_phy_power_down_pmc(void)
902 {
903         unsigned long val;
904         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
905
906         /* power down all 3 UTMIP interfaces */
907         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
908         val |= UTMIP_PWR(0) | UTMIP_PWR(1) | UTMIP_PWR(2);
909         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
910
911         /* turn on pad detectors */
912         writel(PMC_POWER_DOWN_MASK, pmc_base + PMC_USB_AO);
913
914         /* setup sleep walk fl all 3 usb controllers */
915         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
916                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
917                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
918                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
919         writel(val, pmc_base + PMC_SLEEPWALK_REG(0));
920         writel(val, pmc_base + PMC_SLEEPWALK_REG(1));
921         writel(val, pmc_base + PMC_SLEEPWALK_REG(2));
922
923         /* enable pull downs on HSIC PMC */
924         val = UHSIC_STROBE_RPD_A | UHSIC_DATA_RPD_A | UHSIC_STROBE_RPD_B |
925                 UHSIC_DATA_RPD_B | UHSIC_STROBE_RPD_C | UHSIC_DATA_RPD_C |
926                 UHSIC_STROBE_RPD_D | UHSIC_DATA_RPD_D;
927         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
928
929         /* Turn over pad configuration to PMC */
930         val = readl(pmc_base + PMC_SLEEP_CFG);
931         val &= ~UTMIP_WAKE_VAL(0, ~0);
932         val &= ~UTMIP_WAKE_VAL(1, ~0);
933         val &= ~UTMIP_WAKE_VAL(2, ~0);
934         val &= ~UHSIC_WAKE_VAL_P0(~0);
935         val |= UTMIP_WAKE_VAL(0, WAKE_VAL_NONE) | UHSIC_WAKE_VAL_P0(WAKE_VAL_NONE) |
936         UTMIP_WAKE_VAL(1, WAKE_VAL_NONE) | UTMIP_WAKE_VAL(2, WAKE_VAL_NONE) |
937         UTMIP_RCTRL_USE_PMC(0) | UTMIP_RCTRL_USE_PMC(1) | UTMIP_RCTRL_USE_PMC(2) |
938         UTMIP_TCTRL_USE_PMC(0) | UTMIP_TCTRL_USE_PMC(1) | UTMIP_TCTRL_USE_PMC(2) |
939         UTMIP_FSLS_USE_PMC(0) | UTMIP_FSLS_USE_PMC(1) | UTMIP_FSLS_USE_PMC(2) |
940         UTMIP_MASTER_ENABLE(0) | UTMIP_MASTER_ENABLE(1) | UTMIP_MASTER_ENABLE(2) |
941         UHSIC_MASTER_ENABLE_P0;
942         writel(val, pmc_base + PMC_SLEEP_CFG);
943 }
944 #endif
945
946 static int usb_phy_bringup_host_controller(struct tegra_usb_phy *phy)
947 {
948         unsigned long val;
949         void __iomem *base = phy->regs;
950
951         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
952         PHY_DBG("[%d] USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n", __LINE__,
953                 readl(base + USB_USBSTS), readl(base + USB_PORTSC),
954                                                         phy->port_speed);
955
956         /* Device is plugged in when system is in LP0 */
957         /* Bring up the controller from LP0*/
958         val = readl(base + USB_USBCMD);
959         val |= USB_CMD_RESET;
960         writel(val, base + USB_USBCMD);
961
962         if (usb_phy_reg_status_wait(base + USB_USBCMD,
963                 USB_CMD_RESET, 0, 2500) < 0) {
964                 pr_err("%s: timeout waiting for reset\n", __func__);
965         }
966
967         val = readl(base + USB_USBMODE);
968         val &= ~USB_USBMODE_MASK;
969         val |= USB_USBMODE_HOST;
970         writel(val, base + USB_USBMODE);
971         val = readl(base + HOSTPC1_DEVLC);
972         val &= ~HOSTPC1_DEVLC_PTS(~0);
973
974         if (phy->pdata->phy_intf == TEGRA_USB_PHY_INTF_HSIC)
975                 val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
976         else
977                 val |= HOSTPC1_DEVLC_STS;
978         writel(val, base + HOSTPC1_DEVLC);
979
980         /* Enable Port Power */
981         val = readl(base + USB_PORTSC);
982         val |= USB_PORTSC_PP;
983         writel(val, base + USB_PORTSC);
984         udelay(10);
985
986         /* Check if the phy resume from LP0. When the phy resume from LP0
987          * USB register will be reset.to zero */
988         if (!readl(base + USB_ASYNCLISTADDR)) {
989                 /* Program the field PTC based on the saved speed mode */
990                 val = readl(base + USB_PORTSC);
991                 val &= ~USB_PORTSC_PTC(~0);
992                 if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH)
993                         val |= USB_PORTSC_PTC(5);
994                 else if (phy->port_speed == USB_PHY_PORT_SPEED_FULL)
995                         val |= USB_PORTSC_PTC(6);
996                 else if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
997                         val |= USB_PORTSC_PTC(7);
998                 writel(val, base + USB_PORTSC);
999                 udelay(10);
1000
1001                 /* Disable test mode by setting PTC field to NORMAL_OP */
1002                 val = readl(base + USB_PORTSC);
1003                 val &= ~USB_PORTSC_PTC(~0);
1004                 writel(val, base + USB_PORTSC);
1005                 udelay(10);
1006         }
1007
1008         /* Poll until CCS is enabled */
1009         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
1010                                                  USB_PORTSC_CCS, 2000)) {
1011                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
1012         }
1013
1014         /* Poll until PE is enabled */
1015         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_PE,
1016                                                  USB_PORTSC_PE, 2000)) {
1017                 pr_err("%s: timeout waiting for USB_PORTSC_PE\n", __func__);
1018         }
1019
1020         /* Clear the PCI status, to avoid an interrupt taken upon resume */
1021         val = readl(base + USB_USBSTS);
1022         val |= USB_USBSTS_PCI;
1023         writel(val, base + USB_USBSTS);
1024
1025         if (!phy->remote_wakeup) {
1026                 /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
1027                 val = readl(base + USB_PORTSC);
1028                 if ((val & USB_PORTSC_PP) && (val & USB_PORTSC_PE)) {
1029                         val |= USB_PORTSC_SUSP;
1030                         writel(val, base + USB_PORTSC);
1031                         /* Need a 4ms delay before the controller goes to suspend */
1032                         mdelay(4);
1033
1034                         /* Wait until port suspend completes */
1035                         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_SUSP,
1036                                                          USB_PORTSC_SUSP, 1000)) {
1037                                 pr_err("%s: timeout waiting for PORT_SUSPEND\n",
1038                                                                         __func__);
1039                         }
1040                 }
1041         }
1042         PHY_DBG("[%d] USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n", __LINE__,
1043                 readl(base + USB_USBSTS), readl(base + USB_PORTSC),
1044                                                         phy->port_speed);
1045
1046         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1047                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1048         return 0;
1049 }
1050
1051 static void usb_phy_wait_for_sof(struct tegra_usb_phy *phy)
1052 {
1053         unsigned long val;
1054         void __iomem *base = phy->regs;
1055
1056         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1057
1058         val = readl(base + USB_USBSTS);
1059         writel(val, base + USB_USBSTS);
1060         udelay(20);
1061         /* wait for two SOFs */
1062         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1063                 USB_USBSTS_SRI, 2500))
1064                 pr_err("%s: timeout waiting for SOF\n", __func__);
1065
1066         val = readl(base + USB_USBSTS);
1067         writel(val, base + USB_USBSTS);
1068         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI, 0, 2500))
1069                 pr_err("%s: timeout waiting for SOF\n", __func__);
1070
1071         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1072                         USB_USBSTS_SRI, 2500))
1073                 pr_err("%s: timeout waiting for SOF\n", __func__);
1074
1075         udelay(20);
1076 }
1077
1078 static unsigned int utmi_phy_xcvr_setup_value(struct tegra_usb_phy *phy)
1079 {
1080         struct tegra_utmi_config *cfg = &phy->pdata->u_cfg.utmi;
1081         signed long val;
1082
1083         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1084
1085         if (cfg->xcvr_use_fuses) {
1086                 val = XCVR_SETUP(tegra_fuse_readl(FUSE_USB_CALIB_0));
1087                 if (cfg->xcvr_use_lsb) {
1088                         val = min((unsigned int) ((val & XCVR_SETUP_LSB_MASK)
1089                                 + cfg->xcvr_setup_offset),
1090                                 (unsigned int) XCVR_SETUP_LSB_MAX_VAL);
1091                         val |= (cfg->xcvr_setup & XCVR_SETUP_MSB_MASK);
1092                 } else {
1093                         if (cfg->xcvr_setup_offset <= UTMIP_XCVR_MAX_OFFSET)
1094                                 val = val + cfg->xcvr_setup_offset;
1095
1096                         if (val > UTMIP_XCVR_SETUP_MAX_VALUE) {
1097                                 val = UTMIP_XCVR_SETUP_MAX_VALUE;
1098                                 pr_info("%s: reset XCVR_SETUP to max value\n",
1099                                                 __func__);
1100                         } else if (val < UTMIP_XCVR_SETUP_MIN_VALUE) {
1101                                 val = UTMIP_XCVR_SETUP_MIN_VALUE;
1102                                 pr_info("%s: reset XCVR_SETUP to min value\n",
1103                                                 __func__);
1104                         }
1105                 }
1106         } else {
1107                 val = cfg->xcvr_setup;
1108         }
1109
1110         return (unsigned int) val;
1111 }
1112
1113 static int utmi_phy_open(struct tegra_usb_phy *phy)
1114 {
1115         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1116         unsigned long parent_rate, val;
1117         int i;
1118
1119         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1120
1121         phy->utmi_pad_clk = clk_get_sys("utmip-pad", NULL);
1122         if (IS_ERR(phy->utmi_pad_clk)) {
1123                 pr_err("%s: can't get utmip pad clock\n", __func__);
1124                 return PTR_ERR(phy->utmi_pad_clk);
1125         }
1126
1127         phy->utmi_xcvr_setup = utmi_phy_xcvr_setup_value(phy);
1128
1129         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
1130         for (i = 0; i < ARRAY_SIZE(utmip_freq_table); i++) {
1131                 if (utmip_freq_table[i].freq == parent_rate) {
1132                         phy->freq = &utmip_freq_table[i];
1133                         break;
1134                 }
1135         }
1136         if (!phy->freq) {
1137                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
1138                 return -EINVAL;
1139         }
1140
1141         /* Power-up the VBUS detector for UTMIP PHY */
1142         val = readl(pmc_base + PMC_USB_AO);
1143         val &= ~(PMC_USB_AO_VBUS_WAKEUP_PD_P0 | PMC_USB_AO_ID_PD_P0);
1144         writel((val | PMC_USB_AO_PD_P2), (pmc_base + PMC_USB_AO));
1145
1146         utmip_powerup_pmc_wake_detect(phy);
1147
1148         return 0;
1149 }
1150
1151 static void utmi_phy_close(struct tegra_usb_phy *phy)
1152 {
1153         unsigned long val;
1154         void __iomem *base = phy->regs;
1155
1156         DBG("%s inst:[%d]\n", __func__, phy->inst);
1157
1158         /* Disable PHY clock valid interrupts while going into suspend*/
1159         if (phy->pdata->u_data.host.hot_plug) {
1160                 val = readl(base + USB_SUSP_CTRL);
1161                 val &= ~USB_PHY_CLK_VALID_INT_ENB;
1162                 writel(val, base + USB_SUSP_CTRL);
1163         }
1164
1165         clk_put(phy->utmi_pad_clk);
1166 }
1167
1168 static int utmi_phy_pad_power_on(struct tegra_usb_phy *phy)
1169 {
1170         unsigned long val, flags;
1171         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1172
1173         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1174
1175         clk_enable(phy->utmi_pad_clk);
1176
1177         spin_lock_irqsave(&utmip_pad_lock, flags);
1178         utmip_pad_count++;
1179
1180         val = readl(pad_base + UTMIP_BIAS_CFG0);
1181         val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
1182         val |= UTMIP_HSSQUELCH_LEVEL(0x2) | UTMIP_HSDISCON_LEVEL(0x1) |
1183                 UTMIP_HSDISCON_LEVEL_MSB;
1184         writel(val, pad_base + UTMIP_BIAS_CFG0);
1185
1186         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1187
1188         clk_disable(phy->utmi_pad_clk);
1189
1190         return 0;
1191 }
1192
1193 static int utmi_phy_pad_power_off(struct tegra_usb_phy *phy)
1194 {
1195         unsigned long val, flags;
1196         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1197
1198         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1199
1200         clk_enable(phy->utmi_pad_clk);
1201         spin_lock_irqsave(&utmip_pad_lock, flags);
1202
1203         if (!utmip_pad_count) {
1204                 pr_err("%s: utmip pad already powered off\n", __func__);
1205                 goto out;
1206         }
1207         if (--utmip_pad_count == 0) {
1208                 val = readl(pad_base + UTMIP_BIAS_CFG0);
1209                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
1210                 val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) | UTMIP_HSDISCON_LEVEL(~0) |
1211                         UTMIP_HSDISCON_LEVEL_MSB);
1212                 writel(val, pad_base + UTMIP_BIAS_CFG0);
1213         }
1214 out:
1215         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1216         clk_disable(phy->utmi_pad_clk);
1217
1218         return 0;
1219 }
1220
1221 static int utmi_phy_irq(struct tegra_usb_phy *phy)
1222 {
1223         void __iomem *base = phy->regs;
1224         unsigned long val = 0;
1225
1226         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1227         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1228                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1229         DBG("USB_USBMODE[0x%x] USB_USBCMD[0x%x]\n",
1230                         readl(base + USB_USBMODE), readl(base + USB_USBCMD));
1231
1232         usb_phy_fence_read(phy);
1233         /* check if there is any remote wake event */
1234         if (utmi_phy_remotewake_detected(phy))
1235                 pr_info("%s: utmip remote wake detected\n", __func__);
1236
1237         if (phy->pdata->u_data.host.hot_plug) {
1238                 val = readl(base + USB_SUSP_CTRL);
1239                 if ((val  & USB_PHY_CLK_VALID_INT_STS)) {
1240                         val &= ~USB_PHY_CLK_VALID_INT_ENB |
1241                                         USB_PHY_CLK_VALID_INT_STS;
1242                         writel(val , (base + USB_SUSP_CTRL));
1243                         pr_info("%s: usb device plugged-in\n", __func__);
1244                         val = readl(base + USB_USBSTS);
1245                         if (!(val  & USB_USBSTS_PCI))
1246                                 return IRQ_NONE;
1247                         val = readl(base + USB_PORTSC);
1248                         val &= ~(USB_PORTSC_WKCN | USB_PORTSC_RWC_BITS);
1249                         writel(val , (base + USB_PORTSC));
1250                 }
1251         }
1252
1253         return IRQ_HANDLED;
1254 }
1255
1256 static void utmi_phy_enable_obs_bus(struct tegra_usb_phy *phy)
1257 {
1258         unsigned long val;
1259         void __iomem *base = phy->regs;
1260
1261         /* (2LS WAR)is not required for LS and FS devices and is only for HS */
1262         if ((phy->port_speed == USB_PHY_PORT_SPEED_LOW) ||
1263                 (phy->port_speed == USB_PHY_PORT_SPEED_FULL)) {
1264                 /* do not enable the OBS bus */
1265                 val = readl(base + UTMIP_MISC_CFG0);
1266                 val &= ~(UTMIP_DPDM_OBSERVE_SEL(~0));
1267                 writel(val, base + UTMIP_MISC_CFG0);
1268                 DBG("%s(%d) Disable OBS bus\n", __func__, __LINE__);
1269                 return;
1270         }
1271         /* Force DP/DM pulldown active for Host mode */
1272         val = readl(base + UTMIP_MISC_CFG0);
1273         val |= FORCE_PULLDN_DM | FORCE_PULLDN_DP |
1274                         COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS;
1275         writel(val, base + UTMIP_MISC_CFG0);
1276         val = readl(base + UTMIP_MISC_CFG0);
1277         val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1278         if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
1279                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
1280         else
1281                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
1282         writel(val, base + UTMIP_MISC_CFG0);
1283         udelay(1);
1284
1285         val = readl(base + UTMIP_MISC_CFG0);
1286         val |= UTMIP_DPDM_OBSERVE;
1287         writel(val, base + UTMIP_MISC_CFG0);
1288         udelay(10);
1289         DBG("%s(%d) Enable OBS bus\n", __func__, __LINE__);
1290         PHY_DBG("ENABLE_OBS_BUS\n");
1291 }
1292
1293 static int utmi_phy_disable_obs_bus(struct tegra_usb_phy *phy)
1294 {
1295         unsigned long val;
1296         void __iomem *base = phy->regs;
1297         unsigned long flags;
1298
1299         /* check if OBS bus is already enabled */
1300         val = readl(base + UTMIP_MISC_CFG0);
1301         if (val & UTMIP_DPDM_OBSERVE) {
1302                 PHY_DBG("DISABLE_OBS_BUS\n");
1303
1304                 /* disable ALL interrupts on current CPU */
1305                 local_irq_save(flags);
1306
1307                 /* Change the UTMIP OBS bus to drive SE0 */
1308                 val = readl(base + UTMIP_MISC_CFG0);
1309                 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1310                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_SE0;
1311                 writel(val, base + UTMIP_MISC_CFG0);
1312
1313                 /* Wait for 3us(2 LS bit times) */
1314                 udelay(3);
1315
1316                 /* Release UTMIP OBS bus */
1317                 val = readl(base + UTMIP_MISC_CFG0);
1318                 val &= ~UTMIP_DPDM_OBSERVE;
1319                 writel(val, base + UTMIP_MISC_CFG0);
1320
1321                 /* Release DP/DM pulldown for Host mode */
1322                 val = readl(base + UTMIP_MISC_CFG0);
1323                 val &= ~(FORCE_PULLDN_DM | FORCE_PULLDN_DP |
1324                                 COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS);
1325                 writel(val, base + UTMIP_MISC_CFG0);
1326
1327                 val = readl(base + USB_USBCMD);
1328                 val |= USB_USBCMD_RS;
1329                 writel(val, base + USB_USBCMD);
1330
1331                 /* restore ALL interrupts on current CPU */
1332                 local_irq_restore(flags);
1333
1334                 if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
1335                                                          USB_USBCMD_RS, 2000)) {
1336                         pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
1337                         return -ETIMEDOUT;
1338                 }
1339         }
1340         return 0;
1341 }
1342
1343 static int utmi_phy_post_resume(struct tegra_usb_phy *phy)
1344 {
1345         unsigned long val;
1346         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1347         unsigned  int inst = phy->inst;
1348
1349         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1350         val = readl(pmc_base + PMC_SLEEP_CFG);
1351         /* if PMC is not disabled by now then disable it */
1352         if (val & UTMIP_MASTER_ENABLE(inst)) {
1353                 utmip_phy_disable_pmc_bus_ctrl(phy);
1354         }
1355
1356         utmi_phy_disable_obs_bus(phy);
1357
1358         return 0;
1359 }
1360
1361 static int phy_post_suspend(struct tegra_usb_phy *phy)
1362 {
1363
1364         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1365         /* Need a 4ms delay for controller to suspend */
1366         mdelay(4);
1367
1368         return 0;
1369
1370 }
1371
1372 static int utmi_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1373 {
1374         unsigned long val;
1375         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1376         void __iomem *base = phy->regs;
1377         unsigned  int inst = phy->inst;
1378
1379         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1380         phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
1381                         HOSTPC1_DEVLC_PSPD_MASK;
1382
1383         if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH) {
1384                 /* Disable interrupts */
1385                 writel(0, base + USB_USBINTR);
1386                 /* Clear the run bit to stop SOFs - 2LS WAR */
1387                 val = readl(base + USB_USBCMD);
1388                 val &= ~USB_USBCMD_RS;
1389                 writel(val, base + USB_USBCMD);
1390                 if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
1391                                                          USB_USBSTS_HCH, 2000)) {
1392                         pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
1393                 }
1394         }
1395
1396         val = readl(pmc_base + PMC_SLEEP_CFG);
1397         if (val & UTMIP_MASTER_ENABLE(inst)) {
1398                 if (!remote_wakeup)
1399                         utmip_phy_disable_pmc_bus_ctrl(phy);
1400         } else {
1401                 utmi_phy_enable_obs_bus(phy);
1402         }
1403
1404         return 0;
1405 }
1406
1407 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
1408 {
1409         unsigned long val;
1410         void __iomem *base = phy->regs;
1411
1412         PHY_DBG("%s(%d) inst:[%d] BEGIN\n", __func__, __LINE__, phy->inst);
1413         if (!phy->phy_clk_on) {
1414                 PHY_DBG("%s(%d) inst:[%d] phy clk is already off\n",
1415                                         __func__, __LINE__, phy->inst);
1416                 return 0;
1417         }
1418
1419         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1420                 utmip_powerdown_pmc_wake_detect(phy);
1421
1422                 val = readl(base + USB_SUSP_CTRL);
1423                 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
1424                 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
1425                 writel(val, base + USB_SUSP_CTRL);
1426
1427                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1428                 val |= UTMIP_PD_CHRG;
1429                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1430         } else {
1431                 phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
1432                                 HOSTPC1_DEVLC_PSPD_MASK;
1433
1434                 /* Disable interrupts */
1435                 writel(0, base + USB_USBINTR);
1436
1437                 /* Clear the run bit to stop SOFs - 2LS WAR */
1438                 val = readl(base + USB_USBCMD);
1439                 val &= ~USB_USBCMD_RS;
1440                 writel(val, base + USB_USBCMD);
1441
1442                 if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
1443                                                          USB_USBSTS_HCH, 2000)) {
1444                         pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
1445                 }
1446                 utmip_setup_pmc_wake_detect(phy);
1447         }
1448
1449         if (!phy->pdata->u_data.host.hot_plug) {
1450                 val = readl(base + UTMIP_XCVR_CFG0);
1451                 val |= (UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
1452                          UTMIP_FORCE_PDZI_POWERDOWN);
1453                 writel(val, base + UTMIP_XCVR_CFG0);
1454         }
1455
1456         val = readl(base + UTMIP_XCVR_CFG1);
1457         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1458                    UTMIP_FORCE_PDDR_POWERDOWN;
1459         writel(val, base + UTMIP_XCVR_CFG1);
1460
1461         val = readl(base + UTMIP_BIAS_CFG1);
1462         val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
1463         writel(val, base + UTMIP_BIAS_CFG1);
1464
1465         utmi_phy_pad_power_off(phy);
1466
1467         if (phy->pdata->u_data.host.hot_plug) {
1468                 bool enable_hotplug = true;
1469                 /* if it is OTG port then make sure to enable hot-plug feature
1470                    only if host adaptor is connected, i.e id is low */
1471                 if (phy->pdata->port_otg) {
1472                         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1473                         enable_hotplug = (val & USB_ID_STATUS) ? false : true;
1474                 }
1475                 if (enable_hotplug) {
1476                         val = readl(base + USB_PORTSC);
1477                         val |= USB_PORTSC_WKCN;
1478                         writel(val, base + USB_PORTSC);
1479
1480                         val = readl(base + USB_SUSP_CTRL);
1481                         val |= USB_PHY_CLK_VALID_INT_ENB;
1482                         writel(val, base + USB_SUSP_CTRL);
1483                 } else {
1484                         /* Disable PHY clock valid interrupts while going into suspend*/
1485                         val = readl(base + USB_SUSP_CTRL);
1486                         val &= ~USB_PHY_CLK_VALID_INT_ENB;
1487                         writel(val, base + USB_SUSP_CTRL);
1488                 }
1489         }
1490
1491         val = readl(base + HOSTPC1_DEVLC);
1492         val |= HOSTPC1_DEVLC_PHCD;
1493         writel(val, base + HOSTPC1_DEVLC);
1494
1495         if (!phy->pdata->u_data.host.hot_plug) {
1496                 val = readl(base + USB_SUSP_CTRL);
1497                 val |= UTMIP_RESET;
1498                 writel(val, base + USB_SUSP_CTRL);
1499         }
1500
1501         phy->phy_clk_on = false;
1502         phy->hw_accessible = false;
1503
1504         PHY_DBG("%s(%d) inst:[%d] END\n", __func__, __LINE__, phy->inst);
1505
1506         return 0;
1507 }
1508
1509
1510 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
1511 {
1512         unsigned long val;
1513         void __iomem *base = phy->regs;
1514         struct tegra_utmi_config *config = &phy->pdata->u_cfg.utmi;
1515
1516         PHY_DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1517         if (phy->phy_clk_on) {
1518                 PHY_DBG("%s(%d) inst:[%d] phy clk is already On\n",
1519                                         __func__, __LINE__, phy->inst);
1520                 return 0;
1521         }
1522         val = readl(base + USB_SUSP_CTRL);
1523         val |= UTMIP_RESET;
1524         writel(val, base + USB_SUSP_CTRL);
1525
1526         val = readl(base + UTMIP_TX_CFG0);
1527         val |= UTMIP_FS_PREABMLE_J;
1528         writel(val, base + UTMIP_TX_CFG0);
1529
1530         val = readl(base + UTMIP_HSRX_CFG0);
1531         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
1532         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
1533         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
1534         writel(val, base + UTMIP_HSRX_CFG0);
1535
1536         val = readl(base + UTMIP_HSRX_CFG1);
1537         val &= ~UTMIP_HS_SYNC_START_DLY(~0);
1538         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
1539         writel(val, base + UTMIP_HSRX_CFG1);
1540
1541         val = readl(base + UTMIP_DEBOUNCE_CFG0);
1542         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
1543         val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
1544         writel(val, base + UTMIP_DEBOUNCE_CFG0);
1545
1546         val = readl(base + UTMIP_MISC_CFG0);
1547         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
1548         writel(val, base + UTMIP_MISC_CFG0);
1549
1550         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1551                 val = readl(base + USB_SUSP_CTRL);
1552                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
1553                 writel(val, base + USB_SUSP_CTRL);
1554
1555                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1556                 val &= ~UTMIP_PD_CHRG;
1557                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1558         } else {
1559                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1560                 val |= UTMIP_PD_CHRG;
1561                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1562         }
1563
1564         utmi_phy_pad_power_on(phy);
1565
1566         val = readl(base + UTMIP_XCVR_CFG0);
1567         val &= ~(UTMIP_XCVR_LSBIAS_SEL | UTMIP_FORCE_PD_POWERDOWN |
1568                  UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN |
1569                  UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_LSFSLEW(~0) |
1570                  UTMIP_XCVR_LSRSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
1571         val |= UTMIP_XCVR_SETUP(phy->utmi_xcvr_setup);
1572         val |= UTMIP_XCVR_SETUP_MSB(XCVR_SETUP_MSB_CALIB(phy->utmi_xcvr_setup));
1573         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
1574         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
1575         if (!config->xcvr_use_lsb)
1576                 val |= UTMIP_XCVR_HSSLEW_MSB(0x8);
1577         writel(val, base + UTMIP_XCVR_CFG0);
1578
1579         val = readl(base + UTMIP_XCVR_CFG1);
1580         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1581                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
1582         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
1583         writel(val, base + UTMIP_XCVR_CFG1);
1584
1585         val = readl(base + UTMIP_BIAS_CFG1);
1586         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
1587         val |= UTMIP_BIAS_PDTRK_COUNT(phy->freq->pdtrk_count);
1588         writel(val, base + UTMIP_BIAS_CFG1);
1589
1590         val = readl(base + UTMIP_SPARE_CFG0);
1591         val &= ~FUSE_SETUP_SEL;
1592         val |= FUSE_ATERM_SEL;
1593         writel(val, base + UTMIP_SPARE_CFG0);
1594
1595         val = readl(base + USB_SUSP_CTRL);
1596         val |= UTMIP_PHY_ENABLE;
1597         writel(val, base + USB_SUSP_CTRL);
1598
1599         val = readl(base + USB_SUSP_CTRL);
1600         val &= ~UTMIP_RESET;
1601         writel(val, base + USB_SUSP_CTRL);
1602
1603         val = readl(base + HOSTPC1_DEVLC);
1604         val &= ~HOSTPC1_DEVLC_PHCD;
1605         writel(val, base + HOSTPC1_DEVLC);
1606
1607         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1608                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500))
1609                 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
1610
1611         utmi_phy_enable_trking_data(phy);
1612
1613         if (phy->inst == 2)
1614                 writel(0, base + ICUSB_CTRL);
1615
1616         val = readl(base + USB_USBMODE);
1617         val &= ~USB_USBMODE_MASK;
1618         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST)
1619                 val |= USB_USBMODE_HOST;
1620         else
1621                 val |= USB_USBMODE_DEVICE;
1622         writel(val, base + USB_USBMODE);
1623
1624         val = readl(base + HOSTPC1_DEVLC);
1625         val &= ~HOSTPC1_DEVLC_PTS(~0);
1626         val |= HOSTPC1_DEVLC_STS;
1627         writel(val, base + HOSTPC1_DEVLC);
1628
1629         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE)
1630                 utmip_powerup_pmc_wake_detect(phy);
1631         phy->phy_clk_on = true;
1632         phy->hw_accessible = true;
1633         PHY_DBG("%s(%d) End inst:[%d]\n", __func__, __LINE__, phy->inst);
1634         return 0;
1635 }
1636
1637 static void utmi_phy_restore_start(struct tegra_usb_phy *phy)
1638 {
1639         unsigned long val;
1640         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1641         int inst = phy->inst;
1642
1643         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1644         val = readl(pmc_base + UTMIP_UHSIC_STATUS);
1645         /* Check whether we wake up from the remote resume.
1646            For lp1 case, pmc is not responsible for waking the
1647            system, it's the flow controller and hence
1648            UTMIP_WALK_PTR_VAL(inst) will return 0.
1649            Also, for lp1 case phy->remote_wakeup will already be set
1650            to true by utmi_phy_irq() when the remote wakeup happens.
1651            Hence change the logic in the else part to enter only
1652            if phy->remote_wakeup is not set to true by the
1653            utmi_phy_irq(). */
1654         if (UTMIP_WALK_PTR_VAL(inst) & val) {
1655                 phy->remote_wakeup = true;
1656         } else if(!phy->remote_wakeup) {
1657                 if (!((UTMIP_USBON_VAL(phy->inst) |
1658                         UTMIP_USBOP_VAL(phy->inst)) & val)) {
1659                                 utmip_phy_disable_pmc_bus_ctrl(phy);
1660                 }
1661         }
1662         utmi_phy_enable_obs_bus(phy);
1663 }
1664
1665 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
1666 {
1667         unsigned long val;
1668         void __iomem *base = phy->regs;
1669         int wait_time_us = 25000; /* FPR should be set by this time */
1670
1671         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1672         /* check whether we wake up from the remote resume */
1673         if (phy->remote_wakeup) {
1674                 /* wait until SUSPEND and RESUME bit is cleared on remote resume */
1675                 do {
1676                         val = readl(base + USB_PORTSC);
1677                         udelay(1);
1678                         if (wait_time_us == 0) {
1679                                 PHY_DBG("%s PMC REMOTE WAKEUP FPR timeout val = 0x%x instance = %d\n", __func__, val, phy->inst);
1680                                 utmip_phy_disable_pmc_bus_ctrl(phy);
1681                                 utmi_phy_post_resume(phy);
1682                                 return;
1683                         }
1684                         wait_time_us--;
1685                 } while (val & (USB_PORTSC_RESUME | USB_PORTSC_SUSP));
1686
1687                 /* wait for 25 ms to port resume complete */
1688                 msleep(25);
1689                 /* disable PMC master control */
1690                 utmip_phy_disable_pmc_bus_ctrl(phy);
1691
1692                 /* Clear PCI and SRI bits to avoid an interrupt upon resume */
1693                 val = readl(base + USB_USBSTS);
1694                 writel(val, base + USB_USBSTS);
1695                 /* wait to avoid SOF if there is any */
1696                 if (usb_phy_reg_status_wait(base + USB_USBSTS,
1697                         USB_USBSTS_SRI, USB_USBSTS_SRI, 2500) < 0) {
1698                         pr_err("%s: timeout waiting for SOF\n", __func__);
1699                 }
1700                 utmi_phy_post_resume(phy);
1701         }
1702 }
1703
1704 static int utmi_phy_resume(struct tegra_usb_phy *phy)
1705 {
1706         int status = 0;
1707         unsigned long val;
1708         void __iomem *base = phy->regs;
1709
1710         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1711         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) {
1712                 if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
1713                         utmi_phy_restore_start(phy);
1714                         usb_phy_bringup_host_controller(phy);
1715                         utmi_phy_restore_end(phy);
1716                 } else {
1717                         /* device is plugged in when system is in LP0 */
1718                         /* bring up the controller from LP0*/
1719                         val = readl(base + USB_USBCMD);
1720                         val |= USB_CMD_RESET;
1721                         writel(val, base + USB_USBCMD);
1722
1723                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1724                                 USB_CMD_RESET, 0, 2500) < 0) {
1725                                 pr_err("%s: timeout waiting for reset\n", __func__);
1726                         }
1727
1728                         val = readl(base + USB_USBMODE);
1729                         val &= ~USB_USBMODE_MASK;
1730                         val |= USB_USBMODE_HOST;
1731                         writel(val, base + USB_USBMODE);
1732
1733                         val = readl(base + HOSTPC1_DEVLC);
1734                         val &= ~HOSTPC1_DEVLC_PTS(~0);
1735                         val |= HOSTPC1_DEVLC_STS;
1736                         writel(val, base + HOSTPC1_DEVLC);
1737
1738                         writel(USB_USBCMD_RS, base + USB_USBCMD);
1739
1740                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1741                                 USB_USBCMD_RS, USB_USBCMD_RS, 2500) < 0) {
1742                                 pr_err("%s: timeout waiting for run bit\n", __func__);
1743                         }
1744
1745                         /* Enable Port Power */
1746                         val = readl(base + USB_PORTSC);
1747                         val |= USB_PORTSC_PP;
1748                         writel(val, base + USB_PORTSC);
1749                         udelay(10);
1750
1751                         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1752                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1753                 }
1754         }
1755
1756         return status;
1757 }
1758
1759 static bool utmi_phy_charger_detect(struct tegra_usb_phy *phy)
1760 {
1761         unsigned long val;
1762         void __iomem *base = phy->regs;
1763         bool status;
1764
1765         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1766         if (phy->pdata->op_mode != TEGRA_USB_OPMODE_DEVICE) {
1767                 /* Charger detection is not there for ULPI
1768                  * return Charger not available */
1769                 return false;
1770         }
1771
1772         /* Enable charger detection logic */
1773         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1774         val |= UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN;
1775         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1776
1777         /* Source should be on for 100 ms as per USB charging spec */
1778         msleep(TDP_SRC_ON_MS);
1779
1780         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1781         /* If charger is not connected disable the interrupt */
1782         val &= ~VDAT_DET_INT_EN;
1783         val |= VDAT_DET_CHG_DET;
1784         writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
1785
1786         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1787         if (val & VDAT_DET_STS)
1788                 status = true;
1789         else
1790                 status = false;
1791
1792         /* Disable charger detection logic */
1793         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1794         val &= ~(UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN);
1795         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1796
1797         /* Delay of 40 ms before we pull the D+ as per battery charger spec */
1798         msleep(TDPSRC_CON_MS);
1799
1800         return status;
1801 }
1802
1803 static void uhsic_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
1804 {
1805         unsigned long val;
1806         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1807
1808         /* turn on pad detectors for HSIC*/
1809         val = readl(pmc_base + PMC_USB_AO);
1810         val &= ~(HSIC_RESERVED_P0 | STROBE_VAL_PD_P0 | DATA_VAL_PD_P0);
1811         writel(val, pmc_base + PMC_USB_AO);
1812
1813         /* Disable PMC master mode by clearing MASTER_EN */
1814         val = readl(pmc_base + PMC_SLEEP_CFG);
1815         val &= ~(UHSIC_MASTER_ENABLE_P0);
1816         writel(val, pmc_base + PMC_SLEEP_CFG);
1817         mdelay(1);
1818 }
1819
1820 static void uhsic_setup_pmc_wake_detect(struct tegra_usb_phy *phy)
1821 {
1822         unsigned long val;
1823         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1824         void __iomem *base = phy->regs;
1825         bool port_connected;
1826
1827         DBG("%s:%d\n", __func__, __LINE__);
1828
1829         /* check for port connect status */
1830         val = readl(base + USB_PORTSC);
1831         port_connected = val & USB_PORTSC_CCS;
1832
1833         if (!port_connected)
1834                 return;
1835
1836         /*Set PMC MASTER bits to do the following
1837         * a. Take over the hsic drivers
1838         * b. set up such that it will take over resume
1839         *        if remote wakeup is detected
1840         * Prepare PMC to take over suspend-wake detect-drive resume until USB
1841         * controller ready
1842         */
1843
1844         /* disable master enable in PMC */
1845         val = readl(pmc_base + PMC_SLEEP_CFG);
1846         val &= ~UHSIC_MASTER_ENABLE_P0;
1847         writel(val, pmc_base + PMC_SLEEP_CFG);
1848
1849         /* UTMIP_PWR_PX=1 for power savings mode */
1850         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
1851         val |= UHSIC_PWR;
1852         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
1853
1854
1855         /* Enable which type of event can trigger a walk,
1856         * in this case usb_line_wake */
1857         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
1858         val |= UHSIC_LINEVAL_WALK_EN;
1859         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
1860
1861         /* program walk sequence, maintain a J, followed by a driven K
1862         * to signal a resume once an wake event is detected */
1863
1864         val = readl(pmc_base + PMC_SLEEPWALK_UHSIC);
1865
1866         val &= ~UHSIC_DATA_RPU_A;
1867         val |=  UHSIC_DATA_RPD_A;
1868         val &= ~UHSIC_STROBE_RPD_A;
1869         val |=  UHSIC_STROBE_RPU_A;
1870         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1871
1872         val &= ~UHSIC_DATA_RPD_B;
1873         val |=  UHSIC_DATA_RPU_B;
1874         val &= ~UHSIC_STROBE_RPU_B;
1875         val |=  UHSIC_STROBE_RPD_B;
1876         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1877
1878         val &= ~UHSIC_DATA_RPD_C;
1879         val |=  UHSIC_DATA_RPU_C;
1880         val &= ~UHSIC_STROBE_RPU_C;
1881         val |=  UHSIC_STROBE_RPD_C;
1882         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1883
1884         val &= ~UHSIC_DATA_RPD_D;
1885         val |=  UHSIC_DATA_RPU_D;
1886         val &= ~UHSIC_STROBE_RPU_D;
1887         val |=  UHSIC_STROBE_RPD_D;
1888         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1889
1890         /* turn on pad detectors */
1891         val = readl(pmc_base + PMC_USB_AO);
1892         val &= ~(STROBE_VAL_PD_P0 | DATA_VAL_PD_P0);
1893         writel(val, pmc_base + PMC_USB_AO);
1894         /* Add small delay before usb detectors provide stable line values */
1895         udelay(1);
1896
1897         phy->remote_wakeup = false;
1898
1899         /* Turn over pad configuration to PMC  for line wake events*/
1900         val = readl(pmc_base + PMC_SLEEP_CFG);
1901         val &= ~UHSIC_WAKE_VAL(~0);
1902         val |= UHSIC_WAKE_VAL(WAKE_VAL_SD10);
1903         val |= UHSIC_MASTER_ENABLE;
1904         writel(val, pmc_base + PMC_SLEEP_CFG);
1905
1906         val = readl(base + UHSIC_PMC_WAKEUP0);
1907         val |= EVENT_INT_ENB;
1908         writel(val, base + UHSIC_PMC_WAKEUP0);
1909
1910         DBG("%s:PMC enabled for HSIC remote wakeup\n", __func__);
1911 }
1912
1913 static void uhsic_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy)
1914 {
1915         unsigned long val;
1916         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1917         void __iomem *base = phy->regs;
1918
1919         DBG("%s (%d)\n", __func__, __LINE__);
1920         val = readl(pmc_base + PMC_SLEEP_CFG);
1921         val &= ~UHSIC_WAKE_VAL(0x0);
1922         val |= UHSIC_WAKE_VAL(WAKE_VAL_NONE);
1923         writel(val, pmc_base + PMC_SLEEP_CFG);
1924
1925         val = readl(pmc_base + PMC_TRIGGERS);
1926         val |= UHSIC_CLR_WAKE_ALARM_P0 | UHSIC_CLR_WALK_PTR_P0;
1927         writel(val, pmc_base + PMC_TRIGGERS);
1928
1929         val = readl(base + UHSIC_PMC_WAKEUP0);
1930         val &= ~EVENT_INT_ENB;
1931         writel(val, base + UHSIC_PMC_WAKEUP0);
1932
1933         /* Disable PMC master mode by clearing MASTER_EN */
1934         val = readl(pmc_base + PMC_SLEEP_CFG);
1935         val &= ~(UHSIC_MASTER_ENABLE);
1936         writel(val, pmc_base + PMC_SLEEP_CFG);
1937
1938         /* turn off pad detectors */
1939         val = readl(pmc_base + PMC_USB_AO);
1940         val |= (STROBE_VAL_PD_P0 | DATA_VAL_PD_P0);
1941         writel(val, pmc_base + PMC_USB_AO);
1942
1943         phy->remote_wakeup = false;
1944 }
1945
1946 static bool uhsic_phy_remotewake_detected(struct tegra_usb_phy *phy)
1947 {
1948         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1949         void __iomem *base = phy->regs;
1950         u32 val;
1951
1952         val = readl(base + UHSIC_PMC_WAKEUP0);
1953         if (val & EVENT_INT_ENB) {
1954                 val = readl(pmc_base + UTMIP_UHSIC_STATUS);
1955                 if (UHSIC_WAKE_ALARM & val) {
1956                         val = readl(pmc_base + PMC_SLEEP_CFG);
1957                         val &= ~UHSIC_WAKE_VAL(0x0);
1958                         val |= UHSIC_WAKE_VAL(WAKE_VAL_NONE);
1959                         writel(val, pmc_base + PMC_SLEEP_CFG);
1960
1961                         val = readl(pmc_base + PMC_TRIGGERS);
1962                         val |= UHSIC_CLR_WAKE_ALARM_P0 | UHSIC_CLR_WALK_PTR_P0;
1963                         writel(val, pmc_base + PMC_TRIGGERS);
1964
1965                         val = readl(base + UHSIC_PMC_WAKEUP0);
1966                         val &= ~EVENT_INT_ENB;
1967                         writel(val, base + UHSIC_PMC_WAKEUP0);
1968                         phy->remote_wakeup = true;
1969                         DBG("%s:PMC remote wakeup detected for HSIC\n", __func__);
1970                         return true;
1971                 }
1972         }
1973         return false;
1974 }
1975
1976 static int uhsic_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1977 {
1978         DBG("%s(%d)\n", __func__, __LINE__);
1979
1980         if (!remote_wakeup)
1981                 usb_phy_wait_for_sof(phy);
1982
1983         return 0;
1984 }
1985
1986 static int uhsic_phy_post_resume(struct tegra_usb_phy *phy)
1987 {
1988         unsigned long val;
1989         void __iomem *base = phy->regs;
1990
1991         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1992         val = readl(base + USB_TXFILLTUNING);
1993         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
1994                 val = USB_FIFO_TXFILL_THRES(0x10);
1995                 writel(val, base + USB_TXFILLTUNING);
1996         }
1997
1998         return 0;
1999 }
2000
2001 static void uhsic_phy_restore_start(struct tegra_usb_phy *phy)
2002 {
2003         unsigned long val;
2004         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
2005         void __iomem *base = phy->regs;
2006
2007         val = readl(pmc_base + UTMIP_UHSIC_STATUS);
2008
2009         /* check whether we wake up from the remote resume */
2010         if (UHSIC_WALK_PTR_VAL & val) {
2011                 phy->remote_wakeup = true;
2012                 pr_info("%s: uhsic remote wakeup detected\n", __func__);
2013         } else {
2014                 if (!((UHSIC_STROBE_VAL_P0 | UHSIC_DATA_VAL_P0) & val)) {
2015                                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2016                 } else {
2017                         DBG("%s(%d): setting pretend connect\n", __func__, __LINE__);
2018                         val = readl(base + UHSIC_CMD_CFG0);
2019                         val |= UHSIC_PRETEND_CONNECT_DETECT;
2020                         writel(val, base + UHSIC_CMD_CFG0);
2021                 }
2022         }
2023 }
2024
2025 static void uhsic_phy_restore_end(struct tegra_usb_phy *phy)
2026 {
2027
2028         unsigned long val;
2029         void __iomem *base = phy->regs;
2030         int wait_time_us = 3000; /* FPR should be set by this time */
2031
2032         DBG("%s(%d)\n", __func__, __LINE__);
2033
2034         /* check whether we wake up from the remote resume */
2035         if (phy->remote_wakeup) {
2036                 /* wait until FPR bit is set automatically on remote resume */
2037                 do {
2038                         val = readl(base + USB_PORTSC);
2039                         udelay(1);
2040                         if (wait_time_us == 0) {
2041                                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2042                                 uhsic_phy_post_resume(phy);
2043                                 return;
2044                         }
2045                         wait_time_us--;
2046                 } while (!(val & USB_PORTSC_RESUME));
2047                 /* wait for 25 ms to port resume complete */
2048                 msleep(25);
2049                 /* disable PMC master control */
2050                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2051
2052                 /* Clear PCI and SRI bits to avoid an interrupt upon resume */
2053                 val = readl(base + USB_USBSTS);
2054                 writel(val, base + USB_USBSTS);
2055                 /* wait to avoid SOF if there is any */
2056                 if (usb_phy_reg_status_wait(base + USB_USBSTS,
2057                         USB_USBSTS_SRI, USB_USBSTS_SRI, 2500)) {
2058                         pr_warn("%s: timeout waiting for SOF\n", __func__);
2059                 }
2060                 uhsic_phy_post_resume(phy);
2061         } else {
2062                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2063         }
2064
2065         /* Set RUN bit */
2066         val = readl(base + USB_USBCMD);
2067         val |= USB_USBCMD_RS;
2068         writel(val, base + USB_USBCMD);
2069         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2070                                                  USB_USBCMD_RS, 2000)) {
2071                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2072                 return;
2073         }
2074 }
2075
2076 static int uhsic_phy_open(struct tegra_usb_phy *phy)
2077 {
2078         unsigned long parent_rate;
2079         int i;
2080
2081         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2082         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
2083         for (i = 0; i < ARRAY_SIZE(uhsic_freq_table); i++) {
2084                 if (uhsic_freq_table[i].freq == parent_rate) {
2085                         phy->freq = &uhsic_freq_table[i];
2086                         break;
2087                 }
2088         }
2089         if (!phy->freq) {
2090                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
2091                 return -EINVAL;
2092         }
2093
2094         uhsic_powerup_pmc_wake_detect(phy);
2095
2096         return 0;
2097 }
2098
2099 static int uhsic_phy_irq(struct tegra_usb_phy *phy)
2100 {
2101         usb_phy_fence_read(phy);
2102         /* check if there is any remote wake event */
2103         if (uhsic_phy_remotewake_detected(phy))
2104                 pr_info("%s: uhsic remote wake detected\n", __func__);
2105         return IRQ_HANDLED;
2106 }
2107
2108 static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
2109 {
2110         unsigned long val;
2111         void __iomem *base = phy->regs;
2112         struct tegra_hsic_config *config = &phy->pdata->u_cfg.hsic;
2113
2114         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2115
2116         if (phy->phy_clk_on) {
2117                 DBG("%s(%d) inst:[%d] phy clk is already On\n",
2118                                         __func__, __LINE__, phy->inst);
2119                 return 0;
2120         }
2121
2122         val = readl(base + UHSIC_PADS_CFG1);
2123         val &= ~(UHSIC_PD_BG | UHSIC_PD_TRK | UHSIC_PD_RX |
2124                         UHSIC_PD_ZI | UHSIC_RPD_DATA | UHSIC_RPD_STROBE);
2125         val |= (UHSIC_RX_SEL | UHSIC_PD_TX);
2126         writel(val, base + UHSIC_PADS_CFG1);
2127
2128         val = readl(base + USB_SUSP_CTRL);
2129         val |= UHSIC_RESET;
2130         writel(val, base + USB_SUSP_CTRL);
2131         udelay(1);
2132
2133         val = readl(base + USB_SUSP_CTRL);
2134         val |= UHSIC_PHY_ENABLE;
2135         writel(val, base + USB_SUSP_CTRL);
2136
2137         val = readl(base + UHSIC_HSRX_CFG0);
2138         val |= UHSIC_IDLE_WAIT(config->idle_wait_delay);
2139         val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(config->elastic_underrun_limit);
2140         val |= UHSIC_ELASTIC_OVERRUN_LIMIT(config->elastic_overrun_limit);
2141         writel(val, base + UHSIC_HSRX_CFG0);
2142
2143         val = readl(base + UHSIC_HSRX_CFG1);
2144         val |= UHSIC_HS_SYNC_START_DLY(config->sync_start_delay);
2145         writel(val, base + UHSIC_HSRX_CFG1);
2146
2147         /* WAR HSIC TX */
2148         val = readl(base + UHSIC_TX_CFG0);
2149         val &= ~UHSIC_HS_READY_WAIT_FOR_VALID;
2150         writel(val, base + UHSIC_TX_CFG0);
2151
2152         val = readl(base + UHSIC_MISC_CFG0);
2153         val |= UHSIC_SUSPEND_EXIT_ON_EDGE;
2154         /* Disable generic bus reset, to allow AP30 specific bus reset*/
2155         val |= UHSIC_DISABLE_BUSRESET;
2156         writel(val, base + UHSIC_MISC_CFG0);
2157
2158         val = readl(base + UHSIC_MISC_CFG1);
2159         val |= UHSIC_PLLU_STABLE_COUNT(phy->freq->stable_count);
2160         writel(val, base + UHSIC_MISC_CFG1);
2161
2162         val = readl(base + UHSIC_PLL_CFG1);
2163         val |= UHSIC_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
2164         val |= UHSIC_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count);
2165         writel(val, base + UHSIC_PLL_CFG1);
2166
2167         val = readl(base + USB_SUSP_CTRL);
2168         val &= ~(UHSIC_RESET);
2169         writel(val, base + USB_SUSP_CTRL);
2170         udelay(1);
2171
2172         val = readl(base + UHSIC_PADS_CFG1);
2173         val &= ~(UHSIC_PD_TX);
2174         writel(val, base + UHSIC_PADS_CFG1);
2175
2176         val = readl(base + USB_USBMODE);
2177         val |= USB_USBMODE_HOST;
2178         writel(val, base + USB_USBMODE);
2179
2180         /* Change the USB controller PHY type to HSIC */
2181         val = readl(base + HOSTPC1_DEVLC);
2182         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
2183         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2184         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
2185         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2186         val &= ~HOSTPC1_DEVLC_STS;
2187         writel(val, base + HOSTPC1_DEVLC);
2188
2189         val = readl(base + USB_TXFILLTUNING);
2190         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
2191                 val = USB_FIFO_TXFILL_THRES(0x10);
2192                 writel(val, base + USB_TXFILLTUNING);
2193         }
2194
2195         val = readl(base + USB_PORTSC);
2196         val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN);
2197         writel(val, base + USB_PORTSC);
2198
2199         val = readl(base + UHSIC_PADS_CFG0);
2200         val &= ~(UHSIC_TX_RTUNEN);
2201         /* set Rtune impedance to 50 ohm */
2202         val |= UHSIC_TX_RTUNE(8);
2203         writel(val, base + UHSIC_PADS_CFG0);
2204
2205         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
2206                                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500)) {
2207                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2208                 return -ETIMEDOUT;
2209         }
2210
2211         phy->phy_clk_on = true;
2212         phy->hw_accessible = true;
2213
2214         if (phy->pmc_sleepwalk) {
2215                 DBG("%s(%d) inst:[%d] restore phy\n", __func__, __LINE__,
2216                                         phy->inst);
2217                 uhsic_phy_restore_start(phy);
2218                 usb_phy_bringup_host_controller(phy);
2219                 uhsic_phy_restore_end(phy);
2220                 phy->pmc_sleepwalk = false;
2221         }
2222
2223         return 0;
2224 }
2225
2226 static int uhsic_phy_power_off(struct tegra_usb_phy *phy)
2227 {
2228         unsigned long val;
2229         void __iomem *base = phy->regs;
2230
2231         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2232         if (!phy->phy_clk_on) {
2233                 DBG("%s(%d) inst:[%d] phy clk is already off\n",
2234                                         __func__, __LINE__, phy->inst);
2235                 return 0;
2236         }
2237
2238         phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
2239                         HOSTPC1_DEVLC_PSPD_MASK;
2240
2241         /* Disable interrupts */
2242         writel(0, base + USB_USBINTR);
2243
2244         if (phy->pmc_sleepwalk == false) {
2245                 uhsic_setup_pmc_wake_detect(phy);
2246                 phy->pmc_sleepwalk = true;
2247         }
2248
2249         val = readl(base + HOSTPC1_DEVLC);
2250         val |= HOSTPC1_DEVLC_PHCD;
2251         writel(val, base + HOSTPC1_DEVLC);
2252
2253         /* Remove power downs for HSIC from PADS CFG1 register */
2254         val = readl(base + UHSIC_PADS_CFG1);
2255         val |= (UHSIC_PD_BG |UHSIC_PD_TRK | UHSIC_PD_RX |
2256                         UHSIC_PD_ZI | UHSIC_PD_TX);
2257         writel(val, base + UHSIC_PADS_CFG1);
2258         phy->phy_clk_on = false;
2259         phy->hw_accessible = false;
2260
2261         return 0;
2262 }
2263
2264 static int uhsic_phy_bus_port_power(struct tegra_usb_phy *phy)
2265 {
2266         unsigned long val;
2267         void __iomem *base = phy->regs;
2268
2269         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2270
2271         val = readl(base + USB_USBMODE);
2272         val |= USB_USBMODE_HOST;
2273         writel(val, base + USB_USBMODE);
2274
2275         /* Change the USB controller PHY type to HSIC */
2276         val = readl(base + HOSTPC1_DEVLC);
2277         val &= ~(HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK));
2278         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2279         val &= ~(HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK));
2280         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2281         writel(val, base + HOSTPC1_DEVLC);
2282
2283         val = readl(base + UHSIC_MISC_CFG0);
2284         val |= UHSIC_DETECT_SHORT_CONNECT;
2285         writel(val, base + UHSIC_MISC_CFG0);
2286         udelay(1);
2287
2288         val = readl(base + UHSIC_MISC_CFG0);
2289         val |= UHSIC_FORCE_XCVR_MODE;
2290         writel(val, base + UHSIC_MISC_CFG0);
2291
2292         val = readl(base + UHSIC_PADS_CFG1);
2293         val &= ~UHSIC_RPD_STROBE;
2294         writel(val, base + UHSIC_PADS_CFG1);
2295
2296         if (phy->pdata->ops && phy->pdata->ops->port_power)
2297                 phy->pdata->ops->port_power();
2298
2299         if (usb_phy_reg_status_wait(base + UHSIC_STAT_CFG0,
2300                         UHSIC_CONNECT_DETECT, UHSIC_CONNECT_DETECT, 25000)) {
2301                 pr_err("%s: timeout waiting for UHSIC_CONNECT_DETECT\n",
2302                                                                 __func__);
2303                 return -ETIMEDOUT;
2304         }
2305
2306         return 0;
2307 }
2308
2309 static int uhsic_phy_bus_reset(struct tegra_usb_phy *phy)
2310 {
2311         unsigned long val;
2312         void __iomem *base = phy->regs;
2313
2314         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2315
2316         /* Change the USB controller PHY type to HSIC */
2317         val = readl(base + HOSTPC1_DEVLC);
2318         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
2319         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2320         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
2321         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2322         val &= ~HOSTPC1_DEVLC_STS;
2323         writel(val, base + HOSTPC1_DEVLC);
2324         /* wait here, otherwise HOSTPC1_DEVLC_PSPD will timeout */
2325         mdelay(5);
2326
2327         val = readl(base + USB_PORTSC);
2328         val |= USB_PORTSC_PTC(5);
2329         writel(val, base + USB_PORTSC);
2330         udelay(2);
2331
2332         val = readl(base + USB_PORTSC);
2333         val &= ~(USB_PORTSC_PTC(~0));
2334         writel(val, base + USB_PORTSC);
2335         udelay(2);
2336
2337         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_LS(0),
2338                                                  0, 2000)) {
2339                 pr_err("%s: timeout waiting for USB_PORTSC_LS\n", __func__);
2340                 return -ETIMEDOUT;
2341         }
2342
2343         /* Poll until CCS is enabled */
2344         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
2345                                                  USB_PORTSC_CCS, 2000)) {
2346                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
2347                 return -ETIMEDOUT;
2348         }
2349
2350         if (usb_phy_reg_status_wait(base + HOSTPC1_DEVLC,
2351                         HOSTPC1_DEVLC_PSPD(2),
2352                         HOSTPC1_DEVLC_PSPD(2), 2000) < 0) {
2353                 pr_err("%s: timeout waiting hsic high speed configuration\n",
2354                                                 __func__);
2355                         return -ETIMEDOUT;
2356         }
2357
2358         val = readl(base + USB_USBCMD);
2359         val &= ~USB_USBCMD_RS;
2360         writel(val, base + USB_USBCMD);
2361
2362         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
2363                                                  USB_USBSTS_HCH, 2000)) {
2364                 pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
2365                 return -ETIMEDOUT;
2366         }
2367
2368         val = readl(base + UHSIC_PADS_CFG1);
2369         val &= ~UHSIC_RPU_STROBE;
2370         val |= UHSIC_RPD_STROBE;
2371         writel(val, base + UHSIC_PADS_CFG1);
2372
2373         mdelay(50);
2374
2375         val = readl(base + UHSIC_PADS_CFG1);
2376         val &= ~UHSIC_RPD_STROBE;
2377         val |= UHSIC_RPU_STROBE;
2378         writel(val, base + UHSIC_PADS_CFG1);
2379
2380         val = readl(base + USB_USBCMD);
2381         val |= USB_USBCMD_RS;
2382         writel(val, base + USB_USBCMD);
2383
2384         val = readl(base + UHSIC_PADS_CFG1);
2385         val &= ~UHSIC_RPU_STROBE;
2386         writel(val, base + UHSIC_PADS_CFG1);
2387
2388         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2389                                                  USB_USBCMD_RS, 2000)) {
2390                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2391                 return -ETIMEDOUT;
2392         }
2393
2394         return 0;
2395 }
2396
2397 int uhsic_phy_resume(struct tegra_usb_phy *phy)
2398 {
2399         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2400
2401         return 0;
2402 }
2403
2404 static void ulpi_set_trimmer(struct tegra_usb_phy *phy)
2405 {
2406         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2407         void __iomem *base = phy->regs;
2408         unsigned long val;
2409
2410         val = ULPI_DATA_TRIMMER_SEL(config->data_trimmer);
2411         val |= ULPI_STPDIRNXT_TRIMMER_SEL(config->stpdirnxt_trimmer);
2412         val |= ULPI_DIR_TRIMMER_SEL(config->dir_trimmer);
2413         writel(val, base + ULPI_TIMING_CTRL_1);
2414         udelay(10);
2415
2416         val |= ULPI_DATA_TRIMMER_LOAD;
2417         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
2418         val |= ULPI_DIR_TRIMMER_LOAD;
2419         writel(val, base + ULPI_TIMING_CTRL_1);
2420 }
2421
2422 static void reset_utmip_uhsic(void __iomem *base)
2423 {
2424         unsigned long val;
2425
2426         val = readl(base + USB_SUSP_CTRL);
2427         val |= UHSIC_RESET;
2428         writel(val, base + USB_SUSP_CTRL);
2429
2430         val = readl(base + USB_SUSP_CTRL);
2431         val |= UTMIP_RESET;
2432         writel(val, base + USB_SUSP_CTRL);
2433 }
2434
2435 static void ulpi_set_host(void __iomem *base)
2436 {
2437         unsigned long val;
2438
2439         val = readl(base + USB_USBMODE);
2440         val &= ~USB_USBMODE_MASK;
2441         val |= USB_USBMODE_HOST;
2442         writel(val, base + USB_USBMODE);
2443
2444         val = readl(base + HOSTPC1_DEVLC);
2445         val |= HOSTPC1_DEVLC_PTS(2);
2446         writel(val, base + HOSTPC1_DEVLC);
2447 }
2448
2449 static inline void ulpi_pinmux_bypass(struct tegra_usb_phy *phy, bool enable)
2450 {
2451         unsigned long val;
2452         void __iomem *base = phy->regs;
2453
2454         val = readl(base + ULPI_TIMING_CTRL_0);
2455
2456         if (enable)
2457                 val |= ULPI_OUTPUT_PINMUX_BYP;
2458         else
2459                 val &= ~ULPI_OUTPUT_PINMUX_BYP;
2460
2461         writel(val, base + ULPI_TIMING_CTRL_0);
2462 }
2463
2464 static inline void ulpi_null_phy_set_tristate(bool enable)
2465 {
2466 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2467         int tristate = (enable) ? TEGRA_TRI_TRISTATE : TEGRA_TRI_NORMAL;
2468
2469         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA0, tristate);
2470         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA1, tristate);
2471         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA2, tristate);
2472         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA3, tristate);
2473         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA4, tristate);
2474         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA5, tristate);
2475         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA6, tristate);
2476         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA7, tristate);
2477         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_NXT, tristate);
2478
2479         if (enable)
2480                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR, tristate);
2481 #endif
2482 }
2483
2484 static void ulpi_null_phy_obs_read(void)
2485 {
2486         static void __iomem *apb_misc;
2487         unsigned slv0_obs, s2s_obs;
2488
2489         if (!apb_misc)
2490                 apb_misc = ioremap(TEGRA_APB_MISC_BASE, TEGRA_APB_MISC_SIZE);
2491
2492         writel(0x80d1003c, apb_misc + APB_MISC_GP_OBSCTRL_0);
2493         slv0_obs = readl(apb_misc + APB_MISC_GP_OBSDATA_0);
2494
2495         writel(0x80d10040, apb_misc + APB_MISC_GP_OBSCTRL_0);
2496         s2s_obs = readl(apb_misc + APB_MISC_GP_OBSDATA_0);
2497
2498         pr_debug("slv0 obs: %08x\ns2s obs: %08x\n", slv0_obs, s2s_obs);
2499 }
2500
2501 static const struct gpio ulpi_gpios[] = {
2502         {ULPI_STP, GPIOF_IN, "ULPI_STP"},
2503         {ULPI_DIR, GPIOF_OUT_INIT_LOW, "ULPI_DIR"},
2504         {ULPI_D0, GPIOF_OUT_INIT_LOW, "ULPI_D0"},
2505         {ULPI_D1, GPIOF_OUT_INIT_LOW, "ULPI_D1"},
2506 };
2507
2508 static int ulpi_null_phy_open(struct tegra_usb_phy *phy)
2509 {
2510         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2511         int ret;
2512
2513         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2514
2515         ret = gpio_request_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
2516         if (ret)
2517                 return ret;
2518
2519         if (gpio_is_valid(config->phy_restore_gpio)) {
2520                 ret = gpio_request(config->phy_restore_gpio, "phy_restore");
2521                 if (ret)
2522                         goto err_gpio_free;
2523
2524                 gpio_direction_input(config->phy_restore_gpio);
2525         }
2526
2527         tegra_periph_reset_assert(phy->ctrlr_clk);
2528         udelay(10);
2529         tegra_periph_reset_deassert(phy->ctrlr_clk);
2530
2531         return 0;
2532
2533 err_gpio_free:
2534         gpio_free_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
2535         return ret;
2536 }
2537
2538 static void ulpi_null_phy_close(struct tegra_usb_phy *phy)
2539 {
2540         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2541
2542         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2543
2544         if (gpio_is_valid(config->phy_restore_gpio))
2545                 gpio_free(config->phy_restore_gpio);
2546
2547         gpio_free_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
2548 }
2549
2550 static int ulpi_null_phy_power_off(struct tegra_usb_phy *phy)
2551 {
2552         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2553
2554         if (!phy->phy_clk_on) {
2555                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
2556                                                         __LINE__, phy->inst);
2557                 return 0;
2558         }
2559
2560         phy->phy_clk_on = false;
2561         phy->hw_accessible = false;
2562         ulpi_null_phy_set_tristate(true);
2563         return 0;
2564 }
2565
2566 /* NOTE: this function must be called before ehci reset */
2567 static int ulpi_null_phy_init(struct tegra_usb_phy *phy)
2568 {
2569         unsigned long val;
2570         void __iomem *base = phy->regs;
2571
2572         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2573         val = readl(base + ULPIS2S_CTRL);
2574         val |=  ULPIS2S_SLV0_CLAMP_XMIT;
2575         writel(val, base + ULPIS2S_CTRL);
2576
2577         val = readl(base + USB_SUSP_CTRL);
2578         val |= ULPIS2S_SLV0_RESET;
2579         writel(val, base + USB_SUSP_CTRL);
2580         udelay(10);
2581
2582         return 0;
2583 }
2584
2585 static int ulpi_null_phy_irq(struct tegra_usb_phy *phy)
2586 {
2587         usb_phy_fence_read(phy);
2588         return IRQ_HANDLED;
2589 }
2590
2591 /* NOTE: this function must be called after ehci reset */
2592 static int ulpi_null_phy_cmd_reset(struct tegra_usb_phy *phy)
2593 {
2594         unsigned long val;
2595         void __iomem *base = phy->regs;
2596
2597         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2598         ulpi_set_host(base);
2599
2600         /* remove slave0 reset */
2601         val = readl(base + USB_SUSP_CTRL);
2602         val &= ~ULPIS2S_SLV0_RESET;
2603         writel(val, base + USB_SUSP_CTRL);
2604
2605         val = readl(base + ULPIS2S_CTRL);
2606         val &=  ~ULPIS2S_SLV0_CLAMP_XMIT;
2607         writel(val, base + ULPIS2S_CTRL);
2608         udelay(10);
2609
2610         return 0;
2611 }
2612
2613 static int ulpi_null_phy_restore(struct tegra_usb_phy *phy)
2614 {
2615         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2616         unsigned long timeout;
2617         int ulpi_stp = ULPI_STP;
2618
2619         if (gpio_is_valid(config->phy_restore_gpio))
2620                 ulpi_stp = config->phy_restore_gpio;
2621
2622         /* disable ULPI pinmux bypass */
2623         ulpi_pinmux_bypass(phy, false);
2624
2625         /* driving linstate by GPIO */
2626         gpio_set_value(ULPI_D0, 0);
2627         gpio_set_value(ULPI_D1, 0);
2628
2629         /* driving DIR high */
2630         gpio_set_value(ULPI_DIR, 1);
2631
2632         /* remove ULPI tristate */
2633         ulpi_null_phy_set_tristate(false);
2634
2635         /* wait for STP high */
2636         timeout = jiffies + msecs_to_jiffies(25);
2637
2638         while (!gpio_get_value(ulpi_stp)) {
2639                 if (time_after(jiffies, timeout)) {
2640                         pr_warn("phy restore timeout\n");
2641                         return 1;
2642                 }
2643         }
2644
2645         return 0;
2646 }
2647
2648 static int ulpi_null_phy_lp0_resume(struct tegra_usb_phy *phy)
2649 {
2650         unsigned long val;
2651         void __iomem *base = phy->regs;
2652
2653         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2654         ulpi_null_phy_init(phy);
2655
2656         val = readl(base + USB_USBCMD);
2657         val |= USB_CMD_RESET;
2658         writel(val, base + USB_USBCMD);
2659
2660         if (usb_phy_reg_status_wait(base + USB_USBCMD,
2661                 USB_CMD_RESET, 0, 2500) < 0) {
2662                 pr_err("%s: timeout waiting for reset\n", __func__);
2663         }
2664
2665         ulpi_null_phy_cmd_reset(phy);
2666
2667         val = readl(base + USB_USBCMD);
2668         val |= USB_USBCMD_RS;
2669         writel(val, base + USB_USBCMD);
2670         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2671                                                  USB_USBCMD_RS, 2000)) {
2672                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2673                 return -ETIMEDOUT;
2674         }
2675
2676         /* Enable Port Power */
2677         val = readl(base + USB_PORTSC);
2678         val |= USB_PORTSC_PP;
2679         writel(val, base + USB_PORTSC);
2680         udelay(10);
2681
2682         ulpi_null_phy_restore(phy);
2683
2684         return 0;
2685 }
2686
2687 static int ulpi_null_phy_power_on(struct tegra_usb_phy *phy)
2688 {
2689         unsigned long val;
2690         void __iomem *base = phy->regs;
2691         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2692
2693         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2694         if (phy->phy_clk_on) {
2695                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
2696                                                         __LINE__, phy->inst);
2697                 return 0;
2698         }
2699         reset_utmip_uhsic(base);
2700
2701         /* remove ULPI PADS CLKEN reset */
2702         val = readl(base + USB_SUSP_CTRL);
2703         val &= ~ULPI_PADS_CLKEN_RESET;
2704         writel(val, base + USB_SUSP_CTRL);
2705         udelay(10);
2706
2707         val = readl(base + ULPI_TIMING_CTRL_0);
2708         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
2709         writel(val, base + ULPI_TIMING_CTRL_0);
2710
2711         val = readl(base + USB_SUSP_CTRL);
2712         val |= ULPI_PHY_ENABLE;
2713         writel(val, base + USB_SUSP_CTRL);
2714         udelay(10);
2715
2716         /* set timming parameters */
2717         val = readl(base + ULPI_TIMING_CTRL_0);
2718         val |= ULPI_SHADOW_CLK_LOOPBACK_EN;
2719         val &= ~ULPI_SHADOW_CLK_SEL;
2720         val &= ~ULPI_LBK_PAD_EN;
2721         val |= ULPI_SHADOW_CLK_DELAY(config->shadow_clk_delay);
2722         val |= ULPI_CLOCK_OUT_DELAY(config->clock_out_delay);
2723         val |= ULPI_LBK_PAD_E_INPUT_OR;
2724         writel(val, base + ULPI_TIMING_CTRL_0);
2725
2726         writel(0, base + ULPI_TIMING_CTRL_1);
2727         udelay(10);
2728
2729         /* start internal 60MHz clock */
2730         val = readl(base + ULPIS2S_CTRL);
2731         val |= ULPIS2S_ENA;
2732         val |= ULPIS2S_SUPPORT_DISCONNECT;
2733         val |= ULPIS2S_SPARE((phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) ? 3 : 1);
2734         val |= ULPIS2S_PLLU_MASTER_BLASTER60;
2735         writel(val, base + ULPIS2S_CTRL);
2736
2737         /* select ULPI_CORE_CLK_SEL to SHADOW_CLK */
2738         val = readl(base + ULPI_TIMING_CTRL_0);
2739         val |= ULPI_CORE_CLK_SEL;
2740         writel(val, base + ULPI_TIMING_CTRL_0);
2741         udelay(10);
2742
2743         /* enable ULPI null phy clock - can't set the trimmers before this */
2744         val = readl(base + ULPI_TIMING_CTRL_0);
2745         val |= ULPI_CLK_OUT_ENA;
2746         writel(val, base + ULPI_TIMING_CTRL_0);
2747         udelay(10);
2748
2749         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
2750                                                  USB_PHY_CLK_VALID, 2500)) {
2751                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2752                 return -ETIMEDOUT;
2753         }
2754
2755         /* set ULPI trimmers */
2756         ulpi_set_trimmer(phy);
2757
2758         ulpi_set_host(base);
2759
2760         /* remove slave0 reset */
2761         val = readl(base + USB_SUSP_CTRL);
2762         val &= ~ULPIS2S_SLV0_RESET;
2763         writel(val, base + USB_SUSP_CTRL);
2764
2765         /* remove slave1 and line reset */
2766         val = readl(base + USB_SUSP_CTRL);
2767         val &= ~ULPIS2S_SLV1_RESET;
2768         val &= ~ULPIS2S_LINE_RESET;
2769
2770         /* remove ULPI PADS reset */
2771         val &= ~ULPI_PADS_RESET;
2772         writel(val, base + USB_SUSP_CTRL);
2773
2774         if (!phy->ulpi_clk_padout_ena) {
2775                 val = readl(base + ULPI_TIMING_CTRL_0);
2776                 val |= ULPI_CLK_PADOUT_ENA;
2777                 writel(val, base + ULPI_TIMING_CTRL_0);
2778                 phy->ulpi_clk_padout_ena = true;
2779         } else {
2780                 if (!readl(base + USB_ASYNCLISTADDR))
2781                         ulpi_null_phy_lp0_resume(phy);
2782         }
2783         udelay(10);
2784
2785         phy->phy_clk_on = true;
2786         phy->hw_accessible = true;
2787
2788         return 0;
2789 }
2790
2791 static int ulpi_null_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
2792 {
2793         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2794         ulpi_null_phy_obs_read();
2795         usb_phy_wait_for_sof(phy);
2796         ulpi_null_phy_obs_read();
2797         return 0;
2798 }
2799
2800 static int ulpi_null_phy_post_resume(struct tegra_usb_phy *phy)
2801 {
2802         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2803         ulpi_null_phy_obs_read();
2804         return 0;
2805 }
2806
2807 static int ulpi_null_phy_resume(struct tegra_usb_phy *phy)
2808 {
2809         unsigned long val;
2810         void __iomem *base = phy->regs;
2811
2812         if (!readl(base + USB_ASYNCLISTADDR)) {
2813                 /* enable ULPI CLK output pad */
2814                 val = readl(base + ULPI_TIMING_CTRL_0);
2815                 val |= ULPI_CLK_PADOUT_ENA;
2816                 writel(val, base + ULPI_TIMING_CTRL_0);
2817
2818                 /* enable ULPI pinmux bypass */
2819                 ulpi_pinmux_bypass(phy, true);
2820                 udelay(5);
2821 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2822                 /* remove DIR tristate */
2823                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR,
2824                                           TEGRA_TRI_NORMAL);
2825 #endif
2826         }
2827         return 0;
2828 }
2829
2830
2831
2832 static struct tegra_usb_phy_ops utmi_phy_ops = {
2833         .open           = utmi_phy_open,
2834         .close          = utmi_phy_close,
2835         .irq            = utmi_phy_irq,
2836         .power_on       = utmi_phy_power_on,
2837         .power_off      = utmi_phy_power_off,
2838         .pre_resume = utmi_phy_pre_resume,
2839         .resume = utmi_phy_resume,
2840         .post_resume    = utmi_phy_post_resume,
2841         .charger_detect = utmi_phy_charger_detect,
2842         .post_suspend   = phy_post_suspend,
2843 };
2844
2845 static struct tegra_usb_phy_ops uhsic_phy_ops = {
2846         .open           = uhsic_phy_open,
2847         .irq            = uhsic_phy_irq,
2848         .power_on       = uhsic_phy_power_on,
2849         .power_off      = uhsic_phy_power_off,
2850         .pre_resume = uhsic_phy_pre_resume,
2851         .resume = uhsic_phy_resume,
2852         .post_resume = uhsic_phy_post_resume,
2853         .port_power = uhsic_phy_bus_port_power,
2854         .bus_reset      = uhsic_phy_bus_reset,
2855         .post_suspend   = phy_post_suspend,
2856 };
2857
2858 static struct tegra_usb_phy_ops ulpi_null_phy_ops = {
2859         .open           = ulpi_null_phy_open,
2860         .close          = ulpi_null_phy_close,
2861         .init           = ulpi_null_phy_init,
2862         .irq            = ulpi_null_phy_irq,
2863         .power_on       = ulpi_null_phy_power_on,
2864         .power_off      = ulpi_null_phy_power_off,
2865         .pre_resume = ulpi_null_phy_pre_resume,
2866         .resume = ulpi_null_phy_resume,
2867         .post_resume = ulpi_null_phy_post_resume,
2868         .reset          = ulpi_null_phy_cmd_reset,
2869         .post_suspend   = phy_post_suspend,
2870 };
2871
2872 static struct tegra_usb_phy_ops ulpi_link_phy_ops;
2873 static struct tegra_usb_phy_ops icusb_phy_ops;
2874
2875 static struct tegra_usb_phy_ops *phy_ops[] = {
2876         [TEGRA_USB_PHY_INTF_UTMI] = &utmi_phy_ops,
2877         [TEGRA_USB_PHY_INTF_ULPI_LINK] = &ulpi_link_phy_ops,
2878         [TEGRA_USB_PHY_INTF_ULPI_NULL] = &ulpi_null_phy_ops,
2879         [TEGRA_USB_PHY_INTF_HSIC] = &uhsic_phy_ops,
2880         [TEGRA_USB_PHY_INTF_ICUSB] = &icusb_phy_ops,
2881 };
2882
2883 int tegra3_usb_phy_init_ops(struct tegra_usb_phy *phy)
2884 {
2885         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2886
2887         phy->ops = phy_ops[phy->pdata->phy_intf];
2888
2889         /* FIXME: uncommenting below line to make USB host mode fail*/
2890         /* usb_phy_power_down_pmc(); */
2891
2892         return 0;
2893 }