Revert "usb: ehci: tegra: fix hsic enum failure"
[linux-2.6.git] / arch / arm / mach-tegra / tegra3_usb_phy.c
1 /*
2  * arch/arm/mach-tegra/tegra3_usb_phy.c
3  *
4  * Copyright (C) 2011 NVIDIA Corporation
5  *
6  *
7  * This software is licensed under the terms of the GNU General Public
8  * License version 2, as published by the Free Software Foundation, and
9  * may be copied, distributed, and modified under those terms.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17 #include <linux/resource.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/slab.h>
21 #include <linux/err.h>
22 #include <linux/platform_device.h>
23 #include <linux/io.h>
24 #include <linux/gpio.h>
25 #include <linux/interrupt.h>
26 #include <linux/clk.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <mach/iomap.h>
30 #include <mach/pinmux.h>
31 #include <mach/pinmux-tegra30.h>
32 #include "tegra_usb_phy.h"
33 #include "fuse.h"
34
35 #define USB_USBCMD              0x130
36 #define   USB_USBCMD_RS         (1 << 0)
37 #define   USB_CMD_RESET (1<<1)
38
39 #define USB_USBSTS              0x134
40 #define   USB_USBSTS_PCI        (1 << 2)
41 #define   USB_USBSTS_SRI        (1 << 7)
42 #define   USB_USBSTS_HCH        (1 << 12)
43
44 #define USB_USBINTR             0x138
45
46 #define USB_TXFILLTUNING        0x154
47 #define USB_FIFO_TXFILL_THRES(x)   (((x) & 0x1f) << 16)
48 #define USB_FIFO_TXFILL_MASK    0x1f0000
49
50 #define USB_ASYNCLISTADDR       0x148
51
52 #define ICUSB_CTRL              0x15c
53
54 #define USB_PORTSC              0x174
55 #define   USB_PORTSC_WKOC       (1 << 22)
56 #define   USB_PORTSC_WKDS       (1 << 21)
57 #define   USB_PORTSC_WKCN       (1 << 20)
58 #define   USB_PORTSC_PTC(x)     (((x) & 0xf) << 16)
59 #define   USB_PORTSC_PP (1 << 12)
60 #define   USB_PORTSC_LS(x) (((x) & 0x3) << 10)
61 #define   USB_PORTSC_SUSP       (1 << 7)
62 #define   USB_PORTSC_RESUME     (1 << 6)
63 #define   USB_PORTSC_OCC        (1 << 5)
64 #define   USB_PORTSC_PEC        (1 << 3)
65 #define   USB_PORTSC_PE         (1 << 2)
66 #define   USB_PORTSC_CSC        (1 << 1)
67 #define   USB_PORTSC_CCS        (1 << 0)
68 #define   USB_PORTSC_RWC_BITS (USB_PORTSC_CSC | USB_PORTSC_PEC | USB_PORTSC_OCC)
69
70 #define HOSTPC1_DEVLC           0x1b4
71 #define   HOSTPC1_DEVLC_PHCD            (1 << 22)
72 #define   HOSTPC1_DEVLC_PTS(x)          (((x) & 0x7) << 29)
73 #define   HOSTPC1_DEVLC_PTS_MASK        7
74 #define   HOSTPC1_DEVLC_PTS_HSIC        4
75 #define   HOSTPC1_DEVLC_STS             (1 << 28)
76 #define   HOSTPC1_DEVLC_PSPD(x)         (((x) & 0x3) << 25)
77 #define   HOSTPC1_DEVLC_PSPD_MASK       3
78 #define   HOSTPC1_DEVLC_PSPD_HIGH_SPEED 2
79
80 #define USB_USBMODE             0x1f8
81 #define   USB_USBMODE_MASK              (3 << 0)
82 #define   USB_USBMODE_HOST              (3 << 0)
83 #define   USB_USBMODE_DEVICE            (2 << 0)
84
85 #define USB_SUSP_CTRL           0x400
86 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
87 #define   USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
88 #define   USB_SUSP_CLR                  (1 << 5)
89 #define   USB_PHY_CLK_VALID             (1 << 7)
90 #define   USB_PHY_CLK_VALID_INT_ENB     (1 << 9)
91 #define   USB_PHY_CLK_VALID_INT_STS     (1 << 8)
92 #define   UTMIP_RESET                   (1 << 11)
93 #define   UTMIP_PHY_ENABLE              (1 << 12)
94 #define   ULPI_PHY_ENABLE               (1 << 13)
95 #define   UHSIC_RESET                   (1 << 14)
96 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
97 #define   UHSIC_PHY_ENABLE              (1 << 19)
98 #define   ULPIS2S_SLV0_RESET            (1 << 20)
99 #define   ULPIS2S_SLV1_RESET            (1 << 21)
100 #define   ULPIS2S_LINE_RESET            (1 << 22)
101 #define   ULPI_PADS_RESET               (1 << 23)
102 #define   ULPI_PADS_CLKEN_RESET         (1 << 24)
103
104 #define USB_PHY_VBUS_WAKEUP_ID  0x408
105 #define   VDAT_DET_INT_EN       (1 << 16)
106 #define   VDAT_DET_CHG_DET      (1 << 17)
107 #define   VDAT_DET_STS          (1 << 18)
108 #define   USB_ID_STATUS         (1 << 2)
109
110 #define ULPIS2S_CTRL            0x418
111 #define   ULPIS2S_ENA                   (1 << 0)
112 #define   ULPIS2S_SUPPORT_DISCONNECT    (1 << 2)
113 #define   ULPIS2S_PLLU_MASTER_BLASTER60 (1 << 3)
114 #define   ULPIS2S_SPARE(x)              (((x) & 0xF) << 8)
115 #define   ULPIS2S_FORCE_ULPI_CLK_OUT    (1 << 12)
116 #define   ULPIS2S_DISCON_DONT_CHECK_SE0 (1 << 13)
117 #define   ULPIS2S_SUPPORT_HS_KEEP_ALIVE (1 << 14)
118 #define   ULPIS2S_DISABLE_STP_PU        (1 << 15)
119 #define   ULPIS2S_SLV0_CLAMP_XMIT       (1 << 16)
120
121 #define ULPI_TIMING_CTRL_0      0x424
122 #define   ULPI_CLOCK_OUT_DELAY(x)       ((x) & 0x1F)
123 #define   ULPI_OUTPUT_PINMUX_BYP        (1 << 10)
124 #define   ULPI_CLKOUT_PINMUX_BYP        (1 << 11)
125 #define   ULPI_SHADOW_CLK_LOOPBACK_EN   (1 << 12)
126 #define   ULPI_SHADOW_CLK_SEL           (1 << 13)
127 #define   ULPI_CORE_CLK_SEL             (1 << 14)
128 #define   ULPI_SHADOW_CLK_DELAY(x)      (((x) & 0x1F) << 16)
129 #define   ULPI_LBK_PAD_EN               (1 << 26)
130 #define   ULPI_LBK_PAD_E_INPUT_OR       (1 << 27)
131 #define   ULPI_CLK_OUT_ENA              (1 << 28)
132 #define   ULPI_CLK_PADOUT_ENA           (1 << 29)
133
134 #define ULPI_TIMING_CTRL_1      0x428
135 #define   ULPI_DATA_TRIMMER_LOAD        (1 << 0)
136 #define   ULPI_DATA_TRIMMER_SEL(x)      (((x) & 0x7) << 1)
137 #define   ULPI_STPDIRNXT_TRIMMER_LOAD   (1 << 16)
138 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
139 #define   ULPI_DIR_TRIMMER_LOAD         (1 << 24)
140 #define   ULPI_DIR_TRIMMER_SEL(x)       (((x) & 0x7) << 25)
141
142 #define UTMIP_XCVR_CFG0         0x808
143 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
144 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
145 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
146 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
147 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
148 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
149 #define   UTMIP_XCVR_LSBIAS_SEL                 (1 << 21)
150 #define   UTMIP_XCVR_SETUP_MSB(x)               (((x) & 0x7) << 22)
151 #define   UTMIP_XCVR_HSSLEW_MSB(x)              (((x) & 0x7f) << 25)
152 #define   UTMIP_XCVR_MAX_OFFSET         2
153 #define   UTMIP_XCVR_SETUP_MAX_VALUE    0x7f
154 #define   UTMIP_XCVR_SETUP_MIN_VALUE    0
155 #define   XCVR_SETUP_MSB_CALIB(x) ((x) >> 4)
156
157 #define UTMIP_BIAS_CFG0         0x80c
158 #define   UTMIP_OTGPD                   (1 << 11)
159 #define   UTMIP_BIASPD                  (1 << 10)
160 #define   UTMIP_HSSQUELCH_LEVEL(x)      (((x) & 0x3) << 0)
161 #define   UTMIP_HSDISCON_LEVEL(x)       (((x) & 0x3) << 2)
162 #define   UTMIP_HSDISCON_LEVEL_MSB      (1 << 24)
163
164 #define UTMIP_HSRX_CFG0         0x810
165 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
166 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
167
168 #define UTMIP_HSRX_CFG1         0x814
169 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
170
171 #define UTMIP_TX_CFG0           0x820
172 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
173 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
174
175 #define UTMIP_DEBOUNCE_CFG0 0x82c
176 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
177
178 #define UTMIP_BAT_CHRG_CFG0 0x830
179 #define   UTMIP_PD_CHRG                 (1 << 0)
180 #define   UTMIP_ON_SINK_EN              (1 << 2)
181 #define   UTMIP_OP_SRC_EN               (1 << 3)
182
183 #define UTMIP_XCVR_CFG1         0x838
184 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
185 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
186 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
187 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
188
189 #define UTMIP_BIAS_CFG1         0x83c
190 #define   UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
191 #define   UTMIP_BIAS_PDTRK_POWERDOWN    (1 << 0)
192 #define   UTMIP_BIAS_PDTRK_POWERUP      (1 << 1)
193
194 #define UTMIP_MISC_CFG0         0x824
195 #define   UTMIP_DPDM_OBSERVE            (1 << 26)
196 #define   UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
197 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J   UTMIP_DPDM_OBSERVE_SEL(0xf)
198 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K   UTMIP_DPDM_OBSERVE_SEL(0xe)
199 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
200 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
201 #define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
202 #define   FORCE_PULLDN_DM       (1 << 8)
203 #define   FORCE_PULLDN_DP       (1 << 9)
204 #define   COMB_TERMS            (1 << 0)
205 #define   ALWAYS_FREE_RUNNING_TERMS (1 << 1)
206
207 #define UTMIP_SPARE_CFG0        0x834
208 #define   FUSE_SETUP_SEL                (1 << 3)
209 #define   FUSE_ATERM_SEL                (1 << 4)
210
211 #define UTMIP_PMC_WAKEUP0               0x84c
212 #define   EVENT_INT_ENB                 (1 << 0)
213
214 #define UTMIP_BIAS_STS0                 0x840
215 #define   UTMIP_RCTRL_VAL(x)            (((x) & 0xffff) << 0)
216 #define   UTMIP_TCTRL_VAL(x)            (((x) & (0xffff << 16)) >> 16)
217
218 #define UHSIC_PLL_CFG1                          0xc04
219 #define   UHSIC_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
220 #define   UHSIC_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 14)
221
222 #define UHSIC_HSRX_CFG0                         0xc08
223 #define   UHSIC_ELASTIC_UNDERRUN_LIMIT(x)       (((x) & 0x1f) << 2)
224 #define   UHSIC_ELASTIC_OVERRUN_LIMIT(x)        (((x) & 0x1f) << 8)
225 #define   UHSIC_IDLE_WAIT(x)                    (((x) & 0x1f) << 13)
226
227 #define UHSIC_HSRX_CFG1                         0xc0c
228 #define   UHSIC_HS_SYNC_START_DLY(x)            (((x) & 0x1f) << 1)
229
230 #define UHSIC_TX_CFG0                           0xc10
231 #define UHSIC_HS_READY_WAIT_FOR_VALID   (1 << 9)
232 #define UHSIC_MISC_CFG0                         0xc14
233 #define   UHSIC_SUSPEND_EXIT_ON_EDGE            (1 << 7)
234 #define   UHSIC_DETECT_SHORT_CONNECT            (1 << 8)
235 #define   UHSIC_FORCE_XCVR_MODE                 (1 << 15)
236 #define   UHSIC_DISABLE_BUSRESET                (1 << 20)
237 #define UHSIC_MISC_CFG1                         0xc18
238 #define   UHSIC_PLLU_STABLE_COUNT(x)            (((x) & 0xfff) << 2)
239
240 #define UHSIC_PADS_CFG0                         0xc1c
241 #define   UHSIC_TX_RTUNEN                       0xf000
242 #define   UHSIC_TX_RTUNE(x)                     (((x) & 0xf) << 12)
243
244 #define UHSIC_PADS_CFG1                         0xc20
245 #define   UHSIC_PD_BG                           (1 << 2)
246 #define   UHSIC_PD_TX                           (1 << 3)
247 #define   UHSIC_PD_TRK                          (1 << 4)
248 #define   UHSIC_PD_RX                           (1 << 5)
249 #define   UHSIC_PD_ZI                           (1 << 6)
250 #define   UHSIC_RX_SEL                          (1 << 7)
251 #define   UHSIC_RPD_DATA                        (1 << 9)
252 #define   UHSIC_RPD_STROBE                      (1 << 10)
253 #define   UHSIC_RPU_DATA                        (1 << 11)
254 #define   UHSIC_RPU_STROBE                      (1 << 12)
255
256 #define UHSIC_STAT_CFG0                 0xc28
257 #define   UHSIC_CONNECT_DETECT                  (1 << 0)
258
259 #define PMC_USB_DEBOUNCE                        0xec
260 #define   UTMIP_LINE_DEB_CNT(x)                 (((x) & 0xf) << 16)
261
262 #define PMC_USB_AO                              0xf0
263 #define PMC_POWER_DOWN_MASK                     0xffff
264 #define HSIC_RESERVED_P0                        (3 << 14)
265 #define HSIC_STOBE_VAL_PD_P0                    (1 << 13)
266 #define HSIC_DATA_VAL_PD_P0                     (1 << 12)
267 #define USB_ID_PD(inst)                         (1 << ((4*(inst))+3))
268 #define VBUS_WAKEUP_PD(inst)                    (1 << ((4*(inst))+2))
269 #define   USBON_VAL_PD(inst)                    (1 << ((4*(inst))+1))
270 #define   USBON_VAL_PD_P2                       (1 << 9)
271 #define   USBON_VAL_PD_P1                       (1 << 5)
272 #define   USBON_VAL_PD_P0                       (1 << 1)
273 #define   USBOP_VAL_PD(inst)                    (1 << (4*(inst)))
274 #define   USBOP_VAL_PD_P2                       (1 << 8)
275 #define   USBOP_VAL_PD_P1                       (1 << 4)
276 #define   USBOP_VAL_PD_P0                       (1 << 0)
277 #define   PMC_USB_AO_PD_P2                      (0xf << 8)
278 #define   PMC_USB_AO_ID_PD_P0                   (1 << 3)
279 #define   PMC_USB_AO_VBUS_WAKEUP_PD_P0  (1 << 2)
280
281 #define PMC_TRIGGERS                    0x1ec
282 #define   UTMIP_CLR_WALK_PTR(inst)      (1 << (inst))
283 #define   UTMIP_CLR_WALK_PTR_P2         (1 << 2)
284 #define   UTMIP_CLR_WALK_PTR_P1         (1 << 1)
285 #define   UTMIP_CLR_WALK_PTR_P0         (1 << 0)
286 #define   UTMIP_CAP_CFG(inst)   (1 << ((inst)+4))
287 #define   UTMIP_CAP_CFG_P2              (1 << 6)
288 #define   UTMIP_CAP_CFG_P1              (1 << 5)
289 #define   UTMIP_CAP_CFG_P0              (1 << 4)
290 #define   UTMIP_CLR_WAKE_ALARM(inst)            (1 << ((inst)+12))
291 #define   UTMIP_CLR_WAKE_ALARM_P2       (1 << 14)
292
293 #define PMC_PAD_CFG             (0x1f4)
294
295 #define PMC_UTMIP_TERM_PAD_CFG  0x1f8
296 #define   PMC_TCTRL_VAL(x)      (((x) & 0x1f) << 5)
297 #define   PMC_RCTRL_VAL(x)      (((x) & 0x1f) << 0)
298
299 #define UHSIC_SLEEPWALK_REG             0x210
300 #define UHSIC_DATA_RPD_D                (1 << 25)
301 #define UHSIC_STRB_RPD_D                (1 << 24)
302 #define UHSIC_DATA_RPD_C                (1 << 17)
303 #define UHSIC_STRB_RPD_C                (1 << 16)
304 #define UHSIC_DATA_RPD_B                (1 << 9)
305 #define UHSIC_STRB_RPD_B                (1 << 8)
306 #define UHSIC_DATA_RPD_A                (1 << 1)
307 #define UHSIC_STRB_RPD_A                (1 << 0)
308
309 #define PMC_SLEEP_CFG                   0x1fc
310 #define   UTMIP_TCTRL_USE_PMC(inst) (1 << ((8*(inst))+3))
311 #define   UTMIP_TCTRL_USE_PMC_P2                (1 << 19)
312 #define   UTMIP_TCTRL_USE_PMC_P1                (1 << 11)
313 #define   UTMIP_TCTRL_USE_PMC_P0                (1 << 3)
314 #define   UTMIP_RCTRL_USE_PMC(inst) (1 << ((8*(inst))+2))
315 #define   UTMIP_RCTRL_USE_PMC_P2                (1 << 18)
316 #define   UTMIP_RCTRL_USE_PMC_P1                (1 << 10)
317 #define   UTMIP_RCTRL_USE_PMC_P0                (1 << 2)
318 #define   UTMIP_FSLS_USE_PMC(inst)      (1 << ((8*(inst))+1))
319 #define   UTMIP_FSLS_USE_PMC_P2         (1 << 17)
320 #define   UTMIP_FSLS_USE_PMC_P1         (1 << 9)
321 #define   UTMIP_FSLS_USE_PMC_P0         (1 << 1)
322 #define   UTMIP_MASTER_ENABLE(inst) (1 << (8*(inst)))
323 #define   UTMIP_MASTER_ENABLE_P2                (1 << 16)
324 #define   UTMIP_MASTER_ENABLE_P1                (1 << 8)
325 #define   UTMIP_MASTER_ENABLE_P0                (1 << 0)
326 #define UHSIC_MASTER_ENABLE_P0          (1 << 24)
327 #define UHSIC_WAKE_VAL_P0(x)            (((x) & 0xf) << 28)
328
329 #define PMC_SLEEPWALK_CFG               0x200
330 #define   UTMIP_LINEVAL_WALK_EN(inst) (1 << ((8*(inst))+7))
331 #define   UTMIP_LINEVAL_WALK_EN_P2      (1 << 23)
332 #define   UTMIP_LINEVAL_WALK_EN_P1      (1 << 15)
333 #define   UTMIP_LINEVAL_WALK_EN_P0      (1 << 7)
334 #define   UTMIP_WAKE_VAL(inst, x) (((x) & 0xf) << ((8*(inst))+4))
335 #define   UTMIP_WAKE_VAL_P2(x)          (((x) & 0xf) << 20)
336 #define   UTMIP_WAKE_VAL_P1(x)          (((x) & 0xf) << 12)
337 #define   UTMIP_WAKE_VAL_P0(x)          (((x) & 0xf) << 4)
338 #define   WAKE_VAL_NONE         0xc
339 #define   WAKE_VAL_ANY                  0xF
340 #define   WAKE_VAL_FSJ                  0x2
341 #define   WAKE_VAL_FSK                  0x1
342 #define   WAKE_VAL_SE0                  0x0
343
344 #define PMC_SLEEPWALK_REG(inst)         (0x204 + (4*(inst)))
345 #define   UTMIP_USBOP_RPD_A     (1 << 0)
346 #define   UTMIP_USBON_RPD_A     (1 << 1)
347 #define   UTMIP_AP_A                    (1 << 4)
348 #define   UTMIP_AN_A                    (1 << 5)
349 #define   UTMIP_HIGHZ_A         (1 << 6)
350 #define   UTMIP_USBOP_RPD_B     (1 << 8)
351 #define   UTMIP_USBON_RPD_B     (1 << 9)
352 #define   UTMIP_AP_B                    (1 << 12)
353 #define   UTMIP_AN_B                    (1 << 13)
354 #define   UTMIP_HIGHZ_B         (1 << 14)
355 #define   UTMIP_USBOP_RPD_C     (1 << 16)
356 #define   UTMIP_USBON_RPD_C     (1 << 17)
357 #define   UTMIP_AP_C            (1 << 20)
358 #define   UTMIP_AN_C            (1 << 21)
359 #define   UTMIP_HIGHZ_C         (1 << 22)
360 #define   UTMIP_USBOP_RPD_D     (1 << 24)
361 #define   UTMIP_USBON_RPD_D     (1 << 25)
362 #define   UTMIP_AP_D            (1 << 28)
363 #define   UTMIP_AN_D            (1 << 29)
364 #define   UTMIP_HIGHZ_D         (1 << 30)
365
366 #define UTMIP_UHSIC_STATUS              0x214
367 #define   UTMIP_WALK_PTR_VAL(inst)      (0x3 << ((inst)*2))
368 #define   UTMIP_USBOP_VAL(inst)         (1 << ((2*(inst)) + 8))
369 #define   UTMIP_USBOP_VAL_P2            (1 << 12)
370 #define   UTMIP_USBOP_VAL_P1            (1 << 10)
371 #define   UTMIP_USBOP_VAL_P0            (1 << 8)
372 #define   UTMIP_USBON_VAL(inst)         (1 << ((2*(inst)) + 9))
373 #define   UTMIP_USBON_VAL_P2            (1 << 13)
374 #define   UTMIP_USBON_VAL_P1            (1 << 11)
375 #define   UTMIP_USBON_VAL_P0            (1 << 9)
376 #define   UTMIP_WAKE_ALARM(inst)                (1 << ((inst) + 16))
377 #define   UTMIP_WAKE_ALARM_P2   (1 << 18)
378 #define   UTMIP_WAKE_ALARM_P1   (1 << 17)
379 #define   UTMIP_WAKE_ALARM_P0   (1 << 16)
380 #define   UTMIP_WALK_PTR(inst)  (1 << ((inst)*2))
381 #define   UTMIP_WALK_PTR_P2     (1 << 4)
382 #define   UTMIP_WALK_PTR_P1     (1 << 2)
383 #define   UTMIP_WALK_PTR_P0     (1 << 0)
384
385 #define USB1_PREFETCH_ID               6
386 #define USB2_PREFETCH_ID               18
387 #define USB3_PREFETCH_ID               17
388
389 #define PMC_UTMIP_UHSIC_FAKE            0x218
390 #define   USBON_VAL(inst)       (1 << ((4*(inst))+1))
391 #define   USBON_VAL_P2                  (1 << 9)
392 #define   USBON_VAL_P1                  (1 << 5)
393 #define   USBON_VAL_P0                  (1 << 1)
394 #define   USBOP_VAL(inst)       (1 << (4*(inst)))
395 #define   USBOP_VAL_P2                  (1 << 8)
396 #define   USBOP_VAL_P1                  (1 << 4)
397 #define   USBOP_VAL_P0                  (1 << 0)
398
399 #define PMC_UTMIP_BIAS_MASTER_CNTRL 0x30c
400 #define   BIAS_MASTER_PROG_VAL          (1 << 1)
401
402 #define PMC_UTMIP_MASTER_CONFIG         0x310
403 #define   UTMIP_PWR(inst)               (1 << (inst))
404
405 #define FUSE_USB_CALIB_0                0x1F0
406 #define   FUSE_USB_CALIB_XCVR_SETUP(x)  (((x) & 0x7F) << 0)
407
408 /* These values (in milli second) are taken from the battery charging spec */
409 #define TDP_SRC_ON_MS    100
410 #define TDPSRC_CON_MS    40
411
412 #ifdef DEBUG
413 #define DBG(stuff...)   pr_info("tegra3_usb_phy: " stuff)
414 #else
415 #define DBG(stuff...)   do {} while (0)
416 #endif
417
418 #if 0
419 #define PHY_DBG(stuff...)       pr_info("tegra3_usb_phy: " stuff)
420 #else
421 #define PHY_DBG(stuff...)       do {} while (0)
422 #endif
423
424 static u32 utmip_rctrl_val, utmip_tctrl_val;
425 static DEFINE_SPINLOCK(utmip_pad_lock);
426 static int utmip_pad_count;
427
428 static struct tegra_xtal_freq utmip_freq_table[] = {
429         {
430                 .freq = 12000000,
431                 .enable_delay = 0x02,
432                 .stable_count = 0x2F,
433                 .active_delay = 0x04,
434                 .xtal_freq_count = 0x76,
435                 .debounce = 0x7530,
436                 .pdtrk_count = 5,
437         },
438         {
439                 .freq = 13000000,
440                 .enable_delay = 0x02,
441                 .stable_count = 0x33,
442                 .active_delay = 0x05,
443                 .xtal_freq_count = 0x7F,
444                 .debounce = 0x7EF4,
445                 .pdtrk_count = 5,
446         },
447         {
448                 .freq = 19200000,
449                 .enable_delay = 0x03,
450                 .stable_count = 0x4B,
451                 .active_delay = 0x06,
452                 .xtal_freq_count = 0xBB,
453                 .debounce = 0xBB80,
454                 .pdtrk_count = 7,
455         },
456         {
457                 .freq = 26000000,
458                 .enable_delay = 0x04,
459                 .stable_count = 0x66,
460                 .active_delay = 0x09,
461                 .xtal_freq_count = 0xFE,
462                 .debounce = 0xFDE8,
463                 .pdtrk_count = 9,
464         },
465 };
466
467 static struct tegra_xtal_freq uhsic_freq_table[] = {
468         {
469                 .freq = 12000000,
470                 .enable_delay = 0x02,
471                 .stable_count = 0x2F,
472                 .active_delay = 0x0,
473                 .xtal_freq_count = 0x1CA,
474         },
475         {
476                 .freq = 13000000,
477                 .enable_delay = 0x02,
478                 .stable_count = 0x33,
479                 .active_delay = 0x0,
480                 .xtal_freq_count = 0x1F0,
481         },
482         {
483                 .freq = 19200000,
484                 .enable_delay = 0x03,
485                 .stable_count = 0x4B,
486                 .active_delay = 0x0,
487                 .xtal_freq_count = 0x2DD,
488         },
489         {
490                 .freq = 26000000,
491                 .enable_delay = 0x04,
492                 .stable_count = 0x66,
493                 .active_delay = 0x0,
494                 .xtal_freq_count = 0x3E0,
495         },
496 };
497
498 static void usb_phy_fence_read(struct tegra_usb_phy *phy)
499 {
500         /* Fence read for coherency of AHB master intiated writes */
501         if (phy->inst == 0)
502                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB1_PREFETCH_ID));
503         else if (phy->inst == 1)
504                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB2_PREFETCH_ID));
505         else if (phy->inst == 2)
506                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB3_PREFETCH_ID));
507
508         return;
509 }
510
511 static void utmip_setup_pmc_wake_detect(struct tegra_usb_phy *phy)
512 {
513         unsigned long val, pmc_pad_cfg_val;
514         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
515         unsigned  int inst = phy->inst;
516         void __iomem *base = phy->regs;
517         bool port_connected;
518         enum usb_phy_port_speed port_speed;
519
520         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
521
522         /* check for port connect status */
523         val = readl(base + USB_PORTSC);
524         port_connected = val & USB_PORTSC_CCS;
525
526         if (!port_connected)
527                 return;
528
529         port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
530                 HOSTPC1_DEVLC_PSPD_MASK;
531         /*Set PMC MASTER bits to do the following
532         * a. Take over the UTMI drivers
533         * b. set up such that it will take over resume
534         *        if remote wakeup is detected
535         * Prepare PMC to take over suspend-wake detect-drive resume until USB
536         * controller ready
537         */
538
539         /* disable master enable in PMC */
540         val = readl(pmc_base + PMC_SLEEP_CFG);
541         val &= ~UTMIP_MASTER_ENABLE(inst);
542         writel(val, pmc_base + PMC_SLEEP_CFG);
543
544         /* UTMIP_PWR_PX=1 for power savings mode */
545         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
546         val |= UTMIP_PWR(inst);
547         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
548
549         /* config debouncer */
550         val = readl(pmc_base + PMC_USB_DEBOUNCE);
551         val &= ~UTMIP_LINE_DEB_CNT(~0);
552         val |= UTMIP_LINE_DEB_CNT(4);
553         writel(val, pmc_base + PMC_USB_DEBOUNCE);
554
555         /* Make sure nothing is happening on the line with respect to PMC */
556         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
557         val &= ~USBOP_VAL(inst);
558         val &= ~USBON_VAL(inst);
559         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
560
561         /* Make sure wake value for line is none */
562         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
563         val &= ~UTMIP_LINEVAL_WALK_EN(inst);
564         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
565         val = readl(pmc_base + PMC_SLEEP_CFG);
566         val &= ~UTMIP_WAKE_VAL(inst, ~0);
567         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
568         writel(val, pmc_base + PMC_SLEEP_CFG);
569
570         /* turn off pad detectors */
571         val = readl(pmc_base + PMC_USB_AO);
572         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
573         writel(val, pmc_base + PMC_USB_AO);
574
575         /* Remove fake values and make synchronizers work a bit */
576         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
577         val &= ~USBOP_VAL(inst);
578         val &= ~USBON_VAL(inst);
579         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
580
581         /* Enable which type of event can trigger a walk,
582         in this case usb_line_wake */
583         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
584         val |= UTMIP_LINEVAL_WALK_EN(inst);
585         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
586
587         /* Enable which type of event can trigger a walk,
588         * in this case usb_line_wake */
589         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
590         val |= UTMIP_LINEVAL_WALK_EN(inst);
591         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
592
593         /* Clear the walk pointers and wake alarm */
594         val = readl(pmc_base + PMC_TRIGGERS);
595         val |= UTMIP_CLR_WAKE_ALARM(inst) | UTMIP_CLR_WALK_PTR(inst);
596         writel(val, pmc_base + PMC_TRIGGERS);
597
598
599         /* Capture FS/LS pad configurations */
600         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
601         val = readl(pmc_base + PMC_TRIGGERS);
602         val |= UTMIP_CAP_CFG(inst);
603         writel(val, pmc_base + PMC_TRIGGERS);
604         udelay(1);
605         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
606
607         /* BIAS MASTER_ENABLE=0 */
608         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
609         val &= ~BIAS_MASTER_PROG_VAL;
610         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
611
612         /* program walk sequence, maintain a J, followed by a driven K
613         * to signal a resume once an wake event is detected */
614         val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
615         val &= ~UTMIP_AP_A;
616         val |= UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_AN_A |UTMIP_HIGHZ_A |
617                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_AP_B | UTMIP_AN_B |
618                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_AP_C | UTMIP_AN_C |
619                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_AP_D | UTMIP_AN_D;
620         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
621
622         if (port_speed == USB_PHY_PORT_SPEED_LOW) {
623                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
624                 val &= ~(UTMIP_AN_B | UTMIP_HIGHZ_B | UTMIP_AN_C |
625                         UTMIP_HIGHZ_C | UTMIP_AN_D | UTMIP_HIGHZ_D);
626                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
627         } else {
628                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
629                 val &= ~(UTMIP_AP_B | UTMIP_HIGHZ_B | UTMIP_AP_C |
630                         UTMIP_HIGHZ_C | UTMIP_AP_D | UTMIP_HIGHZ_D);
631                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
632         }
633
634         /* turn on pad detectors */
635         val = readl(pmc_base + PMC_USB_AO);
636         val &= ~(USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
637         writel(val, pmc_base + PMC_USB_AO);
638
639         /* Add small delay before usb detectors provide stable line values */
640         mdelay(1);
641
642         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
643         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
644         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
645         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
646
647         phy->remote_wakeup = false;
648
649         /* Turn over pad configuration to PMC  for line wake events*/
650         val = readl(pmc_base + PMC_SLEEP_CFG);
651         val &= ~UTMIP_WAKE_VAL(inst, ~0);
652         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_ANY);
653         val |= UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst);
654         val |= UTMIP_MASTER_ENABLE(inst) | UTMIP_FSLS_USE_PMC(inst);
655         writel(val, pmc_base + PMC_SLEEP_CFG);
656
657         val = readl(base + UTMIP_PMC_WAKEUP0);
658         val |= EVENT_INT_ENB;
659         writel(val, base + UTMIP_PMC_WAKEUP0);
660         PHY_DBG("%s ENABLE_PMC inst = %d\n", __func__, inst);
661 }
662
663 static void utmip_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy)
664 {
665         unsigned long val;
666         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
667         unsigned  int inst = phy->inst;
668         void __iomem *base = phy->regs;
669
670         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
671
672         val = readl(pmc_base + PMC_SLEEP_CFG);
673         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
674         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
675         writel(val, pmc_base + PMC_SLEEP_CFG);
676
677         val = readl(pmc_base + PMC_TRIGGERS);
678         val |= UTMIP_CLR_WAKE_ALARM(inst) | UTMIP_CLR_WALK_PTR(inst);
679         writel(val, pmc_base + PMC_TRIGGERS);
680
681         val = readl(base + UTMIP_PMC_WAKEUP0);
682         val &= ~EVENT_INT_ENB;
683         writel(val, base + UTMIP_PMC_WAKEUP0);
684
685         /* Disable PMC master mode by clearing MASTER_EN */
686         val = readl(pmc_base + PMC_SLEEP_CFG);
687         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
688                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
689         writel(val, pmc_base + PMC_SLEEP_CFG);
690
691         val = readl(pmc_base + PMC_TRIGGERS);
692         val &= ~UTMIP_CAP_CFG(inst);
693         writel(val, pmc_base + PMC_TRIGGERS);
694
695         /* turn off pad detectors */
696         val = readl(pmc_base + PMC_USB_AO);
697         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
698         writel(val, pmc_base + PMC_USB_AO);
699
700         phy->remote_wakeup = false;
701         PHY_DBG("%s DISABLE_PMC inst = %d\n", __func__, inst);
702 }
703
704 bool utmi_phy_remotewake_detected(struct tegra_usb_phy *phy)
705 {
706         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
707         void __iomem *base = phy->regs;
708         unsigned  int inst = phy->inst;
709         u32 val;
710
711         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
712         val = readl(base + UTMIP_PMC_WAKEUP0);
713         if (val & EVENT_INT_ENB) {
714                 val = readl(pmc_base + UTMIP_UHSIC_STATUS);
715                 if (UTMIP_WAKE_ALARM(inst) & val) {
716                         val = readl(pmc_base + PMC_SLEEP_CFG);
717                         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
718                         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
719                         writel(val, pmc_base + PMC_SLEEP_CFG);
720
721                         val = readl(pmc_base + PMC_TRIGGERS);
722                         val |= UTMIP_CLR_WAKE_ALARM(inst) |
723                                 UTMIP_CLR_WALK_PTR(inst);
724                         writel(val, pmc_base + PMC_TRIGGERS);
725
726                         val = readl(base + UTMIP_PMC_WAKEUP0);
727                         val &= ~EVENT_INT_ENB;
728                         writel(val, base + UTMIP_PMC_WAKEUP0);
729                         phy->remote_wakeup = true;
730                         return true;
731                 }
732         }
733         return false;
734 }
735
736 static void utmi_phy_enable_trking_data(struct tegra_usb_phy *phy)
737 {
738         void __iomem *base = IO_ADDRESS(TEGRA_USB_BASE);
739         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
740         static bool init_done = false;
741         u32 val;
742
743         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
744
745         /* Should be done only once after system boot */
746         if (init_done)
747                 return;
748
749         clk_enable(phy->utmi_pad_clk);
750         /* Bias pad MASTER_ENABLE=1 */
751         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
752         val |= BIAS_MASTER_PROG_VAL;
753         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
754
755         /* Setting the tracking length time */
756         val = readl(base + UTMIP_BIAS_CFG1);
757         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
758         val |= UTMIP_BIAS_PDTRK_COUNT(5);
759         writel(val, base + UTMIP_BIAS_CFG1);
760
761         /* Bias PDTRK is Shared and MUST be done from USB1 ONLY, PD_TRK=0 */
762         val = readl(base + UTMIP_BIAS_CFG1);
763         val &= ~UTMIP_BIAS_PDTRK_POWERDOWN;
764         writel(val, base + UTMIP_BIAS_CFG1);
765
766         val = readl(base + UTMIP_BIAS_CFG1);
767         val |= UTMIP_BIAS_PDTRK_POWERUP;
768         writel(val, base + UTMIP_BIAS_CFG1);
769
770         /* Wait for 25usec */
771         udelay(25);
772
773         /* Bias pad MASTER_ENABLE=0 */
774         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
775         val &= ~BIAS_MASTER_PROG_VAL;
776         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
777
778         /* Wait for 1usec */
779         udelay(1);
780
781         /* Bias pad MASTER_ENABLE=1 */
782         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
783         val |= BIAS_MASTER_PROG_VAL;
784         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
785
786         /* Read RCTRL and TCTRL from UTMIP space */
787         val = readl(base + UTMIP_BIAS_STS0);
788         utmip_rctrl_val = ffz(UTMIP_RCTRL_VAL(val));
789         utmip_tctrl_val = ffz(UTMIP_TCTRL_VAL(val));
790
791         /* PD_TRK=1 */
792         val = readl(base + UTMIP_BIAS_CFG1);
793         val |= UTMIP_BIAS_PDTRK_POWERDOWN;
794         writel(val, base + UTMIP_BIAS_CFG1);
795
796         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
797         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
798         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
799         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
800         clk_disable(phy->utmi_pad_clk);
801         init_done = true;
802 }
803
804 static void utmip_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy)
805 {
806         unsigned long val;
807         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
808         unsigned  int inst = phy->inst;
809
810         /* power down UTMIP interfaces */
811         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
812         val |= UTMIP_PWR(inst);
813         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
814
815         /* setup sleep walk usb controller */
816         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
817                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
818                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
819                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
820         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
821
822         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
823         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
824         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
825         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
826
827         /* Turn over pad configuration to PMC */
828         val = readl(pmc_base + PMC_SLEEP_CFG);
829         val &= ~UTMIP_WAKE_VAL(inst, ~0);
830         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE) |
831                 UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
832                 UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst);
833         writel(val, pmc_base + PMC_SLEEP_CFG);
834         PHY_DBG("%s ENABLE_PMC inst = %d\n", __func__, inst);
835 }
836
837 static void utmip_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
838 {
839         unsigned long val;
840         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
841         unsigned  int inst = phy->inst;
842
843         /* Disable PMC master mode by clearing MASTER_EN */
844         val = readl(pmc_base + PMC_SLEEP_CFG);
845         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
846                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
847         writel(val, pmc_base + PMC_SLEEP_CFG);
848         mdelay(1);
849         PHY_DBG("%s DISABLE_PMC inst = %d\n", __func__, inst);
850 }
851
852 static void uhsic_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy)
853 {
854         unsigned long val;
855         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
856
857         /* turn on pad detectors for HSIC*/
858         val = readl(pmc_base + PMC_USB_AO);
859         val |= (HSIC_RESERVED_P0 | HSIC_STOBE_VAL_PD_P0 | HSIC_DATA_VAL_PD_P0);
860         writel(val, pmc_base + PMC_USB_AO);
861
862         /* enable pull downs on HSIC PMC */
863         val = UHSIC_STRB_RPD_A | UHSIC_DATA_RPD_A | UHSIC_STRB_RPD_B |
864                 UHSIC_DATA_RPD_B | UHSIC_STRB_RPD_C | UHSIC_DATA_RPD_C |
865                 UHSIC_STRB_RPD_D | UHSIC_DATA_RPD_D;
866         writel(val, pmc_base + UHSIC_SLEEPWALK_REG);
867
868         /* Turn over pad configuration to PMC */
869         val = readl(pmc_base + PMC_SLEEP_CFG);
870         val &= ~UHSIC_WAKE_VAL_P0(~0);
871         val |= UHSIC_WAKE_VAL_P0(WAKE_VAL_NONE) | UHSIC_MASTER_ENABLE_P0;
872         writel(val, pmc_base + PMC_SLEEP_CFG);
873 }
874
875 static void uhsic_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
876 {
877         unsigned long val;
878         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
879
880         /* turn on pad detectors for HSIC*/
881         val = readl(pmc_base + PMC_USB_AO);
882         val &= ~(HSIC_RESERVED_P0 | HSIC_STOBE_VAL_PD_P0 | HSIC_DATA_VAL_PD_P0);
883         writel(val, pmc_base + PMC_USB_AO);
884
885         /* Disable PMC master mode by clearing MASTER_EN */
886         val = readl(pmc_base + PMC_SLEEP_CFG);
887         val &= ~(UHSIC_MASTER_ENABLE_P0);
888         writel(val, pmc_base + PMC_SLEEP_CFG);
889         mdelay(1);
890 }
891
892 #ifdef KERNEL_WARNING
893 static void usb_phy_power_down_pmc(void)
894 {
895         unsigned long val;
896         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
897
898         /* power down all 3 UTMIP interfaces */
899         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
900         val |= UTMIP_PWR(0) | UTMIP_PWR(1) | UTMIP_PWR(2);
901         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
902
903         /* turn on pad detectors */
904         writel(PMC_POWER_DOWN_MASK, pmc_base + PMC_USB_AO);
905
906         /* setup sleep walk fl all 3 usb controllers */
907         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
908                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
909                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
910                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
911         writel(val, pmc_base + PMC_SLEEPWALK_REG(0));
912         writel(val, pmc_base + PMC_SLEEPWALK_REG(1));
913         writel(val, pmc_base + PMC_SLEEPWALK_REG(2));
914
915         /* enable pull downs on HSIC PMC */
916         val = UHSIC_STRB_RPD_A | UHSIC_DATA_RPD_A | UHSIC_STRB_RPD_B |
917                 UHSIC_DATA_RPD_B | UHSIC_STRB_RPD_C | UHSIC_DATA_RPD_C |
918                 UHSIC_STRB_RPD_D | UHSIC_DATA_RPD_D;
919         writel(val, pmc_base + UHSIC_SLEEPWALK_REG);
920
921         /* Turn over pad configuration to PMC */
922         val = readl(pmc_base + PMC_SLEEP_CFG);
923         val &= ~UTMIP_WAKE_VAL(0, ~0);
924         val &= ~UTMIP_WAKE_VAL(1, ~0);
925         val &= ~UTMIP_WAKE_VAL(2, ~0);
926         val &= ~UHSIC_WAKE_VAL_P0(~0);
927         val |= UTMIP_WAKE_VAL(0, WAKE_VAL_NONE) | UHSIC_WAKE_VAL_P0(WAKE_VAL_NONE) |
928         UTMIP_WAKE_VAL(1, WAKE_VAL_NONE) | UTMIP_WAKE_VAL(2, WAKE_VAL_NONE) |
929         UTMIP_RCTRL_USE_PMC(0) | UTMIP_RCTRL_USE_PMC(1) | UTMIP_RCTRL_USE_PMC(2) |
930         UTMIP_TCTRL_USE_PMC(0) | UTMIP_TCTRL_USE_PMC(1) | UTMIP_TCTRL_USE_PMC(2) |
931         UTMIP_FSLS_USE_PMC(0) | UTMIP_FSLS_USE_PMC(1) | UTMIP_FSLS_USE_PMC(2) |
932         UTMIP_MASTER_ENABLE(0) | UTMIP_MASTER_ENABLE(1) | UTMIP_MASTER_ENABLE(2) |
933         UHSIC_MASTER_ENABLE_P0;
934         writel(val, pmc_base + PMC_SLEEP_CFG);
935 }
936 #endif
937
938 static int usb_phy_bringup_host_controller(struct tegra_usb_phy *phy)
939 {
940         unsigned long val;
941         void __iomem *base = phy->regs;
942
943         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
944         PHY_DBG("[%d] USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n", __LINE__,
945                 readl(base + USB_USBSTS), readl(base + USB_PORTSC),
946                                                         phy->port_speed);
947
948         /* Device is plugged in when system is in LP0 */
949         /* Bring up the controller from LP0*/
950         val = readl(base + USB_USBCMD);
951         val |= USB_CMD_RESET;
952         writel(val, base + USB_USBCMD);
953
954         if (usb_phy_reg_status_wait(base + USB_USBCMD,
955                 USB_CMD_RESET, 0, 2500) < 0) {
956                 pr_err("%s: timeout waiting for reset\n", __func__);
957         }
958
959         val = readl(base + USB_USBMODE);
960         val &= ~USB_USBMODE_MASK;
961         val |= USB_USBMODE_HOST;
962         writel(val, base + USB_USBMODE);
963
964         val = readl(base + HOSTPC1_DEVLC);
965         val &= ~HOSTPC1_DEVLC_PTS(~0);
966         val |= HOSTPC1_DEVLC_STS;
967         writel(val, base + HOSTPC1_DEVLC);
968
969         /* Enable Port Power */
970         val = readl(base + USB_PORTSC);
971         val |= USB_PORTSC_PP;
972         writel(val, base + USB_PORTSC);
973         udelay(10);
974
975         /* Check if the phy resume from LP0. When the phy resume from LP0
976          * USB register will be reset.to zero */
977         if (!readl(base + USB_ASYNCLISTADDR)) {
978                 /* Program the field PTC based on the saved speed mode */
979                 val = readl(base + USB_PORTSC);
980                 val &= ~USB_PORTSC_PTC(~0);
981                 if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH)
982                         val |= USB_PORTSC_PTC(5);
983                 else if (phy->port_speed == USB_PHY_PORT_SPEED_FULL)
984                         val |= USB_PORTSC_PTC(6);
985                 else if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
986                         val |= USB_PORTSC_PTC(7);
987                 writel(val, base + USB_PORTSC);
988                 udelay(10);
989
990                 /* Disable test mode by setting PTC field to NORMAL_OP */
991                 val = readl(base + USB_PORTSC);
992                 val &= ~USB_PORTSC_PTC(~0);
993                 writel(val, base + USB_PORTSC);
994                 udelay(10);
995         }
996
997         /* Poll until CCS is enabled */
998         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
999                                                  USB_PORTSC_CCS, 2000)) {
1000                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
1001         }
1002
1003         /* Poll until PE is enabled */
1004         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_PE,
1005                                                  USB_PORTSC_PE, 2000)) {
1006                 pr_err("%s: timeout waiting for USB_PORTSC_PE\n", __func__);
1007         }
1008
1009         /* Clear the PCI status, to avoid an interrupt taken upon resume */
1010         val = readl(base + USB_USBSTS);
1011         val |= USB_USBSTS_PCI;
1012         writel(val, base + USB_USBSTS);
1013
1014         if (!phy->remote_wakeup) {
1015                 /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
1016                 val = readl(base + USB_PORTSC);
1017                 if ((val & USB_PORTSC_PP) && (val & USB_PORTSC_PE)) {
1018                         val |= USB_PORTSC_SUSP;
1019                         writel(val, base + USB_PORTSC);
1020                         /* Need a 4ms delay before the controller goes to suspend */
1021                         mdelay(4);
1022
1023                         /* Wait until port suspend completes */
1024                         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_SUSP,
1025                                                          USB_PORTSC_SUSP, 1000)) {
1026                                 pr_err("%s: timeout waiting for PORT_SUSPEND\n",
1027                                                                         __func__);
1028                         }
1029                 }
1030         }
1031         PHY_DBG("[%d] USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n", __LINE__,
1032                 readl(base + USB_USBSTS), readl(base + USB_PORTSC),
1033                                                         phy->port_speed);
1034
1035         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1036                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1037         return 0;
1038 }
1039
1040 static void usb_phy_wait_for_sof(struct tegra_usb_phy *phy)
1041 {
1042         unsigned long val;
1043         void __iomem *base = phy->regs;
1044
1045         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1046
1047         val = readl(base + USB_USBSTS);
1048         writel(val, base + USB_USBSTS);
1049         udelay(20);
1050         /* wait for two SOFs */
1051         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1052                 USB_USBSTS_SRI, 2500))
1053                 pr_err("%s: timeout waiting for SOF\n", __func__);
1054
1055         val = readl(base + USB_USBSTS);
1056         writel(val, base + USB_USBSTS);
1057         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI, 0, 2500))
1058                 pr_err("%s: timeout waiting for SOF\n", __func__);
1059
1060         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1061                         USB_USBSTS_SRI, 2500))
1062                 pr_err("%s: timeout waiting for SOF\n", __func__);
1063
1064         udelay(20);
1065 }
1066
1067 static unsigned int utmi_phy_xcvr_setup_value(struct tegra_usb_phy *phy)
1068 {
1069         struct tegra_utmi_config *cfg = &phy->pdata->u_cfg.utmi;
1070         signed long val;
1071
1072         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1073
1074         if (cfg->xcvr_use_fuses) {
1075                 val = FUSE_USB_CALIB_XCVR_SETUP(
1076                                 tegra_fuse_readl(FUSE_USB_CALIB_0));
1077                 if (cfg->xcvr_setup_offset <= UTMIP_XCVR_MAX_OFFSET)
1078                         val = val + cfg->xcvr_setup_offset;
1079
1080                 if (val > UTMIP_XCVR_SETUP_MAX_VALUE) {
1081                         val = UTMIP_XCVR_SETUP_MAX_VALUE;
1082                         pr_info("%s: reset XCVR_SETUP to max value\n",
1083                                  __func__);
1084                 } else if (val < UTMIP_XCVR_SETUP_MIN_VALUE) {
1085                         val = UTMIP_XCVR_SETUP_MIN_VALUE;
1086                         pr_info("%s: reset XCVR_SETUP to min value\n",
1087                                  __func__);
1088                 }
1089         } else {
1090                 val = cfg->xcvr_setup;
1091         }
1092
1093         return (unsigned int) val;
1094 }
1095
1096 static int utmi_phy_open(struct tegra_usb_phy *phy)
1097 {
1098         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1099         unsigned long parent_rate, val;
1100         int i;
1101
1102         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1103
1104         phy->utmi_pad_clk = clk_get_sys("utmip-pad", NULL);
1105         if (IS_ERR(phy->utmi_pad_clk)) {
1106                 pr_err("%s: can't get utmip pad clock\n", __func__);
1107                 return PTR_ERR(phy->utmi_pad_clk);
1108         }
1109
1110         phy->utmi_xcvr_setup = utmi_phy_xcvr_setup_value(phy);
1111
1112         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
1113         for (i = 0; i < ARRAY_SIZE(utmip_freq_table); i++) {
1114                 if (utmip_freq_table[i].freq == parent_rate) {
1115                         phy->freq = &utmip_freq_table[i];
1116                         break;
1117                 }
1118         }
1119         if (!phy->freq) {
1120                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
1121                 return -EINVAL;
1122         }
1123
1124         /* Power-up the VBUS detector for UTMIP PHY */
1125         val = readl(pmc_base + PMC_USB_AO);
1126         val &= ~(PMC_USB_AO_VBUS_WAKEUP_PD_P0 | PMC_USB_AO_ID_PD_P0);
1127         writel((val | PMC_USB_AO_PD_P2), (pmc_base + PMC_USB_AO));
1128
1129         utmip_powerup_pmc_wake_detect(phy);
1130
1131         return 0;
1132 }
1133
1134 static void utmi_phy_close(struct tegra_usb_phy *phy)
1135 {
1136         unsigned long val;
1137         void __iomem *base = phy->regs;
1138
1139         DBG("%s inst:[%d]\n", __func__, phy->inst);
1140
1141         /* Disable PHY clock valid interrupts while going into suspend*/
1142         if (phy->pdata->u_data.host.hot_plug) {
1143                 val = readl(base + USB_SUSP_CTRL);
1144                 val &= ~USB_PHY_CLK_VALID_INT_ENB;
1145                 writel(val, base + USB_SUSP_CTRL);
1146         }
1147
1148         clk_put(phy->utmi_pad_clk);
1149 }
1150
1151 static int utmi_phy_pad_power_on(struct tegra_usb_phy *phy)
1152 {
1153         unsigned long val, flags;
1154         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1155
1156         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1157
1158         clk_enable(phy->utmi_pad_clk);
1159
1160         spin_lock_irqsave(&utmip_pad_lock, flags);
1161         utmip_pad_count++;
1162
1163         val = readl(pad_base + UTMIP_BIAS_CFG0);
1164         val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
1165         val |= UTMIP_HSSQUELCH_LEVEL(0x2) | UTMIP_HSDISCON_LEVEL(0x1) |
1166                 UTMIP_HSDISCON_LEVEL_MSB;
1167         writel(val, pad_base + UTMIP_BIAS_CFG0);
1168
1169         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1170
1171         clk_disable(phy->utmi_pad_clk);
1172
1173         return 0;
1174 }
1175
1176 static int utmi_phy_pad_power_off(struct tegra_usb_phy *phy)
1177 {
1178         unsigned long val, flags;
1179         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1180
1181         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1182
1183         clk_enable(phy->utmi_pad_clk);
1184         spin_lock_irqsave(&utmip_pad_lock, flags);
1185
1186         if (!utmip_pad_count) {
1187                 pr_err("%s: utmip pad already powered off\n", __func__);
1188                 goto out;
1189         }
1190         if (--utmip_pad_count == 0) {
1191                 val = readl(pad_base + UTMIP_BIAS_CFG0);
1192                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
1193                 val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) | UTMIP_HSDISCON_LEVEL(~0) |
1194                         UTMIP_HSDISCON_LEVEL_MSB);
1195                 writel(val, pad_base + UTMIP_BIAS_CFG0);
1196         }
1197 out:
1198         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1199         clk_disable(phy->utmi_pad_clk);
1200
1201         return 0;
1202 }
1203
1204 static int utmi_phy_irq(struct tegra_usb_phy *phy)
1205 {
1206         void __iomem *base = phy->regs;
1207         unsigned long val = 0;
1208
1209         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1210         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1211                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1212         DBG("USB_USBMODE[0x%x] USB_USBCMD[0x%x]\n",
1213                         readl(base + USB_USBMODE), readl(base + USB_USBCMD));
1214
1215         usb_phy_fence_read(phy);
1216         /* check if there is any remote wake event */
1217         if (utmi_phy_remotewake_detected(phy))
1218                 pr_info("%s: utmip remote wake detected\n", __func__);
1219
1220         if (phy->pdata->u_data.host.hot_plug) {
1221                 val = readl(base + USB_SUSP_CTRL);
1222                 if ((val  & USB_PHY_CLK_VALID_INT_STS)) {
1223                         val &= ~USB_PHY_CLK_VALID_INT_ENB |
1224                                         USB_PHY_CLK_VALID_INT_STS;
1225                         writel(val , (base + USB_SUSP_CTRL));
1226                         pr_info("%s: usb device plugged-in\n", __func__);
1227                         val = readl(base + USB_USBSTS);
1228                         if (!(val  & USB_USBSTS_PCI))
1229                                 return IRQ_NONE;
1230                         val = readl(base + USB_PORTSC);
1231                         val &= ~(USB_PORTSC_WKCN | USB_PORTSC_RWC_BITS);
1232                         writel(val , (base + USB_PORTSC));
1233                 }
1234         }
1235
1236         return IRQ_HANDLED;
1237 }
1238
1239 static void utmi_phy_enable_obs_bus(struct tegra_usb_phy *phy)
1240 {
1241         unsigned long val;
1242         void __iomem *base = phy->regs;
1243
1244         /* (2LS WAR)is not required for LS and FS devices and is only for HS */
1245         if ((phy->port_speed == USB_PHY_PORT_SPEED_LOW) ||
1246                 (phy->port_speed == USB_PHY_PORT_SPEED_FULL)) {
1247                 /* do not enable the OBS bus */
1248                 val = readl(base + UTMIP_MISC_CFG0);
1249                 val &= ~(UTMIP_DPDM_OBSERVE_SEL(~0));
1250                 writel(val, base + UTMIP_MISC_CFG0);
1251                 DBG("%s(%d) Disable OBS bus\n", __func__, __LINE__);
1252                 return;
1253         }
1254         /* Force DP/DM pulldown active for Host mode */
1255         val = readl(base + UTMIP_MISC_CFG0);
1256         val |= FORCE_PULLDN_DM | FORCE_PULLDN_DP |
1257                         COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS;
1258         writel(val, base + UTMIP_MISC_CFG0);
1259         val = readl(base + UTMIP_MISC_CFG0);
1260         val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1261         if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
1262                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
1263         else
1264                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
1265         writel(val, base + UTMIP_MISC_CFG0);
1266         udelay(1);
1267
1268         val = readl(base + UTMIP_MISC_CFG0);
1269         val |= UTMIP_DPDM_OBSERVE;
1270         writel(val, base + UTMIP_MISC_CFG0);
1271         udelay(10);
1272         DBG("%s(%d) Enable OBS bus\n", __func__, __LINE__);
1273         PHY_DBG("ENABLE_OBS_BUS\n");
1274 }
1275
1276 static int utmi_phy_disable_obs_bus(struct tegra_usb_phy *phy)
1277 {
1278         unsigned long val;
1279         void __iomem *base = phy->regs;
1280
1281         /* check if OBS bus is already enabled */
1282         val = readl(base + UTMIP_MISC_CFG0);
1283         if (val & UTMIP_DPDM_OBSERVE) {
1284                 PHY_DBG("DISABLE_OBS_BUS\n");
1285                 /* Change the UTMIP OBS bus to drive SE0 */
1286                 val = readl(base + UTMIP_MISC_CFG0);
1287                 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1288                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_SE0;
1289                 writel(val, base + UTMIP_MISC_CFG0);
1290
1291                 /* Wait for 3us(2 LS bit times) */
1292                 udelay(3);
1293
1294                 /* Release UTMIP OBS bus */
1295                 val = readl(base + UTMIP_MISC_CFG0);
1296                 val &= ~UTMIP_DPDM_OBSERVE;
1297                 writel(val, base + UTMIP_MISC_CFG0);
1298
1299                 /* Release DP/DM pulldown for Host mode */
1300                 val = readl(base + UTMIP_MISC_CFG0);
1301                 val &= ~(FORCE_PULLDN_DM | FORCE_PULLDN_DP |
1302                                 COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS);
1303                 writel(val, base + UTMIP_MISC_CFG0);
1304
1305                 val = readl(base + USB_USBCMD);
1306                 val |= USB_USBCMD_RS;
1307                 writel(val, base + USB_USBCMD);
1308                 if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
1309                                                          USB_USBCMD_RS, 2000)) {
1310                         pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
1311                         return -ETIMEDOUT;
1312                 }
1313         }
1314         return 0;
1315 }
1316
1317 static int utmi_phy_post_resume(struct tegra_usb_phy *phy)
1318 {
1319         unsigned long val;
1320         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1321         unsigned  int inst = phy->inst;
1322
1323         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1324         val = readl(pmc_base + PMC_SLEEP_CFG);
1325         /* if PMC is not disabled by now then disable it */
1326         if (val & UTMIP_MASTER_ENABLE(inst)) {
1327                 utmip_phy_disable_pmc_bus_ctrl(phy);
1328         }
1329
1330         utmi_phy_disable_obs_bus(phy);
1331
1332         return 0;
1333 }
1334
1335 static int utmi_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1336 {
1337         unsigned long val;
1338         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1339         void __iomem *base = phy->regs;
1340         unsigned  int inst = phy->inst;
1341
1342         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1343         phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
1344                         HOSTPC1_DEVLC_PSPD_MASK;
1345
1346         if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH) {
1347                 /* Disable interrupts */
1348                 writel(0, base + USB_USBINTR);
1349                 /* Clear the run bit to stop SOFs - 2LS WAR */
1350                 val = readl(base + USB_USBCMD);
1351                 val &= ~USB_USBCMD_RS;
1352                 writel(val, base + USB_USBCMD);
1353                 if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
1354                                                          USB_USBSTS_HCH, 2000)) {
1355                         pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
1356                 }
1357         }
1358
1359         val = readl(pmc_base + PMC_SLEEP_CFG);
1360         if (val & UTMIP_MASTER_ENABLE(inst)) {
1361                 if (!remote_wakeup)
1362                         utmip_phy_disable_pmc_bus_ctrl(phy);
1363         } else {
1364                 utmi_phy_enable_obs_bus(phy);
1365         }
1366
1367         return 0;
1368 }
1369
1370 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
1371 {
1372         unsigned long val;
1373         void __iomem *base = phy->regs;
1374
1375         PHY_DBG("%s(%d) inst:[%d] BEGIN\n", __func__, __LINE__, phy->inst);
1376         if (!phy->phy_clk_on) {
1377                 PHY_DBG("%s(%d) inst:[%d] phy clk is already off\n",
1378                                         __func__, __LINE__, phy->inst);
1379                 return 0;
1380         }
1381
1382         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1383                 utmip_powerdown_pmc_wake_detect(phy);
1384
1385                 val = readl(base + USB_SUSP_CTRL);
1386                 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
1387                 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
1388                 writel(val, base + USB_SUSP_CTRL);
1389
1390                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1391                 val |= UTMIP_PD_CHRG;
1392                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1393         } else {
1394                 phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
1395                                 HOSTPC1_DEVLC_PSPD_MASK;
1396
1397                 /* Disable interrupts */
1398                 writel(0, base + USB_USBINTR);
1399
1400                 /* Clear the run bit to stop SOFs - 2LS WAR */
1401                 val = readl(base + USB_USBCMD);
1402                 val &= ~USB_USBCMD_RS;
1403                 writel(val, base + USB_USBCMD);
1404
1405                 if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
1406                                                          USB_USBSTS_HCH, 2000)) {
1407                         pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
1408                 }
1409                 utmip_setup_pmc_wake_detect(phy);
1410         }
1411
1412         if (!phy->pdata->u_data.host.hot_plug) {
1413                 val = readl(base + UTMIP_XCVR_CFG0);
1414                 val |= (UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
1415                          UTMIP_FORCE_PDZI_POWERDOWN);
1416                 writel(val, base + UTMIP_XCVR_CFG0);
1417         }
1418
1419         val = readl(base + UTMIP_XCVR_CFG1);
1420         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1421                    UTMIP_FORCE_PDDR_POWERDOWN;
1422         writel(val, base + UTMIP_XCVR_CFG1);
1423
1424         val = readl(base + UTMIP_BIAS_CFG1);
1425         val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
1426         writel(val, base + UTMIP_BIAS_CFG1);
1427
1428         utmi_phy_pad_power_off(phy);
1429
1430         if (phy->pdata->u_data.host.hot_plug) {
1431                 bool enable_hotplug = true;
1432                 /* if it is OTG port then make sure to enable hot-plug feature
1433                    only if host adaptor is connected, i.e id is low */
1434                 if (phy->pdata->port_otg) {
1435                         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1436                         enable_hotplug = (val & USB_ID_STATUS) ? false : true;
1437                 }
1438                 if (enable_hotplug) {
1439                         val = readl(base + USB_PORTSC);
1440                         val |= USB_PORTSC_WKCN;
1441                         writel(val, base + USB_PORTSC);
1442
1443                         val = readl(base + USB_SUSP_CTRL);
1444                         val |= USB_PHY_CLK_VALID_INT_ENB;
1445                         writel(val, base + USB_SUSP_CTRL);
1446                 } else {
1447                         /* Disable PHY clock valid interrupts while going into suspend*/
1448                         val = readl(base + USB_SUSP_CTRL);
1449                         val &= ~USB_PHY_CLK_VALID_INT_ENB;
1450                         writel(val, base + USB_SUSP_CTRL);
1451                 }
1452         }
1453
1454         val = readl(base + HOSTPC1_DEVLC);
1455         val |= HOSTPC1_DEVLC_PHCD;
1456         writel(val, base + HOSTPC1_DEVLC);
1457
1458         if (!phy->pdata->u_data.host.hot_plug) {
1459                 val = readl(base + USB_SUSP_CTRL);
1460                 val |= UTMIP_RESET;
1461                 writel(val, base + USB_SUSP_CTRL);
1462         }
1463
1464         phy->phy_clk_on = false;
1465         phy->hw_accessible = false;
1466
1467         PHY_DBG("%s(%d) inst:[%d] END\n", __func__, __LINE__, phy->inst);
1468
1469         return 0;
1470 }
1471
1472
1473 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
1474 {
1475         unsigned long val;
1476         void __iomem *base = phy->regs;
1477         struct tegra_utmi_config *config = &phy->pdata->u_cfg.utmi;
1478
1479         PHY_DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1480         if (phy->phy_clk_on) {
1481                 PHY_DBG("%s(%d) inst:[%d] phy clk is already On\n",
1482                                         __func__, __LINE__, phy->inst);
1483                 return 0;
1484         }
1485         val = readl(base + USB_SUSP_CTRL);
1486         val |= UTMIP_RESET;
1487         writel(val, base + USB_SUSP_CTRL);
1488
1489         val = readl(base + UTMIP_TX_CFG0);
1490         val |= UTMIP_FS_PREABMLE_J;
1491         writel(val, base + UTMIP_TX_CFG0);
1492
1493         val = readl(base + UTMIP_HSRX_CFG0);
1494         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
1495         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
1496         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
1497         writel(val, base + UTMIP_HSRX_CFG0);
1498
1499         val = readl(base + UTMIP_HSRX_CFG1);
1500         val &= ~UTMIP_HS_SYNC_START_DLY(~0);
1501         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
1502         writel(val, base + UTMIP_HSRX_CFG1);
1503
1504         val = readl(base + UTMIP_DEBOUNCE_CFG0);
1505         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
1506         val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
1507         writel(val, base + UTMIP_DEBOUNCE_CFG0);
1508
1509         val = readl(base + UTMIP_MISC_CFG0);
1510         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
1511         writel(val, base + UTMIP_MISC_CFG0);
1512
1513         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1514                 val = readl(base + USB_SUSP_CTRL);
1515                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
1516                 writel(val, base + USB_SUSP_CTRL);
1517
1518                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1519                 val &= ~UTMIP_PD_CHRG;
1520                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1521         } else {
1522                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1523                 val |= UTMIP_PD_CHRG;
1524                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1525         }
1526
1527         utmi_phy_pad_power_on(phy);
1528
1529         val = readl(base + UTMIP_XCVR_CFG0);
1530         val &= ~(UTMIP_XCVR_LSBIAS_SEL | UTMIP_FORCE_PD_POWERDOWN |
1531                  UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN |
1532                  UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_LSFSLEW(~0) |
1533                  UTMIP_XCVR_LSRSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
1534         val |= UTMIP_XCVR_SETUP(phy->utmi_xcvr_setup);
1535         val |= UTMIP_XCVR_SETUP_MSB(XCVR_SETUP_MSB_CALIB(phy->utmi_xcvr_setup));
1536         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
1537         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
1538         val |= UTMIP_XCVR_HSSLEW_MSB(0x8);
1539         writel(val, base + UTMIP_XCVR_CFG0);
1540
1541         val = readl(base + UTMIP_XCVR_CFG1);
1542         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1543                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
1544         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
1545         writel(val, base + UTMIP_XCVR_CFG1);
1546
1547         val = readl(base + UTMIP_BIAS_CFG1);
1548         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
1549         val |= UTMIP_BIAS_PDTRK_COUNT(phy->freq->pdtrk_count);
1550         writel(val, base + UTMIP_BIAS_CFG1);
1551
1552         val = readl(base + UTMIP_SPARE_CFG0);
1553         val &= ~FUSE_SETUP_SEL;
1554         val |= FUSE_ATERM_SEL;
1555         writel(val, base + UTMIP_SPARE_CFG0);
1556
1557         val = readl(base + USB_SUSP_CTRL);
1558         val |= UTMIP_PHY_ENABLE;
1559         writel(val, base + USB_SUSP_CTRL);
1560
1561         val = readl(base + USB_SUSP_CTRL);
1562         val &= ~UTMIP_RESET;
1563         writel(val, base + USB_SUSP_CTRL);
1564
1565         val = readl(base + HOSTPC1_DEVLC);
1566         val &= ~HOSTPC1_DEVLC_PHCD;
1567         writel(val, base + HOSTPC1_DEVLC);
1568
1569         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1570                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500))
1571                 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
1572
1573         utmi_phy_enable_trking_data(phy);
1574
1575         if (phy->inst == 2)
1576                 writel(0, base + ICUSB_CTRL);
1577
1578         val = readl(base + USB_USBMODE);
1579         val &= ~USB_USBMODE_MASK;
1580         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST)
1581                 val |= USB_USBMODE_HOST;
1582         else
1583                 val |= USB_USBMODE_DEVICE;
1584         writel(val, base + USB_USBMODE);
1585
1586         val = readl(base + HOSTPC1_DEVLC);
1587         val &= ~HOSTPC1_DEVLC_PTS(~0);
1588         val |= HOSTPC1_DEVLC_STS;
1589         writel(val, base + HOSTPC1_DEVLC);
1590
1591         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE)
1592                 utmip_powerup_pmc_wake_detect(phy);
1593         phy->phy_clk_on = true;
1594         phy->hw_accessible = true;
1595         PHY_DBG("%s(%d) End inst:[%d]\n", __func__, __LINE__, phy->inst);
1596         return 0;
1597 }
1598
1599 static void utmi_phy_restore_start(struct tegra_usb_phy *phy)
1600 {
1601         unsigned long val;
1602         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1603         int inst = phy->inst;
1604
1605         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1606         val = readl(pmc_base + UTMIP_UHSIC_STATUS);
1607         /* check whether we wake up from the remote resume */
1608         if (UTMIP_WALK_PTR_VAL(inst) & val) {
1609                 phy->remote_wakeup = true;
1610         } else {
1611                 if (!((UTMIP_USBON_VAL(phy->inst) |
1612                         UTMIP_USBOP_VAL(phy->inst)) & val)) {
1613                                 utmip_phy_disable_pmc_bus_ctrl(phy);
1614                 }
1615         }
1616         utmi_phy_enable_obs_bus(phy);
1617 }
1618
1619 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
1620 {
1621         unsigned long val;
1622         void __iomem *base = phy->regs;
1623         int wait_time_us = 25000; /* FPR should be set by this time */
1624
1625         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1626         /* check whether we wake up from the remote resume */
1627         if (phy->remote_wakeup) {
1628                 /* wait until SUSPEND and RESUME bit is cleared on remote resume */
1629                 do {
1630                         val = readl(base + USB_PORTSC);
1631                         udelay(1);
1632                         if (wait_time_us == 0) {
1633                                 PHY_DBG("%s PMC REMOTE WAKEUP FPR timeout val = 0x%x instance = %d\n", __func__, val, phy->inst);
1634                                 utmip_phy_disable_pmc_bus_ctrl(phy);
1635                                 utmi_phy_post_resume(phy);
1636                                 return;
1637                         }
1638                         wait_time_us--;
1639                 } while (val & (USB_PORTSC_RESUME | USB_PORTSC_SUSP));
1640
1641                 /* wait for 25 ms to port resume complete */
1642                 msleep(25);
1643                 /* disable PMC master control */
1644                 utmip_phy_disable_pmc_bus_ctrl(phy);
1645
1646                 /* Clear PCI and SRI bits to avoid an interrupt upon resume */
1647                 val = readl(base + USB_USBSTS);
1648                 writel(val, base + USB_USBSTS);
1649                 /* wait to avoid SOF if there is any */
1650                 if (usb_phy_reg_status_wait(base + USB_USBSTS,
1651                         USB_USBSTS_SRI, USB_USBSTS_SRI, 2500) < 0) {
1652                         pr_err("%s: timeout waiting for SOF\n", __func__);
1653                 }
1654                 utmi_phy_post_resume(phy);
1655         }
1656 }
1657
1658 static int utmi_phy_resume(struct tegra_usb_phy *phy)
1659 {
1660         int status = 0;
1661         unsigned long val;
1662         void __iomem *base = phy->regs;
1663
1664         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1665         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) {
1666                 if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
1667                         utmi_phy_restore_start(phy);
1668                         usb_phy_bringup_host_controller(phy);
1669                         utmi_phy_restore_end(phy);
1670                 } else {
1671                         /* device is plugged in when system is in LP0 */
1672                         /* bring up the controller from LP0*/
1673                         val = readl(base + USB_USBCMD);
1674                         val |= USB_CMD_RESET;
1675                         writel(val, base + USB_USBCMD);
1676
1677                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1678                                 USB_CMD_RESET, 0, 2500) < 0) {
1679                                 pr_err("%s: timeout waiting for reset\n", __func__);
1680                         }
1681
1682                         val = readl(base + USB_USBMODE);
1683                         val &= ~USB_USBMODE_MASK;
1684                         val |= USB_USBMODE_HOST;
1685                         writel(val, base + USB_USBMODE);
1686
1687                         val = readl(base + HOSTPC1_DEVLC);
1688                         val &= ~HOSTPC1_DEVLC_PTS(~0);
1689                         val |= HOSTPC1_DEVLC_STS;
1690                         writel(val, base + HOSTPC1_DEVLC);
1691
1692                         writel(USB_USBCMD_RS, base + USB_USBCMD);
1693
1694                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1695                                 USB_USBCMD_RS, USB_USBCMD_RS, 2500) < 0) {
1696                                 pr_err("%s: timeout waiting for run bit\n", __func__);
1697                         }
1698
1699                         /* Enable Port Power */
1700                         val = readl(base + USB_PORTSC);
1701                         val |= USB_PORTSC_PP;
1702                         writel(val, base + USB_PORTSC);
1703                         udelay(10);
1704
1705                         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1706                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1707                 }
1708         }
1709
1710         return status;
1711 }
1712
1713 bool utmi_phy_charger_detect(struct tegra_usb_phy *phy)
1714 {
1715         unsigned long val;
1716         void __iomem *base = phy->regs;
1717         bool status;
1718
1719         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1720         if (phy->pdata->op_mode != TEGRA_USB_OPMODE_DEVICE) {
1721                 /* Charger detection is not there for ULPI
1722                  * return Charger not available */
1723                 return false;
1724         }
1725
1726         /* Enable charger detection logic */
1727         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1728         val |= UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN;
1729         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1730
1731         /* Source should be on for 100 ms as per USB charging spec */
1732         msleep(TDP_SRC_ON_MS);
1733
1734         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1735         /* If charger is not connected disable the interrupt */
1736         val &= ~VDAT_DET_INT_EN;
1737         val |= VDAT_DET_CHG_DET;
1738         writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
1739
1740         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1741         if (val & VDAT_DET_STS)
1742                 status = true;
1743         else
1744                 status = false;
1745
1746         /* Disable charger detection logic */
1747         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1748         val &= ~(UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN);
1749         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1750
1751         /* Delay of 40 ms before we pull the D+ as per battery charger spec */
1752         msleep(TDPSRC_CON_MS);
1753
1754         return status;
1755 }
1756
1757 static int uhsic_phy_open(struct tegra_usb_phy *phy)
1758 {
1759         unsigned long parent_rate;
1760         int i;
1761
1762         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1763         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
1764         for (i = 0; i < ARRAY_SIZE(uhsic_freq_table); i++) {
1765                 if (uhsic_freq_table[i].freq == parent_rate) {
1766                         phy->freq = &uhsic_freq_table[i];
1767                         break;
1768                 }
1769         }
1770         if (!phy->freq) {
1771                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
1772                 return -EINVAL;
1773         }
1774
1775         utmip_powerup_pmc_wake_detect(phy);
1776
1777         return 0;
1778 }
1779
1780 static int uhsic_phy_irq(struct tegra_usb_phy *phy)
1781 {
1782         usb_phy_fence_read(phy);
1783         return IRQ_HANDLED;
1784 }
1785
1786 static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
1787 {
1788         unsigned long val;
1789         void __iomem *base = phy->regs;
1790         struct tegra_hsic_config *config = &phy->pdata->u_cfg.hsic;
1791
1792         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1793
1794         uhsic_powerup_pmc_wake_detect(phy);
1795
1796         if (phy->phy_clk_on) {
1797                 DBG("%s(%d) inst:[%d] phy clk is already On\n",
1798                                         __func__, __LINE__, phy->inst);
1799                 return 0;
1800         }
1801
1802         val = readl(base + UHSIC_PADS_CFG1);
1803         val &= ~(UHSIC_PD_BG | UHSIC_PD_TX | UHSIC_PD_TRK | UHSIC_PD_RX |
1804                         UHSIC_PD_ZI | UHSIC_RPD_DATA | UHSIC_RPD_STROBE);
1805         val |= UHSIC_RX_SEL;
1806         writel(val, base + UHSIC_PADS_CFG1);
1807         udelay(2);
1808
1809         val = readl(base + USB_SUSP_CTRL);
1810         val |= UHSIC_RESET;
1811         writel(val, base + USB_SUSP_CTRL);
1812         udelay(30);
1813
1814         val = readl(base + USB_SUSP_CTRL);
1815         val |= UHSIC_PHY_ENABLE;
1816         writel(val, base + USB_SUSP_CTRL);
1817
1818         val = readl(base + UHSIC_HSRX_CFG0);
1819         val |= UHSIC_IDLE_WAIT(config->idle_wait_delay);
1820         val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(config->elastic_underrun_limit);
1821         val |= UHSIC_ELASTIC_OVERRUN_LIMIT(config->elastic_overrun_limit);
1822         writel(val, base + UHSIC_HSRX_CFG0);
1823
1824         val = readl(base + UHSIC_HSRX_CFG1);
1825         val |= UHSIC_HS_SYNC_START_DLY(config->sync_start_delay);
1826         writel(val, base + UHSIC_HSRX_CFG1);
1827
1828         /* WAR HSIC TX */
1829         val = readl(base + UHSIC_TX_CFG0);
1830         val &= ~UHSIC_HS_READY_WAIT_FOR_VALID;
1831         writel(val, base + UHSIC_TX_CFG0);
1832
1833         val = readl(base + UHSIC_MISC_CFG0);
1834         val |= UHSIC_SUSPEND_EXIT_ON_EDGE;
1835         /* Disable generic bus reset, to allow AP30 specific bus reset*/
1836         val |= UHSIC_DISABLE_BUSRESET;
1837         writel(val, base + UHSIC_MISC_CFG0);
1838
1839         val = readl(base + UHSIC_MISC_CFG1);
1840         val |= UHSIC_PLLU_STABLE_COUNT(phy->freq->stable_count);
1841         writel(val, base + UHSIC_MISC_CFG1);
1842
1843         val = readl(base + UHSIC_PLL_CFG1);
1844         val |= UHSIC_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
1845         val |= UHSIC_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count);
1846         writel(val, base + UHSIC_PLL_CFG1);
1847
1848         val = readl(base + USB_SUSP_CTRL);
1849         val &= ~(UHSIC_RESET);
1850         writel(val, base + USB_SUSP_CTRL);
1851         udelay(2);
1852
1853         val = readl(base + USB_USBMODE);
1854         val |= USB_USBMODE_HOST;
1855         writel(val, base + USB_USBMODE);
1856
1857         /* Change the USB controller PHY type to HSIC */
1858         val = readl(base + HOSTPC1_DEVLC);
1859         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
1860         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
1861         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
1862         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
1863         writel(val, base + HOSTPC1_DEVLC);
1864
1865         val = readl(base + USB_TXFILLTUNING);
1866         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
1867                 val = USB_FIFO_TXFILL_THRES(0x10);
1868                 writel(val, base + USB_TXFILLTUNING);
1869         }
1870
1871         val = readl(base + USB_PORTSC);
1872         val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN);
1873         writel(val, base + USB_PORTSC);
1874
1875         val = readl(base + UHSIC_PADS_CFG0);
1876         val &= ~(UHSIC_TX_RTUNEN);
1877         /* set Rtune impedance to 50 ohm */
1878         val |= UHSIC_TX_RTUNE(8);
1879         writel(val, base + UHSIC_PADS_CFG0);
1880
1881         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1882                                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500)) {
1883                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
1884                 return -ETIMEDOUT;
1885         }
1886
1887         phy->phy_clk_on = true;
1888         phy->hw_accessible = true;
1889
1890         return 0;
1891 }
1892
1893 static int uhsic_phy_power_off(struct tegra_usb_phy *phy)
1894 {
1895         unsigned long val;
1896         void __iomem *base = phy->regs;
1897
1898         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1899         if (!phy->phy_clk_on) {
1900                 DBG("%s(%d) inst:[%d] phy clk is already off\n",
1901                                         __func__, __LINE__, phy->inst);
1902                 return 0;
1903         }
1904
1905         val = readl(base + UHSIC_PADS_CFG1);
1906         val &= ~UHSIC_RPU_STROBE;
1907         val |= UHSIC_RPD_STROBE;
1908         writel(val, base + UHSIC_PADS_CFG1);
1909
1910         val = readl(base + USB_SUSP_CTRL);
1911         val |= UHSIC_RESET;
1912         writel(val, base + USB_SUSP_CTRL);
1913         udelay(30);
1914
1915         uhsic_powerdown_pmc_wake_detect(phy);
1916
1917         phy->phy_clk_on = false;
1918         phy->hw_accessible = false;
1919
1920         return 0;
1921 }
1922
1923 int uhsic_phy_bus_port_power(struct tegra_usb_phy *phy)
1924 {
1925         unsigned long val;
1926         void __iomem *base = phy->regs;
1927
1928         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1929         val = readl(base + UHSIC_STAT_CFG0);
1930         val &= ~UHSIC_CONNECT_DETECT;
1931         writel(val, base + UHSIC_STAT_CFG0);
1932
1933         val = readl(base + USB_USBMODE);
1934         val |= USB_USBMODE_HOST;
1935         writel(val, base + USB_USBMODE);
1936
1937         /* Change the USB controller PHY type to HSIC */
1938         val = readl(base + HOSTPC1_DEVLC);
1939         val &= ~(HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK));
1940         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
1941         val &= ~(HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK));
1942         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
1943         writel(val, base + HOSTPC1_DEVLC);
1944
1945         val = readl(base + UHSIC_MISC_CFG0);
1946         val |= UHSIC_DETECT_SHORT_CONNECT;
1947         writel(val, base + UHSIC_MISC_CFG0);
1948         udelay(1);
1949
1950         val = readl(base + UHSIC_MISC_CFG0);
1951         val |= UHSIC_FORCE_XCVR_MODE;
1952         writel(val, base + UHSIC_MISC_CFG0);
1953
1954         val = readl(base + UHSIC_PADS_CFG1);
1955         val &= ~UHSIC_RPD_STROBE;
1956         /* safe to enable RPU on STROBE at all times during idle */
1957         val |= UHSIC_RPU_STROBE;
1958         writel(val, base + UHSIC_PADS_CFG1);
1959
1960         val = readl(base + USB_USBCMD);
1961         val &= ~USB_USBCMD_RS;
1962         writel(val, base + USB_USBCMD);
1963
1964         if (usb_phy_reg_status_wait(base + UHSIC_STAT_CFG0,
1965                         UHSIC_CONNECT_DETECT, UHSIC_CONNECT_DETECT, 25000)) {
1966                 pr_err("%s: timeout waiting for UHSIC_CONNECT_DETECT\n",
1967                                                                 __func__);
1968                 return -ETIMEDOUT;
1969         }
1970
1971         return 0;
1972 }
1973
1974 static int uhsic_phy_bus_reset(struct tegra_usb_phy *phy)
1975 {
1976         unsigned long val;
1977         void __iomem *base = phy->regs;
1978
1979         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1980
1981         /* Change the USB controller PHY type to HSIC */
1982         val = readl(base + HOSTPC1_DEVLC);
1983         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
1984         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
1985         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
1986         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
1987         writel(val, base + HOSTPC1_DEVLC);
1988         /* wait here, otherwise HOSTPC1_DEVLC_PSPD will timeout */
1989         mdelay(5);
1990
1991         val = readl(base + USB_PORTSC);
1992         val |= USB_PORTSC_PTC(5);
1993         writel(val, base + USB_PORTSC);
1994         udelay(2);
1995
1996         val = readl(base + USB_PORTSC);
1997         val &= ~(USB_PORTSC_PTC(~0));
1998         writel(val, base + USB_PORTSC);
1999         udelay(2);
2000
2001         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_LS(0),
2002                                                  0, 2000)) {
2003                 pr_err("%s: timeout waiting for USB_PORTSC_LS\n", __func__);
2004                 return -ETIMEDOUT;
2005         }
2006
2007         /* Poll until CCS is enabled */
2008         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
2009                                                  USB_PORTSC_CCS, 2000)) {
2010                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
2011                 return -ETIMEDOUT;
2012         }
2013
2014         if (usb_phy_reg_status_wait(base + HOSTPC1_DEVLC,
2015                         HOSTPC1_DEVLC_PSPD(2),
2016                         HOSTPC1_DEVLC_PSPD(2), 2000) < 0) {
2017                 pr_err("%s: timeout waiting hsic high speed configuration\n",
2018                                                 __func__);
2019                         return -ETIMEDOUT;
2020         }
2021
2022         val = readl(base + USB_USBCMD);
2023         val &= ~USB_USBCMD_RS;
2024         writel(val, base + USB_USBCMD);
2025
2026         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
2027                                                  USB_USBSTS_HCH, 2000)) {
2028                 pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
2029                 return -ETIMEDOUT;
2030         }
2031
2032         val = readl(base + UHSIC_PADS_CFG1);
2033         val &= ~UHSIC_RPU_STROBE;
2034         val |= UHSIC_RPD_STROBE;
2035         writel(val, base + UHSIC_PADS_CFG1);
2036
2037         mdelay(50);
2038
2039         val = readl(base + UHSIC_PADS_CFG1);
2040         val &= ~UHSIC_RPD_STROBE;
2041         val |= UHSIC_RPU_STROBE;
2042         writel(val, base + UHSIC_PADS_CFG1);
2043
2044         val = readl(base + USB_USBCMD);
2045         val |= USB_USBCMD_RS;
2046         writel(val, base + USB_USBCMD);
2047
2048         val = readl(base + UHSIC_PADS_CFG1);
2049         val &= ~UHSIC_RPU_STROBE;
2050         writel(val, base + UHSIC_PADS_CFG1);
2051
2052         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2053                                                  USB_USBCMD_RS, 2000)) {
2054                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2055                 return -ETIMEDOUT;
2056         }
2057
2058         return 0;
2059 }
2060
2061
2062 int uhsic_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
2063 {
2064         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2065
2066         usb_phy_wait_for_sof(phy);
2067
2068         return 0;
2069 }
2070
2071 int uhsic_phy_resume(struct tegra_usb_phy *phy)
2072 {
2073         void __iomem *base = phy->regs;
2074         unsigned long val;
2075
2076         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2077
2078         /* Check if the phy resume from LP0. When the phy resume from LP0
2079          * USB register will be reset.to zero */
2080         if (!readl(base + USB_ASYNCLISTADDR)) {
2081
2082                 val = readl(base + USB_USBCMD);
2083                 val |= USB_CMD_RESET;
2084                 writel(val, base + USB_USBCMD);
2085
2086                 if (usb_phy_reg_status_wait(base + USB_USBCMD,
2087                         USB_CMD_RESET, 0, 2500) < 0) {
2088                         pr_err("%s: timeout waiting for reset\n", __func__);
2089                 }
2090
2091                 val = readl(base + USB_USBMODE);
2092                 val &= ~USB_USBMODE_MASK;
2093                 val |= USB_USBMODE_HOST;
2094                 writel(val, base + USB_USBMODE);
2095
2096                 /* Enable Port Power */
2097                 val = readl(base + USB_PORTSC);
2098                 val |= USB_PORTSC_PP;
2099                 writel(val, base + USB_PORTSC);
2100                 udelay(10);
2101
2102                 DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
2103                 readl(base + USB_USBSTS), readl(base + USB_PORTSC));
2104
2105                 uhsic_phy_bus_port_power(phy);
2106         }
2107
2108         return 0;
2109 }
2110
2111 static int uhsic_phy_post_resume(struct tegra_usb_phy *phy)
2112 {
2113         unsigned long val;
2114         void __iomem *base = phy->regs;
2115
2116         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2117         val = readl(base + USB_TXFILLTUNING);
2118         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
2119                 val = USB_FIFO_TXFILL_THRES(0x10);
2120                 writel(val, base + USB_TXFILLTUNING);
2121         }
2122
2123         return 0;
2124 }
2125
2126 static void ulpi_set_trimmer(struct tegra_usb_phy *phy)
2127 {
2128         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2129         void __iomem *base = phy->regs;
2130         unsigned long val;
2131
2132         val = ULPI_DATA_TRIMMER_SEL(config->data_trimmer);
2133         val |= ULPI_STPDIRNXT_TRIMMER_SEL(config->stpdirnxt_trimmer);
2134         val |= ULPI_DIR_TRIMMER_SEL(config->dir_trimmer);
2135         writel(val, base + ULPI_TIMING_CTRL_1);
2136         udelay(10);
2137
2138         val |= ULPI_DATA_TRIMMER_LOAD;
2139         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
2140         val |= ULPI_DIR_TRIMMER_LOAD;
2141         writel(val, base + ULPI_TIMING_CTRL_1);
2142 }
2143
2144 static void reset_utmip_uhsic(void __iomem *base)
2145 {
2146         unsigned long val;
2147
2148         val = readl(base + USB_SUSP_CTRL);
2149         val |= UHSIC_RESET;
2150         writel(val, base + USB_SUSP_CTRL);
2151
2152         val = readl(base + USB_SUSP_CTRL);
2153         val |= UTMIP_RESET;
2154         writel(val, base + USB_SUSP_CTRL);
2155 }
2156
2157 static void ulpi_set_host(void __iomem *base)
2158 {
2159         unsigned long val;
2160
2161         val = readl(base + USB_USBMODE);
2162         val |= USB_USBMODE_HOST;
2163         writel(val, base + USB_USBMODE);
2164
2165         val = readl(base + HOSTPC1_DEVLC);
2166         val |= HOSTPC1_DEVLC_PTS(2);
2167         writel(val, base + HOSTPC1_DEVLC);
2168 }
2169
2170
2171 static int ulpi_null_phy_power_off(struct tegra_usb_phy *phy)
2172 {
2173         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2174
2175         if (!phy->phy_clk_on) {
2176                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
2177                                                         __LINE__, phy->inst);
2178                 return 0;
2179         }
2180
2181         phy->phy_clk_on = false;
2182         phy->hw_accessible = false;
2183
2184         return 0;
2185 }
2186
2187 static int ulpi_null_phy_init(struct tegra_usb_phy *phy)
2188 {
2189         unsigned long val;
2190         void __iomem *base = phy->regs;
2191
2192         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2193         val = readl(base + ULPIS2S_CTRL);
2194         val |=  ULPIS2S_SLV0_CLAMP_XMIT;
2195         writel(val, base + ULPIS2S_CTRL);
2196
2197         val = readl(base + USB_SUSP_CTRL);
2198         val |= ULPIS2S_SLV0_RESET;
2199         writel(val, base + USB_SUSP_CTRL);
2200         udelay(10);
2201
2202         return 0;
2203 }
2204
2205 static int ulpi_null_phy_irq(struct tegra_usb_phy *phy)
2206 {
2207         usb_phy_fence_read(phy);
2208         return IRQ_HANDLED;
2209 }
2210
2211 static int ulpi_null_phy_cmd_reset(struct tegra_usb_phy *phy)
2212 {
2213         unsigned long val;
2214         void __iomem *base = phy->regs;
2215
2216         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2217         ulpi_set_host(base);
2218
2219         /* remove slave0 reset */
2220         val = readl(base + USB_SUSP_CTRL);
2221         val &= ~ULPIS2S_SLV0_RESET;
2222         writel(val, base + USB_SUSP_CTRL);
2223
2224         val = readl(base + ULPIS2S_CTRL);
2225         val &=  ~ULPIS2S_SLV0_CLAMP_XMIT;
2226         writel(val, base + ULPIS2S_CTRL);
2227         udelay(10);
2228
2229         return 0;
2230 }
2231
2232 static int ulpi_null_phy_lp0_resume(struct tegra_usb_phy *phy)
2233 {
2234         unsigned long val;
2235         void __iomem *base = phy->regs;
2236
2237         ulpi_null_phy_init(phy);
2238
2239         val = readl(base + USB_USBCMD);
2240         val |= USB_CMD_RESET;
2241         writel(val, base + USB_USBCMD);
2242
2243         if (usb_phy_reg_status_wait(base + USB_USBCMD,
2244                 USB_CMD_RESET, 0, 2500) < 0) {
2245                 pr_err("%s: timeout waiting for reset\n", __func__);
2246         }
2247
2248         val = readl(base + USB_USBMODE);
2249         val &= ~USB_USBMODE_MASK;
2250         val |= USB_USBMODE_HOST;
2251         writel(val, base + USB_USBMODE);
2252
2253         ulpi_null_phy_cmd_reset(phy);
2254
2255         val = readl(base + USB_USBCMD);
2256         val |= USB_USBCMD_RS;
2257         writel(val, base + USB_USBCMD);
2258         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2259                                                  USB_USBCMD_RS, 2000)) {
2260                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2261                 return -ETIMEDOUT;
2262         }
2263
2264         /* Enable Port Power */
2265         val = readl(base + USB_PORTSC);
2266         val |= USB_PORTSC_PP;
2267         writel(val, base + USB_PORTSC);
2268         udelay(10);
2269
2270         /* disable ULPI pinmux bypass */
2271         val = readl(base + ULPI_TIMING_CTRL_0);
2272         val &= ~ULPI_OUTPUT_PINMUX_BYP;
2273         writel(val, base + ULPI_TIMING_CTRL_0);
2274
2275         return 0;
2276 }
2277
2278 static int ulpi_null_phy_power_on(struct tegra_usb_phy *phy)
2279 {
2280         unsigned long val;
2281         void __iomem *base = phy->regs;
2282         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2283         static bool cold_boot = true;
2284
2285         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2286         if (phy->phy_clk_on) {
2287                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
2288                                                         __LINE__, phy->inst);
2289                 return 0;
2290         }
2291         reset_utmip_uhsic(base);
2292
2293         /* remove ULPI PADS CLKEN reset */
2294         val = readl(base + USB_SUSP_CTRL);
2295         val &= ~ULPI_PADS_CLKEN_RESET;
2296         writel(val, base + USB_SUSP_CTRL);
2297         udelay(10);
2298
2299         val = readl(base + ULPI_TIMING_CTRL_0);
2300         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
2301         writel(val, base + ULPI_TIMING_CTRL_0);
2302
2303         val = readl(base + USB_SUSP_CTRL);
2304         val |= ULPI_PHY_ENABLE;
2305         writel(val, base + USB_SUSP_CTRL);
2306         udelay(10);
2307
2308         /* set timming parameters */
2309         val = readl(base + ULPI_TIMING_CTRL_0);
2310         val |= ULPI_SHADOW_CLK_LOOPBACK_EN;
2311         val &= ~ULPI_SHADOW_CLK_SEL;
2312         val &= ~ULPI_LBK_PAD_EN;
2313         val |= ULPI_SHADOW_CLK_DELAY(config->shadow_clk_delay);
2314         val |= ULPI_CLOCK_OUT_DELAY(config->clock_out_delay);
2315         val |= ULPI_LBK_PAD_E_INPUT_OR;
2316         writel(val, base + ULPI_TIMING_CTRL_0);
2317
2318         writel(0, base + ULPI_TIMING_CTRL_1);
2319         udelay(10);
2320
2321         /* start internal 60MHz clock */
2322         val = readl(base + ULPIS2S_CTRL);
2323         val |= ULPIS2S_ENA;
2324         val |= ULPIS2S_SUPPORT_DISCONNECT;
2325         val |= ULPIS2S_SPARE((phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) ? 3 : 1);
2326         val |= ULPIS2S_PLLU_MASTER_BLASTER60;
2327         writel(val, base + ULPIS2S_CTRL);
2328
2329         /* select ULPI_CORE_CLK_SEL to SHADOW_CLK */
2330         val = readl(base + ULPI_TIMING_CTRL_0);
2331         val |= ULPI_CORE_CLK_SEL;
2332         writel(val, base + ULPI_TIMING_CTRL_0);
2333         udelay(10);
2334
2335         /* enable ULPI null phy clock - can't set the trimmers before this */
2336         val = readl(base + ULPI_TIMING_CTRL_0);
2337         val |= ULPI_CLK_OUT_ENA;
2338         writel(val, base + ULPI_TIMING_CTRL_0);
2339         udelay(10);
2340
2341         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
2342                                                  USB_PHY_CLK_VALID, 2500)) {
2343                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2344                 return -ETIMEDOUT;
2345         }
2346
2347         /* set ULPI trimmers */
2348         ulpi_set_trimmer(phy);
2349
2350         ulpi_set_host(base);
2351
2352         /* remove slave0 reset */
2353         val = readl(base + USB_SUSP_CTRL);
2354         val &= ~ULPIS2S_SLV0_RESET;
2355         writel(val, base + USB_SUSP_CTRL);
2356
2357         /* remove slave1 and line reset */
2358         val = readl(base + USB_SUSP_CTRL);
2359         val &= ~ULPIS2S_SLV1_RESET;
2360         val &= ~ULPIS2S_LINE_RESET;
2361
2362         /* remove ULPI PADS reset */
2363         val &= ~ULPI_PADS_RESET;
2364         writel(val, base + USB_SUSP_CTRL);
2365
2366         if (cold_boot) {
2367                 val = readl(base + ULPI_TIMING_CTRL_0);
2368                 val |= ULPI_CLK_PADOUT_ENA;
2369                 writel(val, base + ULPI_TIMING_CTRL_0);
2370                 cold_boot = false;
2371         } else {
2372                 if (!readl(base + USB_ASYNCLISTADDR))
2373                         ulpi_null_phy_lp0_resume(phy);
2374         }
2375         udelay(10);
2376
2377         phy->phy_clk_on = true;
2378         phy->hw_accessible = true;
2379
2380         return 0;
2381 }
2382
2383
2384 int ulpi_null_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
2385 {
2386         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2387
2388         usb_phy_wait_for_sof(phy);
2389         return 0;
2390 }
2391
2392 static int ulpi_null_phy_resume(struct tegra_usb_phy *phy)
2393 {
2394         unsigned long val;
2395         void __iomem *base = phy->regs;
2396
2397         if (!readl(base + USB_ASYNCLISTADDR)) {
2398                 /* enable ULPI CLK output pad */
2399                 val = readl(base + ULPI_TIMING_CTRL_0);
2400                 val |= ULPI_CLK_PADOUT_ENA;
2401                 writel(val, base + ULPI_TIMING_CTRL_0);
2402
2403                 /* enable ULPI pinmux bypass */
2404                 val = readl(base + ULPI_TIMING_CTRL_0);
2405                 val |= ULPI_OUTPUT_PINMUX_BYP;
2406                 writel(val, base + ULPI_TIMING_CTRL_0);
2407                 udelay(5);
2408 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2409                 /* remove DIR tristate */
2410                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR, TEGRA_TRI_NORMAL);
2411 #endif
2412         }
2413         return 0;
2414 }
2415
2416
2417
2418 static struct tegra_usb_phy_ops utmi_phy_ops = {
2419         .open           = utmi_phy_open,
2420         .close          = utmi_phy_close,
2421         .irq            = utmi_phy_irq,
2422         .power_on       = utmi_phy_power_on,
2423         .power_off      = utmi_phy_power_off,
2424         .pre_resume = utmi_phy_pre_resume,
2425         .resume = utmi_phy_resume,
2426         .post_resume    = utmi_phy_post_resume,
2427         .charger_detect = utmi_phy_charger_detect,
2428 };
2429
2430 static struct tegra_usb_phy_ops uhsic_phy_ops = {
2431         .open           = uhsic_phy_open,
2432         .irq            = uhsic_phy_irq,
2433         .power_on       = uhsic_phy_power_on,
2434         .power_off      = uhsic_phy_power_off,
2435         .pre_resume = uhsic_phy_pre_resume,
2436         .resume = uhsic_phy_resume,
2437         .post_resume = uhsic_phy_post_resume,
2438         .port_power = uhsic_phy_bus_port_power,
2439         .bus_reset      = uhsic_phy_bus_reset,
2440 };
2441
2442 static struct tegra_usb_phy_ops ulpi_null_phy_ops = {
2443         .init           = ulpi_null_phy_init,
2444         .irq            = ulpi_null_phy_irq,
2445         .power_on       = ulpi_null_phy_power_on,
2446         .power_off      = ulpi_null_phy_power_off,
2447         .pre_resume = ulpi_null_phy_pre_resume,
2448         .resume = ulpi_null_phy_resume,
2449         .reset          = ulpi_null_phy_cmd_reset,
2450 };
2451
2452 static struct tegra_usb_phy_ops ulpi_link_phy_ops;
2453 static struct tegra_usb_phy_ops icusb_phy_ops;
2454
2455 static struct tegra_usb_phy_ops *phy_ops[] = {
2456         [TEGRA_USB_PHY_INTF_UTMI] = &utmi_phy_ops,
2457         [TEGRA_USB_PHY_INTF_ULPI_LINK] = &ulpi_link_phy_ops,
2458         [TEGRA_USB_PHY_INTF_ULPI_NULL] = &ulpi_null_phy_ops,
2459         [TEGRA_USB_PHY_INTF_HSIC] = &uhsic_phy_ops,
2460         [TEGRA_USB_PHY_INTF_ICUSB] = &icusb_phy_ops,
2461 };
2462
2463 int tegra3_usb_phy_init_ops(struct tegra_usb_phy *phy)
2464 {
2465         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2466
2467         phy->ops = phy_ops[phy->pdata->phy_intf];
2468
2469         /* FIXME: uncommenting below line to make USB host mode fail*/
2470         /* usb_phy_power_down_pmc(); */
2471
2472         return 0;
2473 }