ARM: tegra: usb_phy: Fix for glitch on STROBE line
[linux-2.6.git] / arch / arm / mach-tegra / tegra3_usb_phy.c
1 /*
2  * arch/arm/mach-tegra/tegra3_usb_phy.c
3  *
4  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
5  *
6  *
7  * This software is licensed under the terms of the GNU General Public
8  * License version 2, as published by the Free Software Foundation, and
9  * may be copied, distributed, and modified under those terms.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17 #include <linux/resource.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/slab.h>
21 #include <linux/err.h>
22 #include <linux/platform_device.h>
23 #include <linux/io.h>
24 #include <linux/gpio.h>
25 #include <linux/interrupt.h>
26 #include <linux/clk.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <mach/clk.h>
30 #include <mach/iomap.h>
31 #include <mach/pinmux.h>
32 #include "tegra_usb_phy.h"
33 #include "gpio-names.h"
34 #include "fuse.h"
35
36 #define USB_USBCMD              0x130
37 #define   USB_USBCMD_RS         (1 << 0)
38 #define   USB_CMD_RESET (1<<1)
39
40 #define USB_USBSTS              0x134
41 #define   USB_USBSTS_PCI        (1 << 2)
42 #define   USB_USBSTS_SRI        (1 << 7)
43 #define   USB_USBSTS_HCH        (1 << 12)
44
45 #define USB_USBINTR             0x138
46
47 #define USB_TXFILLTUNING        0x154
48 #define USB_FIFO_TXFILL_THRES(x)   (((x) & 0x1f) << 16)
49 #define USB_FIFO_TXFILL_MASK    0x1f0000
50
51 #define USB_ASYNCLISTADDR       0x148
52
53 #define ICUSB_CTRL              0x15c
54
55 #define USB_PORTSC              0x174
56 #define   USB_PORTSC_WKOC       (1 << 22)
57 #define   USB_PORTSC_WKDS       (1 << 21)
58 #define   USB_PORTSC_WKCN       (1 << 20)
59 #define   USB_PORTSC_PTC(x)     (((x) & 0xf) << 16)
60 #define   USB_PORTSC_PP (1 << 12)
61 #define   USB_PORTSC_LS(x) (((x) & 0x3) << 10)
62 #define   USB_PORTSC_SUSP       (1 << 7)
63 #define   USB_PORTSC_RESUME     (1 << 6)
64 #define   USB_PORTSC_OCC        (1 << 5)
65 #define   USB_PORTSC_PEC        (1 << 3)
66 #define   USB_PORTSC_PE         (1 << 2)
67 #define   USB_PORTSC_CSC        (1 << 1)
68 #define   USB_PORTSC_CCS        (1 << 0)
69 #define   USB_PORTSC_RWC_BITS (USB_PORTSC_CSC | USB_PORTSC_PEC | USB_PORTSC_OCC)
70
71 #define HOSTPC1_DEVLC           0x1b4
72 #define   HOSTPC1_DEVLC_PHCD            (1 << 22)
73 #define   HOSTPC1_DEVLC_PTS(x)          (((x) & 0x7) << 29)
74 #define   HOSTPC1_DEVLC_PTS_MASK        7
75 #define   HOSTPC1_DEVLC_PTS_HSIC        4
76 #define   HOSTPC1_DEVLC_STS             (1 << 28)
77 #define   HOSTPC1_DEVLC_PSPD(x)         (((x) & 0x3) << 25)
78 #define   HOSTPC1_DEVLC_PSPD_MASK       3
79 #define   HOSTPC1_DEVLC_PSPD_HIGH_SPEED 2
80
81 #define USB_USBMODE             0x1f8
82 #define   USB_USBMODE_MASK              (3 << 0)
83 #define   USB_USBMODE_HOST              (3 << 0)
84 #define   USB_USBMODE_DEVICE            (2 << 0)
85
86 #define USB_SUSP_CTRL           0x400
87 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
88 #define   USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
89 #define   USB_SUSP_CLR                  (1 << 5)
90 #define   USB_PHY_CLK_VALID             (1 << 7)
91 #define   USB_PHY_CLK_VALID_INT_ENB     (1 << 9)
92 #define   USB_PHY_CLK_VALID_INT_STS     (1 << 8)
93 #define   UTMIP_RESET                   (1 << 11)
94 #define   UTMIP_PHY_ENABLE              (1 << 12)
95 #define   ULPI_PHY_ENABLE               (1 << 13)
96 #define   UHSIC_RESET                   (1 << 14)
97 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
98 #define   UHSIC_PHY_ENABLE              (1 << 19)
99 #define   ULPIS2S_SLV0_RESET            (1 << 20)
100 #define   ULPIS2S_SLV1_RESET            (1 << 21)
101 #define   ULPIS2S_LINE_RESET            (1 << 22)
102 #define   ULPI_PADS_RESET               (1 << 23)
103 #define   ULPI_PADS_CLKEN_RESET         (1 << 24)
104
105 #define USB_PHY_VBUS_WAKEUP_ID  0x408
106 #define   VDAT_DET_INT_EN       (1 << 16)
107 #define   VDAT_DET_CHG_DET      (1 << 17)
108 #define   VDAT_DET_STS          (1 << 18)
109 #define   USB_ID_STATUS         (1 << 2)
110
111 #define ULPIS2S_CTRL            0x418
112 #define   ULPIS2S_ENA                   (1 << 0)
113 #define   ULPIS2S_SUPPORT_DISCONNECT    (1 << 2)
114 #define   ULPIS2S_PLLU_MASTER_BLASTER60 (1 << 3)
115 #define   ULPIS2S_SPARE(x)              (((x) & 0xF) << 8)
116 #define   ULPIS2S_FORCE_ULPI_CLK_OUT    (1 << 12)
117 #define   ULPIS2S_DISCON_DONT_CHECK_SE0 (1 << 13)
118 #define   ULPIS2S_SUPPORT_HS_KEEP_ALIVE (1 << 14)
119 #define   ULPIS2S_DISABLE_STP_PU        (1 << 15)
120 #define   ULPIS2S_SLV0_CLAMP_XMIT       (1 << 16)
121
122 #define ULPI_TIMING_CTRL_0      0x424
123 #define   ULPI_CLOCK_OUT_DELAY(x)       ((x) & 0x1F)
124 #define   ULPI_OUTPUT_PINMUX_BYP        (1 << 10)
125 #define   ULPI_CLKOUT_PINMUX_BYP        (1 << 11)
126 #define   ULPI_SHADOW_CLK_LOOPBACK_EN   (1 << 12)
127 #define   ULPI_SHADOW_CLK_SEL           (1 << 13)
128 #define   ULPI_CORE_CLK_SEL             (1 << 14)
129 #define   ULPI_SHADOW_CLK_DELAY(x)      (((x) & 0x1F) << 16)
130 #define   ULPI_LBK_PAD_EN               (1 << 26)
131 #define   ULPI_LBK_PAD_E_INPUT_OR       (1 << 27)
132 #define   ULPI_CLK_OUT_ENA              (1 << 28)
133 #define   ULPI_CLK_PADOUT_ENA           (1 << 29)
134
135 #define ULPI_TIMING_CTRL_1      0x428
136 #define   ULPI_DATA_TRIMMER_LOAD        (1 << 0)
137 #define   ULPI_DATA_TRIMMER_SEL(x)      (((x) & 0x7) << 1)
138 #define   ULPI_STPDIRNXT_TRIMMER_LOAD   (1 << 16)
139 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
140 #define   ULPI_DIR_TRIMMER_LOAD         (1 << 24)
141 #define   ULPI_DIR_TRIMMER_SEL(x)       (((x) & 0x7) << 25)
142
143 #define UTMIP_XCVR_CFG0         0x808
144 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
145 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
146 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
147 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
148 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
149 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
150 #define   UTMIP_XCVR_LSBIAS_SEL                 (1 << 21)
151 #define   UTMIP_XCVR_SETUP_MSB(x)               (((x) & 0x7) << 22)
152 #define   UTMIP_XCVR_HSSLEW_MSB(x)              (((x) & 0x7f) << 25)
153 #define   UTMIP_XCVR_MAX_OFFSET         2
154 #define   UTMIP_XCVR_SETUP_MAX_VALUE    0x7f
155 #define   UTMIP_XCVR_SETUP_MIN_VALUE    0
156 #define   XCVR_SETUP_MSB_CALIB(x) ((x) >> 4)
157
158 #define UTMIP_BIAS_CFG0         0x80c
159 #define   UTMIP_OTGPD                   (1 << 11)
160 #define   UTMIP_BIASPD                  (1 << 10)
161 #define   UTMIP_HSSQUELCH_LEVEL(x)      (((x) & 0x3) << 0)
162 #define   UTMIP_HSDISCON_LEVEL(x)       (((x) & 0x3) << 2)
163 #define   UTMIP_HSDISCON_LEVEL_MSB      (1 << 24)
164
165 #define UTMIP_HSRX_CFG0         0x810
166 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
167 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
168
169 #define UTMIP_HSRX_CFG1         0x814
170 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
171
172 #define UTMIP_TX_CFG0           0x820
173 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
174 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
175
176 #define UTMIP_DEBOUNCE_CFG0 0x82c
177 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
178
179 #define UTMIP_BAT_CHRG_CFG0 0x830
180 #define   UTMIP_PD_CHRG                 (1 << 0)
181 #define   UTMIP_ON_SINK_EN              (1 << 2)
182 #define   UTMIP_OP_SRC_EN               (1 << 3)
183
184 #define UTMIP_XCVR_CFG1         0x838
185 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
186 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
187 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
188 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
189
190 #define UTMIP_BIAS_CFG1         0x83c
191 #define   UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
192 #define   UTMIP_BIAS_PDTRK_POWERDOWN    (1 << 0)
193 #define   UTMIP_BIAS_PDTRK_POWERUP      (1 << 1)
194
195 #define UTMIP_MISC_CFG0         0x824
196 #define   UTMIP_DPDM_OBSERVE            (1 << 26)
197 #define   UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
198 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J   UTMIP_DPDM_OBSERVE_SEL(0xf)
199 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K   UTMIP_DPDM_OBSERVE_SEL(0xe)
200 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
201 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
202 #define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
203 #define   FORCE_PULLDN_DM       (1 << 8)
204 #define   FORCE_PULLDN_DP       (1 << 9)
205 #define   COMB_TERMS            (1 << 0)
206 #define   ALWAYS_FREE_RUNNING_TERMS (1 << 1)
207
208 #define UTMIP_SPARE_CFG0        0x834
209 #define   FUSE_SETUP_SEL                (1 << 3)
210 #define   FUSE_ATERM_SEL                (1 << 4)
211
212 #define UTMIP_PMC_WAKEUP0               0x84c
213 #define   EVENT_INT_ENB                 (1 << 0)
214
215 #define UHSIC_PMC_WAKEUP0               0xc34
216
217 #define UTMIP_BIAS_STS0                 0x840
218 #define   UTMIP_RCTRL_VAL(x)            (((x) & 0xffff) << 0)
219 #define   UTMIP_TCTRL_VAL(x)            (((x) & (0xffff << 16)) >> 16)
220
221 #define UHSIC_PLL_CFG1                          0xc04
222 #define   UHSIC_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
223 #define   UHSIC_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 14)
224
225 #define UHSIC_HSRX_CFG0                         0xc08
226 #define   UHSIC_ELASTIC_UNDERRUN_LIMIT(x)       (((x) & 0x1f) << 2)
227 #define   UHSIC_ELASTIC_OVERRUN_LIMIT(x)        (((x) & 0x1f) << 8)
228 #define   UHSIC_IDLE_WAIT(x)                    (((x) & 0x1f) << 13)
229
230 #define UHSIC_HSRX_CFG1                         0xc0c
231 #define   UHSIC_HS_SYNC_START_DLY(x)            (((x) & 0x1f) << 1)
232
233 #define UHSIC_TX_CFG0                           0xc10
234 #define UHSIC_HS_READY_WAIT_FOR_VALID   (1 << 9)
235 #define UHSIC_MISC_CFG0                         0xc14
236 #define   UHSIC_SUSPEND_EXIT_ON_EDGE            (1 << 7)
237 #define   UHSIC_DETECT_SHORT_CONNECT            (1 << 8)
238 #define   UHSIC_FORCE_XCVR_MODE                 (1 << 15)
239 #define   UHSIC_DISABLE_BUSRESET                (1 << 20)
240 #define UHSIC_MISC_CFG1                         0xc18
241 #define   UHSIC_PLLU_STABLE_COUNT(x)            (((x) & 0xfff) << 2)
242
243 #define UHSIC_PADS_CFG0                         0xc1c
244 #define   UHSIC_TX_RTUNEN                       0xf000
245 #define   UHSIC_TX_RTUNE(x)                     (((x) & 0xf) << 12)
246
247 #define UHSIC_PADS_CFG1                         0xc20
248 #define   UHSIC_PD_BG                           (1 << 2)
249 #define   UHSIC_PD_TX                           (1 << 3)
250 #define   UHSIC_PD_TRK                          (1 << 4)
251 #define   UHSIC_PD_RX                           (1 << 5)
252 #define   UHSIC_PD_ZI                           (1 << 6)
253 #define   UHSIC_RX_SEL                          (1 << 7)
254 #define   UHSIC_RPD_DATA                        (1 << 9)
255 #define   UHSIC_RPD_STROBE                      (1 << 10)
256 #define   UHSIC_RPU_DATA                        (1 << 11)
257 #define   UHSIC_RPU_STROBE                      (1 << 12)
258
259 #define UHSIC_CMD_CFG0                  0xc24
260 #define UHSIC_PRETEND_CONNECT_DETECT    (1 << 5)
261
262 #define UHSIC_STAT_CFG0         0xc28
263 #define UHSIC_CONNECT_DETECT            (1 << 0)
264
265 #define PMC_USB_DEBOUNCE                        0xec
266 #define UTMIP_LINE_DEB_CNT(x)           (((x) & 0xf) << 16)
267 #define UHSIC_LINE_DEB_CNT(x)           (((x) & 0xf) << 20)
268
269 #define PMC_USB_AO                              0xf0
270
271 #define PMC_POWER_DOWN_MASK                     0xffff
272 #define HSIC_RESERVED_P0                        (3 << 14)
273 #define STROBE_VAL_PD_P0                        (1 << 12)
274 #define DATA_VAL_PD_P0                          (1 << 13)
275
276 #define USB_ID_PD(inst)                 (1 << ((4*(inst))+3))
277 #define VBUS_WAKEUP_PD(inst)                    (1 << ((4*(inst))+2))
278 #define   USBON_VAL_PD(inst)                    (1 << ((4*(inst))+1))
279 #define   USBON_VAL_PD_P2                       (1 << 9)
280 #define   USBON_VAL_PD_P1                       (1 << 5)
281 #define   USBON_VAL_PD_P0                       (1 << 1)
282 #define   USBOP_VAL_PD(inst)                    (1 << (4*(inst)))
283 #define   USBOP_VAL_PD_P2                       (1 << 8)
284 #define   USBOP_VAL_PD_P1                       (1 << 4)
285 #define   USBOP_VAL_PD_P0                       (1 << 0)
286 #define   PMC_USB_AO_PD_P2                      (0xf << 8)
287 #define   PMC_USB_AO_ID_PD_P0                   (1 << 3)
288 #define   PMC_USB_AO_VBUS_WAKEUP_PD_P0  (1 << 2)
289
290 #define PMC_TRIGGERS                    0x1ec
291
292 #define   UHSIC_CLR_WALK_PTR_P0         (1 << 3)
293 #define   UTMIP_CLR_WALK_PTR(inst)      (1 << (inst))
294 #define   UTMIP_CLR_WALK_PTR_P2         (1 << 2)
295 #define   UTMIP_CLR_WALK_PTR_P1         (1 << 1)
296 #define   UTMIP_CLR_WALK_PTR_P0         (1 << 0)
297 #define   UTMIP_CAP_CFG(inst)   (1 << ((inst)+4))
298 #define   UTMIP_CAP_CFG_P2              (1 << 6)
299 #define   UTMIP_CAP_CFG_P1              (1 << 5)
300 #define   UTMIP_CAP_CFG_P0              (1 << 4)
301 #define   UTMIP_CLR_WAKE_ALARM(inst)    (1 << ((inst)+12))
302 #define   UHSIC_CLR_WAKE_ALARM_P0       (1 << 15)
303 #define   UTMIP_CLR_WAKE_ALARM_P2       (1 << 14)
304
305 #define PMC_PAD_CFG             (0x1f4)
306
307 #define PMC_UTMIP_TERM_PAD_CFG  0x1f8
308 #define   PMC_TCTRL_VAL(x)      (((x) & 0x1f) << 5)
309 #define   PMC_RCTRL_VAL(x)      (((x) & 0x1f) << 0)
310
311 #define PMC_SLEEP_CFG                   0x1fc
312
313 #define   UHSIC_MASTER_ENABLE                   (1 << 24)
314 #define   UHSIC_WAKE_VAL(x)             (((x) & 0xf) << 28)
315 #define   WAKE_VAL_SD10                 0x2
316 #define   UTMIP_TCTRL_USE_PMC(inst) (1 << ((8*(inst))+3))
317 #define   UTMIP_TCTRL_USE_PMC_P2                (1 << 19)
318 #define   UTMIP_TCTRL_USE_PMC_P1                (1 << 11)
319 #define   UTMIP_TCTRL_USE_PMC_P0                (1 << 3)
320 #define   UTMIP_RCTRL_USE_PMC(inst) (1 << ((8*(inst))+2))
321 #define   UTMIP_RCTRL_USE_PMC_P2                (1 << 18)
322 #define   UTMIP_RCTRL_USE_PMC_P1                (1 << 10)
323 #define   UTMIP_RCTRL_USE_PMC_P0                (1 << 2)
324 #define   UTMIP_FSLS_USE_PMC(inst)      (1 << ((8*(inst))+1))
325 #define   UTMIP_FSLS_USE_PMC_P2         (1 << 17)
326 #define   UTMIP_FSLS_USE_PMC_P1         (1 << 9)
327 #define   UTMIP_FSLS_USE_PMC_P0         (1 << 1)
328 #define   UTMIP_MASTER_ENABLE(inst) (1 << (8*(inst)))
329 #define   UTMIP_MASTER_ENABLE_P2                (1 << 16)
330 #define   UTMIP_MASTER_ENABLE_P1                (1 << 8)
331 #define   UTMIP_MASTER_ENABLE_P0                (1 << 0)
332 #define UHSIC_MASTER_ENABLE_P0          (1 << 24)
333 #define UHSIC_WAKE_VAL_P0(x)            (((x) & 0xf) << 28)
334
335 #define PMC_SLEEPWALK_CFG               0x200
336
337 #define   UHSIC_WAKE_WALK_EN_P0 (1 << 30)
338 #define   UHSIC_LINEVAL_WALK_EN (1 << 31)
339 #define   UTMIP_LINEVAL_WALK_EN(inst) (1 << ((8*(inst))+7))
340 #define   UTMIP_LINEVAL_WALK_EN_P2      (1 << 23)
341 #define   UTMIP_LINEVAL_WALK_EN_P1      (1 << 15)
342 #define   UTMIP_LINEVAL_WALK_EN_P0      (1 << 7)
343 #define   UTMIP_WAKE_VAL(inst, x) (((x) & 0xf) << ((8*(inst))+4))
344 #define   UTMIP_WAKE_VAL_P2(x)          (((x) & 0xf) << 20)
345 #define   UTMIP_WAKE_VAL_P1(x)          (((x) & 0xf) << 12)
346 #define   UTMIP_WAKE_VAL_P0(x)          (((x) & 0xf) << 4)
347 #define   WAKE_VAL_NONE         0xc
348 #define   WAKE_VAL_ANY                  0xF
349 #define   WAKE_VAL_FSJ                  0x2
350 #define   WAKE_VAL_FSK                  0x1
351 #define   WAKE_VAL_SE0                  0x0
352
353 #define PMC_SLEEPWALK_REG(inst)         (0x204 + (4*(inst)))
354 #define   UTMIP_USBOP_RPD_A     (1 << 0)
355 #define   UTMIP_USBON_RPD_A     (1 << 1)
356 #define   UTMIP_AP_A                    (1 << 4)
357 #define   UTMIP_AN_A                    (1 << 5)
358 #define   UTMIP_HIGHZ_A         (1 << 6)
359 #define   UTMIP_USBOP_RPD_B     (1 << 8)
360 #define   UTMIP_USBON_RPD_B     (1 << 9)
361 #define   UTMIP_AP_B                    (1 << 12)
362 #define   UTMIP_AN_B                    (1 << 13)
363 #define   UTMIP_HIGHZ_B         (1 << 14)
364 #define   UTMIP_USBOP_RPD_C     (1 << 16)
365 #define   UTMIP_USBON_RPD_C     (1 << 17)
366 #define   UTMIP_AP_C            (1 << 20)
367 #define   UTMIP_AN_C            (1 << 21)
368 #define   UTMIP_HIGHZ_C         (1 << 22)
369 #define   UTMIP_USBOP_RPD_D     (1 << 24)
370 #define   UTMIP_USBON_RPD_D     (1 << 25)
371 #define   UTMIP_AP_D            (1 << 28)
372 #define   UTMIP_AN_D            (1 << 29)
373 #define   UTMIP_HIGHZ_D         (1 << 30)
374
375 #define PMC_SLEEPWALK_UHSIC             0x210
376
377 #define UHSIC_STROBE_RPD_A              (1 << 0)
378 #define UHSIC_DATA_RPD_A                (1 << 1)
379 #define UHSIC_STROBE_RPU_A              (1 << 2)
380 #define UHSIC_DATA_RPU_A                (1 << 3)
381 #define UHSIC_STROBE_RPD_B              (1 << 8)
382 #define UHSIC_DATA_RPD_B                (1 << 9)
383 #define UHSIC_STROBE_RPU_B              (1 << 10)
384 #define UHSIC_DATA_RPU_B                (1 << 11)
385 #define UHSIC_STROBE_RPD_C              (1 << 16)
386 #define UHSIC_DATA_RPD_C                (1 << 17)
387 #define UHSIC_STROBE_RPU_C              (1 << 18)
388 #define UHSIC_DATA_RPU_C                (1 << 19)
389 #define UHSIC_STROBE_RPD_D              (1 << 24)
390 #define UHSIC_DATA_RPD_D                (1 << 25)
391 #define UHSIC_STROBE_RPU_D              (1 << 26)
392 #define UHSIC_DATA_RPU_D                (1 << 27)
393
394 #define UTMIP_UHSIC_STATUS              0x214
395
396 #define UTMIP_USBOP_VAL(inst)           (1 << ((2*(inst)) + 8))
397 #define UTMIP_USBOP_VAL_P2              (1 << 12)
398 #define UTMIP_USBOP_VAL_P1              (1 << 10)
399 #define UTMIP_USBOP_VAL_P0              (1 << 8)
400 #define UTMIP_USBON_VAL(inst)           (1 << ((2*(inst)) + 9))
401 #define UTMIP_USBON_VAL_P2              (1 << 13)
402 #define UTMIP_USBON_VAL_P1              (1 << 11)
403 #define UTMIP_USBON_VAL_P0              (1 << 9)
404 #define UHSIC_WAKE_ALARM                (1 << 19)
405 #define UTMIP_WAKE_ALARM(inst)          (1 << ((inst) + 16))
406 #define UTMIP_WAKE_ALARM_P2             (1 << 18)
407 #define UTMIP_WAKE_ALARM_P1             (1 << 17)
408 #define UTMIP_WAKE_ALARM_P0             (1 << 16)
409 #define UHSIC_DATA_VAL_P0               (1 << 15)
410 #define UHSIC_STROBE_VAL_P0             (1 << 14)
411 #define UTMIP_WALK_PTR_VAL(inst)        (0x3 << ((inst)*2))
412 #define UHSIC_WALK_PTR_VAL              (0x3 << 6)
413 #define UTMIP_WALK_PTR(inst)            (1 << ((inst)*2))
414 #define UTMIP_WALK_PTR_P2               (1 << 4)
415 #define UTMIP_WALK_PTR_P1               (1 << 2)
416 #define UTMIP_WALK_PTR_P0               (1 << 0)
417
418 #define USB1_PREFETCH_ID                           6
419 #define USB2_PREFETCH_ID                           18
420 #define USB3_PREFETCH_ID                           17
421
422 #define PMC_UTMIP_UHSIC_FAKE            0x218
423
424 #define UHSIC_STROBE_VAL                (1 << 12)
425 #define UHSIC_DATA_VAL                  (1 << 13)
426 #define UHSIC_STROBE_ENB                (1 << 14)
427 #define UHSIC_DATA_ENB                  (1 << 15)
428 #define   USBON_VAL(inst)       (1 << ((4*(inst))+1))
429 #define   USBON_VAL_P2                  (1 << 9)
430 #define   USBON_VAL_P1                  (1 << 5)
431 #define   USBON_VAL_P0                  (1 << 1)
432 #define   USBOP_VAL(inst)       (1 << (4*(inst)))
433 #define   USBOP_VAL_P2                  (1 << 8)
434 #define   USBOP_VAL_P1                  (1 << 4)
435 #define   USBOP_VAL_P0                  (1 << 0)
436
437 #define PMC_UTMIP_BIAS_MASTER_CNTRL 0x30c
438 #define   BIAS_MASTER_PROG_VAL          (1 << 1)
439
440 #define PMC_UTMIP_MASTER_CONFIG 0x310
441
442 #define UTMIP_PWR(inst)         (1 << (inst))
443 #define UHSIC_PWR                       (1 << 3)
444
445 #define FUSE_USB_CALIB_0                0x1F0
446 #define   XCVR_SETUP(x) (((x) & 0x7F) << 0)
447 #define   XCVR_SETUP_LSB_MASK   0xF
448 #define   XCVR_SETUP_MSB_MASK   0x70
449 #define   XCVR_SETUP_LSB_MAX_VAL        0xF
450
451 #define APB_MISC_GP_OBSCTRL_0   0x818
452 #define APB_MISC_GP_OBSDATA_0   0x81c
453
454 /* ULPI GPIO */
455 #define ULPI_STP        TEGRA_GPIO_PY3
456 #define ULPI_DIR        TEGRA_GPIO_PY1
457 #define ULPI_D0         TEGRA_GPIO_PO1
458 #define ULPI_D1         TEGRA_GPIO_PO2
459
460 /* These values (in milli second) are taken from the battery charging spec */
461 #define TDP_SRC_ON_MS    100
462 #define TDPSRC_CON_MS    40
463
464 #ifdef DEBUG
465 #define DBG(stuff...)   pr_info("tegra3_usb_phy: " stuff)
466 #else
467 #define DBG(stuff...)   do {} while (0)
468 #endif
469
470 #if 0
471 #define PHY_DBG(stuff...)       pr_info("tegra3_usb_phy: " stuff)
472 #else
473 #define PHY_DBG(stuff...)       do {} while (0)
474 #endif
475
476
477 static u32 utmip_rctrl_val, utmip_tctrl_val;
478 static DEFINE_SPINLOCK(utmip_pad_lock);
479 static int utmip_pad_count;
480
481 static struct tegra_xtal_freq utmip_freq_table[] = {
482         {
483                 .freq = 12000000,
484                 .enable_delay = 0x02,
485                 .stable_count = 0x2F,
486                 .active_delay = 0x04,
487                 .xtal_freq_count = 0x76,
488                 .debounce = 0x7530,
489                 .pdtrk_count = 5,
490         },
491         {
492                 .freq = 13000000,
493                 .enable_delay = 0x02,
494                 .stable_count = 0x33,
495                 .active_delay = 0x05,
496                 .xtal_freq_count = 0x7F,
497                 .debounce = 0x7EF4,
498                 .pdtrk_count = 5,
499         },
500         {
501                 .freq = 19200000,
502                 .enable_delay = 0x03,
503                 .stable_count = 0x4B,
504                 .active_delay = 0x06,
505                 .xtal_freq_count = 0xBB,
506                 .debounce = 0xBB80,
507                 .pdtrk_count = 7,
508         },
509         {
510                 .freq = 26000000,
511                 .enable_delay = 0x04,
512                 .stable_count = 0x66,
513                 .active_delay = 0x09,
514                 .xtal_freq_count = 0xFE,
515                 .debounce = 0xFDE8,
516                 .pdtrk_count = 9,
517         },
518 };
519
520 static struct tegra_xtal_freq uhsic_freq_table[] = {
521         {
522                 .freq = 12000000,
523                 .enable_delay = 0x02,
524                 .stable_count = 0x2F,
525                 .active_delay = 0x0,
526                 .xtal_freq_count = 0x1CA,
527         },
528         {
529                 .freq = 13000000,
530                 .enable_delay = 0x02,
531                 .stable_count = 0x33,
532                 .active_delay = 0x0,
533                 .xtal_freq_count = 0x1F0,
534         },
535         {
536                 .freq = 19200000,
537                 .enable_delay = 0x03,
538                 .stable_count = 0x4B,
539                 .active_delay = 0x0,
540                 .xtal_freq_count = 0x2DD,
541         },
542         {
543                 .freq = 26000000,
544                 .enable_delay = 0x04,
545                 .stable_count = 0x66,
546                 .active_delay = 0x0,
547                 .xtal_freq_count = 0x3E0,
548         },
549 };
550
551 static void usb_phy_fence_read(struct tegra_usb_phy *phy)
552 {
553         /* Fence read for coherency of AHB master intiated writes */
554         if (phy->inst == 0)
555                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB1_PREFETCH_ID));
556         else if (phy->inst == 1)
557                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB2_PREFETCH_ID));
558         else if (phy->inst == 2)
559                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB3_PREFETCH_ID));
560
561         return;
562 }
563
564 static void utmip_setup_pmc_wake_detect(struct tegra_usb_phy *phy)
565 {
566         unsigned long val, pmc_pad_cfg_val;
567         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
568         unsigned  int inst = phy->inst;
569         void __iomem *base = phy->regs;
570         bool port_connected;
571         enum usb_phy_port_speed port_speed;
572
573         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
574
575         /* check for port connect status */
576         val = readl(base + USB_PORTSC);
577         port_connected = val & USB_PORTSC_CCS;
578
579         if (!port_connected)
580                 return;
581
582         port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
583                 HOSTPC1_DEVLC_PSPD_MASK;
584         /*Set PMC MASTER bits to do the following
585         * a. Take over the UTMI drivers
586         * b. set up such that it will take over resume
587         *        if remote wakeup is detected
588         * Prepare PMC to take over suspend-wake detect-drive resume until USB
589         * controller ready
590         */
591
592         /* disable master enable in PMC */
593         val = readl(pmc_base + PMC_SLEEP_CFG);
594         val &= ~UTMIP_MASTER_ENABLE(inst);
595         writel(val, pmc_base + PMC_SLEEP_CFG);
596
597         /* UTMIP_PWR_PX=1 for power savings mode */
598         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
599         val |= UTMIP_PWR(inst);
600         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
601
602         /* config debouncer */
603         val = readl(pmc_base + PMC_USB_DEBOUNCE);
604         val &= ~UTMIP_LINE_DEB_CNT(~0);
605         val |= UTMIP_LINE_DEB_CNT(4);
606         writel(val, pmc_base + PMC_USB_DEBOUNCE);
607
608         /* Make sure nothing is happening on the line with respect to PMC */
609         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
610         val &= ~USBOP_VAL(inst);
611         val &= ~USBON_VAL(inst);
612         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
613
614         /* Make sure wake value for line is none */
615         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
616         val &= ~UTMIP_LINEVAL_WALK_EN(inst);
617         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
618         val = readl(pmc_base + PMC_SLEEP_CFG);
619         val &= ~UTMIP_WAKE_VAL(inst, ~0);
620         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
621         writel(val, pmc_base + PMC_SLEEP_CFG);
622
623         /* turn off pad detectors */
624         val = readl(pmc_base + PMC_USB_AO);
625         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
626         writel(val, pmc_base + PMC_USB_AO);
627
628         /* Remove fake values and make synchronizers work a bit */
629         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
630         val &= ~USBOP_VAL(inst);
631         val &= ~USBON_VAL(inst);
632         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
633
634         /* Enable which type of event can trigger a walk,
635         in this case usb_line_wake */
636         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
637         val |= UTMIP_LINEVAL_WALK_EN(inst);
638         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
639
640         /* Enable which type of event can trigger a walk,
641         * in this case usb_line_wake */
642         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
643         val |= UTMIP_LINEVAL_WALK_EN(inst);
644         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
645
646         /* Clear the walk pointers and wake alarm */
647         val = readl(pmc_base + PMC_TRIGGERS);
648         val |= UTMIP_CLR_WAKE_ALARM(inst) | UTMIP_CLR_WALK_PTR(inst);
649         writel(val, pmc_base + PMC_TRIGGERS);
650
651
652         /* Capture FS/LS pad configurations */
653         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
654         val = readl(pmc_base + PMC_TRIGGERS);
655         val |= UTMIP_CAP_CFG(inst);
656         writel(val, pmc_base + PMC_TRIGGERS);
657         udelay(1);
658         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
659
660         /* BIAS MASTER_ENABLE=0 */
661         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
662         val &= ~BIAS_MASTER_PROG_VAL;
663         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
664
665         /* program walk sequence, maintain a J, followed by a driven K
666         * to signal a resume once an wake event is detected */
667         val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
668         val &= ~UTMIP_AP_A;
669         val |= UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_AN_A |UTMIP_HIGHZ_A |
670                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_AP_B | UTMIP_AN_B |
671                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_AP_C | UTMIP_AN_C |
672                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_AP_D | UTMIP_AN_D;
673         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
674
675         if (port_speed == USB_PHY_PORT_SPEED_LOW) {
676                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
677                 val &= ~(UTMIP_AN_B | UTMIP_HIGHZ_B | UTMIP_AN_C |
678                         UTMIP_HIGHZ_C | UTMIP_AN_D | UTMIP_HIGHZ_D);
679                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
680         } else {
681                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
682                 val &= ~(UTMIP_AP_B | UTMIP_HIGHZ_B | UTMIP_AP_C |
683                         UTMIP_HIGHZ_C | UTMIP_AP_D | UTMIP_HIGHZ_D);
684                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
685         }
686
687         /* turn on pad detectors */
688         val = readl(pmc_base + PMC_USB_AO);
689         val &= ~(USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
690         writel(val, pmc_base + PMC_USB_AO);
691
692         /* Add small delay before usb detectors provide stable line values */
693         mdelay(1);
694
695         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
696         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
697         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
698         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
699
700         phy->remote_wakeup = false;
701
702         /* Turn over pad configuration to PMC  for line wake events*/
703         val = readl(pmc_base + PMC_SLEEP_CFG);
704         val &= ~UTMIP_WAKE_VAL(inst, ~0);
705         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_ANY);
706         val |= UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst);
707         val |= UTMIP_MASTER_ENABLE(inst) | UTMIP_FSLS_USE_PMC(inst);
708         writel(val, pmc_base + PMC_SLEEP_CFG);
709
710         val = readl(base + UTMIP_PMC_WAKEUP0);
711         val |= EVENT_INT_ENB;
712         writel(val, base + UTMIP_PMC_WAKEUP0);
713         PHY_DBG("%s ENABLE_PMC inst = %d\n", __func__, inst);
714 }
715
716 static void utmip_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy)
717 {
718         unsigned long val;
719         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
720         unsigned  int inst = phy->inst;
721         void __iomem *base = phy->regs;
722
723         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
724
725         val = readl(pmc_base + PMC_SLEEP_CFG);
726         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
727         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
728         writel(val, pmc_base + PMC_SLEEP_CFG);
729
730         val = readl(pmc_base + PMC_TRIGGERS);
731         val |= UTMIP_CLR_WAKE_ALARM(inst) | UTMIP_CLR_WALK_PTR(inst);
732         writel(val, pmc_base + PMC_TRIGGERS);
733
734         val = readl(base + UTMIP_PMC_WAKEUP0);
735         val &= ~EVENT_INT_ENB;
736         writel(val, base + UTMIP_PMC_WAKEUP0);
737
738         /* Disable PMC master mode by clearing MASTER_EN */
739         val = readl(pmc_base + PMC_SLEEP_CFG);
740         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
741                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
742         writel(val, pmc_base + PMC_SLEEP_CFG);
743
744         val = readl(pmc_base + PMC_TRIGGERS);
745         val &= ~UTMIP_CAP_CFG(inst);
746         writel(val, pmc_base + PMC_TRIGGERS);
747
748         /* turn off pad detectors */
749         val = readl(pmc_base + PMC_USB_AO);
750         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
751         writel(val, pmc_base + PMC_USB_AO);
752
753         phy->remote_wakeup = false;
754         PHY_DBG("%s DISABLE_PMC inst = %d\n", __func__, inst);
755 }
756
757 bool utmi_phy_remotewake_detected(struct tegra_usb_phy *phy)
758 {
759         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
760         void __iomem *base = phy->regs;
761         unsigned  int inst = phy->inst;
762         u32 val;
763
764         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
765         val = readl(base + UTMIP_PMC_WAKEUP0);
766         if (val & EVENT_INT_ENB) {
767                 val = readl(pmc_base + UTMIP_UHSIC_STATUS);
768                 if (UTMIP_WAKE_ALARM(inst) & val) {
769                         val = readl(pmc_base + PMC_SLEEP_CFG);
770                         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
771                         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
772                         writel(val, pmc_base + PMC_SLEEP_CFG);
773
774                         val = readl(pmc_base + PMC_TRIGGERS);
775                         val |= UTMIP_CLR_WAKE_ALARM(inst) |
776                                 UTMIP_CLR_WALK_PTR(inst);
777                         writel(val, pmc_base + PMC_TRIGGERS);
778
779                         val = readl(base + UTMIP_PMC_WAKEUP0);
780                         val &= ~EVENT_INT_ENB;
781                         writel(val, base + UTMIP_PMC_WAKEUP0);
782                         phy->remote_wakeup = true;
783                         return true;
784                 }
785         }
786         return false;
787 }
788
789 static void utmi_phy_enable_trking_data(struct tegra_usb_phy *phy)
790 {
791         void __iomem *base = IO_ADDRESS(TEGRA_USB_BASE);
792         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
793         static bool init_done = false;
794         u32 val;
795
796         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
797
798         /* Should be done only once after system boot */
799         if (init_done)
800                 return;
801
802         clk_enable(phy->utmi_pad_clk);
803         /* Bias pad MASTER_ENABLE=1 */
804         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
805         val |= BIAS_MASTER_PROG_VAL;
806         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
807
808         /* Setting the tracking length time */
809         val = readl(base + UTMIP_BIAS_CFG1);
810         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
811         val |= UTMIP_BIAS_PDTRK_COUNT(5);
812         writel(val, base + UTMIP_BIAS_CFG1);
813
814         /* Bias PDTRK is Shared and MUST be done from USB1 ONLY, PD_TRK=0 */
815         val = readl(base + UTMIP_BIAS_CFG1);
816         val &= ~UTMIP_BIAS_PDTRK_POWERDOWN;
817         writel(val, base + UTMIP_BIAS_CFG1);
818
819         val = readl(base + UTMIP_BIAS_CFG1);
820         val |= UTMIP_BIAS_PDTRK_POWERUP;
821         writel(val, base + UTMIP_BIAS_CFG1);
822
823         /* Wait for 25usec */
824         udelay(25);
825
826         /* Bias pad MASTER_ENABLE=0 */
827         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
828         val &= ~BIAS_MASTER_PROG_VAL;
829         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
830
831         /* Wait for 1usec */
832         udelay(1);
833
834         /* Bias pad MASTER_ENABLE=1 */
835         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
836         val |= BIAS_MASTER_PROG_VAL;
837         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
838
839         /* Read RCTRL and TCTRL from UTMIP space */
840         val = readl(base + UTMIP_BIAS_STS0);
841         utmip_rctrl_val = ffz(UTMIP_RCTRL_VAL(val));
842         utmip_tctrl_val = ffz(UTMIP_TCTRL_VAL(val));
843
844         /* PD_TRK=1 */
845         val = readl(base + UTMIP_BIAS_CFG1);
846         val |= UTMIP_BIAS_PDTRK_POWERDOWN;
847         writel(val, base + UTMIP_BIAS_CFG1);
848
849         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
850         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
851         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
852         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
853         clk_disable(phy->utmi_pad_clk);
854         init_done = true;
855 }
856
857 static void utmip_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy)
858 {
859         unsigned long val;
860         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
861         unsigned  int inst = phy->inst;
862
863         /* power down UTMIP interfaces */
864         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
865         val |= UTMIP_PWR(inst);
866         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
867
868         /* setup sleep walk usb controller */
869         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
870                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
871                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
872                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
873         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
874
875         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
876         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
877         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
878         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
879
880         /* Turn over pad configuration to PMC */
881         val = readl(pmc_base + PMC_SLEEP_CFG);
882         val &= ~UTMIP_WAKE_VAL(inst, ~0);
883         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE) |
884                 UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
885                 UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst);
886         writel(val, pmc_base + PMC_SLEEP_CFG);
887         PHY_DBG("%s ENABLE_PMC inst = %d\n", __func__, inst);
888 }
889
890 static void utmip_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
891 {
892         unsigned long val;
893         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
894         unsigned  int inst = phy->inst;
895
896         /* Disable PMC master mode by clearing MASTER_EN */
897         val = readl(pmc_base + PMC_SLEEP_CFG);
898         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
899                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
900         writel(val, pmc_base + PMC_SLEEP_CFG);
901         mdelay(1);
902         PHY_DBG("%s DISABLE_PMC inst = %d\n", __func__, inst);
903 }
904
905
906 #ifdef KERNEL_WARNING
907 static void usb_phy_power_down_pmc(void)
908 {
909         unsigned long val;
910         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
911
912         /* power down all 3 UTMIP interfaces */
913         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
914         val |= UTMIP_PWR(0) | UTMIP_PWR(1) | UTMIP_PWR(2);
915         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
916
917         /* turn on pad detectors */
918         writel(PMC_POWER_DOWN_MASK, pmc_base + PMC_USB_AO);
919
920         /* setup sleep walk fl all 3 usb controllers */
921         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
922                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
923                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
924                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
925         writel(val, pmc_base + PMC_SLEEPWALK_REG(0));
926         writel(val, pmc_base + PMC_SLEEPWALK_REG(1));
927         writel(val, pmc_base + PMC_SLEEPWALK_REG(2));
928
929         /* enable pull downs on HSIC PMC */
930         val = UHSIC_STROBE_RPD_A | UHSIC_DATA_RPD_A | UHSIC_STROBE_RPD_B |
931                 UHSIC_DATA_RPD_B | UHSIC_STROBE_RPD_C | UHSIC_DATA_RPD_C |
932                 UHSIC_STROBE_RPD_D | UHSIC_DATA_RPD_D;
933         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
934
935         /* Turn over pad configuration to PMC */
936         val = readl(pmc_base + PMC_SLEEP_CFG);
937         val &= ~UTMIP_WAKE_VAL(0, ~0);
938         val &= ~UTMIP_WAKE_VAL(1, ~0);
939         val &= ~UTMIP_WAKE_VAL(2, ~0);
940         val &= ~UHSIC_WAKE_VAL_P0(~0);
941         val |= UTMIP_WAKE_VAL(0, WAKE_VAL_NONE) | UHSIC_WAKE_VAL_P0(WAKE_VAL_NONE) |
942         UTMIP_WAKE_VAL(1, WAKE_VAL_NONE) | UTMIP_WAKE_VAL(2, WAKE_VAL_NONE) |
943         UTMIP_RCTRL_USE_PMC(0) | UTMIP_RCTRL_USE_PMC(1) | UTMIP_RCTRL_USE_PMC(2) |
944         UTMIP_TCTRL_USE_PMC(0) | UTMIP_TCTRL_USE_PMC(1) | UTMIP_TCTRL_USE_PMC(2) |
945         UTMIP_FSLS_USE_PMC(0) | UTMIP_FSLS_USE_PMC(1) | UTMIP_FSLS_USE_PMC(2) |
946         UTMIP_MASTER_ENABLE(0) | UTMIP_MASTER_ENABLE(1) | UTMIP_MASTER_ENABLE(2) |
947         UHSIC_MASTER_ENABLE_P0;
948         writel(val, pmc_base + PMC_SLEEP_CFG);
949 }
950 #endif
951
952 static int usb_phy_bringup_host_controller(struct tegra_usb_phy *phy)
953 {
954         unsigned long val;
955         void __iomem *base = phy->regs;
956
957         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
958         PHY_DBG("[%d] USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n", __LINE__,
959                 readl(base + USB_USBSTS), readl(base + USB_PORTSC),
960                                                         phy->port_speed);
961
962         /* Device is plugged in when system is in LP0 */
963         /* Bring up the controller from LP0*/
964         val = readl(base + USB_USBCMD);
965         val |= USB_CMD_RESET;
966         writel(val, base + USB_USBCMD);
967
968         if (usb_phy_reg_status_wait(base + USB_USBCMD,
969                 USB_CMD_RESET, 0, 2500) < 0) {
970                 pr_err("%s: timeout waiting for reset\n", __func__);
971         }
972
973         val = readl(base + USB_USBMODE);
974         val &= ~USB_USBMODE_MASK;
975         val |= USB_USBMODE_HOST;
976         writel(val, base + USB_USBMODE);
977         val = readl(base + HOSTPC1_DEVLC);
978         val &= ~HOSTPC1_DEVLC_PTS(~0);
979
980         if (phy->pdata->phy_intf == TEGRA_USB_PHY_INTF_HSIC)
981                 val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
982         else
983                 val |= HOSTPC1_DEVLC_STS;
984         writel(val, base + HOSTPC1_DEVLC);
985
986         /* Enable Port Power */
987         val = readl(base + USB_PORTSC);
988         val |= USB_PORTSC_PP;
989         writel(val, base + USB_PORTSC);
990         udelay(10);
991
992         /* Check if the phy resume from LP0. When the phy resume from LP0
993          * USB register will be reset.to zero */
994         if (!readl(base + USB_ASYNCLISTADDR)) {
995                 /* Program the field PTC based on the saved speed mode */
996                 val = readl(base + USB_PORTSC);
997                 val &= ~USB_PORTSC_PTC(~0);
998                 if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH)
999                         val |= USB_PORTSC_PTC(5);
1000                 else if (phy->port_speed == USB_PHY_PORT_SPEED_FULL)
1001                         val |= USB_PORTSC_PTC(6);
1002                 else if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
1003                         val |= USB_PORTSC_PTC(7);
1004                 writel(val, base + USB_PORTSC);
1005                 udelay(10);
1006
1007                 /* Disable test mode by setting PTC field to NORMAL_OP */
1008                 val = readl(base + USB_PORTSC);
1009                 val &= ~USB_PORTSC_PTC(~0);
1010                 writel(val, base + USB_PORTSC);
1011                 udelay(10);
1012         }
1013
1014         /* Poll until CCS is enabled */
1015         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
1016                                                  USB_PORTSC_CCS, 2000)) {
1017                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
1018         }
1019
1020         /* Poll until PE is enabled */
1021         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_PE,
1022                                                  USB_PORTSC_PE, 2000)) {
1023                 pr_err("%s: timeout waiting for USB_PORTSC_PE\n", __func__);
1024         }
1025
1026         /* Clear the PCI status, to avoid an interrupt taken upon resume */
1027         val = readl(base + USB_USBSTS);
1028         val |= USB_USBSTS_PCI;
1029         writel(val, base + USB_USBSTS);
1030
1031         if (!phy->remote_wakeup) {
1032                 /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
1033                 val = readl(base + USB_PORTSC);
1034                 if ((val & USB_PORTSC_PP) && (val & USB_PORTSC_PE)) {
1035                         val |= USB_PORTSC_SUSP;
1036                         writel(val, base + USB_PORTSC);
1037                         /* Need a 4ms delay before the controller goes to suspend */
1038                         mdelay(4);
1039
1040                         /* Wait until port suspend completes */
1041                         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_SUSP,
1042                                                          USB_PORTSC_SUSP, 1000)) {
1043                                 pr_err("%s: timeout waiting for PORT_SUSPEND\n",
1044                                                                         __func__);
1045                         }
1046                 }
1047         }
1048         PHY_DBG("[%d] USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n", __LINE__,
1049                 readl(base + USB_USBSTS), readl(base + USB_PORTSC),
1050                                                         phy->port_speed);
1051
1052         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1053                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1054         return 0;
1055 }
1056
1057 static void usb_phy_wait_for_sof(struct tegra_usb_phy *phy)
1058 {
1059         unsigned long val;
1060         void __iomem *base = phy->regs;
1061
1062         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1063
1064         val = readl(base + USB_USBSTS);
1065         writel(val, base + USB_USBSTS);
1066         udelay(20);
1067         /* wait for two SOFs */
1068         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1069                 USB_USBSTS_SRI, 2500))
1070                 pr_err("%s: timeout waiting for SOF\n", __func__);
1071
1072         val = readl(base + USB_USBSTS);
1073         writel(val, base + USB_USBSTS);
1074         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI, 0, 2500))
1075                 pr_err("%s: timeout waiting for SOF\n", __func__);
1076
1077         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1078                         USB_USBSTS_SRI, 2500))
1079                 pr_err("%s: timeout waiting for SOF\n", __func__);
1080
1081         udelay(20);
1082 }
1083
1084 static unsigned int utmi_phy_xcvr_setup_value(struct tegra_usb_phy *phy)
1085 {
1086         struct tegra_utmi_config *cfg = &phy->pdata->u_cfg.utmi;
1087         signed long val;
1088
1089         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1090
1091         if (cfg->xcvr_use_fuses) {
1092                 val = XCVR_SETUP(tegra_fuse_readl(FUSE_USB_CALIB_0));
1093                 if (cfg->xcvr_use_lsb) {
1094                         val = min((unsigned int) ((val & XCVR_SETUP_LSB_MASK)
1095                                 + cfg->xcvr_setup_offset),
1096                                 (unsigned int) XCVR_SETUP_LSB_MAX_VAL);
1097                         val |= (cfg->xcvr_setup & XCVR_SETUP_MSB_MASK);
1098                 } else {
1099                         if (cfg->xcvr_setup_offset <= UTMIP_XCVR_MAX_OFFSET)
1100                                 val = val + cfg->xcvr_setup_offset;
1101
1102                         if (val > UTMIP_XCVR_SETUP_MAX_VALUE) {
1103                                 val = UTMIP_XCVR_SETUP_MAX_VALUE;
1104                                 pr_info("%s: reset XCVR_SETUP to max value\n",
1105                                                 __func__);
1106                         } else if (val < UTMIP_XCVR_SETUP_MIN_VALUE) {
1107                                 val = UTMIP_XCVR_SETUP_MIN_VALUE;
1108                                 pr_info("%s: reset XCVR_SETUP to min value\n",
1109                                                 __func__);
1110                         }
1111                 }
1112         } else {
1113                 val = cfg->xcvr_setup;
1114         }
1115
1116         return (unsigned int) val;
1117 }
1118
1119 static int utmi_phy_open(struct tegra_usb_phy *phy)
1120 {
1121         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1122         unsigned long parent_rate, val;
1123         int i;
1124
1125         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1126
1127         phy->utmi_pad_clk = clk_get_sys("utmip-pad", NULL);
1128         if (IS_ERR(phy->utmi_pad_clk)) {
1129                 pr_err("%s: can't get utmip pad clock\n", __func__);
1130                 return PTR_ERR(phy->utmi_pad_clk);
1131         }
1132
1133         phy->utmi_xcvr_setup = utmi_phy_xcvr_setup_value(phy);
1134
1135         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
1136         for (i = 0; i < ARRAY_SIZE(utmip_freq_table); i++) {
1137                 if (utmip_freq_table[i].freq == parent_rate) {
1138                         phy->freq = &utmip_freq_table[i];
1139                         break;
1140                 }
1141         }
1142         if (!phy->freq) {
1143                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
1144                 return -EINVAL;
1145         }
1146
1147         /* Power-up the VBUS detector for UTMIP PHY */
1148         val = readl(pmc_base + PMC_USB_AO);
1149         val &= ~(PMC_USB_AO_VBUS_WAKEUP_PD_P0 | PMC_USB_AO_ID_PD_P0);
1150         writel((val | PMC_USB_AO_PD_P2), (pmc_base + PMC_USB_AO));
1151
1152         utmip_powerup_pmc_wake_detect(phy);
1153
1154         return 0;
1155 }
1156
1157 static void utmi_phy_close(struct tegra_usb_phy *phy)
1158 {
1159         unsigned long val;
1160         void __iomem *base = phy->regs;
1161
1162         DBG("%s inst:[%d]\n", __func__, phy->inst);
1163
1164         /* Disable PHY clock valid interrupts while going into suspend*/
1165         if (phy->pdata->u_data.host.hot_plug) {
1166                 val = readl(base + USB_SUSP_CTRL);
1167                 val &= ~USB_PHY_CLK_VALID_INT_ENB;
1168                 writel(val, base + USB_SUSP_CTRL);
1169         }
1170
1171         clk_put(phy->utmi_pad_clk);
1172 }
1173
1174 static int utmi_phy_pad_power_on(struct tegra_usb_phy *phy)
1175 {
1176         unsigned long val, flags;
1177         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1178
1179         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1180
1181         clk_enable(phy->utmi_pad_clk);
1182
1183         spin_lock_irqsave(&utmip_pad_lock, flags);
1184         utmip_pad_count++;
1185
1186         val = readl(pad_base + UTMIP_BIAS_CFG0);
1187         val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
1188         val |= UTMIP_HSSQUELCH_LEVEL(0x2) | UTMIP_HSDISCON_LEVEL(0x1) |
1189                 UTMIP_HSDISCON_LEVEL_MSB;
1190         writel(val, pad_base + UTMIP_BIAS_CFG0);
1191
1192         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1193
1194         clk_disable(phy->utmi_pad_clk);
1195
1196         return 0;
1197 }
1198
1199 static int utmi_phy_pad_power_off(struct tegra_usb_phy *phy)
1200 {
1201         unsigned long val, flags;
1202         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1203
1204         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1205
1206         clk_enable(phy->utmi_pad_clk);
1207         spin_lock_irqsave(&utmip_pad_lock, flags);
1208
1209         if (!utmip_pad_count) {
1210                 pr_err("%s: utmip pad already powered off\n", __func__);
1211                 goto out;
1212         }
1213         if (--utmip_pad_count == 0) {
1214                 val = readl(pad_base + UTMIP_BIAS_CFG0);
1215                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
1216                 val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) | UTMIP_HSDISCON_LEVEL(~0) |
1217                         UTMIP_HSDISCON_LEVEL_MSB);
1218                 writel(val, pad_base + UTMIP_BIAS_CFG0);
1219         }
1220 out:
1221         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1222         clk_disable(phy->utmi_pad_clk);
1223
1224         return 0;
1225 }
1226
1227 static int utmi_phy_irq(struct tegra_usb_phy *phy)
1228 {
1229         void __iomem *base = phy->regs;
1230         unsigned long val = 0;
1231
1232         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1233         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1234                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1235         DBG("USB_USBMODE[0x%x] USB_USBCMD[0x%x]\n",
1236                         readl(base + USB_USBMODE), readl(base + USB_USBCMD));
1237
1238         usb_phy_fence_read(phy);
1239         /* check if there is any remote wake event */
1240         if (utmi_phy_remotewake_detected(phy))
1241                 pr_info("%s: utmip remote wake detected\n", __func__);
1242
1243         if (phy->pdata->u_data.host.hot_plug) {
1244                 val = readl(base + USB_SUSP_CTRL);
1245                 if ((val  & USB_PHY_CLK_VALID_INT_STS)) {
1246                         val &= ~USB_PHY_CLK_VALID_INT_ENB |
1247                                         USB_PHY_CLK_VALID_INT_STS;
1248                         writel(val , (base + USB_SUSP_CTRL));
1249                         pr_info("%s: usb device plugged-in\n", __func__);
1250                         val = readl(base + USB_USBSTS);
1251                         if (!(val  & USB_USBSTS_PCI))
1252                                 return IRQ_NONE;
1253                         val = readl(base + USB_PORTSC);
1254                         val &= ~(USB_PORTSC_WKCN | USB_PORTSC_RWC_BITS);
1255                         writel(val , (base + USB_PORTSC));
1256                 }
1257         }
1258
1259         return IRQ_HANDLED;
1260 }
1261
1262 static void utmi_phy_enable_obs_bus(struct tegra_usb_phy *phy)
1263 {
1264         unsigned long val;
1265         void __iomem *base = phy->regs;
1266
1267         /* (2LS WAR)is not required for LS and FS devices and is only for HS */
1268         if ((phy->port_speed == USB_PHY_PORT_SPEED_LOW) ||
1269                 (phy->port_speed == USB_PHY_PORT_SPEED_FULL)) {
1270                 /* do not enable the OBS bus */
1271                 val = readl(base + UTMIP_MISC_CFG0);
1272                 val &= ~(UTMIP_DPDM_OBSERVE_SEL(~0));
1273                 writel(val, base + UTMIP_MISC_CFG0);
1274                 DBG("%s(%d) Disable OBS bus\n", __func__, __LINE__);
1275                 return;
1276         }
1277         /* Force DP/DM pulldown active for Host mode */
1278         val = readl(base + UTMIP_MISC_CFG0);
1279         val |= FORCE_PULLDN_DM | FORCE_PULLDN_DP |
1280                         COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS;
1281         writel(val, base + UTMIP_MISC_CFG0);
1282         val = readl(base + UTMIP_MISC_CFG0);
1283         val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1284         if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
1285                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
1286         else
1287                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
1288         writel(val, base + UTMIP_MISC_CFG0);
1289         udelay(1);
1290
1291         val = readl(base + UTMIP_MISC_CFG0);
1292         val |= UTMIP_DPDM_OBSERVE;
1293         writel(val, base + UTMIP_MISC_CFG0);
1294         udelay(10);
1295         DBG("%s(%d) Enable OBS bus\n", __func__, __LINE__);
1296         PHY_DBG("ENABLE_OBS_BUS\n");
1297 }
1298
1299 static int utmi_phy_disable_obs_bus(struct tegra_usb_phy *phy)
1300 {
1301         unsigned long val;
1302         void __iomem *base = phy->regs;
1303         unsigned long flags;
1304
1305         /* check if OBS bus is already enabled */
1306         val = readl(base + UTMIP_MISC_CFG0);
1307         if (val & UTMIP_DPDM_OBSERVE) {
1308                 PHY_DBG("DISABLE_OBS_BUS\n");
1309
1310                 /* disable ALL interrupts on current CPU */
1311                 local_irq_save(flags);
1312
1313                 /* Change the UTMIP OBS bus to drive SE0 */
1314                 val = readl(base + UTMIP_MISC_CFG0);
1315                 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1316                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_SE0;
1317                 writel(val, base + UTMIP_MISC_CFG0);
1318
1319                 /* Wait for 3us(2 LS bit times) */
1320                 udelay(3);
1321
1322                 /* Release UTMIP OBS bus */
1323                 val = readl(base + UTMIP_MISC_CFG0);
1324                 val &= ~UTMIP_DPDM_OBSERVE;
1325                 writel(val, base + UTMIP_MISC_CFG0);
1326
1327                 /* Release DP/DM pulldown for Host mode */
1328                 val = readl(base + UTMIP_MISC_CFG0);
1329                 val &= ~(FORCE_PULLDN_DM | FORCE_PULLDN_DP |
1330                                 COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS);
1331                 writel(val, base + UTMIP_MISC_CFG0);
1332
1333                 val = readl(base + USB_USBCMD);
1334                 val |= USB_USBCMD_RS;
1335                 writel(val, base + USB_USBCMD);
1336
1337                 /* restore ALL interrupts on current CPU */
1338                 local_irq_restore(flags);
1339
1340                 if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
1341                                                          USB_USBCMD_RS, 2000)) {
1342                         pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
1343                         return -ETIMEDOUT;
1344                 }
1345         }
1346         return 0;
1347 }
1348
1349 static int utmi_phy_post_resume(struct tegra_usb_phy *phy)
1350 {
1351         unsigned long val;
1352         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1353         unsigned  int inst = phy->inst;
1354
1355         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1356         val = readl(pmc_base + PMC_SLEEP_CFG);
1357         /* if PMC is not disabled by now then disable it */
1358         if (val & UTMIP_MASTER_ENABLE(inst)) {
1359                 utmip_phy_disable_pmc_bus_ctrl(phy);
1360         }
1361
1362         utmi_phy_disable_obs_bus(phy);
1363
1364         return 0;
1365 }
1366
1367 static int utmi_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1368 {
1369         unsigned long val;
1370         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1371         void __iomem *base = phy->regs;
1372         unsigned  int inst = phy->inst;
1373
1374         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1375         phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
1376                         HOSTPC1_DEVLC_PSPD_MASK;
1377
1378         if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH) {
1379                 /* Disable interrupts */
1380                 writel(0, base + USB_USBINTR);
1381                 /* Clear the run bit to stop SOFs - 2LS WAR */
1382                 val = readl(base + USB_USBCMD);
1383                 val &= ~USB_USBCMD_RS;
1384                 writel(val, base + USB_USBCMD);
1385                 if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
1386                                                          USB_USBSTS_HCH, 2000)) {
1387                         pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
1388                 }
1389         }
1390
1391         val = readl(pmc_base + PMC_SLEEP_CFG);
1392         if (val & UTMIP_MASTER_ENABLE(inst)) {
1393                 if (!remote_wakeup)
1394                         utmip_phy_disable_pmc_bus_ctrl(phy);
1395         } else {
1396                 utmi_phy_enable_obs_bus(phy);
1397         }
1398
1399         return 0;
1400 }
1401
1402 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
1403 {
1404         unsigned long val;
1405         void __iomem *base = phy->regs;
1406
1407         PHY_DBG("%s(%d) inst:[%d] BEGIN\n", __func__, __LINE__, phy->inst);
1408         if (!phy->phy_clk_on) {
1409                 PHY_DBG("%s(%d) inst:[%d] phy clk is already off\n",
1410                                         __func__, __LINE__, phy->inst);
1411                 return 0;
1412         }
1413
1414         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1415                 utmip_powerdown_pmc_wake_detect(phy);
1416
1417                 val = readl(base + USB_SUSP_CTRL);
1418                 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
1419                 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
1420                 writel(val, base + USB_SUSP_CTRL);
1421
1422                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1423                 val |= UTMIP_PD_CHRG;
1424                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1425         } else {
1426                 phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
1427                                 HOSTPC1_DEVLC_PSPD_MASK;
1428
1429                 /* Disable interrupts */
1430                 writel(0, base + USB_USBINTR);
1431
1432                 /* Clear the run bit to stop SOFs - 2LS WAR */
1433                 val = readl(base + USB_USBCMD);
1434                 val &= ~USB_USBCMD_RS;
1435                 writel(val, base + USB_USBCMD);
1436
1437                 if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
1438                                                          USB_USBSTS_HCH, 2000)) {
1439                         pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
1440                 }
1441                 utmip_setup_pmc_wake_detect(phy);
1442         }
1443
1444         if (!phy->pdata->u_data.host.hot_plug) {
1445                 val = readl(base + UTMIP_XCVR_CFG0);
1446                 val |= (UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
1447                          UTMIP_FORCE_PDZI_POWERDOWN);
1448                 writel(val, base + UTMIP_XCVR_CFG0);
1449         }
1450
1451         val = readl(base + UTMIP_XCVR_CFG1);
1452         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1453                    UTMIP_FORCE_PDDR_POWERDOWN;
1454         writel(val, base + UTMIP_XCVR_CFG1);
1455
1456         val = readl(base + UTMIP_BIAS_CFG1);
1457         val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
1458         writel(val, base + UTMIP_BIAS_CFG1);
1459
1460         utmi_phy_pad_power_off(phy);
1461
1462         if (phy->pdata->u_data.host.hot_plug) {
1463                 bool enable_hotplug = true;
1464                 /* if it is OTG port then make sure to enable hot-plug feature
1465                    only if host adaptor is connected, i.e id is low */
1466                 if (phy->pdata->port_otg) {
1467                         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1468                         enable_hotplug = (val & USB_ID_STATUS) ? false : true;
1469                 }
1470                 if (enable_hotplug) {
1471                         val = readl(base + USB_PORTSC);
1472                         val |= USB_PORTSC_WKCN;
1473                         writel(val, base + USB_PORTSC);
1474
1475                         val = readl(base + USB_SUSP_CTRL);
1476                         val |= USB_PHY_CLK_VALID_INT_ENB;
1477                         writel(val, base + USB_SUSP_CTRL);
1478                 } else {
1479                         /* Disable PHY clock valid interrupts while going into suspend*/
1480                         val = readl(base + USB_SUSP_CTRL);
1481                         val &= ~USB_PHY_CLK_VALID_INT_ENB;
1482                         writel(val, base + USB_SUSP_CTRL);
1483                 }
1484         }
1485
1486         val = readl(base + HOSTPC1_DEVLC);
1487         val |= HOSTPC1_DEVLC_PHCD;
1488         writel(val, base + HOSTPC1_DEVLC);
1489
1490         if (!phy->pdata->u_data.host.hot_plug) {
1491                 val = readl(base + USB_SUSP_CTRL);
1492                 val |= UTMIP_RESET;
1493                 writel(val, base + USB_SUSP_CTRL);
1494         }
1495
1496         phy->phy_clk_on = false;
1497         phy->hw_accessible = false;
1498
1499         PHY_DBG("%s(%d) inst:[%d] END\n", __func__, __LINE__, phy->inst);
1500
1501         return 0;
1502 }
1503
1504
1505 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
1506 {
1507         unsigned long val;
1508         void __iomem *base = phy->regs;
1509         struct tegra_utmi_config *config = &phy->pdata->u_cfg.utmi;
1510
1511         PHY_DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1512         if (phy->phy_clk_on) {
1513                 PHY_DBG("%s(%d) inst:[%d] phy clk is already On\n",
1514                                         __func__, __LINE__, phy->inst);
1515                 return 0;
1516         }
1517         val = readl(base + USB_SUSP_CTRL);
1518         val |= UTMIP_RESET;
1519         writel(val, base + USB_SUSP_CTRL);
1520
1521         val = readl(base + UTMIP_TX_CFG0);
1522         val |= UTMIP_FS_PREABMLE_J;
1523         writel(val, base + UTMIP_TX_CFG0);
1524
1525         val = readl(base + UTMIP_HSRX_CFG0);
1526         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
1527         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
1528         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
1529         writel(val, base + UTMIP_HSRX_CFG0);
1530
1531         val = readl(base + UTMIP_HSRX_CFG1);
1532         val &= ~UTMIP_HS_SYNC_START_DLY(~0);
1533         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
1534         writel(val, base + UTMIP_HSRX_CFG1);
1535
1536         val = readl(base + UTMIP_DEBOUNCE_CFG0);
1537         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
1538         val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
1539         writel(val, base + UTMIP_DEBOUNCE_CFG0);
1540
1541         val = readl(base + UTMIP_MISC_CFG0);
1542         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
1543         writel(val, base + UTMIP_MISC_CFG0);
1544
1545         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1546                 val = readl(base + USB_SUSP_CTRL);
1547                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
1548                 writel(val, base + USB_SUSP_CTRL);
1549
1550                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1551                 val &= ~UTMIP_PD_CHRG;
1552                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1553         } else {
1554                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1555                 val |= UTMIP_PD_CHRG;
1556                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1557         }
1558
1559         utmi_phy_pad_power_on(phy);
1560
1561         val = readl(base + UTMIP_XCVR_CFG0);
1562         val &= ~(UTMIP_XCVR_LSBIAS_SEL | UTMIP_FORCE_PD_POWERDOWN |
1563                  UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN |
1564                  UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_LSFSLEW(~0) |
1565                  UTMIP_XCVR_LSRSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
1566         val |= UTMIP_XCVR_SETUP(phy->utmi_xcvr_setup);
1567         val |= UTMIP_XCVR_SETUP_MSB(XCVR_SETUP_MSB_CALIB(phy->utmi_xcvr_setup));
1568         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
1569         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
1570         if (!config->xcvr_use_lsb)
1571                 val |= UTMIP_XCVR_HSSLEW_MSB(0x8);
1572         writel(val, base + UTMIP_XCVR_CFG0);
1573
1574         val = readl(base + UTMIP_XCVR_CFG1);
1575         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1576                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
1577         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
1578         writel(val, base + UTMIP_XCVR_CFG1);
1579
1580         val = readl(base + UTMIP_BIAS_CFG1);
1581         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
1582         val |= UTMIP_BIAS_PDTRK_COUNT(phy->freq->pdtrk_count);
1583         writel(val, base + UTMIP_BIAS_CFG1);
1584
1585         val = readl(base + UTMIP_SPARE_CFG0);
1586         val &= ~FUSE_SETUP_SEL;
1587         val |= FUSE_ATERM_SEL;
1588         writel(val, base + UTMIP_SPARE_CFG0);
1589
1590         val = readl(base + USB_SUSP_CTRL);
1591         val |= UTMIP_PHY_ENABLE;
1592         writel(val, base + USB_SUSP_CTRL);
1593
1594         val = readl(base + USB_SUSP_CTRL);
1595         val &= ~UTMIP_RESET;
1596         writel(val, base + USB_SUSP_CTRL);
1597
1598         val = readl(base + HOSTPC1_DEVLC);
1599         val &= ~HOSTPC1_DEVLC_PHCD;
1600         writel(val, base + HOSTPC1_DEVLC);
1601
1602         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1603                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500))
1604                 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
1605
1606         utmi_phy_enable_trking_data(phy);
1607
1608         if (phy->inst == 2)
1609                 writel(0, base + ICUSB_CTRL);
1610
1611         val = readl(base + USB_USBMODE);
1612         val &= ~USB_USBMODE_MASK;
1613         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST)
1614                 val |= USB_USBMODE_HOST;
1615         else
1616                 val |= USB_USBMODE_DEVICE;
1617         writel(val, base + USB_USBMODE);
1618
1619         val = readl(base + HOSTPC1_DEVLC);
1620         val &= ~HOSTPC1_DEVLC_PTS(~0);
1621         val |= HOSTPC1_DEVLC_STS;
1622         writel(val, base + HOSTPC1_DEVLC);
1623
1624         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE)
1625                 utmip_powerup_pmc_wake_detect(phy);
1626         phy->phy_clk_on = true;
1627         phy->hw_accessible = true;
1628         PHY_DBG("%s(%d) End inst:[%d]\n", __func__, __LINE__, phy->inst);
1629         return 0;
1630 }
1631
1632 static void utmi_phy_restore_start(struct tegra_usb_phy *phy)
1633 {
1634         unsigned long val;
1635         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1636         int inst = phy->inst;
1637
1638         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1639         val = readl(pmc_base + UTMIP_UHSIC_STATUS);
1640         /* check whether we wake up from the remote resume */
1641         if (UTMIP_WALK_PTR_VAL(inst) & val) {
1642                 phy->remote_wakeup = true;
1643         } else {
1644                 if (!((UTMIP_USBON_VAL(phy->inst) |
1645                         UTMIP_USBOP_VAL(phy->inst)) & val)) {
1646                                 utmip_phy_disable_pmc_bus_ctrl(phy);
1647                 }
1648         }
1649         utmi_phy_enable_obs_bus(phy);
1650 }
1651
1652 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
1653 {
1654         unsigned long val;
1655         void __iomem *base = phy->regs;
1656         int wait_time_us = 25000; /* FPR should be set by this time */
1657
1658         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1659         /* check whether we wake up from the remote resume */
1660         if (phy->remote_wakeup) {
1661                 /* wait until SUSPEND and RESUME bit is cleared on remote resume */
1662                 do {
1663                         val = readl(base + USB_PORTSC);
1664                         udelay(1);
1665                         if (wait_time_us == 0) {
1666                                 PHY_DBG("%s PMC REMOTE WAKEUP FPR timeout val = 0x%x instance = %d\n", __func__, val, phy->inst);
1667                                 utmip_phy_disable_pmc_bus_ctrl(phy);
1668                                 utmi_phy_post_resume(phy);
1669                                 return;
1670                         }
1671                         wait_time_us--;
1672                 } while (val & (USB_PORTSC_RESUME | USB_PORTSC_SUSP));
1673
1674                 /* wait for 25 ms to port resume complete */
1675                 msleep(25);
1676                 /* disable PMC master control */
1677                 utmip_phy_disable_pmc_bus_ctrl(phy);
1678
1679                 /* Clear PCI and SRI bits to avoid an interrupt upon resume */
1680                 val = readl(base + USB_USBSTS);
1681                 writel(val, base + USB_USBSTS);
1682                 /* wait to avoid SOF if there is any */
1683                 if (usb_phy_reg_status_wait(base + USB_USBSTS,
1684                         USB_USBSTS_SRI, USB_USBSTS_SRI, 2500) < 0) {
1685                         pr_err("%s: timeout waiting for SOF\n", __func__);
1686                 }
1687                 utmi_phy_post_resume(phy);
1688         }
1689 }
1690
1691 static int utmi_phy_resume(struct tegra_usb_phy *phy)
1692 {
1693         int status = 0;
1694         unsigned long val;
1695         void __iomem *base = phy->regs;
1696
1697         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1698         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) {
1699                 if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
1700                         utmi_phy_restore_start(phy);
1701                         usb_phy_bringup_host_controller(phy);
1702                         utmi_phy_restore_end(phy);
1703                 } else {
1704                         /* device is plugged in when system is in LP0 */
1705                         /* bring up the controller from LP0*/
1706                         val = readl(base + USB_USBCMD);
1707                         val |= USB_CMD_RESET;
1708                         writel(val, base + USB_USBCMD);
1709
1710                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1711                                 USB_CMD_RESET, 0, 2500) < 0) {
1712                                 pr_err("%s: timeout waiting for reset\n", __func__);
1713                         }
1714
1715                         val = readl(base + USB_USBMODE);
1716                         val &= ~USB_USBMODE_MASK;
1717                         val |= USB_USBMODE_HOST;
1718                         writel(val, base + USB_USBMODE);
1719
1720                         val = readl(base + HOSTPC1_DEVLC);
1721                         val &= ~HOSTPC1_DEVLC_PTS(~0);
1722                         val |= HOSTPC1_DEVLC_STS;
1723                         writel(val, base + HOSTPC1_DEVLC);
1724
1725                         writel(USB_USBCMD_RS, base + USB_USBCMD);
1726
1727                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1728                                 USB_USBCMD_RS, USB_USBCMD_RS, 2500) < 0) {
1729                                 pr_err("%s: timeout waiting for run bit\n", __func__);
1730                         }
1731
1732                         /* Enable Port Power */
1733                         val = readl(base + USB_PORTSC);
1734                         val |= USB_PORTSC_PP;
1735                         writel(val, base + USB_PORTSC);
1736                         udelay(10);
1737
1738                         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1739                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1740                 }
1741         }
1742
1743         return status;
1744 }
1745
1746 bool utmi_phy_charger_detect(struct tegra_usb_phy *phy)
1747 {
1748         unsigned long val;
1749         void __iomem *base = phy->regs;
1750         bool status;
1751
1752         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1753         if (phy->pdata->op_mode != TEGRA_USB_OPMODE_DEVICE) {
1754                 /* Charger detection is not there for ULPI
1755                  * return Charger not available */
1756                 return false;
1757         }
1758
1759         /* Enable charger detection logic */
1760         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1761         val |= UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN;
1762         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1763
1764         /* Source should be on for 100 ms as per USB charging spec */
1765         msleep(TDP_SRC_ON_MS);
1766
1767         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1768         /* If charger is not connected disable the interrupt */
1769         val &= ~VDAT_DET_INT_EN;
1770         val |= VDAT_DET_CHG_DET;
1771         writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
1772
1773         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1774         if (val & VDAT_DET_STS)
1775                 status = true;
1776         else
1777                 status = false;
1778
1779         /* Disable charger detection logic */
1780         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1781         val &= ~(UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN);
1782         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1783
1784         /* Delay of 40 ms before we pull the D+ as per battery charger spec */
1785         msleep(TDPSRC_CON_MS);
1786
1787         return status;
1788 }
1789
1790 static void uhsic_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
1791 {
1792         unsigned long val;
1793         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1794
1795         /* turn on pad detectors for HSIC*/
1796         val = readl(pmc_base + PMC_USB_AO);
1797         val &= ~(HSIC_RESERVED_P0 | STROBE_VAL_PD_P0 | DATA_VAL_PD_P0);
1798         writel(val, pmc_base + PMC_USB_AO);
1799
1800         /* Disable PMC master mode by clearing MASTER_EN */
1801         val = readl(pmc_base + PMC_SLEEP_CFG);
1802         val &= ~(UHSIC_MASTER_ENABLE_P0);
1803         writel(val, pmc_base + PMC_SLEEP_CFG);
1804         mdelay(1);
1805 }
1806
1807 static void uhsic_setup_pmc_wake_detect(struct tegra_usb_phy *phy)
1808 {
1809         unsigned long val;
1810         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1811         void __iomem *base = phy->regs;
1812         bool port_connected;
1813
1814         DBG("%s:%d\n", __func__, __LINE__);
1815
1816         /* check for port connect status */
1817         val = readl(base + USB_PORTSC);
1818         port_connected = val & USB_PORTSC_CCS;
1819
1820         if (!port_connected)
1821                 return;
1822
1823         /*Set PMC MASTER bits to do the following
1824         * a. Take over the hsic drivers
1825         * b. set up such that it will take over resume
1826         *        if remote wakeup is detected
1827         * Prepare PMC to take over suspend-wake detect-drive resume until USB
1828         * controller ready
1829         */
1830
1831         /* disable master enable in PMC */
1832         val = readl(pmc_base + PMC_SLEEP_CFG);
1833         val &= ~UHSIC_MASTER_ENABLE_P0;
1834         writel(val, pmc_base + PMC_SLEEP_CFG);
1835
1836         /* UTMIP_PWR_PX=1 for power savings mode */
1837         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
1838         val |= UHSIC_PWR;
1839         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
1840
1841
1842         /* Enable which type of event can trigger a walk,
1843         * in this case usb_line_wake */
1844         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
1845         val |= UHSIC_LINEVAL_WALK_EN;
1846         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
1847
1848         /* program walk sequence, maintain a J, followed by a driven K
1849         * to signal a resume once an wake event is detected */
1850
1851         val = readl(pmc_base + PMC_SLEEPWALK_UHSIC);
1852
1853         val &= ~UHSIC_DATA_RPU_A;
1854         val |=  UHSIC_DATA_RPD_A;
1855         val &= ~UHSIC_STROBE_RPD_A;
1856         val |=  UHSIC_STROBE_RPU_A;
1857         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1858
1859         val &= ~UHSIC_DATA_RPD_B;
1860         val |=  UHSIC_DATA_RPU_B;
1861         val &= ~UHSIC_STROBE_RPU_B;
1862         val |=  UHSIC_STROBE_RPD_B;
1863         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1864
1865         val &= ~UHSIC_DATA_RPD_C;
1866         val |=  UHSIC_DATA_RPU_C;
1867         val &= ~UHSIC_STROBE_RPU_C;
1868         val |=  UHSIC_STROBE_RPD_C;
1869         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1870
1871         val &= ~UHSIC_DATA_RPD_D;
1872         val |=  UHSIC_DATA_RPU_D;
1873         val &= ~UHSIC_STROBE_RPU_D;
1874         val |=  UHSIC_STROBE_RPD_D;
1875         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1876
1877         /* turn on pad detectors */
1878         val = readl(pmc_base + PMC_USB_AO);
1879         val &= ~(STROBE_VAL_PD_P0 | DATA_VAL_PD_P0);
1880         writel(val, pmc_base + PMC_USB_AO);
1881         /* Add small delay before usb detectors provide stable line values */
1882         udelay(1);
1883
1884         phy->remote_wakeup = false;
1885
1886         /* Turn over pad configuration to PMC  for line wake events*/
1887         val = readl(pmc_base + PMC_SLEEP_CFG);
1888         val &= ~UHSIC_WAKE_VAL(~0);
1889         val |= UHSIC_WAKE_VAL(WAKE_VAL_SD10);
1890         val |= UHSIC_MASTER_ENABLE;
1891         writel(val, pmc_base + PMC_SLEEP_CFG);
1892
1893         val = readl(base + UHSIC_PMC_WAKEUP0);
1894         val |= EVENT_INT_ENB;
1895         writel(val, base + UHSIC_PMC_WAKEUP0);
1896
1897         DBG("%s:PMC enabled for HSIC remote wakeup\n", __func__);
1898 }
1899
1900 static void uhsic_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy)
1901 {
1902         unsigned long val;
1903         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1904         void __iomem *base = phy->regs;
1905
1906         DBG("%s (%d)\n", __func__, __LINE__);
1907         val = readl(pmc_base + PMC_SLEEP_CFG);
1908         val &= ~UHSIC_WAKE_VAL(0x0);
1909         val |= UHSIC_WAKE_VAL(WAKE_VAL_NONE);
1910         writel(val, pmc_base + PMC_SLEEP_CFG);
1911
1912         val = readl(pmc_base + PMC_TRIGGERS);
1913         val |= UHSIC_CLR_WAKE_ALARM_P0 | UHSIC_CLR_WALK_PTR_P0;
1914         writel(val, pmc_base + PMC_TRIGGERS);
1915
1916         val = readl(base + UHSIC_PMC_WAKEUP0);
1917         val &= ~EVENT_INT_ENB;
1918         writel(val, base + UHSIC_PMC_WAKEUP0);
1919
1920         /* Disable PMC master mode by clearing MASTER_EN */
1921         val = readl(pmc_base + PMC_SLEEP_CFG);
1922         val &= ~(UHSIC_MASTER_ENABLE);
1923         writel(val, pmc_base + PMC_SLEEP_CFG);
1924
1925         /* turn off pad detectors */
1926         val = readl(pmc_base + PMC_USB_AO);
1927         val |= (STROBE_VAL_PD_P0 | DATA_VAL_PD_P0);
1928         writel(val, pmc_base + PMC_USB_AO);
1929
1930         phy->remote_wakeup = false;
1931 }
1932
1933 static bool uhsic_phy_remotewake_detected(struct tegra_usb_phy *phy)
1934 {
1935         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1936         void __iomem *base = phy->regs;
1937         u32 val;
1938
1939         val = readl(base + UHSIC_PMC_WAKEUP0);
1940         if (val & EVENT_INT_ENB) {
1941                 val = readl(pmc_base + UTMIP_UHSIC_STATUS);
1942                 if (UHSIC_WAKE_ALARM & val) {
1943                         val = readl(pmc_base + PMC_SLEEP_CFG);
1944                         val &= ~UHSIC_WAKE_VAL(0x0);
1945                         val |= UHSIC_WAKE_VAL(WAKE_VAL_NONE);
1946                         writel(val, pmc_base + PMC_SLEEP_CFG);
1947
1948                         val = readl(pmc_base + PMC_TRIGGERS);
1949                         val |= UHSIC_CLR_WAKE_ALARM_P0 | UHSIC_CLR_WALK_PTR_P0;
1950                         writel(val, pmc_base + PMC_TRIGGERS);
1951
1952                         val = readl(base + UHSIC_PMC_WAKEUP0);
1953                         val &= ~EVENT_INT_ENB;
1954                         writel(val, base + UHSIC_PMC_WAKEUP0);
1955                         phy->remote_wakeup = true;
1956                         DBG("%s:PMC remote wakeup detected for HSIC\n", __func__);
1957                         return true;
1958                 }
1959         }
1960         return false;
1961 }
1962
1963 static int uhsic_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1964 {
1965         DBG("%s(%d)\n", __func__, __LINE__);
1966
1967         if (!remote_wakeup)
1968                 usb_phy_wait_for_sof(phy);
1969
1970         return 0;
1971 }
1972
1973 static int uhsic_phy_post_resume(struct tegra_usb_phy *phy)
1974 {
1975         unsigned long val;
1976         void __iomem *base = phy->regs;
1977
1978         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1979         val = readl(base + USB_TXFILLTUNING);
1980         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
1981                 val = USB_FIFO_TXFILL_THRES(0x10);
1982                 writel(val, base + USB_TXFILLTUNING);
1983         }
1984
1985         return 0;
1986 }
1987
1988 static void uhsic_phy_restore_start(struct tegra_usb_phy *phy)
1989 {
1990         unsigned long val;
1991         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1992         void __iomem *base = phy->regs;
1993
1994         val = readl(pmc_base + UTMIP_UHSIC_STATUS);
1995
1996         /* check whether we wake up from the remote resume */
1997         if (UHSIC_WALK_PTR_VAL & val) {
1998                 phy->remote_wakeup = true;
1999         } else {
2000                 if (!((UHSIC_STROBE_VAL_P0 | UHSIC_DATA_VAL_P0) & val)) {
2001                                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2002                 } else {
2003                         DBG("%s(%d): setting pretend connect\n", __func__, __LINE__);
2004                         val = readl(base + UHSIC_CMD_CFG0);
2005                         val |= UHSIC_PRETEND_CONNECT_DETECT;
2006                         writel(val, base + UHSIC_CMD_CFG0);
2007                 }
2008         }
2009 }
2010
2011 static void uhsic_phy_restore_end(struct tegra_usb_phy *phy)
2012 {
2013
2014         unsigned long val;
2015         void __iomem *base = phy->regs;
2016         int wait_time_us = 3000; /* FPR should be set by this time */
2017
2018         DBG("%s(%d)\n", __func__, __LINE__);
2019
2020         /* check whether we wake up from the remote resume */
2021         if (phy->remote_wakeup) {
2022                 /* wait until FPR bit is set automatically on remote resume */
2023                 do {
2024                         val = readl(base + USB_PORTSC);
2025                         udelay(1);
2026                         if (wait_time_us == 0) {
2027                                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2028                                 uhsic_phy_post_resume(phy);
2029                                 return;
2030                         }
2031                         wait_time_us--;
2032                 } while (!(val & USB_PORTSC_RESUME));
2033                 /* wait for 25 ms to port resume complete */
2034                 msleep(25);
2035                 /* disable PMC master control */
2036                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2037
2038                 /* Clear PCI and SRI bits to avoid an interrupt upon resume */
2039                 val = readl(base + USB_USBSTS);
2040                 writel(val, base + USB_USBSTS);
2041                 /* wait to avoid SOF if there is any */
2042                 if (usb_phy_reg_status_wait(base + USB_USBSTS,
2043                         USB_USBSTS_SRI, USB_USBSTS_SRI, 2500)) {
2044                         pr_warn("%s: timeout waiting for SOF\n", __func__);
2045                 }
2046                 uhsic_phy_post_resume(phy);
2047         } else {
2048                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2049         }
2050
2051         /* Set RUN bit */
2052         val = readl(base + USB_USBCMD);
2053         val |= USB_USBCMD_RS;
2054         writel(val, base + USB_USBCMD);
2055         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2056                                                  USB_USBCMD_RS, 2000)) {
2057                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2058                 return;
2059         }
2060 }
2061
2062 static int uhsic_phy_open(struct tegra_usb_phy *phy)
2063 {
2064         unsigned long parent_rate;
2065         int i;
2066
2067         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2068         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
2069         for (i = 0; i < ARRAY_SIZE(uhsic_freq_table); i++) {
2070                 if (uhsic_freq_table[i].freq == parent_rate) {
2071                         phy->freq = &uhsic_freq_table[i];
2072                         break;
2073                 }
2074         }
2075         if (!phy->freq) {
2076                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
2077                 return -EINVAL;
2078         }
2079
2080         uhsic_powerup_pmc_wake_detect(phy);
2081
2082         return 0;
2083 }
2084
2085 static int uhsic_phy_irq(struct tegra_usb_phy *phy)
2086 {
2087         usb_phy_fence_read(phy);
2088         /* check if there is any remote wake event */
2089         if (uhsic_phy_remotewake_detected(phy))
2090                 pr_info("%s: uhsic remote wake detected\n", __func__);
2091         return IRQ_HANDLED;
2092 }
2093
2094 static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
2095 {
2096         unsigned long val;
2097         void __iomem *base = phy->regs;
2098         struct tegra_hsic_config *config = &phy->pdata->u_cfg.hsic;
2099
2100         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2101
2102         if (phy->phy_clk_on) {
2103                 DBG("%s(%d) inst:[%d] phy clk is already On\n",
2104                                         __func__, __LINE__, phy->inst);
2105                 return 0;
2106         }
2107
2108         val = readl(base + UHSIC_PADS_CFG1);
2109         val &= ~(UHSIC_PD_BG | UHSIC_PD_TRK | UHSIC_PD_RX |
2110                         UHSIC_PD_ZI | UHSIC_RPD_DATA | UHSIC_RPD_STROBE);
2111         val |= (UHSIC_RX_SEL | UHSIC_PD_TX);
2112         writel(val, base + UHSIC_PADS_CFG1);
2113
2114         val = readl(base + USB_SUSP_CTRL);
2115         val |= UHSIC_RESET;
2116         writel(val, base + USB_SUSP_CTRL);
2117         udelay(1);
2118
2119         val = readl(base + USB_SUSP_CTRL);
2120         val |= UHSIC_PHY_ENABLE;
2121         writel(val, base + USB_SUSP_CTRL);
2122
2123         val = readl(base + UHSIC_HSRX_CFG0);
2124         val |= UHSIC_IDLE_WAIT(config->idle_wait_delay);
2125         val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(config->elastic_underrun_limit);
2126         val |= UHSIC_ELASTIC_OVERRUN_LIMIT(config->elastic_overrun_limit);
2127         writel(val, base + UHSIC_HSRX_CFG0);
2128
2129         val = readl(base + UHSIC_HSRX_CFG1);
2130         val |= UHSIC_HS_SYNC_START_DLY(config->sync_start_delay);
2131         writel(val, base + UHSIC_HSRX_CFG1);
2132
2133         /* WAR HSIC TX */
2134         val = readl(base + UHSIC_TX_CFG0);
2135         val &= ~UHSIC_HS_READY_WAIT_FOR_VALID;
2136         writel(val, base + UHSIC_TX_CFG0);
2137
2138         val = readl(base + UHSIC_MISC_CFG0);
2139         val |= UHSIC_SUSPEND_EXIT_ON_EDGE;
2140         /* Disable generic bus reset, to allow AP30 specific bus reset*/
2141         val |= UHSIC_DISABLE_BUSRESET;
2142         writel(val, base + UHSIC_MISC_CFG0);
2143
2144         val = readl(base + UHSIC_MISC_CFG1);
2145         val |= UHSIC_PLLU_STABLE_COUNT(phy->freq->stable_count);
2146         writel(val, base + UHSIC_MISC_CFG1);
2147
2148         val = readl(base + UHSIC_PLL_CFG1);
2149         val |= UHSIC_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
2150         val |= UHSIC_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count);
2151         writel(val, base + UHSIC_PLL_CFG1);
2152
2153         val = readl(base + USB_SUSP_CTRL);
2154         val &= ~(UHSIC_RESET);
2155         writel(val, base + USB_SUSP_CTRL);
2156         udelay(1);
2157
2158         val = readl(base + UHSIC_PADS_CFG1);
2159         val &= ~(UHSIC_PD_TX);
2160         writel(val, base + UHSIC_PADS_CFG1);
2161
2162         val = readl(base + USB_USBMODE);
2163         val |= USB_USBMODE_HOST;
2164         writel(val, base + USB_USBMODE);
2165
2166         /* Change the USB controller PHY type to HSIC */
2167         val = readl(base + HOSTPC1_DEVLC);
2168         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
2169         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2170         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
2171         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2172         val &= ~HOSTPC1_DEVLC_STS;
2173         writel(val, base + HOSTPC1_DEVLC);
2174
2175         val = readl(base + USB_TXFILLTUNING);
2176         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
2177                 val = USB_FIFO_TXFILL_THRES(0x10);
2178                 writel(val, base + USB_TXFILLTUNING);
2179         }
2180
2181         val = readl(base + USB_PORTSC);
2182         val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN);
2183         writel(val, base + USB_PORTSC);
2184
2185         val = readl(base + UHSIC_PADS_CFG0);
2186         val &= ~(UHSIC_TX_RTUNEN);
2187         /* set Rtune impedance to 50 ohm */
2188         val |= UHSIC_TX_RTUNE(8);
2189         writel(val, base + UHSIC_PADS_CFG0);
2190
2191         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
2192                                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500)) {
2193                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2194                 return -ETIMEDOUT;
2195         }
2196
2197         phy->phy_clk_on = true;
2198         phy->hw_accessible = true;
2199
2200         return 0;
2201 }
2202
2203 static int uhsic_phy_power_off(struct tegra_usb_phy *phy)
2204 {
2205         unsigned long val;
2206         void __iomem *base = phy->regs;
2207
2208         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2209         if (!phy->phy_clk_on) {
2210                 DBG("%s(%d) inst:[%d] phy clk is already off\n",
2211                                         __func__, __LINE__, phy->inst);
2212                 return 0;
2213         }
2214
2215         phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
2216                         HOSTPC1_DEVLC_PSPD_MASK;
2217
2218         /* Disable interrupts */
2219         writel(0, base + USB_USBINTR);
2220
2221         uhsic_setup_pmc_wake_detect(phy);
2222
2223         val = readl(base + HOSTPC1_DEVLC);
2224         val |= HOSTPC1_DEVLC_PHCD;
2225         writel(val, base + HOSTPC1_DEVLC);
2226
2227         phy->phy_clk_on = false;
2228         phy->hw_accessible = false;
2229
2230         return 0;
2231 }
2232
2233 int uhsic_phy_bus_port_power(struct tegra_usb_phy *phy)
2234 {
2235         unsigned long val;
2236         void __iomem *base = phy->regs;
2237
2238         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2239
2240         val = readl(base + USB_USBMODE);
2241         val |= USB_USBMODE_HOST;
2242         writel(val, base + USB_USBMODE);
2243
2244         /* Change the USB controller PHY type to HSIC */
2245         val = readl(base + HOSTPC1_DEVLC);
2246         val &= ~(HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK));
2247         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2248         val &= ~(HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK));
2249         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2250         writel(val, base + HOSTPC1_DEVLC);
2251
2252         val = readl(base + UHSIC_MISC_CFG0);
2253         val |= UHSIC_DETECT_SHORT_CONNECT;
2254         writel(val, base + UHSIC_MISC_CFG0);
2255         udelay(1);
2256
2257         val = readl(base + UHSIC_MISC_CFG0);
2258         val |= UHSIC_FORCE_XCVR_MODE;
2259         writel(val, base + UHSIC_MISC_CFG0);
2260
2261         val = readl(base + UHSIC_PADS_CFG1);
2262         val &= ~UHSIC_RPD_STROBE;
2263         writel(val, base + UHSIC_PADS_CFG1);
2264
2265         if (phy->pdata->ops && phy->pdata->ops->port_power)
2266                 phy->pdata->ops->port_power();
2267
2268         if (usb_phy_reg_status_wait(base + UHSIC_STAT_CFG0,
2269                         UHSIC_CONNECT_DETECT, UHSIC_CONNECT_DETECT, 25000)) {
2270                 pr_err("%s: timeout waiting for UHSIC_CONNECT_DETECT\n",
2271                                                                 __func__);
2272                 return -ETIMEDOUT;
2273         }
2274
2275         return 0;
2276 }
2277
2278 static int uhsic_phy_bus_reset(struct tegra_usb_phy *phy)
2279 {
2280         unsigned long val;
2281         void __iomem *base = phy->regs;
2282
2283         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2284
2285         /* Change the USB controller PHY type to HSIC */
2286         val = readl(base + HOSTPC1_DEVLC);
2287         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
2288         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2289         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
2290         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2291         val &= ~HOSTPC1_DEVLC_STS;
2292         writel(val, base + HOSTPC1_DEVLC);
2293         /* wait here, otherwise HOSTPC1_DEVLC_PSPD will timeout */
2294         mdelay(5);
2295
2296         val = readl(base + USB_PORTSC);
2297         val |= USB_PORTSC_PTC(5);
2298         writel(val, base + USB_PORTSC);
2299         udelay(2);
2300
2301         val = readl(base + USB_PORTSC);
2302         val &= ~(USB_PORTSC_PTC(~0));
2303         writel(val, base + USB_PORTSC);
2304         udelay(2);
2305
2306         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_LS(0),
2307                                                  0, 2000)) {
2308                 pr_err("%s: timeout waiting for USB_PORTSC_LS\n", __func__);
2309                 return -ETIMEDOUT;
2310         }
2311
2312         /* Poll until CCS is enabled */
2313         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
2314                                                  USB_PORTSC_CCS, 2000)) {
2315                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
2316                 return -ETIMEDOUT;
2317         }
2318
2319         if (usb_phy_reg_status_wait(base + HOSTPC1_DEVLC,
2320                         HOSTPC1_DEVLC_PSPD(2),
2321                         HOSTPC1_DEVLC_PSPD(2), 2000) < 0) {
2322                 pr_err("%s: timeout waiting hsic high speed configuration\n",
2323                                                 __func__);
2324                         return -ETIMEDOUT;
2325         }
2326
2327         val = readl(base + USB_USBCMD);
2328         val &= ~USB_USBCMD_RS;
2329         writel(val, base + USB_USBCMD);
2330
2331         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
2332                                                  USB_USBSTS_HCH, 2000)) {
2333                 pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
2334                 return -ETIMEDOUT;
2335         }
2336
2337         val = readl(base + UHSIC_PADS_CFG1);
2338         val &= ~UHSIC_RPU_STROBE;
2339         val |= UHSIC_RPD_STROBE;
2340         writel(val, base + UHSIC_PADS_CFG1);
2341
2342         mdelay(50);
2343
2344         val = readl(base + UHSIC_PADS_CFG1);
2345         val &= ~UHSIC_RPD_STROBE;
2346         val |= UHSIC_RPU_STROBE;
2347         writel(val, base + UHSIC_PADS_CFG1);
2348
2349         val = readl(base + USB_USBCMD);
2350         val |= USB_USBCMD_RS;
2351         writel(val, base + USB_USBCMD);
2352
2353         val = readl(base + UHSIC_PADS_CFG1);
2354         val &= ~UHSIC_RPU_STROBE;
2355         writel(val, base + UHSIC_PADS_CFG1);
2356
2357         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2358                                                  USB_USBCMD_RS, 2000)) {
2359                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2360                 return -ETIMEDOUT;
2361         }
2362
2363         return 0;
2364 }
2365
2366 int uhsic_phy_resume(struct tegra_usb_phy *phy)
2367 {
2368         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2369
2370         uhsic_phy_restore_start(phy);
2371         usb_phy_bringup_host_controller(phy);
2372         uhsic_phy_restore_end(phy);
2373
2374         return 0;
2375 }
2376
2377 static void ulpi_set_trimmer(struct tegra_usb_phy *phy)
2378 {
2379         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2380         void __iomem *base = phy->regs;
2381         unsigned long val;
2382
2383         val = ULPI_DATA_TRIMMER_SEL(config->data_trimmer);
2384         val |= ULPI_STPDIRNXT_TRIMMER_SEL(config->stpdirnxt_trimmer);
2385         val |= ULPI_DIR_TRIMMER_SEL(config->dir_trimmer);
2386         writel(val, base + ULPI_TIMING_CTRL_1);
2387         udelay(10);
2388
2389         val |= ULPI_DATA_TRIMMER_LOAD;
2390         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
2391         val |= ULPI_DIR_TRIMMER_LOAD;
2392         writel(val, base + ULPI_TIMING_CTRL_1);
2393 }
2394
2395 static void reset_utmip_uhsic(void __iomem *base)
2396 {
2397         unsigned long val;
2398
2399         val = readl(base + USB_SUSP_CTRL);
2400         val |= UHSIC_RESET;
2401         writel(val, base + USB_SUSP_CTRL);
2402
2403         val = readl(base + USB_SUSP_CTRL);
2404         val |= UTMIP_RESET;
2405         writel(val, base + USB_SUSP_CTRL);
2406 }
2407
2408 static void ulpi_set_host(void __iomem *base)
2409 {
2410         unsigned long val;
2411
2412         val = readl(base + USB_USBMODE);
2413         val &= ~USB_USBMODE_MASK;
2414         val |= USB_USBMODE_HOST;
2415         writel(val, base + USB_USBMODE);
2416
2417         val = readl(base + HOSTPC1_DEVLC);
2418         val |= HOSTPC1_DEVLC_PTS(2);
2419         writel(val, base + HOSTPC1_DEVLC);
2420 }
2421
2422 static inline void ulpi_pinmux_bypass(struct tegra_usb_phy *phy, bool enable)
2423 {
2424         unsigned long val;
2425         void __iomem *base = phy->regs;
2426
2427         val = readl(base + ULPI_TIMING_CTRL_0);
2428
2429         if (enable)
2430                 val |= ULPI_OUTPUT_PINMUX_BYP;
2431         else
2432                 val &= ~ULPI_OUTPUT_PINMUX_BYP;
2433
2434         writel(val, base + ULPI_TIMING_CTRL_0);
2435 }
2436
2437 static inline void ulpi_null_phy_set_tristate(bool enable)
2438 {
2439 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2440         int tristate = (enable) ? TEGRA_TRI_TRISTATE : TEGRA_TRI_NORMAL;
2441
2442         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA0, tristate);
2443         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA1, tristate);
2444         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA2, tristate);
2445         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA3, tristate);
2446         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA4, tristate);
2447         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA5, tristate);
2448         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA6, tristate);
2449         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA7, tristate);
2450         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_NXT, tristate);
2451
2452         if (enable)
2453                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR, tristate);
2454 #endif
2455 }
2456
2457 static void ulpi_null_phy_obs_read(void)
2458 {
2459         static void __iomem *apb_misc;
2460         unsigned slv0_obs, s2s_obs;
2461
2462         if (!apb_misc)
2463                 apb_misc = ioremap(TEGRA_APB_MISC_BASE, TEGRA_APB_MISC_SIZE);
2464
2465         writel(0x80d1003c, apb_misc + APB_MISC_GP_OBSCTRL_0);
2466         slv0_obs = readl(apb_misc + APB_MISC_GP_OBSDATA_0);
2467
2468         writel(0x80d10040, apb_misc + APB_MISC_GP_OBSCTRL_0);
2469         s2s_obs = readl(apb_misc + APB_MISC_GP_OBSDATA_0);
2470
2471         pr_debug("slv0 obs: %08x\ns2s obs: %08x\n", slv0_obs, s2s_obs);
2472 }
2473
2474 static const struct gpio ulpi_gpios[] = {
2475         {ULPI_STP, GPIOF_IN, "ULPI_STP"},
2476         {ULPI_DIR, GPIOF_OUT_INIT_LOW, "ULPI_DIR"},
2477         {ULPI_D0, GPIOF_OUT_INIT_LOW, "ULPI_D0"},
2478         {ULPI_D1, GPIOF_OUT_INIT_LOW, "ULPI_D1"},
2479 };
2480
2481 static int ulpi_null_phy_open(struct tegra_usb_phy *phy)
2482 {
2483         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2484         int ret;
2485
2486         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2487
2488         ret = gpio_request_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
2489         if (ret)
2490                 return ret;
2491
2492         if (gpio_is_valid(config->phy_restore_gpio)) {
2493                 ret = gpio_request(config->phy_restore_gpio, "phy_restore");
2494                 if (ret)
2495                         goto err_gpio_free;
2496
2497                 gpio_direction_input(config->phy_restore_gpio);
2498         }
2499
2500         tegra_periph_reset_assert(phy->ctrlr_clk);
2501         udelay(10);
2502         tegra_periph_reset_deassert(phy->ctrlr_clk);
2503
2504         return 0;
2505
2506 err_gpio_free:
2507         gpio_free_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
2508         return ret;
2509 }
2510
2511 static void ulpi_null_phy_close(struct tegra_usb_phy *phy)
2512 {
2513         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2514
2515         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2516
2517         if (gpio_is_valid(config->phy_restore_gpio))
2518                 gpio_free(config->phy_restore_gpio);
2519
2520         gpio_free_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
2521 }
2522
2523 static int ulpi_null_phy_power_off(struct tegra_usb_phy *phy)
2524 {
2525         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2526
2527         if (!phy->phy_clk_on) {
2528                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
2529                                                         __LINE__, phy->inst);
2530                 return 0;
2531         }
2532
2533         phy->phy_clk_on = false;
2534         phy->hw_accessible = false;
2535         ulpi_null_phy_set_tristate(true);
2536         return 0;
2537 }
2538
2539 /* NOTE: this function must be called before ehci reset */
2540 static int ulpi_null_phy_init(struct tegra_usb_phy *phy)
2541 {
2542         unsigned long val;
2543         void __iomem *base = phy->regs;
2544
2545         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2546         val = readl(base + ULPIS2S_CTRL);
2547         val |=  ULPIS2S_SLV0_CLAMP_XMIT;
2548         writel(val, base + ULPIS2S_CTRL);
2549
2550         val = readl(base + USB_SUSP_CTRL);
2551         val |= ULPIS2S_SLV0_RESET;
2552         writel(val, base + USB_SUSP_CTRL);
2553         udelay(10);
2554
2555         return 0;
2556 }
2557
2558 static int ulpi_null_phy_irq(struct tegra_usb_phy *phy)
2559 {
2560         usb_phy_fence_read(phy);
2561         return IRQ_HANDLED;
2562 }
2563
2564 /* NOTE: this function must be called after ehci reset */
2565 static int ulpi_null_phy_cmd_reset(struct tegra_usb_phy *phy)
2566 {
2567         unsigned long val;
2568         void __iomem *base = phy->regs;
2569
2570         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2571         ulpi_set_host(base);
2572
2573         /* remove slave0 reset */
2574         val = readl(base + USB_SUSP_CTRL);
2575         val &= ~ULPIS2S_SLV0_RESET;
2576         writel(val, base + USB_SUSP_CTRL);
2577
2578         val = readl(base + ULPIS2S_CTRL);
2579         val &=  ~ULPIS2S_SLV0_CLAMP_XMIT;
2580         writel(val, base + ULPIS2S_CTRL);
2581         udelay(10);
2582
2583         return 0;
2584 }
2585
2586 static int ulpi_null_phy_restore(struct tegra_usb_phy *phy)
2587 {
2588         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2589         unsigned long timeout;
2590         int ulpi_stp = ULPI_STP;
2591
2592         if (gpio_is_valid(config->phy_restore_gpio))
2593                 ulpi_stp = config->phy_restore_gpio;
2594
2595         /* disable ULPI pinmux bypass */
2596         ulpi_pinmux_bypass(phy, false);
2597
2598         /* driving linstate by GPIO */
2599         gpio_set_value(ULPI_D0, 0);
2600         gpio_set_value(ULPI_D1, 0);
2601
2602         /* driving DIR high */
2603         gpio_set_value(ULPI_DIR, 1);
2604
2605         /* remove ULPI tristate */
2606         ulpi_null_phy_set_tristate(false);
2607
2608         /* wait for STP high */
2609         timeout = jiffies + msecs_to_jiffies(25);
2610
2611         while (!gpio_get_value(ulpi_stp)) {
2612                 if (time_after(jiffies, timeout)) {
2613                         pr_warn("phy restore timeout\n");
2614                         return 1;
2615                 }
2616         }
2617
2618         return 0;
2619 }
2620
2621 static int ulpi_null_phy_lp0_resume(struct tegra_usb_phy *phy)
2622 {
2623         unsigned long val;
2624         void __iomem *base = phy->regs;
2625
2626         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2627         ulpi_null_phy_init(phy);
2628
2629         val = readl(base + USB_USBCMD);
2630         val |= USB_CMD_RESET;
2631         writel(val, base + USB_USBCMD);
2632
2633         if (usb_phy_reg_status_wait(base + USB_USBCMD,
2634                 USB_CMD_RESET, 0, 2500) < 0) {
2635                 pr_err("%s: timeout waiting for reset\n", __func__);
2636         }
2637
2638         ulpi_null_phy_cmd_reset(phy);
2639
2640         val = readl(base + USB_USBCMD);
2641         val |= USB_USBCMD_RS;
2642         writel(val, base + USB_USBCMD);
2643         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2644                                                  USB_USBCMD_RS, 2000)) {
2645                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2646                 return -ETIMEDOUT;
2647         }
2648
2649         /* Enable Port Power */
2650         val = readl(base + USB_PORTSC);
2651         val |= USB_PORTSC_PP;
2652         writel(val, base + USB_PORTSC);
2653         udelay(10);
2654
2655         ulpi_null_phy_restore(phy);
2656
2657         return 0;
2658 }
2659
2660 static int ulpi_null_phy_power_on(struct tegra_usb_phy *phy)
2661 {
2662         unsigned long val;
2663         void __iomem *base = phy->regs;
2664         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2665
2666         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2667         if (phy->phy_clk_on) {
2668                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
2669                                                         __LINE__, phy->inst);
2670                 return 0;
2671         }
2672         reset_utmip_uhsic(base);
2673
2674         /* remove ULPI PADS CLKEN reset */
2675         val = readl(base + USB_SUSP_CTRL);
2676         val &= ~ULPI_PADS_CLKEN_RESET;
2677         writel(val, base + USB_SUSP_CTRL);
2678         udelay(10);
2679
2680         val = readl(base + ULPI_TIMING_CTRL_0);
2681         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
2682         writel(val, base + ULPI_TIMING_CTRL_0);
2683
2684         val = readl(base + USB_SUSP_CTRL);
2685         val |= ULPI_PHY_ENABLE;
2686         writel(val, base + USB_SUSP_CTRL);
2687         udelay(10);
2688
2689         /* set timming parameters */
2690         val = readl(base + ULPI_TIMING_CTRL_0);
2691         val |= ULPI_SHADOW_CLK_LOOPBACK_EN;
2692         val &= ~ULPI_SHADOW_CLK_SEL;
2693         val &= ~ULPI_LBK_PAD_EN;
2694         val |= ULPI_SHADOW_CLK_DELAY(config->shadow_clk_delay);
2695         val |= ULPI_CLOCK_OUT_DELAY(config->clock_out_delay);
2696         val |= ULPI_LBK_PAD_E_INPUT_OR;
2697         writel(val, base + ULPI_TIMING_CTRL_0);
2698
2699         writel(0, base + ULPI_TIMING_CTRL_1);
2700         udelay(10);
2701
2702         /* start internal 60MHz clock */
2703         val = readl(base + ULPIS2S_CTRL);
2704         val |= ULPIS2S_ENA;
2705         val |= ULPIS2S_SUPPORT_DISCONNECT;
2706         val |= ULPIS2S_SPARE((phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) ? 3 : 1);
2707         val |= ULPIS2S_PLLU_MASTER_BLASTER60;
2708         writel(val, base + ULPIS2S_CTRL);
2709
2710         /* select ULPI_CORE_CLK_SEL to SHADOW_CLK */
2711         val = readl(base + ULPI_TIMING_CTRL_0);
2712         val |= ULPI_CORE_CLK_SEL;
2713         writel(val, base + ULPI_TIMING_CTRL_0);
2714         udelay(10);
2715
2716         /* enable ULPI null phy clock - can't set the trimmers before this */
2717         val = readl(base + ULPI_TIMING_CTRL_0);
2718         val |= ULPI_CLK_OUT_ENA;
2719         writel(val, base + ULPI_TIMING_CTRL_0);
2720         udelay(10);
2721
2722         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
2723                                                  USB_PHY_CLK_VALID, 2500)) {
2724                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2725                 return -ETIMEDOUT;
2726         }
2727
2728         /* set ULPI trimmers */
2729         ulpi_set_trimmer(phy);
2730
2731         ulpi_set_host(base);
2732
2733         /* remove slave0 reset */
2734         val = readl(base + USB_SUSP_CTRL);
2735         val &= ~ULPIS2S_SLV0_RESET;
2736         writel(val, base + USB_SUSP_CTRL);
2737
2738         /* remove slave1 and line reset */
2739         val = readl(base + USB_SUSP_CTRL);
2740         val &= ~ULPIS2S_SLV1_RESET;
2741         val &= ~ULPIS2S_LINE_RESET;
2742
2743         /* remove ULPI PADS reset */
2744         val &= ~ULPI_PADS_RESET;
2745         writel(val, base + USB_SUSP_CTRL);
2746
2747         if (!phy->ulpi_clk_padout_ena) {
2748                 val = readl(base + ULPI_TIMING_CTRL_0);
2749                 val |= ULPI_CLK_PADOUT_ENA;
2750                 writel(val, base + ULPI_TIMING_CTRL_0);
2751                 phy->ulpi_clk_padout_ena = true;
2752         } else {
2753                 if (!readl(base + USB_ASYNCLISTADDR))
2754                         ulpi_null_phy_lp0_resume(phy);
2755         }
2756         udelay(10);
2757
2758         phy->phy_clk_on = true;
2759         phy->hw_accessible = true;
2760
2761         return 0;
2762 }
2763
2764 static int ulpi_null_phy_pre_resume(struct tegra_usb_phy *phy,
2765                                     bool remote_wakeup)
2766 {
2767         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2768         ulpi_null_phy_obs_read();
2769         usb_phy_wait_for_sof(phy);
2770         ulpi_null_phy_obs_read();
2771         return 0;
2772 }
2773
2774 static int ulpi_null_phy_post_resume(struct tegra_usb_phy *phy)
2775 {
2776         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2777         ulpi_null_phy_obs_read();
2778         return 0;
2779 }
2780
2781 static int ulpi_null_phy_resume(struct tegra_usb_phy *phy)
2782 {
2783         unsigned long val;
2784         void __iomem *base = phy->regs;
2785
2786         if (!readl(base + USB_ASYNCLISTADDR)) {
2787                 /* enable ULPI CLK output pad */
2788                 val = readl(base + ULPI_TIMING_CTRL_0);
2789                 val |= ULPI_CLK_PADOUT_ENA;
2790                 writel(val, base + ULPI_TIMING_CTRL_0);
2791
2792                 /* enable ULPI pinmux bypass */
2793                 ulpi_pinmux_bypass(phy, true);
2794                 udelay(5);
2795 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2796                 /* remove DIR tristate */
2797                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR,
2798                                           TEGRA_TRI_NORMAL);
2799 #endif
2800         }
2801         return 0;
2802 }
2803
2804
2805
2806 static struct tegra_usb_phy_ops utmi_phy_ops = {
2807         .open           = utmi_phy_open,
2808         .close          = utmi_phy_close,
2809         .irq            = utmi_phy_irq,
2810         .power_on       = utmi_phy_power_on,
2811         .power_off      = utmi_phy_power_off,
2812         .pre_resume = utmi_phy_pre_resume,
2813         .resume = utmi_phy_resume,
2814         .post_resume    = utmi_phy_post_resume,
2815         .charger_detect = utmi_phy_charger_detect,
2816 };
2817
2818 static struct tegra_usb_phy_ops uhsic_phy_ops = {
2819         .open           = uhsic_phy_open,
2820         .irq            = uhsic_phy_irq,
2821         .power_on       = uhsic_phy_power_on,
2822         .power_off      = uhsic_phy_power_off,
2823         .pre_resume = uhsic_phy_pre_resume,
2824         .resume = uhsic_phy_resume,
2825         .post_resume = uhsic_phy_post_resume,
2826         .port_power = uhsic_phy_bus_port_power,
2827         .bus_reset      = uhsic_phy_bus_reset,
2828 };
2829
2830 static struct tegra_usb_phy_ops ulpi_null_phy_ops = {
2831         .open           = ulpi_null_phy_open,
2832         .close          = ulpi_null_phy_close,
2833         .init           = ulpi_null_phy_init,
2834         .irq            = ulpi_null_phy_irq,
2835         .power_on       = ulpi_null_phy_power_on,
2836         .power_off      = ulpi_null_phy_power_off,
2837         .pre_resume = ulpi_null_phy_pre_resume,
2838         .resume = ulpi_null_phy_resume,
2839         .post_resume = ulpi_null_phy_post_resume,
2840         .reset          = ulpi_null_phy_cmd_reset,
2841 };
2842
2843 static struct tegra_usb_phy_ops ulpi_link_phy_ops;
2844 static struct tegra_usb_phy_ops icusb_phy_ops;
2845
2846 static struct tegra_usb_phy_ops *phy_ops[] = {
2847         [TEGRA_USB_PHY_INTF_UTMI] = &utmi_phy_ops,
2848         [TEGRA_USB_PHY_INTF_ULPI_LINK] = &ulpi_link_phy_ops,
2849         [TEGRA_USB_PHY_INTF_ULPI_NULL] = &ulpi_null_phy_ops,
2850         [TEGRA_USB_PHY_INTF_HSIC] = &uhsic_phy_ops,
2851         [TEGRA_USB_PHY_INTF_ICUSB] = &icusb_phy_ops,
2852 };
2853
2854 int tegra3_usb_phy_init_ops(struct tegra_usb_phy *phy)
2855 {
2856         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2857
2858         phy->ops = phy_ops[phy->pdata->phy_intf];
2859
2860         /* FIXME: uncommenting below line to make USB host mode fail*/
2861         /* usb_phy_power_down_pmc(); */
2862
2863         return 0;
2864 }