arm: tegra: usb_phy: add common phy interface
[linux-2.6.git] / arch / arm / mach-tegra / tegra3_usb_phy.c
1 /*
2  * arch/arm/mach-tegra/tegra3_usb_phy.c
3  *
4  * Copyright (C) 2011 NVIDIA Corporation
5  *
6  *
7  * This software is licensed under the terms of the GNU General Public
8  * License version 2, as published by the Free Software Foundation, and
9  * may be copied, distributed, and modified under those terms.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17 #include <linux/resource.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/slab.h>
21 #include <linux/err.h>
22 #include <linux/platform_device.h>
23 #include <linux/io.h>
24 #include <linux/gpio.h>
25 #include <linux/interrupt.h>
26 #include <linux/clk.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <mach/iomap.h>
30 #include <mach/pinmux.h>
31 #include <mach/pinmux-tegra30.h>
32 #include "tegra_usb_phy.h"
33 #include "fuse.h"
34
35 #define USB_USBCMD              0x130
36 #define   USB_USBCMD_RS         (1 << 0)
37 #define   USB_CMD_RESET (1<<1)
38
39 #define USB_USBSTS              0x134
40 #define   USB_USBSTS_PCI        (1 << 2)
41 #define   USB_USBSTS_SRI        (1 << 7)
42 #define   USB_USBSTS_HCH        (1 << 12)
43
44 #define USB_TXFILLTUNING        0x154
45 #define USB_FIFO_TXFILL_THRES(x)   (((x) & 0x1f) << 16)
46 #define USB_FIFO_TXFILL_MASK    0x1f0000
47
48 #define USB_ASYNCLISTADDR       0x148
49
50 #define ICUSB_CTRL              0x15c
51
52 #define USB_PORTSC              0x174
53 #define   USB_PORTSC_WKOC       (1 << 22)
54 #define   USB_PORTSC_WKDS       (1 << 21)
55 #define   USB_PORTSC_WKCN       (1 << 20)
56 #define   USB_PORTSC_PTC(x)     (((x) & 0xf) << 16)
57 #define   USB_PORTSC_PP (1 << 12)
58 #define   USB_PORTSC_LS(x) (((x) & 0x3) << 10)
59 #define   USB_PORTSC_SUSP       (1 << 7)
60 #define   USB_PORTSC_RESUME     (1 << 6)
61 #define   USB_PORTSC_OCC        (1 << 5)
62 #define   USB_PORTSC_PEC        (1 << 3)
63 #define   USB_PORTSC_PE         (1 << 2)
64 #define   USB_PORTSC_CSC        (1 << 1)
65 #define   USB_PORTSC_CCS        (1 << 0)
66 #define   USB_PORTSC_RWC_BITS (USB_PORTSC_CSC | USB_PORTSC_PEC | USB_PORTSC_OCC)
67
68 #define HOSTPC1_DEVLC           0x1b4
69 #define   HOSTPC1_DEVLC_PHCD            (1 << 22)
70 #define   HOSTPC1_DEVLC_PTS(x)          (((x) & 0x7) << 29)
71 #define   HOSTPC1_DEVLC_PTS_MASK        7
72 #define   HOSTPC1_DEVLC_PTS_HSIC        4
73 #define   HOSTPC1_DEVLC_STS             (1 << 28)
74 #define   HOSTPC1_DEVLC_PSPD(x)         (((x) & 0x3) << 25)
75 #define   HOSTPC1_DEVLC_PSPD_MASK       3
76 #define   HOSTPC1_DEVLC_PSPD_HIGH_SPEED 2
77
78 #define USB_USBMODE             0x1f8
79 #define   USB_USBMODE_MASK              (3 << 0)
80 #define   USB_USBMODE_HOST              (3 << 0)
81 #define   USB_USBMODE_DEVICE            (2 << 0)
82
83 #define USB_SUSP_CTRL           0x400
84 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
85 #define   USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
86 #define   USB_SUSP_CLR                  (1 << 5)
87 #define   USB_PHY_CLK_VALID             (1 << 7)
88 #define   USB_PHY_CLK_VALID_INT_ENB     (1 << 9)
89 #define   USB_PHY_CLK_VALID_INT_STS     (1 << 8)
90 #define   UTMIP_RESET                   (1 << 11)
91 #define   UTMIP_PHY_ENABLE              (1 << 12)
92 #define   ULPI_PHY_ENABLE               (1 << 13)
93 #define   UHSIC_RESET                   (1 << 14)
94 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
95 #define   UHSIC_PHY_ENABLE              (1 << 19)
96 #define   ULPIS2S_SLV0_RESET            (1 << 20)
97 #define   ULPIS2S_SLV1_RESET            (1 << 21)
98 #define   ULPIS2S_LINE_RESET            (1 << 22)
99 #define   ULPI_PADS_RESET               (1 << 23)
100 #define   ULPI_PADS_CLKEN_RESET         (1 << 24)
101
102 #define USB_PHY_VBUS_WAKEUP_ID  0x408
103 #define   VDAT_DET_INT_EN       (1 << 16)
104 #define   VDAT_DET_CHG_DET      (1 << 17)
105 #define   VDAT_DET_STS          (1 << 18)
106 #define   USB_ID_STATUS         (1 << 2)
107
108 #define ULPIS2S_CTRL            0x418
109 #define   ULPIS2S_ENA                   (1 << 0)
110 #define   ULPIS2S_SUPPORT_DISCONNECT    (1 << 2)
111 #define   ULPIS2S_PLLU_MASTER_BLASTER60 (1 << 3)
112 #define   ULPIS2S_SPARE(x)              (((x) & 0xF) << 8)
113 #define   ULPIS2S_FORCE_ULPI_CLK_OUT    (1 << 12)
114 #define   ULPIS2S_DISCON_DONT_CHECK_SE0 (1 << 13)
115 #define   ULPIS2S_SUPPORT_HS_KEEP_ALIVE (1 << 14)
116 #define   ULPIS2S_DISABLE_STP_PU        (1 << 15)
117 #define   ULPIS2S_SLV0_CLAMP_XMIT       (1 << 16)
118
119 #define ULPI_TIMING_CTRL_0      0x424
120 #define   ULPI_CLOCK_OUT_DELAY(x)       ((x) & 0x1F)
121 #define   ULPI_OUTPUT_PINMUX_BYP        (1 << 10)
122 #define   ULPI_CLKOUT_PINMUX_BYP        (1 << 11)
123 #define   ULPI_SHADOW_CLK_LOOPBACK_EN   (1 << 12)
124 #define   ULPI_SHADOW_CLK_SEL           (1 << 13)
125 #define   ULPI_CORE_CLK_SEL             (1 << 14)
126 #define   ULPI_SHADOW_CLK_DELAY(x)      (((x) & 0x1F) << 16)
127 #define   ULPI_LBK_PAD_EN               (1 << 26)
128 #define   ULPI_LBK_PAD_E_INPUT_OR       (1 << 27)
129 #define   ULPI_CLK_OUT_ENA              (1 << 28)
130 #define   ULPI_CLK_PADOUT_ENA           (1 << 29)
131
132 #define ULPI_TIMING_CTRL_1      0x428
133 #define   ULPI_DATA_TRIMMER_LOAD        (1 << 0)
134 #define   ULPI_DATA_TRIMMER_SEL(x)      (((x) & 0x7) << 1)
135 #define   ULPI_STPDIRNXT_TRIMMER_LOAD   (1 << 16)
136 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
137 #define   ULPI_DIR_TRIMMER_LOAD         (1 << 24)
138 #define   ULPI_DIR_TRIMMER_SEL(x)       (((x) & 0x7) << 25)
139
140 #define UTMIP_XCVR_CFG0         0x808
141 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
142 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
143 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
144 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
145 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
146 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
147 #define   UTMIP_XCVR_LSBIAS_SEL                 (1 << 21)
148 #define   UTMIP_XCVR_SETUP_MSB(x)               (((x) & 0x7) << 22)
149 #define   UTMIP_XCVR_HSSLEW_MSB(x)              (((x) & 0x7f) << 25)
150 #define   UTMIP_XCVR_MAX_OFFSET         2
151 #define   UTMIP_XCVR_SETUP_MAX_VALUE    0x7f
152 #define   UTMIP_XCVR_SETUP_MIN_VALUE    0
153 #define   XCVR_SETUP_MSB_CALIB(x) ((x) >> 4)
154
155 #define UTMIP_BIAS_CFG0         0x80c
156 #define   UTMIP_OTGPD                   (1 << 11)
157 #define   UTMIP_BIASPD                  (1 << 10)
158 #define   UTMIP_HSSQUELCH_LEVEL(x)      (((x) & 0x3) << 0)
159 #define   UTMIP_HSDISCON_LEVEL(x)       (((x) & 0x3) << 2)
160 #define   UTMIP_HSDISCON_LEVEL_MSB      (1 << 24)
161
162 #define UTMIP_HSRX_CFG0         0x810
163 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
164 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
165
166 #define UTMIP_HSRX_CFG1         0x814
167 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
168
169 #define UTMIP_TX_CFG0           0x820
170 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
171 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
172
173 #define UTMIP_DEBOUNCE_CFG0 0x82c
174 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
175
176 #define UTMIP_BAT_CHRG_CFG0 0x830
177 #define   UTMIP_PD_CHRG                 (1 << 0)
178 #define   UTMIP_ON_SINK_EN              (1 << 2)
179 #define   UTMIP_OP_SRC_EN               (1 << 3)
180
181 #define UTMIP_XCVR_CFG1         0x838
182 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
183 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
184 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
185 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
186
187 #define UTMIP_BIAS_CFG1         0x83c
188 #define   UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
189 #define   UTMIP_BIAS_PDTRK_POWERDOWN    (1 << 0)
190 #define   UTMIP_BIAS_PDTRK_POWERUP      (1 << 1)
191
192 #define UTMIP_MISC_CFG0         0x824
193 #define   UTMIP_DPDM_OBSERVE            (1 << 26)
194 #define   UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
195 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J   UTMIP_DPDM_OBSERVE_SEL(0xf)
196 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K   UTMIP_DPDM_OBSERVE_SEL(0xe)
197 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
198 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
199 #define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
200 #define   FORCE_PULLDN_DM       (1 << 8)
201 #define   FORCE_PULLDN_DP       (1 << 9)
202 #define   COMB_TERMS            (1 << 0)
203 #define   ALWAYS_FREE_RUNNING_TERMS (1 << 1)
204
205 #define UTMIP_SPARE_CFG0        0x834
206 #define   FUSE_SETUP_SEL                (1 << 3)
207 #define   FUSE_ATERM_SEL                (1 << 4)
208
209 #define UTMIP_PMC_WAKEUP0               0x84c
210 #define   EVENT_INT_ENB                 (1 << 0)
211
212 #define UTMIP_BIAS_STS0                 0x840
213 #define   UTMIP_RCTRL_VAL(x)            (((x) & 0xffff) << 0)
214 #define   UTMIP_TCTRL_VAL(x)            (((x) & (0xffff << 16)) >> 16)
215
216 #define UHSIC_PLL_CFG1                          0xc04
217 #define   UHSIC_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
218 #define   UHSIC_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 14)
219
220 #define UHSIC_HSRX_CFG0                         0xc08
221 #define   UHSIC_ELASTIC_UNDERRUN_LIMIT(x)       (((x) & 0x1f) << 2)
222 #define   UHSIC_ELASTIC_OVERRUN_LIMIT(x)        (((x) & 0x1f) << 8)
223 #define   UHSIC_IDLE_WAIT(x)                    (((x) & 0x1f) << 13)
224
225 #define UHSIC_HSRX_CFG1                         0xc0c
226 #define   UHSIC_HS_SYNC_START_DLY(x)            (((x) & 0x1f) << 1)
227
228 #define UHSIC_TX_CFG0                           0xc10
229 #define UHSIC_HS_READY_WAIT_FOR_VALID   (1 << 9)
230 #define UHSIC_MISC_CFG0                         0xc14
231 #define   UHSIC_SUSPEND_EXIT_ON_EDGE            (1 << 7)
232 #define   UHSIC_DETECT_SHORT_CONNECT            (1 << 8)
233 #define   UHSIC_FORCE_XCVR_MODE                 (1 << 15)
234 #define   UHSIC_DISABLE_BUSRESET                (1 << 20)
235 #define UHSIC_MISC_CFG1                         0xc18
236 #define   UHSIC_PLLU_STABLE_COUNT(x)            (((x) & 0xfff) << 2)
237
238 #define UHSIC_PADS_CFG0                         0xc1c
239 #define   UHSIC_TX_RTUNEN                       0xf000
240 #define   UHSIC_TX_RTUNE(x)                     (((x) & 0xf) << 12)
241
242 #define UHSIC_PADS_CFG1                         0xc20
243 #define   UHSIC_PD_BG                           (1 << 2)
244 #define   UHSIC_PD_TX                           (1 << 3)
245 #define   UHSIC_PD_TRK                          (1 << 4)
246 #define   UHSIC_PD_RX                           (1 << 5)
247 #define   UHSIC_PD_ZI                           (1 << 6)
248 #define   UHSIC_RX_SEL                          (1 << 7)
249 #define   UHSIC_RPD_DATA                        (1 << 9)
250 #define   UHSIC_RPD_STROBE                      (1 << 10)
251 #define   UHSIC_RPU_DATA                        (1 << 11)
252 #define   UHSIC_RPU_STROBE                      (1 << 12)
253
254 #define UHSIC_STAT_CFG0                 0xc28
255 #define   UHSIC_CONNECT_DETECT                  (1 << 0)
256
257 #define PMC_USB_DEBOUNCE                        0xec
258 #define   UTMIP_LINE_DEB_CNT(x)                 (((x) & 0xf) << 16)
259
260 #define PMC_USB_AO                              0xf0
261 #define PMC_POWER_DOWN_MASK                     0xffff
262 #define HSIC_RESERVED_P0                        (3 << 14)
263 #define HSIC_STOBE_VAL_PD_P0                    (1 << 13)
264 #define HSIC_DATA_VAL_PD_P0                     (1 << 12)
265 #define USB_ID_PD(inst)                         (1 << ((4*(inst))+3))
266 #define VBUS_WAKEUP_PD(inst)                    (1 << ((4*(inst))+2))
267 #define   USBON_VAL_PD(inst)                    (1 << ((4*(inst))+1))
268 #define   USBON_VAL_PD_P2                       (1 << 9)
269 #define   USBON_VAL_PD_P1                       (1 << 5)
270 #define   USBON_VAL_PD_P0                       (1 << 1)
271 #define   USBOP_VAL_PD(inst)                    (1 << (4*(inst)))
272 #define   USBOP_VAL_PD_P2                       (1 << 8)
273 #define   USBOP_VAL_PD_P1                       (1 << 4)
274 #define   USBOP_VAL_PD_P0                       (1 << 0)
275 #define   PMC_USB_AO_PD_P2                      (0xf << 8)
276 #define   PMC_USB_AO_ID_PD_P0                   (1 << 3)
277 #define   PMC_USB_AO_VBUS_WAKEUP_PD_P0  (1 << 2)
278
279 #define PMC_TRIGGERS                    0x1ec
280 #define   UTMIP_CLR_WALK_PTR(inst)      (1 << (inst))
281 #define   UTMIP_CLR_WALK_PTR_P2         (1 << 2)
282 #define   UTMIP_CLR_WALK_PTR_P1         (1 << 1)
283 #define   UTMIP_CLR_WALK_PTR_P0         (1 << 0)
284 #define   UTMIP_CAP_CFG(inst)   (1 << ((inst)+4))
285 #define   UTMIP_CAP_CFG_P2              (1 << 6)
286 #define   UTMIP_CAP_CFG_P1              (1 << 5)
287 #define   UTMIP_CAP_CFG_P0              (1 << 4)
288 #define   UTMIP_CLR_WAKE_ALARM(inst)            (1 << ((inst)+12))
289 #define   UTMIP_CLR_WAKE_ALARM_P2       (1 << 14)
290
291 #define PMC_PAD_CFG             (0x1f4)
292
293 #define PMC_UTMIP_TERM_PAD_CFG  0x1f8
294 #define   PMC_TCTRL_VAL(x)      (((x) & 0x1f) << 5)
295 #define   PMC_RCTRL_VAL(x)      (((x) & 0x1f) << 0)
296
297 #define UHSIC_SLEEPWALK_REG             0x210
298 #define UHSIC_DATA_RPD_D                (1 << 25)
299 #define UHSIC_STRB_RPD_D                (1 << 24)
300 #define UHSIC_DATA_RPD_C                (1 << 17)
301 #define UHSIC_STRB_RPD_C                (1 << 16)
302 #define UHSIC_DATA_RPD_B                (1 << 9)
303 #define UHSIC_STRB_RPD_B                (1 << 8)
304 #define UHSIC_DATA_RPD_A                (1 << 1)
305 #define UHSIC_STRB_RPD_A                (1 << 0)
306
307 #define PMC_SLEEP_CFG                   0x1fc
308 #define   UTMIP_TCTRL_USE_PMC(inst) (1 << ((8*(inst))+3))
309 #define   UTMIP_TCTRL_USE_PMC_P2                (1 << 19)
310 #define   UTMIP_TCTRL_USE_PMC_P1                (1 << 11)
311 #define   UTMIP_TCTRL_USE_PMC_P0                (1 << 3)
312 #define   UTMIP_RCTRL_USE_PMC(inst) (1 << ((8*(inst))+2))
313 #define   UTMIP_RCTRL_USE_PMC_P2                (1 << 18)
314 #define   UTMIP_RCTRL_USE_PMC_P1                (1 << 10)
315 #define   UTMIP_RCTRL_USE_PMC_P0                (1 << 2)
316 #define   UTMIP_FSLS_USE_PMC(inst)      (1 << ((8*(inst))+1))
317 #define   UTMIP_FSLS_USE_PMC_P2         (1 << 17)
318 #define   UTMIP_FSLS_USE_PMC_P1         (1 << 9)
319 #define   UTMIP_FSLS_USE_PMC_P0         (1 << 1)
320 #define   UTMIP_MASTER_ENABLE(inst) (1 << (8*(inst)))
321 #define   UTMIP_MASTER_ENABLE_P2                (1 << 16)
322 #define   UTMIP_MASTER_ENABLE_P1                (1 << 8)
323 #define   UTMIP_MASTER_ENABLE_P0                (1 << 0)
324 #define UHSIC_MASTER_ENABLE_P0          (1 << 24)
325 #define UHSIC_WAKE_VAL_P0(x)            (((x) & 0xf) << 28)
326
327 #define PMC_SLEEPWALK_CFG               0x200
328 #define   UTMIP_LINEVAL_WALK_EN(inst) (1 << ((8*(inst))+7))
329 #define   UTMIP_LINEVAL_WALK_EN_P2      (1 << 23)
330 #define   UTMIP_LINEVAL_WALK_EN_P1      (1 << 15)
331 #define   UTMIP_LINEVAL_WALK_EN_P0      (1 << 7)
332 #define   UTMIP_WAKE_VAL(inst, x) (((x) & 0xf) << ((8*(inst))+4))
333 #define   UTMIP_WAKE_VAL_P2(x)          (((x) & 0xf) << 20)
334 #define   UTMIP_WAKE_VAL_P1(x)          (((x) & 0xf) << 12)
335 #define   UTMIP_WAKE_VAL_P0(x)          (((x) & 0xf) << 4)
336 #define   WAKE_VAL_NONE         0xc
337 #define   WAKE_VAL_ANY                  0xF
338 #define   WAKE_VAL_FSJ                  0x2
339 #define   WAKE_VAL_FSK                  0x1
340 #define   WAKE_VAL_SE0                  0x0
341
342 #define PMC_SLEEPWALK_REG(inst)         (0x204 + (4*(inst)))
343 #define   UTMIP_USBOP_RPD_A     (1 << 0)
344 #define   UTMIP_USBON_RPD_A     (1 << 1)
345 #define   UTMIP_AP_A                    (1 << 4)
346 #define   UTMIP_AN_A                    (1 << 5)
347 #define   UTMIP_HIGHZ_A         (1 << 6)
348 #define   UTMIP_USBOP_RPD_B     (1 << 8)
349 #define   UTMIP_USBON_RPD_B     (1 << 9)
350 #define   UTMIP_AP_B                    (1 << 12)
351 #define   UTMIP_AN_B                    (1 << 13)
352 #define   UTMIP_HIGHZ_B         (1 << 14)
353 #define   UTMIP_USBOP_RPD_C     (1 << 16)
354 #define   UTMIP_USBON_RPD_C     (1 << 17)
355 #define   UTMIP_AP_C            (1 << 20)
356 #define   UTMIP_AN_C            (1 << 21)
357 #define   UTMIP_HIGHZ_C         (1 << 22)
358 #define   UTMIP_USBOP_RPD_D     (1 << 24)
359 #define   UTMIP_USBON_RPD_D     (1 << 25)
360 #define   UTMIP_AP_D            (1 << 28)
361 #define   UTMIP_AN_D            (1 << 29)
362 #define   UTMIP_HIGHZ_D         (1 << 30)
363
364 #define UTMIP_UHSIC_STATUS              0x214
365 #define   UTMIP_WALK_PTR_VAL(inst)      (0x3 << ((inst)*2))
366 #define   UTMIP_USBOP_VAL(inst)         (1 << ((2*(inst)) + 8))
367 #define   UTMIP_USBOP_VAL_P2            (1 << 12)
368 #define   UTMIP_USBOP_VAL_P1            (1 << 10)
369 #define   UTMIP_USBOP_VAL_P0            (1 << 8)
370 #define   UTMIP_USBON_VAL(inst)         (1 << ((2*(inst)) + 9))
371 #define   UTMIP_USBON_VAL_P2            (1 << 13)
372 #define   UTMIP_USBON_VAL_P1            (1 << 11)
373 #define   UTMIP_USBON_VAL_P0            (1 << 9)
374 #define   UTMIP_WAKE_ALARM(inst)                (1 << ((inst) + 16))
375 #define   UTMIP_WAKE_ALARM_P2   (1 << 18)
376 #define   UTMIP_WAKE_ALARM_P1   (1 << 17)
377 #define   UTMIP_WAKE_ALARM_P0   (1 << 16)
378 #define   UTMIP_WALK_PTR(inst)  (1 << ((inst)*2))
379 #define   UTMIP_WALK_PTR_P2     (1 << 4)
380 #define   UTMIP_WALK_PTR_P1     (1 << 2)
381 #define   UTMIP_WALK_PTR_P0     (1 << 0)
382
383 #define USB1_PREFETCH_ID               6
384 #define USB2_PREFETCH_ID               18
385 #define USB3_PREFETCH_ID               17
386
387 #define PMC_UTMIP_UHSIC_FAKE            0x218
388 #define   USBON_VAL(inst)       (1 << ((4*(inst))+1))
389 #define   USBON_VAL_P2                  (1 << 9)
390 #define   USBON_VAL_P1                  (1 << 5)
391 #define   USBON_VAL_P0                  (1 << 1)
392 #define   USBOP_VAL(inst)       (1 << (4*(inst)))
393 #define   USBOP_VAL_P2                  (1 << 8)
394 #define   USBOP_VAL_P1                  (1 << 4)
395 #define   USBOP_VAL_P0                  (1 << 0)
396
397 #define PMC_UTMIP_BIAS_MASTER_CNTRL 0x30c
398 #define   BIAS_MASTER_PROG_VAL          (1 << 1)
399
400 #define PMC_UTMIP_MASTER_CONFIG         0x310
401 #define   UTMIP_PWR(inst)               (1 << (inst))
402
403 #define FUSE_USB_CALIB_0                0x1F0
404 #define   FUSE_USB_CALIB_XCVR_SETUP(x)  (((x) & 0x7F) << 0)
405
406 /* These values (in milli second) are taken from the battery charging spec */
407 #define TDP_SRC_ON_MS    100
408 #define TDPSRC_CON_MS    40
409
410 #ifdef DEBUG
411 #define DBG(stuff...)   pr_info("tegra3_usb_phy: " stuff)
412 #else
413 #define DBG(stuff...)   do {} while (0)
414 #endif
415
416 static u32 utmip_rctrl_val, utmip_tctrl_val;
417 static DEFINE_SPINLOCK(utmip_pad_lock);
418 static int utmip_pad_count;
419
420 static struct tegra_xtal_freq utmip_freq_table[] = {
421         {
422                 .freq = 12000000,
423                 .enable_delay = 0x02,
424                 .stable_count = 0x2F,
425                 .active_delay = 0x04,
426                 .xtal_freq_count = 0x76,
427                 .debounce = 0x7530,
428                 .pdtrk_count = 5,
429         },
430         {
431                 .freq = 13000000,
432                 .enable_delay = 0x02,
433                 .stable_count = 0x33,
434                 .active_delay = 0x05,
435                 .xtal_freq_count = 0x7F,
436                 .debounce = 0x7EF4,
437                 .pdtrk_count = 5,
438         },
439         {
440                 .freq = 19200000,
441                 .enable_delay = 0x03,
442                 .stable_count = 0x4B,
443                 .active_delay = 0x06,
444                 .xtal_freq_count = 0xBB,
445                 .debounce = 0xBB80,
446                 .pdtrk_count = 7,
447         },
448         {
449                 .freq = 26000000,
450                 .enable_delay = 0x04,
451                 .stable_count = 0x66,
452                 .active_delay = 0x09,
453                 .xtal_freq_count = 0xFE,
454                 .debounce = 0xFDE8,
455                 .pdtrk_count = 9,
456         },
457 };
458
459 static struct tegra_xtal_freq uhsic_freq_table[] = {
460         {
461                 .freq = 12000000,
462                 .enable_delay = 0x02,
463                 .stable_count = 0x2F,
464                 .active_delay = 0x0,
465                 .xtal_freq_count = 0x1CA,
466         },
467         {
468                 .freq = 13000000,
469                 .enable_delay = 0x02,
470                 .stable_count = 0x33,
471                 .active_delay = 0x0,
472                 .xtal_freq_count = 0x1F0,
473         },
474         {
475                 .freq = 19200000,
476                 .enable_delay = 0x03,
477                 .stable_count = 0x4B,
478                 .active_delay = 0x0,
479                 .xtal_freq_count = 0x2DD,
480         },
481         {
482                 .freq = 26000000,
483                 .enable_delay = 0x04,
484                 .stable_count = 0x66,
485                 .active_delay = 0x0,
486                 .xtal_freq_count = 0x3E0,
487         },
488 };
489
490 static void usb_phy_fence_read(struct tegra_usb_phy *phy)
491 {
492         /* Fence read for coherency of AHB master intiated writes */
493         if (phy->inst == 0)
494                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB1_PREFETCH_ID));
495         else if (phy->inst == 1)
496                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB2_PREFETCH_ID));
497         else if (phy->inst == 2)
498                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB3_PREFETCH_ID));
499
500         return;
501 }
502
503 static void utmip_setup_pmc_wake_detect(struct tegra_usb_phy *phy)
504 {
505         unsigned long val, pmc_pad_cfg_val;
506         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
507         unsigned  int inst = phy->inst;
508         void __iomem *base = phy->regs;
509         bool port_connected;
510         enum usb_phy_port_speed port_speed;
511
512         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
513
514         /* check for port connect status */
515         val = readl(base + USB_PORTSC);
516         port_connected = val & USB_PORTSC_CCS;
517
518         if (!port_connected)
519                 return;
520
521         port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
522                 HOSTPC1_DEVLC_PSPD_MASK;
523         /*Set PMC MASTER bits to do the following
524         * a. Take over the UTMI drivers
525         * b. set up such that it will take over resume
526         *        if remote wakeup is detected
527         * Prepare PMC to take over suspend-wake detect-drive resume until USB
528         * controller ready
529         */
530
531         /* disable master enable in PMC */
532         val = readl(pmc_base + PMC_SLEEP_CFG);
533         val &= ~UTMIP_MASTER_ENABLE(inst);
534         writel(val, pmc_base + PMC_SLEEP_CFG);
535
536         /* UTMIP_PWR_PX=1 for power savings mode */
537         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
538         val |= UTMIP_PWR(inst);
539         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
540
541         /* config debouncer */
542         val = readl(pmc_base + PMC_USB_DEBOUNCE);
543         val &= ~UTMIP_LINE_DEB_CNT(~0);
544         val |= UTMIP_LINE_DEB_CNT(4);
545         writel(val, pmc_base + PMC_USB_DEBOUNCE);
546
547         /* Make sure nothing is happening on the line with respect to PMC */
548         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
549         val &= ~USBOP_VAL(inst);
550         val &= ~USBON_VAL(inst);
551         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
552
553         /* Make sure wake value for line is none */
554         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
555         val &= ~UTMIP_LINEVAL_WALK_EN(inst);
556         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
557         val = readl(pmc_base + PMC_SLEEP_CFG);
558         val &= ~UTMIP_WAKE_VAL(inst, ~0);
559         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
560         writel(val, pmc_base + PMC_SLEEP_CFG);
561
562         /* turn off pad detectors */
563         val = readl(pmc_base + PMC_USB_AO);
564         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
565         writel(val, pmc_base + PMC_USB_AO);
566
567         /* Remove fake values and make synchronizers work a bit */
568         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
569         val &= ~USBOP_VAL(inst);
570         val &= ~USBON_VAL(inst);
571         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
572
573         /* Enable which type of event can trigger a walk,
574         in this case usb_line_wake */
575         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
576         val |= UTMIP_LINEVAL_WALK_EN(inst);
577         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
578
579         /* Enable which type of event can trigger a walk,
580         * in this case usb_line_wake */
581         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
582         val |= UTMIP_LINEVAL_WALK_EN(inst);
583         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
584
585         /* Clear the walk pointers and wake alarm */
586         val = readl(pmc_base + PMC_TRIGGERS);
587         val |= UTMIP_CLR_WAKE_ALARM(inst) | UTMIP_CLR_WALK_PTR(inst);
588         writel(val, pmc_base + PMC_TRIGGERS);
589
590
591         /* Capture FS/LS pad configurations */
592         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
593         val = readl(pmc_base + PMC_TRIGGERS);
594         val |= UTMIP_CAP_CFG(inst);
595         writel(val, pmc_base + PMC_TRIGGERS);
596         udelay(1);
597         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
598
599         /* BIAS MASTER_ENABLE=0 */
600         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
601         val &= ~BIAS_MASTER_PROG_VAL;
602         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
603
604         /* program walk sequence, maintain a J, followed by a driven K
605         * to signal a resume once an wake event is detected */
606         val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
607         val &= ~UTMIP_AP_A;
608         val |= UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_AN_A |UTMIP_HIGHZ_A |
609                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_AP_B | UTMIP_AN_B |
610                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_AP_C | UTMIP_AN_C |
611                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_AP_D | UTMIP_AN_D;
612         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
613
614         if (port_speed == USB_PHY_PORT_SPEED_LOW) {
615                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
616                 val &= ~(UTMIP_AN_B | UTMIP_HIGHZ_B | UTMIP_AN_C |
617                         UTMIP_HIGHZ_C | UTMIP_AN_D | UTMIP_HIGHZ_D);
618                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
619         } else {
620                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
621                 val &= ~(UTMIP_AP_B | UTMIP_HIGHZ_B | UTMIP_AP_C |
622                         UTMIP_HIGHZ_C | UTMIP_AP_D | UTMIP_HIGHZ_D);
623                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
624         }
625
626         /* turn on pad detectors */
627         val = readl(pmc_base + PMC_USB_AO);
628         val &= ~(USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
629         writel(val, pmc_base + PMC_USB_AO);
630
631         /* Add small delay before usb detectors provide stable line values */
632         mdelay(1);
633
634         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
635         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
636         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
637         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
638
639         phy->remote_wakeup = false;
640
641         /* Turn over pad configuration to PMC  for line wake events*/
642         val = readl(pmc_base + PMC_SLEEP_CFG);
643         val &= ~UTMIP_WAKE_VAL(inst, ~0);
644         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_ANY);
645         val |= UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst);
646         val |= UTMIP_MASTER_ENABLE(inst) | UTMIP_FSLS_USE_PMC(inst);
647         writel(val, pmc_base + PMC_SLEEP_CFG);
648
649         val = readl(base + UTMIP_PMC_WAKEUP0);
650         val |= EVENT_INT_ENB;
651         writel(val, base + UTMIP_PMC_WAKEUP0);
652 }
653
654 static void utmip_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy)
655 {
656         unsigned long val;
657         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
658         unsigned  int inst = phy->inst;
659         void __iomem *base = phy->regs;
660
661         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
662
663         val = readl(pmc_base + PMC_SLEEP_CFG);
664         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
665         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
666         writel(val, pmc_base + PMC_SLEEP_CFG);
667
668         val = readl(pmc_base + PMC_TRIGGERS);
669         val |= UTMIP_CLR_WAKE_ALARM(inst) | UTMIP_CLR_WALK_PTR(inst);
670         writel(val, pmc_base + PMC_TRIGGERS);
671
672         val = readl(base + UTMIP_PMC_WAKEUP0);
673         val &= ~EVENT_INT_ENB;
674         writel(val, base + UTMIP_PMC_WAKEUP0);
675
676         /* Disable PMC master mode by clearing MASTER_EN */
677         val = readl(pmc_base + PMC_SLEEP_CFG);
678         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
679                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
680         writel(val, pmc_base + PMC_SLEEP_CFG);
681
682         val = readl(pmc_base + PMC_TRIGGERS);
683         val &= ~UTMIP_CAP_CFG(inst);
684         writel(val, pmc_base + PMC_TRIGGERS);
685
686         /* turn off pad detectors */
687         val = readl(pmc_base + PMC_USB_AO);
688         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
689         writel(val, pmc_base + PMC_USB_AO);
690
691         phy->remote_wakeup = false;
692 }
693
694 bool utmi_phy_remotewake_detected(struct tegra_usb_phy *phy)
695 {
696         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
697         void __iomem *base = phy->regs;
698         unsigned  int inst = phy->inst;
699         u32 val;
700
701         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
702         val = readl(base + UTMIP_PMC_WAKEUP0);
703         if (val & EVENT_INT_ENB) {
704                 val = readl(pmc_base + UTMIP_UHSIC_STATUS);
705                 if (UTMIP_WAKE_ALARM(inst) & val) {
706                         val = readl(pmc_base + PMC_SLEEP_CFG);
707                         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
708                         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
709                         writel(val, pmc_base + PMC_SLEEP_CFG);
710
711                         val = readl(pmc_base + PMC_TRIGGERS);
712                         val |= UTMIP_CLR_WAKE_ALARM(inst) |
713                                 UTMIP_CLR_WALK_PTR(inst);
714                         writel(val, pmc_base + PMC_TRIGGERS);
715
716                         val = readl(base + UTMIP_PMC_WAKEUP0);
717                         val &= ~EVENT_INT_ENB;
718                         writel(val, base + UTMIP_PMC_WAKEUP0);
719                         phy->remote_wakeup = true;
720                         return true;
721                 }
722         }
723         return false;
724 }
725
726 static void utmi_phy_enable_trking_data(struct tegra_usb_phy *phy)
727 {
728         void __iomem *base = IO_ADDRESS(TEGRA_USB_BASE);
729         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
730         static bool init_done = false;
731         u32 val;
732
733         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
734
735         /* Should be done only once after system boot */
736         if (init_done)
737                 return;
738
739         clk_enable(phy->utmi_pad_clk);
740         /* Bias pad MASTER_ENABLE=1 */
741         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
742         val |= BIAS_MASTER_PROG_VAL;
743         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
744
745         /* Setting the tracking length time */
746         val = readl(base + UTMIP_BIAS_CFG1);
747         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
748         val |= UTMIP_BIAS_PDTRK_COUNT(5);
749         writel(val, base + UTMIP_BIAS_CFG1);
750
751         /* Bias PDTRK is Shared and MUST be done from USB1 ONLY, PD_TRK=0 */
752         val = readl(base + UTMIP_BIAS_CFG1);
753         val &= ~UTMIP_BIAS_PDTRK_POWERDOWN;
754         writel(val, base + UTMIP_BIAS_CFG1);
755
756         val = readl(base + UTMIP_BIAS_CFG1);
757         val |= UTMIP_BIAS_PDTRK_POWERUP;
758         writel(val, base + UTMIP_BIAS_CFG1);
759
760         /* Wait for 25usec */
761         udelay(25);
762
763         /* Bias pad MASTER_ENABLE=0 */
764         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
765         val &= ~BIAS_MASTER_PROG_VAL;
766         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
767
768         /* Wait for 1usec */
769         udelay(1);
770
771         /* Bias pad MASTER_ENABLE=1 */
772         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
773         val |= BIAS_MASTER_PROG_VAL;
774         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
775
776         /* Read RCTRL and TCTRL from UTMIP space */
777         val = readl(base + UTMIP_BIAS_STS0);
778         utmip_rctrl_val = ffz(UTMIP_RCTRL_VAL(val));
779         utmip_tctrl_val = ffz(UTMIP_TCTRL_VAL(val));
780
781         /* PD_TRK=1 */
782         val = readl(base + UTMIP_BIAS_CFG1);
783         val |= UTMIP_BIAS_PDTRK_POWERDOWN;
784         writel(val, base + UTMIP_BIAS_CFG1);
785
786         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
787         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
788         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
789         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
790         clk_disable(phy->utmi_pad_clk);
791         init_done = true;
792 }
793
794 static void utmip_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy)
795 {
796         unsigned long val;
797         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
798         unsigned  int inst = phy->inst;
799
800         /* power down UTMIP interfaces */
801         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
802         val |= UTMIP_PWR(inst);
803         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
804
805         /* setup sleep walk usb controller */
806         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
807                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
808                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
809                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
810         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
811
812         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
813         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
814         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
815         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
816
817         /* Turn over pad configuration to PMC */
818         val = readl(pmc_base + PMC_SLEEP_CFG);
819         val &= ~UTMIP_WAKE_VAL(inst, ~0);
820         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE) |
821                 UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
822                 UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst);
823         writel(val, pmc_base + PMC_SLEEP_CFG);
824 }
825
826 static void utmip_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
827 {
828         unsigned long val;
829         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
830         unsigned  int inst = phy->inst;
831
832         /* Disable PMC master mode by clearing MASTER_EN */
833         val = readl(pmc_base + PMC_SLEEP_CFG);
834         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
835                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
836         writel(val, pmc_base + PMC_SLEEP_CFG);
837         mdelay(1);
838 }
839
840 static void uhsic_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy)
841 {
842         unsigned long val;
843         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
844
845         /* turn on pad detectors for HSIC*/
846         val = readl(pmc_base + PMC_USB_AO);
847         val |= (HSIC_RESERVED_P0 | HSIC_STOBE_VAL_PD_P0 | HSIC_DATA_VAL_PD_P0);
848         writel(val, pmc_base + PMC_USB_AO);
849
850         /* enable pull downs on HSIC PMC */
851         val = UHSIC_STRB_RPD_A | UHSIC_DATA_RPD_A | UHSIC_STRB_RPD_B |
852                 UHSIC_DATA_RPD_B | UHSIC_STRB_RPD_C | UHSIC_DATA_RPD_C |
853                 UHSIC_STRB_RPD_D | UHSIC_DATA_RPD_D;
854         writel(val, pmc_base + UHSIC_SLEEPWALK_REG);
855
856         /* Turn over pad configuration to PMC */
857         val = readl(pmc_base + PMC_SLEEP_CFG);
858         val &= ~UHSIC_WAKE_VAL_P0(~0);
859         val |= UHSIC_WAKE_VAL_P0(WAKE_VAL_NONE) | UHSIC_MASTER_ENABLE_P0;
860         writel(val, pmc_base + PMC_SLEEP_CFG);
861 }
862
863 static void uhsic_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
864 {
865         unsigned long val;
866         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
867
868         /* turn on pad detectors for HSIC*/
869         val = readl(pmc_base + PMC_USB_AO);
870         val &= ~(HSIC_RESERVED_P0 | HSIC_STOBE_VAL_PD_P0 | HSIC_DATA_VAL_PD_P0);
871         writel(val, pmc_base + PMC_USB_AO);
872
873         /* Disable PMC master mode by clearing MASTER_EN */
874         val = readl(pmc_base + PMC_SLEEP_CFG);
875         val &= ~(UHSIC_MASTER_ENABLE_P0);
876         writel(val, pmc_base + PMC_SLEEP_CFG);
877         mdelay(1);
878 }
879
880 static void usb_phy_power_down_pmc(void)
881 {
882         unsigned long val;
883         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
884
885         /* power down all 3 UTMIP interfaces */
886         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
887         val |= UTMIP_PWR(0) | UTMIP_PWR(1) | UTMIP_PWR(2);
888         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
889
890         /* turn on pad detectors */
891         writel(PMC_POWER_DOWN_MASK, pmc_base + PMC_USB_AO);
892
893         /* setup sleep walk fl all 3 usb controllers */
894         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
895                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
896                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
897                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
898         writel(val, pmc_base + PMC_SLEEPWALK_REG(0));
899         writel(val, pmc_base + PMC_SLEEPWALK_REG(1));
900         writel(val, pmc_base + PMC_SLEEPWALK_REG(2));
901
902         /* enable pull downs on HSIC PMC */
903         val = UHSIC_STRB_RPD_A | UHSIC_DATA_RPD_A | UHSIC_STRB_RPD_B |
904                 UHSIC_DATA_RPD_B | UHSIC_STRB_RPD_C | UHSIC_DATA_RPD_C |
905                 UHSIC_STRB_RPD_D | UHSIC_DATA_RPD_D;
906         writel(val, pmc_base + UHSIC_SLEEPWALK_REG);
907
908         /* Turn over pad configuration to PMC */
909         val = readl(pmc_base + PMC_SLEEP_CFG);
910         val &= ~UTMIP_WAKE_VAL(0, ~0);
911         val &= ~UTMIP_WAKE_VAL(1, ~0);
912         val &= ~UTMIP_WAKE_VAL(2, ~0);
913         val &= ~UHSIC_WAKE_VAL_P0(~0);
914         val |= UTMIP_WAKE_VAL(0, WAKE_VAL_NONE) | UHSIC_WAKE_VAL_P0(WAKE_VAL_NONE) |
915         UTMIP_WAKE_VAL(1, WAKE_VAL_NONE) | UTMIP_WAKE_VAL(2, WAKE_VAL_NONE) |
916         UTMIP_RCTRL_USE_PMC(0) | UTMIP_RCTRL_USE_PMC(1) | UTMIP_RCTRL_USE_PMC(2) |
917         UTMIP_TCTRL_USE_PMC(0) | UTMIP_TCTRL_USE_PMC(1) | UTMIP_TCTRL_USE_PMC(2) |
918         UTMIP_FSLS_USE_PMC(0) | UTMIP_FSLS_USE_PMC(1) | UTMIP_FSLS_USE_PMC(2) |
919         UTMIP_MASTER_ENABLE(0) | UTMIP_MASTER_ENABLE(1) | UTMIP_MASTER_ENABLE(2) |
920         UHSIC_MASTER_ENABLE_P0;
921         writel(val, pmc_base + PMC_SLEEP_CFG);
922 }
923
924 static int usb_phy_bringup_host_controller(struct tegra_usb_phy *phy)
925 {
926         unsigned long val;
927         void __iomem *base = phy->regs;
928
929         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
930         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n",
931                 readl(base + USB_USBSTS), readl(base + USB_PORTSC),
932                                                         phy->port_speed);
933
934         /* Enable Port Power */
935         val = readl(base + USB_PORTSC);
936         val |= USB_PORTSC_PP;
937         writel(val, base + USB_PORTSC);
938         udelay(10);
939
940         /* Check if the phy resume from LP0. When the phy resume from LP0
941          * USB register will be reset.to zero */
942         if (!readl(base + USB_ASYNCLISTADDR)) {
943                 /* Program the field PTC based on the saved speed mode */
944                 val = readl(base + USB_PORTSC);
945                 val &= ~USB_PORTSC_PTC(~0);
946                 if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH)
947                         val |= USB_PORTSC_PTC(5);
948                 else if (phy->port_speed == USB_PHY_PORT_SPEED_FULL)
949                         val |= USB_PORTSC_PTC(6);
950                 else if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
951                         val |= USB_PORTSC_PTC(7);
952                 writel(val, base + USB_PORTSC);
953                 udelay(10);
954
955                 /* Disable test mode by setting PTC field to NORMAL_OP */
956                 val = readl(base + USB_PORTSC);
957                 val &= ~USB_PORTSC_PTC(~0);
958                 writel(val, base + USB_PORTSC);
959                 udelay(10);
960         }
961
962         /* Poll until CCS is enabled */
963         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
964                                                  USB_PORTSC_CCS, 2000)) {
965                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
966         }
967
968         /* Poll until PE is enabled */
969         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_PE,
970                                                  USB_PORTSC_PE, 2000)) {
971                 pr_err("%s: timeout waiting for USB_PORTSC_PE\n", __func__);
972         }
973
974         /* Clear the PCI status, to avoid an interrupt taken upon resume */
975         val = readl(base + USB_USBSTS);
976         val |= USB_USBSTS_PCI;
977         writel(val, base + USB_USBSTS);
978
979         /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
980         val = readl(base + USB_PORTSC);
981         if ((val & USB_PORTSC_PP) && (val & USB_PORTSC_PE)) {
982                 val |= USB_PORTSC_SUSP;
983                 writel(val, base + USB_PORTSC);
984                 /* Need a 4ms delay before the controller goes to suspend */
985                 mdelay(4);
986
987                 /* Wait until port suspend completes */
988                 if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_SUSP,
989                                                  USB_PORTSC_SUSP, 1000)) {
990                         pr_err("%s: timeout waiting for PORT_SUSPEND\n",
991                                                                 __func__);
992                 }
993         }
994
995         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
996                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
997         return 0;
998 }
999
1000 static void usb_phy_wait_for_sof(struct tegra_usb_phy *phy)
1001 {
1002         unsigned long val;
1003         void __iomem *base = phy->regs;
1004
1005         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1006
1007         val = readl(base + USB_USBSTS);
1008         writel(val, base + USB_USBSTS);
1009         udelay(20);
1010         /* wait for two SOFs */
1011         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1012                 USB_USBSTS_SRI, 2500))
1013                 pr_err("%s: timeout waiting for SOF\n", __func__);
1014
1015         val = readl(base + USB_USBSTS);
1016         writel(val, base + USB_USBSTS);
1017         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI, 0, 2500))
1018                 pr_err("%s: timeout waiting for SOF\n", __func__);
1019
1020         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1021                         USB_USBSTS_SRI, 2500))
1022                 pr_err("%s: timeout waiting for SOF\n", __func__);
1023
1024         udelay(20);
1025 }
1026
1027 static unsigned int utmi_phy_xcvr_setup_value(struct tegra_usb_phy *phy)
1028 {
1029         struct tegra_utmi_config *cfg = &phy->pdata->u_cfg.utmi;
1030         signed long val;
1031
1032         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1033
1034         if (cfg->xcvr_use_fuses) {
1035                 val = FUSE_USB_CALIB_XCVR_SETUP(
1036                                 tegra_fuse_readl(FUSE_USB_CALIB_0));
1037                 if (cfg->xcvr_setup_offset <= UTMIP_XCVR_MAX_OFFSET)
1038                         val = val + cfg->xcvr_setup_offset;
1039
1040                 if (val > UTMIP_XCVR_SETUP_MAX_VALUE) {
1041                         val = UTMIP_XCVR_SETUP_MAX_VALUE;
1042                         pr_info("%s: reset XCVR_SETUP to max value\n",
1043                                  __func__);
1044                 } else if (val < UTMIP_XCVR_SETUP_MIN_VALUE) {
1045                         val = UTMIP_XCVR_SETUP_MIN_VALUE;
1046                         pr_info("%s: reset XCVR_SETUP to min value\n",
1047                                  __func__);
1048                 }
1049         } else {
1050                 val = cfg->xcvr_setup;
1051         }
1052
1053         return (unsigned int) val;
1054 }
1055
1056 static int utmi_phy_open(struct tegra_usb_phy *phy)
1057 {
1058         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1059         unsigned long parent_rate, val;
1060         int i;
1061
1062         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1063
1064         phy->utmi_pad_clk = clk_get_sys("utmip-pad", NULL);
1065         if (IS_ERR(phy->utmi_pad_clk)) {
1066                 pr_err("%s: can't get utmip pad clock\n", __func__);
1067                 return PTR_ERR(phy->utmi_pad_clk);
1068         }
1069
1070         phy->utmi_xcvr_setup = utmi_phy_xcvr_setup_value(phy);
1071
1072         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
1073         for (i = 0; i < ARRAY_SIZE(utmip_freq_table); i++) {
1074                 if (utmip_freq_table[i].freq == parent_rate) {
1075                         phy->freq = &utmip_freq_table[i];
1076                         break;
1077                 }
1078         }
1079         if (!phy->freq) {
1080                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
1081                 return -EINVAL;
1082         }
1083
1084         /* Power-up the VBUS detector for UTMIP PHY */
1085         val = readl(pmc_base + PMC_USB_AO);
1086         val &= ~(PMC_USB_AO_VBUS_WAKEUP_PD_P0 | PMC_USB_AO_ID_PD_P0);
1087         writel((val | PMC_USB_AO_PD_P2), (pmc_base + PMC_USB_AO));
1088
1089         utmip_powerup_pmc_wake_detect(phy);
1090
1091         return 0;
1092 }
1093
1094 static void utmi_phy_close(struct tegra_usb_phy *phy)
1095 {
1096         unsigned long val;
1097         void __iomem *base = phy->regs;
1098
1099         DBG("%s inst:[%d]\n", __func__, phy->inst);
1100
1101         /* Disable PHY clock valid interrupts while going into suspend*/
1102         if (phy->pdata->u_data.host.hot_plug) {
1103                 val = readl(base + USB_SUSP_CTRL);
1104                 val &= ~USB_PHY_CLK_VALID_INT_ENB;
1105                 writel(val, base + USB_SUSP_CTRL);
1106         }
1107
1108         val = readl(base + USB_PORTSC);
1109         val |= USB_PORTSC_WKCN;
1110         writel(val, base + USB_PORTSC);
1111
1112         clk_put(phy->utmi_pad_clk);
1113 }
1114
1115 static int utmi_phy_pad_power_on(struct tegra_usb_phy *phy)
1116 {
1117         unsigned long val, flags;
1118         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1119
1120         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1121
1122         clk_enable(phy->utmi_pad_clk);
1123
1124         spin_lock_irqsave(&utmip_pad_lock, flags);
1125         utmip_pad_count++;
1126
1127         val = readl(pad_base + UTMIP_BIAS_CFG0);
1128         val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
1129         val |= UTMIP_HSSQUELCH_LEVEL(0x2) | UTMIP_HSDISCON_LEVEL(0x1) |
1130                 UTMIP_HSDISCON_LEVEL_MSB;
1131         writel(val, pad_base + UTMIP_BIAS_CFG0);
1132
1133         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1134
1135         clk_disable(phy->utmi_pad_clk);
1136
1137         return 0;
1138 }
1139
1140 static int utmi_phy_pad_power_off(struct tegra_usb_phy *phy)
1141 {
1142         unsigned long val, flags;
1143         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1144
1145         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1146
1147         clk_enable(phy->utmi_pad_clk);
1148         spin_lock_irqsave(&utmip_pad_lock, flags);
1149
1150         if (!utmip_pad_count) {
1151                 pr_err("%s: utmip pad already powered off\n", __func__);
1152                 goto out;
1153         }
1154         if (--utmip_pad_count == 0) {
1155                 val = readl(pad_base + UTMIP_BIAS_CFG0);
1156                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
1157                 val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) | UTMIP_HSDISCON_LEVEL(~0) |
1158                         UTMIP_HSDISCON_LEVEL_MSB);
1159                 writel(val, pad_base + UTMIP_BIAS_CFG0);
1160         }
1161 out:
1162         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1163         clk_disable(phy->utmi_pad_clk);
1164
1165         return 0;
1166 }
1167
1168 static int utmi_phy_irq(struct tegra_usb_phy *phy)
1169 {
1170         void __iomem *base = phy->regs;
1171         unsigned long val = 0;
1172
1173         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1174         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1175                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1176         DBG("USB_USBMODE[0x%x] USB_USBCMD[0x%x]\n",
1177                         readl(base + USB_USBMODE), readl(base + USB_USBCMD));
1178
1179         usb_phy_fence_read(phy);
1180         /* check if there is any remote wake event */
1181         if (utmi_phy_remotewake_detected(phy))
1182                 pr_info("%s: utmip remote wake detected\n", __func__);
1183
1184         if (phy->pdata->u_data.host.hot_plug) {
1185                 val = readl(base + USB_SUSP_CTRL);
1186                 if ((val  & USB_PHY_CLK_VALID_INT_STS)) {
1187                         val &= ~USB_PHY_CLK_VALID_INT_ENB |
1188                                         USB_PHY_CLK_VALID_INT_STS;
1189                         writel(val , (base + USB_SUSP_CTRL));
1190                         pr_info("%s: usb device plugged-in\n", __func__);
1191                         val = readl(base + USB_USBSTS);
1192                         if (!(val  & USB_USBSTS_PCI))
1193                                 return IRQ_NONE;
1194                         val = readl(base + USB_PORTSC);
1195                         val &= ~(USB_PORTSC_WKCN | USB_PORTSC_RWC_BITS);
1196                         writel(val , (base + USB_PORTSC));
1197                 }
1198         }
1199
1200         return IRQ_HANDLED;
1201 }
1202
1203 static void utmi_phy_enable_obs_bus(struct tegra_usb_phy *phy)
1204 {
1205         unsigned long val;
1206         void __iomem *base = phy->regs;
1207
1208         /* (2LS WAR)is not required for LS and FS devices and is only for HS */
1209         if ((phy->port_speed == USB_PHY_PORT_SPEED_LOW) ||
1210                 (phy->port_speed == USB_PHY_PORT_SPEED_FULL)) {
1211                 /* do not enable the OBS bus */
1212                 val = readl(base + UTMIP_MISC_CFG0);
1213                 val &= ~(UTMIP_DPDM_OBSERVE_SEL(~0));
1214                 writel(val, base + UTMIP_MISC_CFG0);
1215                 DBG("%s(%d) Disable OBS bus\n", __func__, __LINE__);
1216                 return;
1217         }
1218         /* Force DP/DM pulldown active for Host mode */
1219         val = readl(base + UTMIP_MISC_CFG0);
1220         val |= FORCE_PULLDN_DM | FORCE_PULLDN_DP |
1221                         COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS;
1222         writel(val, base + UTMIP_MISC_CFG0);
1223         val = readl(base + UTMIP_MISC_CFG0);
1224         val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1225         if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
1226                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
1227         else
1228                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
1229         writel(val, base + UTMIP_MISC_CFG0);
1230         udelay(1);
1231
1232         val = readl(base + UTMIP_MISC_CFG0);
1233         val |= UTMIP_DPDM_OBSERVE;
1234         writel(val, base + UTMIP_MISC_CFG0);
1235         udelay(10);
1236         DBG("%s(%d) Enable OBS bus\n", __func__, __LINE__);
1237 }
1238
1239 static void utmi_phy_disable_obs_bus(struct tegra_usb_phy *phy)
1240 {
1241         unsigned long val;
1242         void __iomem *base = phy->regs;
1243
1244         /* check if OBS bus is already enabled */
1245         val = readl(base + UTMIP_MISC_CFG0);
1246         if (val & UTMIP_DPDM_OBSERVE) {
1247                 /* Change the UTMIP OBS bus to drive SE0 */
1248                 val = readl(base + UTMIP_MISC_CFG0);
1249                 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1250                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_SE0;
1251                 writel(val, base + UTMIP_MISC_CFG0);
1252
1253                 /* Wait for 3us(2 LS bit times) */
1254                 udelay(3);
1255
1256                 /* Release UTMIP OBS bus */
1257                 val = readl(base + UTMIP_MISC_CFG0);
1258                 val &= ~UTMIP_DPDM_OBSERVE;
1259                 writel(val, base + UTMIP_MISC_CFG0);
1260
1261                 /* Release DP/DM pulldown for Host mode */
1262                 val = readl(base + UTMIP_MISC_CFG0);
1263                 val &= ~(FORCE_PULLDN_DM | FORCE_PULLDN_DP |
1264                                 COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS);
1265                 writel(val, base + UTMIP_MISC_CFG0);
1266         }
1267 }
1268
1269 static int utmi_phy_post_resume(struct tegra_usb_phy *phy)
1270 {
1271         unsigned long val;
1272         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1273         unsigned  int inst = phy->inst;
1274
1275         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1276         val = readl(pmc_base + PMC_SLEEP_CFG);
1277         /* if PMC is not disabled by now then disable it */
1278         if (val & UTMIP_MASTER_ENABLE(inst)) {
1279                 utmip_phy_disable_pmc_bus_ctrl(phy);
1280         }
1281
1282         utmi_phy_disable_obs_bus(phy);
1283
1284         return 0;
1285 }
1286
1287 static int utmi_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1288 {
1289         unsigned long val;
1290         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1291         unsigned  int inst = phy->inst;
1292
1293         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1294         val = readl(pmc_base + PMC_SLEEP_CFG);
1295         if (val & UTMIP_MASTER_ENABLE(inst)) {
1296                 if (!remote_wakeup)
1297                         utmip_phy_disable_pmc_bus_ctrl(phy);
1298         } else {
1299                 utmi_phy_enable_obs_bus(phy);
1300         }
1301
1302         return 0;
1303 }
1304
1305 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
1306 {
1307         unsigned long val;
1308         void __iomem *base = phy->regs;
1309
1310         DBG("%s(%d) inst:[%d] BEGIN\n", __func__, __LINE__, phy->inst);
1311         if (!phy->phy_clk_on) {
1312                 DBG("%s(%d) inst:[%d] phy clk is already off\n",
1313                                         __func__, __LINE__, phy->inst);
1314                 return 0;
1315         }
1316
1317         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1318                 utmip_powerdown_pmc_wake_detect(phy);
1319
1320                 val = readl(base + USB_SUSP_CTRL);
1321                 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
1322                 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
1323                 writel(val, base + USB_SUSP_CTRL);
1324
1325                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1326                 val |= UTMIP_PD_CHRG;
1327                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1328         } else {
1329                 utmip_setup_pmc_wake_detect(phy);
1330         }
1331
1332         if (!phy->pdata->u_data.host.hot_plug) {
1333                 val = readl(base + UTMIP_XCVR_CFG0);
1334                 val |= (UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
1335                          UTMIP_FORCE_PDZI_POWERDOWN);
1336                 writel(val, base + UTMIP_XCVR_CFG0);
1337         }
1338
1339         val = readl(base + UTMIP_XCVR_CFG1);
1340         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1341                    UTMIP_FORCE_PDDR_POWERDOWN;
1342         writel(val, base + UTMIP_XCVR_CFG1);
1343
1344         val = readl(base + UTMIP_BIAS_CFG1);
1345         val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
1346         writel(val, base + UTMIP_BIAS_CFG1);
1347
1348         utmi_phy_pad_power_off(phy);
1349
1350         phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
1351                         HOSTPC1_DEVLC_PSPD_MASK;
1352
1353         if (phy->pdata->u_data.host.hot_plug) {
1354                 bool enable_hotplug = true;
1355                 /* if it is OTG port then make sure to enable hot-plug feature
1356                    only if host adaptor is connected, i.e id is low */
1357                 if (phy->pdata->port_otg) {
1358                         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1359                         enable_hotplug = (val & USB_ID_STATUS) ? false : true;
1360                 }
1361                 if (enable_hotplug) {
1362                         val = readl(base + USB_PORTSC);
1363                         val |= USB_PORTSC_WKCN;
1364                         writel(val, base + USB_PORTSC);
1365
1366                         val = readl(base + USB_SUSP_CTRL);
1367                         val |= USB_PHY_CLK_VALID_INT_ENB;
1368                         writel(val, base + USB_SUSP_CTRL);
1369                 } else {
1370                         /* Disable PHY clock valid interrupts while going into suspend*/
1371                         val = readl(base + USB_SUSP_CTRL);
1372                         val &= ~USB_PHY_CLK_VALID_INT_ENB;
1373                         writel(val, base + USB_SUSP_CTRL);
1374                 }
1375         }
1376
1377         if (phy->inst == 0) {
1378                         val = readl(base + USB_SUSP_CTRL);
1379                         val |= UTMIP_RESET;
1380                         writel(val, base + USB_SUSP_CTRL);
1381         }
1382
1383         val = readl(base + HOSTPC1_DEVLC);
1384         val |= HOSTPC1_DEVLC_PHCD;
1385         writel(val, base + HOSTPC1_DEVLC);
1386
1387         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
1388                                                                 0, 2500))
1389                 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
1390
1391         phy->phy_clk_on = false;
1392         phy->hw_accessible = false;
1393
1394         DBG("%s(%d) inst:[%d] END\n", __func__, __LINE__, phy->inst);
1395
1396         return 0;
1397 }
1398
1399
1400 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
1401 {
1402         unsigned long val;
1403         void __iomem *base = phy->regs;
1404         struct tegra_utmi_config *config = &phy->pdata->u_cfg.utmi;
1405
1406         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1407         if (phy->phy_clk_on) {
1408                 DBG("%s(%d) inst:[%d] phy clk is already On\n",
1409                                         __func__, __LINE__, phy->inst);
1410                 return 0;
1411         }
1412         val = readl(base + USB_SUSP_CTRL);
1413         val |= UTMIP_RESET;
1414         writel(val, base + USB_SUSP_CTRL);
1415
1416         val = readl(base + UTMIP_TX_CFG0);
1417         val |= UTMIP_FS_PREABMLE_J;
1418         writel(val, base + UTMIP_TX_CFG0);
1419
1420         val = readl(base + UTMIP_HSRX_CFG0);
1421         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
1422         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
1423         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
1424         writel(val, base + UTMIP_HSRX_CFG0);
1425
1426         val = readl(base + UTMIP_HSRX_CFG1);
1427         val &= ~UTMIP_HS_SYNC_START_DLY(~0);
1428         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
1429         writel(val, base + UTMIP_HSRX_CFG1);
1430
1431         val = readl(base + UTMIP_DEBOUNCE_CFG0);
1432         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
1433         val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
1434         writel(val, base + UTMIP_DEBOUNCE_CFG0);
1435
1436         val = readl(base + UTMIP_MISC_CFG0);
1437         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
1438         writel(val, base + UTMIP_MISC_CFG0);
1439
1440         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1441                 val = readl(base + USB_SUSP_CTRL);
1442                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
1443                 writel(val, base + USB_SUSP_CTRL);
1444
1445                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1446                 val &= ~UTMIP_PD_CHRG;
1447                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1448         } else {
1449                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1450                 val |= UTMIP_PD_CHRG;
1451                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1452         }
1453
1454         utmi_phy_pad_power_on(phy);
1455
1456         val = readl(base + UTMIP_XCVR_CFG0);
1457         val &= ~(UTMIP_XCVR_LSBIAS_SEL | UTMIP_FORCE_PD_POWERDOWN |
1458                  UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN |
1459                  UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_LSFSLEW(~0) |
1460                  UTMIP_XCVR_LSRSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
1461         val |= UTMIP_XCVR_SETUP(phy->utmi_xcvr_setup);
1462         val |= UTMIP_XCVR_SETUP_MSB(XCVR_SETUP_MSB_CALIB(phy->utmi_xcvr_setup));
1463         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
1464         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
1465         val |= UTMIP_XCVR_HSSLEW_MSB(0x8);
1466         writel(val, base + UTMIP_XCVR_CFG0);
1467
1468         val = readl(base + UTMIP_XCVR_CFG1);
1469         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1470                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
1471         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
1472         writel(val, base + UTMIP_XCVR_CFG1);
1473
1474         val = readl(base + UTMIP_BIAS_CFG1);
1475         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
1476         val |= UTMIP_BIAS_PDTRK_COUNT(phy->freq->pdtrk_count);
1477         writel(val, base + UTMIP_BIAS_CFG1);
1478
1479         val = readl(base + UTMIP_SPARE_CFG0);
1480         val &= ~FUSE_SETUP_SEL;
1481         val |= FUSE_ATERM_SEL;
1482         writel(val, base + UTMIP_SPARE_CFG0);
1483
1484         val = readl(base + USB_SUSP_CTRL);
1485         val |= UTMIP_PHY_ENABLE;
1486         writel(val, base + USB_SUSP_CTRL);
1487
1488         val = readl(base + USB_SUSP_CTRL);
1489         val &= ~UTMIP_RESET;
1490         writel(val, base + USB_SUSP_CTRL);
1491
1492         val = readl(base + HOSTPC1_DEVLC);
1493         val &= ~HOSTPC1_DEVLC_PHCD;
1494         writel(val, base + HOSTPC1_DEVLC);
1495
1496         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1497                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500))
1498                 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
1499
1500         utmi_phy_enable_trking_data(phy);
1501
1502         if (phy->inst == 2)
1503                 writel(0, base + ICUSB_CTRL);
1504
1505         val = readl(base + USB_USBMODE);
1506         val &= ~USB_USBMODE_MASK;
1507         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST)
1508                 val |= USB_USBMODE_HOST;
1509         else
1510                 val |= USB_USBMODE_DEVICE;
1511         writel(val, base + USB_USBMODE);
1512
1513         val = readl(base + HOSTPC1_DEVLC);
1514         val &= ~HOSTPC1_DEVLC_PTS(~0);
1515         val |= HOSTPC1_DEVLC_STS;
1516         writel(val, base + HOSTPC1_DEVLC);
1517
1518         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE)
1519                 utmip_powerup_pmc_wake_detect(phy);
1520         phy->phy_clk_on = true;
1521         phy->hw_accessible = true;
1522         DBG("%s(%d) End\n", __func__, __LINE__);
1523
1524         return 0;
1525 }
1526
1527 static void utmi_phy_restore_start(struct tegra_usb_phy *phy)
1528 {
1529         unsigned long val;
1530         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1531         int inst = phy->inst;
1532
1533         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1534         val = readl(pmc_base + UTMIP_UHSIC_STATUS);
1535         /* check whether we wake up from the remote resume */
1536         if (UTMIP_WALK_PTR_VAL(inst) & val) {
1537                 phy->remote_wakeup = true;
1538         } else {
1539                 if (!((UTMIP_USBON_VAL(phy->inst) |
1540                         UTMIP_USBOP_VAL(phy->inst)) & val)) {
1541                                 utmip_phy_disable_pmc_bus_ctrl(phy);
1542                 }
1543         }
1544         utmi_phy_enable_obs_bus(phy);
1545 }
1546
1547 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
1548 {
1549         unsigned long val;
1550         void __iomem *base = phy->regs;
1551         int wait_time_us = 3000; /* FPR should be set by this time */
1552
1553         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1554         /* check whether we wake up from the remote resume */
1555         if (phy->remote_wakeup) {
1556                 /* wait until FPR bit is set automatically on remote resume */
1557                 do {
1558                         val = readl(base + USB_PORTSC);
1559                         udelay(1);
1560                         if (wait_time_us == 0)
1561                                 return;
1562                         wait_time_us--;
1563                 } while (!(val & USB_PORTSC_RESUME));
1564                 /* wait for 25 ms to port resume complete */
1565                 msleep(25);
1566                 /* disable PMC master control */
1567                 utmip_phy_disable_pmc_bus_ctrl(phy);
1568
1569                 /* Clear PCI and SRI bits to avoid an interrupt upon resume */
1570                 val = readl(base + USB_USBSTS);
1571                 writel(val, base + USB_USBSTS);
1572                 /* wait to avoid SOF if there is any */
1573                 if (usb_phy_reg_status_wait(base + USB_USBSTS,
1574                         USB_USBSTS_SRI, USB_USBSTS_SRI, 2500) < 0) {
1575                         pr_err("%s: timeout waiting for SOF\n", __func__);
1576                 }
1577                 utmi_phy_post_resume(phy);
1578         }
1579 }
1580
1581 static int utmi_phy_resume(struct tegra_usb_phy *phy)
1582 {
1583         int status = 0;
1584         unsigned long val;
1585         void __iomem *base = phy->regs;
1586
1587         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1588         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) {
1589                 if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
1590                         utmi_phy_restore_start(phy);
1591                         usb_phy_bringup_host_controller(phy);
1592                         utmi_phy_restore_end(phy);
1593                 } else {
1594                         /* device is plugged in when system is in LP0 */
1595                         /* bring up the controller from LP0*/
1596                         val = readl(base + USB_USBCMD);
1597                         val |= USB_CMD_RESET;
1598                         writel(val, base + USB_USBCMD);
1599
1600                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1601                                 USB_CMD_RESET, 0, 2500) < 0) {
1602                                 pr_err("%s: timeout waiting for reset\n", __func__);
1603                         }
1604
1605                         val = readl(base + USB_USBMODE);
1606                         val &= ~USB_USBMODE_MASK;
1607                         val |= USB_USBMODE_HOST;
1608                         writel(val, base + USB_USBMODE);
1609
1610                         val = readl(base + HOSTPC1_DEVLC);
1611                         val &= ~HOSTPC1_DEVLC_PTS(~0);
1612                         val |= HOSTPC1_DEVLC_STS;
1613                         writel(val, base + HOSTPC1_DEVLC);
1614
1615                         writel(USB_USBCMD_RS, base + USB_USBCMD);
1616
1617                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1618                                 USB_USBCMD_RS, USB_USBCMD_RS, 2500) < 0) {
1619                                 pr_err("%s: timeout waiting for run bit\n", __func__);
1620                         }
1621
1622                         /* Enable Port Power */
1623                         val = readl(base + USB_PORTSC);
1624                         val |= USB_PORTSC_PP;
1625                         writel(val, base + USB_PORTSC);
1626                         udelay(10);
1627
1628                         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1629                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1630                 }
1631         }
1632
1633         return status;
1634 }
1635
1636 bool utmi_phy_charger_detect(struct tegra_usb_phy *phy)
1637 {
1638         unsigned long val;
1639         void __iomem *base = phy->regs;
1640         bool status;
1641
1642         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1643         if (phy->pdata->op_mode != TEGRA_USB_OPMODE_DEVICE) {
1644                 /* Charger detection is not there for ULPI
1645                  * return Charger not available */
1646                 return false;
1647         }
1648
1649         /* Enable charger detection logic */
1650         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1651         val |= UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN;
1652         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1653
1654         /* Source should be on for 100 ms as per USB charging spec */
1655         msleep(TDP_SRC_ON_MS);
1656
1657         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1658         /* If charger is not connected disable the interrupt */
1659         val &= ~VDAT_DET_INT_EN;
1660         val |= VDAT_DET_CHG_DET;
1661         writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
1662
1663         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1664         if (val & VDAT_DET_STS)
1665                 status = true;
1666         else
1667                 status = false;
1668
1669         /* Disable charger detection logic */
1670         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1671         val &= ~(UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN);
1672         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1673
1674         /* Delay of 40 ms before we pull the D+ as per battery charger spec */
1675         msleep(TDPSRC_CON_MS);
1676
1677         return status;
1678 }
1679
1680 static int uhsic_phy_open(struct tegra_usb_phy *phy)
1681 {
1682         unsigned long parent_rate;
1683         int i;
1684
1685         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1686         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
1687         for (i = 0; i < ARRAY_SIZE(uhsic_freq_table); i++) {
1688                 if (uhsic_freq_table[i].freq == parent_rate) {
1689                         phy->freq = &uhsic_freq_table[i];
1690                         break;
1691                 }
1692         }
1693         if (!phy->freq) {
1694                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
1695                 return -EINVAL;
1696         }
1697
1698         utmip_powerup_pmc_wake_detect(phy);
1699
1700         return 0;
1701 }
1702
1703 static int uhsic_phy_irq(struct tegra_usb_phy *phy)
1704 {
1705         usb_phy_fence_read(phy);
1706         return IRQ_HANDLED;
1707 }
1708
1709 static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
1710 {
1711         unsigned long val;
1712         void __iomem *base = phy->regs;
1713         struct tegra_hsic_config *config = &phy->pdata->u_cfg.hsic;
1714
1715         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1716
1717         utmip_powerup_pmc_wake_detect(phy);
1718
1719         if (phy->phy_clk_on) {
1720                 DBG("%s(%d) inst:[%d] phy clk is already On\n",
1721                                         __func__, __LINE__, phy->inst);
1722                 return 0;
1723         }
1724
1725         val = readl(base + UHSIC_PADS_CFG1);
1726         val &= ~(UHSIC_PD_BG | UHSIC_PD_TX | UHSIC_PD_TRK | UHSIC_PD_RX |
1727                         UHSIC_PD_ZI | UHSIC_RPD_DATA | UHSIC_RPD_STROBE);
1728         val |= UHSIC_RX_SEL;
1729         writel(val, base + UHSIC_PADS_CFG1);
1730         udelay(2);
1731
1732         val = readl(base + USB_SUSP_CTRL);
1733         val |= UHSIC_RESET;
1734         writel(val, base + USB_SUSP_CTRL);
1735         udelay(30);
1736
1737         val = readl(base + USB_SUSP_CTRL);
1738         val |= UHSIC_PHY_ENABLE;
1739         writel(val, base + USB_SUSP_CTRL);
1740
1741         val = readl(base + UHSIC_HSRX_CFG0);
1742         val |= UHSIC_IDLE_WAIT(config->idle_wait_delay);
1743         val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(config->elastic_underrun_limit);
1744         val |= UHSIC_ELASTIC_OVERRUN_LIMIT(config->elastic_overrun_limit);
1745         writel(val, base + UHSIC_HSRX_CFG0);
1746
1747         val = readl(base + UHSIC_HSRX_CFG1);
1748         val |= UHSIC_HS_SYNC_START_DLY(config->sync_start_delay);
1749         writel(val, base + UHSIC_HSRX_CFG1);
1750
1751         /* WAR HSIC TX */
1752         val = readl(base + UHSIC_TX_CFG0);
1753         val &= ~UHSIC_HS_READY_WAIT_FOR_VALID;
1754         writel(val, base + UHSIC_TX_CFG0);
1755
1756         val = readl(base + UHSIC_MISC_CFG0);
1757         val |= UHSIC_SUSPEND_EXIT_ON_EDGE;
1758         /* Disable generic bus reset, to allow AP30 specific bus reset*/
1759         val |= UHSIC_DISABLE_BUSRESET;
1760         writel(val, base + UHSIC_MISC_CFG0);
1761
1762         val = readl(base + UHSIC_MISC_CFG1);
1763         val |= UHSIC_PLLU_STABLE_COUNT(phy->freq->stable_count);
1764         writel(val, base + UHSIC_MISC_CFG1);
1765
1766         val = readl(base + UHSIC_PLL_CFG1);
1767         val |= UHSIC_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
1768         val |= UHSIC_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count);
1769         writel(val, base + UHSIC_PLL_CFG1);
1770
1771         val = readl(base + USB_SUSP_CTRL);
1772         val &= ~(UHSIC_RESET);
1773         writel(val, base + USB_SUSP_CTRL);
1774         udelay(2);
1775
1776         val = readl(base + USB_USBMODE);
1777         val |= USB_USBMODE_HOST;
1778         writel(val, base + USB_USBMODE);
1779
1780         /* Change the USB controller PHY type to HSIC */
1781         val = readl(base + HOSTPC1_DEVLC);
1782         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
1783         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
1784         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
1785         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
1786         writel(val, base + HOSTPC1_DEVLC);
1787
1788         val = readl(base + USB_TXFILLTUNING);
1789         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
1790                 val = USB_FIFO_TXFILL_THRES(0x10);
1791                 writel(val, base + USB_TXFILLTUNING);
1792         }
1793
1794         val = readl(base + USB_PORTSC);
1795         val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN);
1796         writel(val, base + USB_PORTSC);
1797
1798         val = readl(base + UHSIC_PADS_CFG0);
1799         val &= ~(UHSIC_TX_RTUNEN);
1800         /* set Rtune impedance to 50 ohm */
1801         val |= UHSIC_TX_RTUNE(8);
1802         writel(val, base + UHSIC_PADS_CFG0);
1803
1804         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1805                                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500)) {
1806                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
1807                 return -ETIMEDOUT;
1808         }
1809
1810         phy->phy_clk_on = true;
1811         phy->hw_accessible = true;
1812
1813         return 0;
1814 }
1815
1816 static int uhsic_phy_power_off(struct tegra_usb_phy *phy)
1817 {
1818         unsigned long val;
1819         void __iomem *base = phy->regs;
1820
1821         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1822         if (!phy->phy_clk_on) {
1823                 DBG("%s(%d) inst:[%d] phy clk is already off\n",
1824                                         __func__, __LINE__, phy->inst);
1825                 return 0;
1826         }
1827
1828         val = readl(base + UHSIC_PADS_CFG1);
1829         val &= ~UHSIC_RPU_STROBE;
1830         val |= UHSIC_RPD_STROBE;
1831         writel(val, base + UHSIC_PADS_CFG1);
1832
1833         val = readl(base + USB_SUSP_CTRL);
1834         val |= UHSIC_RESET;
1835         writel(val, base + USB_SUSP_CTRL);
1836         udelay(30);
1837
1838         utmip_powerdown_pmc_wake_detect(phy);
1839
1840         phy->phy_clk_on = false;
1841         phy->hw_accessible = false;
1842
1843         return 0;
1844 }
1845
1846 int uhsic_phy_bus_port_power(struct tegra_usb_phy *phy)
1847 {
1848         unsigned long val;
1849         void __iomem *base = phy->regs;
1850
1851         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1852         val = readl(base + UHSIC_STAT_CFG0);
1853         val &= ~UHSIC_CONNECT_DETECT;
1854         writel(val, base + UHSIC_STAT_CFG0);
1855
1856         val = readl(base + USB_USBMODE);
1857         val |= USB_USBMODE_HOST;
1858         writel(val, base + USB_USBMODE);
1859
1860         /* Change the USB controller PHY type to HSIC */
1861         val = readl(base + HOSTPC1_DEVLC);
1862         val &= ~(HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK));
1863         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
1864         val &= ~(HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK));
1865         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
1866         writel(val, base + HOSTPC1_DEVLC);
1867
1868         val = readl(base + UHSIC_MISC_CFG0);
1869         val |= UHSIC_DETECT_SHORT_CONNECT;
1870         writel(val, base + UHSIC_MISC_CFG0);
1871         udelay(1);
1872
1873         val = readl(base + UHSIC_MISC_CFG0);
1874         val |= UHSIC_FORCE_XCVR_MODE;
1875         writel(val, base + UHSIC_MISC_CFG0);
1876
1877         val = readl(base + UHSIC_PADS_CFG1);
1878         val &= ~UHSIC_RPD_STROBE;
1879         /* safe to enable RPU on STROBE at all times during idle */
1880         val |= UHSIC_RPU_STROBE;
1881         writel(val, base + UHSIC_PADS_CFG1);
1882
1883         val = readl(base + USB_USBCMD);
1884         val &= ~USB_USBCMD_RS;
1885         writel(val, base + USB_USBCMD);
1886
1887         if (usb_phy_reg_status_wait(base + UHSIC_STAT_CFG0,
1888                         UHSIC_CONNECT_DETECT, UHSIC_CONNECT_DETECT, 25000)) {
1889                 pr_err("%s: timeout waiting for UHSIC_CONNECT_DETECT\n",
1890                                                                 __func__);
1891                 return -ETIMEDOUT;
1892         }
1893
1894         return 0;
1895 }
1896
1897 static int uhsic_phy_bus_reset(struct tegra_usb_phy *phy)
1898 {
1899         unsigned long val;
1900         void __iomem *base = phy->regs;
1901
1902         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1903
1904         /* Change the USB controller PHY type to HSIC */
1905         val = readl(base + HOSTPC1_DEVLC);
1906         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
1907         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
1908         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
1909         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
1910         writel(val, base + HOSTPC1_DEVLC);
1911         /* wait here, otherwise HOSTPC1_DEVLC_PSPD will timeout */
1912         mdelay(5);
1913
1914         val = readl(base + USB_PORTSC);
1915         val |= USB_PORTSC_PTC(5);
1916         writel(val, base + USB_PORTSC);
1917         udelay(2);
1918
1919         val = readl(base + USB_PORTSC);
1920         val &= ~(USB_PORTSC_PTC(~0));
1921         writel(val, base + USB_PORTSC);
1922         udelay(2);
1923
1924         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_LS(0),
1925                                                  0, 2000)) {
1926                 pr_err("%s: timeout waiting for USB_PORTSC_LS\n", __func__);
1927                 return -ETIMEDOUT;
1928         }
1929
1930         /* Poll until CCS is enabled */
1931         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
1932                                                  USB_PORTSC_CCS, 2000)) {
1933                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
1934                 return -ETIMEDOUT;
1935         }
1936
1937         if (usb_phy_reg_status_wait(base + HOSTPC1_DEVLC,
1938                         HOSTPC1_DEVLC_PSPD(2),
1939                         HOSTPC1_DEVLC_PSPD(2), 2000) < 0) {
1940                 pr_err("%s: timeout waiting hsic high speed configuration\n",
1941                                                 __func__);
1942                         return -ETIMEDOUT;
1943         }
1944
1945         val = readl(base + USB_USBCMD);
1946         val &= ~USB_USBCMD_RS;
1947         writel(val, base + USB_USBCMD);
1948
1949         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
1950                                                  USB_USBSTS_HCH, 2000)) {
1951                 pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
1952                 return -ETIMEDOUT;
1953         }
1954
1955         val = readl(base + UHSIC_PADS_CFG1);
1956         val &= ~UHSIC_RPU_STROBE;
1957         val |= UHSIC_RPD_STROBE;
1958         writel(val, base + UHSIC_PADS_CFG1);
1959
1960         mdelay(50);
1961
1962         val = readl(base + UHSIC_PADS_CFG1);
1963         val &= ~UHSIC_RPD_STROBE;
1964         val |= UHSIC_RPU_STROBE;
1965         writel(val, base + UHSIC_PADS_CFG1);
1966
1967         val = readl(base + USB_USBCMD);
1968         val |= USB_USBCMD_RS;
1969         writel(val, base + USB_USBCMD);
1970
1971         val = readl(base + UHSIC_PADS_CFG1);
1972         val &= ~UHSIC_RPU_STROBE;
1973         writel(val, base + UHSIC_PADS_CFG1);
1974
1975         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
1976                                                  USB_USBCMD_RS, 2000)) {
1977                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
1978                 return -ETIMEDOUT;
1979         }
1980
1981         return 0;
1982 }
1983
1984
1985 int uhsic_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1986 {
1987         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1988
1989         usb_phy_wait_for_sof(phy);
1990
1991         return 0;
1992 }
1993
1994 int uhsic_phy_resume(struct tegra_usb_phy *phy)
1995 {
1996         void __iomem *base = phy->regs;
1997         unsigned long val;
1998
1999         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2000
2001         /* Check if the phy resume from LP0. When the phy resume from LP0
2002          * USB register will be reset.to zero */
2003         if (!readl(base + USB_ASYNCLISTADDR)) {
2004
2005                 val = readl(base + USB_USBCMD);
2006                 val |= USB_CMD_RESET;
2007                 writel(val, base + USB_USBCMD);
2008
2009                 if (usb_phy_reg_status_wait(base + USB_USBCMD,
2010                         USB_CMD_RESET, 0, 2500) < 0) {
2011                         pr_err("%s: timeout waiting for reset\n", __func__);
2012                 }
2013
2014                 val = readl(base + USB_USBMODE);
2015                 val &= ~USB_USBMODE_MASK;
2016                 val |= USB_USBMODE_HOST;
2017                 writel(val, base + USB_USBMODE);
2018
2019                 /* Enable Port Power */
2020                 val = readl(base + USB_PORTSC);
2021                 val |= USB_PORTSC_PP;
2022                 writel(val, base + USB_PORTSC);
2023                 udelay(10);
2024
2025                 DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
2026                 readl(base + USB_USBSTS), readl(base + USB_PORTSC));
2027
2028                 uhsic_phy_bus_port_power(phy);
2029         }
2030
2031         return 0;
2032 }
2033
2034 static int uhsic_phy_post_resume(struct tegra_usb_phy *phy)
2035 {
2036         unsigned long val;
2037         void __iomem *base = phy->regs;
2038
2039         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2040         val = readl(base + USB_TXFILLTUNING);
2041         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
2042                 val = USB_FIFO_TXFILL_THRES(0x10);
2043                 writel(val, base + USB_TXFILLTUNING);
2044         }
2045
2046         return 0;
2047 }
2048
2049 static void ulpi_set_trimmer(struct tegra_usb_phy *phy)
2050 {
2051         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2052         void __iomem *base = phy->regs;
2053         unsigned long val;
2054
2055         val = ULPI_DATA_TRIMMER_SEL(config->data_trimmer);
2056         val |= ULPI_STPDIRNXT_TRIMMER_SEL(config->stpdirnxt_trimmer);
2057         val |= ULPI_DIR_TRIMMER_SEL(config->dir_trimmer);
2058         writel(val, base + ULPI_TIMING_CTRL_1);
2059         udelay(10);
2060
2061         val |= ULPI_DATA_TRIMMER_LOAD;
2062         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
2063         val |= ULPI_DIR_TRIMMER_LOAD;
2064         writel(val, base + ULPI_TIMING_CTRL_1);
2065 }
2066
2067 static void reset_utmip_uhsic(void __iomem *base)
2068 {
2069         unsigned long val;
2070
2071         val = readl(base + USB_SUSP_CTRL);
2072         val |= UHSIC_RESET;
2073         writel(val, base + USB_SUSP_CTRL);
2074
2075         val = readl(base + USB_SUSP_CTRL);
2076         val |= UTMIP_RESET;
2077         writel(val, base + USB_SUSP_CTRL);
2078 }
2079
2080 static void ulpi_set_host(void __iomem *base)
2081 {
2082         unsigned long val;
2083
2084         val = readl(base + USB_USBMODE);
2085         val |= USB_USBMODE_HOST;
2086         writel(val, base + USB_USBMODE);
2087
2088         val = readl(base + HOSTPC1_DEVLC);
2089         val |= HOSTPC1_DEVLC_PTS(2);
2090         writel(val, base + HOSTPC1_DEVLC);
2091 }
2092
2093
2094
2095 static inline void null_phy_set_tristate(bool enable)
2096 {
2097 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2098         int tristate = (enable) ? TEGRA_TRI_TRISTATE : TEGRA_TRI_NORMAL;
2099         DBG("%s(%d) inst:[%s] FIXME enable pin group +++\n", __func__,
2100                                 __LINE__, enable ? "TRISTATE" : "NORMAL");
2101
2102         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA0, tristate);
2103         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA1, tristate);
2104         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA2, tristate);
2105         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA3, tristate);
2106         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA4, tristate);
2107         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA5, tristate);
2108         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA6, tristate);
2109         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA7, tristate);
2110         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_NXT, tristate);
2111
2112         if (enable)
2113                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR, tristate);
2114 #endif
2115
2116 }
2117
2118
2119 static int ulpi_null_phy_power_off(struct tegra_usb_phy *phy)
2120 {
2121         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2122
2123         if (!phy->phy_clk_on) {
2124                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
2125                                                         __LINE__, phy->inst);
2126                 return 0;
2127         }
2128
2129         null_phy_set_tristate(true);
2130
2131         phy->phy_clk_on = false;
2132         phy->hw_accessible = false;
2133
2134         return 0;
2135 }
2136
2137 static int ulpi_null_phy_init(struct tegra_usb_phy *phy)
2138 {
2139         unsigned long val;
2140         void __iomem *base = phy->regs;
2141
2142         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2143         val = readl(base + ULPIS2S_CTRL);
2144         val |=  ULPIS2S_SLV0_CLAMP_XMIT;
2145         writel(val, base + ULPIS2S_CTRL);
2146
2147         val = readl(base + USB_SUSP_CTRL);
2148         val |= ULPIS2S_SLV0_RESET;
2149         writel(val, base + USB_SUSP_CTRL);
2150         udelay(10);
2151
2152         return 0;
2153 }
2154
2155 static int ulpi_null_phy_irq(struct tegra_usb_phy *phy)
2156 {
2157         usb_phy_fence_read(phy);
2158         return IRQ_HANDLED;
2159 }
2160
2161 static int ulpi_null_phy_cmd_reset(struct tegra_usb_phy *phy)
2162 {
2163         unsigned long val;
2164         void __iomem *base = phy->regs;
2165
2166         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2167         ulpi_set_host(base);
2168
2169         /* remove slave0 reset */
2170         val = readl(base + USB_SUSP_CTRL);
2171         val &= ~ULPIS2S_SLV0_RESET;
2172         writel(val, base + USB_SUSP_CTRL);
2173
2174         val = readl(base + ULPIS2S_CTRL);
2175         val &=  ~ULPIS2S_SLV0_CLAMP_XMIT;
2176         writel(val, base + ULPIS2S_CTRL);
2177         udelay(10);
2178
2179         return 0;
2180 }
2181
2182 static int ulpi_null_phy_power_on(struct tegra_usb_phy *phy)
2183 {
2184         unsigned long val;
2185         void __iomem *base = phy->regs;
2186         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2187         static bool cold_boot = true;
2188
2189         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2190         if (phy->phy_clk_on) {
2191                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
2192                                                         __LINE__, phy->inst);
2193                 return 0;
2194         }
2195         reset_utmip_uhsic(base);
2196
2197         /* remove ULPI PADS CLKEN reset */
2198         val = readl(base + USB_SUSP_CTRL);
2199         val &= ~ULPI_PADS_CLKEN_RESET;
2200         writel(val, base + USB_SUSP_CTRL);
2201         udelay(10);
2202
2203         val = readl(base + ULPI_TIMING_CTRL_0);
2204         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
2205         writel(val, base + ULPI_TIMING_CTRL_0);
2206
2207         val = readl(base + USB_SUSP_CTRL);
2208         val |= ULPI_PHY_ENABLE;
2209         writel(val, base + USB_SUSP_CTRL);
2210         udelay(10);
2211
2212         /* set timming parameters */
2213         val = readl(base + ULPI_TIMING_CTRL_0);
2214         val |= ULPI_SHADOW_CLK_LOOPBACK_EN;
2215         val &= ~ULPI_SHADOW_CLK_SEL;
2216         val &= ~ULPI_LBK_PAD_EN;
2217         val |= ULPI_SHADOW_CLK_DELAY(config->shadow_clk_delay);
2218         val |= ULPI_CLOCK_OUT_DELAY(config->clock_out_delay);
2219         val |= ULPI_LBK_PAD_E_INPUT_OR;
2220         writel(val, base + ULPI_TIMING_CTRL_0);
2221
2222         writel(0, base + ULPI_TIMING_CTRL_1);
2223         udelay(10);
2224
2225         /* start internal 60MHz clock */
2226         val = readl(base + ULPIS2S_CTRL);
2227         val |= ULPIS2S_ENA;
2228         val |= ULPIS2S_SUPPORT_DISCONNECT;
2229         val |= ULPIS2S_SPARE((phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) ? 3 : 1);
2230         val |= ULPIS2S_PLLU_MASTER_BLASTER60;
2231         writel(val, base + ULPIS2S_CTRL);
2232
2233         /* select ULPI_CORE_CLK_SEL to SHADOW_CLK */
2234         val = readl(base + ULPI_TIMING_CTRL_0);
2235         val |= ULPI_CORE_CLK_SEL;
2236         writel(val, base + ULPI_TIMING_CTRL_0);
2237         udelay(10);
2238
2239         /* enable ULPI null phy clock - can't set the trimmers before this */
2240         val = readl(base + ULPI_TIMING_CTRL_0);
2241         val |= ULPI_CLK_OUT_ENA;
2242         writel(val, base + ULPI_TIMING_CTRL_0);
2243         udelay(10);
2244
2245         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
2246                                                  USB_PHY_CLK_VALID, 2500)) {
2247                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2248                 return -ETIMEDOUT;
2249         }
2250
2251         /* set ULPI trimmers */
2252         ulpi_set_trimmer(phy);
2253
2254         ulpi_set_host(base);
2255
2256         /* remove slave0 reset */
2257         val = readl(base + USB_SUSP_CTRL);
2258         val &= ~ULPIS2S_SLV0_RESET;
2259         writel(val, base + USB_SUSP_CTRL);
2260
2261         /* remove slave1 and line reset */
2262         val = readl(base + USB_SUSP_CTRL);
2263         val &= ~ULPIS2S_SLV1_RESET;
2264         val &= ~ULPIS2S_LINE_RESET;
2265
2266         /* remove ULPI PADS reset */
2267         val &= ~ULPI_PADS_RESET;
2268         writel(val, base + USB_SUSP_CTRL);
2269
2270         if (cold_boot) {
2271                 val = readl(base + ULPI_TIMING_CTRL_0);
2272                 val |= ULPI_CLK_PADOUT_ENA;
2273                 writel(val, base + ULPI_TIMING_CTRL_0);
2274                 cold_boot = false;
2275         }
2276         udelay(10);
2277
2278         phy->phy_clk_on = true;
2279         phy->hw_accessible = true;
2280
2281         return 0;
2282 }
2283
2284
2285 int ulpi_null_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
2286 {
2287         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2288
2289         usb_phy_wait_for_sof(phy);
2290         return 0;
2291 }
2292
2293 static struct tegra_usb_phy_ops utmi_phy_ops = {
2294         .open           = utmi_phy_open,
2295         .close          = utmi_phy_close,
2296         .irq            = utmi_phy_irq,
2297         .power_on       = utmi_phy_power_on,
2298         .power_off      = utmi_phy_power_off,
2299         .pre_resume = utmi_phy_pre_resume,
2300         .resume = utmi_phy_resume,
2301         .post_resume    = utmi_phy_post_resume,
2302         .charger_detect = utmi_phy_charger_detect,
2303 };
2304
2305 static struct tegra_usb_phy_ops uhsic_phy_ops = {
2306         .open           = uhsic_phy_open,
2307         .irq            = uhsic_phy_irq,
2308         .power_on       = uhsic_phy_power_on,
2309         .power_off      = uhsic_phy_power_off,
2310         .pre_resume = uhsic_phy_pre_resume,
2311         .resume = uhsic_phy_resume,
2312         .post_resume = uhsic_phy_post_resume,
2313         .port_power = uhsic_phy_bus_port_power,
2314         .bus_reset      = uhsic_phy_bus_reset,
2315 };
2316
2317 static struct tegra_usb_phy_ops ulpi_null_phy_ops = {
2318         .init           = ulpi_null_phy_init,
2319         .irq            = ulpi_null_phy_irq,
2320         .power_on       = ulpi_null_phy_power_on,
2321         .power_off      = ulpi_null_phy_power_off,
2322         .pre_resume = ulpi_null_phy_pre_resume,
2323         .reset          = ulpi_null_phy_cmd_reset,
2324 };
2325
2326 static struct tegra_usb_phy_ops ulpi_link_phy_ops;
2327 static struct tegra_usb_phy_ops icusb_phy_ops;
2328
2329 static struct tegra_usb_phy_ops *phy_ops[] = {
2330         [TEGRA_USB_PHY_INTF_UTMI] = &utmi_phy_ops,
2331         [TEGRA_USB_PHY_INTF_ULPI_LINK] = &ulpi_link_phy_ops,
2332         [TEGRA_USB_PHY_INTF_ULPI_NULL] = &ulpi_null_phy_ops,
2333         [TEGRA_USB_PHY_INTF_HSIC] = &uhsic_phy_ops,
2334         [TEGRA_USB_PHY_INTF_ICUSB] = &icusb_phy_ops,
2335 };
2336
2337 int tegra3_usb_phy_init_ops(struct tegra_usb_phy *phy)
2338 {
2339         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2340
2341         phy->ops = phy_ops[phy->pdata->phy_intf];
2342
2343         /* FIXME: uncommenting below line to make USB host mode fail*/
2344         /* usb_phy_power_down_pmc(); */
2345
2346         return 0;
2347 }