arm: tegra: usb: fix UTMIP auto suspend issues
[linux-2.6.git] / arch / arm / mach-tegra / tegra3_usb_phy.c
1 /*
2  * arch/arm/mach-tegra/tegra3_usb_phy.c
3  *
4  * Copyright (C) 2011 NVIDIA Corporation
5  *
6  *
7  * This software is licensed under the terms of the GNU General Public
8  * License version 2, as published by the Free Software Foundation, and
9  * may be copied, distributed, and modified under those terms.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17 #include <linux/resource.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/slab.h>
21 #include <linux/err.h>
22 #include <linux/platform_device.h>
23 #include <linux/io.h>
24 #include <linux/gpio.h>
25 #include <linux/interrupt.h>
26 #include <linux/clk.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <mach/iomap.h>
30 #include <mach/pinmux.h>
31 #include "tegra_usb_phy.h"
32 #include "fuse.h"
33
34 #define USB_USBCMD              0x130
35 #define   USB_USBCMD_RS         (1 << 0)
36 #define   USB_CMD_RESET (1<<1)
37
38 #define USB_USBSTS              0x134
39 #define   USB_USBSTS_PCI        (1 << 2)
40 #define   USB_USBSTS_SRI        (1 << 7)
41 #define   USB_USBSTS_HCH        (1 << 12)
42
43 #define USB_USBINTR             0x138
44
45 #define USB_TXFILLTUNING        0x154
46 #define USB_FIFO_TXFILL_THRES(x)   (((x) & 0x1f) << 16)
47 #define USB_FIFO_TXFILL_MASK    0x1f0000
48
49 #define USB_ASYNCLISTADDR       0x148
50
51 #define ICUSB_CTRL              0x15c
52
53 #define USB_PORTSC              0x174
54 #define   USB_PORTSC_WKOC       (1 << 22)
55 #define   USB_PORTSC_WKDS       (1 << 21)
56 #define   USB_PORTSC_WKCN       (1 << 20)
57 #define   USB_PORTSC_PTC(x)     (((x) & 0xf) << 16)
58 #define   USB_PORTSC_PP (1 << 12)
59 #define   USB_PORTSC_LS(x) (((x) & 0x3) << 10)
60 #define   USB_PORTSC_SUSP       (1 << 7)
61 #define   USB_PORTSC_RESUME     (1 << 6)
62 #define   USB_PORTSC_OCC        (1 << 5)
63 #define   USB_PORTSC_PEC        (1 << 3)
64 #define   USB_PORTSC_PE         (1 << 2)
65 #define   USB_PORTSC_CSC        (1 << 1)
66 #define   USB_PORTSC_CCS        (1 << 0)
67 #define   USB_PORTSC_RWC_BITS (USB_PORTSC_CSC | USB_PORTSC_PEC | USB_PORTSC_OCC)
68
69 #define HOSTPC1_DEVLC           0x1b4
70 #define   HOSTPC1_DEVLC_PHCD            (1 << 22)
71 #define   HOSTPC1_DEVLC_PTS(x)          (((x) & 0x7) << 29)
72 #define   HOSTPC1_DEVLC_PTS_MASK        7
73 #define   HOSTPC1_DEVLC_PTS_HSIC        4
74 #define   HOSTPC1_DEVLC_STS             (1 << 28)
75 #define   HOSTPC1_DEVLC_PSPD(x)         (((x) & 0x3) << 25)
76 #define   HOSTPC1_DEVLC_PSPD_MASK       3
77 #define   HOSTPC1_DEVLC_PSPD_HIGH_SPEED 2
78
79 #define USB_USBMODE             0x1f8
80 #define   USB_USBMODE_MASK              (3 << 0)
81 #define   USB_USBMODE_HOST              (3 << 0)
82 #define   USB_USBMODE_DEVICE            (2 << 0)
83
84 #define USB_SUSP_CTRL           0x400
85 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
86 #define   USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
87 #define   USB_SUSP_CLR                  (1 << 5)
88 #define   USB_PHY_CLK_VALID             (1 << 7)
89 #define   USB_PHY_CLK_VALID_INT_ENB     (1 << 9)
90 #define   USB_PHY_CLK_VALID_INT_STS     (1 << 8)
91 #define   UTMIP_RESET                   (1 << 11)
92 #define   UTMIP_PHY_ENABLE              (1 << 12)
93 #define   ULPI_PHY_ENABLE               (1 << 13)
94 #define   UHSIC_RESET                   (1 << 14)
95 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
96 #define   UHSIC_PHY_ENABLE              (1 << 19)
97 #define   ULPIS2S_SLV0_RESET            (1 << 20)
98 #define   ULPIS2S_SLV1_RESET            (1 << 21)
99 #define   ULPIS2S_LINE_RESET            (1 << 22)
100 #define   ULPI_PADS_RESET               (1 << 23)
101 #define   ULPI_PADS_CLKEN_RESET         (1 << 24)
102
103 #define USB_PHY_VBUS_WAKEUP_ID  0x408
104 #define   VDAT_DET_INT_EN       (1 << 16)
105 #define   VDAT_DET_CHG_DET      (1 << 17)
106 #define   VDAT_DET_STS          (1 << 18)
107 #define   USB_ID_STATUS         (1 << 2)
108
109 #define ULPIS2S_CTRL            0x418
110 #define   ULPIS2S_ENA                   (1 << 0)
111 #define   ULPIS2S_SUPPORT_DISCONNECT    (1 << 2)
112 #define   ULPIS2S_PLLU_MASTER_BLASTER60 (1 << 3)
113 #define   ULPIS2S_SPARE(x)              (((x) & 0xF) << 8)
114 #define   ULPIS2S_FORCE_ULPI_CLK_OUT    (1 << 12)
115 #define   ULPIS2S_DISCON_DONT_CHECK_SE0 (1 << 13)
116 #define   ULPIS2S_SUPPORT_HS_KEEP_ALIVE (1 << 14)
117 #define   ULPIS2S_DISABLE_STP_PU        (1 << 15)
118 #define   ULPIS2S_SLV0_CLAMP_XMIT       (1 << 16)
119
120 #define ULPI_TIMING_CTRL_0      0x424
121 #define   ULPI_CLOCK_OUT_DELAY(x)       ((x) & 0x1F)
122 #define   ULPI_OUTPUT_PINMUX_BYP        (1 << 10)
123 #define   ULPI_CLKOUT_PINMUX_BYP        (1 << 11)
124 #define   ULPI_SHADOW_CLK_LOOPBACK_EN   (1 << 12)
125 #define   ULPI_SHADOW_CLK_SEL           (1 << 13)
126 #define   ULPI_CORE_CLK_SEL             (1 << 14)
127 #define   ULPI_SHADOW_CLK_DELAY(x)      (((x) & 0x1F) << 16)
128 #define   ULPI_LBK_PAD_EN               (1 << 26)
129 #define   ULPI_LBK_PAD_E_INPUT_OR       (1 << 27)
130 #define   ULPI_CLK_OUT_ENA              (1 << 28)
131 #define   ULPI_CLK_PADOUT_ENA           (1 << 29)
132
133 #define ULPI_TIMING_CTRL_1      0x428
134 #define   ULPI_DATA_TRIMMER_LOAD        (1 << 0)
135 #define   ULPI_DATA_TRIMMER_SEL(x)      (((x) & 0x7) << 1)
136 #define   ULPI_STPDIRNXT_TRIMMER_LOAD   (1 << 16)
137 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
138 #define   ULPI_DIR_TRIMMER_LOAD         (1 << 24)
139 #define   ULPI_DIR_TRIMMER_SEL(x)       (((x) & 0x7) << 25)
140
141 #define UTMIP_XCVR_CFG0         0x808
142 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
143 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
144 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
145 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
146 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
147 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
148 #define   UTMIP_XCVR_LSBIAS_SEL                 (1 << 21)
149 #define   UTMIP_XCVR_SETUP_MSB(x)               (((x) & 0x7) << 22)
150 #define   UTMIP_XCVR_HSSLEW_MSB(x)              (((x) & 0x7f) << 25)
151 #define   UTMIP_XCVR_MAX_OFFSET         2
152 #define   UTMIP_XCVR_SETUP_MAX_VALUE    0x7f
153 #define   UTMIP_XCVR_SETUP_MIN_VALUE    0
154 #define   XCVR_SETUP_MSB_CALIB(x) ((x) >> 4)
155
156 #define UTMIP_BIAS_CFG0         0x80c
157 #define   UTMIP_OTGPD                   (1 << 11)
158 #define   UTMIP_BIASPD                  (1 << 10)
159 #define   UTMIP_HSSQUELCH_LEVEL(x)      (((x) & 0x3) << 0)
160 #define   UTMIP_HSDISCON_LEVEL(x)       (((x) & 0x3) << 2)
161 #define   UTMIP_HSDISCON_LEVEL_MSB      (1 << 24)
162
163 #define UTMIP_HSRX_CFG0         0x810
164 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
165 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
166
167 #define UTMIP_HSRX_CFG1         0x814
168 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
169
170 #define UTMIP_TX_CFG0           0x820
171 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
172 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
173
174 #define UTMIP_DEBOUNCE_CFG0 0x82c
175 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
176
177 #define UTMIP_BAT_CHRG_CFG0 0x830
178 #define   UTMIP_PD_CHRG                 (1 << 0)
179 #define   UTMIP_ON_SINK_EN              (1 << 2)
180 #define   UTMIP_OP_SRC_EN               (1 << 3)
181
182 #define UTMIP_XCVR_CFG1         0x838
183 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
184 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
185 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
186 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
187
188 #define UTMIP_BIAS_CFG1         0x83c
189 #define   UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
190 #define   UTMIP_BIAS_PDTRK_POWERDOWN    (1 << 0)
191 #define   UTMIP_BIAS_PDTRK_POWERUP      (1 << 1)
192
193 #define UTMIP_MISC_CFG0         0x824
194 #define   UTMIP_DPDM_OBSERVE            (1 << 26)
195 #define   UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
196 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J   UTMIP_DPDM_OBSERVE_SEL(0xf)
197 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K   UTMIP_DPDM_OBSERVE_SEL(0xe)
198 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
199 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
200 #define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
201 #define   FORCE_PULLDN_DM       (1 << 8)
202 #define   FORCE_PULLDN_DP       (1 << 9)
203 #define   COMB_TERMS            (1 << 0)
204 #define   ALWAYS_FREE_RUNNING_TERMS (1 << 1)
205
206 #define UTMIP_SPARE_CFG0        0x834
207 #define   FUSE_SETUP_SEL                (1 << 3)
208 #define   FUSE_ATERM_SEL                (1 << 4)
209
210 #define UTMIP_PMC_WAKEUP0               0x84c
211 #define   EVENT_INT_ENB                 (1 << 0)
212
213 #define UTMIP_BIAS_STS0                 0x840
214 #define   UTMIP_RCTRL_VAL(x)            (((x) & 0xffff) << 0)
215 #define   UTMIP_TCTRL_VAL(x)            (((x) & (0xffff << 16)) >> 16)
216
217 #define UHSIC_PLL_CFG1                          0xc04
218 #define   UHSIC_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
219 #define   UHSIC_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 14)
220
221 #define UHSIC_HSRX_CFG0                         0xc08
222 #define   UHSIC_ELASTIC_UNDERRUN_LIMIT(x)       (((x) & 0x1f) << 2)
223 #define   UHSIC_ELASTIC_OVERRUN_LIMIT(x)        (((x) & 0x1f) << 8)
224 #define   UHSIC_IDLE_WAIT(x)                    (((x) & 0x1f) << 13)
225
226 #define UHSIC_HSRX_CFG1                         0xc0c
227 #define   UHSIC_HS_SYNC_START_DLY(x)            (((x) & 0x1f) << 1)
228
229 #define UHSIC_TX_CFG0                           0xc10
230 #define UHSIC_HS_READY_WAIT_FOR_VALID   (1 << 9)
231 #define UHSIC_MISC_CFG0                         0xc14
232 #define   UHSIC_SUSPEND_EXIT_ON_EDGE            (1 << 7)
233 #define   UHSIC_DETECT_SHORT_CONNECT            (1 << 8)
234 #define   UHSIC_FORCE_XCVR_MODE                 (1 << 15)
235 #define   UHSIC_DISABLE_BUSRESET                (1 << 20)
236 #define UHSIC_MISC_CFG1                         0xc18
237 #define   UHSIC_PLLU_STABLE_COUNT(x)            (((x) & 0xfff) << 2)
238
239 #define UHSIC_PADS_CFG0                         0xc1c
240 #define   UHSIC_TX_RTUNEN                       0xf000
241 #define   UHSIC_TX_RTUNE(x)                     (((x) & 0xf) << 12)
242
243 #define UHSIC_PADS_CFG1                         0xc20
244 #define   UHSIC_PD_BG                           (1 << 2)
245 #define   UHSIC_PD_TX                           (1 << 3)
246 #define   UHSIC_PD_TRK                          (1 << 4)
247 #define   UHSIC_PD_RX                           (1 << 5)
248 #define   UHSIC_PD_ZI                           (1 << 6)
249 #define   UHSIC_RX_SEL                          (1 << 7)
250 #define   UHSIC_RPD_DATA                        (1 << 9)
251 #define   UHSIC_RPD_STROBE                      (1 << 10)
252 #define   UHSIC_RPU_DATA                        (1 << 11)
253 #define   UHSIC_RPU_STROBE                      (1 << 12)
254
255 #define UHSIC_STAT_CFG0                 0xc28
256 #define   UHSIC_CONNECT_DETECT                  (1 << 0)
257
258 #define PMC_USB_DEBOUNCE                        0xec
259 #define   UTMIP_LINE_DEB_CNT(x)                 (((x) & 0xf) << 16)
260
261 #define PMC_USB_AO                              0xf0
262 #define PMC_POWER_DOWN_MASK                     0xffff
263 #define HSIC_RESERVED_P0                        (3 << 14)
264 #define HSIC_STOBE_VAL_PD_P0                    (1 << 13)
265 #define HSIC_DATA_VAL_PD_P0                     (1 << 12)
266 #define USB_ID_PD(inst)                         (1 << ((4*(inst))+3))
267 #define VBUS_WAKEUP_PD(inst)                    (1 << ((4*(inst))+2))
268 #define   USBON_VAL_PD(inst)                    (1 << ((4*(inst))+1))
269 #define   USBON_VAL_PD_P2                       (1 << 9)
270 #define   USBON_VAL_PD_P1                       (1 << 5)
271 #define   USBON_VAL_PD_P0                       (1 << 1)
272 #define   USBOP_VAL_PD(inst)                    (1 << (4*(inst)))
273 #define   USBOP_VAL_PD_P2                       (1 << 8)
274 #define   USBOP_VAL_PD_P1                       (1 << 4)
275 #define   USBOP_VAL_PD_P0                       (1 << 0)
276 #define   PMC_USB_AO_PD_P2                      (0xf << 8)
277 #define   PMC_USB_AO_ID_PD_P0                   (1 << 3)
278 #define   PMC_USB_AO_VBUS_WAKEUP_PD_P0  (1 << 2)
279
280 #define PMC_TRIGGERS                    0x1ec
281 #define   UTMIP_CLR_WALK_PTR(inst)      (1 << (inst))
282 #define   UTMIP_CLR_WALK_PTR_P2         (1 << 2)
283 #define   UTMIP_CLR_WALK_PTR_P1         (1 << 1)
284 #define   UTMIP_CLR_WALK_PTR_P0         (1 << 0)
285 #define   UTMIP_CAP_CFG(inst)   (1 << ((inst)+4))
286 #define   UTMIP_CAP_CFG_P2              (1 << 6)
287 #define   UTMIP_CAP_CFG_P1              (1 << 5)
288 #define   UTMIP_CAP_CFG_P0              (1 << 4)
289 #define   UTMIP_CLR_WAKE_ALARM(inst)            (1 << ((inst)+12))
290 #define   UTMIP_CLR_WAKE_ALARM_P2       (1 << 14)
291
292 #define PMC_PAD_CFG             (0x1f4)
293
294 #define PMC_UTMIP_TERM_PAD_CFG  0x1f8
295 #define   PMC_TCTRL_VAL(x)      (((x) & 0x1f) << 5)
296 #define   PMC_RCTRL_VAL(x)      (((x) & 0x1f) << 0)
297
298 #define UHSIC_SLEEPWALK_REG             0x210
299 #define UHSIC_DATA_RPD_D                (1 << 25)
300 #define UHSIC_STRB_RPD_D                (1 << 24)
301 #define UHSIC_DATA_RPD_C                (1 << 17)
302 #define UHSIC_STRB_RPD_C                (1 << 16)
303 #define UHSIC_DATA_RPD_B                (1 << 9)
304 #define UHSIC_STRB_RPD_B                (1 << 8)
305 #define UHSIC_DATA_RPD_A                (1 << 1)
306 #define UHSIC_STRB_RPD_A                (1 << 0)
307
308 #define PMC_SLEEP_CFG                   0x1fc
309 #define   UTMIP_TCTRL_USE_PMC(inst) (1 << ((8*(inst))+3))
310 #define   UTMIP_TCTRL_USE_PMC_P2                (1 << 19)
311 #define   UTMIP_TCTRL_USE_PMC_P1                (1 << 11)
312 #define   UTMIP_TCTRL_USE_PMC_P0                (1 << 3)
313 #define   UTMIP_RCTRL_USE_PMC(inst) (1 << ((8*(inst))+2))
314 #define   UTMIP_RCTRL_USE_PMC_P2                (1 << 18)
315 #define   UTMIP_RCTRL_USE_PMC_P1                (1 << 10)
316 #define   UTMIP_RCTRL_USE_PMC_P0                (1 << 2)
317 #define   UTMIP_FSLS_USE_PMC(inst)      (1 << ((8*(inst))+1))
318 #define   UTMIP_FSLS_USE_PMC_P2         (1 << 17)
319 #define   UTMIP_FSLS_USE_PMC_P1         (1 << 9)
320 #define   UTMIP_FSLS_USE_PMC_P0         (1 << 1)
321 #define   UTMIP_MASTER_ENABLE(inst) (1 << (8*(inst)))
322 #define   UTMIP_MASTER_ENABLE_P2                (1 << 16)
323 #define   UTMIP_MASTER_ENABLE_P1                (1 << 8)
324 #define   UTMIP_MASTER_ENABLE_P0                (1 << 0)
325 #define UHSIC_MASTER_ENABLE_P0          (1 << 24)
326 #define UHSIC_WAKE_VAL_P0(x)            (((x) & 0xf) << 28)
327
328 #define PMC_SLEEPWALK_CFG               0x200
329 #define   UTMIP_LINEVAL_WALK_EN(inst) (1 << ((8*(inst))+7))
330 #define   UTMIP_LINEVAL_WALK_EN_P2      (1 << 23)
331 #define   UTMIP_LINEVAL_WALK_EN_P1      (1 << 15)
332 #define   UTMIP_LINEVAL_WALK_EN_P0      (1 << 7)
333 #define   UTMIP_WAKE_VAL(inst, x) (((x) & 0xf) << ((8*(inst))+4))
334 #define   UTMIP_WAKE_VAL_P2(x)          (((x) & 0xf) << 20)
335 #define   UTMIP_WAKE_VAL_P1(x)          (((x) & 0xf) << 12)
336 #define   UTMIP_WAKE_VAL_P0(x)          (((x) & 0xf) << 4)
337 #define   WAKE_VAL_NONE         0xc
338 #define   WAKE_VAL_ANY                  0xF
339 #define   WAKE_VAL_FSJ                  0x2
340 #define   WAKE_VAL_FSK                  0x1
341 #define   WAKE_VAL_SE0                  0x0
342
343 #define PMC_SLEEPWALK_REG(inst)         (0x204 + (4*(inst)))
344 #define   UTMIP_USBOP_RPD_A     (1 << 0)
345 #define   UTMIP_USBON_RPD_A     (1 << 1)
346 #define   UTMIP_AP_A                    (1 << 4)
347 #define   UTMIP_AN_A                    (1 << 5)
348 #define   UTMIP_HIGHZ_A         (1 << 6)
349 #define   UTMIP_USBOP_RPD_B     (1 << 8)
350 #define   UTMIP_USBON_RPD_B     (1 << 9)
351 #define   UTMIP_AP_B                    (1 << 12)
352 #define   UTMIP_AN_B                    (1 << 13)
353 #define   UTMIP_HIGHZ_B         (1 << 14)
354 #define   UTMIP_USBOP_RPD_C     (1 << 16)
355 #define   UTMIP_USBON_RPD_C     (1 << 17)
356 #define   UTMIP_AP_C            (1 << 20)
357 #define   UTMIP_AN_C            (1 << 21)
358 #define   UTMIP_HIGHZ_C         (1 << 22)
359 #define   UTMIP_USBOP_RPD_D     (1 << 24)
360 #define   UTMIP_USBON_RPD_D     (1 << 25)
361 #define   UTMIP_AP_D            (1 << 28)
362 #define   UTMIP_AN_D            (1 << 29)
363 #define   UTMIP_HIGHZ_D         (1 << 30)
364
365 #define UTMIP_UHSIC_STATUS              0x214
366 #define   UTMIP_WALK_PTR_VAL(inst)      (0x3 << ((inst)*2))
367 #define   UTMIP_USBOP_VAL(inst)         (1 << ((2*(inst)) + 8))
368 #define   UTMIP_USBOP_VAL_P2            (1 << 12)
369 #define   UTMIP_USBOP_VAL_P1            (1 << 10)
370 #define   UTMIP_USBOP_VAL_P0            (1 << 8)
371 #define   UTMIP_USBON_VAL(inst)         (1 << ((2*(inst)) + 9))
372 #define   UTMIP_USBON_VAL_P2            (1 << 13)
373 #define   UTMIP_USBON_VAL_P1            (1 << 11)
374 #define   UTMIP_USBON_VAL_P0            (1 << 9)
375 #define   UTMIP_WAKE_ALARM(inst)                (1 << ((inst) + 16))
376 #define   UTMIP_WAKE_ALARM_P2   (1 << 18)
377 #define   UTMIP_WAKE_ALARM_P1   (1 << 17)
378 #define   UTMIP_WAKE_ALARM_P0   (1 << 16)
379 #define   UTMIP_WALK_PTR(inst)  (1 << ((inst)*2))
380 #define   UTMIP_WALK_PTR_P2     (1 << 4)
381 #define   UTMIP_WALK_PTR_P1     (1 << 2)
382 #define   UTMIP_WALK_PTR_P0     (1 << 0)
383
384 #define USB1_PREFETCH_ID               6
385 #define USB2_PREFETCH_ID               18
386 #define USB3_PREFETCH_ID               17
387
388 #define PMC_UTMIP_UHSIC_FAKE            0x218
389 #define   USBON_VAL(inst)       (1 << ((4*(inst))+1))
390 #define   USBON_VAL_P2                  (1 << 9)
391 #define   USBON_VAL_P1                  (1 << 5)
392 #define   USBON_VAL_P0                  (1 << 1)
393 #define   USBOP_VAL(inst)       (1 << (4*(inst)))
394 #define   USBOP_VAL_P2                  (1 << 8)
395 #define   USBOP_VAL_P1                  (1 << 4)
396 #define   USBOP_VAL_P0                  (1 << 0)
397
398 #define PMC_UTMIP_BIAS_MASTER_CNTRL 0x30c
399 #define   BIAS_MASTER_PROG_VAL          (1 << 1)
400
401 #define PMC_UTMIP_MASTER_CONFIG         0x310
402 #define   UTMIP_PWR(inst)               (1 << (inst))
403
404 #define FUSE_USB_CALIB_0                0x1F0
405 #define   FUSE_USB_CALIB_XCVR_SETUP(x)  (((x) & 0x7F) << 0)
406
407 /* These values (in milli second) are taken from the battery charging spec */
408 #define TDP_SRC_ON_MS    100
409 #define TDPSRC_CON_MS    40
410
411 #ifdef DEBUG
412 #define DBG(stuff...)   pr_info("tegra3_usb_phy: " stuff)
413 #else
414 #define DBG(stuff...)   do {} while (0)
415 #endif
416
417 #if 0
418 #define PHY_DBG(stuff...)       pr_info("tegra3_usb_phy: " stuff)
419 #else
420 #define PHY_DBG(stuff...)       do {} while (0)
421 #endif
422
423 static u32 utmip_rctrl_val, utmip_tctrl_val;
424 static DEFINE_SPINLOCK(utmip_pad_lock);
425 static int utmip_pad_count;
426
427 static struct tegra_xtal_freq utmip_freq_table[] = {
428         {
429                 .freq = 12000000,
430                 .enable_delay = 0x02,
431                 .stable_count = 0x2F,
432                 .active_delay = 0x04,
433                 .xtal_freq_count = 0x76,
434                 .debounce = 0x7530,
435                 .pdtrk_count = 5,
436         },
437         {
438                 .freq = 13000000,
439                 .enable_delay = 0x02,
440                 .stable_count = 0x33,
441                 .active_delay = 0x05,
442                 .xtal_freq_count = 0x7F,
443                 .debounce = 0x7EF4,
444                 .pdtrk_count = 5,
445         },
446         {
447                 .freq = 19200000,
448                 .enable_delay = 0x03,
449                 .stable_count = 0x4B,
450                 .active_delay = 0x06,
451                 .xtal_freq_count = 0xBB,
452                 .debounce = 0xBB80,
453                 .pdtrk_count = 7,
454         },
455         {
456                 .freq = 26000000,
457                 .enable_delay = 0x04,
458                 .stable_count = 0x66,
459                 .active_delay = 0x09,
460                 .xtal_freq_count = 0xFE,
461                 .debounce = 0xFDE8,
462                 .pdtrk_count = 9,
463         },
464 };
465
466 static struct tegra_xtal_freq uhsic_freq_table[] = {
467         {
468                 .freq = 12000000,
469                 .enable_delay = 0x02,
470                 .stable_count = 0x2F,
471                 .active_delay = 0x0,
472                 .xtal_freq_count = 0x1CA,
473         },
474         {
475                 .freq = 13000000,
476                 .enable_delay = 0x02,
477                 .stable_count = 0x33,
478                 .active_delay = 0x0,
479                 .xtal_freq_count = 0x1F0,
480         },
481         {
482                 .freq = 19200000,
483                 .enable_delay = 0x03,
484                 .stable_count = 0x4B,
485                 .active_delay = 0x0,
486                 .xtal_freq_count = 0x2DD,
487         },
488         {
489                 .freq = 26000000,
490                 .enable_delay = 0x04,
491                 .stable_count = 0x66,
492                 .active_delay = 0x0,
493                 .xtal_freq_count = 0x3E0,
494         },
495 };
496
497 static void usb_phy_fence_read(struct tegra_usb_phy *phy)
498 {
499         /* Fence read for coherency of AHB master intiated writes */
500         if (phy->inst == 0)
501                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB1_PREFETCH_ID));
502         else if (phy->inst == 1)
503                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB2_PREFETCH_ID));
504         else if (phy->inst == 2)
505                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB3_PREFETCH_ID));
506
507         return;
508 }
509
510 static void utmip_setup_pmc_wake_detect(struct tegra_usb_phy *phy)
511 {
512         unsigned long val, pmc_pad_cfg_val;
513         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
514         unsigned  int inst = phy->inst;
515         void __iomem *base = phy->regs;
516         bool port_connected;
517         enum usb_phy_port_speed port_speed;
518
519         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
520
521         /* check for port connect status */
522         val = readl(base + USB_PORTSC);
523         port_connected = val & USB_PORTSC_CCS;
524
525         if (!port_connected)
526                 return;
527
528         port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
529                 HOSTPC1_DEVLC_PSPD_MASK;
530         /*Set PMC MASTER bits to do the following
531         * a. Take over the UTMI drivers
532         * b. set up such that it will take over resume
533         *        if remote wakeup is detected
534         * Prepare PMC to take over suspend-wake detect-drive resume until USB
535         * controller ready
536         */
537
538         /* disable master enable in PMC */
539         val = readl(pmc_base + PMC_SLEEP_CFG);
540         val &= ~UTMIP_MASTER_ENABLE(inst);
541         writel(val, pmc_base + PMC_SLEEP_CFG);
542
543         /* UTMIP_PWR_PX=1 for power savings mode */
544         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
545         val |= UTMIP_PWR(inst);
546         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
547
548         /* config debouncer */
549         val = readl(pmc_base + PMC_USB_DEBOUNCE);
550         val &= ~UTMIP_LINE_DEB_CNT(~0);
551         val |= UTMIP_LINE_DEB_CNT(4);
552         writel(val, pmc_base + PMC_USB_DEBOUNCE);
553
554         /* Make sure nothing is happening on the line with respect to PMC */
555         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
556         val &= ~USBOP_VAL(inst);
557         val &= ~USBON_VAL(inst);
558         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
559
560         /* Make sure wake value for line is none */
561         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
562         val &= ~UTMIP_LINEVAL_WALK_EN(inst);
563         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
564         val = readl(pmc_base + PMC_SLEEP_CFG);
565         val &= ~UTMIP_WAKE_VAL(inst, ~0);
566         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
567         writel(val, pmc_base + PMC_SLEEP_CFG);
568
569         /* turn off pad detectors */
570         val = readl(pmc_base + PMC_USB_AO);
571         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
572         writel(val, pmc_base + PMC_USB_AO);
573
574         /* Remove fake values and make synchronizers work a bit */
575         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
576         val &= ~USBOP_VAL(inst);
577         val &= ~USBON_VAL(inst);
578         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
579
580         /* Enable which type of event can trigger a walk,
581         in this case usb_line_wake */
582         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
583         val |= UTMIP_LINEVAL_WALK_EN(inst);
584         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
585
586         /* Enable which type of event can trigger a walk,
587         * in this case usb_line_wake */
588         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
589         val |= UTMIP_LINEVAL_WALK_EN(inst);
590         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
591
592         /* Clear the walk pointers and wake alarm */
593         val = readl(pmc_base + PMC_TRIGGERS);
594         val |= UTMIP_CLR_WAKE_ALARM(inst) | UTMIP_CLR_WALK_PTR(inst);
595         writel(val, pmc_base + PMC_TRIGGERS);
596
597
598         /* Capture FS/LS pad configurations */
599         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
600         val = readl(pmc_base + PMC_TRIGGERS);
601         val |= UTMIP_CAP_CFG(inst);
602         writel(val, pmc_base + PMC_TRIGGERS);
603         udelay(1);
604         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
605
606         /* BIAS MASTER_ENABLE=0 */
607         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
608         val &= ~BIAS_MASTER_PROG_VAL;
609         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
610
611         /* program walk sequence, maintain a J, followed by a driven K
612         * to signal a resume once an wake event is detected */
613         val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
614         val &= ~UTMIP_AP_A;
615         val |= UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_AN_A |UTMIP_HIGHZ_A |
616                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_AP_B | UTMIP_AN_B |
617                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_AP_C | UTMIP_AN_C |
618                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_AP_D | UTMIP_AN_D;
619         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
620
621         if (port_speed == USB_PHY_PORT_SPEED_LOW) {
622                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
623                 val &= ~(UTMIP_AN_B | UTMIP_HIGHZ_B | UTMIP_AN_C |
624                         UTMIP_HIGHZ_C | UTMIP_AN_D | UTMIP_HIGHZ_D);
625                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
626         } else {
627                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
628                 val &= ~(UTMIP_AP_B | UTMIP_HIGHZ_B | UTMIP_AP_C |
629                         UTMIP_HIGHZ_C | UTMIP_AP_D | UTMIP_HIGHZ_D);
630                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
631         }
632
633         /* turn on pad detectors */
634         val = readl(pmc_base + PMC_USB_AO);
635         val &= ~(USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
636         writel(val, pmc_base + PMC_USB_AO);
637
638         /* Add small delay before usb detectors provide stable line values */
639         mdelay(1);
640
641         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
642         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
643         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
644         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
645
646         phy->remote_wakeup = false;
647
648         /* Turn over pad configuration to PMC  for line wake events*/
649         val = readl(pmc_base + PMC_SLEEP_CFG);
650         val &= ~UTMIP_WAKE_VAL(inst, ~0);
651         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_ANY);
652         val |= UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst);
653         val |= UTMIP_MASTER_ENABLE(inst) | UTMIP_FSLS_USE_PMC(inst);
654         writel(val, pmc_base + PMC_SLEEP_CFG);
655
656         val = readl(base + UTMIP_PMC_WAKEUP0);
657         val |= EVENT_INT_ENB;
658         writel(val, base + UTMIP_PMC_WAKEUP0);
659         PHY_DBG("%s ENABLE_PMC inst = %d\n", __func__, inst);
660 }
661
662 static void utmip_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy)
663 {
664         unsigned long val;
665         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
666         unsigned  int inst = phy->inst;
667         void __iomem *base = phy->regs;
668
669         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
670
671         val = readl(pmc_base + PMC_SLEEP_CFG);
672         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
673         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
674         writel(val, pmc_base + PMC_SLEEP_CFG);
675
676         val = readl(pmc_base + PMC_TRIGGERS);
677         val |= UTMIP_CLR_WAKE_ALARM(inst) | UTMIP_CLR_WALK_PTR(inst);
678         writel(val, pmc_base + PMC_TRIGGERS);
679
680         val = readl(base + UTMIP_PMC_WAKEUP0);
681         val &= ~EVENT_INT_ENB;
682         writel(val, base + UTMIP_PMC_WAKEUP0);
683
684         /* Disable PMC master mode by clearing MASTER_EN */
685         val = readl(pmc_base + PMC_SLEEP_CFG);
686         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
687                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
688         writel(val, pmc_base + PMC_SLEEP_CFG);
689
690         val = readl(pmc_base + PMC_TRIGGERS);
691         val &= ~UTMIP_CAP_CFG(inst);
692         writel(val, pmc_base + PMC_TRIGGERS);
693
694         /* turn off pad detectors */
695         val = readl(pmc_base + PMC_USB_AO);
696         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
697         writel(val, pmc_base + PMC_USB_AO);
698
699         phy->remote_wakeup = false;
700         PHY_DBG("%s DISABLE_PMC inst = %d\n", __func__, inst);
701 }
702
703 bool utmi_phy_remotewake_detected(struct tegra_usb_phy *phy)
704 {
705         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
706         void __iomem *base = phy->regs;
707         unsigned  int inst = phy->inst;
708         u32 val;
709
710         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
711         val = readl(base + UTMIP_PMC_WAKEUP0);
712         if (val & EVENT_INT_ENB) {
713                 val = readl(pmc_base + UTMIP_UHSIC_STATUS);
714                 if (UTMIP_WAKE_ALARM(inst) & val) {
715                         val = readl(pmc_base + PMC_SLEEP_CFG);
716                         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
717                         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
718                         writel(val, pmc_base + PMC_SLEEP_CFG);
719
720                         val = readl(pmc_base + PMC_TRIGGERS);
721                         val |= UTMIP_CLR_WAKE_ALARM(inst) |
722                                 UTMIP_CLR_WALK_PTR(inst);
723                         writel(val, pmc_base + PMC_TRIGGERS);
724
725                         val = readl(base + UTMIP_PMC_WAKEUP0);
726                         val &= ~EVENT_INT_ENB;
727                         writel(val, base + UTMIP_PMC_WAKEUP0);
728                         phy->remote_wakeup = true;
729                         return true;
730                 }
731         }
732         return false;
733 }
734
735 static void utmi_phy_enable_trking_data(struct tegra_usb_phy *phy)
736 {
737         void __iomem *base = IO_ADDRESS(TEGRA_USB_BASE);
738         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
739         static bool init_done = false;
740         u32 val;
741
742         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
743
744         /* Should be done only once after system boot */
745         if (init_done)
746                 return;
747
748         clk_enable(phy->utmi_pad_clk);
749         /* Bias pad MASTER_ENABLE=1 */
750         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
751         val |= BIAS_MASTER_PROG_VAL;
752         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
753
754         /* Setting the tracking length time */
755         val = readl(base + UTMIP_BIAS_CFG1);
756         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
757         val |= UTMIP_BIAS_PDTRK_COUNT(5);
758         writel(val, base + UTMIP_BIAS_CFG1);
759
760         /* Bias PDTRK is Shared and MUST be done from USB1 ONLY, PD_TRK=0 */
761         val = readl(base + UTMIP_BIAS_CFG1);
762         val &= ~UTMIP_BIAS_PDTRK_POWERDOWN;
763         writel(val, base + UTMIP_BIAS_CFG1);
764
765         val = readl(base + UTMIP_BIAS_CFG1);
766         val |= UTMIP_BIAS_PDTRK_POWERUP;
767         writel(val, base + UTMIP_BIAS_CFG1);
768
769         /* Wait for 25usec */
770         udelay(25);
771
772         /* Bias pad MASTER_ENABLE=0 */
773         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
774         val &= ~BIAS_MASTER_PROG_VAL;
775         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
776
777         /* Wait for 1usec */
778         udelay(1);
779
780         /* Bias pad MASTER_ENABLE=1 */
781         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
782         val |= BIAS_MASTER_PROG_VAL;
783         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
784
785         /* Read RCTRL and TCTRL from UTMIP space */
786         val = readl(base + UTMIP_BIAS_STS0);
787         utmip_rctrl_val = ffz(UTMIP_RCTRL_VAL(val));
788         utmip_tctrl_val = ffz(UTMIP_TCTRL_VAL(val));
789
790         /* PD_TRK=1 */
791         val = readl(base + UTMIP_BIAS_CFG1);
792         val |= UTMIP_BIAS_PDTRK_POWERDOWN;
793         writel(val, base + UTMIP_BIAS_CFG1);
794
795         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
796         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
797         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
798         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
799         clk_disable(phy->utmi_pad_clk);
800         init_done = true;
801 }
802
803 static void utmip_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy)
804 {
805         unsigned long val;
806         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
807         unsigned  int inst = phy->inst;
808
809         /* power down UTMIP interfaces */
810         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
811         val |= UTMIP_PWR(inst);
812         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
813
814         /* setup sleep walk usb controller */
815         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
816                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
817                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
818                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
819         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
820
821         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
822         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
823         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
824         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
825
826         /* Turn over pad configuration to PMC */
827         val = readl(pmc_base + PMC_SLEEP_CFG);
828         val &= ~UTMIP_WAKE_VAL(inst, ~0);
829         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE) |
830                 UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
831                 UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst);
832         writel(val, pmc_base + PMC_SLEEP_CFG);
833         PHY_DBG("%s ENABLE_PMC inst = %d\n", __func__, inst);
834 }
835
836 static void utmip_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
837 {
838         unsigned long val;
839         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
840         unsigned  int inst = phy->inst;
841
842         /* Disable PMC master mode by clearing MASTER_EN */
843         val = readl(pmc_base + PMC_SLEEP_CFG);
844         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
845                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
846         writel(val, pmc_base + PMC_SLEEP_CFG);
847         mdelay(1);
848         PHY_DBG("%s DISABLE_PMC inst = %d\n", __func__, inst);
849 }
850
851 static void uhsic_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy)
852 {
853         unsigned long val;
854         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
855
856         /* turn on pad detectors for HSIC*/
857         val = readl(pmc_base + PMC_USB_AO);
858         val |= (HSIC_RESERVED_P0 | HSIC_STOBE_VAL_PD_P0 | HSIC_DATA_VAL_PD_P0);
859         writel(val, pmc_base + PMC_USB_AO);
860
861         /* enable pull downs on HSIC PMC */
862         val = UHSIC_STRB_RPD_A | UHSIC_DATA_RPD_A | UHSIC_STRB_RPD_B |
863                 UHSIC_DATA_RPD_B | UHSIC_STRB_RPD_C | UHSIC_DATA_RPD_C |
864                 UHSIC_STRB_RPD_D | UHSIC_DATA_RPD_D;
865         writel(val, pmc_base + UHSIC_SLEEPWALK_REG);
866
867         /* Turn over pad configuration to PMC */
868         val = readl(pmc_base + PMC_SLEEP_CFG);
869         val &= ~UHSIC_WAKE_VAL_P0(~0);
870         val |= UHSIC_WAKE_VAL_P0(WAKE_VAL_NONE) | UHSIC_MASTER_ENABLE_P0;
871         writel(val, pmc_base + PMC_SLEEP_CFG);
872 }
873
874 static void uhsic_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
875 {
876         unsigned long val;
877         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
878
879         /* turn on pad detectors for HSIC*/
880         val = readl(pmc_base + PMC_USB_AO);
881         val &= ~(HSIC_RESERVED_P0 | HSIC_STOBE_VAL_PD_P0 | HSIC_DATA_VAL_PD_P0);
882         writel(val, pmc_base + PMC_USB_AO);
883
884         /* Disable PMC master mode by clearing MASTER_EN */
885         val = readl(pmc_base + PMC_SLEEP_CFG);
886         val &= ~(UHSIC_MASTER_ENABLE_P0);
887         writel(val, pmc_base + PMC_SLEEP_CFG);
888         mdelay(1);
889 }
890
891 static void usb_phy_power_down_pmc(void)
892 {
893         unsigned long val;
894         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
895
896         /* power down all 3 UTMIP interfaces */
897         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
898         val |= UTMIP_PWR(0) | UTMIP_PWR(1) | UTMIP_PWR(2);
899         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
900
901         /* turn on pad detectors */
902         writel(PMC_POWER_DOWN_MASK, pmc_base + PMC_USB_AO);
903
904         /* setup sleep walk fl all 3 usb controllers */
905         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
906                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
907                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
908                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
909         writel(val, pmc_base + PMC_SLEEPWALK_REG(0));
910         writel(val, pmc_base + PMC_SLEEPWALK_REG(1));
911         writel(val, pmc_base + PMC_SLEEPWALK_REG(2));
912
913         /* enable pull downs on HSIC PMC */
914         val = UHSIC_STRB_RPD_A | UHSIC_DATA_RPD_A | UHSIC_STRB_RPD_B |
915                 UHSIC_DATA_RPD_B | UHSIC_STRB_RPD_C | UHSIC_DATA_RPD_C |
916                 UHSIC_STRB_RPD_D | UHSIC_DATA_RPD_D;
917         writel(val, pmc_base + UHSIC_SLEEPWALK_REG);
918
919         /* Turn over pad configuration to PMC */
920         val = readl(pmc_base + PMC_SLEEP_CFG);
921         val &= ~UTMIP_WAKE_VAL(0, ~0);
922         val &= ~UTMIP_WAKE_VAL(1, ~0);
923         val &= ~UTMIP_WAKE_VAL(2, ~0);
924         val &= ~UHSIC_WAKE_VAL_P0(~0);
925         val |= UTMIP_WAKE_VAL(0, WAKE_VAL_NONE) | UHSIC_WAKE_VAL_P0(WAKE_VAL_NONE) |
926         UTMIP_WAKE_VAL(1, WAKE_VAL_NONE) | UTMIP_WAKE_VAL(2, WAKE_VAL_NONE) |
927         UTMIP_RCTRL_USE_PMC(0) | UTMIP_RCTRL_USE_PMC(1) | UTMIP_RCTRL_USE_PMC(2) |
928         UTMIP_TCTRL_USE_PMC(0) | UTMIP_TCTRL_USE_PMC(1) | UTMIP_TCTRL_USE_PMC(2) |
929         UTMIP_FSLS_USE_PMC(0) | UTMIP_FSLS_USE_PMC(1) | UTMIP_FSLS_USE_PMC(2) |
930         UTMIP_MASTER_ENABLE(0) | UTMIP_MASTER_ENABLE(1) | UTMIP_MASTER_ENABLE(2) |
931         UHSIC_MASTER_ENABLE_P0;
932         writel(val, pmc_base + PMC_SLEEP_CFG);
933 }
934
935 static int usb_phy_bringup_host_controller(struct tegra_usb_phy *phy)
936 {
937         unsigned long val;
938         void __iomem *base = phy->regs;
939
940         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
941         PHY_DBG("[%d] USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n", __LINE__,
942                 readl(base + USB_USBSTS), readl(base + USB_PORTSC),
943                                                         phy->port_speed);
944
945         /* Device is plugged in when system is in LP0 */
946         /* Bring up the controller from LP0*/
947         val = readl(base + USB_USBCMD);
948         val |= USB_CMD_RESET;
949         writel(val, base + USB_USBCMD);
950
951         if (usb_phy_reg_status_wait(base + USB_USBCMD,
952                 USB_CMD_RESET, 0, 2500) < 0) {
953                 pr_err("%s: timeout waiting for reset\n", __func__);
954         }
955
956         val = readl(base + USB_USBMODE);
957         val &= ~USB_USBMODE_MASK;
958         val |= USB_USBMODE_HOST;
959         writel(val, base + USB_USBMODE);
960
961         val = readl(base + HOSTPC1_DEVLC);
962         val &= ~HOSTPC1_DEVLC_PTS(~0);
963         val |= HOSTPC1_DEVLC_STS;
964         writel(val, base + HOSTPC1_DEVLC);
965
966         /* Enable Port Power */
967         val = readl(base + USB_PORTSC);
968         val |= USB_PORTSC_PP;
969         writel(val, base + USB_PORTSC);
970         udelay(10);
971
972         /* Check if the phy resume from LP0. When the phy resume from LP0
973          * USB register will be reset.to zero */
974         if (!readl(base + USB_ASYNCLISTADDR)) {
975                 /* Program the field PTC based on the saved speed mode */
976                 val = readl(base + USB_PORTSC);
977                 val &= ~USB_PORTSC_PTC(~0);
978                 if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH)
979                         val |= USB_PORTSC_PTC(5);
980                 else if (phy->port_speed == USB_PHY_PORT_SPEED_FULL)
981                         val |= USB_PORTSC_PTC(6);
982                 else if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
983                         val |= USB_PORTSC_PTC(7);
984                 writel(val, base + USB_PORTSC);
985                 udelay(10);
986
987                 /* Disable test mode by setting PTC field to NORMAL_OP */
988                 val = readl(base + USB_PORTSC);
989                 val &= ~USB_PORTSC_PTC(~0);
990                 writel(val, base + USB_PORTSC);
991                 udelay(10);
992         }
993
994         /* Poll until CCS is enabled */
995         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
996                                                  USB_PORTSC_CCS, 2000)) {
997                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
998         }
999
1000         /* Poll until PE is enabled */
1001         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_PE,
1002                                                  USB_PORTSC_PE, 2000)) {
1003                 pr_err("%s: timeout waiting for USB_PORTSC_PE\n", __func__);
1004         }
1005
1006         /* Clear the PCI status, to avoid an interrupt taken upon resume */
1007         val = readl(base + USB_USBSTS);
1008         val |= USB_USBSTS_PCI;
1009         writel(val, base + USB_USBSTS);
1010
1011         if (!phy->remote_wakeup) {
1012                 /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
1013                 val = readl(base + USB_PORTSC);
1014                 if ((val & USB_PORTSC_PP) && (val & USB_PORTSC_PE)) {
1015                         val |= USB_PORTSC_SUSP;
1016                         writel(val, base + USB_PORTSC);
1017                         /* Need a 4ms delay before the controller goes to suspend */
1018                         mdelay(4);
1019
1020                         /* Wait until port suspend completes */
1021                         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_SUSP,
1022                                                          USB_PORTSC_SUSP, 1000)) {
1023                                 pr_err("%s: timeout waiting for PORT_SUSPEND\n",
1024                                                                         __func__);
1025                         }
1026                 }
1027         }
1028         PHY_DBG("[%d] USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n", __LINE__,
1029                 readl(base + USB_USBSTS), readl(base + USB_PORTSC),
1030                                                         phy->port_speed);
1031
1032         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1033                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1034         return 0;
1035 }
1036
1037 static void usb_phy_wait_for_sof(struct tegra_usb_phy *phy)
1038 {
1039         unsigned long val;
1040         void __iomem *base = phy->regs;
1041
1042         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1043
1044         val = readl(base + USB_USBSTS);
1045         writel(val, base + USB_USBSTS);
1046         udelay(20);
1047         /* wait for two SOFs */
1048         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1049                 USB_USBSTS_SRI, 2500))
1050                 pr_err("%s: timeout waiting for SOF\n", __func__);
1051
1052         val = readl(base + USB_USBSTS);
1053         writel(val, base + USB_USBSTS);
1054         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI, 0, 2500))
1055                 pr_err("%s: timeout waiting for SOF\n", __func__);
1056
1057         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1058                         USB_USBSTS_SRI, 2500))
1059                 pr_err("%s: timeout waiting for SOF\n", __func__);
1060
1061         udelay(20);
1062 }
1063
1064 static unsigned int utmi_phy_xcvr_setup_value(struct tegra_usb_phy *phy)
1065 {
1066         struct tegra_utmi_config *cfg = &phy->pdata->u_cfg.utmi;
1067         signed long val;
1068
1069         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1070
1071         if (cfg->xcvr_use_fuses) {
1072                 val = FUSE_USB_CALIB_XCVR_SETUP(
1073                                 tegra_fuse_readl(FUSE_USB_CALIB_0));
1074                 if (cfg->xcvr_setup_offset <= UTMIP_XCVR_MAX_OFFSET)
1075                         val = val + cfg->xcvr_setup_offset;
1076
1077                 if (val > UTMIP_XCVR_SETUP_MAX_VALUE) {
1078                         val = UTMIP_XCVR_SETUP_MAX_VALUE;
1079                         pr_info("%s: reset XCVR_SETUP to max value\n",
1080                                  __func__);
1081                 } else if (val < UTMIP_XCVR_SETUP_MIN_VALUE) {
1082                         val = UTMIP_XCVR_SETUP_MIN_VALUE;
1083                         pr_info("%s: reset XCVR_SETUP to min value\n",
1084                                  __func__);
1085                 }
1086         } else {
1087                 val = cfg->xcvr_setup;
1088         }
1089
1090         return (unsigned int) val;
1091 }
1092
1093 static int utmi_phy_open(struct tegra_usb_phy *phy)
1094 {
1095         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1096         unsigned long parent_rate, val;
1097         int i;
1098
1099         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1100
1101         phy->utmi_pad_clk = clk_get_sys("utmip-pad", NULL);
1102         if (IS_ERR(phy->utmi_pad_clk)) {
1103                 pr_err("%s: can't get utmip pad clock\n", __func__);
1104                 return PTR_ERR(phy->utmi_pad_clk);
1105         }
1106
1107         phy->utmi_xcvr_setup = utmi_phy_xcvr_setup_value(phy);
1108
1109         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
1110         for (i = 0; i < ARRAY_SIZE(utmip_freq_table); i++) {
1111                 if (utmip_freq_table[i].freq == parent_rate) {
1112                         phy->freq = &utmip_freq_table[i];
1113                         break;
1114                 }
1115         }
1116         if (!phy->freq) {
1117                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
1118                 return -EINVAL;
1119         }
1120
1121         /* Power-up the VBUS detector for UTMIP PHY */
1122         val = readl(pmc_base + PMC_USB_AO);
1123         val &= ~(PMC_USB_AO_VBUS_WAKEUP_PD_P0 | PMC_USB_AO_ID_PD_P0);
1124         writel((val | PMC_USB_AO_PD_P2), (pmc_base + PMC_USB_AO));
1125
1126         utmip_powerup_pmc_wake_detect(phy);
1127
1128         return 0;
1129 }
1130
1131 static void utmi_phy_close(struct tegra_usb_phy *phy)
1132 {
1133         unsigned long val;
1134         void __iomem *base = phy->regs;
1135
1136         DBG("%s inst:[%d]\n", __func__, phy->inst);
1137
1138         /* Disable PHY clock valid interrupts while going into suspend*/
1139         if (phy->pdata->u_data.host.hot_plug) {
1140                 val = readl(base + USB_SUSP_CTRL);
1141                 val &= ~USB_PHY_CLK_VALID_INT_ENB;
1142                 writel(val, base + USB_SUSP_CTRL);
1143         }
1144
1145         val = readl(base + USB_PORTSC);
1146         val |= USB_PORTSC_WKCN;
1147         writel(val, base + USB_PORTSC);
1148
1149         clk_put(phy->utmi_pad_clk);
1150 }
1151
1152 static int utmi_phy_pad_power_on(struct tegra_usb_phy *phy)
1153 {
1154         unsigned long val, flags;
1155         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1156
1157         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1158
1159         clk_enable(phy->utmi_pad_clk);
1160
1161         spin_lock_irqsave(&utmip_pad_lock, flags);
1162         utmip_pad_count++;
1163
1164         val = readl(pad_base + UTMIP_BIAS_CFG0);
1165         val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
1166         val |= UTMIP_HSSQUELCH_LEVEL(0x2) | UTMIP_HSDISCON_LEVEL(0x1) |
1167                 UTMIP_HSDISCON_LEVEL_MSB;
1168         writel(val, pad_base + UTMIP_BIAS_CFG0);
1169
1170         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1171
1172         clk_disable(phy->utmi_pad_clk);
1173
1174         return 0;
1175 }
1176
1177 static int utmi_phy_pad_power_off(struct tegra_usb_phy *phy)
1178 {
1179         unsigned long val, flags;
1180         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1181
1182         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1183
1184         clk_enable(phy->utmi_pad_clk);
1185         spin_lock_irqsave(&utmip_pad_lock, flags);
1186
1187         if (!utmip_pad_count) {
1188                 pr_err("%s: utmip pad already powered off\n", __func__);
1189                 goto out;
1190         }
1191         if (--utmip_pad_count == 0) {
1192                 val = readl(pad_base + UTMIP_BIAS_CFG0);
1193                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
1194                 val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) | UTMIP_HSDISCON_LEVEL(~0) |
1195                         UTMIP_HSDISCON_LEVEL_MSB);
1196                 writel(val, pad_base + UTMIP_BIAS_CFG0);
1197         }
1198 out:
1199         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1200         clk_disable(phy->utmi_pad_clk);
1201
1202         return 0;
1203 }
1204
1205 static int utmi_phy_irq(struct tegra_usb_phy *phy)
1206 {
1207         void __iomem *base = phy->regs;
1208         unsigned long val = 0;
1209
1210         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1211         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1212                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1213         DBG("USB_USBMODE[0x%x] USB_USBCMD[0x%x]\n",
1214                         readl(base + USB_USBMODE), readl(base + USB_USBCMD));
1215
1216         usb_phy_fence_read(phy);
1217         /* check if there is any remote wake event */
1218         if (utmi_phy_remotewake_detected(phy))
1219                 pr_info("%s: utmip remote wake detected\n", __func__);
1220
1221         if (phy->pdata->u_data.host.hot_plug) {
1222                 val = readl(base + USB_SUSP_CTRL);
1223                 if ((val  & USB_PHY_CLK_VALID_INT_STS)) {
1224                         val &= ~USB_PHY_CLK_VALID_INT_ENB |
1225                                         USB_PHY_CLK_VALID_INT_STS;
1226                         writel(val , (base + USB_SUSP_CTRL));
1227                         pr_info("%s: usb device plugged-in\n", __func__);
1228                         val = readl(base + USB_USBSTS);
1229                         if (!(val  & USB_USBSTS_PCI))
1230                                 return IRQ_NONE;
1231                         val = readl(base + USB_PORTSC);
1232                         val &= ~(USB_PORTSC_WKCN | USB_PORTSC_RWC_BITS);
1233                         writel(val , (base + USB_PORTSC));
1234                 }
1235         }
1236
1237         return IRQ_HANDLED;
1238 }
1239
1240 static void utmi_phy_enable_obs_bus(struct tegra_usb_phy *phy)
1241 {
1242         unsigned long val;
1243         void __iomem *base = phy->regs;
1244
1245         /* (2LS WAR)is not required for LS and FS devices and is only for HS */
1246         if ((phy->port_speed == USB_PHY_PORT_SPEED_LOW) ||
1247                 (phy->port_speed == USB_PHY_PORT_SPEED_FULL)) {
1248                 /* do not enable the OBS bus */
1249                 val = readl(base + UTMIP_MISC_CFG0);
1250                 val &= ~(UTMIP_DPDM_OBSERVE_SEL(~0));
1251                 writel(val, base + UTMIP_MISC_CFG0);
1252                 DBG("%s(%d) Disable OBS bus\n", __func__, __LINE__);
1253                 return;
1254         }
1255         /* Force DP/DM pulldown active for Host mode */
1256         val = readl(base + UTMIP_MISC_CFG0);
1257         val |= FORCE_PULLDN_DM | FORCE_PULLDN_DP |
1258                         COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS;
1259         writel(val, base + UTMIP_MISC_CFG0);
1260         val = readl(base + UTMIP_MISC_CFG0);
1261         val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1262         if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
1263                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
1264         else
1265                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
1266         writel(val, base + UTMIP_MISC_CFG0);
1267         udelay(1);
1268
1269         val = readl(base + UTMIP_MISC_CFG0);
1270         val |= UTMIP_DPDM_OBSERVE;
1271         writel(val, base + UTMIP_MISC_CFG0);
1272         udelay(10);
1273         DBG("%s(%d) Enable OBS bus\n", __func__, __LINE__);
1274         PHY_DBG("ENABLE_OBS_BUS\n");
1275 }
1276
1277 static int utmi_phy_disable_obs_bus(struct tegra_usb_phy *phy)
1278 {
1279         unsigned long val;
1280         void __iomem *base = phy->regs;
1281
1282         /* check if OBS bus is already enabled */
1283         val = readl(base + UTMIP_MISC_CFG0);
1284         if (val & UTMIP_DPDM_OBSERVE) {
1285                 PHY_DBG("DISABLE_OBS_BUS\n");
1286                 /* Change the UTMIP OBS bus to drive SE0 */
1287                 val = readl(base + UTMIP_MISC_CFG0);
1288                 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1289                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_SE0;
1290                 writel(val, base + UTMIP_MISC_CFG0);
1291
1292                 /* Wait for 3us(2 LS bit times) */
1293                 udelay(3);
1294
1295                 /* Release UTMIP OBS bus */
1296                 val = readl(base + UTMIP_MISC_CFG0);
1297                 val &= ~UTMIP_DPDM_OBSERVE;
1298                 writel(val, base + UTMIP_MISC_CFG0);
1299
1300                 /* Release DP/DM pulldown for Host mode */
1301                 val = readl(base + UTMIP_MISC_CFG0);
1302                 val &= ~(FORCE_PULLDN_DM | FORCE_PULLDN_DP |
1303                                 COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS);
1304                 writel(val, base + UTMIP_MISC_CFG0);
1305
1306                 val = readl(base + USB_USBCMD);
1307                 val |= USB_USBCMD_RS;
1308                 writel(val, base + USB_USBCMD);
1309                 if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
1310                                                          USB_USBCMD_RS, 2000)) {
1311                         pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
1312                         return -ETIMEDOUT;
1313                 }
1314         }
1315         return 0;
1316 }
1317
1318 static int utmi_phy_post_resume(struct tegra_usb_phy *phy)
1319 {
1320         unsigned long val;
1321         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1322         unsigned  int inst = phy->inst;
1323
1324         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1325         val = readl(pmc_base + PMC_SLEEP_CFG);
1326         /* if PMC is not disabled by now then disable it */
1327         if (val & UTMIP_MASTER_ENABLE(inst)) {
1328                 utmip_phy_disable_pmc_bus_ctrl(phy);
1329         }
1330
1331         utmi_phy_disable_obs_bus(phy);
1332
1333         return 0;
1334 }
1335
1336 static int utmi_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1337 {
1338         unsigned long val;
1339         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1340         void __iomem *base = phy->regs;
1341         unsigned  int inst = phy->inst;
1342
1343         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1344         phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
1345                         HOSTPC1_DEVLC_PSPD_MASK;
1346
1347         if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH) {
1348                 /* Disable interrupts */
1349                 writel(0, base + USB_USBINTR);
1350                 /* Clear the run bit to stop SOFs - 2LS WAR */
1351                 val = readl(base + USB_USBCMD);
1352                 val &= ~USB_USBCMD_RS;
1353                 writel(val, base + USB_USBCMD);
1354                 if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
1355                                                          USB_USBSTS_HCH, 2000)) {
1356                         pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
1357                 }
1358         }
1359
1360         val = readl(pmc_base + PMC_SLEEP_CFG);
1361         if (val & UTMIP_MASTER_ENABLE(inst)) {
1362                 if (!remote_wakeup)
1363                         utmip_phy_disable_pmc_bus_ctrl(phy);
1364         } else {
1365                 utmi_phy_enable_obs_bus(phy);
1366         }
1367
1368         return 0;
1369 }
1370
1371 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
1372 {
1373         unsigned long val;
1374         void __iomem *base = phy->regs;
1375
1376         PHY_DBG("%s(%d) inst:[%d] BEGIN\n", __func__, __LINE__, phy->inst);
1377         if (!phy->phy_clk_on) {
1378                 PHY_DBG("%s(%d) inst:[%d] phy clk is already off\n",
1379                                         __func__, __LINE__, phy->inst);
1380                 return 0;
1381         }
1382
1383         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1384                 utmip_powerdown_pmc_wake_detect(phy);
1385
1386                 val = readl(base + USB_SUSP_CTRL);
1387                 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
1388                 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
1389                 writel(val, base + USB_SUSP_CTRL);
1390
1391                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1392                 val |= UTMIP_PD_CHRG;
1393                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1394         } else {
1395                 phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
1396                                 HOSTPC1_DEVLC_PSPD_MASK;
1397
1398                 /* Disable interrupts */
1399                 writel(0, base + USB_USBINTR);
1400
1401                 /* Clear the run bit to stop SOFs - 2LS WAR */
1402                 val = readl(base + USB_USBCMD);
1403                 val &= ~USB_USBCMD_RS;
1404                 writel(val, base + USB_USBCMD);
1405
1406                 if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
1407                                                          USB_USBSTS_HCH, 2000)) {
1408                         pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
1409                 }
1410                 utmip_setup_pmc_wake_detect(phy);
1411         }
1412
1413         if (!phy->pdata->u_data.host.hot_plug) {
1414                 val = readl(base + UTMIP_XCVR_CFG0);
1415                 val |= (UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
1416                          UTMIP_FORCE_PDZI_POWERDOWN);
1417                 writel(val, base + UTMIP_XCVR_CFG0);
1418         }
1419
1420         val = readl(base + UTMIP_XCVR_CFG1);
1421         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1422                    UTMIP_FORCE_PDDR_POWERDOWN;
1423         writel(val, base + UTMIP_XCVR_CFG1);
1424
1425         val = readl(base + UTMIP_BIAS_CFG1);
1426         val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
1427         writel(val, base + UTMIP_BIAS_CFG1);
1428
1429         utmi_phy_pad_power_off(phy);
1430
1431         if (phy->pdata->u_data.host.hot_plug) {
1432                 bool enable_hotplug = true;
1433                 /* if it is OTG port then make sure to enable hot-plug feature
1434                    only if host adaptor is connected, i.e id is low */
1435                 if (phy->pdata->port_otg) {
1436                         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1437                         enable_hotplug = (val & USB_ID_STATUS) ? false : true;
1438                 }
1439                 if (enable_hotplug) {
1440                         val = readl(base + USB_PORTSC);
1441                         val |= USB_PORTSC_WKCN;
1442                         writel(val, base + USB_PORTSC);
1443
1444                         val = readl(base + USB_SUSP_CTRL);
1445                         val |= USB_PHY_CLK_VALID_INT_ENB;
1446                         writel(val, base + USB_SUSP_CTRL);
1447                 } else {
1448                         /* Disable PHY clock valid interrupts while going into suspend*/
1449                         val = readl(base + USB_SUSP_CTRL);
1450                         val &= ~USB_PHY_CLK_VALID_INT_ENB;
1451                         writel(val, base + USB_SUSP_CTRL);
1452                 }
1453         }
1454
1455         val = readl(base + HOSTPC1_DEVLC);
1456         val |= HOSTPC1_DEVLC_PHCD;
1457         writel(val, base + HOSTPC1_DEVLC);
1458
1459         if (!phy->pdata->u_data.host.hot_plug) {
1460                 val = readl(base + USB_SUSP_CTRL);
1461                 val |= UTMIP_RESET;
1462                 writel(val, base + USB_SUSP_CTRL);
1463         }
1464
1465         phy->phy_clk_on = false;
1466         phy->hw_accessible = false;
1467
1468         PHY_DBG("%s(%d) inst:[%d] END\n", __func__, __LINE__, phy->inst);
1469
1470         return 0;
1471 }
1472
1473
1474 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
1475 {
1476         unsigned long val;
1477         void __iomem *base = phy->regs;
1478         struct tegra_utmi_config *config = &phy->pdata->u_cfg.utmi;
1479
1480         PHY_DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1481         if (phy->phy_clk_on) {
1482                 PHY_DBG("%s(%d) inst:[%d] phy clk is already On\n",
1483                                         __func__, __LINE__, phy->inst);
1484                 return 0;
1485         }
1486         val = readl(base + USB_SUSP_CTRL);
1487         val |= UTMIP_RESET;
1488         writel(val, base + USB_SUSP_CTRL);
1489
1490         val = readl(base + UTMIP_TX_CFG0);
1491         val |= UTMIP_FS_PREABMLE_J;
1492         writel(val, base + UTMIP_TX_CFG0);
1493
1494         val = readl(base + UTMIP_HSRX_CFG0);
1495         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
1496         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
1497         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
1498         writel(val, base + UTMIP_HSRX_CFG0);
1499
1500         val = readl(base + UTMIP_HSRX_CFG1);
1501         val &= ~UTMIP_HS_SYNC_START_DLY(~0);
1502         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
1503         writel(val, base + UTMIP_HSRX_CFG1);
1504
1505         val = readl(base + UTMIP_DEBOUNCE_CFG0);
1506         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
1507         val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
1508         writel(val, base + UTMIP_DEBOUNCE_CFG0);
1509
1510         val = readl(base + UTMIP_MISC_CFG0);
1511         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
1512         writel(val, base + UTMIP_MISC_CFG0);
1513
1514         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1515                 val = readl(base + USB_SUSP_CTRL);
1516                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
1517                 writel(val, base + USB_SUSP_CTRL);
1518
1519                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1520                 val &= ~UTMIP_PD_CHRG;
1521                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1522         } else {
1523                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1524                 val |= UTMIP_PD_CHRG;
1525                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1526         }
1527
1528         utmi_phy_pad_power_on(phy);
1529
1530         val = readl(base + UTMIP_XCVR_CFG0);
1531         val &= ~(UTMIP_XCVR_LSBIAS_SEL | UTMIP_FORCE_PD_POWERDOWN |
1532                  UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN |
1533                  UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_LSFSLEW(~0) |
1534                  UTMIP_XCVR_LSRSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
1535         val |= UTMIP_XCVR_SETUP(phy->utmi_xcvr_setup);
1536         val |= UTMIP_XCVR_SETUP_MSB(XCVR_SETUP_MSB_CALIB(phy->utmi_xcvr_setup));
1537         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
1538         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
1539         val |= UTMIP_XCVR_HSSLEW_MSB(0x8);
1540         writel(val, base + UTMIP_XCVR_CFG0);
1541
1542         val = readl(base + UTMIP_XCVR_CFG1);
1543         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1544                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
1545         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
1546         writel(val, base + UTMIP_XCVR_CFG1);
1547
1548         val = readl(base + UTMIP_BIAS_CFG1);
1549         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
1550         val |= UTMIP_BIAS_PDTRK_COUNT(phy->freq->pdtrk_count);
1551         writel(val, base + UTMIP_BIAS_CFG1);
1552
1553         val = readl(base + UTMIP_SPARE_CFG0);
1554         val &= ~FUSE_SETUP_SEL;
1555         val |= FUSE_ATERM_SEL;
1556         writel(val, base + UTMIP_SPARE_CFG0);
1557
1558         val = readl(base + USB_SUSP_CTRL);
1559         val |= UTMIP_PHY_ENABLE;
1560         writel(val, base + USB_SUSP_CTRL);
1561
1562         val = readl(base + USB_SUSP_CTRL);
1563         val &= ~UTMIP_RESET;
1564         writel(val, base + USB_SUSP_CTRL);
1565
1566         val = readl(base + HOSTPC1_DEVLC);
1567         val &= ~HOSTPC1_DEVLC_PHCD;
1568         writel(val, base + HOSTPC1_DEVLC);
1569
1570         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1571                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500))
1572                 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
1573
1574         utmi_phy_enable_trking_data(phy);
1575
1576         if (phy->inst == 2)
1577                 writel(0, base + ICUSB_CTRL);
1578
1579         val = readl(base + USB_USBMODE);
1580         val &= ~USB_USBMODE_MASK;
1581         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST)
1582                 val |= USB_USBMODE_HOST;
1583         else
1584                 val |= USB_USBMODE_DEVICE;
1585         writel(val, base + USB_USBMODE);
1586
1587         val = readl(base + HOSTPC1_DEVLC);
1588         val &= ~HOSTPC1_DEVLC_PTS(~0);
1589         val |= HOSTPC1_DEVLC_STS;
1590         writel(val, base + HOSTPC1_DEVLC);
1591
1592         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE)
1593                 utmip_powerup_pmc_wake_detect(phy);
1594         phy->phy_clk_on = true;
1595         phy->hw_accessible = true;
1596         PHY_DBG("%s(%d) End inst:[%d]\n", __func__, __LINE__, phy->inst);
1597         return 0;
1598 }
1599
1600 static void utmi_phy_restore_start(struct tegra_usb_phy *phy)
1601 {
1602         unsigned long val;
1603         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1604         int inst = phy->inst;
1605
1606         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1607         val = readl(pmc_base + UTMIP_UHSIC_STATUS);
1608         /* check whether we wake up from the remote resume */
1609         if (UTMIP_WALK_PTR_VAL(inst) & val) {
1610                 phy->remote_wakeup = true;
1611         } else {
1612                 if (!((UTMIP_USBON_VAL(phy->inst) |
1613                         UTMIP_USBOP_VAL(phy->inst)) & val)) {
1614                                 utmip_phy_disable_pmc_bus_ctrl(phy);
1615                 }
1616         }
1617         utmi_phy_enable_obs_bus(phy);
1618 }
1619
1620 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
1621 {
1622         unsigned long val;
1623         void __iomem *base = phy->regs;
1624         int wait_time_us = 25000; /* FPR should be set by this time */
1625
1626         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1627         /* check whether we wake up from the remote resume */
1628         if (phy->remote_wakeup) {
1629                 /* wait until SUSPEND and RESUME bit is cleared on remote resume */
1630                 do {
1631                         val = readl(base + USB_PORTSC);
1632                         udelay(1);
1633                         if (wait_time_us == 0) {
1634                                 PHY_DBG("%s PMC REMOTE WAKEUP FPR timeout val = 0x%x instance = %d\n", __func__, val, phy->inst);
1635                                 utmip_phy_disable_pmc_bus_ctrl(phy);
1636                                 utmi_phy_post_resume(phy);
1637                                 return;
1638                         }
1639                         wait_time_us--;
1640                 } while (val & (USB_PORTSC_RESUME | USB_PORTSC_SUSP));
1641
1642                 /* wait for 25 ms to port resume complete */
1643                 msleep(25);
1644                 /* disable PMC master control */
1645                 utmip_phy_disable_pmc_bus_ctrl(phy);
1646
1647                 /* Clear PCI and SRI bits to avoid an interrupt upon resume */
1648                 val = readl(base + USB_USBSTS);
1649                 writel(val, base + USB_USBSTS);
1650                 /* wait to avoid SOF if there is any */
1651                 if (usb_phy_reg_status_wait(base + USB_USBSTS,
1652                         USB_USBSTS_SRI, USB_USBSTS_SRI, 2500) < 0) {
1653                         pr_err("%s: timeout waiting for SOF\n", __func__);
1654                 }
1655                 utmi_phy_post_resume(phy);
1656         }
1657 }
1658
1659 static int utmi_phy_resume(struct tegra_usb_phy *phy)
1660 {
1661         int status = 0;
1662         unsigned long val;
1663         void __iomem *base = phy->regs;
1664
1665         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1666         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) {
1667                 if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
1668                         utmi_phy_restore_start(phy);
1669                         usb_phy_bringup_host_controller(phy);
1670                         utmi_phy_restore_end(phy);
1671                 } else {
1672                         /* device is plugged in when system is in LP0 */
1673                         /* bring up the controller from LP0*/
1674                         val = readl(base + USB_USBCMD);
1675                         val |= USB_CMD_RESET;
1676                         writel(val, base + USB_USBCMD);
1677
1678                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1679                                 USB_CMD_RESET, 0, 2500) < 0) {
1680                                 pr_err("%s: timeout waiting for reset\n", __func__);
1681                         }
1682
1683                         val = readl(base + USB_USBMODE);
1684                         val &= ~USB_USBMODE_MASK;
1685                         val |= USB_USBMODE_HOST;
1686                         writel(val, base + USB_USBMODE);
1687
1688                         val = readl(base + HOSTPC1_DEVLC);
1689                         val &= ~HOSTPC1_DEVLC_PTS(~0);
1690                         val |= HOSTPC1_DEVLC_STS;
1691                         writel(val, base + HOSTPC1_DEVLC);
1692
1693                         writel(USB_USBCMD_RS, base + USB_USBCMD);
1694
1695                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1696                                 USB_USBCMD_RS, USB_USBCMD_RS, 2500) < 0) {
1697                                 pr_err("%s: timeout waiting for run bit\n", __func__);
1698                         }
1699
1700                         /* Enable Port Power */
1701                         val = readl(base + USB_PORTSC);
1702                         val |= USB_PORTSC_PP;
1703                         writel(val, base + USB_PORTSC);
1704                         udelay(10);
1705
1706                         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1707                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1708                 }
1709         }
1710
1711         return status;
1712 }
1713
1714 bool utmi_phy_charger_detect(struct tegra_usb_phy *phy)
1715 {
1716         unsigned long val;
1717         void __iomem *base = phy->regs;
1718         bool status;
1719
1720         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1721         if (phy->pdata->op_mode != TEGRA_USB_OPMODE_DEVICE) {
1722                 /* Charger detection is not there for ULPI
1723                  * return Charger not available */
1724                 return false;
1725         }
1726
1727         /* Enable charger detection logic */
1728         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1729         val |= UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN;
1730         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1731
1732         /* Source should be on for 100 ms as per USB charging spec */
1733         msleep(TDP_SRC_ON_MS);
1734
1735         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1736         /* If charger is not connected disable the interrupt */
1737         val &= ~VDAT_DET_INT_EN;
1738         val |= VDAT_DET_CHG_DET;
1739         writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
1740
1741         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1742         if (val & VDAT_DET_STS)
1743                 status = true;
1744         else
1745                 status = false;
1746
1747         /* Disable charger detection logic */
1748         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1749         val &= ~(UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN);
1750         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1751
1752         /* Delay of 40 ms before we pull the D+ as per battery charger spec */
1753         msleep(TDPSRC_CON_MS);
1754
1755         return status;
1756 }
1757
1758 static int uhsic_phy_open(struct tegra_usb_phy *phy)
1759 {
1760         unsigned long parent_rate;
1761         int i;
1762
1763         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1764         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
1765         for (i = 0; i < ARRAY_SIZE(uhsic_freq_table); i++) {
1766                 if (uhsic_freq_table[i].freq == parent_rate) {
1767                         phy->freq = &uhsic_freq_table[i];
1768                         break;
1769                 }
1770         }
1771         if (!phy->freq) {
1772                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
1773                 return -EINVAL;
1774         }
1775
1776         utmip_powerup_pmc_wake_detect(phy);
1777
1778         return 0;
1779 }
1780
1781 static int uhsic_phy_irq(struct tegra_usb_phy *phy)
1782 {
1783         usb_phy_fence_read(phy);
1784         return IRQ_HANDLED;
1785 }
1786
1787 static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
1788 {
1789         unsigned long val;
1790         void __iomem *base = phy->regs;
1791         struct tegra_hsic_config *config = &phy->pdata->u_cfg.hsic;
1792
1793         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1794
1795         uhsic_powerup_pmc_wake_detect(phy);
1796
1797         if (phy->phy_clk_on) {
1798                 DBG("%s(%d) inst:[%d] phy clk is already On\n",
1799                                         __func__, __LINE__, phy->inst);
1800                 return 0;
1801         }
1802
1803         val = readl(base + UHSIC_PADS_CFG1);
1804         val &= ~(UHSIC_PD_BG | UHSIC_PD_TX | UHSIC_PD_TRK | UHSIC_PD_RX |
1805                         UHSIC_PD_ZI | UHSIC_RPD_DATA | UHSIC_RPD_STROBE);
1806         val |= UHSIC_RX_SEL;
1807         writel(val, base + UHSIC_PADS_CFG1);
1808         udelay(2);
1809
1810         val = readl(base + USB_SUSP_CTRL);
1811         val |= UHSIC_RESET;
1812         writel(val, base + USB_SUSP_CTRL);
1813         udelay(30);
1814
1815         val = readl(base + USB_SUSP_CTRL);
1816         val |= UHSIC_PHY_ENABLE;
1817         writel(val, base + USB_SUSP_CTRL);
1818
1819         val = readl(base + UHSIC_HSRX_CFG0);
1820         val |= UHSIC_IDLE_WAIT(config->idle_wait_delay);
1821         val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(config->elastic_underrun_limit);
1822         val |= UHSIC_ELASTIC_OVERRUN_LIMIT(config->elastic_overrun_limit);
1823         writel(val, base + UHSIC_HSRX_CFG0);
1824
1825         val = readl(base + UHSIC_HSRX_CFG1);
1826         val |= UHSIC_HS_SYNC_START_DLY(config->sync_start_delay);
1827         writel(val, base + UHSIC_HSRX_CFG1);
1828
1829         /* WAR HSIC TX */
1830         val = readl(base + UHSIC_TX_CFG0);
1831         val &= ~UHSIC_HS_READY_WAIT_FOR_VALID;
1832         writel(val, base + UHSIC_TX_CFG0);
1833
1834         val = readl(base + UHSIC_MISC_CFG0);
1835         val |= UHSIC_SUSPEND_EXIT_ON_EDGE;
1836         /* Disable generic bus reset, to allow AP30 specific bus reset*/
1837         val |= UHSIC_DISABLE_BUSRESET;
1838         writel(val, base + UHSIC_MISC_CFG0);
1839
1840         val = readl(base + UHSIC_MISC_CFG1);
1841         val |= UHSIC_PLLU_STABLE_COUNT(phy->freq->stable_count);
1842         writel(val, base + UHSIC_MISC_CFG1);
1843
1844         val = readl(base + UHSIC_PLL_CFG1);
1845         val |= UHSIC_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
1846         val |= UHSIC_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count);
1847         writel(val, base + UHSIC_PLL_CFG1);
1848
1849         val = readl(base + USB_SUSP_CTRL);
1850         val &= ~(UHSIC_RESET);
1851         writel(val, base + USB_SUSP_CTRL);
1852         udelay(2);
1853
1854         val = readl(base + USB_USBMODE);
1855         val |= USB_USBMODE_HOST;
1856         writel(val, base + USB_USBMODE);
1857
1858         /* Change the USB controller PHY type to HSIC */
1859         val = readl(base + HOSTPC1_DEVLC);
1860         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
1861         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
1862         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
1863         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
1864         writel(val, base + HOSTPC1_DEVLC);
1865
1866         val = readl(base + USB_TXFILLTUNING);
1867         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
1868                 val = USB_FIFO_TXFILL_THRES(0x10);
1869                 writel(val, base + USB_TXFILLTUNING);
1870         }
1871
1872         val = readl(base + USB_PORTSC);
1873         val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN);
1874         writel(val, base + USB_PORTSC);
1875
1876         val = readl(base + UHSIC_PADS_CFG0);
1877         val &= ~(UHSIC_TX_RTUNEN);
1878         /* set Rtune impedance to 50 ohm */
1879         val |= UHSIC_TX_RTUNE(8);
1880         writel(val, base + UHSIC_PADS_CFG0);
1881
1882         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1883                                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500)) {
1884                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
1885                 return -ETIMEDOUT;
1886         }
1887
1888         phy->phy_clk_on = true;
1889         phy->hw_accessible = true;
1890
1891         return 0;
1892 }
1893
1894 static int uhsic_phy_power_off(struct tegra_usb_phy *phy)
1895 {
1896         unsigned long val;
1897         void __iomem *base = phy->regs;
1898
1899         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1900         if (!phy->phy_clk_on) {
1901                 DBG("%s(%d) inst:[%d] phy clk is already off\n",
1902                                         __func__, __LINE__, phy->inst);
1903                 return 0;
1904         }
1905
1906         val = readl(base + UHSIC_PADS_CFG1);
1907         val &= ~UHSIC_RPU_STROBE;
1908         val |= UHSIC_RPD_STROBE;
1909         writel(val, base + UHSIC_PADS_CFG1);
1910
1911         val = readl(base + USB_SUSP_CTRL);
1912         val |= UHSIC_RESET;
1913         writel(val, base + USB_SUSP_CTRL);
1914         udelay(30);
1915
1916         uhsic_powerdown_pmc_wake_detect(phy);
1917
1918         phy->phy_clk_on = false;
1919         phy->hw_accessible = false;
1920
1921         return 0;
1922 }
1923
1924 int uhsic_phy_bus_port_power(struct tegra_usb_phy *phy)
1925 {
1926         unsigned long val;
1927         void __iomem *base = phy->regs;
1928
1929         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1930         val = readl(base + UHSIC_STAT_CFG0);
1931         val &= ~UHSIC_CONNECT_DETECT;
1932         writel(val, base + UHSIC_STAT_CFG0);
1933
1934         val = readl(base + USB_USBMODE);
1935         val |= USB_USBMODE_HOST;
1936         writel(val, base + USB_USBMODE);
1937
1938         /* Change the USB controller PHY type to HSIC */
1939         val = readl(base + HOSTPC1_DEVLC);
1940         val &= ~(HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK));
1941         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
1942         val &= ~(HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK));
1943         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
1944         writel(val, base + HOSTPC1_DEVLC);
1945
1946         val = readl(base + UHSIC_MISC_CFG0);
1947         val |= UHSIC_DETECT_SHORT_CONNECT;
1948         writel(val, base + UHSIC_MISC_CFG0);
1949         udelay(1);
1950
1951         val = readl(base + UHSIC_MISC_CFG0);
1952         val |= UHSIC_FORCE_XCVR_MODE;
1953         writel(val, base + UHSIC_MISC_CFG0);
1954
1955         val = readl(base + UHSIC_PADS_CFG1);
1956         val &= ~UHSIC_RPD_STROBE;
1957         /* safe to enable RPU on STROBE at all times during idle */
1958         val |= UHSIC_RPU_STROBE;
1959         writel(val, base + UHSIC_PADS_CFG1);
1960
1961         val = readl(base + USB_USBCMD);
1962         val &= ~USB_USBCMD_RS;
1963         writel(val, base + USB_USBCMD);
1964
1965         if (usb_phy_reg_status_wait(base + UHSIC_STAT_CFG0,
1966                         UHSIC_CONNECT_DETECT, UHSIC_CONNECT_DETECT, 25000)) {
1967                 pr_err("%s: timeout waiting for UHSIC_CONNECT_DETECT\n",
1968                                                                 __func__);
1969                 return -ETIMEDOUT;
1970         }
1971
1972         return 0;
1973 }
1974
1975 static int uhsic_phy_bus_reset(struct tegra_usb_phy *phy)
1976 {
1977         unsigned long val;
1978         void __iomem *base = phy->regs;
1979
1980         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1981
1982         /* Change the USB controller PHY type to HSIC */
1983         val = readl(base + HOSTPC1_DEVLC);
1984         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
1985         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
1986         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
1987         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
1988         writel(val, base + HOSTPC1_DEVLC);
1989         /* wait here, otherwise HOSTPC1_DEVLC_PSPD will timeout */
1990         mdelay(5);
1991
1992         val = readl(base + USB_PORTSC);
1993         val |= USB_PORTSC_PTC(5);
1994         writel(val, base + USB_PORTSC);
1995         udelay(2);
1996
1997         val = readl(base + USB_PORTSC);
1998         val &= ~(USB_PORTSC_PTC(~0));
1999         writel(val, base + USB_PORTSC);
2000         udelay(2);
2001
2002         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_LS(0),
2003                                                  0, 2000)) {
2004                 pr_err("%s: timeout waiting for USB_PORTSC_LS\n", __func__);
2005                 return -ETIMEDOUT;
2006         }
2007
2008         /* Poll until CCS is enabled */
2009         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
2010                                                  USB_PORTSC_CCS, 2000)) {
2011                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
2012                 return -ETIMEDOUT;
2013         }
2014
2015         if (usb_phy_reg_status_wait(base + HOSTPC1_DEVLC,
2016                         HOSTPC1_DEVLC_PSPD(2),
2017                         HOSTPC1_DEVLC_PSPD(2), 2000) < 0) {
2018                 pr_err("%s: timeout waiting hsic high speed configuration\n",
2019                                                 __func__);
2020                         return -ETIMEDOUT;
2021         }
2022
2023         val = readl(base + USB_USBCMD);
2024         val &= ~USB_USBCMD_RS;
2025         writel(val, base + USB_USBCMD);
2026
2027         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
2028                                                  USB_USBSTS_HCH, 2000)) {
2029                 pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
2030                 return -ETIMEDOUT;
2031         }
2032
2033         val = readl(base + UHSIC_PADS_CFG1);
2034         val &= ~UHSIC_RPU_STROBE;
2035         val |= UHSIC_RPD_STROBE;
2036         writel(val, base + UHSIC_PADS_CFG1);
2037
2038         mdelay(50);
2039
2040         val = readl(base + UHSIC_PADS_CFG1);
2041         val &= ~UHSIC_RPD_STROBE;
2042         val |= UHSIC_RPU_STROBE;
2043         writel(val, base + UHSIC_PADS_CFG1);
2044
2045         val = readl(base + USB_USBCMD);
2046         val |= USB_USBCMD_RS;
2047         writel(val, base + USB_USBCMD);
2048
2049         val = readl(base + UHSIC_PADS_CFG1);
2050         val &= ~UHSIC_RPU_STROBE;
2051         writel(val, base + UHSIC_PADS_CFG1);
2052
2053         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2054                                                  USB_USBCMD_RS, 2000)) {
2055                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2056                 return -ETIMEDOUT;
2057         }
2058
2059         return 0;
2060 }
2061
2062
2063 int uhsic_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
2064 {
2065         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2066
2067         usb_phy_wait_for_sof(phy);
2068
2069         return 0;
2070 }
2071
2072 int uhsic_phy_resume(struct tegra_usb_phy *phy)
2073 {
2074         void __iomem *base = phy->regs;
2075         unsigned long val;
2076
2077         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2078
2079         /* Check if the phy resume from LP0. When the phy resume from LP0
2080          * USB register will be reset.to zero */
2081         if (!readl(base + USB_ASYNCLISTADDR)) {
2082
2083                 val = readl(base + USB_USBCMD);
2084                 val |= USB_CMD_RESET;
2085                 writel(val, base + USB_USBCMD);
2086
2087                 if (usb_phy_reg_status_wait(base + USB_USBCMD,
2088                         USB_CMD_RESET, 0, 2500) < 0) {
2089                         pr_err("%s: timeout waiting for reset\n", __func__);
2090                 }
2091
2092                 val = readl(base + USB_USBMODE);
2093                 val &= ~USB_USBMODE_MASK;
2094                 val |= USB_USBMODE_HOST;
2095                 writel(val, base + USB_USBMODE);
2096
2097                 /* Enable Port Power */
2098                 val = readl(base + USB_PORTSC);
2099                 val |= USB_PORTSC_PP;
2100                 writel(val, base + USB_PORTSC);
2101                 udelay(10);
2102
2103                 DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
2104                 readl(base + USB_USBSTS), readl(base + USB_PORTSC));
2105
2106                 uhsic_phy_bus_port_power(phy);
2107         }
2108
2109         return 0;
2110 }
2111
2112 static int uhsic_phy_post_resume(struct tegra_usb_phy *phy)
2113 {
2114         unsigned long val;
2115         void __iomem *base = phy->regs;
2116
2117         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2118         val = readl(base + USB_TXFILLTUNING);
2119         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
2120                 val = USB_FIFO_TXFILL_THRES(0x10);
2121                 writel(val, base + USB_TXFILLTUNING);
2122         }
2123
2124         return 0;
2125 }
2126
2127 static void ulpi_set_trimmer(struct tegra_usb_phy *phy)
2128 {
2129         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2130         void __iomem *base = phy->regs;
2131         unsigned long val;
2132
2133         val = ULPI_DATA_TRIMMER_SEL(config->data_trimmer);
2134         val |= ULPI_STPDIRNXT_TRIMMER_SEL(config->stpdirnxt_trimmer);
2135         val |= ULPI_DIR_TRIMMER_SEL(config->dir_trimmer);
2136         writel(val, base + ULPI_TIMING_CTRL_1);
2137         udelay(10);
2138
2139         val |= ULPI_DATA_TRIMMER_LOAD;
2140         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
2141         val |= ULPI_DIR_TRIMMER_LOAD;
2142         writel(val, base + ULPI_TIMING_CTRL_1);
2143 }
2144
2145 static void reset_utmip_uhsic(void __iomem *base)
2146 {
2147         unsigned long val;
2148
2149         val = readl(base + USB_SUSP_CTRL);
2150         val |= UHSIC_RESET;
2151         writel(val, base + USB_SUSP_CTRL);
2152
2153         val = readl(base + USB_SUSP_CTRL);
2154         val |= UTMIP_RESET;
2155         writel(val, base + USB_SUSP_CTRL);
2156 }
2157
2158 static void ulpi_set_host(void __iomem *base)
2159 {
2160         unsigned long val;
2161
2162         val = readl(base + USB_USBMODE);
2163         val |= USB_USBMODE_HOST;
2164         writel(val, base + USB_USBMODE);
2165
2166         val = readl(base + HOSTPC1_DEVLC);
2167         val |= HOSTPC1_DEVLC_PTS(2);
2168         writel(val, base + HOSTPC1_DEVLC);
2169 }
2170
2171
2172 static int ulpi_null_phy_power_off(struct tegra_usb_phy *phy)
2173 {
2174         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2175
2176         if (!phy->phy_clk_on) {
2177                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
2178                                                         __LINE__, phy->inst);
2179                 return 0;
2180         }
2181
2182         phy->phy_clk_on = false;
2183         phy->hw_accessible = false;
2184
2185         return 0;
2186 }
2187
2188 static int ulpi_null_phy_init(struct tegra_usb_phy *phy)
2189 {
2190         unsigned long val;
2191         void __iomem *base = phy->regs;
2192
2193         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2194         val = readl(base + ULPIS2S_CTRL);
2195         val |=  ULPIS2S_SLV0_CLAMP_XMIT;
2196         writel(val, base + ULPIS2S_CTRL);
2197
2198         val = readl(base + USB_SUSP_CTRL);
2199         val |= ULPIS2S_SLV0_RESET;
2200         writel(val, base + USB_SUSP_CTRL);
2201         udelay(10);
2202
2203         return 0;
2204 }
2205
2206 static int ulpi_null_phy_irq(struct tegra_usb_phy *phy)
2207 {
2208         usb_phy_fence_read(phy);
2209         return IRQ_HANDLED;
2210 }
2211
2212 static int ulpi_null_phy_cmd_reset(struct tegra_usb_phy *phy)
2213 {
2214         unsigned long val;
2215         void __iomem *base = phy->regs;
2216
2217         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2218         ulpi_set_host(base);
2219
2220         /* remove slave0 reset */
2221         val = readl(base + USB_SUSP_CTRL);
2222         val &= ~ULPIS2S_SLV0_RESET;
2223         writel(val, base + USB_SUSP_CTRL);
2224
2225         val = readl(base + ULPIS2S_CTRL);
2226         val &=  ~ULPIS2S_SLV0_CLAMP_XMIT;
2227         writel(val, base + ULPIS2S_CTRL);
2228         udelay(10);
2229
2230         return 0;
2231 }
2232
2233 static int ulpi_null_phy_lp0_resume(struct tegra_usb_phy *phy)
2234 {
2235         unsigned long val;
2236         void __iomem *base = phy->regs;
2237
2238         ulpi_null_phy_init(phy);
2239
2240         val = readl(base + USB_USBCMD);
2241         val |= USB_CMD_RESET;
2242         writel(val, base + USB_USBCMD);
2243
2244         if (usb_phy_reg_status_wait(base + USB_USBCMD,
2245                 USB_CMD_RESET, 0, 2500) < 0) {
2246                 pr_err("%s: timeout waiting for reset\n", __func__);
2247         }
2248
2249         val = readl(base + USB_USBMODE);
2250         val &= ~USB_USBMODE_MASK;
2251         val |= USB_USBMODE_HOST;
2252         writel(val, base + USB_USBMODE);
2253
2254         ulpi_null_phy_cmd_reset(phy);
2255
2256         val = readl(base + USB_USBCMD);
2257         val |= USB_USBCMD_RS;
2258         writel(val, base + USB_USBCMD);
2259         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2260                                                  USB_USBCMD_RS, 2000)) {
2261                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2262                 return -ETIMEDOUT;
2263         }
2264
2265         /* Enable Port Power */
2266         val = readl(base + USB_PORTSC);
2267         val |= USB_PORTSC_PP;
2268         writel(val, base + USB_PORTSC);
2269         udelay(10);
2270
2271         /* disable ULPI pinmux bypass */
2272         val = readl(base + ULPI_TIMING_CTRL_0);
2273         val &= ~ULPI_OUTPUT_PINMUX_BYP;
2274         writel(val, base + ULPI_TIMING_CTRL_0);
2275
2276         return 0;
2277 }
2278
2279 static int ulpi_null_phy_power_on(struct tegra_usb_phy *phy)
2280 {
2281         unsigned long val;
2282         void __iomem *base = phy->regs;
2283         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2284         static bool cold_boot = true;
2285
2286         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2287         if (phy->phy_clk_on) {
2288                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
2289                                                         __LINE__, phy->inst);
2290                 return 0;
2291         }
2292         reset_utmip_uhsic(base);
2293
2294         /* remove ULPI PADS CLKEN reset */
2295         val = readl(base + USB_SUSP_CTRL);
2296         val &= ~ULPI_PADS_CLKEN_RESET;
2297         writel(val, base + USB_SUSP_CTRL);
2298         udelay(10);
2299
2300         val = readl(base + ULPI_TIMING_CTRL_0);
2301         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
2302         writel(val, base + ULPI_TIMING_CTRL_0);
2303
2304         val = readl(base + USB_SUSP_CTRL);
2305         val |= ULPI_PHY_ENABLE;
2306         writel(val, base + USB_SUSP_CTRL);
2307         udelay(10);
2308
2309         /* set timming parameters */
2310         val = readl(base + ULPI_TIMING_CTRL_0);
2311         val |= ULPI_SHADOW_CLK_LOOPBACK_EN;
2312         val &= ~ULPI_SHADOW_CLK_SEL;
2313         val &= ~ULPI_LBK_PAD_EN;
2314         val |= ULPI_SHADOW_CLK_DELAY(config->shadow_clk_delay);
2315         val |= ULPI_CLOCK_OUT_DELAY(config->clock_out_delay);
2316         val |= ULPI_LBK_PAD_E_INPUT_OR;
2317         writel(val, base + ULPI_TIMING_CTRL_0);
2318
2319         writel(0, base + ULPI_TIMING_CTRL_1);
2320         udelay(10);
2321
2322         /* start internal 60MHz clock */
2323         val = readl(base + ULPIS2S_CTRL);
2324         val |= ULPIS2S_ENA;
2325         val |= ULPIS2S_SUPPORT_DISCONNECT;
2326         val |= ULPIS2S_SPARE((phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) ? 3 : 1);
2327         val |= ULPIS2S_PLLU_MASTER_BLASTER60;
2328         writel(val, base + ULPIS2S_CTRL);
2329
2330         /* select ULPI_CORE_CLK_SEL to SHADOW_CLK */
2331         val = readl(base + ULPI_TIMING_CTRL_0);
2332         val |= ULPI_CORE_CLK_SEL;
2333         writel(val, base + ULPI_TIMING_CTRL_0);
2334         udelay(10);
2335
2336         /* enable ULPI null phy clock - can't set the trimmers before this */
2337         val = readl(base + ULPI_TIMING_CTRL_0);
2338         val |= ULPI_CLK_OUT_ENA;
2339         writel(val, base + ULPI_TIMING_CTRL_0);
2340         udelay(10);
2341
2342         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
2343                                                  USB_PHY_CLK_VALID, 2500)) {
2344                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2345                 return -ETIMEDOUT;
2346         }
2347
2348         /* set ULPI trimmers */
2349         ulpi_set_trimmer(phy);
2350
2351         ulpi_set_host(base);
2352
2353         /* remove slave0 reset */
2354         val = readl(base + USB_SUSP_CTRL);
2355         val &= ~ULPIS2S_SLV0_RESET;
2356         writel(val, base + USB_SUSP_CTRL);
2357
2358         /* remove slave1 and line reset */
2359         val = readl(base + USB_SUSP_CTRL);
2360         val &= ~ULPIS2S_SLV1_RESET;
2361         val &= ~ULPIS2S_LINE_RESET;
2362
2363         /* remove ULPI PADS reset */
2364         val &= ~ULPI_PADS_RESET;
2365         writel(val, base + USB_SUSP_CTRL);
2366
2367         if (cold_boot) {
2368                 val = readl(base + ULPI_TIMING_CTRL_0);
2369                 val |= ULPI_CLK_PADOUT_ENA;
2370                 writel(val, base + ULPI_TIMING_CTRL_0);
2371                 cold_boot = false;
2372         } else {
2373                 if (!readl(base + USB_ASYNCLISTADDR))
2374                         ulpi_null_phy_lp0_resume(phy);
2375         }
2376         udelay(10);
2377
2378         phy->phy_clk_on = true;
2379         phy->hw_accessible = true;
2380
2381         return 0;
2382 }
2383
2384
2385 int ulpi_null_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
2386 {
2387         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2388
2389         usb_phy_wait_for_sof(phy);
2390         return 0;
2391 }
2392
2393 static int ulpi_null_phy_resume(struct tegra_usb_phy *phy)
2394 {
2395         unsigned long val;
2396         void __iomem *base = phy->regs;
2397
2398         if (!readl(base + USB_ASYNCLISTADDR)) {
2399                 /* enable ULPI CLK output pad */
2400                 val = readl(base + ULPI_TIMING_CTRL_0);
2401                 val |= ULPI_CLK_PADOUT_ENA;
2402                 writel(val, base + ULPI_TIMING_CTRL_0);
2403
2404                 /* enable ULPI pinmux bypass */
2405                 val = readl(base + ULPI_TIMING_CTRL_0);
2406                 val |= ULPI_OUTPUT_PINMUX_BYP;
2407                 writel(val, base + ULPI_TIMING_CTRL_0);
2408                 udelay(5);
2409 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2410                 /* remove DIR tristate */
2411                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR, TEGRA_TRI_NORMAL);
2412 #endif
2413         }
2414         return 0;
2415 }
2416
2417
2418
2419 static struct tegra_usb_phy_ops utmi_phy_ops = {
2420         .open           = utmi_phy_open,
2421         .close          = utmi_phy_close,
2422         .irq            = utmi_phy_irq,
2423         .power_on       = utmi_phy_power_on,
2424         .power_off      = utmi_phy_power_off,
2425         .pre_resume = utmi_phy_pre_resume,
2426         .resume = utmi_phy_resume,
2427         .post_resume    = utmi_phy_post_resume,
2428         .charger_detect = utmi_phy_charger_detect,
2429 };
2430
2431 static struct tegra_usb_phy_ops uhsic_phy_ops = {
2432         .open           = uhsic_phy_open,
2433         .irq            = uhsic_phy_irq,
2434         .power_on       = uhsic_phy_power_on,
2435         .power_off      = uhsic_phy_power_off,
2436         .pre_resume = uhsic_phy_pre_resume,
2437         .resume = uhsic_phy_resume,
2438         .post_resume = uhsic_phy_post_resume,
2439         .port_power = uhsic_phy_bus_port_power,
2440         .bus_reset      = uhsic_phy_bus_reset,
2441 };
2442
2443 static struct tegra_usb_phy_ops ulpi_null_phy_ops = {
2444         .init           = ulpi_null_phy_init,
2445         .irq            = ulpi_null_phy_irq,
2446         .power_on       = ulpi_null_phy_power_on,
2447         .power_off      = ulpi_null_phy_power_off,
2448         .pre_resume = ulpi_null_phy_pre_resume,
2449         .resume = ulpi_null_phy_resume,
2450         .reset          = ulpi_null_phy_cmd_reset,
2451 };
2452
2453 static struct tegra_usb_phy_ops ulpi_link_phy_ops;
2454 static struct tegra_usb_phy_ops icusb_phy_ops;
2455
2456 static struct tegra_usb_phy_ops *phy_ops[] = {
2457         [TEGRA_USB_PHY_INTF_UTMI] = &utmi_phy_ops,
2458         [TEGRA_USB_PHY_INTF_ULPI_LINK] = &ulpi_link_phy_ops,
2459         [TEGRA_USB_PHY_INTF_ULPI_NULL] = &ulpi_null_phy_ops,
2460         [TEGRA_USB_PHY_INTF_HSIC] = &uhsic_phy_ops,
2461         [TEGRA_USB_PHY_INTF_ICUSB] = &icusb_phy_ops,
2462 };
2463
2464 int tegra3_usb_phy_init_ops(struct tegra_usb_phy *phy)
2465 {
2466         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2467
2468         phy->ops = phy_ops[phy->pdata->phy_intf];
2469
2470         /* FIXME: uncommenting below line to make USB host mode fail*/
2471         /* usb_phy_power_down_pmc(); */
2472
2473         return 0;
2474 }