Merge branch 'android-tegra-nv-3.4' into android-t114-3.4
[linux-2.6.git] / arch / arm / mach-tegra / tegra3_usb_phy.c
1 /*
2  * arch/arm/mach-tegra/tegra3_usb_phy.c
3  *
4  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
5  *
6  *
7  * This software is licensed under the terms of the GNU General Public
8  * License version 2, as published by the Free Software Foundation, and
9  * may be copied, distributed, and modified under those terms.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17 #include <linux/resource.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/slab.h>
21 #include <linux/err.h>
22 #include <linux/platform_device.h>
23 #include <linux/io.h>
24 #include <linux/gpio.h>
25 #include <linux/interrupt.h>
26 #include <linux/clk.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <mach/iomap.h>
30 #include <mach/pinmux.h>
31 #include <mach/pinmux-tegra30.h>
32 #include "tegra_usb_phy.h"
33 #include "fuse.h"
34
35 #define USB_USBCMD              0x130
36 #define   USB_USBCMD_RS         (1 << 0)
37 #define   USB_CMD_RESET (1<<1)
38
39 #define USB_USBSTS              0x134
40 #define   USB_USBSTS_PCI        (1 << 2)
41 #define   USB_USBSTS_SRI        (1 << 7)
42 #define   USB_USBSTS_HCH        (1 << 12)
43
44 #define USB_USBINTR             0x138
45
46 #define USB_TXFILLTUNING        0x154
47 #define USB_FIFO_TXFILL_THRES(x)   (((x) & 0x1f) << 16)
48 #define USB_FIFO_TXFILL_MASK    0x1f0000
49
50 #define USB_ASYNCLISTADDR       0x148
51
52 #define ICUSB_CTRL              0x15c
53
54 #define USB_PORTSC              0x174
55 #define   USB_PORTSC_WKOC       (1 << 22)
56 #define   USB_PORTSC_WKDS       (1 << 21)
57 #define   USB_PORTSC_WKCN       (1 << 20)
58 #define   USB_PORTSC_PTC(x)     (((x) & 0xf) << 16)
59 #define   USB_PORTSC_PP (1 << 12)
60 #define   USB_PORTSC_LS(x) (((x) & 0x3) << 10)
61 #define   USB_PORTSC_SUSP       (1 << 7)
62 #define   USB_PORTSC_RESUME     (1 << 6)
63 #define   USB_PORTSC_OCC        (1 << 5)
64 #define   USB_PORTSC_PEC        (1 << 3)
65 #define   USB_PORTSC_PE         (1 << 2)
66 #define   USB_PORTSC_CSC        (1 << 1)
67 #define   USB_PORTSC_CCS        (1 << 0)
68 #define   USB_PORTSC_RWC_BITS (USB_PORTSC_CSC | USB_PORTSC_PEC | USB_PORTSC_OCC)
69
70 #define HOSTPC1_DEVLC           0x1b4
71 #define   HOSTPC1_DEVLC_PHCD            (1 << 22)
72 #define   HOSTPC1_DEVLC_PTS(x)          (((x) & 0x7) << 29)
73 #define   HOSTPC1_DEVLC_PTS_MASK        7
74 #define   HOSTPC1_DEVLC_PTS_HSIC        4
75 #define   HOSTPC1_DEVLC_STS             (1 << 28)
76 #define   HOSTPC1_DEVLC_PSPD(x)         (((x) & 0x3) << 25)
77 #define   HOSTPC1_DEVLC_PSPD_MASK       3
78 #define   HOSTPC1_DEVLC_PSPD_HIGH_SPEED 2
79
80 #define USB_USBMODE             0x1f8
81 #define   USB_USBMODE_MASK              (3 << 0)
82 #define   USB_USBMODE_HOST              (3 << 0)
83 #define   USB_USBMODE_DEVICE            (2 << 0)
84
85 #define USB_SUSP_CTRL           0x400
86 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
87 #define   USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
88 #define   USB_SUSP_CLR                  (1 << 5)
89 #define   USB_PHY_CLK_VALID             (1 << 7)
90 #define   USB_PHY_CLK_VALID_INT_ENB     (1 << 9)
91 #define   USB_PHY_CLK_VALID_INT_STS     (1 << 8)
92 #define   UTMIP_RESET                   (1 << 11)
93 #define   UTMIP_PHY_ENABLE              (1 << 12)
94 #define   ULPI_PHY_ENABLE               (1 << 13)
95 #define   UHSIC_RESET                   (1 << 14)
96 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
97 #define   UHSIC_PHY_ENABLE              (1 << 19)
98 #define   ULPIS2S_SLV0_RESET            (1 << 20)
99 #define   ULPIS2S_SLV1_RESET            (1 << 21)
100 #define   ULPIS2S_LINE_RESET            (1 << 22)
101 #define   ULPI_PADS_RESET               (1 << 23)
102 #define   ULPI_PADS_CLKEN_RESET         (1 << 24)
103
104 #define USB_PHY_VBUS_WAKEUP_ID  0x408
105 #define   VDAT_DET_INT_EN       (1 << 16)
106 #define   VDAT_DET_CHG_DET      (1 << 17)
107 #define   VDAT_DET_STS          (1 << 18)
108 #define   USB_ID_STATUS         (1 << 2)
109
110 #define ULPIS2S_CTRL            0x418
111 #define   ULPIS2S_ENA                   (1 << 0)
112 #define   ULPIS2S_SUPPORT_DISCONNECT    (1 << 2)
113 #define   ULPIS2S_PLLU_MASTER_BLASTER60 (1 << 3)
114 #define   ULPIS2S_SPARE(x)              (((x) & 0xF) << 8)
115 #define   ULPIS2S_FORCE_ULPI_CLK_OUT    (1 << 12)
116 #define   ULPIS2S_DISCON_DONT_CHECK_SE0 (1 << 13)
117 #define   ULPIS2S_SUPPORT_HS_KEEP_ALIVE (1 << 14)
118 #define   ULPIS2S_DISABLE_STP_PU        (1 << 15)
119 #define   ULPIS2S_SLV0_CLAMP_XMIT       (1 << 16)
120
121 #define ULPI_TIMING_CTRL_0      0x424
122 #define   ULPI_CLOCK_OUT_DELAY(x)       ((x) & 0x1F)
123 #define   ULPI_OUTPUT_PINMUX_BYP        (1 << 10)
124 #define   ULPI_CLKOUT_PINMUX_BYP        (1 << 11)
125 #define   ULPI_SHADOW_CLK_LOOPBACK_EN   (1 << 12)
126 #define   ULPI_SHADOW_CLK_SEL           (1 << 13)
127 #define   ULPI_CORE_CLK_SEL             (1 << 14)
128 #define   ULPI_SHADOW_CLK_DELAY(x)      (((x) & 0x1F) << 16)
129 #define   ULPI_LBK_PAD_EN               (1 << 26)
130 #define   ULPI_LBK_PAD_E_INPUT_OR       (1 << 27)
131 #define   ULPI_CLK_OUT_ENA              (1 << 28)
132 #define   ULPI_CLK_PADOUT_ENA           (1 << 29)
133
134 #define ULPI_TIMING_CTRL_1      0x428
135 #define   ULPI_DATA_TRIMMER_LOAD        (1 << 0)
136 #define   ULPI_DATA_TRIMMER_SEL(x)      (((x) & 0x7) << 1)
137 #define   ULPI_STPDIRNXT_TRIMMER_LOAD   (1 << 16)
138 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
139 #define   ULPI_DIR_TRIMMER_LOAD         (1 << 24)
140 #define   ULPI_DIR_TRIMMER_SEL(x)       (((x) & 0x7) << 25)
141
142 #define UTMIP_XCVR_CFG0         0x808
143 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
144 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
145 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
146 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
147 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
148 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
149 #define   UTMIP_XCVR_LSBIAS_SEL                 (1 << 21)
150 #define   UTMIP_XCVR_SETUP_MSB(x)               (((x) & 0x7) << 22)
151 #define   UTMIP_XCVR_HSSLEW_MSB(x)              (((x) & 0x7f) << 25)
152 #define   UTMIP_XCVR_MAX_OFFSET         2
153 #define   UTMIP_XCVR_SETUP_MAX_VALUE    0x7f
154 #define   UTMIP_XCVR_SETUP_MIN_VALUE    0
155 #define   XCVR_SETUP_MSB_CALIB(x) ((x) >> 4)
156
157 #define UTMIP_BIAS_CFG0         0x80c
158 #define   UTMIP_OTGPD                   (1 << 11)
159 #define   UTMIP_BIASPD                  (1 << 10)
160 #define   UTMIP_HSSQUELCH_LEVEL(x)      (((x) & 0x3) << 0)
161 #define   UTMIP_HSDISCON_LEVEL(x)       (((x) & 0x3) << 2)
162 #define   UTMIP_HSDISCON_LEVEL_MSB      (1 << 24)
163
164 #define UTMIP_HSRX_CFG0         0x810
165 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
166 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
167
168 #define UTMIP_HSRX_CFG1         0x814
169 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
170
171 #define UTMIP_TX_CFG0           0x820
172 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
173 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
174
175 #define UTMIP_DEBOUNCE_CFG0 0x82c
176 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
177
178 #define UTMIP_BAT_CHRG_CFG0 0x830
179 #define   UTMIP_PD_CHRG                 (1 << 0)
180 #define   UTMIP_ON_SINK_EN              (1 << 2)
181 #define   UTMIP_OP_SRC_EN               (1 << 3)
182
183 #define UTMIP_XCVR_CFG1         0x838
184 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
185 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
186 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
187 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
188
189 #define UTMIP_BIAS_CFG1         0x83c
190 #define   UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
191 #define   UTMIP_BIAS_PDTRK_POWERDOWN    (1 << 0)
192 #define   UTMIP_BIAS_PDTRK_POWERUP      (1 << 1)
193
194 #define UTMIP_MISC_CFG0         0x824
195 #define   UTMIP_DPDM_OBSERVE            (1 << 26)
196 #define   UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
197 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J   UTMIP_DPDM_OBSERVE_SEL(0xf)
198 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K   UTMIP_DPDM_OBSERVE_SEL(0xe)
199 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
200 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
201 #define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
202 #define   FORCE_PULLDN_DM       (1 << 8)
203 #define   FORCE_PULLDN_DP       (1 << 9)
204 #define   COMB_TERMS            (1 << 0)
205 #define   ALWAYS_FREE_RUNNING_TERMS (1 << 1)
206
207 #define UTMIP_SPARE_CFG0        0x834
208 #define   FUSE_SETUP_SEL                (1 << 3)
209 #define   FUSE_ATERM_SEL                (1 << 4)
210
211 #define UTMIP_PMC_WAKEUP0               0x84c
212 #define   EVENT_INT_ENB                 (1 << 0)
213
214 #define UHSIC_PMC_WAKEUP0               0xc34
215
216 #define UTMIP_BIAS_STS0                 0x840
217 #define   UTMIP_RCTRL_VAL(x)            (((x) & 0xffff) << 0)
218 #define   UTMIP_TCTRL_VAL(x)            (((x) & (0xffff << 16)) >> 16)
219
220 #define UHSIC_PLL_CFG1                          0xc04
221 #define   UHSIC_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
222 #define   UHSIC_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 14)
223
224 #define UHSIC_HSRX_CFG0                         0xc08
225 #define   UHSIC_ELASTIC_UNDERRUN_LIMIT(x)       (((x) & 0x1f) << 2)
226 #define   UHSIC_ELASTIC_OVERRUN_LIMIT(x)        (((x) & 0x1f) << 8)
227 #define   UHSIC_IDLE_WAIT(x)                    (((x) & 0x1f) << 13)
228
229 #define UHSIC_HSRX_CFG1                         0xc0c
230 #define   UHSIC_HS_SYNC_START_DLY(x)            (((x) & 0x1f) << 1)
231
232 #define UHSIC_TX_CFG0                           0xc10
233 #define UHSIC_HS_READY_WAIT_FOR_VALID   (1 << 9)
234 #define UHSIC_MISC_CFG0                         0xc14
235 #define   UHSIC_SUSPEND_EXIT_ON_EDGE            (1 << 7)
236 #define   UHSIC_DETECT_SHORT_CONNECT            (1 << 8)
237 #define   UHSIC_FORCE_XCVR_MODE                 (1 << 15)
238 #define   UHSIC_DISABLE_BUSRESET                (1 << 20)
239 #define UHSIC_MISC_CFG1                         0xc18
240 #define   UHSIC_PLLU_STABLE_COUNT(x)            (((x) & 0xfff) << 2)
241
242 #define UHSIC_PADS_CFG0                         0xc1c
243 #define   UHSIC_TX_RTUNEN                       0xf000
244 #define   UHSIC_TX_RTUNE(x)                     (((x) & 0xf) << 12)
245
246 #define UHSIC_PADS_CFG1                         0xc20
247 #define   UHSIC_PD_BG                           (1 << 2)
248 #define   UHSIC_PD_TX                           (1 << 3)
249 #define   UHSIC_PD_TRK                          (1 << 4)
250 #define   UHSIC_PD_RX                           (1 << 5)
251 #define   UHSIC_PD_ZI                           (1 << 6)
252 #define   UHSIC_RX_SEL                          (1 << 7)
253 #define   UHSIC_RPD_DATA                        (1 << 9)
254 #define   UHSIC_RPD_STROBE                      (1 << 10)
255 #define   UHSIC_RPU_DATA                        (1 << 11)
256 #define   UHSIC_RPU_STROBE                      (1 << 12)
257
258 #define UHSIC_CMD_CFG0                  0xc24
259 #define UHSIC_PRETEND_CONNECT_DETECT    (1 << 5)
260
261 #define UHSIC_STAT_CFG0         0xc28
262 #define UHSIC_CONNECT_DETECT            (1 << 0)
263
264 #define PMC_USB_DEBOUNCE                        0xec
265 #define UTMIP_LINE_DEB_CNT(x)           (((x) & 0xf) << 16)
266 #define UHSIC_LINE_DEB_CNT(x)           (((x) & 0xf) << 20)
267
268 #define PMC_USB_AO                              0xf0
269
270 #define PMC_POWER_DOWN_MASK                     0xffff
271 #define HSIC_RESERVED_P0                        (3 << 14)
272 #define STROBE_VAL_PD_P0                        (1 << 12)
273 #define DATA_VAL_PD_P0                          (1 << 13)
274
275 #define USB_ID_PD(inst)                 (1 << ((4*(inst))+3))
276 #define VBUS_WAKEUP_PD(inst)                    (1 << ((4*(inst))+2))
277 #define   USBON_VAL_PD(inst)                    (1 << ((4*(inst))+1))
278 #define   USBON_VAL_PD_P2                       (1 << 9)
279 #define   USBON_VAL_PD_P1                       (1 << 5)
280 #define   USBON_VAL_PD_P0                       (1 << 1)
281 #define   USBOP_VAL_PD(inst)                    (1 << (4*(inst)))
282 #define   USBOP_VAL_PD_P2                       (1 << 8)
283 #define   USBOP_VAL_PD_P1                       (1 << 4)
284 #define   USBOP_VAL_PD_P0                       (1 << 0)
285 #define   PMC_USB_AO_PD_P2                      (0xf << 8)
286 #define   PMC_USB_AO_ID_PD_P0                   (1 << 3)
287 #define   PMC_USB_AO_VBUS_WAKEUP_PD_P0  (1 << 2)
288
289 #define PMC_TRIGGERS                    0x1ec
290
291 #define   UHSIC_CLR_WALK_PTR_P0         (1 << 3)
292 #define   UTMIP_CLR_WALK_PTR(inst)      (1 << (inst))
293 #define   UTMIP_CLR_WALK_PTR_P2         (1 << 2)
294 #define   UTMIP_CLR_WALK_PTR_P1         (1 << 1)
295 #define   UTMIP_CLR_WALK_PTR_P0         (1 << 0)
296 #define   UTMIP_CAP_CFG(inst)   (1 << ((inst)+4))
297 #define   UTMIP_CAP_CFG_P2              (1 << 6)
298 #define   UTMIP_CAP_CFG_P1              (1 << 5)
299 #define   UTMIP_CAP_CFG_P0              (1 << 4)
300 #define   UTMIP_CLR_WAKE_ALARM(inst)    (1 << ((inst)+12))
301 #define   UHSIC_CLR_WAKE_ALARM_P0       (1 << 15)
302 #define   UTMIP_CLR_WAKE_ALARM_P2       (1 << 14)
303
304 #define PMC_PAD_CFG             (0x1f4)
305
306 #define PMC_UTMIP_TERM_PAD_CFG  0x1f8
307 #define   PMC_TCTRL_VAL(x)      (((x) & 0x1f) << 5)
308 #define   PMC_RCTRL_VAL(x)      (((x) & 0x1f) << 0)
309
310 #define PMC_SLEEP_CFG                   0x1fc
311
312 #define   UHSIC_MASTER_ENABLE                   (1 << 24)
313 #define   UHSIC_WAKE_VAL(x)             (((x) & 0xf) << 28)
314 #define   WAKE_VAL_SD10                 0x2
315 #define   UTMIP_TCTRL_USE_PMC(inst) (1 << ((8*(inst))+3))
316 #define   UTMIP_TCTRL_USE_PMC_P2                (1 << 19)
317 #define   UTMIP_TCTRL_USE_PMC_P1                (1 << 11)
318 #define   UTMIP_TCTRL_USE_PMC_P0                (1 << 3)
319 #define   UTMIP_RCTRL_USE_PMC(inst) (1 << ((8*(inst))+2))
320 #define   UTMIP_RCTRL_USE_PMC_P2                (1 << 18)
321 #define   UTMIP_RCTRL_USE_PMC_P1                (1 << 10)
322 #define   UTMIP_RCTRL_USE_PMC_P0                (1 << 2)
323 #define   UTMIP_FSLS_USE_PMC(inst)      (1 << ((8*(inst))+1))
324 #define   UTMIP_FSLS_USE_PMC_P2         (1 << 17)
325 #define   UTMIP_FSLS_USE_PMC_P1         (1 << 9)
326 #define   UTMIP_FSLS_USE_PMC_P0         (1 << 1)
327 #define   UTMIP_MASTER_ENABLE(inst) (1 << (8*(inst)))
328 #define   UTMIP_MASTER_ENABLE_P2                (1 << 16)
329 #define   UTMIP_MASTER_ENABLE_P1                (1 << 8)
330 #define   UTMIP_MASTER_ENABLE_P0                (1 << 0)
331 #define UHSIC_MASTER_ENABLE_P0          (1 << 24)
332 #define UHSIC_WAKE_VAL_P0(x)            (((x) & 0xf) << 28)
333
334 #define PMC_SLEEPWALK_CFG               0x200
335
336 #define   UHSIC_WAKE_WALK_EN_P0 (1 << 30)
337 #define   UHSIC_LINEVAL_WALK_EN (1 << 31)
338 #define   UTMIP_LINEVAL_WALK_EN(inst) (1 << ((8*(inst))+7))
339 #define   UTMIP_LINEVAL_WALK_EN_P2      (1 << 23)
340 #define   UTMIP_LINEVAL_WALK_EN_P1      (1 << 15)
341 #define   UTMIP_LINEVAL_WALK_EN_P0      (1 << 7)
342 #define   UTMIP_WAKE_VAL(inst, x) (((x) & 0xf) << ((8*(inst))+4))
343 #define   UTMIP_WAKE_VAL_P2(x)          (((x) & 0xf) << 20)
344 #define   UTMIP_WAKE_VAL_P1(x)          (((x) & 0xf) << 12)
345 #define   UTMIP_WAKE_VAL_P0(x)          (((x) & 0xf) << 4)
346 #define   WAKE_VAL_NONE         0xc
347 #define   WAKE_VAL_ANY                  0xF
348 #define   WAKE_VAL_FSJ                  0x2
349 #define   WAKE_VAL_FSK                  0x1
350 #define   WAKE_VAL_SE0                  0x0
351
352 #define PMC_SLEEPWALK_REG(inst)         (0x204 + (4*(inst)))
353 #define   UTMIP_USBOP_RPD_A     (1 << 0)
354 #define   UTMIP_USBON_RPD_A     (1 << 1)
355 #define   UTMIP_AP_A                    (1 << 4)
356 #define   UTMIP_AN_A                    (1 << 5)
357 #define   UTMIP_HIGHZ_A         (1 << 6)
358 #define   UTMIP_USBOP_RPD_B     (1 << 8)
359 #define   UTMIP_USBON_RPD_B     (1 << 9)
360 #define   UTMIP_AP_B                    (1 << 12)
361 #define   UTMIP_AN_B                    (1 << 13)
362 #define   UTMIP_HIGHZ_B         (1 << 14)
363 #define   UTMIP_USBOP_RPD_C     (1 << 16)
364 #define   UTMIP_USBON_RPD_C     (1 << 17)
365 #define   UTMIP_AP_C            (1 << 20)
366 #define   UTMIP_AN_C            (1 << 21)
367 #define   UTMIP_HIGHZ_C         (1 << 22)
368 #define   UTMIP_USBOP_RPD_D     (1 << 24)
369 #define   UTMIP_USBON_RPD_D     (1 << 25)
370 #define   UTMIP_AP_D            (1 << 28)
371 #define   UTMIP_AN_D            (1 << 29)
372 #define   UTMIP_HIGHZ_D         (1 << 30)
373
374 #define PMC_SLEEPWALK_UHSIC             0x210
375
376 #define UHSIC_STROBE_RPD_A              (1 << 0)
377 #define UHSIC_DATA_RPD_A                (1 << 1)
378 #define UHSIC_STROBE_RPU_A              (1 << 2)
379 #define UHSIC_DATA_RPU_A                (1 << 3)
380 #define UHSIC_STROBE_RPD_B              (1 << 8)
381 #define UHSIC_DATA_RPD_B                (1 << 9)
382 #define UHSIC_STROBE_RPU_B              (1 << 10)
383 #define UHSIC_DATA_RPU_B                (1 << 11)
384 #define UHSIC_STROBE_RPD_C              (1 << 16)
385 #define UHSIC_DATA_RPD_C                (1 << 17)
386 #define UHSIC_STROBE_RPU_C              (1 << 18)
387 #define UHSIC_DATA_RPU_C                (1 << 19)
388 #define UHSIC_STROBE_RPD_D              (1 << 24)
389 #define UHSIC_DATA_RPD_D                (1 << 25)
390 #define UHSIC_STROBE_RPU_D              (1 << 26)
391 #define UHSIC_DATA_RPU_D                (1 << 27)
392
393 #define UTMIP_UHSIC_STATUS              0x214
394
395 #define UTMIP_USBOP_VAL(inst)           (1 << ((2*(inst)) + 8))
396 #define UTMIP_USBOP_VAL_P2              (1 << 12)
397 #define UTMIP_USBOP_VAL_P1              (1 << 10)
398 #define UTMIP_USBOP_VAL_P0              (1 << 8)
399 #define UTMIP_USBON_VAL(inst)           (1 << ((2*(inst)) + 9))
400 #define UTMIP_USBON_VAL_P2              (1 << 13)
401 #define UTMIP_USBON_VAL_P1              (1 << 11)
402 #define UTMIP_USBON_VAL_P0              (1 << 9)
403 #define UHSIC_WAKE_ALARM                (1 << 19)
404 #define UTMIP_WAKE_ALARM(inst)          (1 << ((inst) + 16))
405 #define UTMIP_WAKE_ALARM_P2             (1 << 18)
406 #define UTMIP_WAKE_ALARM_P1             (1 << 17)
407 #define UTMIP_WAKE_ALARM_P0             (1 << 16)
408 #define UHSIC_DATA_VAL_P0               (1 << 15)
409 #define UHSIC_STROBE_VAL_P0             (1 << 14)
410 #define UTMIP_WALK_PTR_VAL(inst)        (0x3 << ((inst)*2))
411 #define UHSIC_WALK_PTR_VAL              (0x3 << 6)
412 #define UTMIP_WALK_PTR(inst)            (1 << ((inst)*2))
413 #define UTMIP_WALK_PTR_P2               (1 << 4)
414 #define UTMIP_WALK_PTR_P1               (1 << 2)
415 #define UTMIP_WALK_PTR_P0               (1 << 0)
416
417 #define USB1_PREFETCH_ID                           6
418 #define USB2_PREFETCH_ID                           18
419 #define USB3_PREFETCH_ID                           17
420
421 #define PMC_UTMIP_UHSIC_FAKE            0x218
422
423 #define UHSIC_STROBE_VAL                (1 << 12)
424 #define UHSIC_DATA_VAL                  (1 << 13)
425 #define UHSIC_STROBE_ENB                (1 << 14)
426 #define UHSIC_DATA_ENB                  (1 << 15)
427 #define   USBON_VAL(inst)       (1 << ((4*(inst))+1))
428 #define   USBON_VAL_P2                  (1 << 9)
429 #define   USBON_VAL_P1                  (1 << 5)
430 #define   USBON_VAL_P0                  (1 << 1)
431 #define   USBOP_VAL(inst)       (1 << (4*(inst)))
432 #define   USBOP_VAL_P2                  (1 << 8)
433 #define   USBOP_VAL_P1                  (1 << 4)
434 #define   USBOP_VAL_P0                  (1 << 0)
435
436 #define PMC_UTMIP_BIAS_MASTER_CNTRL 0x30c
437 #define   BIAS_MASTER_PROG_VAL          (1 << 1)
438
439 #define PMC_UTMIP_MASTER_CONFIG 0x310
440
441 #define UTMIP_PWR(inst)         (1 << (inst))
442 #define UHSIC_PWR                       (1 << 3)
443
444 #define FUSE_USB_CALIB_0                0x1F0
445 #define   XCVR_SETUP(x) (((x) & 0x7F) << 0)
446 #define   XCVR_SETUP_LSB_MASK   0xF
447 #define   XCVR_SETUP_MSB_MASK   0x70
448 #define   XCVR_SETUP_LSB_MAX_VAL        0xF
449
450 /* These values (in milli second) are taken from the battery charging spec */
451 #define TDP_SRC_ON_MS    100
452 #define TDPSRC_CON_MS    40
453
454 #ifdef DEBUG
455 #define DBG(stuff...)   pr_info("tegra3_usb_phy: " stuff)
456 #else
457 #define DBG(stuff...)   do {} while (0)
458 #endif
459
460 #if 0
461 #define PHY_DBG(stuff...)       pr_info("tegra3_usb_phy: " stuff)
462 #else
463 #define PHY_DBG(stuff...)       do {} while (0)
464 #endif
465
466 static u32 utmip_rctrl_val, utmip_tctrl_val;
467 static DEFINE_SPINLOCK(utmip_pad_lock);
468 static int utmip_pad_count;
469
470 static struct tegra_xtal_freq utmip_freq_table[] = {
471         {
472                 .freq = 12000000,
473                 .enable_delay = 0x02,
474                 .stable_count = 0x2F,
475                 .active_delay = 0x04,
476                 .xtal_freq_count = 0x76,
477                 .debounce = 0x7530,
478                 .pdtrk_count = 5,
479         },
480         {
481                 .freq = 13000000,
482                 .enable_delay = 0x02,
483                 .stable_count = 0x33,
484                 .active_delay = 0x05,
485                 .xtal_freq_count = 0x7F,
486                 .debounce = 0x7EF4,
487                 .pdtrk_count = 5,
488         },
489         {
490                 .freq = 19200000,
491                 .enable_delay = 0x03,
492                 .stable_count = 0x4B,
493                 .active_delay = 0x06,
494                 .xtal_freq_count = 0xBB,
495                 .debounce = 0xBB80,
496                 .pdtrk_count = 7,
497         },
498         {
499                 .freq = 26000000,
500                 .enable_delay = 0x04,
501                 .stable_count = 0x66,
502                 .active_delay = 0x09,
503                 .xtal_freq_count = 0xFE,
504                 .debounce = 0xFDE8,
505                 .pdtrk_count = 9,
506         },
507 };
508
509 static struct tegra_xtal_freq uhsic_freq_table[] = {
510         {
511                 .freq = 12000000,
512                 .enable_delay = 0x02,
513                 .stable_count = 0x2F,
514                 .active_delay = 0x0,
515                 .xtal_freq_count = 0x1CA,
516         },
517         {
518                 .freq = 13000000,
519                 .enable_delay = 0x02,
520                 .stable_count = 0x33,
521                 .active_delay = 0x0,
522                 .xtal_freq_count = 0x1F0,
523         },
524         {
525                 .freq = 19200000,
526                 .enable_delay = 0x03,
527                 .stable_count = 0x4B,
528                 .active_delay = 0x0,
529                 .xtal_freq_count = 0x2DD,
530         },
531         {
532                 .freq = 26000000,
533                 .enable_delay = 0x04,
534                 .stable_count = 0x66,
535                 .active_delay = 0x0,
536                 .xtal_freq_count = 0x3E0,
537         },
538 };
539
540 static void usb_phy_fence_read(struct tegra_usb_phy *phy)
541 {
542         /* Fence read for coherency of AHB master intiated writes */
543         if (phy->inst == 0)
544                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB1_PREFETCH_ID));
545         else if (phy->inst == 1)
546                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB2_PREFETCH_ID));
547         else if (phy->inst == 2)
548                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB3_PREFETCH_ID));
549
550         return;
551 }
552
553 static void utmip_setup_pmc_wake_detect(struct tegra_usb_phy *phy)
554 {
555         unsigned long val, pmc_pad_cfg_val;
556         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
557         unsigned  int inst = phy->inst;
558         void __iomem *base = phy->regs;
559         bool port_connected;
560         enum usb_phy_port_speed port_speed;
561
562         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
563
564         /* check for port connect status */
565         val = readl(base + USB_PORTSC);
566         port_connected = val & USB_PORTSC_CCS;
567
568         if (!port_connected)
569                 return;
570
571         port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
572                 HOSTPC1_DEVLC_PSPD_MASK;
573         /*Set PMC MASTER bits to do the following
574         * a. Take over the UTMI drivers
575         * b. set up such that it will take over resume
576         *        if remote wakeup is detected
577         * Prepare PMC to take over suspend-wake detect-drive resume until USB
578         * controller ready
579         */
580
581         /* disable master enable in PMC */
582         val = readl(pmc_base + PMC_SLEEP_CFG);
583         val &= ~UTMIP_MASTER_ENABLE(inst);
584         writel(val, pmc_base + PMC_SLEEP_CFG);
585
586         /* UTMIP_PWR_PX=1 for power savings mode */
587         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
588         val |= UTMIP_PWR(inst);
589         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
590
591         /* config debouncer */
592         val = readl(pmc_base + PMC_USB_DEBOUNCE);
593         val &= ~UTMIP_LINE_DEB_CNT(~0);
594         val |= UTMIP_LINE_DEB_CNT(4);
595         writel(val, pmc_base + PMC_USB_DEBOUNCE);
596
597         /* Make sure nothing is happening on the line with respect to PMC */
598         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
599         val &= ~USBOP_VAL(inst);
600         val &= ~USBON_VAL(inst);
601         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
602
603         /* Make sure wake value for line is none */
604         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
605         val &= ~UTMIP_LINEVAL_WALK_EN(inst);
606         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
607         val = readl(pmc_base + PMC_SLEEP_CFG);
608         val &= ~UTMIP_WAKE_VAL(inst, ~0);
609         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
610         writel(val, pmc_base + PMC_SLEEP_CFG);
611
612         /* turn off pad detectors */
613         val = readl(pmc_base + PMC_USB_AO);
614         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
615         writel(val, pmc_base + PMC_USB_AO);
616
617         /* Remove fake values and make synchronizers work a bit */
618         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
619         val &= ~USBOP_VAL(inst);
620         val &= ~USBON_VAL(inst);
621         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
622
623         /* Enable which type of event can trigger a walk,
624         in this case usb_line_wake */
625         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
626         val |= UTMIP_LINEVAL_WALK_EN(inst);
627         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
628
629         /* Enable which type of event can trigger a walk,
630         * in this case usb_line_wake */
631         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
632         val |= UTMIP_LINEVAL_WALK_EN(inst);
633         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
634
635         /* Clear the walk pointers and wake alarm */
636         val = readl(pmc_base + PMC_TRIGGERS);
637         val |= UTMIP_CLR_WAKE_ALARM(inst) | UTMIP_CLR_WALK_PTR(inst);
638         writel(val, pmc_base + PMC_TRIGGERS);
639
640
641         /* Capture FS/LS pad configurations */
642         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
643         val = readl(pmc_base + PMC_TRIGGERS);
644         val |= UTMIP_CAP_CFG(inst);
645         writel(val, pmc_base + PMC_TRIGGERS);
646         udelay(1);
647         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
648
649         /* BIAS MASTER_ENABLE=0 */
650         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
651         val &= ~BIAS_MASTER_PROG_VAL;
652         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
653
654         /* program walk sequence, maintain a J, followed by a driven K
655         * to signal a resume once an wake event is detected */
656         val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
657         val &= ~UTMIP_AP_A;
658         val |= UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_AN_A |UTMIP_HIGHZ_A |
659                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_AP_B | UTMIP_AN_B |
660                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_AP_C | UTMIP_AN_C |
661                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_AP_D | UTMIP_AN_D;
662         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
663
664         if (port_speed == USB_PHY_PORT_SPEED_LOW) {
665                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
666                 val &= ~(UTMIP_AN_B | UTMIP_HIGHZ_B | UTMIP_AN_C |
667                         UTMIP_HIGHZ_C | UTMIP_AN_D | UTMIP_HIGHZ_D);
668                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
669         } else {
670                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
671                 val &= ~(UTMIP_AP_B | UTMIP_HIGHZ_B | UTMIP_AP_C |
672                         UTMIP_HIGHZ_C | UTMIP_AP_D | UTMIP_HIGHZ_D);
673                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
674         }
675
676         /* turn on pad detectors */
677         val = readl(pmc_base + PMC_USB_AO);
678         val &= ~(USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
679         writel(val, pmc_base + PMC_USB_AO);
680
681         /* Add small delay before usb detectors provide stable line values */
682         mdelay(1);
683
684         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
685         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
686         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
687         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
688
689         phy->remote_wakeup = false;
690
691         /* Turn over pad configuration to PMC  for line wake events*/
692         val = readl(pmc_base + PMC_SLEEP_CFG);
693         val &= ~UTMIP_WAKE_VAL(inst, ~0);
694         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_ANY);
695         val |= UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst);
696         val |= UTMIP_MASTER_ENABLE(inst) | UTMIP_FSLS_USE_PMC(inst);
697         writel(val, pmc_base + PMC_SLEEP_CFG);
698
699         val = readl(base + UTMIP_PMC_WAKEUP0);
700         val |= EVENT_INT_ENB;
701         writel(val, base + UTMIP_PMC_WAKEUP0);
702         PHY_DBG("%s ENABLE_PMC inst = %d\n", __func__, inst);
703 }
704
705 static void utmip_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy)
706 {
707         unsigned long val;
708         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
709         unsigned  int inst = phy->inst;
710         void __iomem *base = phy->regs;
711
712         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
713
714         val = readl(pmc_base + PMC_SLEEP_CFG);
715         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
716         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
717         writel(val, pmc_base + PMC_SLEEP_CFG);
718
719         val = readl(pmc_base + PMC_TRIGGERS);
720         val |= UTMIP_CLR_WAKE_ALARM(inst) | UTMIP_CLR_WALK_PTR(inst);
721         writel(val, pmc_base + PMC_TRIGGERS);
722
723         val = readl(base + UTMIP_PMC_WAKEUP0);
724         val &= ~EVENT_INT_ENB;
725         writel(val, base + UTMIP_PMC_WAKEUP0);
726
727         /* Disable PMC master mode by clearing MASTER_EN */
728         val = readl(pmc_base + PMC_SLEEP_CFG);
729         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
730                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
731         writel(val, pmc_base + PMC_SLEEP_CFG);
732
733         val = readl(pmc_base + PMC_TRIGGERS);
734         val &= ~UTMIP_CAP_CFG(inst);
735         writel(val, pmc_base + PMC_TRIGGERS);
736
737         /* turn off pad detectors */
738         val = readl(pmc_base + PMC_USB_AO);
739         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
740         writel(val, pmc_base + PMC_USB_AO);
741
742         phy->remote_wakeup = false;
743         PHY_DBG("%s DISABLE_PMC inst = %d\n", __func__, inst);
744 }
745
746 static bool utmi_phy_remotewake_detected(struct tegra_usb_phy *phy)
747 {
748         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
749         void __iomem *base = phy->regs;
750         unsigned  int inst = phy->inst;
751         u32 val;
752
753         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
754         val = readl(base + UTMIP_PMC_WAKEUP0);
755         if (val & EVENT_INT_ENB) {
756                 val = readl(pmc_base + UTMIP_UHSIC_STATUS);
757                 if (UTMIP_WAKE_ALARM(inst) & val) {
758                         val = readl(pmc_base + PMC_SLEEP_CFG);
759                         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
760                         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
761                         writel(val, pmc_base + PMC_SLEEP_CFG);
762
763                         val = readl(pmc_base + PMC_TRIGGERS);
764                         val |= UTMIP_CLR_WAKE_ALARM(inst) |
765                                 UTMIP_CLR_WALK_PTR(inst);
766                         writel(val, pmc_base + PMC_TRIGGERS);
767
768                         val = readl(base + UTMIP_PMC_WAKEUP0);
769                         val &= ~EVENT_INT_ENB;
770                         writel(val, base + UTMIP_PMC_WAKEUP0);
771                         phy->remote_wakeup = true;
772                         return true;
773                 }
774         }
775         return false;
776 }
777
778 static void utmi_phy_enable_trking_data(struct tegra_usb_phy *phy)
779 {
780         void __iomem *base = IO_ADDRESS(TEGRA_USB_BASE);
781         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
782         static bool init_done = false;
783         u32 val;
784
785         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
786
787         /* Should be done only once after system boot */
788         if (init_done)
789                 return;
790
791         clk_enable(phy->utmi_pad_clk);
792         /* Bias pad MASTER_ENABLE=1 */
793         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
794         val |= BIAS_MASTER_PROG_VAL;
795         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
796
797         /* Setting the tracking length time */
798         val = readl(base + UTMIP_BIAS_CFG1);
799         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
800         val |= UTMIP_BIAS_PDTRK_COUNT(5);
801         writel(val, base + UTMIP_BIAS_CFG1);
802
803         /* Bias PDTRK is Shared and MUST be done from USB1 ONLY, PD_TRK=0 */
804         val = readl(base + UTMIP_BIAS_CFG1);
805         val &= ~UTMIP_BIAS_PDTRK_POWERDOWN;
806         writel(val, base + UTMIP_BIAS_CFG1);
807
808         val = readl(base + UTMIP_BIAS_CFG1);
809         val |= UTMIP_BIAS_PDTRK_POWERUP;
810         writel(val, base + UTMIP_BIAS_CFG1);
811
812         /* Wait for 25usec */
813         udelay(25);
814
815         /* Bias pad MASTER_ENABLE=0 */
816         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
817         val &= ~BIAS_MASTER_PROG_VAL;
818         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
819
820         /* Wait for 1usec */
821         udelay(1);
822
823         /* Bias pad MASTER_ENABLE=1 */
824         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
825         val |= BIAS_MASTER_PROG_VAL;
826         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
827
828         /* Read RCTRL and TCTRL from UTMIP space */
829         val = readl(base + UTMIP_BIAS_STS0);
830         utmip_rctrl_val = ffz(UTMIP_RCTRL_VAL(val));
831         utmip_tctrl_val = ffz(UTMIP_TCTRL_VAL(val));
832
833         /* PD_TRK=1 */
834         val = readl(base + UTMIP_BIAS_CFG1);
835         val |= UTMIP_BIAS_PDTRK_POWERDOWN;
836         writel(val, base + UTMIP_BIAS_CFG1);
837
838         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
839         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
840         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
841         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
842         clk_disable(phy->utmi_pad_clk);
843         init_done = true;
844 }
845
846 static void utmip_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy)
847 {
848         unsigned long val;
849         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
850         unsigned  int inst = phy->inst;
851
852         /* power down UTMIP interfaces */
853         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
854         val |= UTMIP_PWR(inst);
855         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
856
857         /* setup sleep walk usb controller */
858         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
859                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
860                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
861                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
862         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
863
864         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
865         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
866         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
867         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
868
869         /* Turn over pad configuration to PMC */
870         val = readl(pmc_base + PMC_SLEEP_CFG);
871         val &= ~UTMIP_WAKE_VAL(inst, ~0);
872         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE) |
873                 UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
874                 UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst);
875         writel(val, pmc_base + PMC_SLEEP_CFG);
876         PHY_DBG("%s ENABLE_PMC inst = %d\n", __func__, inst);
877 }
878
879 static void utmip_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
880 {
881         unsigned long val;
882         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
883         unsigned  int inst = phy->inst;
884
885         /* Disable PMC master mode by clearing MASTER_EN */
886         val = readl(pmc_base + PMC_SLEEP_CFG);
887         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
888                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
889         writel(val, pmc_base + PMC_SLEEP_CFG);
890         mdelay(1);
891         PHY_DBG("%s DISABLE_PMC inst = %d\n", __func__, inst);
892 }
893
894
895 #ifdef KERNEL_WARNING
896 static void usb_phy_power_down_pmc(void)
897 {
898         unsigned long val;
899         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
900
901         /* power down all 3 UTMIP interfaces */
902         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
903         val |= UTMIP_PWR(0) | UTMIP_PWR(1) | UTMIP_PWR(2);
904         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
905
906         /* turn on pad detectors */
907         writel(PMC_POWER_DOWN_MASK, pmc_base + PMC_USB_AO);
908
909         /* setup sleep walk fl all 3 usb controllers */
910         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
911                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
912                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
913                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
914         writel(val, pmc_base + PMC_SLEEPWALK_REG(0));
915         writel(val, pmc_base + PMC_SLEEPWALK_REG(1));
916         writel(val, pmc_base + PMC_SLEEPWALK_REG(2));
917
918         /* enable pull downs on HSIC PMC */
919         val = UHSIC_STROBE_RPD_A | UHSIC_DATA_RPD_A | UHSIC_STROBE_RPD_B |
920                 UHSIC_DATA_RPD_B | UHSIC_STROBE_RPD_C | UHSIC_DATA_RPD_C |
921                 UHSIC_STROBE_RPD_D | UHSIC_DATA_RPD_D;
922         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
923
924         /* Turn over pad configuration to PMC */
925         val = readl(pmc_base + PMC_SLEEP_CFG);
926         val &= ~UTMIP_WAKE_VAL(0, ~0);
927         val &= ~UTMIP_WAKE_VAL(1, ~0);
928         val &= ~UTMIP_WAKE_VAL(2, ~0);
929         val &= ~UHSIC_WAKE_VAL_P0(~0);
930         val |= UTMIP_WAKE_VAL(0, WAKE_VAL_NONE) | UHSIC_WAKE_VAL_P0(WAKE_VAL_NONE) |
931         UTMIP_WAKE_VAL(1, WAKE_VAL_NONE) | UTMIP_WAKE_VAL(2, WAKE_VAL_NONE) |
932         UTMIP_RCTRL_USE_PMC(0) | UTMIP_RCTRL_USE_PMC(1) | UTMIP_RCTRL_USE_PMC(2) |
933         UTMIP_TCTRL_USE_PMC(0) | UTMIP_TCTRL_USE_PMC(1) | UTMIP_TCTRL_USE_PMC(2) |
934         UTMIP_FSLS_USE_PMC(0) | UTMIP_FSLS_USE_PMC(1) | UTMIP_FSLS_USE_PMC(2) |
935         UTMIP_MASTER_ENABLE(0) | UTMIP_MASTER_ENABLE(1) | UTMIP_MASTER_ENABLE(2) |
936         UHSIC_MASTER_ENABLE_P0;
937         writel(val, pmc_base + PMC_SLEEP_CFG);
938 }
939 #endif
940
941 static int usb_phy_bringup_host_controller(struct tegra_usb_phy *phy)
942 {
943         unsigned long val;
944         void __iomem *base = phy->regs;
945
946         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
947         PHY_DBG("[%d] USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n", __LINE__,
948                 readl(base + USB_USBSTS), readl(base + USB_PORTSC),
949                                                         phy->port_speed);
950
951         /* Device is plugged in when system is in LP0 */
952         /* Bring up the controller from LP0*/
953         val = readl(base + USB_USBCMD);
954         val |= USB_CMD_RESET;
955         writel(val, base + USB_USBCMD);
956
957         if (usb_phy_reg_status_wait(base + USB_USBCMD,
958                 USB_CMD_RESET, 0, 2500) < 0) {
959                 pr_err("%s: timeout waiting for reset\n", __func__);
960         }
961
962         val = readl(base + USB_USBMODE);
963         val &= ~USB_USBMODE_MASK;
964         val |= USB_USBMODE_HOST;
965         writel(val, base + USB_USBMODE);
966         val = readl(base + HOSTPC1_DEVLC);
967         val &= ~HOSTPC1_DEVLC_PTS(~0);
968
969         if (phy->pdata->phy_intf == TEGRA_USB_PHY_INTF_HSIC)
970                 val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
971         else
972                 val |= HOSTPC1_DEVLC_STS;
973         writel(val, base + HOSTPC1_DEVLC);
974
975         /* Enable Port Power */
976         val = readl(base + USB_PORTSC);
977         val |= USB_PORTSC_PP;
978         writel(val, base + USB_PORTSC);
979         udelay(10);
980
981         /* Check if the phy resume from LP0. When the phy resume from LP0
982          * USB register will be reset.to zero */
983         if (!readl(base + USB_ASYNCLISTADDR)) {
984                 /* Program the field PTC based on the saved speed mode */
985                 val = readl(base + USB_PORTSC);
986                 val &= ~USB_PORTSC_PTC(~0);
987                 if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH)
988                         val |= USB_PORTSC_PTC(5);
989                 else if (phy->port_speed == USB_PHY_PORT_SPEED_FULL)
990                         val |= USB_PORTSC_PTC(6);
991                 else if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
992                         val |= USB_PORTSC_PTC(7);
993                 writel(val, base + USB_PORTSC);
994                 udelay(10);
995
996                 /* Disable test mode by setting PTC field to NORMAL_OP */
997                 val = readl(base + USB_PORTSC);
998                 val &= ~USB_PORTSC_PTC(~0);
999                 writel(val, base + USB_PORTSC);
1000                 udelay(10);
1001         }
1002
1003         /* Poll until CCS is enabled */
1004         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
1005                                                  USB_PORTSC_CCS, 2000)) {
1006                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
1007         }
1008
1009         /* Poll until PE is enabled */
1010         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_PE,
1011                                                  USB_PORTSC_PE, 2000)) {
1012                 pr_err("%s: timeout waiting for USB_PORTSC_PE\n", __func__);
1013         }
1014
1015         /* Clear the PCI status, to avoid an interrupt taken upon resume */
1016         val = readl(base + USB_USBSTS);
1017         val |= USB_USBSTS_PCI;
1018         writel(val, base + USB_USBSTS);
1019
1020         if (!phy->remote_wakeup) {
1021                 /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
1022                 val = readl(base + USB_PORTSC);
1023                 if ((val & USB_PORTSC_PP) && (val & USB_PORTSC_PE)) {
1024                         val |= USB_PORTSC_SUSP;
1025                         writel(val, base + USB_PORTSC);
1026                         /* Need a 4ms delay before the controller goes to suspend */
1027                         mdelay(4);
1028
1029                         /* Wait until port suspend completes */
1030                         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_SUSP,
1031                                                          USB_PORTSC_SUSP, 1000)) {
1032                                 pr_err("%s: timeout waiting for PORT_SUSPEND\n",
1033                                                                         __func__);
1034                         }
1035                 }
1036         }
1037         PHY_DBG("[%d] USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n", __LINE__,
1038                 readl(base + USB_USBSTS), readl(base + USB_PORTSC),
1039                                                         phy->port_speed);
1040
1041         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1042                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1043         return 0;
1044 }
1045
1046 static void usb_phy_wait_for_sof(struct tegra_usb_phy *phy)
1047 {
1048         unsigned long val;
1049         void __iomem *base = phy->regs;
1050
1051         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1052
1053         val = readl(base + USB_USBSTS);
1054         writel(val, base + USB_USBSTS);
1055         udelay(20);
1056         /* wait for two SOFs */
1057         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1058                 USB_USBSTS_SRI, 2500))
1059                 pr_err("%s: timeout waiting for SOF\n", __func__);
1060
1061         val = readl(base + USB_USBSTS);
1062         writel(val, base + USB_USBSTS);
1063         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI, 0, 2500))
1064                 pr_err("%s: timeout waiting for SOF\n", __func__);
1065
1066         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1067                         USB_USBSTS_SRI, 2500))
1068                 pr_err("%s: timeout waiting for SOF\n", __func__);
1069
1070         udelay(20);
1071 }
1072
1073 static unsigned int utmi_phy_xcvr_setup_value(struct tegra_usb_phy *phy)
1074 {
1075         struct tegra_utmi_config *cfg = &phy->pdata->u_cfg.utmi;
1076         signed long val;
1077
1078         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1079
1080         if (cfg->xcvr_use_fuses) {
1081                 val = XCVR_SETUP(tegra_fuse_readl(FUSE_USB_CALIB_0));
1082                 if (cfg->xcvr_use_lsb) {
1083                         val = min(((val & XCVR_SETUP_LSB_MASK) + cfg->xcvr_setup_offset),
1084                                         XCVR_SETUP_LSB_MAX_VAL);
1085                         val |= (cfg->xcvr_setup & XCVR_SETUP_MSB_MASK);
1086                 } else {
1087                         if (cfg->xcvr_setup_offset <= UTMIP_XCVR_MAX_OFFSET)
1088                                 val = val + cfg->xcvr_setup_offset;
1089
1090                         if (val > UTMIP_XCVR_SETUP_MAX_VALUE) {
1091                                 val = UTMIP_XCVR_SETUP_MAX_VALUE;
1092                                 pr_info("%s: reset XCVR_SETUP to max value\n",
1093                                                 __func__);
1094                         } else if (val < UTMIP_XCVR_SETUP_MIN_VALUE) {
1095                                 val = UTMIP_XCVR_SETUP_MIN_VALUE;
1096                                 pr_info("%s: reset XCVR_SETUP to min value\n",
1097                                                 __func__);
1098                         }
1099                 }
1100         } else {
1101                 val = cfg->xcvr_setup;
1102         }
1103
1104         return (unsigned int) val;
1105 }
1106
1107 static int utmi_phy_open(struct tegra_usb_phy *phy)
1108 {
1109         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1110         unsigned long parent_rate, val;
1111         int i;
1112
1113         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1114
1115         phy->utmi_pad_clk = clk_get_sys("utmip-pad", NULL);
1116         if (IS_ERR(phy->utmi_pad_clk)) {
1117                 pr_err("%s: can't get utmip pad clock\n", __func__);
1118                 return PTR_ERR(phy->utmi_pad_clk);
1119         }
1120
1121         phy->utmi_xcvr_setup = utmi_phy_xcvr_setup_value(phy);
1122
1123         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
1124         for (i = 0; i < ARRAY_SIZE(utmip_freq_table); i++) {
1125                 if (utmip_freq_table[i].freq == parent_rate) {
1126                         phy->freq = &utmip_freq_table[i];
1127                         break;
1128                 }
1129         }
1130         if (!phy->freq) {
1131                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
1132                 return -EINVAL;
1133         }
1134
1135         /* Power-up the VBUS detector for UTMIP PHY */
1136         val = readl(pmc_base + PMC_USB_AO);
1137         val &= ~(PMC_USB_AO_VBUS_WAKEUP_PD_P0 | PMC_USB_AO_ID_PD_P0);
1138         writel((val | PMC_USB_AO_PD_P2), (pmc_base + PMC_USB_AO));
1139
1140         utmip_powerup_pmc_wake_detect(phy);
1141
1142         return 0;
1143 }
1144
1145 static void utmi_phy_close(struct tegra_usb_phy *phy)
1146 {
1147         unsigned long val;
1148         void __iomem *base = phy->regs;
1149
1150         DBG("%s inst:[%d]\n", __func__, phy->inst);
1151
1152         /* Disable PHY clock valid interrupts while going into suspend*/
1153         if (phy->pdata->u_data.host.hot_plug) {
1154                 val = readl(base + USB_SUSP_CTRL);
1155                 val &= ~USB_PHY_CLK_VALID_INT_ENB;
1156                 writel(val, base + USB_SUSP_CTRL);
1157         }
1158
1159         clk_put(phy->utmi_pad_clk);
1160 }
1161
1162 static int utmi_phy_pad_power_on(struct tegra_usb_phy *phy)
1163 {
1164         unsigned long val, flags;
1165         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1166
1167         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1168
1169         clk_enable(phy->utmi_pad_clk);
1170
1171         spin_lock_irqsave(&utmip_pad_lock, flags);
1172         utmip_pad_count++;
1173
1174         val = readl(pad_base + UTMIP_BIAS_CFG0);
1175         val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
1176         val |= UTMIP_HSSQUELCH_LEVEL(0x2) | UTMIP_HSDISCON_LEVEL(0x1) |
1177                 UTMIP_HSDISCON_LEVEL_MSB;
1178         writel(val, pad_base + UTMIP_BIAS_CFG0);
1179
1180         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1181
1182         clk_disable(phy->utmi_pad_clk);
1183
1184         return 0;
1185 }
1186
1187 static int utmi_phy_pad_power_off(struct tegra_usb_phy *phy)
1188 {
1189         unsigned long val, flags;
1190         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1191
1192         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1193
1194         clk_enable(phy->utmi_pad_clk);
1195         spin_lock_irqsave(&utmip_pad_lock, flags);
1196
1197         if (!utmip_pad_count) {
1198                 pr_err("%s: utmip pad already powered off\n", __func__);
1199                 goto out;
1200         }
1201         if (--utmip_pad_count == 0) {
1202                 val = readl(pad_base + UTMIP_BIAS_CFG0);
1203                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
1204                 val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) | UTMIP_HSDISCON_LEVEL(~0) |
1205                         UTMIP_HSDISCON_LEVEL_MSB);
1206                 writel(val, pad_base + UTMIP_BIAS_CFG0);
1207         }
1208 out:
1209         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1210         clk_disable(phy->utmi_pad_clk);
1211
1212         return 0;
1213 }
1214
1215 static int utmi_phy_irq(struct tegra_usb_phy *phy)
1216 {
1217         void __iomem *base = phy->regs;
1218         unsigned long val = 0;
1219
1220         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1221         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1222                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1223         DBG("USB_USBMODE[0x%x] USB_USBCMD[0x%x]\n",
1224                         readl(base + USB_USBMODE), readl(base + USB_USBCMD));
1225
1226         usb_phy_fence_read(phy);
1227         /* check if there is any remote wake event */
1228         if (utmi_phy_remotewake_detected(phy))
1229                 pr_info("%s: utmip remote wake detected\n", __func__);
1230
1231         if (phy->pdata->u_data.host.hot_plug) {
1232                 val = readl(base + USB_SUSP_CTRL);
1233                 if ((val  & USB_PHY_CLK_VALID_INT_STS)) {
1234                         val &= ~USB_PHY_CLK_VALID_INT_ENB |
1235                                         USB_PHY_CLK_VALID_INT_STS;
1236                         writel(val , (base + USB_SUSP_CTRL));
1237                         pr_info("%s: usb device plugged-in\n", __func__);
1238                         val = readl(base + USB_USBSTS);
1239                         if (!(val  & USB_USBSTS_PCI))
1240                                 return IRQ_NONE;
1241                         val = readl(base + USB_PORTSC);
1242                         val &= ~(USB_PORTSC_WKCN | USB_PORTSC_RWC_BITS);
1243                         writel(val , (base + USB_PORTSC));
1244                 }
1245         }
1246
1247         return IRQ_HANDLED;
1248 }
1249
1250 static void utmi_phy_enable_obs_bus(struct tegra_usb_phy *phy)
1251 {
1252         unsigned long val;
1253         void __iomem *base = phy->regs;
1254
1255         /* (2LS WAR)is not required for LS and FS devices and is only for HS */
1256         if ((phy->port_speed == USB_PHY_PORT_SPEED_LOW) ||
1257                 (phy->port_speed == USB_PHY_PORT_SPEED_FULL)) {
1258                 /* do not enable the OBS bus */
1259                 val = readl(base + UTMIP_MISC_CFG0);
1260                 val &= ~(UTMIP_DPDM_OBSERVE_SEL(~0));
1261                 writel(val, base + UTMIP_MISC_CFG0);
1262                 DBG("%s(%d) Disable OBS bus\n", __func__, __LINE__);
1263                 return;
1264         }
1265         /* Force DP/DM pulldown active for Host mode */
1266         val = readl(base + UTMIP_MISC_CFG0);
1267         val |= FORCE_PULLDN_DM | FORCE_PULLDN_DP |
1268                         COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS;
1269         writel(val, base + UTMIP_MISC_CFG0);
1270         val = readl(base + UTMIP_MISC_CFG0);
1271         val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1272         if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
1273                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
1274         else
1275                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
1276         writel(val, base + UTMIP_MISC_CFG0);
1277         udelay(1);
1278
1279         val = readl(base + UTMIP_MISC_CFG0);
1280         val |= UTMIP_DPDM_OBSERVE;
1281         writel(val, base + UTMIP_MISC_CFG0);
1282         udelay(10);
1283         DBG("%s(%d) Enable OBS bus\n", __func__, __LINE__);
1284         PHY_DBG("ENABLE_OBS_BUS\n");
1285 }
1286
1287 static int utmi_phy_disable_obs_bus(struct tegra_usb_phy *phy)
1288 {
1289         unsigned long val;
1290         void __iomem *base = phy->regs;
1291         unsigned long flags;
1292
1293         /* check if OBS bus is already enabled */
1294         val = readl(base + UTMIP_MISC_CFG0);
1295         if (val & UTMIP_DPDM_OBSERVE) {
1296                 PHY_DBG("DISABLE_OBS_BUS\n");
1297
1298                 /* disable ALL interrupts on current CPU */
1299                 local_irq_save(flags);
1300
1301                 /* Change the UTMIP OBS bus to drive SE0 */
1302                 val = readl(base + UTMIP_MISC_CFG0);
1303                 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1304                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_SE0;
1305                 writel(val, base + UTMIP_MISC_CFG0);
1306
1307                 /* Wait for 3us(2 LS bit times) */
1308                 udelay(3);
1309
1310                 /* Release UTMIP OBS bus */
1311                 val = readl(base + UTMIP_MISC_CFG0);
1312                 val &= ~UTMIP_DPDM_OBSERVE;
1313                 writel(val, base + UTMIP_MISC_CFG0);
1314
1315                 /* Release DP/DM pulldown for Host mode */
1316                 val = readl(base + UTMIP_MISC_CFG0);
1317                 val &= ~(FORCE_PULLDN_DM | FORCE_PULLDN_DP |
1318                                 COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS);
1319                 writel(val, base + UTMIP_MISC_CFG0);
1320
1321                 val = readl(base + USB_USBCMD);
1322                 val |= USB_USBCMD_RS;
1323                 writel(val, base + USB_USBCMD);
1324
1325                 /* restore ALL interrupts on current CPU */
1326                 local_irq_restore(flags);
1327
1328                 if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
1329                                                          USB_USBCMD_RS, 2000)) {
1330                         pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
1331                         return -ETIMEDOUT;
1332                 }
1333         }
1334         return 0;
1335 }
1336
1337 static int utmi_phy_post_resume(struct tegra_usb_phy *phy)
1338 {
1339         unsigned long val;
1340         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1341         unsigned  int inst = phy->inst;
1342
1343         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1344         val = readl(pmc_base + PMC_SLEEP_CFG);
1345         /* if PMC is not disabled by now then disable it */
1346         if (val & UTMIP_MASTER_ENABLE(inst)) {
1347                 utmip_phy_disable_pmc_bus_ctrl(phy);
1348         }
1349
1350         utmi_phy_disable_obs_bus(phy);
1351
1352         return 0;
1353 }
1354
1355 static void phy_post_suspend(struct tegra_usb_phy *phy)
1356 {
1357
1358         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1359         /* Need a 4ms delay for controller to suspend */
1360         mdelay(4);
1361
1362 }
1363
1364 static int utmi_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1365 {
1366         unsigned long val;
1367         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1368         void __iomem *base = phy->regs;
1369         unsigned  int inst = phy->inst;
1370
1371         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1372         phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
1373                         HOSTPC1_DEVLC_PSPD_MASK;
1374
1375         if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH) {
1376                 /* Disable interrupts */
1377                 writel(0, base + USB_USBINTR);
1378                 /* Clear the run bit to stop SOFs - 2LS WAR */
1379                 val = readl(base + USB_USBCMD);
1380                 val &= ~USB_USBCMD_RS;
1381                 writel(val, base + USB_USBCMD);
1382                 if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
1383                                                          USB_USBSTS_HCH, 2000)) {
1384                         pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
1385                 }
1386         }
1387
1388         val = readl(pmc_base + PMC_SLEEP_CFG);
1389         if (val & UTMIP_MASTER_ENABLE(inst)) {
1390                 if (!remote_wakeup)
1391                         utmip_phy_disable_pmc_bus_ctrl(phy);
1392         } else {
1393                 utmi_phy_enable_obs_bus(phy);
1394         }
1395
1396         return 0;
1397 }
1398
1399 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
1400 {
1401         unsigned long val;
1402         void __iomem *base = phy->regs;
1403
1404         PHY_DBG("%s(%d) inst:[%d] BEGIN\n", __func__, __LINE__, phy->inst);
1405         if (!phy->phy_clk_on) {
1406                 PHY_DBG("%s(%d) inst:[%d] phy clk is already off\n",
1407                                         __func__, __LINE__, phy->inst);
1408                 return 0;
1409         }
1410
1411         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1412                 utmip_powerdown_pmc_wake_detect(phy);
1413
1414                 val = readl(base + USB_SUSP_CTRL);
1415                 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
1416                 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
1417                 writel(val, base + USB_SUSP_CTRL);
1418
1419                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1420                 val |= UTMIP_PD_CHRG;
1421                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1422         } else {
1423                 phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
1424                                 HOSTPC1_DEVLC_PSPD_MASK;
1425
1426                 /* Disable interrupts */
1427                 writel(0, base + USB_USBINTR);
1428
1429                 /* Clear the run bit to stop SOFs - 2LS WAR */
1430                 val = readl(base + USB_USBCMD);
1431                 val &= ~USB_USBCMD_RS;
1432                 writel(val, base + USB_USBCMD);
1433
1434                 if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
1435                                                          USB_USBSTS_HCH, 2000)) {
1436                         pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
1437                 }
1438                 utmip_setup_pmc_wake_detect(phy);
1439         }
1440
1441         if (!phy->pdata->u_data.host.hot_plug) {
1442                 val = readl(base + UTMIP_XCVR_CFG0);
1443                 val |= (UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
1444                          UTMIP_FORCE_PDZI_POWERDOWN);
1445                 writel(val, base + UTMIP_XCVR_CFG0);
1446         }
1447
1448         val = readl(base + UTMIP_XCVR_CFG1);
1449         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1450                    UTMIP_FORCE_PDDR_POWERDOWN;
1451         writel(val, base + UTMIP_XCVR_CFG1);
1452
1453         val = readl(base + UTMIP_BIAS_CFG1);
1454         val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
1455         writel(val, base + UTMIP_BIAS_CFG1);
1456
1457         utmi_phy_pad_power_off(phy);
1458
1459         if (phy->pdata->u_data.host.hot_plug) {
1460                 bool enable_hotplug = true;
1461                 /* if it is OTG port then make sure to enable hot-plug feature
1462                    only if host adaptor is connected, i.e id is low */
1463                 if (phy->pdata->port_otg) {
1464                         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1465                         enable_hotplug = (val & USB_ID_STATUS) ? false : true;
1466                 }
1467                 if (enable_hotplug) {
1468                         val = readl(base + USB_PORTSC);
1469                         val |= USB_PORTSC_WKCN;
1470                         writel(val, base + USB_PORTSC);
1471
1472                         val = readl(base + USB_SUSP_CTRL);
1473                         val |= USB_PHY_CLK_VALID_INT_ENB;
1474                         writel(val, base + USB_SUSP_CTRL);
1475                 } else {
1476                         /* Disable PHY clock valid interrupts while going into suspend*/
1477                         val = readl(base + USB_SUSP_CTRL);
1478                         val &= ~USB_PHY_CLK_VALID_INT_ENB;
1479                         writel(val, base + USB_SUSP_CTRL);
1480                 }
1481         }
1482
1483         val = readl(base + HOSTPC1_DEVLC);
1484         val |= HOSTPC1_DEVLC_PHCD;
1485         writel(val, base + HOSTPC1_DEVLC);
1486
1487         if (!phy->pdata->u_data.host.hot_plug) {
1488                 val = readl(base + USB_SUSP_CTRL);
1489                 val |= UTMIP_RESET;
1490                 writel(val, base + USB_SUSP_CTRL);
1491         }
1492
1493         phy->phy_clk_on = false;
1494         phy->hw_accessible = false;
1495
1496         PHY_DBG("%s(%d) inst:[%d] END\n", __func__, __LINE__, phy->inst);
1497
1498         return 0;
1499 }
1500
1501
1502 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
1503 {
1504         unsigned long val;
1505         void __iomem *base = phy->regs;
1506         struct tegra_utmi_config *config = &phy->pdata->u_cfg.utmi;
1507
1508         PHY_DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1509         if (phy->phy_clk_on) {
1510                 PHY_DBG("%s(%d) inst:[%d] phy clk is already On\n",
1511                                         __func__, __LINE__, phy->inst);
1512                 return 0;
1513         }
1514         val = readl(base + USB_SUSP_CTRL);
1515         val |= UTMIP_RESET;
1516         writel(val, base + USB_SUSP_CTRL);
1517
1518         val = readl(base + UTMIP_TX_CFG0);
1519         val |= UTMIP_FS_PREABMLE_J;
1520         writel(val, base + UTMIP_TX_CFG0);
1521
1522         val = readl(base + UTMIP_HSRX_CFG0);
1523         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
1524         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
1525         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
1526         writel(val, base + UTMIP_HSRX_CFG0);
1527
1528         val = readl(base + UTMIP_HSRX_CFG1);
1529         val &= ~UTMIP_HS_SYNC_START_DLY(~0);
1530         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
1531         writel(val, base + UTMIP_HSRX_CFG1);
1532
1533         val = readl(base + UTMIP_DEBOUNCE_CFG0);
1534         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
1535         val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
1536         writel(val, base + UTMIP_DEBOUNCE_CFG0);
1537
1538         val = readl(base + UTMIP_MISC_CFG0);
1539         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
1540         writel(val, base + UTMIP_MISC_CFG0);
1541
1542         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1543                 val = readl(base + USB_SUSP_CTRL);
1544                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
1545                 writel(val, base + USB_SUSP_CTRL);
1546
1547                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1548                 val &= ~UTMIP_PD_CHRG;
1549                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1550         } else {
1551                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1552                 val |= UTMIP_PD_CHRG;
1553                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1554         }
1555
1556         utmi_phy_pad_power_on(phy);
1557
1558         val = readl(base + UTMIP_XCVR_CFG0);
1559         val &= ~(UTMIP_XCVR_LSBIAS_SEL | UTMIP_FORCE_PD_POWERDOWN |
1560                  UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN |
1561                  UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_LSFSLEW(~0) |
1562                  UTMIP_XCVR_LSRSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
1563         val |= UTMIP_XCVR_SETUP(phy->utmi_xcvr_setup);
1564         val |= UTMIP_XCVR_SETUP_MSB(XCVR_SETUP_MSB_CALIB(phy->utmi_xcvr_setup));
1565         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
1566         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
1567         if (!config->xcvr_use_lsb)
1568                 val |= UTMIP_XCVR_HSSLEW_MSB(0x8);
1569         writel(val, base + UTMIP_XCVR_CFG0);
1570
1571         val = readl(base + UTMIP_XCVR_CFG1);
1572         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1573                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
1574         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
1575         writel(val, base + UTMIP_XCVR_CFG1);
1576
1577         val = readl(base + UTMIP_BIAS_CFG1);
1578         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
1579         val |= UTMIP_BIAS_PDTRK_COUNT(phy->freq->pdtrk_count);
1580         writel(val, base + UTMIP_BIAS_CFG1);
1581
1582         val = readl(base + UTMIP_SPARE_CFG0);
1583         val &= ~FUSE_SETUP_SEL;
1584         val |= FUSE_ATERM_SEL;
1585         writel(val, base + UTMIP_SPARE_CFG0);
1586
1587         val = readl(base + USB_SUSP_CTRL);
1588         val |= UTMIP_PHY_ENABLE;
1589         writel(val, base + USB_SUSP_CTRL);
1590
1591         val = readl(base + USB_SUSP_CTRL);
1592         val &= ~UTMIP_RESET;
1593         writel(val, base + USB_SUSP_CTRL);
1594
1595         val = readl(base + HOSTPC1_DEVLC);
1596         val &= ~HOSTPC1_DEVLC_PHCD;
1597         writel(val, base + HOSTPC1_DEVLC);
1598
1599         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1600                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500))
1601                 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
1602
1603         utmi_phy_enable_trking_data(phy);
1604
1605         if (phy->inst == 2)
1606                 writel(0, base + ICUSB_CTRL);
1607
1608         val = readl(base + USB_USBMODE);
1609         val &= ~USB_USBMODE_MASK;
1610         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST)
1611                 val |= USB_USBMODE_HOST;
1612         else
1613                 val |= USB_USBMODE_DEVICE;
1614         writel(val, base + USB_USBMODE);
1615
1616         val = readl(base + HOSTPC1_DEVLC);
1617         val &= ~HOSTPC1_DEVLC_PTS(~0);
1618         val |= HOSTPC1_DEVLC_STS;
1619         writel(val, base + HOSTPC1_DEVLC);
1620
1621         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE)
1622                 utmip_powerup_pmc_wake_detect(phy);
1623         phy->phy_clk_on = true;
1624         phy->hw_accessible = true;
1625         PHY_DBG("%s(%d) End inst:[%d]\n", __func__, __LINE__, phy->inst);
1626         return 0;
1627 }
1628
1629 static void utmi_phy_restore_start(struct tegra_usb_phy *phy)
1630 {
1631         unsigned long val;
1632         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1633         int inst = phy->inst;
1634
1635         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1636         val = readl(pmc_base + UTMIP_UHSIC_STATUS);
1637         /* check whether we wake up from the remote resume */
1638         if (UTMIP_WALK_PTR_VAL(inst) & val) {
1639                 phy->remote_wakeup = true;
1640         } else {
1641                 if (!((UTMIP_USBON_VAL(phy->inst) |
1642                         UTMIP_USBOP_VAL(phy->inst)) & val)) {
1643                                 utmip_phy_disable_pmc_bus_ctrl(phy);
1644                 }
1645         }
1646         utmi_phy_enable_obs_bus(phy);
1647 }
1648
1649 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
1650 {
1651         unsigned long val;
1652         void __iomem *base = phy->regs;
1653         int wait_time_us = 25000; /* FPR should be set by this time */
1654
1655         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1656         /* check whether we wake up from the remote resume */
1657         if (phy->remote_wakeup) {
1658                 /* wait until SUSPEND and RESUME bit is cleared on remote resume */
1659                 do {
1660                         val = readl(base + USB_PORTSC);
1661                         udelay(1);
1662                         if (wait_time_us == 0) {
1663                                 PHY_DBG("%s PMC REMOTE WAKEUP FPR timeout val = 0x%x instance = %d\n", __func__, val, phy->inst);
1664                                 utmip_phy_disable_pmc_bus_ctrl(phy);
1665                                 utmi_phy_post_resume(phy);
1666                                 return;
1667                         }
1668                         wait_time_us--;
1669                 } while (val & (USB_PORTSC_RESUME | USB_PORTSC_SUSP));
1670
1671                 /* wait for 25 ms to port resume complete */
1672                 msleep(25);
1673                 /* disable PMC master control */
1674                 utmip_phy_disable_pmc_bus_ctrl(phy);
1675
1676                 /* Clear PCI and SRI bits to avoid an interrupt upon resume */
1677                 val = readl(base + USB_USBSTS);
1678                 writel(val, base + USB_USBSTS);
1679                 /* wait to avoid SOF if there is any */
1680                 if (usb_phy_reg_status_wait(base + USB_USBSTS,
1681                         USB_USBSTS_SRI, USB_USBSTS_SRI, 2500) < 0) {
1682                         pr_err("%s: timeout waiting for SOF\n", __func__);
1683                 }
1684                 utmi_phy_post_resume(phy);
1685         }
1686 }
1687
1688 static int utmi_phy_resume(struct tegra_usb_phy *phy)
1689 {
1690         int status = 0;
1691         unsigned long val;
1692         void __iomem *base = phy->regs;
1693
1694         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1695         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) {
1696                 if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
1697                         utmi_phy_restore_start(phy);
1698                         usb_phy_bringup_host_controller(phy);
1699                         utmi_phy_restore_end(phy);
1700                 } else {
1701                         /* device is plugged in when system is in LP0 */
1702                         /* bring up the controller from LP0*/
1703                         val = readl(base + USB_USBCMD);
1704                         val |= USB_CMD_RESET;
1705                         writel(val, base + USB_USBCMD);
1706
1707                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1708                                 USB_CMD_RESET, 0, 2500) < 0) {
1709                                 pr_err("%s: timeout waiting for reset\n", __func__);
1710                         }
1711
1712                         val = readl(base + USB_USBMODE);
1713                         val &= ~USB_USBMODE_MASK;
1714                         val |= USB_USBMODE_HOST;
1715                         writel(val, base + USB_USBMODE);
1716
1717                         val = readl(base + HOSTPC1_DEVLC);
1718                         val &= ~HOSTPC1_DEVLC_PTS(~0);
1719                         val |= HOSTPC1_DEVLC_STS;
1720                         writel(val, base + HOSTPC1_DEVLC);
1721
1722                         writel(USB_USBCMD_RS, base + USB_USBCMD);
1723
1724                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1725                                 USB_USBCMD_RS, USB_USBCMD_RS, 2500) < 0) {
1726                                 pr_err("%s: timeout waiting for run bit\n", __func__);
1727                         }
1728
1729                         /* Enable Port Power */
1730                         val = readl(base + USB_PORTSC);
1731                         val |= USB_PORTSC_PP;
1732                         writel(val, base + USB_PORTSC);
1733                         udelay(10);
1734
1735                         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1736                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1737                 }
1738         }
1739
1740         return status;
1741 }
1742
1743 static bool utmi_phy_charger_detect(struct tegra_usb_phy *phy)
1744 {
1745         unsigned long val;
1746         void __iomem *base = phy->regs;
1747         bool status;
1748
1749         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1750         if (phy->pdata->op_mode != TEGRA_USB_OPMODE_DEVICE) {
1751                 /* Charger detection is not there for ULPI
1752                  * return Charger not available */
1753                 return false;
1754         }
1755
1756         /* Enable charger detection logic */
1757         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1758         val |= UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN;
1759         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1760
1761         /* Source should be on for 100 ms as per USB charging spec */
1762         msleep(TDP_SRC_ON_MS);
1763
1764         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1765         /* If charger is not connected disable the interrupt */
1766         val &= ~VDAT_DET_INT_EN;
1767         val |= VDAT_DET_CHG_DET;
1768         writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
1769
1770         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1771         if (val & VDAT_DET_STS)
1772                 status = true;
1773         else
1774                 status = false;
1775
1776         /* Disable charger detection logic */
1777         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1778         val &= ~(UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN);
1779         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1780
1781         /* Delay of 40 ms before we pull the D+ as per battery charger spec */
1782         msleep(TDPSRC_CON_MS);
1783
1784         return status;
1785 }
1786
1787 static void uhsic_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
1788 {
1789         unsigned long val;
1790         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1791
1792         /* turn on pad detectors for HSIC*/
1793         val = readl(pmc_base + PMC_USB_AO);
1794         val &= ~(HSIC_RESERVED_P0 | STROBE_VAL_PD_P0 | DATA_VAL_PD_P0);
1795         writel(val, pmc_base + PMC_USB_AO);
1796
1797         /* Disable PMC master mode by clearing MASTER_EN */
1798         val = readl(pmc_base + PMC_SLEEP_CFG);
1799         val &= ~(UHSIC_MASTER_ENABLE_P0);
1800         writel(val, pmc_base + PMC_SLEEP_CFG);
1801         mdelay(1);
1802 }
1803
1804 static void uhsic_setup_pmc_wake_detect(struct tegra_usb_phy *phy)
1805 {
1806         unsigned long val;
1807         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1808         void __iomem *base = phy->regs;
1809         bool port_connected;
1810
1811         DBG("%s:%d\n", __func__, __LINE__);
1812
1813         /* check for port connect status */
1814         val = readl(base + USB_PORTSC);
1815         port_connected = val & USB_PORTSC_CCS;
1816
1817         if (!port_connected)
1818                 return;
1819
1820         /*Set PMC MASTER bits to do the following
1821         * a. Take over the hsic drivers
1822         * b. set up such that it will take over resume
1823         *        if remote wakeup is detected
1824         * Prepare PMC to take over suspend-wake detect-drive resume until USB
1825         * controller ready
1826         */
1827
1828         /* disable master enable in PMC */
1829         val = readl(pmc_base + PMC_SLEEP_CFG);
1830         val &= ~UHSIC_MASTER_ENABLE_P0;
1831         writel(val, pmc_base + PMC_SLEEP_CFG);
1832
1833         /* UTMIP_PWR_PX=1 for power savings mode */
1834         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
1835         val |= UHSIC_PWR;
1836         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
1837
1838
1839         /* Enable which type of event can trigger a walk,
1840         * in this case usb_line_wake */
1841         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
1842         val |= UHSIC_LINEVAL_WALK_EN;
1843         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
1844
1845         /* program walk sequence, maintain a J, followed by a driven K
1846         * to signal a resume once an wake event is detected */
1847
1848         val = readl(pmc_base + PMC_SLEEPWALK_UHSIC);
1849
1850         val &= ~UHSIC_DATA_RPU_A;
1851         val |=  UHSIC_DATA_RPD_A;
1852         val &= ~UHSIC_STROBE_RPD_A;
1853         val |=  UHSIC_STROBE_RPU_A;
1854         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1855
1856         val &= ~UHSIC_DATA_RPD_B;
1857         val |=  UHSIC_DATA_RPU_B;
1858         val &= ~UHSIC_STROBE_RPU_B;
1859         val |=  UHSIC_STROBE_RPD_B;
1860         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1861
1862         val &= ~UHSIC_DATA_RPD_C;
1863         val |=  UHSIC_DATA_RPU_C;
1864         val &= ~UHSIC_STROBE_RPU_C;
1865         val |=  UHSIC_STROBE_RPD_C;
1866         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1867
1868         val &= ~UHSIC_DATA_RPD_D;
1869         val |=  UHSIC_DATA_RPU_D;
1870         val &= ~UHSIC_STROBE_RPU_D;
1871         val |=  UHSIC_STROBE_RPD_D;
1872         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1873
1874         /* turn on pad detectors */
1875         val = readl(pmc_base + PMC_USB_AO);
1876         val &= ~(STROBE_VAL_PD_P0 | DATA_VAL_PD_P0);
1877         writel(val, pmc_base + PMC_USB_AO);
1878         /* Add small delay before usb detectors provide stable line values */
1879         udelay(1);
1880
1881         phy->remote_wakeup = false;
1882
1883         /* Turn over pad configuration to PMC  for line wake events*/
1884         val = readl(pmc_base + PMC_SLEEP_CFG);
1885         val &= ~UHSIC_WAKE_VAL(~0);
1886         val |= UHSIC_WAKE_VAL(WAKE_VAL_SD10);
1887         val |= UHSIC_MASTER_ENABLE;
1888         writel(val, pmc_base + PMC_SLEEP_CFG);
1889
1890         val = readl(base + UHSIC_PMC_WAKEUP0);
1891         val |= EVENT_INT_ENB;
1892         writel(val, base + UHSIC_PMC_WAKEUP0);
1893
1894         DBG("%s:PMC enabled for HSIC remote wakeup\n", __func__);
1895 }
1896
1897 static void uhsic_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy)
1898 {
1899         unsigned long val;
1900         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1901         void __iomem *base = phy->regs;
1902
1903         DBG("%s (%d)\n", __func__, __LINE__);
1904         val = readl(pmc_base + PMC_SLEEP_CFG);
1905         val &= ~UHSIC_WAKE_VAL(0x0);
1906         val |= UHSIC_WAKE_VAL(WAKE_VAL_NONE);
1907         writel(val, pmc_base + PMC_SLEEP_CFG);
1908
1909         val = readl(pmc_base + PMC_TRIGGERS);
1910         val |= UHSIC_CLR_WAKE_ALARM_P0 | UHSIC_CLR_WALK_PTR_P0;
1911         writel(val, pmc_base + PMC_TRIGGERS);
1912
1913         val = readl(base + UHSIC_PMC_WAKEUP0);
1914         val &= ~EVENT_INT_ENB;
1915         writel(val, base + UHSIC_PMC_WAKEUP0);
1916
1917         /* Disable PMC master mode by clearing MASTER_EN */
1918         val = readl(pmc_base + PMC_SLEEP_CFG);
1919         val &= ~(UHSIC_MASTER_ENABLE);
1920         writel(val, pmc_base + PMC_SLEEP_CFG);
1921
1922         /* turn off pad detectors */
1923         val = readl(pmc_base + PMC_USB_AO);
1924         val |= (STROBE_VAL_PD_P0 | DATA_VAL_PD_P0);
1925         writel(val, pmc_base + PMC_USB_AO);
1926
1927         phy->remote_wakeup = false;
1928 }
1929
1930 static bool uhsic_phy_remotewake_detected(struct tegra_usb_phy *phy)
1931 {
1932         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1933         void __iomem *base = phy->regs;
1934         u32 val;
1935
1936         val = readl(base + UHSIC_PMC_WAKEUP0);
1937         if (val & EVENT_INT_ENB) {
1938                 val = readl(pmc_base + UTMIP_UHSIC_STATUS);
1939                 if (UHSIC_WAKE_ALARM & val) {
1940                         val = readl(pmc_base + PMC_SLEEP_CFG);
1941                         val &= ~UHSIC_WAKE_VAL(0x0);
1942                         val |= UHSIC_WAKE_VAL(WAKE_VAL_NONE);
1943                         writel(val, pmc_base + PMC_SLEEP_CFG);
1944
1945                         val = readl(pmc_base + PMC_TRIGGERS);
1946                         val |= UHSIC_CLR_WAKE_ALARM_P0 | UHSIC_CLR_WALK_PTR_P0;
1947                         writel(val, pmc_base + PMC_TRIGGERS);
1948
1949                         val = readl(base + UHSIC_PMC_WAKEUP0);
1950                         val &= ~EVENT_INT_ENB;
1951                         writel(val, base + UHSIC_PMC_WAKEUP0);
1952                         phy->remote_wakeup = true;
1953                         DBG("%s:PMC remote wakeup detected for HSIC\n", __func__);
1954                         return true;
1955                 }
1956         }
1957         return false;
1958 }
1959
1960 static int uhsic_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1961 {
1962         DBG("%s(%d)\n", __func__, __LINE__);
1963
1964         if (!remote_wakeup)
1965                 usb_phy_wait_for_sof(phy);
1966
1967         return 0;
1968 }
1969
1970 static int uhsic_phy_post_resume(struct tegra_usb_phy *phy)
1971 {
1972         unsigned long val;
1973         void __iomem *base = phy->regs;
1974
1975         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1976         val = readl(base + USB_TXFILLTUNING);
1977         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
1978                 val = USB_FIFO_TXFILL_THRES(0x10);
1979                 writel(val, base + USB_TXFILLTUNING);
1980         }
1981
1982         return 0;
1983 }
1984
1985 static void uhsic_phy_restore_start(struct tegra_usb_phy *phy)
1986 {
1987         unsigned long val;
1988         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1989         void __iomem *base = phy->regs;
1990
1991         val = readl(pmc_base + UTMIP_UHSIC_STATUS);
1992
1993         /* check whether we wake up from the remote resume */
1994         if (UHSIC_WALK_PTR_VAL & val) {
1995                 phy->remote_wakeup = true;
1996         } else {
1997                 if (!((UHSIC_STROBE_VAL_P0 | UHSIC_DATA_VAL_P0) & val)) {
1998                                 uhsic_phy_disable_pmc_bus_ctrl(phy);
1999                 } else {
2000                         DBG("%s(%d): setting pretend connect\n", __func__, __LINE__);
2001                         val = readl(base + UHSIC_CMD_CFG0);
2002                         val |= UHSIC_PRETEND_CONNECT_DETECT;
2003                         writel(val, base + UHSIC_CMD_CFG0);
2004                 }
2005         }
2006 }
2007
2008 static void uhsic_phy_restore_end(struct tegra_usb_phy *phy)
2009 {
2010
2011         unsigned long val;
2012         void __iomem *base = phy->regs;
2013         int wait_time_us = 3000; /* FPR should be set by this time */
2014
2015         DBG("%s(%d)\n", __func__, __LINE__);
2016
2017         /* check whether we wake up from the remote resume */
2018         if (phy->remote_wakeup) {
2019                 /* wait until FPR bit is set automatically on remote resume */
2020                 do {
2021                         val = readl(base + USB_PORTSC);
2022                         udelay(1);
2023                         if (wait_time_us == 0) {
2024                                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2025                                 uhsic_phy_post_resume(phy);
2026                                 return;
2027                         }
2028                         wait_time_us--;
2029                 } while (!(val & USB_PORTSC_RESUME));
2030                 /* wait for 25 ms to port resume complete */
2031                 msleep(25);
2032                 /* disable PMC master control */
2033                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2034
2035                 /* Clear PCI and SRI bits to avoid an interrupt upon resume */
2036                 val = readl(base + USB_USBSTS);
2037                 writel(val, base + USB_USBSTS);
2038                 /* wait to avoid SOF if there is any */
2039                 if (usb_phy_reg_status_wait(base + USB_USBSTS,
2040                         USB_USBSTS_SRI, USB_USBSTS_SRI, 2500)) {
2041                         pr_warn("%s: timeout waiting for SOF\n", __func__);
2042                 }
2043                 uhsic_phy_post_resume(phy);
2044         } else {
2045                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2046         }
2047
2048         /* Set RUN bit */
2049         val = readl(base + USB_USBCMD);
2050         val |= USB_USBCMD_RS;
2051         writel(val, base + USB_USBCMD);
2052         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2053                                                  USB_USBCMD_RS, 2000)) {
2054                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2055                 return;
2056         }
2057 }
2058
2059 static int uhsic_phy_open(struct tegra_usb_phy *phy)
2060 {
2061         unsigned long parent_rate;
2062         int i;
2063
2064         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2065         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
2066         for (i = 0; i < ARRAY_SIZE(uhsic_freq_table); i++) {
2067                 if (uhsic_freq_table[i].freq == parent_rate) {
2068                         phy->freq = &uhsic_freq_table[i];
2069                         break;
2070                 }
2071         }
2072         if (!phy->freq) {
2073                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
2074                 return -EINVAL;
2075         }
2076
2077         uhsic_powerup_pmc_wake_detect(phy);
2078
2079         return 0;
2080 }
2081
2082 static int uhsic_phy_irq(struct tegra_usb_phy *phy)
2083 {
2084         usb_phy_fence_read(phy);
2085         /* check if there is any remote wake event */
2086         if (uhsic_phy_remotewake_detected(phy))
2087                 pr_info("%s: uhsic remote wake detected\n", __func__);
2088         return IRQ_HANDLED;
2089 }
2090
2091 static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
2092 {
2093         unsigned long val;
2094         void __iomem *base = phy->regs;
2095         struct tegra_hsic_config *config = &phy->pdata->u_cfg.hsic;
2096
2097         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2098
2099         if (phy->phy_clk_on) {
2100                 DBG("%s(%d) inst:[%d] phy clk is already On\n",
2101                                         __func__, __LINE__, phy->inst);
2102                 return 0;
2103         }
2104
2105         val = readl(base + UHSIC_PADS_CFG1);
2106         val &= ~(UHSIC_PD_BG | UHSIC_PD_TX | UHSIC_PD_TRK | UHSIC_PD_RX |
2107                         UHSIC_PD_ZI | UHSIC_RPD_DATA | UHSIC_RPD_STROBE);
2108         val |= UHSIC_RX_SEL;
2109         writel(val, base + UHSIC_PADS_CFG1);
2110         udelay(2);
2111
2112         val = readl(base + USB_SUSP_CTRL);
2113         val |= UHSIC_RESET;
2114         writel(val, base + USB_SUSP_CTRL);
2115         udelay(30);
2116
2117         val = readl(base + USB_SUSP_CTRL);
2118         val |= UHSIC_PHY_ENABLE;
2119         writel(val, base + USB_SUSP_CTRL);
2120
2121         val = readl(base + UHSIC_HSRX_CFG0);
2122         val |= UHSIC_IDLE_WAIT(config->idle_wait_delay);
2123         val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(config->elastic_underrun_limit);
2124         val |= UHSIC_ELASTIC_OVERRUN_LIMIT(config->elastic_overrun_limit);
2125         writel(val, base + UHSIC_HSRX_CFG0);
2126
2127         val = readl(base + UHSIC_HSRX_CFG1);
2128         val |= UHSIC_HS_SYNC_START_DLY(config->sync_start_delay);
2129         writel(val, base + UHSIC_HSRX_CFG1);
2130
2131         /* WAR HSIC TX */
2132         val = readl(base + UHSIC_TX_CFG0);
2133         val &= ~UHSIC_HS_READY_WAIT_FOR_VALID;
2134         writel(val, base + UHSIC_TX_CFG0);
2135
2136         val = readl(base + UHSIC_MISC_CFG0);
2137         val |= UHSIC_SUSPEND_EXIT_ON_EDGE;
2138         /* Disable generic bus reset, to allow AP30 specific bus reset*/
2139         val |= UHSIC_DISABLE_BUSRESET;
2140         writel(val, base + UHSIC_MISC_CFG0);
2141
2142         val = readl(base + UHSIC_MISC_CFG1);
2143         val |= UHSIC_PLLU_STABLE_COUNT(phy->freq->stable_count);
2144         writel(val, base + UHSIC_MISC_CFG1);
2145
2146         val = readl(base + UHSIC_PLL_CFG1);
2147         val |= UHSIC_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
2148         val |= UHSIC_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count);
2149         writel(val, base + UHSIC_PLL_CFG1);
2150
2151         val = readl(base + USB_SUSP_CTRL);
2152         val &= ~(UHSIC_RESET);
2153         writel(val, base + USB_SUSP_CTRL);
2154         udelay(2);
2155
2156         val = readl(base + USB_USBMODE);
2157         val |= USB_USBMODE_HOST;
2158         writel(val, base + USB_USBMODE);
2159
2160         /* Change the USB controller PHY type to HSIC */
2161         val = readl(base + HOSTPC1_DEVLC);
2162         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
2163         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2164         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
2165         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2166         val &= ~HOSTPC1_DEVLC_STS;
2167         writel(val, base + HOSTPC1_DEVLC);
2168
2169         val = readl(base + USB_TXFILLTUNING);
2170         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
2171                 val = USB_FIFO_TXFILL_THRES(0x10);
2172                 writel(val, base + USB_TXFILLTUNING);
2173         }
2174
2175         val = readl(base + USB_PORTSC);
2176         val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN);
2177         writel(val, base + USB_PORTSC);
2178
2179         val = readl(base + UHSIC_PADS_CFG0);
2180         val &= ~(UHSIC_TX_RTUNEN);
2181         /* set Rtune impedance to 50 ohm */
2182         val |= UHSIC_TX_RTUNE(8);
2183         writel(val, base + UHSIC_PADS_CFG0);
2184
2185         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
2186                                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500)) {
2187                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2188                 return -ETIMEDOUT;
2189         }
2190
2191         phy->phy_clk_on = true;
2192         phy->hw_accessible = true;
2193
2194         return 0;
2195 }
2196
2197 static int uhsic_phy_power_off(struct tegra_usb_phy *phy)
2198 {
2199         unsigned long val;
2200         void __iomem *base = phy->regs;
2201
2202         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2203         if (!phy->phy_clk_on) {
2204                 DBG("%s(%d) inst:[%d] phy clk is already off\n",
2205                                         __func__, __LINE__, phy->inst);
2206                 return 0;
2207         }
2208
2209         phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
2210                         HOSTPC1_DEVLC_PSPD_MASK;
2211
2212         /* Disable interrupts */
2213         writel(0, base + USB_USBINTR);
2214
2215         uhsic_setup_pmc_wake_detect(phy);
2216
2217         val = readl(base + HOSTPC1_DEVLC);
2218         val |= HOSTPC1_DEVLC_PHCD;
2219         writel(val, base + HOSTPC1_DEVLC);
2220
2221         phy->phy_clk_on = false;
2222         phy->hw_accessible = false;
2223
2224         return 0;
2225 }
2226
2227 static int uhsic_phy_bus_port_power(struct tegra_usb_phy *phy)
2228 {
2229         unsigned long val;
2230         void __iomem *base = phy->regs;
2231
2232         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2233
2234         val = readl(base + USB_USBMODE);
2235         val |= USB_USBMODE_HOST;
2236         writel(val, base + USB_USBMODE);
2237
2238         /* Change the USB controller PHY type to HSIC */
2239         val = readl(base + HOSTPC1_DEVLC);
2240         val &= ~(HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK));
2241         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2242         val &= ~(HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK));
2243         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2244         writel(val, base + HOSTPC1_DEVLC);
2245
2246         val = readl(base + UHSIC_MISC_CFG0);
2247         val |= UHSIC_DETECT_SHORT_CONNECT;
2248         writel(val, base + UHSIC_MISC_CFG0);
2249         udelay(1);
2250
2251         val = readl(base + UHSIC_MISC_CFG0);
2252         val |= UHSIC_FORCE_XCVR_MODE;
2253         writel(val, base + UHSIC_MISC_CFG0);
2254
2255         val = readl(base + UHSIC_PADS_CFG1);
2256         val &= ~UHSIC_RPD_STROBE;
2257         writel(val, base + UHSIC_PADS_CFG1);
2258
2259         if (phy->pdata->ops && phy->pdata->ops->port_power)
2260                 phy->pdata->ops->port_power();
2261
2262         if (usb_phy_reg_status_wait(base + UHSIC_STAT_CFG0,
2263                         UHSIC_CONNECT_DETECT, UHSIC_CONNECT_DETECT, 25000)) {
2264                 pr_err("%s: timeout waiting for UHSIC_CONNECT_DETECT\n",
2265                                                                 __func__);
2266                 return -ETIMEDOUT;
2267         }
2268
2269         return 0;
2270 }
2271
2272 static int uhsic_phy_bus_reset(struct tegra_usb_phy *phy)
2273 {
2274         unsigned long val;
2275         void __iomem *base = phy->regs;
2276
2277         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2278
2279         /* Change the USB controller PHY type to HSIC */
2280         val = readl(base + HOSTPC1_DEVLC);
2281         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
2282         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2283         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
2284         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2285         val &= ~HOSTPC1_DEVLC_STS;
2286         writel(val, base + HOSTPC1_DEVLC);
2287         /* wait here, otherwise HOSTPC1_DEVLC_PSPD will timeout */
2288         mdelay(5);
2289
2290         val = readl(base + USB_PORTSC);
2291         val |= USB_PORTSC_PTC(5);
2292         writel(val, base + USB_PORTSC);
2293         udelay(2);
2294
2295         val = readl(base + USB_PORTSC);
2296         val &= ~(USB_PORTSC_PTC(~0));
2297         writel(val, base + USB_PORTSC);
2298         udelay(2);
2299
2300         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_LS(0),
2301                                                  0, 2000)) {
2302                 pr_err("%s: timeout waiting for USB_PORTSC_LS\n", __func__);
2303                 return -ETIMEDOUT;
2304         }
2305
2306         /* Poll until CCS is enabled */
2307         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
2308                                                  USB_PORTSC_CCS, 2000)) {
2309                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
2310                 return -ETIMEDOUT;
2311         }
2312
2313         if (usb_phy_reg_status_wait(base + HOSTPC1_DEVLC,
2314                         HOSTPC1_DEVLC_PSPD(2),
2315                         HOSTPC1_DEVLC_PSPD(2), 2000) < 0) {
2316                 pr_err("%s: timeout waiting hsic high speed configuration\n",
2317                                                 __func__);
2318                         return -ETIMEDOUT;
2319         }
2320
2321         val = readl(base + USB_USBCMD);
2322         val &= ~USB_USBCMD_RS;
2323         writel(val, base + USB_USBCMD);
2324
2325         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
2326                                                  USB_USBSTS_HCH, 2000)) {
2327                 pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
2328                 return -ETIMEDOUT;
2329         }
2330
2331         val = readl(base + UHSIC_PADS_CFG1);
2332         val &= ~UHSIC_RPU_STROBE;
2333         val |= UHSIC_RPD_STROBE;
2334         writel(val, base + UHSIC_PADS_CFG1);
2335
2336         mdelay(50);
2337
2338         val = readl(base + UHSIC_PADS_CFG1);
2339         val &= ~UHSIC_RPD_STROBE;
2340         val |= UHSIC_RPU_STROBE;
2341         writel(val, base + UHSIC_PADS_CFG1);
2342
2343         val = readl(base + USB_USBCMD);
2344         val |= USB_USBCMD_RS;
2345         writel(val, base + USB_USBCMD);
2346
2347         val = readl(base + UHSIC_PADS_CFG1);
2348         val &= ~UHSIC_RPU_STROBE;
2349         writel(val, base + UHSIC_PADS_CFG1);
2350
2351         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2352                                                  USB_USBCMD_RS, 2000)) {
2353                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2354                 return -ETIMEDOUT;
2355         }
2356
2357         return 0;
2358 }
2359
2360 int uhsic_phy_resume(struct tegra_usb_phy *phy)
2361 {
2362         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2363
2364         uhsic_phy_restore_start(phy);
2365         usb_phy_bringup_host_controller(phy);
2366         uhsic_phy_restore_end(phy);
2367
2368         return 0;
2369 }
2370
2371 static void ulpi_set_trimmer(struct tegra_usb_phy *phy)
2372 {
2373         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2374         void __iomem *base = phy->regs;
2375         unsigned long val;
2376
2377         val = ULPI_DATA_TRIMMER_SEL(config->data_trimmer);
2378         val |= ULPI_STPDIRNXT_TRIMMER_SEL(config->stpdirnxt_trimmer);
2379         val |= ULPI_DIR_TRIMMER_SEL(config->dir_trimmer);
2380         writel(val, base + ULPI_TIMING_CTRL_1);
2381         udelay(10);
2382
2383         val |= ULPI_DATA_TRIMMER_LOAD;
2384         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
2385         val |= ULPI_DIR_TRIMMER_LOAD;
2386         writel(val, base + ULPI_TIMING_CTRL_1);
2387 }
2388
2389 static void reset_utmip_uhsic(void __iomem *base)
2390 {
2391         unsigned long val;
2392
2393         val = readl(base + USB_SUSP_CTRL);
2394         val |= UHSIC_RESET;
2395         writel(val, base + USB_SUSP_CTRL);
2396
2397         val = readl(base + USB_SUSP_CTRL);
2398         val |= UTMIP_RESET;
2399         writel(val, base + USB_SUSP_CTRL);
2400 }
2401
2402 static void ulpi_set_host(void __iomem *base)
2403 {
2404         unsigned long val;
2405
2406         val = readl(base + USB_USBMODE);
2407         val |= USB_USBMODE_HOST;
2408         writel(val, base + USB_USBMODE);
2409
2410         val = readl(base + HOSTPC1_DEVLC);
2411         val |= HOSTPC1_DEVLC_PTS(2);
2412         writel(val, base + HOSTPC1_DEVLC);
2413 }
2414
2415
2416 static int ulpi_null_phy_power_off(struct tegra_usb_phy *phy)
2417 {
2418         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2419
2420         if (!phy->phy_clk_on) {
2421                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
2422                                                         __LINE__, phy->inst);
2423                 return 0;
2424         }
2425
2426         phy->phy_clk_on = false;
2427         phy->hw_accessible = false;
2428
2429         return 0;
2430 }
2431
2432 static int ulpi_null_phy_init(struct tegra_usb_phy *phy)
2433 {
2434         unsigned long val;
2435         void __iomem *base = phy->regs;
2436
2437         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2438         val = readl(base + ULPIS2S_CTRL);
2439         val |=  ULPIS2S_SLV0_CLAMP_XMIT;
2440         writel(val, base + ULPIS2S_CTRL);
2441
2442         val = readl(base + USB_SUSP_CTRL);
2443         val |= ULPIS2S_SLV0_RESET;
2444         writel(val, base + USB_SUSP_CTRL);
2445         udelay(10);
2446
2447         return 0;
2448 }
2449
2450 static int ulpi_null_phy_irq(struct tegra_usb_phy *phy)
2451 {
2452         usb_phy_fence_read(phy);
2453         return IRQ_HANDLED;
2454 }
2455
2456 static int ulpi_null_phy_cmd_reset(struct tegra_usb_phy *phy)
2457 {
2458         unsigned long val;
2459         void __iomem *base = phy->regs;
2460
2461         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2462         ulpi_set_host(base);
2463
2464         /* remove slave0 reset */
2465         val = readl(base + USB_SUSP_CTRL);
2466         val &= ~ULPIS2S_SLV0_RESET;
2467         writel(val, base + USB_SUSP_CTRL);
2468
2469         val = readl(base + ULPIS2S_CTRL);
2470         val &=  ~ULPIS2S_SLV0_CLAMP_XMIT;
2471         writel(val, base + ULPIS2S_CTRL);
2472         udelay(10);
2473
2474         return 0;
2475 }
2476
2477 static int ulpi_null_phy_lp0_resume(struct tegra_usb_phy *phy)
2478 {
2479         unsigned long val;
2480         void __iomem *base = phy->regs;
2481
2482         ulpi_null_phy_init(phy);
2483
2484         val = readl(base + USB_USBCMD);
2485         val |= USB_CMD_RESET;
2486         writel(val, base + USB_USBCMD);
2487
2488         if (usb_phy_reg_status_wait(base + USB_USBCMD,
2489                 USB_CMD_RESET, 0, 2500) < 0) {
2490                 pr_err("%s: timeout waiting for reset\n", __func__);
2491         }
2492
2493         val = readl(base + USB_USBMODE);
2494         val &= ~USB_USBMODE_MASK;
2495         val |= USB_USBMODE_HOST;
2496         writel(val, base + USB_USBMODE);
2497
2498         ulpi_null_phy_cmd_reset(phy);
2499
2500         val = readl(base + USB_USBCMD);
2501         val |= USB_USBCMD_RS;
2502         writel(val, base + USB_USBCMD);
2503         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2504                                                  USB_USBCMD_RS, 2000)) {
2505                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2506                 return -ETIMEDOUT;
2507         }
2508
2509         /* Enable Port Power */
2510         val = readl(base + USB_PORTSC);
2511         val |= USB_PORTSC_PP;
2512         writel(val, base + USB_PORTSC);
2513         udelay(10);
2514
2515         /* disable ULPI pinmux bypass */
2516         val = readl(base + ULPI_TIMING_CTRL_0);
2517         val &= ~ULPI_OUTPUT_PINMUX_BYP;
2518         writel(val, base + ULPI_TIMING_CTRL_0);
2519
2520         return 0;
2521 }
2522
2523 static int ulpi_null_phy_power_on(struct tegra_usb_phy *phy)
2524 {
2525         unsigned long val;
2526         void __iomem *base = phy->regs;
2527         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2528         static bool cold_boot = true;
2529
2530         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2531         if (phy->phy_clk_on) {
2532                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
2533                                                         __LINE__, phy->inst);
2534                 return 0;
2535         }
2536         reset_utmip_uhsic(base);
2537
2538         /* remove ULPI PADS CLKEN reset */
2539         val = readl(base + USB_SUSP_CTRL);
2540         val &= ~ULPI_PADS_CLKEN_RESET;
2541         writel(val, base + USB_SUSP_CTRL);
2542         udelay(10);
2543
2544         val = readl(base + ULPI_TIMING_CTRL_0);
2545         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
2546         writel(val, base + ULPI_TIMING_CTRL_0);
2547
2548         val = readl(base + USB_SUSP_CTRL);
2549         val |= ULPI_PHY_ENABLE;
2550         writel(val, base + USB_SUSP_CTRL);
2551         udelay(10);
2552
2553         /* set timming parameters */
2554         val = readl(base + ULPI_TIMING_CTRL_0);
2555         val |= ULPI_SHADOW_CLK_LOOPBACK_EN;
2556         val &= ~ULPI_SHADOW_CLK_SEL;
2557         val &= ~ULPI_LBK_PAD_EN;
2558         val |= ULPI_SHADOW_CLK_DELAY(config->shadow_clk_delay);
2559         val |= ULPI_CLOCK_OUT_DELAY(config->clock_out_delay);
2560         val |= ULPI_LBK_PAD_E_INPUT_OR;
2561         writel(val, base + ULPI_TIMING_CTRL_0);
2562
2563         writel(0, base + ULPI_TIMING_CTRL_1);
2564         udelay(10);
2565
2566         /* start internal 60MHz clock */
2567         val = readl(base + ULPIS2S_CTRL);
2568         val |= ULPIS2S_ENA;
2569         val |= ULPIS2S_SUPPORT_DISCONNECT;
2570         val |= ULPIS2S_SPARE((phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) ? 3 : 1);
2571         val |= ULPIS2S_PLLU_MASTER_BLASTER60;
2572         writel(val, base + ULPIS2S_CTRL);
2573
2574         /* select ULPI_CORE_CLK_SEL to SHADOW_CLK */
2575         val = readl(base + ULPI_TIMING_CTRL_0);
2576         val |= ULPI_CORE_CLK_SEL;
2577         writel(val, base + ULPI_TIMING_CTRL_0);
2578         udelay(10);
2579
2580         /* enable ULPI null phy clock - can't set the trimmers before this */
2581         val = readl(base + ULPI_TIMING_CTRL_0);
2582         val |= ULPI_CLK_OUT_ENA;
2583         writel(val, base + ULPI_TIMING_CTRL_0);
2584         udelay(10);
2585
2586         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
2587                                                  USB_PHY_CLK_VALID, 2500)) {
2588                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2589                 return -ETIMEDOUT;
2590         }
2591
2592         /* set ULPI trimmers */
2593         ulpi_set_trimmer(phy);
2594
2595         ulpi_set_host(base);
2596
2597         /* remove slave0 reset */
2598         val = readl(base + USB_SUSP_CTRL);
2599         val &= ~ULPIS2S_SLV0_RESET;
2600         writel(val, base + USB_SUSP_CTRL);
2601
2602         /* remove slave1 and line reset */
2603         val = readl(base + USB_SUSP_CTRL);
2604         val &= ~ULPIS2S_SLV1_RESET;
2605         val &= ~ULPIS2S_LINE_RESET;
2606
2607         /* remove ULPI PADS reset */
2608         val &= ~ULPI_PADS_RESET;
2609         writel(val, base + USB_SUSP_CTRL);
2610
2611         if (cold_boot) {
2612                 val = readl(base + ULPI_TIMING_CTRL_0);
2613                 val |= ULPI_CLK_PADOUT_ENA;
2614                 writel(val, base + ULPI_TIMING_CTRL_0);
2615                 cold_boot = false;
2616         } else {
2617                 if (!readl(base + USB_ASYNCLISTADDR))
2618                         ulpi_null_phy_lp0_resume(phy);
2619         }
2620         udelay(10);
2621
2622         phy->phy_clk_on = true;
2623         phy->hw_accessible = true;
2624
2625         return 0;
2626 }
2627
2628
2629 static int ulpi_null_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
2630 {
2631         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2632
2633         usb_phy_wait_for_sof(phy);
2634         return 0;
2635 }
2636
2637 static int ulpi_null_phy_resume(struct tegra_usb_phy *phy)
2638 {
2639         unsigned long val;
2640         void __iomem *base = phy->regs;
2641
2642         if (!readl(base + USB_ASYNCLISTADDR)) {
2643                 /* enable ULPI CLK output pad */
2644                 val = readl(base + ULPI_TIMING_CTRL_0);
2645                 val |= ULPI_CLK_PADOUT_ENA;
2646                 writel(val, base + ULPI_TIMING_CTRL_0);
2647
2648                 /* enable ULPI pinmux bypass */
2649                 val = readl(base + ULPI_TIMING_CTRL_0);
2650                 val |= ULPI_OUTPUT_PINMUX_BYP;
2651                 writel(val, base + ULPI_TIMING_CTRL_0);
2652                 udelay(5);
2653 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2654                 /* remove DIR tristate */
2655                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR, TEGRA_TRI_NORMAL);
2656 #endif
2657         }
2658         return 0;
2659 }
2660
2661
2662
2663 static struct tegra_usb_phy_ops utmi_phy_ops = {
2664         .open           = utmi_phy_open,
2665         .close          = utmi_phy_close,
2666         .irq            = utmi_phy_irq,
2667         .power_on       = utmi_phy_power_on,
2668         .power_off      = utmi_phy_power_off,
2669         .pre_resume = utmi_phy_pre_resume,
2670         .resume = utmi_phy_resume,
2671         .post_resume    = utmi_phy_post_resume,
2672         .charger_detect = utmi_phy_charger_detect,
2673         .post_suspend   = phy_post_suspend,
2674 };
2675
2676 static struct tegra_usb_phy_ops uhsic_phy_ops = {
2677         .open           = uhsic_phy_open,
2678         .irq            = uhsic_phy_irq,
2679         .power_on       = uhsic_phy_power_on,
2680         .power_off      = uhsic_phy_power_off,
2681         .pre_resume = uhsic_phy_pre_resume,
2682         .resume = uhsic_phy_resume,
2683         .post_resume = uhsic_phy_post_resume,
2684         .port_power = uhsic_phy_bus_port_power,
2685         .bus_reset      = uhsic_phy_bus_reset,
2686         .post_suspend   = phy_post_suspend,
2687 };
2688
2689 static struct tegra_usb_phy_ops ulpi_null_phy_ops = {
2690         .init           = ulpi_null_phy_init,
2691         .irq            = ulpi_null_phy_irq,
2692         .power_on       = ulpi_null_phy_power_on,
2693         .power_off      = ulpi_null_phy_power_off,
2694         .pre_resume = ulpi_null_phy_pre_resume,
2695         .resume = ulpi_null_phy_resume,
2696         .reset          = ulpi_null_phy_cmd_reset,
2697         .post_suspend   = phy_post_suspend,
2698 };
2699
2700 static struct tegra_usb_phy_ops ulpi_link_phy_ops;
2701 static struct tegra_usb_phy_ops icusb_phy_ops;
2702
2703 static struct tegra_usb_phy_ops *phy_ops[] = {
2704         [TEGRA_USB_PHY_INTF_UTMI] = &utmi_phy_ops,
2705         [TEGRA_USB_PHY_INTF_ULPI_LINK] = &ulpi_link_phy_ops,
2706         [TEGRA_USB_PHY_INTF_ULPI_NULL] = &ulpi_null_phy_ops,
2707         [TEGRA_USB_PHY_INTF_HSIC] = &uhsic_phy_ops,
2708         [TEGRA_USB_PHY_INTF_ICUSB] = &icusb_phy_ops,
2709 };
2710
2711 int tegra3_usb_phy_init_ops(struct tegra_usb_phy *phy)
2712 {
2713         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2714
2715         phy->ops = phy_ops[phy->pdata->phy_intf];
2716
2717         /* FIXME: uncommenting below line to make USB host mode fail*/
2718         /* usb_phy_power_down_pmc(); */
2719
2720         return 0;
2721 }