arm: tegra3: usb_phy: HSIC rail consumes 4mA in suspend
[linux-2.6.git] / arch / arm / mach-tegra / tegra3_usb_phy.c
1 /*
2  * arch/arm/mach-tegra/tegra3_usb_phy.c
3  *
4  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
5  *
6  *
7  * This software is licensed under the terms of the GNU General Public
8  * License version 2, as published by the Free Software Foundation, and
9  * may be copied, distributed, and modified under those terms.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17 #include <linux/resource.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/slab.h>
21 #include <linux/err.h>
22 #include <linux/platform_device.h>
23 #include <linux/io.h>
24 #include <linux/gpio.h>
25 #include <linux/interrupt.h>
26 #include <linux/clk.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <mach/clk.h>
30 #include <mach/iomap.h>
31 #include <mach/pinmux.h>
32 #include "tegra_usb_phy.h"
33 #include "gpio-names.h"
34 #include "fuse.h"
35
36 #define USB_USBCMD              0x130
37 #define   USB_USBCMD_RS         (1 << 0)
38 #define   USB_CMD_RESET (1<<1)
39
40 #define USB_USBSTS              0x134
41 #define   USB_USBSTS_PCI        (1 << 2)
42 #define   USB_USBSTS_SRI        (1 << 7)
43 #define   USB_USBSTS_HCH        (1 << 12)
44
45 #define USB_USBINTR             0x138
46
47 #define USB_TXFILLTUNING        0x154
48 #define USB_FIFO_TXFILL_THRES(x)   (((x) & 0x1f) << 16)
49 #define USB_FIFO_TXFILL_MASK    0x1f0000
50
51 #define USB_ASYNCLISTADDR       0x148
52
53 #define ICUSB_CTRL              0x15c
54
55 #define USB_PORTSC              0x174
56 #define   USB_PORTSC_WKOC       (1 << 22)
57 #define   USB_PORTSC_WKDS       (1 << 21)
58 #define   USB_PORTSC_WKCN       (1 << 20)
59 #define   USB_PORTSC_PTC(x)     (((x) & 0xf) << 16)
60 #define   USB_PORTSC_PP (1 << 12)
61 #define   USB_PORTSC_LS(x) (((x) & 0x3) << 10)
62 #define   USB_PORTSC_SUSP       (1 << 7)
63 #define   USB_PORTSC_RESUME     (1 << 6)
64 #define   USB_PORTSC_OCC        (1 << 5)
65 #define   USB_PORTSC_PEC        (1 << 3)
66 #define   USB_PORTSC_PE         (1 << 2)
67 #define   USB_PORTSC_CSC        (1 << 1)
68 #define   USB_PORTSC_CCS        (1 << 0)
69 #define   USB_PORTSC_RWC_BITS (USB_PORTSC_CSC | USB_PORTSC_PEC | USB_PORTSC_OCC)
70
71 #define HOSTPC1_DEVLC           0x1b4
72 #define   HOSTPC1_DEVLC_PHCD            (1 << 22)
73 #define   HOSTPC1_DEVLC_PTS(x)          (((x) & 0x7) << 29)
74 #define   HOSTPC1_DEVLC_PTS_MASK        7
75 #define   HOSTPC1_DEVLC_PTS_HSIC        4
76 #define   HOSTPC1_DEVLC_STS             (1 << 28)
77 #define   HOSTPC1_DEVLC_PSPD(x)         (((x) & 0x3) << 25)
78 #define   HOSTPC1_DEVLC_PSPD_MASK       3
79 #define   HOSTPC1_DEVLC_PSPD_HIGH_SPEED 2
80
81 #define USB_USBMODE             0x1f8
82 #define   USB_USBMODE_MASK              (3 << 0)
83 #define   USB_USBMODE_HOST              (3 << 0)
84 #define   USB_USBMODE_DEVICE            (2 << 0)
85
86 #define USB_SUSP_CTRL           0x400
87 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
88 #define   USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
89 #define   USB_SUSP_CLR                  (1 << 5)
90 #define   USB_PHY_CLK_VALID             (1 << 7)
91 #define   USB_PHY_CLK_VALID_INT_ENB     (1 << 9)
92 #define   USB_PHY_CLK_VALID_INT_STS     (1 << 8)
93 #define   UTMIP_RESET                   (1 << 11)
94 #define   UTMIP_PHY_ENABLE              (1 << 12)
95 #define   ULPI_PHY_ENABLE               (1 << 13)
96 #define   UHSIC_RESET                   (1 << 14)
97 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
98 #define   UHSIC_PHY_ENABLE              (1 << 19)
99 #define   ULPIS2S_SLV0_RESET            (1 << 20)
100 #define   ULPIS2S_SLV1_RESET            (1 << 21)
101 #define   ULPIS2S_LINE_RESET            (1 << 22)
102 #define   ULPI_PADS_RESET               (1 << 23)
103 #define   ULPI_PADS_CLKEN_RESET         (1 << 24)
104
105 #define USB_PHY_VBUS_WAKEUP_ID  0x408
106 #define   VDAT_DET_INT_EN       (1 << 16)
107 #define   VDAT_DET_CHG_DET      (1 << 17)
108 #define   VDAT_DET_STS          (1 << 18)
109 #define   USB_ID_STATUS         (1 << 2)
110
111 #define ULPIS2S_CTRL            0x418
112 #define   ULPIS2S_ENA                   (1 << 0)
113 #define   ULPIS2S_SUPPORT_DISCONNECT    (1 << 2)
114 #define   ULPIS2S_PLLU_MASTER_BLASTER60 (1 << 3)
115 #define   ULPIS2S_SPARE(x)              (((x) & 0xF) << 8)
116 #define   ULPIS2S_FORCE_ULPI_CLK_OUT    (1 << 12)
117 #define   ULPIS2S_DISCON_DONT_CHECK_SE0 (1 << 13)
118 #define   ULPIS2S_SUPPORT_HS_KEEP_ALIVE (1 << 14)
119 #define   ULPIS2S_DISABLE_STP_PU        (1 << 15)
120 #define   ULPIS2S_SLV0_CLAMP_XMIT       (1 << 16)
121
122 #define ULPI_TIMING_CTRL_0      0x424
123 #define   ULPI_CLOCK_OUT_DELAY(x)       ((x) & 0x1F)
124 #define   ULPI_OUTPUT_PINMUX_BYP        (1 << 10)
125 #define   ULPI_CLKOUT_PINMUX_BYP        (1 << 11)
126 #define   ULPI_SHADOW_CLK_LOOPBACK_EN   (1 << 12)
127 #define   ULPI_SHADOW_CLK_SEL           (1 << 13)
128 #define   ULPI_CORE_CLK_SEL             (1 << 14)
129 #define   ULPI_SHADOW_CLK_DELAY(x)      (((x) & 0x1F) << 16)
130 #define   ULPI_LBK_PAD_EN               (1 << 26)
131 #define   ULPI_LBK_PAD_E_INPUT_OR       (1 << 27)
132 #define   ULPI_CLK_OUT_ENA              (1 << 28)
133 #define   ULPI_CLK_PADOUT_ENA           (1 << 29)
134
135 #define ULPI_TIMING_CTRL_1      0x428
136 #define   ULPI_DATA_TRIMMER_LOAD        (1 << 0)
137 #define   ULPI_DATA_TRIMMER_SEL(x)      (((x) & 0x7) << 1)
138 #define   ULPI_STPDIRNXT_TRIMMER_LOAD   (1 << 16)
139 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
140 #define   ULPI_DIR_TRIMMER_LOAD         (1 << 24)
141 #define   ULPI_DIR_TRIMMER_SEL(x)       (((x) & 0x7) << 25)
142
143 #define UTMIP_XCVR_CFG0         0x808
144 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
145 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
146 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
147 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
148 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
149 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
150 #define   UTMIP_XCVR_LSBIAS_SEL                 (1 << 21)
151 #define   UTMIP_XCVR_SETUP_MSB(x)               (((x) & 0x7) << 22)
152 #define   UTMIP_XCVR_HSSLEW_MSB(x)              (((x) & 0x7f) << 25)
153 #define   UTMIP_XCVR_MAX_OFFSET         2
154 #define   UTMIP_XCVR_SETUP_MAX_VALUE    0x7f
155 #define   UTMIP_XCVR_SETUP_MIN_VALUE    0
156 #define   XCVR_SETUP_MSB_CALIB(x) ((x) >> 4)
157
158 #define UTMIP_BIAS_CFG0         0x80c
159 #define   UTMIP_OTGPD                   (1 << 11)
160 #define   UTMIP_BIASPD                  (1 << 10)
161 #define   UTMIP_HSSQUELCH_LEVEL(x)      (((x) & 0x3) << 0)
162 #define   UTMIP_HSDISCON_LEVEL(x)       (((x) & 0x3) << 2)
163 #define   UTMIP_HSDISCON_LEVEL_MSB      (1 << 24)
164
165 #define UTMIP_HSRX_CFG0         0x810
166 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
167 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
168
169 #define UTMIP_HSRX_CFG1         0x814
170 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
171
172 #define UTMIP_TX_CFG0           0x820
173 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
174 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
175
176 #define UTMIP_DEBOUNCE_CFG0 0x82c
177 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
178
179 #define UTMIP_BAT_CHRG_CFG0 0x830
180 #define   UTMIP_PD_CHRG                 (1 << 0)
181 #define   UTMIP_ON_SINK_EN              (1 << 2)
182 #define   UTMIP_OP_SRC_EN               (1 << 3)
183
184 #define UTMIP_XCVR_CFG1         0x838
185 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
186 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
187 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
188 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
189
190 #define UTMIP_BIAS_CFG1         0x83c
191 #define   UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
192 #define   UTMIP_BIAS_PDTRK_POWERDOWN    (1 << 0)
193 #define   UTMIP_BIAS_PDTRK_POWERUP      (1 << 1)
194
195 #define UTMIP_MISC_CFG0         0x824
196 #define   UTMIP_DPDM_OBSERVE            (1 << 26)
197 #define   UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
198 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J   UTMIP_DPDM_OBSERVE_SEL(0xf)
199 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K   UTMIP_DPDM_OBSERVE_SEL(0xe)
200 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
201 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
202 #define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
203 #define   FORCE_PULLDN_DM       (1 << 8)
204 #define   FORCE_PULLDN_DP       (1 << 9)
205 #define   COMB_TERMS            (1 << 0)
206 #define   ALWAYS_FREE_RUNNING_TERMS (1 << 1)
207
208 #define UTMIP_SPARE_CFG0        0x834
209 #define   FUSE_SETUP_SEL                (1 << 3)
210 #define   FUSE_ATERM_SEL                (1 << 4)
211
212 #define UTMIP_PMC_WAKEUP0               0x84c
213 #define   EVENT_INT_ENB                 (1 << 0)
214
215 #define UHSIC_PMC_WAKEUP0               0xc34
216
217 #define UTMIP_BIAS_STS0                 0x840
218 #define   UTMIP_RCTRL_VAL(x)            (((x) & 0xffff) << 0)
219 #define   UTMIP_TCTRL_VAL(x)            (((x) & (0xffff << 16)) >> 16)
220
221 #define UHSIC_PLL_CFG1                          0xc04
222 #define   UHSIC_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
223 #define   UHSIC_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 14)
224
225 #define UHSIC_HSRX_CFG0                         0xc08
226 #define   UHSIC_ELASTIC_UNDERRUN_LIMIT(x)       (((x) & 0x1f) << 2)
227 #define   UHSIC_ELASTIC_OVERRUN_LIMIT(x)        (((x) & 0x1f) << 8)
228 #define   UHSIC_IDLE_WAIT(x)                    (((x) & 0x1f) << 13)
229
230 #define UHSIC_HSRX_CFG1                         0xc0c
231 #define   UHSIC_HS_SYNC_START_DLY(x)            (((x) & 0x1f) << 1)
232
233 #define UHSIC_TX_CFG0                           0xc10
234 #define UHSIC_HS_READY_WAIT_FOR_VALID   (1 << 9)
235 #define UHSIC_MISC_CFG0                         0xc14
236 #define   UHSIC_SUSPEND_EXIT_ON_EDGE            (1 << 7)
237 #define   UHSIC_DETECT_SHORT_CONNECT            (1 << 8)
238 #define   UHSIC_FORCE_XCVR_MODE                 (1 << 15)
239 #define   UHSIC_DISABLE_BUSRESET                (1 << 20)
240 #define UHSIC_MISC_CFG1                         0xc18
241 #define   UHSIC_PLLU_STABLE_COUNT(x)            (((x) & 0xfff) << 2)
242
243 #define UHSIC_PADS_CFG0                         0xc1c
244 #define   UHSIC_TX_RTUNEN                       0xf000
245 #define   UHSIC_TX_RTUNE(x)                     (((x) & 0xf) << 12)
246
247 #define UHSIC_PADS_CFG1                         0xc20
248 #define   UHSIC_PD_BG                           (1 << 2)
249 #define   UHSIC_PD_TX                           (1 << 3)
250 #define   UHSIC_PD_TRK                          (1 << 4)
251 #define   UHSIC_PD_RX                           (1 << 5)
252 #define   UHSIC_PD_ZI                           (1 << 6)
253 #define   UHSIC_RX_SEL                          (1 << 7)
254 #define   UHSIC_RPD_DATA                        (1 << 9)
255 #define   UHSIC_RPD_STROBE                      (1 << 10)
256 #define   UHSIC_RPU_DATA                        (1 << 11)
257 #define   UHSIC_RPU_STROBE                      (1 << 12)
258
259 #define UHSIC_CMD_CFG0                  0xc24
260 #define UHSIC_PRETEND_CONNECT_DETECT    (1 << 5)
261
262 #define UHSIC_STAT_CFG0         0xc28
263 #define UHSIC_CONNECT_DETECT            (1 << 0)
264
265 #define PMC_USB_DEBOUNCE                        0xec
266 #define UTMIP_LINE_DEB_CNT(x)           (((x) & 0xf) << 16)
267 #define UHSIC_LINE_DEB_CNT(x)           (((x) & 0xf) << 20)
268
269 #define PMC_USB_AO                              0xf0
270
271 #define PMC_POWER_DOWN_MASK                     0xffff
272 #define HSIC_RESERVED_P0                        (3 << 14)
273 #define STROBE_VAL_PD_P0                        (1 << 12)
274 #define DATA_VAL_PD_P0                          (1 << 13)
275
276 #define USB_ID_PD(inst)                 (1 << ((4*(inst))+3))
277 #define VBUS_WAKEUP_PD(inst)                    (1 << ((4*(inst))+2))
278 #define   USBON_VAL_PD(inst)                    (1 << ((4*(inst))+1))
279 #define   USBON_VAL_PD_P2                       (1 << 9)
280 #define   USBON_VAL_PD_P1                       (1 << 5)
281 #define   USBON_VAL_PD_P0                       (1 << 1)
282 #define   USBOP_VAL_PD(inst)                    (1 << (4*(inst)))
283 #define   USBOP_VAL_PD_P2                       (1 << 8)
284 #define   USBOP_VAL_PD_P1                       (1 << 4)
285 #define   USBOP_VAL_PD_P0                       (1 << 0)
286 #define   PMC_USB_AO_PD_P2                      (0xf << 8)
287 #define   PMC_USB_AO_ID_PD_P0                   (1 << 3)
288 #define   PMC_USB_AO_VBUS_WAKEUP_PD_P0  (1 << 2)
289
290 #define PMC_TRIGGERS                    0x1ec
291
292 #define   UHSIC_CLR_WALK_PTR_P0         (1 << 3)
293 #define   UTMIP_CLR_WALK_PTR(inst)      (1 << (inst))
294 #define   UTMIP_CLR_WALK_PTR_P2         (1 << 2)
295 #define   UTMIP_CLR_WALK_PTR_P1         (1 << 1)
296 #define   UTMIP_CLR_WALK_PTR_P0         (1 << 0)
297 #define   UTMIP_CAP_CFG(inst)   (1 << ((inst)+4))
298 #define   UTMIP_CAP_CFG_P2              (1 << 6)
299 #define   UTMIP_CAP_CFG_P1              (1 << 5)
300 #define   UTMIP_CAP_CFG_P0              (1 << 4)
301 #define   UTMIP_CLR_WAKE_ALARM(inst)    (1 << ((inst)+12))
302 #define   UHSIC_CLR_WAKE_ALARM_P0       (1 << 15)
303 #define   UTMIP_CLR_WAKE_ALARM_P2       (1 << 14)
304
305 #define PMC_PAD_CFG             (0x1f4)
306
307 #define PMC_UTMIP_TERM_PAD_CFG  0x1f8
308 #define   PMC_TCTRL_VAL(x)      (((x) & 0x1f) << 5)
309 #define   PMC_RCTRL_VAL(x)      (((x) & 0x1f) << 0)
310
311 #define PMC_SLEEP_CFG                   0x1fc
312
313 #define   UHSIC_MASTER_ENABLE                   (1 << 24)
314 #define   UHSIC_WAKE_VAL(x)             (((x) & 0xf) << 28)
315 #define   WAKE_VAL_SD10                 0x2
316 #define   UTMIP_TCTRL_USE_PMC(inst) (1 << ((8*(inst))+3))
317 #define   UTMIP_TCTRL_USE_PMC_P2                (1 << 19)
318 #define   UTMIP_TCTRL_USE_PMC_P1                (1 << 11)
319 #define   UTMIP_TCTRL_USE_PMC_P0                (1 << 3)
320 #define   UTMIP_RCTRL_USE_PMC(inst) (1 << ((8*(inst))+2))
321 #define   UTMIP_RCTRL_USE_PMC_P2                (1 << 18)
322 #define   UTMIP_RCTRL_USE_PMC_P1                (1 << 10)
323 #define   UTMIP_RCTRL_USE_PMC_P0                (1 << 2)
324 #define   UTMIP_FSLS_USE_PMC(inst)      (1 << ((8*(inst))+1))
325 #define   UTMIP_FSLS_USE_PMC_P2         (1 << 17)
326 #define   UTMIP_FSLS_USE_PMC_P1         (1 << 9)
327 #define   UTMIP_FSLS_USE_PMC_P0         (1 << 1)
328 #define   UTMIP_MASTER_ENABLE(inst) (1 << (8*(inst)))
329 #define   UTMIP_MASTER_ENABLE_P2                (1 << 16)
330 #define   UTMIP_MASTER_ENABLE_P1                (1 << 8)
331 #define   UTMIP_MASTER_ENABLE_P0                (1 << 0)
332 #define UHSIC_MASTER_ENABLE_P0          (1 << 24)
333 #define UHSIC_WAKE_VAL_P0(x)            (((x) & 0xf) << 28)
334
335 #define PMC_SLEEPWALK_CFG               0x200
336
337 #define   UHSIC_WAKE_WALK_EN_P0 (1 << 30)
338 #define   UHSIC_LINEVAL_WALK_EN (1 << 31)
339 #define   UTMIP_LINEVAL_WALK_EN(inst) (1 << ((8*(inst))+7))
340 #define   UTMIP_LINEVAL_WALK_EN_P2      (1 << 23)
341 #define   UTMIP_LINEVAL_WALK_EN_P1      (1 << 15)
342 #define   UTMIP_LINEVAL_WALK_EN_P0      (1 << 7)
343 #define   UTMIP_WAKE_VAL(inst, x) (((x) & 0xf) << ((8*(inst))+4))
344 #define   UTMIP_WAKE_VAL_P2(x)          (((x) & 0xf) << 20)
345 #define   UTMIP_WAKE_VAL_P1(x)          (((x) & 0xf) << 12)
346 #define   UTMIP_WAKE_VAL_P0(x)          (((x) & 0xf) << 4)
347 #define   WAKE_VAL_NONE         0xc
348 #define   WAKE_VAL_ANY                  0xF
349 #define   WAKE_VAL_FSJ                  0x2
350 #define   WAKE_VAL_FSK                  0x1
351 #define   WAKE_VAL_SE0                  0x0
352
353 #define PMC_SLEEPWALK_REG(inst)         (0x204 + (4*(inst)))
354 #define   UTMIP_USBOP_RPD_A     (1 << 0)
355 #define   UTMIP_USBON_RPD_A     (1 << 1)
356 #define   UTMIP_AP_A                    (1 << 4)
357 #define   UTMIP_AN_A                    (1 << 5)
358 #define   UTMIP_HIGHZ_A         (1 << 6)
359 #define   UTMIP_USBOP_RPD_B     (1 << 8)
360 #define   UTMIP_USBON_RPD_B     (1 << 9)
361 #define   UTMIP_AP_B                    (1 << 12)
362 #define   UTMIP_AN_B                    (1 << 13)
363 #define   UTMIP_HIGHZ_B         (1 << 14)
364 #define   UTMIP_USBOP_RPD_C     (1 << 16)
365 #define   UTMIP_USBON_RPD_C     (1 << 17)
366 #define   UTMIP_AP_C            (1 << 20)
367 #define   UTMIP_AN_C            (1 << 21)
368 #define   UTMIP_HIGHZ_C         (1 << 22)
369 #define   UTMIP_USBOP_RPD_D     (1 << 24)
370 #define   UTMIP_USBON_RPD_D     (1 << 25)
371 #define   UTMIP_AP_D            (1 << 28)
372 #define   UTMIP_AN_D            (1 << 29)
373 #define   UTMIP_HIGHZ_D         (1 << 30)
374
375 #define PMC_SLEEPWALK_UHSIC             0x210
376
377 #define UHSIC_STROBE_RPD_A              (1 << 0)
378 #define UHSIC_DATA_RPD_A                (1 << 1)
379 #define UHSIC_STROBE_RPU_A              (1 << 2)
380 #define UHSIC_DATA_RPU_A                (1 << 3)
381 #define UHSIC_STROBE_RPD_B              (1 << 8)
382 #define UHSIC_DATA_RPD_B                (1 << 9)
383 #define UHSIC_STROBE_RPU_B              (1 << 10)
384 #define UHSIC_DATA_RPU_B                (1 << 11)
385 #define UHSIC_STROBE_RPD_C              (1 << 16)
386 #define UHSIC_DATA_RPD_C                (1 << 17)
387 #define UHSIC_STROBE_RPU_C              (1 << 18)
388 #define UHSIC_DATA_RPU_C                (1 << 19)
389 #define UHSIC_STROBE_RPD_D              (1 << 24)
390 #define UHSIC_DATA_RPD_D                (1 << 25)
391 #define UHSIC_STROBE_RPU_D              (1 << 26)
392 #define UHSIC_DATA_RPU_D                (1 << 27)
393
394 #define UTMIP_UHSIC_STATUS              0x214
395
396 #define UTMIP_USBOP_VAL(inst)           (1 << ((2*(inst)) + 8))
397 #define UTMIP_USBOP_VAL_P2              (1 << 12)
398 #define UTMIP_USBOP_VAL_P1              (1 << 10)
399 #define UTMIP_USBOP_VAL_P0              (1 << 8)
400 #define UTMIP_USBON_VAL(inst)           (1 << ((2*(inst)) + 9))
401 #define UTMIP_USBON_VAL_P2              (1 << 13)
402 #define UTMIP_USBON_VAL_P1              (1 << 11)
403 #define UTMIP_USBON_VAL_P0              (1 << 9)
404 #define UHSIC_WAKE_ALARM                (1 << 19)
405 #define UTMIP_WAKE_ALARM(inst)          (1 << ((inst) + 16))
406 #define UTMIP_WAKE_ALARM_P2             (1 << 18)
407 #define UTMIP_WAKE_ALARM_P1             (1 << 17)
408 #define UTMIP_WAKE_ALARM_P0             (1 << 16)
409 #define UHSIC_DATA_VAL_P0               (1 << 15)
410 #define UHSIC_STROBE_VAL_P0             (1 << 14)
411 #define UTMIP_WALK_PTR_VAL(inst)        (0x3 << ((inst)*2))
412 #define UHSIC_WALK_PTR_VAL              (0x3 << 6)
413 #define UTMIP_WALK_PTR(inst)            (1 << ((inst)*2))
414 #define UTMIP_WALK_PTR_P2               (1 << 4)
415 #define UTMIP_WALK_PTR_P1               (1 << 2)
416 #define UTMIP_WALK_PTR_P0               (1 << 0)
417
418 #define USB1_PREFETCH_ID                           6
419 #define USB2_PREFETCH_ID                           18
420 #define USB3_PREFETCH_ID                           17
421
422 #define PMC_UTMIP_UHSIC_FAKE            0x218
423
424 #define UHSIC_STROBE_VAL                (1 << 12)
425 #define UHSIC_DATA_VAL                  (1 << 13)
426 #define UHSIC_STROBE_ENB                (1 << 14)
427 #define UHSIC_DATA_ENB                  (1 << 15)
428 #define   USBON_VAL(inst)       (1 << ((4*(inst))+1))
429 #define   USBON_VAL_P2                  (1 << 9)
430 #define   USBON_VAL_P1                  (1 << 5)
431 #define   USBON_VAL_P0                  (1 << 1)
432 #define   USBOP_VAL(inst)       (1 << (4*(inst)))
433 #define   USBOP_VAL_P2                  (1 << 8)
434 #define   USBOP_VAL_P1                  (1 << 4)
435 #define   USBOP_VAL_P0                  (1 << 0)
436
437 #define PMC_UTMIP_BIAS_MASTER_CNTRL 0x30c
438 #define   BIAS_MASTER_PROG_VAL          (1 << 1)
439
440 #define PMC_UTMIP_MASTER_CONFIG 0x310
441
442 #define UTMIP_PWR(inst)         (1 << (inst))
443 #define UHSIC_PWR                       (1 << 3)
444
445 #define FUSE_USB_CALIB_0                0x1F0
446 #define   XCVR_SETUP(x) (((x) & 0x7F) << 0)
447 #define   XCVR_SETUP_LSB_MASK   0xF
448 #define   XCVR_SETUP_MSB_MASK   0x70
449 #define   XCVR_SETUP_LSB_MAX_VAL        0xF
450
451 #define APB_MISC_GP_OBSCTRL_0   0x818
452 #define APB_MISC_GP_OBSDATA_0   0x81c
453
454 /* ULPI GPIO */
455 #define ULPI_STP        TEGRA_GPIO_PY3
456 #define ULPI_DIR        TEGRA_GPIO_PY1
457 #define ULPI_D0         TEGRA_GPIO_PO1
458 #define ULPI_D1         TEGRA_GPIO_PO2
459
460 /* These values (in milli second) are taken from the battery charging spec */
461 #define TDP_SRC_ON_MS    100
462 #define TDPSRC_CON_MS    40
463
464 #ifdef DEBUG
465 #define DBG(stuff...)   pr_info("tegra3_usb_phy: " stuff)
466 #else
467 #define DBG(stuff...)   do {} while (0)
468 #endif
469
470 #if 0
471 #define PHY_DBG(stuff...)       pr_info("tegra3_usb_phy: " stuff)
472 #else
473 #define PHY_DBG(stuff...)       do {} while (0)
474 #endif
475
476
477 static u32 utmip_rctrl_val, utmip_tctrl_val;
478 static DEFINE_SPINLOCK(utmip_pad_lock);
479 static int utmip_pad_count;
480
481 static struct tegra_xtal_freq utmip_freq_table[] = {
482         {
483                 .freq = 12000000,
484                 .enable_delay = 0x02,
485                 .stable_count = 0x2F,
486                 .active_delay = 0x04,
487                 .xtal_freq_count = 0x76,
488                 .debounce = 0x7530,
489                 .pdtrk_count = 5,
490         },
491         {
492                 .freq = 13000000,
493                 .enable_delay = 0x02,
494                 .stable_count = 0x33,
495                 .active_delay = 0x05,
496                 .xtal_freq_count = 0x7F,
497                 .debounce = 0x7EF4,
498                 .pdtrk_count = 5,
499         },
500         {
501                 .freq = 19200000,
502                 .enable_delay = 0x03,
503                 .stable_count = 0x4B,
504                 .active_delay = 0x06,
505                 .xtal_freq_count = 0xBB,
506                 .debounce = 0xBB80,
507                 .pdtrk_count = 7,
508         },
509         {
510                 .freq = 26000000,
511                 .enable_delay = 0x04,
512                 .stable_count = 0x66,
513                 .active_delay = 0x09,
514                 .xtal_freq_count = 0xFE,
515                 .debounce = 0xFDE8,
516                 .pdtrk_count = 9,
517         },
518 };
519
520 static struct tegra_xtal_freq uhsic_freq_table[] = {
521         {
522                 .freq = 12000000,
523                 .enable_delay = 0x02,
524                 .stable_count = 0x2F,
525                 .active_delay = 0x0,
526                 .xtal_freq_count = 0x1CA,
527         },
528         {
529                 .freq = 13000000,
530                 .enable_delay = 0x02,
531                 .stable_count = 0x33,
532                 .active_delay = 0x0,
533                 .xtal_freq_count = 0x1F0,
534         },
535         {
536                 .freq = 19200000,
537                 .enable_delay = 0x03,
538                 .stable_count = 0x4B,
539                 .active_delay = 0x0,
540                 .xtal_freq_count = 0x2DD,
541         },
542         {
543                 .freq = 26000000,
544                 .enable_delay = 0x04,
545                 .stable_count = 0x66,
546                 .active_delay = 0x0,
547                 .xtal_freq_count = 0x3E0,
548         },
549 };
550
551 static void usb_phy_fence_read(struct tegra_usb_phy *phy)
552 {
553         /* Fence read for coherency of AHB master intiated writes */
554         if (phy->inst == 0)
555                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB1_PREFETCH_ID));
556         else if (phy->inst == 1)
557                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB2_PREFETCH_ID));
558         else if (phy->inst == 2)
559                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB3_PREFETCH_ID));
560
561         return;
562 }
563
564 static void utmip_setup_pmc_wake_detect(struct tegra_usb_phy *phy)
565 {
566         unsigned long val, pmc_pad_cfg_val;
567         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
568         unsigned  int inst = phy->inst;
569         void __iomem *base = phy->regs;
570         bool port_connected;
571         enum usb_phy_port_speed port_speed;
572
573         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
574
575         /* check for port connect status */
576         val = readl(base + USB_PORTSC);
577         port_connected = val & USB_PORTSC_CCS;
578
579         if (!port_connected)
580                 return;
581
582         port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
583                 HOSTPC1_DEVLC_PSPD_MASK;
584         /*Set PMC MASTER bits to do the following
585         * a. Take over the UTMI drivers
586         * b. set up such that it will take over resume
587         *        if remote wakeup is detected
588         * Prepare PMC to take over suspend-wake detect-drive resume until USB
589         * controller ready
590         */
591
592         /* disable master enable in PMC */
593         val = readl(pmc_base + PMC_SLEEP_CFG);
594         val &= ~UTMIP_MASTER_ENABLE(inst);
595         writel(val, pmc_base + PMC_SLEEP_CFG);
596
597         /* UTMIP_PWR_PX=1 for power savings mode */
598         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
599         val |= UTMIP_PWR(inst);
600         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
601
602         /* config debouncer */
603         val = readl(pmc_base + PMC_USB_DEBOUNCE);
604         val &= ~UTMIP_LINE_DEB_CNT(~0);
605         val |= UTMIP_LINE_DEB_CNT(4);
606         writel(val, pmc_base + PMC_USB_DEBOUNCE);
607
608         /* Make sure nothing is happening on the line with respect to PMC */
609         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
610         val &= ~USBOP_VAL(inst);
611         val &= ~USBON_VAL(inst);
612         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
613
614         /* Make sure wake value for line is none */
615         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
616         val &= ~UTMIP_LINEVAL_WALK_EN(inst);
617         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
618         val = readl(pmc_base + PMC_SLEEP_CFG);
619         val &= ~UTMIP_WAKE_VAL(inst, ~0);
620         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
621         writel(val, pmc_base + PMC_SLEEP_CFG);
622
623         /* turn off pad detectors */
624         val = readl(pmc_base + PMC_USB_AO);
625         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
626         writel(val, pmc_base + PMC_USB_AO);
627
628         /* Remove fake values and make synchronizers work a bit */
629         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
630         val &= ~USBOP_VAL(inst);
631         val &= ~USBON_VAL(inst);
632         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
633
634         /* Enable which type of event can trigger a walk,
635         in this case usb_line_wake */
636         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
637         val |= UTMIP_LINEVAL_WALK_EN(inst);
638         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
639
640         /* Enable which type of event can trigger a walk,
641         * in this case usb_line_wake */
642         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
643         val |= UTMIP_LINEVAL_WALK_EN(inst);
644         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
645
646         /* Capture FS/LS pad configurations */
647         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
648         val = readl(pmc_base + PMC_TRIGGERS);
649         val |= UTMIP_CAP_CFG(inst);
650         writel(val, pmc_base + PMC_TRIGGERS);
651         udelay(1);
652         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
653
654         /* BIAS MASTER_ENABLE=0 */
655         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
656         val &= ~BIAS_MASTER_PROG_VAL;
657         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
658
659         /* program walk sequence, maintain a J, followed by a driven K
660         * to signal a resume once an wake event is detected */
661         val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
662         val &= ~UTMIP_AP_A;
663         val |= UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_AN_A |UTMIP_HIGHZ_A |
664                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_AP_B | UTMIP_AN_B |
665                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_AP_C | UTMIP_AN_C |
666                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_AP_D | UTMIP_AN_D;
667         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
668
669         if (port_speed == USB_PHY_PORT_SPEED_LOW) {
670                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
671                 val &= ~(UTMIP_AN_B | UTMIP_HIGHZ_B | UTMIP_AN_C |
672                         UTMIP_HIGHZ_C | UTMIP_AN_D | UTMIP_HIGHZ_D);
673                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
674         } else {
675                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
676                 val &= ~(UTMIP_AP_B | UTMIP_HIGHZ_B | UTMIP_AP_C |
677                         UTMIP_HIGHZ_C | UTMIP_AP_D | UTMIP_HIGHZ_D);
678                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
679         }
680
681         /* turn on pad detectors */
682         val = readl(pmc_base + PMC_USB_AO);
683         val &= ~(USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
684         writel(val, pmc_base + PMC_USB_AO);
685
686         /* Add small delay before usb detectors provide stable line values */
687         mdelay(1);
688
689         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
690         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
691         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
692         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
693
694         phy->remote_wakeup = false;
695
696         /* Turn over pad configuration to PMC  for line wake events*/
697         val = readl(pmc_base + PMC_SLEEP_CFG);
698         val &= ~UTMIP_WAKE_VAL(inst, ~0);
699         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_ANY);
700         val |= UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst);
701         val |= UTMIP_MASTER_ENABLE(inst) | UTMIP_FSLS_USE_PMC(inst);
702         writel(val, pmc_base + PMC_SLEEP_CFG);
703
704         val = readl(base + UTMIP_PMC_WAKEUP0);
705         val |= EVENT_INT_ENB;
706         writel(val, base + UTMIP_PMC_WAKEUP0);
707         PHY_DBG("%s ENABLE_PMC inst = %d\n", __func__, inst);
708 }
709
710 static void utmip_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy)
711 {
712         unsigned long val;
713         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
714         unsigned  int inst = phy->inst;
715         void __iomem *base = phy->regs;
716
717         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
718
719         val = readl(pmc_base + PMC_SLEEP_CFG);
720         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
721         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
722         writel(val, pmc_base + PMC_SLEEP_CFG);
723
724         val = readl(base + UTMIP_PMC_WAKEUP0);
725         val &= ~EVENT_INT_ENB;
726         writel(val, base + UTMIP_PMC_WAKEUP0);
727
728         /* Disable PMC master mode by clearing MASTER_EN */
729         val = readl(pmc_base + PMC_SLEEP_CFG);
730         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
731                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
732         writel(val, pmc_base + PMC_SLEEP_CFG);
733
734         val = readl(pmc_base + PMC_TRIGGERS);
735         val &= ~UTMIP_CAP_CFG(inst);
736         writel(val, pmc_base + PMC_TRIGGERS);
737
738         /* turn off pad detectors */
739         val = readl(pmc_base + PMC_USB_AO);
740         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
741         writel(val, pmc_base + PMC_USB_AO);
742
743         val = readl(pmc_base + PMC_TRIGGERS);
744         val |= UTMIP_CLR_WALK_PTR(inst);
745         writel(val, pmc_base + PMC_TRIGGERS);
746
747         phy->remote_wakeup = false;
748         PHY_DBG("%s DISABLE_PMC inst = %d\n", __func__, inst);
749 }
750
751 bool utmi_phy_remotewake_detected(struct tegra_usb_phy *phy)
752 {
753         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
754         void __iomem *base = phy->regs;
755         unsigned  int inst = phy->inst;
756         u32 val;
757
758         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
759         val = readl(base + UTMIP_PMC_WAKEUP0);
760         if (val & EVENT_INT_ENB) {
761                 val = readl(pmc_base + UTMIP_UHSIC_STATUS);
762                 if (UTMIP_WAKE_ALARM(inst) & val) {
763                         val = readl(pmc_base + PMC_SLEEP_CFG);
764                         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
765                         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
766                         writel(val, pmc_base + PMC_SLEEP_CFG);
767
768                         val = readl(pmc_base + PMC_TRIGGERS);
769                         val |= UTMIP_CLR_WAKE_ALARM(inst);
770                         writel(val, pmc_base + PMC_TRIGGERS);
771
772                         val = readl(base + UTMIP_PMC_WAKEUP0);
773                         val &= ~EVENT_INT_ENB;
774                         writel(val, base + UTMIP_PMC_WAKEUP0);
775                         phy->remote_wakeup = true;
776                         return true;
777                 }
778         }
779         return false;
780 }
781
782 static void utmi_phy_enable_trking_data(struct tegra_usb_phy *phy)
783 {
784         void __iomem *base = IO_ADDRESS(TEGRA_USB_BASE);
785         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
786         static bool init_done = false;
787         u32 val;
788
789         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
790
791         /* Should be done only once after system boot */
792         if (init_done)
793                 return;
794
795         clk_enable(phy->utmi_pad_clk);
796         /* Bias pad MASTER_ENABLE=1 */
797         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
798         val |= BIAS_MASTER_PROG_VAL;
799         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
800
801         /* Setting the tracking length time */
802         val = readl(base + UTMIP_BIAS_CFG1);
803         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
804         val |= UTMIP_BIAS_PDTRK_COUNT(5);
805         writel(val, base + UTMIP_BIAS_CFG1);
806
807         /* Bias PDTRK is Shared and MUST be done from USB1 ONLY, PD_TRK=0 */
808         val = readl(base + UTMIP_BIAS_CFG1);
809         val &= ~UTMIP_BIAS_PDTRK_POWERDOWN;
810         writel(val, base + UTMIP_BIAS_CFG1);
811
812         val = readl(base + UTMIP_BIAS_CFG1);
813         val |= UTMIP_BIAS_PDTRK_POWERUP;
814         writel(val, base + UTMIP_BIAS_CFG1);
815
816         /* Wait for 25usec */
817         udelay(25);
818
819         /* Bias pad MASTER_ENABLE=0 */
820         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
821         val &= ~BIAS_MASTER_PROG_VAL;
822         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
823
824         /* Wait for 1usec */
825         udelay(1);
826
827         /* Bias pad MASTER_ENABLE=1 */
828         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
829         val |= BIAS_MASTER_PROG_VAL;
830         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
831
832         /* Read RCTRL and TCTRL from UTMIP space */
833         val = readl(base + UTMIP_BIAS_STS0);
834         utmip_rctrl_val = ffz(UTMIP_RCTRL_VAL(val));
835         utmip_tctrl_val = ffz(UTMIP_TCTRL_VAL(val));
836
837         /* PD_TRK=1 */
838         val = readl(base + UTMIP_BIAS_CFG1);
839         val |= UTMIP_BIAS_PDTRK_POWERDOWN;
840         writel(val, base + UTMIP_BIAS_CFG1);
841
842         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
843         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
844         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
845         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
846         clk_disable(phy->utmi_pad_clk);
847         init_done = true;
848 }
849
850 static void utmip_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy)
851 {
852         unsigned long val;
853         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
854         unsigned  int inst = phy->inst;
855
856         /* power down UTMIP interfaces */
857         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
858         val |= UTMIP_PWR(inst);
859         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
860
861         /* setup sleep walk usb controller */
862         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
863                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
864                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
865                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
866         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
867
868         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
869         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
870         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
871         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
872
873         /* Turn over pad configuration to PMC */
874         val = readl(pmc_base + PMC_SLEEP_CFG);
875         val &= ~UTMIP_WAKE_VAL(inst, ~0);
876         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE) |
877                 UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
878                 UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst);
879         writel(val, pmc_base + PMC_SLEEP_CFG);
880         PHY_DBG("%s ENABLE_PMC inst = %d\n", __func__, inst);
881 }
882
883 static void utmip_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
884 {
885         unsigned long val;
886         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
887         unsigned  int inst = phy->inst;
888
889         /* Disable PMC master mode by clearing MASTER_EN */
890         val = readl(pmc_base + PMC_SLEEP_CFG);
891         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
892                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
893         writel(val, pmc_base + PMC_SLEEP_CFG);
894         mdelay(1);
895         PHY_DBG("%s DISABLE_PMC inst = %d\n", __func__, inst);
896 }
897
898
899 #ifdef KERNEL_WARNING
900 static void usb_phy_power_down_pmc(void)
901 {
902         unsigned long val;
903         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
904
905         /* power down all 3 UTMIP interfaces */
906         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
907         val |= UTMIP_PWR(0) | UTMIP_PWR(1) | UTMIP_PWR(2);
908         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
909
910         /* turn on pad detectors */
911         writel(PMC_POWER_DOWN_MASK, pmc_base + PMC_USB_AO);
912
913         /* setup sleep walk fl all 3 usb controllers */
914         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
915                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
916                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
917                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
918         writel(val, pmc_base + PMC_SLEEPWALK_REG(0));
919         writel(val, pmc_base + PMC_SLEEPWALK_REG(1));
920         writel(val, pmc_base + PMC_SLEEPWALK_REG(2));
921
922         /* enable pull downs on HSIC PMC */
923         val = UHSIC_STROBE_RPD_A | UHSIC_DATA_RPD_A | UHSIC_STROBE_RPD_B |
924                 UHSIC_DATA_RPD_B | UHSIC_STROBE_RPD_C | UHSIC_DATA_RPD_C |
925                 UHSIC_STROBE_RPD_D | UHSIC_DATA_RPD_D;
926         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
927
928         /* Turn over pad configuration to PMC */
929         val = readl(pmc_base + PMC_SLEEP_CFG);
930         val &= ~UTMIP_WAKE_VAL(0, ~0);
931         val &= ~UTMIP_WAKE_VAL(1, ~0);
932         val &= ~UTMIP_WAKE_VAL(2, ~0);
933         val &= ~UHSIC_WAKE_VAL_P0(~0);
934         val |= UTMIP_WAKE_VAL(0, WAKE_VAL_NONE) | UHSIC_WAKE_VAL_P0(WAKE_VAL_NONE) |
935         UTMIP_WAKE_VAL(1, WAKE_VAL_NONE) | UTMIP_WAKE_VAL(2, WAKE_VAL_NONE) |
936         UTMIP_RCTRL_USE_PMC(0) | UTMIP_RCTRL_USE_PMC(1) | UTMIP_RCTRL_USE_PMC(2) |
937         UTMIP_TCTRL_USE_PMC(0) | UTMIP_TCTRL_USE_PMC(1) | UTMIP_TCTRL_USE_PMC(2) |
938         UTMIP_FSLS_USE_PMC(0) | UTMIP_FSLS_USE_PMC(1) | UTMIP_FSLS_USE_PMC(2) |
939         UTMIP_MASTER_ENABLE(0) | UTMIP_MASTER_ENABLE(1) | UTMIP_MASTER_ENABLE(2) |
940         UHSIC_MASTER_ENABLE_P0;
941         writel(val, pmc_base + PMC_SLEEP_CFG);
942 }
943 #endif
944
945 static int usb_phy_bringup_host_controller(struct tegra_usb_phy *phy)
946 {
947         unsigned long val;
948         void __iomem *base = phy->regs;
949
950         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
951         PHY_DBG("[%d] USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n", __LINE__,
952                 readl(base + USB_USBSTS), readl(base + USB_PORTSC),
953                                                         phy->port_speed);
954
955         /* Device is plugged in when system is in LP0 */
956         /* Bring up the controller from LP0*/
957         val = readl(base + USB_USBCMD);
958         val |= USB_CMD_RESET;
959         writel(val, base + USB_USBCMD);
960
961         if (usb_phy_reg_status_wait(base + USB_USBCMD,
962                 USB_CMD_RESET, 0, 2500) < 0) {
963                 pr_err("%s: timeout waiting for reset\n", __func__);
964         }
965
966         val = readl(base + USB_USBMODE);
967         val &= ~USB_USBMODE_MASK;
968         val |= USB_USBMODE_HOST;
969         writel(val, base + USB_USBMODE);
970         val = readl(base + HOSTPC1_DEVLC);
971         val &= ~HOSTPC1_DEVLC_PTS(~0);
972
973         if (phy->pdata->phy_intf == TEGRA_USB_PHY_INTF_HSIC)
974                 val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
975         else
976                 val |= HOSTPC1_DEVLC_STS;
977         writel(val, base + HOSTPC1_DEVLC);
978
979         /* Enable Port Power */
980         val = readl(base + USB_PORTSC);
981         val |= USB_PORTSC_PP;
982         writel(val, base + USB_PORTSC);
983         udelay(10);
984
985         /* Check if the phy resume from LP0. When the phy resume from LP0
986          * USB register will be reset.to zero */
987         if (!readl(base + USB_ASYNCLISTADDR)) {
988                 /* Program the field PTC based on the saved speed mode */
989                 val = readl(base + USB_PORTSC);
990                 val &= ~USB_PORTSC_PTC(~0);
991                 if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH)
992                         val |= USB_PORTSC_PTC(5);
993                 else if (phy->port_speed == USB_PHY_PORT_SPEED_FULL)
994                         val |= USB_PORTSC_PTC(6);
995                 else if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
996                         val |= USB_PORTSC_PTC(7);
997                 writel(val, base + USB_PORTSC);
998                 udelay(10);
999
1000                 /* Disable test mode by setting PTC field to NORMAL_OP */
1001                 val = readl(base + USB_PORTSC);
1002                 val &= ~USB_PORTSC_PTC(~0);
1003                 writel(val, base + USB_PORTSC);
1004                 udelay(10);
1005         }
1006
1007         /* Poll until CCS is enabled */
1008         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
1009                                                  USB_PORTSC_CCS, 2000)) {
1010                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
1011         }
1012
1013         /* Poll until PE is enabled */
1014         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_PE,
1015                                                  USB_PORTSC_PE, 2000)) {
1016                 pr_err("%s: timeout waiting for USB_PORTSC_PE\n", __func__);
1017         }
1018
1019         /* Clear the PCI status, to avoid an interrupt taken upon resume */
1020         val = readl(base + USB_USBSTS);
1021         val |= USB_USBSTS_PCI;
1022         writel(val, base + USB_USBSTS);
1023
1024         if (!phy->remote_wakeup) {
1025                 /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
1026                 val = readl(base + USB_PORTSC);
1027                 if ((val & USB_PORTSC_PP) && (val & USB_PORTSC_PE)) {
1028                         val |= USB_PORTSC_SUSP;
1029                         writel(val, base + USB_PORTSC);
1030                         /* Need a 4ms delay before the controller goes to suspend */
1031                         mdelay(4);
1032
1033                         /* Wait until port suspend completes */
1034                         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_SUSP,
1035                                                          USB_PORTSC_SUSP, 1000)) {
1036                                 pr_err("%s: timeout waiting for PORT_SUSPEND\n",
1037                                                                         __func__);
1038                         }
1039                 }
1040         }
1041         PHY_DBG("[%d] USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n", __LINE__,
1042                 readl(base + USB_USBSTS), readl(base + USB_PORTSC),
1043                                                         phy->port_speed);
1044
1045         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1046                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1047         return 0;
1048 }
1049
1050 static void usb_phy_wait_for_sof(struct tegra_usb_phy *phy)
1051 {
1052         unsigned long val;
1053         void __iomem *base = phy->regs;
1054
1055         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1056
1057         val = readl(base + USB_USBSTS);
1058         writel(val, base + USB_USBSTS);
1059         udelay(20);
1060         /* wait for two SOFs */
1061         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1062                 USB_USBSTS_SRI, 2500))
1063                 pr_err("%s: timeout waiting for SOF\n", __func__);
1064
1065         val = readl(base + USB_USBSTS);
1066         writel(val, base + USB_USBSTS);
1067         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI, 0, 2500))
1068                 pr_err("%s: timeout waiting for SOF\n", __func__);
1069
1070         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1071                         USB_USBSTS_SRI, 2500))
1072                 pr_err("%s: timeout waiting for SOF\n", __func__);
1073
1074         udelay(20);
1075 }
1076
1077 static unsigned int utmi_phy_xcvr_setup_value(struct tegra_usb_phy *phy)
1078 {
1079         struct tegra_utmi_config *cfg = &phy->pdata->u_cfg.utmi;
1080         signed long val;
1081
1082         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1083
1084         if (cfg->xcvr_use_fuses) {
1085                 val = XCVR_SETUP(tegra_fuse_readl(FUSE_USB_CALIB_0));
1086                 if (cfg->xcvr_use_lsb) {
1087                         val = min((unsigned int) ((val & XCVR_SETUP_LSB_MASK)
1088                                 + cfg->xcvr_setup_offset),
1089                                 (unsigned int) XCVR_SETUP_LSB_MAX_VAL);
1090                         val |= (cfg->xcvr_setup & XCVR_SETUP_MSB_MASK);
1091                 } else {
1092                         if (cfg->xcvr_setup_offset <= UTMIP_XCVR_MAX_OFFSET)
1093                                 val = val + cfg->xcvr_setup_offset;
1094
1095                         if (val > UTMIP_XCVR_SETUP_MAX_VALUE) {
1096                                 val = UTMIP_XCVR_SETUP_MAX_VALUE;
1097                                 pr_info("%s: reset XCVR_SETUP to max value\n",
1098                                                 __func__);
1099                         } else if (val < UTMIP_XCVR_SETUP_MIN_VALUE) {
1100                                 val = UTMIP_XCVR_SETUP_MIN_VALUE;
1101                                 pr_info("%s: reset XCVR_SETUP to min value\n",
1102                                                 __func__);
1103                         }
1104                 }
1105         } else {
1106                 val = cfg->xcvr_setup;
1107         }
1108
1109         return (unsigned int) val;
1110 }
1111
1112 static int utmi_phy_open(struct tegra_usb_phy *phy)
1113 {
1114         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1115         unsigned long parent_rate, val;
1116         int i;
1117
1118         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1119
1120         phy->utmi_pad_clk = clk_get_sys("utmip-pad", NULL);
1121         if (IS_ERR(phy->utmi_pad_clk)) {
1122                 pr_err("%s: can't get utmip pad clock\n", __func__);
1123                 return PTR_ERR(phy->utmi_pad_clk);
1124         }
1125
1126         phy->utmi_xcvr_setup = utmi_phy_xcvr_setup_value(phy);
1127
1128         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
1129         for (i = 0; i < ARRAY_SIZE(utmip_freq_table); i++) {
1130                 if (utmip_freq_table[i].freq == parent_rate) {
1131                         phy->freq = &utmip_freq_table[i];
1132                         break;
1133                 }
1134         }
1135         if (!phy->freq) {
1136                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
1137                 return -EINVAL;
1138         }
1139
1140         /* Power-up the VBUS detector for UTMIP PHY */
1141         val = readl(pmc_base + PMC_USB_AO);
1142         val &= ~(PMC_USB_AO_VBUS_WAKEUP_PD_P0 | PMC_USB_AO_ID_PD_P0);
1143         writel((val | PMC_USB_AO_PD_P2), (pmc_base + PMC_USB_AO));
1144
1145         utmip_powerup_pmc_wake_detect(phy);
1146
1147         return 0;
1148 }
1149
1150 static void utmi_phy_close(struct tegra_usb_phy *phy)
1151 {
1152         unsigned long val;
1153         void __iomem *base = phy->regs;
1154
1155         DBG("%s inst:[%d]\n", __func__, phy->inst);
1156
1157         /* Disable PHY clock valid interrupts while going into suspend*/
1158         if (phy->pdata->u_data.host.hot_plug) {
1159                 val = readl(base + USB_SUSP_CTRL);
1160                 val &= ~USB_PHY_CLK_VALID_INT_ENB;
1161                 writel(val, base + USB_SUSP_CTRL);
1162         }
1163
1164         clk_put(phy->utmi_pad_clk);
1165 }
1166
1167 static int utmi_phy_pad_power_on(struct tegra_usb_phy *phy)
1168 {
1169         unsigned long val, flags;
1170         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1171
1172         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1173
1174         clk_enable(phy->utmi_pad_clk);
1175
1176         spin_lock_irqsave(&utmip_pad_lock, flags);
1177         utmip_pad_count++;
1178
1179         val = readl(pad_base + UTMIP_BIAS_CFG0);
1180         val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
1181         val |= UTMIP_HSSQUELCH_LEVEL(0x2) | UTMIP_HSDISCON_LEVEL(0x1) |
1182                 UTMIP_HSDISCON_LEVEL_MSB;
1183         writel(val, pad_base + UTMIP_BIAS_CFG0);
1184
1185         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1186
1187         clk_disable(phy->utmi_pad_clk);
1188
1189         return 0;
1190 }
1191
1192 static int utmi_phy_pad_power_off(struct tegra_usb_phy *phy)
1193 {
1194         unsigned long val, flags;
1195         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1196
1197         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1198
1199         clk_enable(phy->utmi_pad_clk);
1200         spin_lock_irqsave(&utmip_pad_lock, flags);
1201
1202         if (!utmip_pad_count) {
1203                 pr_err("%s: utmip pad already powered off\n", __func__);
1204                 goto out;
1205         }
1206         if (--utmip_pad_count == 0) {
1207                 val = readl(pad_base + UTMIP_BIAS_CFG0);
1208                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
1209                 val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) | UTMIP_HSDISCON_LEVEL(~0) |
1210                         UTMIP_HSDISCON_LEVEL_MSB);
1211                 writel(val, pad_base + UTMIP_BIAS_CFG0);
1212         }
1213 out:
1214         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1215         clk_disable(phy->utmi_pad_clk);
1216
1217         return 0;
1218 }
1219
1220 static int utmi_phy_irq(struct tegra_usb_phy *phy)
1221 {
1222         void __iomem *base = phy->regs;
1223         unsigned long val = 0;
1224
1225         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1226         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1227                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1228         DBG("USB_USBMODE[0x%x] USB_USBCMD[0x%x]\n",
1229                         readl(base + USB_USBMODE), readl(base + USB_USBCMD));
1230
1231         usb_phy_fence_read(phy);
1232         /* check if there is any remote wake event */
1233         if (utmi_phy_remotewake_detected(phy))
1234                 pr_info("%s: utmip remote wake detected\n", __func__);
1235
1236         if (phy->pdata->u_data.host.hot_plug) {
1237                 val = readl(base + USB_SUSP_CTRL);
1238                 if ((val  & USB_PHY_CLK_VALID_INT_STS)) {
1239                         val &= ~USB_PHY_CLK_VALID_INT_ENB |
1240                                         USB_PHY_CLK_VALID_INT_STS;
1241                         writel(val , (base + USB_SUSP_CTRL));
1242                         pr_info("%s: usb device plugged-in\n", __func__);
1243                         val = readl(base + USB_USBSTS);
1244                         if (!(val  & USB_USBSTS_PCI))
1245                                 return IRQ_NONE;
1246                         val = readl(base + USB_PORTSC);
1247                         val &= ~(USB_PORTSC_WKCN | USB_PORTSC_RWC_BITS);
1248                         writel(val , (base + USB_PORTSC));
1249                 }
1250         }
1251
1252         return IRQ_HANDLED;
1253 }
1254
1255 static void utmi_phy_enable_obs_bus(struct tegra_usb_phy *phy)
1256 {
1257         unsigned long val;
1258         void __iomem *base = phy->regs;
1259
1260         /* (2LS WAR)is not required for LS and FS devices and is only for HS */
1261         if ((phy->port_speed == USB_PHY_PORT_SPEED_LOW) ||
1262                 (phy->port_speed == USB_PHY_PORT_SPEED_FULL)) {
1263                 /* do not enable the OBS bus */
1264                 val = readl(base + UTMIP_MISC_CFG0);
1265                 val &= ~(UTMIP_DPDM_OBSERVE_SEL(~0));
1266                 writel(val, base + UTMIP_MISC_CFG0);
1267                 DBG("%s(%d) Disable OBS bus\n", __func__, __LINE__);
1268                 return;
1269         }
1270         /* Force DP/DM pulldown active for Host mode */
1271         val = readl(base + UTMIP_MISC_CFG0);
1272         val |= FORCE_PULLDN_DM | FORCE_PULLDN_DP |
1273                         COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS;
1274         writel(val, base + UTMIP_MISC_CFG0);
1275         val = readl(base + UTMIP_MISC_CFG0);
1276         val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1277         if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
1278                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
1279         else
1280                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
1281         writel(val, base + UTMIP_MISC_CFG0);
1282         udelay(1);
1283
1284         val = readl(base + UTMIP_MISC_CFG0);
1285         val |= UTMIP_DPDM_OBSERVE;
1286         writel(val, base + UTMIP_MISC_CFG0);
1287         udelay(10);
1288         DBG("%s(%d) Enable OBS bus\n", __func__, __LINE__);
1289         PHY_DBG("ENABLE_OBS_BUS\n");
1290 }
1291
1292 static int utmi_phy_disable_obs_bus(struct tegra_usb_phy *phy)
1293 {
1294         unsigned long val;
1295         void __iomem *base = phy->regs;
1296         unsigned long flags;
1297
1298         /* check if OBS bus is already enabled */
1299         val = readl(base + UTMIP_MISC_CFG0);
1300         if (val & UTMIP_DPDM_OBSERVE) {
1301                 PHY_DBG("DISABLE_OBS_BUS\n");
1302
1303                 /* disable ALL interrupts on current CPU */
1304                 local_irq_save(flags);
1305
1306                 /* Change the UTMIP OBS bus to drive SE0 */
1307                 val = readl(base + UTMIP_MISC_CFG0);
1308                 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1309                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_SE0;
1310                 writel(val, base + UTMIP_MISC_CFG0);
1311
1312                 /* Wait for 3us(2 LS bit times) */
1313                 udelay(3);
1314
1315                 /* Release UTMIP OBS bus */
1316                 val = readl(base + UTMIP_MISC_CFG0);
1317                 val &= ~UTMIP_DPDM_OBSERVE;
1318                 writel(val, base + UTMIP_MISC_CFG0);
1319
1320                 /* Release DP/DM pulldown for Host mode */
1321                 val = readl(base + UTMIP_MISC_CFG0);
1322                 val &= ~(FORCE_PULLDN_DM | FORCE_PULLDN_DP |
1323                                 COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS);
1324                 writel(val, base + UTMIP_MISC_CFG0);
1325
1326                 val = readl(base + USB_USBCMD);
1327                 val |= USB_USBCMD_RS;
1328                 writel(val, base + USB_USBCMD);
1329
1330                 /* restore ALL interrupts on current CPU */
1331                 local_irq_restore(flags);
1332
1333                 if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
1334                                                          USB_USBCMD_RS, 2000)) {
1335                         pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
1336                         return -ETIMEDOUT;
1337                 }
1338         }
1339         return 0;
1340 }
1341
1342 static int utmi_phy_post_resume(struct tegra_usb_phy *phy)
1343 {
1344         unsigned long val;
1345         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1346         unsigned  int inst = phy->inst;
1347
1348         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1349         val = readl(pmc_base + PMC_SLEEP_CFG);
1350         /* if PMC is not disabled by now then disable it */
1351         if (val & UTMIP_MASTER_ENABLE(inst)) {
1352                 utmip_phy_disable_pmc_bus_ctrl(phy);
1353         }
1354
1355         utmi_phy_disable_obs_bus(phy);
1356
1357         return 0;
1358 }
1359
1360 static int utmi_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1361 {
1362         unsigned long val;
1363         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1364         void __iomem *base = phy->regs;
1365         unsigned  int inst = phy->inst;
1366
1367         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1368         phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
1369                         HOSTPC1_DEVLC_PSPD_MASK;
1370
1371         if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH) {
1372                 /* Disable interrupts */
1373                 writel(0, base + USB_USBINTR);
1374                 /* Clear the run bit to stop SOFs - 2LS WAR */
1375                 val = readl(base + USB_USBCMD);
1376                 val &= ~USB_USBCMD_RS;
1377                 writel(val, base + USB_USBCMD);
1378                 if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
1379                                                          USB_USBSTS_HCH, 2000)) {
1380                         pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
1381                 }
1382         }
1383
1384         val = readl(pmc_base + PMC_SLEEP_CFG);
1385         if (val & UTMIP_MASTER_ENABLE(inst)) {
1386                 if (!remote_wakeup)
1387                         utmip_phy_disable_pmc_bus_ctrl(phy);
1388         } else {
1389                 utmi_phy_enable_obs_bus(phy);
1390         }
1391
1392         return 0;
1393 }
1394
1395 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
1396 {
1397         unsigned long val;
1398         void __iomem *base = phy->regs;
1399
1400         PHY_DBG("%s(%d) inst:[%d] BEGIN\n", __func__, __LINE__, phy->inst);
1401         if (!phy->phy_clk_on) {
1402                 PHY_DBG("%s(%d) inst:[%d] phy clk is already off\n",
1403                                         __func__, __LINE__, phy->inst);
1404                 return 0;
1405         }
1406
1407         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1408                 utmip_powerdown_pmc_wake_detect(phy);
1409
1410                 val = readl(base + USB_SUSP_CTRL);
1411                 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
1412                 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
1413                 writel(val, base + USB_SUSP_CTRL);
1414
1415                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1416                 val |= UTMIP_PD_CHRG;
1417                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1418         } else {
1419                 phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
1420                                 HOSTPC1_DEVLC_PSPD_MASK;
1421
1422                 /* Disable interrupts */
1423                 writel(0, base + USB_USBINTR);
1424
1425                 /* Clear the run bit to stop SOFs - 2LS WAR */
1426                 val = readl(base + USB_USBCMD);
1427                 val &= ~USB_USBCMD_RS;
1428                 writel(val, base + USB_USBCMD);
1429
1430                 if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
1431                                                          USB_USBSTS_HCH, 2000)) {
1432                         pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
1433                 }
1434                 utmip_setup_pmc_wake_detect(phy);
1435         }
1436
1437         if (!phy->pdata->u_data.host.hot_plug) {
1438                 val = readl(base + UTMIP_XCVR_CFG0);
1439                 val |= (UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
1440                          UTMIP_FORCE_PDZI_POWERDOWN);
1441                 writel(val, base + UTMIP_XCVR_CFG0);
1442         }
1443
1444         val = readl(base + UTMIP_XCVR_CFG1);
1445         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1446                    UTMIP_FORCE_PDDR_POWERDOWN;
1447         writel(val, base + UTMIP_XCVR_CFG1);
1448
1449         val = readl(base + UTMIP_BIAS_CFG1);
1450         val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
1451         writel(val, base + UTMIP_BIAS_CFG1);
1452
1453         utmi_phy_pad_power_off(phy);
1454
1455         if (phy->pdata->u_data.host.hot_plug) {
1456                 bool enable_hotplug = true;
1457                 /* if it is OTG port then make sure to enable hot-plug feature
1458                    only if host adaptor is connected, i.e id is low */
1459                 if (phy->pdata->port_otg) {
1460                         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1461                         enable_hotplug = (val & USB_ID_STATUS) ? false : true;
1462                 }
1463                 if (enable_hotplug) {
1464                         val = readl(base + USB_PORTSC);
1465                         val |= USB_PORTSC_WKCN;
1466                         writel(val, base + USB_PORTSC);
1467
1468                         val = readl(base + USB_SUSP_CTRL);
1469                         val |= USB_PHY_CLK_VALID_INT_ENB;
1470                         writel(val, base + USB_SUSP_CTRL);
1471                 } else {
1472                         /* Disable PHY clock valid interrupts while going into suspend*/
1473                         val = readl(base + USB_SUSP_CTRL);
1474                         val &= ~USB_PHY_CLK_VALID_INT_ENB;
1475                         writel(val, base + USB_SUSP_CTRL);
1476                 }
1477         }
1478
1479         val = readl(base + HOSTPC1_DEVLC);
1480         val |= HOSTPC1_DEVLC_PHCD;
1481         writel(val, base + HOSTPC1_DEVLC);
1482
1483         if (!phy->pdata->u_data.host.hot_plug) {
1484                 val = readl(base + USB_SUSP_CTRL);
1485                 val |= UTMIP_RESET;
1486                 writel(val, base + USB_SUSP_CTRL);
1487         }
1488
1489         phy->phy_clk_on = false;
1490         phy->hw_accessible = false;
1491
1492         PHY_DBG("%s(%d) inst:[%d] END\n", __func__, __LINE__, phy->inst);
1493
1494         return 0;
1495 }
1496
1497
1498 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
1499 {
1500         unsigned long val;
1501         void __iomem *base = phy->regs;
1502         struct tegra_utmi_config *config = &phy->pdata->u_cfg.utmi;
1503
1504         PHY_DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1505         if (phy->phy_clk_on) {
1506                 PHY_DBG("%s(%d) inst:[%d] phy clk is already On\n",
1507                                         __func__, __LINE__, phy->inst);
1508                 return 0;
1509         }
1510         val = readl(base + USB_SUSP_CTRL);
1511         val |= UTMIP_RESET;
1512         writel(val, base + USB_SUSP_CTRL);
1513
1514         val = readl(base + UTMIP_TX_CFG0);
1515         val |= UTMIP_FS_PREABMLE_J;
1516         writel(val, base + UTMIP_TX_CFG0);
1517
1518         val = readl(base + UTMIP_HSRX_CFG0);
1519         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
1520         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
1521         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
1522         writel(val, base + UTMIP_HSRX_CFG0);
1523
1524         val = readl(base + UTMIP_HSRX_CFG1);
1525         val &= ~UTMIP_HS_SYNC_START_DLY(~0);
1526         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
1527         writel(val, base + UTMIP_HSRX_CFG1);
1528
1529         val = readl(base + UTMIP_DEBOUNCE_CFG0);
1530         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
1531         val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
1532         writel(val, base + UTMIP_DEBOUNCE_CFG0);
1533
1534         val = readl(base + UTMIP_MISC_CFG0);
1535         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
1536         writel(val, base + UTMIP_MISC_CFG0);
1537
1538         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1539                 val = readl(base + USB_SUSP_CTRL);
1540                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
1541                 writel(val, base + USB_SUSP_CTRL);
1542
1543                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1544                 val &= ~UTMIP_PD_CHRG;
1545                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1546         } else {
1547                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1548                 val |= UTMIP_PD_CHRG;
1549                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1550         }
1551
1552         utmi_phy_pad_power_on(phy);
1553
1554         val = readl(base + UTMIP_XCVR_CFG0);
1555         val &= ~(UTMIP_XCVR_LSBIAS_SEL | UTMIP_FORCE_PD_POWERDOWN |
1556                  UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN |
1557                  UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_LSFSLEW(~0) |
1558                  UTMIP_XCVR_LSRSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
1559         val |= UTMIP_XCVR_SETUP(phy->utmi_xcvr_setup);
1560         val |= UTMIP_XCVR_SETUP_MSB(XCVR_SETUP_MSB_CALIB(phy->utmi_xcvr_setup));
1561         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
1562         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
1563         if (!config->xcvr_use_lsb)
1564                 val |= UTMIP_XCVR_HSSLEW_MSB(0x8);
1565         writel(val, base + UTMIP_XCVR_CFG0);
1566
1567         val = readl(base + UTMIP_XCVR_CFG1);
1568         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1569                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
1570         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
1571         writel(val, base + UTMIP_XCVR_CFG1);
1572
1573         val = readl(base + UTMIP_BIAS_CFG1);
1574         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
1575         val |= UTMIP_BIAS_PDTRK_COUNT(phy->freq->pdtrk_count);
1576         writel(val, base + UTMIP_BIAS_CFG1);
1577
1578         val = readl(base + UTMIP_SPARE_CFG0);
1579         val &= ~FUSE_SETUP_SEL;
1580         val |= FUSE_ATERM_SEL;
1581         writel(val, base + UTMIP_SPARE_CFG0);
1582
1583         val = readl(base + USB_SUSP_CTRL);
1584         val |= UTMIP_PHY_ENABLE;
1585         writel(val, base + USB_SUSP_CTRL);
1586
1587         val = readl(base + USB_SUSP_CTRL);
1588         val &= ~UTMIP_RESET;
1589         writel(val, base + USB_SUSP_CTRL);
1590
1591         val = readl(base + HOSTPC1_DEVLC);
1592         val &= ~HOSTPC1_DEVLC_PHCD;
1593         writel(val, base + HOSTPC1_DEVLC);
1594
1595         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1596                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500))
1597                 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
1598
1599         utmi_phy_enable_trking_data(phy);
1600
1601         if (phy->inst == 2)
1602                 writel(0, base + ICUSB_CTRL);
1603
1604         val = readl(base + USB_USBMODE);
1605         val &= ~USB_USBMODE_MASK;
1606         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST)
1607                 val |= USB_USBMODE_HOST;
1608         else
1609                 val |= USB_USBMODE_DEVICE;
1610         writel(val, base + USB_USBMODE);
1611
1612         val = readl(base + HOSTPC1_DEVLC);
1613         val &= ~HOSTPC1_DEVLC_PTS(~0);
1614         val |= HOSTPC1_DEVLC_STS;
1615         writel(val, base + HOSTPC1_DEVLC);
1616
1617         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE)
1618                 utmip_powerup_pmc_wake_detect(phy);
1619         phy->phy_clk_on = true;
1620         phy->hw_accessible = true;
1621         PHY_DBG("%s(%d) End inst:[%d]\n", __func__, __LINE__, phy->inst);
1622         return 0;
1623 }
1624
1625 static void utmi_phy_restore_start(struct tegra_usb_phy *phy)
1626 {
1627         unsigned long val;
1628         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1629         int inst = phy->inst;
1630
1631         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1632         val = readl(pmc_base + UTMIP_UHSIC_STATUS);
1633         /* Check whether we wake up from the remote resume.
1634            For lp1 case, pmc is not responsible for waking the
1635            system, it's the flow controller and hence
1636            UTMIP_WALK_PTR_VAL(inst) will return 0.
1637            Also, for lp1 case phy->remote_wakeup will already be set
1638            to true by utmi_phy_irq() when the remote wakeup happens.
1639            Hence change the logic in the else part to enter only
1640            if phy->remote_wakeup is not set to true by the
1641            utmi_phy_irq(). */
1642         if (UTMIP_WALK_PTR_VAL(inst) & val) {
1643                 phy->remote_wakeup = true;
1644         } else if(!phy->remote_wakeup) {
1645                 if (!((UTMIP_USBON_VAL(phy->inst) |
1646                         UTMIP_USBOP_VAL(phy->inst)) & val)) {
1647                                 utmip_phy_disable_pmc_bus_ctrl(phy);
1648                 }
1649         }
1650         utmi_phy_enable_obs_bus(phy);
1651 }
1652
1653 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
1654 {
1655         unsigned long val;
1656         void __iomem *base = phy->regs;
1657         int wait_time_us = 25000; /* FPR should be set by this time */
1658
1659         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1660         /* check whether we wake up from the remote resume */
1661         if (phy->remote_wakeup) {
1662                 /* wait until SUSPEND and RESUME bit is cleared on remote resume */
1663                 do {
1664                         val = readl(base + USB_PORTSC);
1665                         udelay(1);
1666                         if (wait_time_us == 0) {
1667                                 PHY_DBG("%s PMC REMOTE WAKEUP FPR timeout val = 0x%x instance = %d\n", __func__, val, phy->inst);
1668                                 utmip_phy_disable_pmc_bus_ctrl(phy);
1669                                 utmi_phy_post_resume(phy);
1670                                 return;
1671                         }
1672                         wait_time_us--;
1673                 } while (val & (USB_PORTSC_RESUME | USB_PORTSC_SUSP));
1674
1675                 /* wait for 25 ms to port resume complete */
1676                 msleep(25);
1677                 /* disable PMC master control */
1678                 utmip_phy_disable_pmc_bus_ctrl(phy);
1679
1680                 /* Clear PCI and SRI bits to avoid an interrupt upon resume */
1681                 val = readl(base + USB_USBSTS);
1682                 writel(val, base + USB_USBSTS);
1683                 /* wait to avoid SOF if there is any */
1684                 if (usb_phy_reg_status_wait(base + USB_USBSTS,
1685                         USB_USBSTS_SRI, USB_USBSTS_SRI, 2500) < 0) {
1686                         pr_err("%s: timeout waiting for SOF\n", __func__);
1687                 }
1688                 utmi_phy_post_resume(phy);
1689         }
1690 }
1691
1692 static int utmi_phy_resume(struct tegra_usb_phy *phy)
1693 {
1694         int status = 0;
1695         unsigned long val;
1696         void __iomem *base = phy->regs;
1697
1698         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1699         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) {
1700                 if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
1701                         utmi_phy_restore_start(phy);
1702                         usb_phy_bringup_host_controller(phy);
1703                         utmi_phy_restore_end(phy);
1704                 } else {
1705                         /* device is plugged in when system is in LP0 */
1706                         /* bring up the controller from LP0*/
1707                         val = readl(base + USB_USBCMD);
1708                         val |= USB_CMD_RESET;
1709                         writel(val, base + USB_USBCMD);
1710
1711                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1712                                 USB_CMD_RESET, 0, 2500) < 0) {
1713                                 pr_err("%s: timeout waiting for reset\n", __func__);
1714                         }
1715
1716                         val = readl(base + USB_USBMODE);
1717                         val &= ~USB_USBMODE_MASK;
1718                         val |= USB_USBMODE_HOST;
1719                         writel(val, base + USB_USBMODE);
1720
1721                         val = readl(base + HOSTPC1_DEVLC);
1722                         val &= ~HOSTPC1_DEVLC_PTS(~0);
1723                         val |= HOSTPC1_DEVLC_STS;
1724                         writel(val, base + HOSTPC1_DEVLC);
1725
1726                         writel(USB_USBCMD_RS, base + USB_USBCMD);
1727
1728                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1729                                 USB_USBCMD_RS, USB_USBCMD_RS, 2500) < 0) {
1730                                 pr_err("%s: timeout waiting for run bit\n", __func__);
1731                         }
1732
1733                         /* Enable Port Power */
1734                         val = readl(base + USB_PORTSC);
1735                         val |= USB_PORTSC_PP;
1736                         writel(val, base + USB_PORTSC);
1737                         udelay(10);
1738
1739                         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1740                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1741                 }
1742         }
1743
1744         return status;
1745 }
1746
1747 bool utmi_phy_charger_detect(struct tegra_usb_phy *phy)
1748 {
1749         unsigned long val;
1750         void __iomem *base = phy->regs;
1751         bool status;
1752
1753         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1754         if (phy->pdata->op_mode != TEGRA_USB_OPMODE_DEVICE) {
1755                 /* Charger detection is not there for ULPI
1756                  * return Charger not available */
1757                 return false;
1758         }
1759
1760         /* Enable charger detection logic */
1761         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1762         val |= UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN;
1763         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1764
1765         /* Source should be on for 100 ms as per USB charging spec */
1766         msleep(TDP_SRC_ON_MS);
1767
1768         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1769         /* If charger is not connected disable the interrupt */
1770         val &= ~VDAT_DET_INT_EN;
1771         val |= VDAT_DET_CHG_DET;
1772         writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
1773
1774         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1775         if (val & VDAT_DET_STS)
1776                 status = true;
1777         else
1778                 status = false;
1779
1780         /* Disable charger detection logic */
1781         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1782         val &= ~(UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN);
1783         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1784
1785         /* Delay of 40 ms before we pull the D+ as per battery charger spec */
1786         msleep(TDPSRC_CON_MS);
1787
1788         return status;
1789 }
1790
1791 static void uhsic_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
1792 {
1793         unsigned long val;
1794         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1795
1796         /* turn on pad detectors for HSIC*/
1797         val = readl(pmc_base + PMC_USB_AO);
1798         val &= ~(HSIC_RESERVED_P0 | STROBE_VAL_PD_P0 | DATA_VAL_PD_P0);
1799         writel(val, pmc_base + PMC_USB_AO);
1800
1801         /* Disable PMC master mode by clearing MASTER_EN */
1802         val = readl(pmc_base + PMC_SLEEP_CFG);
1803         val &= ~(UHSIC_MASTER_ENABLE_P0);
1804         writel(val, pmc_base + PMC_SLEEP_CFG);
1805         mdelay(1);
1806 }
1807
1808 static void uhsic_setup_pmc_wake_detect(struct tegra_usb_phy *phy)
1809 {
1810         unsigned long val;
1811         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1812         void __iomem *base = phy->regs;
1813         bool port_connected;
1814
1815         DBG("%s:%d\n", __func__, __LINE__);
1816
1817         /* check for port connect status */
1818         val = readl(base + USB_PORTSC);
1819         port_connected = val & USB_PORTSC_CCS;
1820
1821         if (!port_connected)
1822                 return;
1823
1824         /*Set PMC MASTER bits to do the following
1825         * a. Take over the hsic drivers
1826         * b. set up such that it will take over resume
1827         *        if remote wakeup is detected
1828         * Prepare PMC to take over suspend-wake detect-drive resume until USB
1829         * controller ready
1830         */
1831
1832         /* disable master enable in PMC */
1833         val = readl(pmc_base + PMC_SLEEP_CFG);
1834         val &= ~UHSIC_MASTER_ENABLE_P0;
1835         writel(val, pmc_base + PMC_SLEEP_CFG);
1836
1837         /* UTMIP_PWR_PX=1 for power savings mode */
1838         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
1839         val |= UHSIC_PWR;
1840         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
1841
1842
1843         /* Enable which type of event can trigger a walk,
1844         * in this case usb_line_wake */
1845         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
1846         val |= UHSIC_LINEVAL_WALK_EN;
1847         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
1848
1849         /* program walk sequence, maintain a J, followed by a driven K
1850         * to signal a resume once an wake event is detected */
1851
1852         val = readl(pmc_base + PMC_SLEEPWALK_UHSIC);
1853
1854         val &= ~UHSIC_DATA_RPU_A;
1855         val |=  UHSIC_DATA_RPD_A;
1856         val &= ~UHSIC_STROBE_RPD_A;
1857         val |=  UHSIC_STROBE_RPU_A;
1858         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1859
1860         val &= ~UHSIC_DATA_RPD_B;
1861         val |=  UHSIC_DATA_RPU_B;
1862         val &= ~UHSIC_STROBE_RPU_B;
1863         val |=  UHSIC_STROBE_RPD_B;
1864         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1865
1866         val &= ~UHSIC_DATA_RPD_C;
1867         val |=  UHSIC_DATA_RPU_C;
1868         val &= ~UHSIC_STROBE_RPU_C;
1869         val |=  UHSIC_STROBE_RPD_C;
1870         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1871
1872         val &= ~UHSIC_DATA_RPD_D;
1873         val |=  UHSIC_DATA_RPU_D;
1874         val &= ~UHSIC_STROBE_RPU_D;
1875         val |=  UHSIC_STROBE_RPD_D;
1876         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1877
1878         /* turn on pad detectors */
1879         val = readl(pmc_base + PMC_USB_AO);
1880         val &= ~(STROBE_VAL_PD_P0 | DATA_VAL_PD_P0);
1881         writel(val, pmc_base + PMC_USB_AO);
1882         /* Add small delay before usb detectors provide stable line values */
1883         udelay(1);
1884
1885         phy->remote_wakeup = false;
1886
1887         /* Turn over pad configuration to PMC  for line wake events*/
1888         val = readl(pmc_base + PMC_SLEEP_CFG);
1889         val &= ~UHSIC_WAKE_VAL(~0);
1890         val |= UHSIC_WAKE_VAL(WAKE_VAL_SD10);
1891         val |= UHSIC_MASTER_ENABLE;
1892         writel(val, pmc_base + PMC_SLEEP_CFG);
1893
1894         val = readl(base + UHSIC_PMC_WAKEUP0);
1895         val |= EVENT_INT_ENB;
1896         writel(val, base + UHSIC_PMC_WAKEUP0);
1897
1898         DBG("%s:PMC enabled for HSIC remote wakeup\n", __func__);
1899 }
1900
1901 static void uhsic_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy)
1902 {
1903         unsigned long val;
1904         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1905         void __iomem *base = phy->regs;
1906
1907         DBG("%s (%d)\n", __func__, __LINE__);
1908         val = readl(pmc_base + PMC_SLEEP_CFG);
1909         val &= ~UHSIC_WAKE_VAL(0x0);
1910         val |= UHSIC_WAKE_VAL(WAKE_VAL_NONE);
1911         writel(val, pmc_base + PMC_SLEEP_CFG);
1912
1913         val = readl(pmc_base + PMC_TRIGGERS);
1914         val |= UHSIC_CLR_WAKE_ALARM_P0 | UHSIC_CLR_WALK_PTR_P0;
1915         writel(val, pmc_base + PMC_TRIGGERS);
1916
1917         val = readl(base + UHSIC_PMC_WAKEUP0);
1918         val &= ~EVENT_INT_ENB;
1919         writel(val, base + UHSIC_PMC_WAKEUP0);
1920
1921         /* Disable PMC master mode by clearing MASTER_EN */
1922         val = readl(pmc_base + PMC_SLEEP_CFG);
1923         val &= ~(UHSIC_MASTER_ENABLE);
1924         writel(val, pmc_base + PMC_SLEEP_CFG);
1925
1926         /* turn off pad detectors */
1927         val = readl(pmc_base + PMC_USB_AO);
1928         val |= (STROBE_VAL_PD_P0 | DATA_VAL_PD_P0);
1929         writel(val, pmc_base + PMC_USB_AO);
1930
1931         phy->remote_wakeup = false;
1932 }
1933
1934 static bool uhsic_phy_remotewake_detected(struct tegra_usb_phy *phy)
1935 {
1936         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1937         void __iomem *base = phy->regs;
1938         u32 val;
1939
1940         val = readl(base + UHSIC_PMC_WAKEUP0);
1941         if (val & EVENT_INT_ENB) {
1942                 val = readl(pmc_base + UTMIP_UHSIC_STATUS);
1943                 if (UHSIC_WAKE_ALARM & val) {
1944                         val = readl(pmc_base + PMC_SLEEP_CFG);
1945                         val &= ~UHSIC_WAKE_VAL(0x0);
1946                         val |= UHSIC_WAKE_VAL(WAKE_VAL_NONE);
1947                         writel(val, pmc_base + PMC_SLEEP_CFG);
1948
1949                         val = readl(pmc_base + PMC_TRIGGERS);
1950                         val |= UHSIC_CLR_WAKE_ALARM_P0 | UHSIC_CLR_WALK_PTR_P0;
1951                         writel(val, pmc_base + PMC_TRIGGERS);
1952
1953                         val = readl(base + UHSIC_PMC_WAKEUP0);
1954                         val &= ~EVENT_INT_ENB;
1955                         writel(val, base + UHSIC_PMC_WAKEUP0);
1956                         phy->remote_wakeup = true;
1957                         DBG("%s:PMC remote wakeup detected for HSIC\n", __func__);
1958                         return true;
1959                 }
1960         }
1961         return false;
1962 }
1963
1964 static int uhsic_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1965 {
1966         DBG("%s(%d)\n", __func__, __LINE__);
1967
1968         if (!remote_wakeup)
1969                 usb_phy_wait_for_sof(phy);
1970
1971         return 0;
1972 }
1973
1974 static int uhsic_phy_post_resume(struct tegra_usb_phy *phy)
1975 {
1976         unsigned long val;
1977         void __iomem *base = phy->regs;
1978
1979         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1980         val = readl(base + USB_TXFILLTUNING);
1981         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
1982                 val = USB_FIFO_TXFILL_THRES(0x10);
1983                 writel(val, base + USB_TXFILLTUNING);
1984         }
1985
1986         return 0;
1987 }
1988
1989 static void uhsic_phy_restore_start(struct tegra_usb_phy *phy)
1990 {
1991         unsigned long val;
1992         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1993         void __iomem *base = phy->regs;
1994
1995         val = readl(pmc_base + UTMIP_UHSIC_STATUS);
1996
1997         /* check whether we wake up from the remote resume */
1998         if (UHSIC_WALK_PTR_VAL & val) {
1999                 phy->remote_wakeup = true;
2000                 pr_info("%s: uhsic remote wakeup detected\n", __func__);
2001         } else {
2002                 if (!((UHSIC_STROBE_VAL_P0 | UHSIC_DATA_VAL_P0) & val)) {
2003                                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2004                 } else {
2005                         DBG("%s(%d): setting pretend connect\n", __func__, __LINE__);
2006                         val = readl(base + UHSIC_CMD_CFG0);
2007                         val |= UHSIC_PRETEND_CONNECT_DETECT;
2008                         writel(val, base + UHSIC_CMD_CFG0);
2009                 }
2010         }
2011 }
2012
2013 static void uhsic_phy_restore_end(struct tegra_usb_phy *phy)
2014 {
2015
2016         unsigned long val;
2017         void __iomem *base = phy->regs;
2018         int wait_time_us = 3000; /* FPR should be set by this time */
2019
2020         DBG("%s(%d)\n", __func__, __LINE__);
2021
2022         /* check whether we wake up from the remote resume */
2023         if (phy->remote_wakeup) {
2024                 /* wait until FPR bit is set automatically on remote resume */
2025                 do {
2026                         val = readl(base + USB_PORTSC);
2027                         udelay(1);
2028                         if (wait_time_us == 0) {
2029                                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2030                                 uhsic_phy_post_resume(phy);
2031                                 return;
2032                         }
2033                         wait_time_us--;
2034                 } while (!(val & USB_PORTSC_RESUME));
2035                 /* wait for 25 ms to port resume complete */
2036                 msleep(25);
2037                 /* disable PMC master control */
2038                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2039
2040                 /* Clear PCI and SRI bits to avoid an interrupt upon resume */
2041                 val = readl(base + USB_USBSTS);
2042                 writel(val, base + USB_USBSTS);
2043                 /* wait to avoid SOF if there is any */
2044                 if (usb_phy_reg_status_wait(base + USB_USBSTS,
2045                         USB_USBSTS_SRI, USB_USBSTS_SRI, 2500)) {
2046                         pr_warn("%s: timeout waiting for SOF\n", __func__);
2047                 }
2048                 uhsic_phy_post_resume(phy);
2049         } else {
2050                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2051         }
2052
2053         /* Set RUN bit */
2054         val = readl(base + USB_USBCMD);
2055         val |= USB_USBCMD_RS;
2056         writel(val, base + USB_USBCMD);
2057         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2058                                                  USB_USBCMD_RS, 2000)) {
2059                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2060                 return;
2061         }
2062 }
2063
2064 static int uhsic_phy_open(struct tegra_usb_phy *phy)
2065 {
2066         unsigned long parent_rate;
2067         int i;
2068
2069         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2070         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
2071         for (i = 0; i < ARRAY_SIZE(uhsic_freq_table); i++) {
2072                 if (uhsic_freq_table[i].freq == parent_rate) {
2073                         phy->freq = &uhsic_freq_table[i];
2074                         break;
2075                 }
2076         }
2077         if (!phy->freq) {
2078                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
2079                 return -EINVAL;
2080         }
2081
2082         uhsic_powerup_pmc_wake_detect(phy);
2083
2084         return 0;
2085 }
2086
2087 static int uhsic_phy_irq(struct tegra_usb_phy *phy)
2088 {
2089         usb_phy_fence_read(phy);
2090         /* check if there is any remote wake event */
2091         if (uhsic_phy_remotewake_detected(phy))
2092                 pr_info("%s: uhsic remote wake detected\n", __func__);
2093         return IRQ_HANDLED;
2094 }
2095
2096 static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
2097 {
2098         unsigned long val;
2099         void __iomem *base = phy->regs;
2100         struct tegra_hsic_config *config = &phy->pdata->u_cfg.hsic;
2101
2102         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2103
2104         if (phy->phy_clk_on) {
2105                 DBG("%s(%d) inst:[%d] phy clk is already On\n",
2106                                         __func__, __LINE__, phy->inst);
2107                 return 0;
2108         }
2109
2110         val = readl(base + UHSIC_PADS_CFG1);
2111         val &= ~(UHSIC_PD_BG | UHSIC_PD_TRK | UHSIC_PD_RX |
2112                         UHSIC_PD_ZI | UHSIC_RPD_DATA | UHSIC_RPD_STROBE);
2113         val |= (UHSIC_RX_SEL | UHSIC_PD_TX);
2114         writel(val, base + UHSIC_PADS_CFG1);
2115
2116         val = readl(base + USB_SUSP_CTRL);
2117         val |= UHSIC_RESET;
2118         writel(val, base + USB_SUSP_CTRL);
2119         udelay(1);
2120
2121         val = readl(base + USB_SUSP_CTRL);
2122         val |= UHSIC_PHY_ENABLE;
2123         writel(val, base + USB_SUSP_CTRL);
2124
2125         val = readl(base + UHSIC_HSRX_CFG0);
2126         val |= UHSIC_IDLE_WAIT(config->idle_wait_delay);
2127         val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(config->elastic_underrun_limit);
2128         val |= UHSIC_ELASTIC_OVERRUN_LIMIT(config->elastic_overrun_limit);
2129         writel(val, base + UHSIC_HSRX_CFG0);
2130
2131         val = readl(base + UHSIC_HSRX_CFG1);
2132         val |= UHSIC_HS_SYNC_START_DLY(config->sync_start_delay);
2133         writel(val, base + UHSIC_HSRX_CFG1);
2134
2135         /* WAR HSIC TX */
2136         val = readl(base + UHSIC_TX_CFG0);
2137         val &= ~UHSIC_HS_READY_WAIT_FOR_VALID;
2138         writel(val, base + UHSIC_TX_CFG0);
2139
2140         val = readl(base + UHSIC_MISC_CFG0);
2141         val |= UHSIC_SUSPEND_EXIT_ON_EDGE;
2142         /* Disable generic bus reset, to allow AP30 specific bus reset*/
2143         val |= UHSIC_DISABLE_BUSRESET;
2144         writel(val, base + UHSIC_MISC_CFG0);
2145
2146         val = readl(base + UHSIC_MISC_CFG1);
2147         val |= UHSIC_PLLU_STABLE_COUNT(phy->freq->stable_count);
2148         writel(val, base + UHSIC_MISC_CFG1);
2149
2150         val = readl(base + UHSIC_PLL_CFG1);
2151         val |= UHSIC_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
2152         val |= UHSIC_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count);
2153         writel(val, base + UHSIC_PLL_CFG1);
2154
2155         val = readl(base + USB_SUSP_CTRL);
2156         val &= ~(UHSIC_RESET);
2157         writel(val, base + USB_SUSP_CTRL);
2158         udelay(1);
2159
2160         val = readl(base + UHSIC_PADS_CFG1);
2161         val &= ~(UHSIC_PD_TX);
2162         writel(val, base + UHSIC_PADS_CFG1);
2163
2164         val = readl(base + USB_USBMODE);
2165         val |= USB_USBMODE_HOST;
2166         writel(val, base + USB_USBMODE);
2167
2168         /* Change the USB controller PHY type to HSIC */
2169         val = readl(base + HOSTPC1_DEVLC);
2170         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
2171         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2172         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
2173         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2174         val &= ~HOSTPC1_DEVLC_STS;
2175         writel(val, base + HOSTPC1_DEVLC);
2176
2177         val = readl(base + USB_TXFILLTUNING);
2178         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
2179                 val = USB_FIFO_TXFILL_THRES(0x10);
2180                 writel(val, base + USB_TXFILLTUNING);
2181         }
2182
2183         val = readl(base + USB_PORTSC);
2184         val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN);
2185         writel(val, base + USB_PORTSC);
2186
2187         val = readl(base + UHSIC_PADS_CFG0);
2188         val &= ~(UHSIC_TX_RTUNEN);
2189         /* set Rtune impedance to 50 ohm */
2190         val |= UHSIC_TX_RTUNE(8);
2191         writel(val, base + UHSIC_PADS_CFG0);
2192
2193         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
2194                                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500)) {
2195                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2196                 return -ETIMEDOUT;
2197         }
2198
2199         phy->phy_clk_on = true;
2200         phy->hw_accessible = true;
2201
2202         if (phy->pmc_sleepwalk) {
2203                 DBG("%s(%d) inst:[%d] restore phy\n", __func__, __LINE__,
2204                                         phy->inst);
2205                 uhsic_phy_restore_start(phy);
2206                 usb_phy_bringup_host_controller(phy);
2207                 uhsic_phy_restore_end(phy);
2208                 phy->pmc_sleepwalk = false;
2209         }
2210
2211         return 0;
2212 }
2213
2214 static int uhsic_phy_power_off(struct tegra_usb_phy *phy)
2215 {
2216         unsigned long val;
2217         void __iomem *base = phy->regs;
2218
2219         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2220         if (!phy->phy_clk_on) {
2221                 DBG("%s(%d) inst:[%d] phy clk is already off\n",
2222                                         __func__, __LINE__, phy->inst);
2223                 return 0;
2224         }
2225
2226         phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
2227                         HOSTPC1_DEVLC_PSPD_MASK;
2228
2229         /* Disable interrupts */
2230         writel(0, base + USB_USBINTR);
2231
2232         if (phy->pmc_sleepwalk == false) {
2233                 uhsic_setup_pmc_wake_detect(phy);
2234                 phy->pmc_sleepwalk = true;
2235         }
2236
2237         val = readl(base + HOSTPC1_DEVLC);
2238         val |= HOSTPC1_DEVLC_PHCD;
2239         writel(val, base + HOSTPC1_DEVLC);
2240
2241         /* Remove power downs for HSIC from PADS CFG1 register */
2242         val = readl(base + UHSIC_PADS_CFG1);
2243         val |= (UHSIC_PD_BG |UHSIC_PD_TRK | UHSIC_PD_RX |
2244                         UHSIC_PD_ZI | UHSIC_PD_TX);
2245         writel(val, base + UHSIC_PADS_CFG1);
2246         phy->phy_clk_on = false;
2247         phy->hw_accessible = false;
2248
2249         return 0;
2250 }
2251
2252 int uhsic_phy_bus_port_power(struct tegra_usb_phy *phy)
2253 {
2254         unsigned long val;
2255         void __iomem *base = phy->regs;
2256
2257         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2258
2259         val = readl(base + USB_USBMODE);
2260         val |= USB_USBMODE_HOST;
2261         writel(val, base + USB_USBMODE);
2262
2263         /* Change the USB controller PHY type to HSIC */
2264         val = readl(base + HOSTPC1_DEVLC);
2265         val &= ~(HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK));
2266         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2267         val &= ~(HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK));
2268         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2269         writel(val, base + HOSTPC1_DEVLC);
2270
2271         val = readl(base + UHSIC_MISC_CFG0);
2272         val |= UHSIC_DETECT_SHORT_CONNECT;
2273         writel(val, base + UHSIC_MISC_CFG0);
2274         udelay(1);
2275
2276         val = readl(base + UHSIC_MISC_CFG0);
2277         val |= UHSIC_FORCE_XCVR_MODE;
2278         writel(val, base + UHSIC_MISC_CFG0);
2279
2280         val = readl(base + UHSIC_PADS_CFG1);
2281         val &= ~UHSIC_RPD_STROBE;
2282         writel(val, base + UHSIC_PADS_CFG1);
2283
2284         if (phy->pdata->ops && phy->pdata->ops->port_power)
2285                 phy->pdata->ops->port_power();
2286
2287         if (usb_phy_reg_status_wait(base + UHSIC_STAT_CFG0,
2288                         UHSIC_CONNECT_DETECT, UHSIC_CONNECT_DETECT, 25000)) {
2289                 pr_err("%s: timeout waiting for UHSIC_CONNECT_DETECT\n",
2290                                                                 __func__);
2291                 return -ETIMEDOUT;
2292         }
2293
2294         return 0;
2295 }
2296
2297 static int uhsic_phy_bus_reset(struct tegra_usb_phy *phy)
2298 {
2299         unsigned long val;
2300         void __iomem *base = phy->regs;
2301
2302         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2303
2304         /* Change the USB controller PHY type to HSIC */
2305         val = readl(base + HOSTPC1_DEVLC);
2306         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
2307         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2308         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
2309         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2310         val &= ~HOSTPC1_DEVLC_STS;
2311         writel(val, base + HOSTPC1_DEVLC);
2312         /* wait here, otherwise HOSTPC1_DEVLC_PSPD will timeout */
2313         mdelay(5);
2314
2315         val = readl(base + USB_PORTSC);
2316         val |= USB_PORTSC_PTC(5);
2317         writel(val, base + USB_PORTSC);
2318         udelay(2);
2319
2320         val = readl(base + USB_PORTSC);
2321         val &= ~(USB_PORTSC_PTC(~0));
2322         writel(val, base + USB_PORTSC);
2323         udelay(2);
2324
2325         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_LS(0),
2326                                                  0, 2000)) {
2327                 pr_err("%s: timeout waiting for USB_PORTSC_LS\n", __func__);
2328                 return -ETIMEDOUT;
2329         }
2330
2331         /* Poll until CCS is enabled */
2332         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
2333                                                  USB_PORTSC_CCS, 2000)) {
2334                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
2335                 return -ETIMEDOUT;
2336         }
2337
2338         if (usb_phy_reg_status_wait(base + HOSTPC1_DEVLC,
2339                         HOSTPC1_DEVLC_PSPD(2),
2340                         HOSTPC1_DEVLC_PSPD(2), 2000) < 0) {
2341                 pr_err("%s: timeout waiting hsic high speed configuration\n",
2342                                                 __func__);
2343                         return -ETIMEDOUT;
2344         }
2345
2346         val = readl(base + USB_USBCMD);
2347         val &= ~USB_USBCMD_RS;
2348         writel(val, base + USB_USBCMD);
2349
2350         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
2351                                                  USB_USBSTS_HCH, 2000)) {
2352                 pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
2353                 return -ETIMEDOUT;
2354         }
2355
2356         val = readl(base + UHSIC_PADS_CFG1);
2357         val &= ~UHSIC_RPU_STROBE;
2358         val |= UHSIC_RPD_STROBE;
2359         writel(val, base + UHSIC_PADS_CFG1);
2360
2361         mdelay(50);
2362
2363         val = readl(base + UHSIC_PADS_CFG1);
2364         val &= ~UHSIC_RPD_STROBE;
2365         val |= UHSIC_RPU_STROBE;
2366         writel(val, base + UHSIC_PADS_CFG1);
2367
2368         val = readl(base + USB_USBCMD);
2369         val |= USB_USBCMD_RS;
2370         writel(val, base + USB_USBCMD);
2371
2372         val = readl(base + UHSIC_PADS_CFG1);
2373         val &= ~UHSIC_RPU_STROBE;
2374         writel(val, base + UHSIC_PADS_CFG1);
2375
2376         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2377                                                  USB_USBCMD_RS, 2000)) {
2378                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2379                 return -ETIMEDOUT;
2380         }
2381
2382         return 0;
2383 }
2384
2385 int uhsic_phy_resume(struct tegra_usb_phy *phy)
2386 {
2387         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2388
2389         return 0;
2390 }
2391
2392 static void ulpi_set_trimmer(struct tegra_usb_phy *phy)
2393 {
2394         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2395         void __iomem *base = phy->regs;
2396         unsigned long val;
2397
2398         val = ULPI_DATA_TRIMMER_SEL(config->data_trimmer);
2399         val |= ULPI_STPDIRNXT_TRIMMER_SEL(config->stpdirnxt_trimmer);
2400         val |= ULPI_DIR_TRIMMER_SEL(config->dir_trimmer);
2401         writel(val, base + ULPI_TIMING_CTRL_1);
2402         udelay(10);
2403
2404         val |= ULPI_DATA_TRIMMER_LOAD;
2405         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
2406         val |= ULPI_DIR_TRIMMER_LOAD;
2407         writel(val, base + ULPI_TIMING_CTRL_1);
2408 }
2409
2410 static void reset_utmip_uhsic(void __iomem *base)
2411 {
2412         unsigned long val;
2413
2414         val = readl(base + USB_SUSP_CTRL);
2415         val |= UHSIC_RESET;
2416         writel(val, base + USB_SUSP_CTRL);
2417
2418         val = readl(base + USB_SUSP_CTRL);
2419         val |= UTMIP_RESET;
2420         writel(val, base + USB_SUSP_CTRL);
2421 }
2422
2423 static void ulpi_set_host(void __iomem *base)
2424 {
2425         unsigned long val;
2426
2427         val = readl(base + USB_USBMODE);
2428         val &= ~USB_USBMODE_MASK;
2429         val |= USB_USBMODE_HOST;
2430         writel(val, base + USB_USBMODE);
2431
2432         val = readl(base + HOSTPC1_DEVLC);
2433         val |= HOSTPC1_DEVLC_PTS(2);
2434         writel(val, base + HOSTPC1_DEVLC);
2435 }
2436
2437 static inline void ulpi_pinmux_bypass(struct tegra_usb_phy *phy, bool enable)
2438 {
2439         unsigned long val;
2440         void __iomem *base = phy->regs;
2441
2442         val = readl(base + ULPI_TIMING_CTRL_0);
2443
2444         if (enable)
2445                 val |= ULPI_OUTPUT_PINMUX_BYP;
2446         else
2447                 val &= ~ULPI_OUTPUT_PINMUX_BYP;
2448
2449         writel(val, base + ULPI_TIMING_CTRL_0);
2450 }
2451
2452 static inline void ulpi_null_phy_set_tristate(bool enable)
2453 {
2454 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2455         int tristate = (enable) ? TEGRA_TRI_TRISTATE : TEGRA_TRI_NORMAL;
2456
2457         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA0, tristate);
2458         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA1, tristate);
2459         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA2, tristate);
2460         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA3, tristate);
2461         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA4, tristate);
2462         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA5, tristate);
2463         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA6, tristate);
2464         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA7, tristate);
2465         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_NXT, tristate);
2466
2467         if (enable)
2468                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR, tristate);
2469 #endif
2470 }
2471
2472 static void ulpi_null_phy_obs_read(void)
2473 {
2474         static void __iomem *apb_misc;
2475         unsigned slv0_obs, s2s_obs;
2476
2477         if (!apb_misc)
2478                 apb_misc = ioremap(TEGRA_APB_MISC_BASE, TEGRA_APB_MISC_SIZE);
2479
2480         writel(0x80d1003c, apb_misc + APB_MISC_GP_OBSCTRL_0);
2481         slv0_obs = readl(apb_misc + APB_MISC_GP_OBSDATA_0);
2482
2483         writel(0x80d10040, apb_misc + APB_MISC_GP_OBSCTRL_0);
2484         s2s_obs = readl(apb_misc + APB_MISC_GP_OBSDATA_0);
2485
2486         pr_debug("slv0 obs: %08x\ns2s obs: %08x\n", slv0_obs, s2s_obs);
2487 }
2488
2489 static const struct gpio ulpi_gpios[] = {
2490         {ULPI_STP, GPIOF_IN, "ULPI_STP"},
2491         {ULPI_DIR, GPIOF_OUT_INIT_LOW, "ULPI_DIR"},
2492         {ULPI_D0, GPIOF_OUT_INIT_LOW, "ULPI_D0"},
2493         {ULPI_D1, GPIOF_OUT_INIT_LOW, "ULPI_D1"},
2494 };
2495
2496 static int ulpi_null_phy_open(struct tegra_usb_phy *phy)
2497 {
2498         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2499         int ret;
2500
2501         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2502
2503         ret = gpio_request_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
2504         if (ret)
2505                 return ret;
2506
2507         if (gpio_is_valid(config->phy_restore_gpio)) {
2508                 ret = gpio_request(config->phy_restore_gpio, "phy_restore");
2509                 if (ret)
2510                         goto err_gpio_free;
2511
2512                 gpio_direction_input(config->phy_restore_gpio);
2513         }
2514
2515         tegra_periph_reset_assert(phy->ctrlr_clk);
2516         udelay(10);
2517         tegra_periph_reset_deassert(phy->ctrlr_clk);
2518
2519         return 0;
2520
2521 err_gpio_free:
2522         gpio_free_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
2523         return ret;
2524 }
2525
2526 static void ulpi_null_phy_close(struct tegra_usb_phy *phy)
2527 {
2528         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2529
2530         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2531
2532         if (gpio_is_valid(config->phy_restore_gpio))
2533                 gpio_free(config->phy_restore_gpio);
2534
2535         gpio_free_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
2536 }
2537
2538 static int ulpi_null_phy_power_off(struct tegra_usb_phy *phy)
2539 {
2540         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2541
2542         if (!phy->phy_clk_on) {
2543                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
2544                                                         __LINE__, phy->inst);
2545                 return 0;
2546         }
2547
2548         phy->phy_clk_on = false;
2549         phy->hw_accessible = false;
2550         ulpi_null_phy_set_tristate(true);
2551         return 0;
2552 }
2553
2554 /* NOTE: this function must be called before ehci reset */
2555 static int ulpi_null_phy_init(struct tegra_usb_phy *phy)
2556 {
2557         unsigned long val;
2558         void __iomem *base = phy->regs;
2559
2560         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2561         val = readl(base + ULPIS2S_CTRL);
2562         val |=  ULPIS2S_SLV0_CLAMP_XMIT;
2563         writel(val, base + ULPIS2S_CTRL);
2564
2565         val = readl(base + USB_SUSP_CTRL);
2566         val |= ULPIS2S_SLV0_RESET;
2567         writel(val, base + USB_SUSP_CTRL);
2568         udelay(10);
2569
2570         return 0;
2571 }
2572
2573 static int ulpi_null_phy_irq(struct tegra_usb_phy *phy)
2574 {
2575         usb_phy_fence_read(phy);
2576         return IRQ_HANDLED;
2577 }
2578
2579 /* NOTE: this function must be called after ehci reset */
2580 static int ulpi_null_phy_cmd_reset(struct tegra_usb_phy *phy)
2581 {
2582         unsigned long val;
2583         void __iomem *base = phy->regs;
2584
2585         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2586         ulpi_set_host(base);
2587
2588         /* remove slave0 reset */
2589         val = readl(base + USB_SUSP_CTRL);
2590         val &= ~ULPIS2S_SLV0_RESET;
2591         writel(val, base + USB_SUSP_CTRL);
2592
2593         val = readl(base + ULPIS2S_CTRL);
2594         val &=  ~ULPIS2S_SLV0_CLAMP_XMIT;
2595         writel(val, base + ULPIS2S_CTRL);
2596         udelay(10);
2597
2598         return 0;
2599 }
2600
2601 static int ulpi_null_phy_restore(struct tegra_usb_phy *phy)
2602 {
2603         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2604         unsigned long timeout;
2605         int ulpi_stp = ULPI_STP;
2606
2607         if (gpio_is_valid(config->phy_restore_gpio))
2608                 ulpi_stp = config->phy_restore_gpio;
2609
2610         /* disable ULPI pinmux bypass */
2611         ulpi_pinmux_bypass(phy, false);
2612
2613         /* driving linstate by GPIO */
2614         gpio_set_value(ULPI_D0, 0);
2615         gpio_set_value(ULPI_D1, 0);
2616
2617         /* driving DIR high */
2618         gpio_set_value(ULPI_DIR, 1);
2619
2620         /* remove ULPI tristate */
2621         ulpi_null_phy_set_tristate(false);
2622
2623         /* wait for STP high */
2624         timeout = jiffies + msecs_to_jiffies(25);
2625
2626         while (!gpio_get_value(ulpi_stp)) {
2627                 if (time_after(jiffies, timeout)) {
2628                         pr_warn("phy restore timeout\n");
2629                         return 1;
2630                 }
2631         }
2632
2633         return 0;
2634 }
2635
2636 static int ulpi_null_phy_lp0_resume(struct tegra_usb_phy *phy)
2637 {
2638         unsigned long val;
2639         void __iomem *base = phy->regs;
2640
2641         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2642         ulpi_null_phy_init(phy);
2643
2644         val = readl(base + USB_USBCMD);
2645         val |= USB_CMD_RESET;
2646         writel(val, base + USB_USBCMD);
2647
2648         if (usb_phy_reg_status_wait(base + USB_USBCMD,
2649                 USB_CMD_RESET, 0, 2500) < 0) {
2650                 pr_err("%s: timeout waiting for reset\n", __func__);
2651         }
2652
2653         ulpi_null_phy_cmd_reset(phy);
2654
2655         val = readl(base + USB_USBCMD);
2656         val |= USB_USBCMD_RS;
2657         writel(val, base + USB_USBCMD);
2658         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2659                                                  USB_USBCMD_RS, 2000)) {
2660                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2661                 return -ETIMEDOUT;
2662         }
2663
2664         /* Enable Port Power */
2665         val = readl(base + USB_PORTSC);
2666         val |= USB_PORTSC_PP;
2667         writel(val, base + USB_PORTSC);
2668         udelay(10);
2669
2670         ulpi_null_phy_restore(phy);
2671
2672         return 0;
2673 }
2674
2675 static int ulpi_null_phy_power_on(struct tegra_usb_phy *phy)
2676 {
2677         unsigned long val;
2678         void __iomem *base = phy->regs;
2679         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2680
2681         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2682         if (phy->phy_clk_on) {
2683                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
2684                                                         __LINE__, phy->inst);
2685                 return 0;
2686         }
2687         reset_utmip_uhsic(base);
2688
2689         /* remove ULPI PADS CLKEN reset */
2690         val = readl(base + USB_SUSP_CTRL);
2691         val &= ~ULPI_PADS_CLKEN_RESET;
2692         writel(val, base + USB_SUSP_CTRL);
2693         udelay(10);
2694
2695         val = readl(base + ULPI_TIMING_CTRL_0);
2696         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
2697         writel(val, base + ULPI_TIMING_CTRL_0);
2698
2699         val = readl(base + USB_SUSP_CTRL);
2700         val |= ULPI_PHY_ENABLE;
2701         writel(val, base + USB_SUSP_CTRL);
2702         udelay(10);
2703
2704         /* set timming parameters */
2705         val = readl(base + ULPI_TIMING_CTRL_0);
2706         val |= ULPI_SHADOW_CLK_LOOPBACK_EN;
2707         val &= ~ULPI_SHADOW_CLK_SEL;
2708         val &= ~ULPI_LBK_PAD_EN;
2709         val |= ULPI_SHADOW_CLK_DELAY(config->shadow_clk_delay);
2710         val |= ULPI_CLOCK_OUT_DELAY(config->clock_out_delay);
2711         val |= ULPI_LBK_PAD_E_INPUT_OR;
2712         writel(val, base + ULPI_TIMING_CTRL_0);
2713
2714         writel(0, base + ULPI_TIMING_CTRL_1);
2715         udelay(10);
2716
2717         /* start internal 60MHz clock */
2718         val = readl(base + ULPIS2S_CTRL);
2719         val |= ULPIS2S_ENA;
2720         val |= ULPIS2S_SUPPORT_DISCONNECT;
2721         val |= ULPIS2S_SPARE((phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) ? 3 : 1);
2722         val |= ULPIS2S_PLLU_MASTER_BLASTER60;
2723         writel(val, base + ULPIS2S_CTRL);
2724
2725         /* select ULPI_CORE_CLK_SEL to SHADOW_CLK */
2726         val = readl(base + ULPI_TIMING_CTRL_0);
2727         val |= ULPI_CORE_CLK_SEL;
2728         writel(val, base + ULPI_TIMING_CTRL_0);
2729         udelay(10);
2730
2731         /* enable ULPI null phy clock - can't set the trimmers before this */
2732         val = readl(base + ULPI_TIMING_CTRL_0);
2733         val |= ULPI_CLK_OUT_ENA;
2734         writel(val, base + ULPI_TIMING_CTRL_0);
2735         udelay(10);
2736
2737         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
2738                                                  USB_PHY_CLK_VALID, 2500)) {
2739                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2740                 return -ETIMEDOUT;
2741         }
2742
2743         /* set ULPI trimmers */
2744         ulpi_set_trimmer(phy);
2745
2746         ulpi_set_host(base);
2747
2748         /* remove slave0 reset */
2749         val = readl(base + USB_SUSP_CTRL);
2750         val &= ~ULPIS2S_SLV0_RESET;
2751         writel(val, base + USB_SUSP_CTRL);
2752
2753         /* remove slave1 and line reset */
2754         val = readl(base + USB_SUSP_CTRL);
2755         val &= ~ULPIS2S_SLV1_RESET;
2756         val &= ~ULPIS2S_LINE_RESET;
2757
2758         /* remove ULPI PADS reset */
2759         val &= ~ULPI_PADS_RESET;
2760         writel(val, base + USB_SUSP_CTRL);
2761
2762         if (!phy->ulpi_clk_padout_ena) {
2763                 val = readl(base + ULPI_TIMING_CTRL_0);
2764                 val |= ULPI_CLK_PADOUT_ENA;
2765                 writel(val, base + ULPI_TIMING_CTRL_0);
2766                 phy->ulpi_clk_padout_ena = true;
2767         } else {
2768                 if (!readl(base + USB_ASYNCLISTADDR))
2769                         ulpi_null_phy_lp0_resume(phy);
2770         }
2771         udelay(10);
2772
2773         phy->phy_clk_on = true;
2774         phy->hw_accessible = true;
2775
2776         return 0;
2777 }
2778
2779 static int ulpi_null_phy_pre_resume(struct tegra_usb_phy *phy,
2780                                     bool remote_wakeup)
2781 {
2782         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2783         ulpi_null_phy_obs_read();
2784         usb_phy_wait_for_sof(phy);
2785         ulpi_null_phy_obs_read();
2786         return 0;
2787 }
2788
2789 static int ulpi_null_phy_post_resume(struct tegra_usb_phy *phy)
2790 {
2791         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2792         ulpi_null_phy_obs_read();
2793         return 0;
2794 }
2795
2796 static int ulpi_null_phy_resume(struct tegra_usb_phy *phy)
2797 {
2798         unsigned long val;
2799         void __iomem *base = phy->regs;
2800
2801         if (!readl(base + USB_ASYNCLISTADDR)) {
2802                 /* enable ULPI CLK output pad */
2803                 val = readl(base + ULPI_TIMING_CTRL_0);
2804                 val |= ULPI_CLK_PADOUT_ENA;
2805                 writel(val, base + ULPI_TIMING_CTRL_0);
2806
2807                 /* enable ULPI pinmux bypass */
2808                 ulpi_pinmux_bypass(phy, true);
2809                 udelay(5);
2810 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2811                 /* remove DIR tristate */
2812                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR,
2813                                           TEGRA_TRI_NORMAL);
2814 #endif
2815         }
2816         return 0;
2817 }
2818
2819
2820
2821 static struct tegra_usb_phy_ops utmi_phy_ops = {
2822         .open           = utmi_phy_open,
2823         .close          = utmi_phy_close,
2824         .irq            = utmi_phy_irq,
2825         .power_on       = utmi_phy_power_on,
2826         .power_off      = utmi_phy_power_off,
2827         .pre_resume = utmi_phy_pre_resume,
2828         .resume = utmi_phy_resume,
2829         .post_resume    = utmi_phy_post_resume,
2830         .charger_detect = utmi_phy_charger_detect,
2831 };
2832
2833 static struct tegra_usb_phy_ops uhsic_phy_ops = {
2834         .open           = uhsic_phy_open,
2835         .irq            = uhsic_phy_irq,
2836         .power_on       = uhsic_phy_power_on,
2837         .power_off      = uhsic_phy_power_off,
2838         .pre_resume = uhsic_phy_pre_resume,
2839         .resume = uhsic_phy_resume,
2840         .post_resume = uhsic_phy_post_resume,
2841         .port_power = uhsic_phy_bus_port_power,
2842         .bus_reset      = uhsic_phy_bus_reset,
2843 };
2844
2845 static struct tegra_usb_phy_ops ulpi_null_phy_ops = {
2846         .open           = ulpi_null_phy_open,
2847         .close          = ulpi_null_phy_close,
2848         .init           = ulpi_null_phy_init,
2849         .irq            = ulpi_null_phy_irq,
2850         .power_on       = ulpi_null_phy_power_on,
2851         .power_off      = ulpi_null_phy_power_off,
2852         .pre_resume = ulpi_null_phy_pre_resume,
2853         .resume = ulpi_null_phy_resume,
2854         .post_resume = ulpi_null_phy_post_resume,
2855         .reset          = ulpi_null_phy_cmd_reset,
2856 };
2857
2858 static struct tegra_usb_phy_ops ulpi_link_phy_ops;
2859 static struct tegra_usb_phy_ops icusb_phy_ops;
2860
2861 static struct tegra_usb_phy_ops *phy_ops[] = {
2862         [TEGRA_USB_PHY_INTF_UTMI] = &utmi_phy_ops,
2863         [TEGRA_USB_PHY_INTF_ULPI_LINK] = &ulpi_link_phy_ops,
2864         [TEGRA_USB_PHY_INTF_ULPI_NULL] = &ulpi_null_phy_ops,
2865         [TEGRA_USB_PHY_INTF_HSIC] = &uhsic_phy_ops,
2866         [TEGRA_USB_PHY_INTF_ICUSB] = &icusb_phy_ops,
2867 };
2868
2869 int tegra3_usb_phy_init_ops(struct tegra_usb_phy *phy)
2870 {
2871         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2872
2873         phy->ops = phy_ops[phy->pdata->phy_intf];
2874
2875         /* FIXME: uncommenting below line to make USB host mode fail*/
2876         /* usb_phy_power_down_pmc(); */
2877
2878         return 0;
2879 }