fcd8b5a5ee4c05e1e9ef46ba8861d3dd80a1aa80
[linux-2.6.git] / arch / arm / mach-tegra / tegra3_usb_phy.c
1 /*
2  * arch/arm/mach-tegra/tegra3_usb_phy.c
3  *
4  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
5  *
6  *
7  * This software is licensed under the terms of the GNU General Public
8  * License version 2, as published by the Free Software Foundation, and
9  * may be copied, distributed, and modified under those terms.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17 #include <linux/resource.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/slab.h>
21 #include <linux/err.h>
22 #include <linux/platform_device.h>
23 #include <linux/io.h>
24 #include <linux/gpio.h>
25 #include <linux/interrupt.h>
26 #include <linux/clk.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <mach/iomap.h>
30 #include <mach/pinmux.h>
31 #include <mach/pinmux-tegra30.h>
32 #include "tegra_usb_phy.h"
33 #include "fuse.h"
34
35 #define USB_USBCMD              0x130
36 #define   USB_USBCMD_RS         (1 << 0)
37 #define   USB_CMD_RESET (1<<1)
38
39 #define USB_USBSTS              0x134
40 #define   USB_USBSTS_PCI        (1 << 2)
41 #define   USB_USBSTS_SRI        (1 << 7)
42 #define   USB_USBSTS_HCH        (1 << 12)
43
44 #define USB_USBINTR             0x138
45
46 #define USB_TXFILLTUNING        0x154
47 #define USB_FIFO_TXFILL_THRES(x)   (((x) & 0x1f) << 16)
48 #define USB_FIFO_TXFILL_MASK    0x1f0000
49
50 #define USB_ASYNCLISTADDR       0x148
51
52 #define ICUSB_CTRL              0x15c
53
54 #define USB_PORTSC              0x174
55 #define   USB_PORTSC_WKOC       (1 << 22)
56 #define   USB_PORTSC_WKDS       (1 << 21)
57 #define   USB_PORTSC_WKCN       (1 << 20)
58 #define   USB_PORTSC_PTC(x)     (((x) & 0xf) << 16)
59 #define   USB_PORTSC_PP (1 << 12)
60 #define   USB_PORTSC_LS(x) (((x) & 0x3) << 10)
61 #define   USB_PORTSC_SUSP       (1 << 7)
62 #define   USB_PORTSC_RESUME     (1 << 6)
63 #define   USB_PORTSC_OCC        (1 << 5)
64 #define   USB_PORTSC_PEC        (1 << 3)
65 #define   USB_PORTSC_PE         (1 << 2)
66 #define   USB_PORTSC_CSC        (1 << 1)
67 #define   USB_PORTSC_CCS        (1 << 0)
68 #define   USB_PORTSC_RWC_BITS (USB_PORTSC_CSC | USB_PORTSC_PEC | USB_PORTSC_OCC)
69
70 #define HOSTPC1_DEVLC           0x1b4
71 #define   HOSTPC1_DEVLC_PHCD            (1 << 22)
72 #define   HOSTPC1_DEVLC_PTS(x)          (((x) & 0x7) << 29)
73 #define   HOSTPC1_DEVLC_PTS_MASK        7
74 #define   HOSTPC1_DEVLC_PTS_HSIC        4
75 #define   HOSTPC1_DEVLC_STS             (1 << 28)
76 #define   HOSTPC1_DEVLC_PSPD(x)         (((x) & 0x3) << 25)
77 #define   HOSTPC1_DEVLC_PSPD_MASK       3
78 #define   HOSTPC1_DEVLC_PSPD_HIGH_SPEED 2
79
80 #define USB_USBMODE             0x1f8
81 #define   USB_USBMODE_MASK              (3 << 0)
82 #define   USB_USBMODE_HOST              (3 << 0)
83 #define   USB_USBMODE_DEVICE            (2 << 0)
84
85 #define USB_SUSP_CTRL           0x400
86 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
87 #define   USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
88 #define   USB_SUSP_CLR                  (1 << 5)
89 #define   USB_PHY_CLK_VALID             (1 << 7)
90 #define   USB_PHY_CLK_VALID_INT_ENB     (1 << 9)
91 #define   USB_PHY_CLK_VALID_INT_STS     (1 << 8)
92 #define   UTMIP_RESET                   (1 << 11)
93 #define   UTMIP_PHY_ENABLE              (1 << 12)
94 #define   ULPI_PHY_ENABLE               (1 << 13)
95 #define   UHSIC_RESET                   (1 << 14)
96 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
97 #define   UHSIC_PHY_ENABLE              (1 << 19)
98 #define   ULPIS2S_SLV0_RESET            (1 << 20)
99 #define   ULPIS2S_SLV1_RESET            (1 << 21)
100 #define   ULPIS2S_LINE_RESET            (1 << 22)
101 #define   ULPI_PADS_RESET               (1 << 23)
102 #define   ULPI_PADS_CLKEN_RESET         (1 << 24)
103
104 #define USB_PHY_VBUS_WAKEUP_ID  0x408
105 #define   VDAT_DET_INT_EN       (1 << 16)
106 #define   VDAT_DET_CHG_DET      (1 << 17)
107 #define   VDAT_DET_STS          (1 << 18)
108 #define   USB_ID_STATUS         (1 << 2)
109
110 #define ULPIS2S_CTRL            0x418
111 #define   ULPIS2S_ENA                   (1 << 0)
112 #define   ULPIS2S_SUPPORT_DISCONNECT    (1 << 2)
113 #define   ULPIS2S_PLLU_MASTER_BLASTER60 (1 << 3)
114 #define   ULPIS2S_SPARE(x)              (((x) & 0xF) << 8)
115 #define   ULPIS2S_FORCE_ULPI_CLK_OUT    (1 << 12)
116 #define   ULPIS2S_DISCON_DONT_CHECK_SE0 (1 << 13)
117 #define   ULPIS2S_SUPPORT_HS_KEEP_ALIVE (1 << 14)
118 #define   ULPIS2S_DISABLE_STP_PU        (1 << 15)
119 #define   ULPIS2S_SLV0_CLAMP_XMIT       (1 << 16)
120
121 #define ULPI_TIMING_CTRL_0      0x424
122 #define   ULPI_CLOCK_OUT_DELAY(x)       ((x) & 0x1F)
123 #define   ULPI_OUTPUT_PINMUX_BYP        (1 << 10)
124 #define   ULPI_CLKOUT_PINMUX_BYP        (1 << 11)
125 #define   ULPI_SHADOW_CLK_LOOPBACK_EN   (1 << 12)
126 #define   ULPI_SHADOW_CLK_SEL           (1 << 13)
127 #define   ULPI_CORE_CLK_SEL             (1 << 14)
128 #define   ULPI_SHADOW_CLK_DELAY(x)      (((x) & 0x1F) << 16)
129 #define   ULPI_LBK_PAD_EN               (1 << 26)
130 #define   ULPI_LBK_PAD_E_INPUT_OR       (1 << 27)
131 #define   ULPI_CLK_OUT_ENA              (1 << 28)
132 #define   ULPI_CLK_PADOUT_ENA           (1 << 29)
133
134 #define ULPI_TIMING_CTRL_1      0x428
135 #define   ULPI_DATA_TRIMMER_LOAD        (1 << 0)
136 #define   ULPI_DATA_TRIMMER_SEL(x)      (((x) & 0x7) << 1)
137 #define   ULPI_STPDIRNXT_TRIMMER_LOAD   (1 << 16)
138 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
139 #define   ULPI_DIR_TRIMMER_LOAD         (1 << 24)
140 #define   ULPI_DIR_TRIMMER_SEL(x)       (((x) & 0x7) << 25)
141
142 #define UTMIP_XCVR_CFG0         0x808
143 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
144 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
145 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
146 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
147 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
148 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
149 #define   UTMIP_XCVR_LSBIAS_SEL                 (1 << 21)
150 #define   UTMIP_XCVR_SETUP_MSB(x)               (((x) & 0x7) << 22)
151 #define   UTMIP_XCVR_HSSLEW_MSB(x)              (((x) & 0x7f) << 25)
152 #define   UTMIP_XCVR_MAX_OFFSET         2
153 #define   UTMIP_XCVR_SETUP_MAX_VALUE    0x7f
154 #define   UTMIP_XCVR_SETUP_MIN_VALUE    0
155 #define   XCVR_SETUP_MSB_CALIB(x) ((x) >> 4)
156
157 #define UTMIP_BIAS_CFG0         0x80c
158 #define   UTMIP_OTGPD                   (1 << 11)
159 #define   UTMIP_BIASPD                  (1 << 10)
160 #define   UTMIP_HSSQUELCH_LEVEL(x)      (((x) & 0x3) << 0)
161 #define   UTMIP_HSDISCON_LEVEL(x)       (((x) & 0x3) << 2)
162 #define   UTMIP_HSDISCON_LEVEL_MSB      (1 << 24)
163
164 #define UTMIP_HSRX_CFG0         0x810
165 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
166 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
167
168 #define UTMIP_HSRX_CFG1         0x814
169 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
170
171 #define UTMIP_TX_CFG0           0x820
172 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
173 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
174
175 #define UTMIP_DEBOUNCE_CFG0 0x82c
176 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
177
178 #define UTMIP_BAT_CHRG_CFG0 0x830
179 #define   UTMIP_PD_CHRG                 (1 << 0)
180 #define   UTMIP_ON_SINK_EN              (1 << 2)
181 #define   UTMIP_OP_SRC_EN               (1 << 3)
182
183 #define UTMIP_XCVR_CFG1         0x838
184 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
185 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
186 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
187 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
188
189 #define UTMIP_BIAS_CFG1         0x83c
190 #define   UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
191 #define   UTMIP_BIAS_PDTRK_POWERDOWN    (1 << 0)
192 #define   UTMIP_BIAS_PDTRK_POWERUP      (1 << 1)
193
194 #define UTMIP_MISC_CFG0         0x824
195 #define   UTMIP_DPDM_OBSERVE            (1 << 26)
196 #define   UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
197 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J   UTMIP_DPDM_OBSERVE_SEL(0xf)
198 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K   UTMIP_DPDM_OBSERVE_SEL(0xe)
199 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
200 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
201 #define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
202 #define   FORCE_PULLDN_DM       (1 << 8)
203 #define   FORCE_PULLDN_DP       (1 << 9)
204 #define   COMB_TERMS            (1 << 0)
205 #define   ALWAYS_FREE_RUNNING_TERMS (1 << 1)
206
207 #define UTMIP_SPARE_CFG0        0x834
208 #define   FUSE_SETUP_SEL                (1 << 3)
209 #define   FUSE_ATERM_SEL                (1 << 4)
210
211 #define UTMIP_PMC_WAKEUP0               0x84c
212 #define   EVENT_INT_ENB                 (1 << 0)
213
214 #define UHSIC_PMC_WAKEUP0               0xc34
215
216 #define UTMIP_BIAS_STS0                 0x840
217 #define   UTMIP_RCTRL_VAL(x)            (((x) & 0xffff) << 0)
218 #define   UTMIP_TCTRL_VAL(x)            (((x) & (0xffff << 16)) >> 16)
219
220 #define UHSIC_PLL_CFG1                          0xc04
221 #define   UHSIC_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
222 #define   UHSIC_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 14)
223
224 #define UHSIC_HSRX_CFG0                         0xc08
225 #define   UHSIC_ELASTIC_UNDERRUN_LIMIT(x)       (((x) & 0x1f) << 2)
226 #define   UHSIC_ELASTIC_OVERRUN_LIMIT(x)        (((x) & 0x1f) << 8)
227 #define   UHSIC_IDLE_WAIT(x)                    (((x) & 0x1f) << 13)
228
229 #define UHSIC_HSRX_CFG1                         0xc0c
230 #define   UHSIC_HS_SYNC_START_DLY(x)            (((x) & 0x1f) << 1)
231
232 #define UHSIC_TX_CFG0                           0xc10
233 #define UHSIC_HS_READY_WAIT_FOR_VALID   (1 << 9)
234 #define UHSIC_MISC_CFG0                         0xc14
235 #define   UHSIC_SUSPEND_EXIT_ON_EDGE            (1 << 7)
236 #define   UHSIC_DETECT_SHORT_CONNECT            (1 << 8)
237 #define   UHSIC_FORCE_XCVR_MODE                 (1 << 15)
238 #define   UHSIC_DISABLE_BUSRESET                (1 << 20)
239 #define UHSIC_MISC_CFG1                         0xc18
240 #define   UHSIC_PLLU_STABLE_COUNT(x)            (((x) & 0xfff) << 2)
241
242 #define UHSIC_PADS_CFG0                         0xc1c
243 #define   UHSIC_TX_RTUNEN                       0xf000
244 #define   UHSIC_TX_RTUNE(x)                     (((x) & 0xf) << 12)
245
246 #define UHSIC_PADS_CFG1                         0xc20
247 #define   UHSIC_PD_BG                           (1 << 2)
248 #define   UHSIC_PD_TX                           (1 << 3)
249 #define   UHSIC_PD_TRK                          (1 << 4)
250 #define   UHSIC_PD_RX                           (1 << 5)
251 #define   UHSIC_PD_ZI                           (1 << 6)
252 #define   UHSIC_RX_SEL                          (1 << 7)
253 #define   UHSIC_RPD_DATA                        (1 << 9)
254 #define   UHSIC_RPD_STROBE                      (1 << 10)
255 #define   UHSIC_RPU_DATA                        (1 << 11)
256 #define   UHSIC_RPU_STROBE                      (1 << 12)
257
258 #define UHSIC_CMD_CFG0                  0xc24
259 #define UHSIC_PRETEND_CONNECT_DETECT    (1 << 5)
260
261 #define UHSIC_STAT_CFG0         0xc28
262 #define UHSIC_CONNECT_DETECT            (1 << 0)
263
264 #define PMC_USB_DEBOUNCE                        0xec
265 #define UTMIP_LINE_DEB_CNT(x)           (((x) & 0xf) << 16)
266 #define UHSIC_LINE_DEB_CNT(x)           (((x) & 0xf) << 20)
267
268 #define PMC_USB_AO                              0xf0
269
270 #define PMC_POWER_DOWN_MASK                     0xffff
271 #define HSIC_RESERVED_P0                        (3 << 14)
272 #define STROBE_VAL_PD_P0                        (1 << 12)
273 #define DATA_VAL_PD_P0                          (1 << 13)
274
275 #define USB_ID_PD(inst)                 (1 << ((4*(inst))+3))
276 #define VBUS_WAKEUP_PD(inst)                    (1 << ((4*(inst))+2))
277 #define   USBON_VAL_PD(inst)                    (1 << ((4*(inst))+1))
278 #define   USBON_VAL_PD_P2                       (1 << 9)
279 #define   USBON_VAL_PD_P1                       (1 << 5)
280 #define   USBON_VAL_PD_P0                       (1 << 1)
281 #define   USBOP_VAL_PD(inst)                    (1 << (4*(inst)))
282 #define   USBOP_VAL_PD_P2                       (1 << 8)
283 #define   USBOP_VAL_PD_P1                       (1 << 4)
284 #define   USBOP_VAL_PD_P0                       (1 << 0)
285 #define   PMC_USB_AO_PD_P2                      (0xf << 8)
286 #define   PMC_USB_AO_ID_PD_P0                   (1 << 3)
287 #define   PMC_USB_AO_VBUS_WAKEUP_PD_P0  (1 << 2)
288
289 #define PMC_TRIGGERS                    0x1ec
290
291 #define   UHSIC_CLR_WALK_PTR_P0         (1 << 3)
292 #define   UTMIP_CLR_WALK_PTR(inst)      (1 << (inst))
293 #define   UTMIP_CLR_WALK_PTR_P2         (1 << 2)
294 #define   UTMIP_CLR_WALK_PTR_P1         (1 << 1)
295 #define   UTMIP_CLR_WALK_PTR_P0         (1 << 0)
296 #define   UTMIP_CAP_CFG(inst)   (1 << ((inst)+4))
297 #define   UTMIP_CAP_CFG_P2              (1 << 6)
298 #define   UTMIP_CAP_CFG_P1              (1 << 5)
299 #define   UTMIP_CAP_CFG_P0              (1 << 4)
300 #define   UTMIP_CLR_WAKE_ALARM(inst)    (1 << ((inst)+12))
301 #define   UHSIC_CLR_WAKE_ALARM_P0       (1 << 15)
302 #define   UTMIP_CLR_WAKE_ALARM_P2       (1 << 14)
303
304 #define PMC_PAD_CFG             (0x1f4)
305
306 #define PMC_UTMIP_TERM_PAD_CFG  0x1f8
307 #define   PMC_TCTRL_VAL(x)      (((x) & 0x1f) << 5)
308 #define   PMC_RCTRL_VAL(x)      (((x) & 0x1f) << 0)
309
310 #define PMC_SLEEP_CFG                   0x1fc
311
312 #define   UHSIC_MASTER_ENABLE                   (1 << 24)
313 #define   UHSIC_WAKE_VAL(x)             (((x) & 0xf) << 28)
314 #define   WAKE_VAL_SD10                 0x2
315 #define   UTMIP_TCTRL_USE_PMC(inst) (1 << ((8*(inst))+3))
316 #define   UTMIP_TCTRL_USE_PMC_P2                (1 << 19)
317 #define   UTMIP_TCTRL_USE_PMC_P1                (1 << 11)
318 #define   UTMIP_TCTRL_USE_PMC_P0                (1 << 3)
319 #define   UTMIP_RCTRL_USE_PMC(inst) (1 << ((8*(inst))+2))
320 #define   UTMIP_RCTRL_USE_PMC_P2                (1 << 18)
321 #define   UTMIP_RCTRL_USE_PMC_P1                (1 << 10)
322 #define   UTMIP_RCTRL_USE_PMC_P0                (1 << 2)
323 #define   UTMIP_FSLS_USE_PMC(inst)      (1 << ((8*(inst))+1))
324 #define   UTMIP_FSLS_USE_PMC_P2         (1 << 17)
325 #define   UTMIP_FSLS_USE_PMC_P1         (1 << 9)
326 #define   UTMIP_FSLS_USE_PMC_P0         (1 << 1)
327 #define   UTMIP_MASTER_ENABLE(inst) (1 << (8*(inst)))
328 #define   UTMIP_MASTER_ENABLE_P2                (1 << 16)
329 #define   UTMIP_MASTER_ENABLE_P1                (1 << 8)
330 #define   UTMIP_MASTER_ENABLE_P0                (1 << 0)
331 #define UHSIC_MASTER_ENABLE_P0          (1 << 24)
332 #define UHSIC_WAKE_VAL_P0(x)            (((x) & 0xf) << 28)
333
334 #define PMC_SLEEPWALK_CFG               0x200
335
336 #define   UHSIC_WAKE_WALK_EN_P0 (1 << 30)
337 #define   UHSIC_LINEVAL_WALK_EN (1 << 31)
338 #define   UTMIP_LINEVAL_WALK_EN(inst) (1 << ((8*(inst))+7))
339 #define   UTMIP_LINEVAL_WALK_EN_P2      (1 << 23)
340 #define   UTMIP_LINEVAL_WALK_EN_P1      (1 << 15)
341 #define   UTMIP_LINEVAL_WALK_EN_P0      (1 << 7)
342 #define   UTMIP_WAKE_VAL(inst, x) (((x) & 0xf) << ((8*(inst))+4))
343 #define   UTMIP_WAKE_VAL_P2(x)          (((x) & 0xf) << 20)
344 #define   UTMIP_WAKE_VAL_P1(x)          (((x) & 0xf) << 12)
345 #define   UTMIP_WAKE_VAL_P0(x)          (((x) & 0xf) << 4)
346 #define   WAKE_VAL_NONE         0xc
347 #define   WAKE_VAL_ANY                  0xF
348 #define   WAKE_VAL_FSJ                  0x2
349 #define   WAKE_VAL_FSK                  0x1
350 #define   WAKE_VAL_SE0                  0x0
351
352 #define PMC_SLEEPWALK_REG(inst)         (0x204 + (4*(inst)))
353 #define   UTMIP_USBOP_RPD_A     (1 << 0)
354 #define   UTMIP_USBON_RPD_A     (1 << 1)
355 #define   UTMIP_AP_A                    (1 << 4)
356 #define   UTMIP_AN_A                    (1 << 5)
357 #define   UTMIP_HIGHZ_A         (1 << 6)
358 #define   UTMIP_USBOP_RPD_B     (1 << 8)
359 #define   UTMIP_USBON_RPD_B     (1 << 9)
360 #define   UTMIP_AP_B                    (1 << 12)
361 #define   UTMIP_AN_B                    (1 << 13)
362 #define   UTMIP_HIGHZ_B         (1 << 14)
363 #define   UTMIP_USBOP_RPD_C     (1 << 16)
364 #define   UTMIP_USBON_RPD_C     (1 << 17)
365 #define   UTMIP_AP_C            (1 << 20)
366 #define   UTMIP_AN_C            (1 << 21)
367 #define   UTMIP_HIGHZ_C         (1 << 22)
368 #define   UTMIP_USBOP_RPD_D     (1 << 24)
369 #define   UTMIP_USBON_RPD_D     (1 << 25)
370 #define   UTMIP_AP_D            (1 << 28)
371 #define   UTMIP_AN_D            (1 << 29)
372 #define   UTMIP_HIGHZ_D         (1 << 30)
373
374 #define PMC_SLEEPWALK_UHSIC             0x210
375
376 #define UHSIC_STROBE_RPD_A              (1 << 0)
377 #define UHSIC_DATA_RPD_A                (1 << 1)
378 #define UHSIC_STROBE_RPU_A              (1 << 2)
379 #define UHSIC_DATA_RPU_A                (1 << 3)
380 #define UHSIC_STROBE_RPD_B              (1 << 8)
381 #define UHSIC_DATA_RPD_B                (1 << 9)
382 #define UHSIC_STROBE_RPU_B              (1 << 10)
383 #define UHSIC_DATA_RPU_B                (1 << 11)
384 #define UHSIC_STROBE_RPD_C              (1 << 16)
385 #define UHSIC_DATA_RPD_C                (1 << 17)
386 #define UHSIC_STROBE_RPU_C              (1 << 18)
387 #define UHSIC_DATA_RPU_C                (1 << 19)
388 #define UHSIC_STROBE_RPD_D              (1 << 24)
389 #define UHSIC_DATA_RPD_D                (1 << 25)
390 #define UHSIC_STROBE_RPU_D              (1 << 26)
391 #define UHSIC_DATA_RPU_D                (1 << 27)
392
393 #define UTMIP_UHSIC_STATUS              0x214
394
395 #define UTMIP_USBOP_VAL(inst)           (1 << ((2*(inst)) + 8))
396 #define UTMIP_USBOP_VAL_P2              (1 << 12)
397 #define UTMIP_USBOP_VAL_P1              (1 << 10)
398 #define UTMIP_USBOP_VAL_P0              (1 << 8)
399 #define UTMIP_USBON_VAL(inst)           (1 << ((2*(inst)) + 9))
400 #define UTMIP_USBON_VAL_P2              (1 << 13)
401 #define UTMIP_USBON_VAL_P1              (1 << 11)
402 #define UTMIP_USBON_VAL_P0              (1 << 9)
403 #define UHSIC_WAKE_ALARM                (1 << 19)
404 #define UTMIP_WAKE_ALARM(inst)          (1 << ((inst) + 16))
405 #define UTMIP_WAKE_ALARM_P2             (1 << 18)
406 #define UTMIP_WAKE_ALARM_P1             (1 << 17)
407 #define UTMIP_WAKE_ALARM_P0             (1 << 16)
408 #define UHSIC_DATA_VAL_P0               (1 << 15)
409 #define UHSIC_STROBE_VAL_P0             (1 << 14)
410 #define UTMIP_WALK_PTR_VAL(inst)        (0x3 << ((inst)*2))
411 #define UHSIC_WALK_PTR_VAL              (0x3 << 6)
412 #define UTMIP_WALK_PTR(inst)            (1 << ((inst)*2))
413 #define UTMIP_WALK_PTR_P2               (1 << 4)
414 #define UTMIP_WALK_PTR_P1               (1 << 2)
415 #define UTMIP_WALK_PTR_P0               (1 << 0)
416
417 #define USB1_PREFETCH_ID                           6
418 #define USB2_PREFETCH_ID                           18
419 #define USB3_PREFETCH_ID                           17
420
421 #define PMC_UTMIP_UHSIC_FAKE            0x218
422
423 #define UHSIC_STROBE_VAL                (1 << 12)
424 #define UHSIC_DATA_VAL                  (1 << 13)
425 #define UHSIC_STROBE_ENB                (1 << 14)
426 #define UHSIC_DATA_ENB                  (1 << 15)
427 #define   USBON_VAL(inst)       (1 << ((4*(inst))+1))
428 #define   USBON_VAL_P2                  (1 << 9)
429 #define   USBON_VAL_P1                  (1 << 5)
430 #define   USBON_VAL_P0                  (1 << 1)
431 #define   USBOP_VAL(inst)       (1 << (4*(inst)))
432 #define   USBOP_VAL_P2                  (1 << 8)
433 #define   USBOP_VAL_P1                  (1 << 4)
434 #define   USBOP_VAL_P0                  (1 << 0)
435
436 #define PMC_UTMIP_BIAS_MASTER_CNTRL 0x30c
437 #define   BIAS_MASTER_PROG_VAL          (1 << 1)
438
439 #define PMC_UTMIP_MASTER_CONFIG 0x310
440
441 #define UTMIP_PWR(inst)         (1 << (inst))
442 #define UHSIC_PWR                       (1 << 3)
443
444 #define FUSE_USB_CALIB_0                0x1F0
445 #define   XCVR_SETUP(x) (((x) & 0x7F) << 0)
446 #define   XCVR_SETUP_LSB_MASK   0xF
447 #define   XCVR_SETUP_MSB_MASK   0x70
448 #define   XCVR_SETUP_LSB_MAX_VAL        0xF
449
450 /* These values (in milli second) are taken from the battery charging spec */
451 #define TDP_SRC_ON_MS    100
452 #define TDPSRC_CON_MS    40
453
454 #ifdef DEBUG
455 #define DBG(stuff...)   pr_info("tegra3_usb_phy: " stuff)
456 #else
457 #define DBG(stuff...)   do {} while (0)
458 #endif
459
460 #if 0
461 #define PHY_DBG(stuff...)       pr_info("tegra3_usb_phy: " stuff)
462 #else
463 #define PHY_DBG(stuff...)       do {} while (0)
464 #endif
465
466 static u32 utmip_rctrl_val, utmip_tctrl_val;
467 static DEFINE_SPINLOCK(utmip_pad_lock);
468 static int utmip_pad_count;
469
470 static struct tegra_xtal_freq utmip_freq_table[] = {
471         {
472                 .freq = 12000000,
473                 .enable_delay = 0x02,
474                 .stable_count = 0x2F,
475                 .active_delay = 0x04,
476                 .xtal_freq_count = 0x76,
477                 .debounce = 0x7530,
478                 .pdtrk_count = 5,
479         },
480         {
481                 .freq = 13000000,
482                 .enable_delay = 0x02,
483                 .stable_count = 0x33,
484                 .active_delay = 0x05,
485                 .xtal_freq_count = 0x7F,
486                 .debounce = 0x7EF4,
487                 .pdtrk_count = 5,
488         },
489         {
490                 .freq = 19200000,
491                 .enable_delay = 0x03,
492                 .stable_count = 0x4B,
493                 .active_delay = 0x06,
494                 .xtal_freq_count = 0xBB,
495                 .debounce = 0xBB80,
496                 .pdtrk_count = 7,
497         },
498         {
499                 .freq = 26000000,
500                 .enable_delay = 0x04,
501                 .stable_count = 0x66,
502                 .active_delay = 0x09,
503                 .xtal_freq_count = 0xFE,
504                 .debounce = 0xFDE8,
505                 .pdtrk_count = 9,
506         },
507 };
508
509 static struct tegra_xtal_freq uhsic_freq_table[] = {
510         {
511                 .freq = 12000000,
512                 .enable_delay = 0x02,
513                 .stable_count = 0x2F,
514                 .active_delay = 0x0,
515                 .xtal_freq_count = 0x1CA,
516         },
517         {
518                 .freq = 13000000,
519                 .enable_delay = 0x02,
520                 .stable_count = 0x33,
521                 .active_delay = 0x0,
522                 .xtal_freq_count = 0x1F0,
523         },
524         {
525                 .freq = 19200000,
526                 .enable_delay = 0x03,
527                 .stable_count = 0x4B,
528                 .active_delay = 0x0,
529                 .xtal_freq_count = 0x2DD,
530         },
531         {
532                 .freq = 26000000,
533                 .enable_delay = 0x04,
534                 .stable_count = 0x66,
535                 .active_delay = 0x0,
536                 .xtal_freq_count = 0x3E0,
537         },
538 };
539
540 static void usb_phy_fence_read(struct tegra_usb_phy *phy)
541 {
542         /* Fence read for coherency of AHB master intiated writes */
543         if (phy->inst == 0)
544                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB1_PREFETCH_ID));
545         else if (phy->inst == 1)
546                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB2_PREFETCH_ID));
547         else if (phy->inst == 2)
548                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB3_PREFETCH_ID));
549
550         return;
551 }
552
553 static void utmip_setup_pmc_wake_detect(struct tegra_usb_phy *phy)
554 {
555         unsigned long val, pmc_pad_cfg_val;
556         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
557         unsigned  int inst = phy->inst;
558         void __iomem *base = phy->regs;
559         bool port_connected;
560         enum usb_phy_port_speed port_speed;
561
562         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
563
564         /* check for port connect status */
565         val = readl(base + USB_PORTSC);
566         port_connected = val & USB_PORTSC_CCS;
567
568         if (!port_connected)
569                 return;
570
571         port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
572                 HOSTPC1_DEVLC_PSPD_MASK;
573         /*Set PMC MASTER bits to do the following
574         * a. Take over the UTMI drivers
575         * b. set up such that it will take over resume
576         *        if remote wakeup is detected
577         * Prepare PMC to take over suspend-wake detect-drive resume until USB
578         * controller ready
579         */
580
581         /* disable master enable in PMC */
582         val = readl(pmc_base + PMC_SLEEP_CFG);
583         val &= ~UTMIP_MASTER_ENABLE(inst);
584         writel(val, pmc_base + PMC_SLEEP_CFG);
585
586         /* UTMIP_PWR_PX=1 for power savings mode */
587         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
588         val |= UTMIP_PWR(inst);
589         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
590
591         /* config debouncer */
592         val = readl(pmc_base + PMC_USB_DEBOUNCE);
593         val &= ~UTMIP_LINE_DEB_CNT(~0);
594         val |= UTMIP_LINE_DEB_CNT(4);
595         writel(val, pmc_base + PMC_USB_DEBOUNCE);
596
597         /* Make sure nothing is happening on the line with respect to PMC */
598         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
599         val &= ~USBOP_VAL(inst);
600         val &= ~USBON_VAL(inst);
601         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
602
603         /* Make sure wake value for line is none */
604         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
605         val &= ~UTMIP_LINEVAL_WALK_EN(inst);
606         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
607         val = readl(pmc_base + PMC_SLEEP_CFG);
608         val &= ~UTMIP_WAKE_VAL(inst, ~0);
609         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
610         writel(val, pmc_base + PMC_SLEEP_CFG);
611
612         /* turn off pad detectors */
613         val = readl(pmc_base + PMC_USB_AO);
614         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
615         writel(val, pmc_base + PMC_USB_AO);
616
617         /* Remove fake values and make synchronizers work a bit */
618         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
619         val &= ~USBOP_VAL(inst);
620         val &= ~USBON_VAL(inst);
621         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
622
623         /* Enable which type of event can trigger a walk,
624         in this case usb_line_wake */
625         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
626         val |= UTMIP_LINEVAL_WALK_EN(inst);
627         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
628
629         /* Enable which type of event can trigger a walk,
630         * in this case usb_line_wake */
631         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
632         val |= UTMIP_LINEVAL_WALK_EN(inst);
633         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
634
635         /* Clear the walk pointers and wake alarm */
636         val = readl(pmc_base + PMC_TRIGGERS);
637         val |= UTMIP_CLR_WAKE_ALARM(inst) | UTMIP_CLR_WALK_PTR(inst);
638         writel(val, pmc_base + PMC_TRIGGERS);
639
640
641         /* Capture FS/LS pad configurations */
642         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
643         val = readl(pmc_base + PMC_TRIGGERS);
644         val |= UTMIP_CAP_CFG(inst);
645         writel(val, pmc_base + PMC_TRIGGERS);
646         udelay(1);
647         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
648
649         /* BIAS MASTER_ENABLE=0 */
650         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
651         val &= ~BIAS_MASTER_PROG_VAL;
652         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
653
654         /* program walk sequence, maintain a J, followed by a driven K
655         * to signal a resume once an wake event is detected */
656         val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
657         val &= ~UTMIP_AP_A;
658         val |= UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_AN_A |UTMIP_HIGHZ_A |
659                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_AP_B | UTMIP_AN_B |
660                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_AP_C | UTMIP_AN_C |
661                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_AP_D | UTMIP_AN_D;
662         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
663
664         if (port_speed == USB_PHY_PORT_SPEED_LOW) {
665                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
666                 val &= ~(UTMIP_AN_B | UTMIP_HIGHZ_B | UTMIP_AN_C |
667                         UTMIP_HIGHZ_C | UTMIP_AN_D | UTMIP_HIGHZ_D);
668                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
669         } else {
670                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
671                 val &= ~(UTMIP_AP_B | UTMIP_HIGHZ_B | UTMIP_AP_C |
672                         UTMIP_HIGHZ_C | UTMIP_AP_D | UTMIP_HIGHZ_D);
673                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
674         }
675
676         /* turn on pad detectors */
677         val = readl(pmc_base + PMC_USB_AO);
678         val &= ~(USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
679         writel(val, pmc_base + PMC_USB_AO);
680
681         /* Add small delay before usb detectors provide stable line values */
682         mdelay(1);
683
684         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
685         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
686         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
687         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
688
689         phy->remote_wakeup = false;
690
691         /* Turn over pad configuration to PMC  for line wake events*/
692         val = readl(pmc_base + PMC_SLEEP_CFG);
693         val &= ~UTMIP_WAKE_VAL(inst, ~0);
694         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_ANY);
695         val |= UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst);
696         val |= UTMIP_MASTER_ENABLE(inst) | UTMIP_FSLS_USE_PMC(inst);
697         writel(val, pmc_base + PMC_SLEEP_CFG);
698
699         val = readl(base + UTMIP_PMC_WAKEUP0);
700         val |= EVENT_INT_ENB;
701         writel(val, base + UTMIP_PMC_WAKEUP0);
702         PHY_DBG("%s ENABLE_PMC inst = %d\n", __func__, inst);
703 }
704
705 static void utmip_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy)
706 {
707         unsigned long val;
708         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
709         unsigned  int inst = phy->inst;
710         void __iomem *base = phy->regs;
711
712         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
713
714         val = readl(pmc_base + PMC_SLEEP_CFG);
715         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
716         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
717         writel(val, pmc_base + PMC_SLEEP_CFG);
718
719         val = readl(pmc_base + PMC_TRIGGERS);
720         val |= UTMIP_CLR_WAKE_ALARM(inst) | UTMIP_CLR_WALK_PTR(inst);
721         writel(val, pmc_base + PMC_TRIGGERS);
722
723         val = readl(base + UTMIP_PMC_WAKEUP0);
724         val &= ~EVENT_INT_ENB;
725         writel(val, base + UTMIP_PMC_WAKEUP0);
726
727         /* Disable PMC master mode by clearing MASTER_EN */
728         val = readl(pmc_base + PMC_SLEEP_CFG);
729         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
730                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
731         writel(val, pmc_base + PMC_SLEEP_CFG);
732
733         val = readl(pmc_base + PMC_TRIGGERS);
734         val &= ~UTMIP_CAP_CFG(inst);
735         writel(val, pmc_base + PMC_TRIGGERS);
736
737         /* turn off pad detectors */
738         val = readl(pmc_base + PMC_USB_AO);
739         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
740         writel(val, pmc_base + PMC_USB_AO);
741
742         phy->remote_wakeup = false;
743         PHY_DBG("%s DISABLE_PMC inst = %d\n", __func__, inst);
744 }
745
746 static bool utmi_phy_remotewake_detected(struct tegra_usb_phy *phy)
747 {
748         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
749         void __iomem *base = phy->regs;
750         unsigned  int inst = phy->inst;
751         u32 val;
752
753         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
754         val = readl(base + UTMIP_PMC_WAKEUP0);
755         if (val & EVENT_INT_ENB) {
756                 val = readl(pmc_base + UTMIP_UHSIC_STATUS);
757                 if (UTMIP_WAKE_ALARM(inst) & val) {
758                         val = readl(pmc_base + PMC_SLEEP_CFG);
759                         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
760                         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
761                         writel(val, pmc_base + PMC_SLEEP_CFG);
762
763                         val = readl(pmc_base + PMC_TRIGGERS);
764                         val |= UTMIP_CLR_WAKE_ALARM(inst) |
765                                 UTMIP_CLR_WALK_PTR(inst);
766                         writel(val, pmc_base + PMC_TRIGGERS);
767
768                         val = readl(base + UTMIP_PMC_WAKEUP0);
769                         val &= ~EVENT_INT_ENB;
770                         writel(val, base + UTMIP_PMC_WAKEUP0);
771                         phy->remote_wakeup = true;
772                         return true;
773                 }
774         }
775         return false;
776 }
777
778 static void utmi_phy_enable_trking_data(struct tegra_usb_phy *phy)
779 {
780         void __iomem *base = IO_ADDRESS(TEGRA_USB_BASE);
781         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
782         static bool init_done = false;
783         u32 val;
784
785         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
786
787         /* Should be done only once after system boot */
788         if (init_done)
789                 return;
790
791         clk_enable(phy->utmi_pad_clk);
792         /* Bias pad MASTER_ENABLE=1 */
793         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
794         val |= BIAS_MASTER_PROG_VAL;
795         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
796
797         /* Setting the tracking length time */
798         val = readl(base + UTMIP_BIAS_CFG1);
799         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
800         val |= UTMIP_BIAS_PDTRK_COUNT(5);
801         writel(val, base + UTMIP_BIAS_CFG1);
802
803         /* Bias PDTRK is Shared and MUST be done from USB1 ONLY, PD_TRK=0 */
804         val = readl(base + UTMIP_BIAS_CFG1);
805         val &= ~UTMIP_BIAS_PDTRK_POWERDOWN;
806         writel(val, base + UTMIP_BIAS_CFG1);
807
808         val = readl(base + UTMIP_BIAS_CFG1);
809         val |= UTMIP_BIAS_PDTRK_POWERUP;
810         writel(val, base + UTMIP_BIAS_CFG1);
811
812         /* Wait for 25usec */
813         udelay(25);
814
815         /* Bias pad MASTER_ENABLE=0 */
816         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
817         val &= ~BIAS_MASTER_PROG_VAL;
818         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
819
820         /* Wait for 1usec */
821         udelay(1);
822
823         /* Bias pad MASTER_ENABLE=1 */
824         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
825         val |= BIAS_MASTER_PROG_VAL;
826         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
827
828         /* Read RCTRL and TCTRL from UTMIP space */
829         val = readl(base + UTMIP_BIAS_STS0);
830         utmip_rctrl_val = ffz(UTMIP_RCTRL_VAL(val));
831         utmip_tctrl_val = ffz(UTMIP_TCTRL_VAL(val));
832
833         /* PD_TRK=1 */
834         val = readl(base + UTMIP_BIAS_CFG1);
835         val |= UTMIP_BIAS_PDTRK_POWERDOWN;
836         writel(val, base + UTMIP_BIAS_CFG1);
837
838         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
839         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
840         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
841         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
842         clk_disable(phy->utmi_pad_clk);
843         init_done = true;
844 }
845
846 static void utmip_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy)
847 {
848         unsigned long val;
849         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
850         unsigned  int inst = phy->inst;
851
852         /* power down UTMIP interfaces */
853         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
854         val |= UTMIP_PWR(inst);
855         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
856
857         /* setup sleep walk usb controller */
858         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
859                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
860                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
861                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
862         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
863
864         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
865         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
866         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
867         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
868
869         /* Turn over pad configuration to PMC */
870         val = readl(pmc_base + PMC_SLEEP_CFG);
871         val &= ~UTMIP_WAKE_VAL(inst, ~0);
872         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE) |
873                 UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
874                 UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst);
875         writel(val, pmc_base + PMC_SLEEP_CFG);
876         PHY_DBG("%s ENABLE_PMC inst = %d\n", __func__, inst);
877 }
878
879 static void utmip_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
880 {
881         unsigned long val;
882         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
883         unsigned  int inst = phy->inst;
884
885         /* Disable PMC master mode by clearing MASTER_EN */
886         val = readl(pmc_base + PMC_SLEEP_CFG);
887         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
888                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
889         writel(val, pmc_base + PMC_SLEEP_CFG);
890         mdelay(1);
891         PHY_DBG("%s DISABLE_PMC inst = %d\n", __func__, inst);
892 }
893
894
895 #ifdef KERNEL_WARNING
896 static void usb_phy_power_down_pmc(void)
897 {
898         unsigned long val;
899         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
900
901         /* power down all 3 UTMIP interfaces */
902         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
903         val |= UTMIP_PWR(0) | UTMIP_PWR(1) | UTMIP_PWR(2);
904         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
905
906         /* turn on pad detectors */
907         writel(PMC_POWER_DOWN_MASK, pmc_base + PMC_USB_AO);
908
909         /* setup sleep walk fl all 3 usb controllers */
910         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
911                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
912                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
913                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
914         writel(val, pmc_base + PMC_SLEEPWALK_REG(0));
915         writel(val, pmc_base + PMC_SLEEPWALK_REG(1));
916         writel(val, pmc_base + PMC_SLEEPWALK_REG(2));
917
918         /* enable pull downs on HSIC PMC */
919         val = UHSIC_STROBE_RPD_A | UHSIC_DATA_RPD_A | UHSIC_STROBE_RPD_B |
920                 UHSIC_DATA_RPD_B | UHSIC_STROBE_RPD_C | UHSIC_DATA_RPD_C |
921                 UHSIC_STROBE_RPD_D | UHSIC_DATA_RPD_D;
922         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
923
924         /* Turn over pad configuration to PMC */
925         val = readl(pmc_base + PMC_SLEEP_CFG);
926         val &= ~UTMIP_WAKE_VAL(0, ~0);
927         val &= ~UTMIP_WAKE_VAL(1, ~0);
928         val &= ~UTMIP_WAKE_VAL(2, ~0);
929         val &= ~UHSIC_WAKE_VAL_P0(~0);
930         val |= UTMIP_WAKE_VAL(0, WAKE_VAL_NONE) | UHSIC_WAKE_VAL_P0(WAKE_VAL_NONE) |
931         UTMIP_WAKE_VAL(1, WAKE_VAL_NONE) | UTMIP_WAKE_VAL(2, WAKE_VAL_NONE) |
932         UTMIP_RCTRL_USE_PMC(0) | UTMIP_RCTRL_USE_PMC(1) | UTMIP_RCTRL_USE_PMC(2) |
933         UTMIP_TCTRL_USE_PMC(0) | UTMIP_TCTRL_USE_PMC(1) | UTMIP_TCTRL_USE_PMC(2) |
934         UTMIP_FSLS_USE_PMC(0) | UTMIP_FSLS_USE_PMC(1) | UTMIP_FSLS_USE_PMC(2) |
935         UTMIP_MASTER_ENABLE(0) | UTMIP_MASTER_ENABLE(1) | UTMIP_MASTER_ENABLE(2) |
936         UHSIC_MASTER_ENABLE_P0;
937         writel(val, pmc_base + PMC_SLEEP_CFG);
938 }
939 #endif
940
941 static int usb_phy_bringup_host_controller(struct tegra_usb_phy *phy)
942 {
943         unsigned long val;
944         void __iomem *base = phy->regs;
945
946         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
947         PHY_DBG("[%d] USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n", __LINE__,
948                 readl(base + USB_USBSTS), readl(base + USB_PORTSC),
949                                                         phy->port_speed);
950
951         /* Device is plugged in when system is in LP0 */
952         /* Bring up the controller from LP0*/
953         val = readl(base + USB_USBCMD);
954         val |= USB_CMD_RESET;
955         writel(val, base + USB_USBCMD);
956
957         if (usb_phy_reg_status_wait(base + USB_USBCMD,
958                 USB_CMD_RESET, 0, 2500) < 0) {
959                 pr_err("%s: timeout waiting for reset\n", __func__);
960         }
961
962         val = readl(base + USB_USBMODE);
963         val &= ~USB_USBMODE_MASK;
964         val |= USB_USBMODE_HOST;
965         writel(val, base + USB_USBMODE);
966         val = readl(base + HOSTPC1_DEVLC);
967         val &= ~HOSTPC1_DEVLC_PTS(~0);
968
969         if (phy->pdata->phy_intf == TEGRA_USB_PHY_INTF_HSIC)
970                 val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
971         else
972                 val |= HOSTPC1_DEVLC_STS;
973         writel(val, base + HOSTPC1_DEVLC);
974
975         /* Enable Port Power */
976         val = readl(base + USB_PORTSC);
977         val |= USB_PORTSC_PP;
978         writel(val, base + USB_PORTSC);
979         udelay(10);
980
981         /* Check if the phy resume from LP0. When the phy resume from LP0
982          * USB register will be reset.to zero */
983         if (!readl(base + USB_ASYNCLISTADDR)) {
984                 /* Program the field PTC based on the saved speed mode */
985                 val = readl(base + USB_PORTSC);
986                 val &= ~USB_PORTSC_PTC(~0);
987                 if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH)
988                         val |= USB_PORTSC_PTC(5);
989                 else if (phy->port_speed == USB_PHY_PORT_SPEED_FULL)
990                         val |= USB_PORTSC_PTC(6);
991                 else if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
992                         val |= USB_PORTSC_PTC(7);
993                 writel(val, base + USB_PORTSC);
994                 udelay(10);
995
996                 /* Disable test mode by setting PTC field to NORMAL_OP */
997                 val = readl(base + USB_PORTSC);
998                 val &= ~USB_PORTSC_PTC(~0);
999                 writel(val, base + USB_PORTSC);
1000                 udelay(10);
1001         }
1002
1003         /* Poll until CCS is enabled */
1004         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
1005                                                  USB_PORTSC_CCS, 2000)) {
1006                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
1007         }
1008
1009         /* Poll until PE is enabled */
1010         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_PE,
1011                                                  USB_PORTSC_PE, 2000)) {
1012                 pr_err("%s: timeout waiting for USB_PORTSC_PE\n", __func__);
1013         }
1014
1015         /* Clear the PCI status, to avoid an interrupt taken upon resume */
1016         val = readl(base + USB_USBSTS);
1017         val |= USB_USBSTS_PCI;
1018         writel(val, base + USB_USBSTS);
1019
1020         if (!phy->remote_wakeup) {
1021                 /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
1022                 val = readl(base + USB_PORTSC);
1023                 if ((val & USB_PORTSC_PP) && (val & USB_PORTSC_PE)) {
1024                         val |= USB_PORTSC_SUSP;
1025                         writel(val, base + USB_PORTSC);
1026                         /* Need a 4ms delay before the controller goes to suspend */
1027                         mdelay(4);
1028
1029                         /* Wait until port suspend completes */
1030                         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_SUSP,
1031                                                          USB_PORTSC_SUSP, 1000)) {
1032                                 pr_err("%s: timeout waiting for PORT_SUSPEND\n",
1033                                                                         __func__);
1034                         }
1035                 }
1036         }
1037         PHY_DBG("[%d] USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n", __LINE__,
1038                 readl(base + USB_USBSTS), readl(base + USB_PORTSC),
1039                                                         phy->port_speed);
1040
1041         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1042                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1043         return 0;
1044 }
1045
1046 static void usb_phy_wait_for_sof(struct tegra_usb_phy *phy)
1047 {
1048         unsigned long val;
1049         void __iomem *base = phy->regs;
1050
1051         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1052
1053         val = readl(base + USB_USBSTS);
1054         writel(val, base + USB_USBSTS);
1055         udelay(20);
1056         /* wait for two SOFs */
1057         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1058                 USB_USBSTS_SRI, 2500))
1059                 pr_err("%s: timeout waiting for SOF\n", __func__);
1060
1061         val = readl(base + USB_USBSTS);
1062         writel(val, base + USB_USBSTS);
1063         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI, 0, 2500))
1064                 pr_err("%s: timeout waiting for SOF\n", __func__);
1065
1066         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1067                         USB_USBSTS_SRI, 2500))
1068                 pr_err("%s: timeout waiting for SOF\n", __func__);
1069
1070         udelay(20);
1071 }
1072
1073 static unsigned int utmi_phy_xcvr_setup_value(struct tegra_usb_phy *phy)
1074 {
1075         struct tegra_utmi_config *cfg = &phy->pdata->u_cfg.utmi;
1076         signed long val;
1077
1078         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1079
1080         if (cfg->xcvr_use_fuses) {
1081                 val = XCVR_SETUP(tegra_fuse_readl(FUSE_USB_CALIB_0));
1082                 if (cfg->xcvr_use_lsb) {
1083                         val = min((unsigned int) ((val & XCVR_SETUP_LSB_MASK)
1084                                 + cfg->xcvr_setup_offset),
1085                                 (unsigned int) XCVR_SETUP_LSB_MAX_VAL);
1086                         val |= (cfg->xcvr_setup & XCVR_SETUP_MSB_MASK);
1087                 } else {
1088                         if (cfg->xcvr_setup_offset <= UTMIP_XCVR_MAX_OFFSET)
1089                                 val = val + cfg->xcvr_setup_offset;
1090
1091                         if (val > UTMIP_XCVR_SETUP_MAX_VALUE) {
1092                                 val = UTMIP_XCVR_SETUP_MAX_VALUE;
1093                                 pr_info("%s: reset XCVR_SETUP to max value\n",
1094                                                 __func__);
1095                         } else if (val < UTMIP_XCVR_SETUP_MIN_VALUE) {
1096                                 val = UTMIP_XCVR_SETUP_MIN_VALUE;
1097                                 pr_info("%s: reset XCVR_SETUP to min value\n",
1098                                                 __func__);
1099                         }
1100                 }
1101         } else {
1102                 val = cfg->xcvr_setup;
1103         }
1104
1105         return (unsigned int) val;
1106 }
1107
1108 static int utmi_phy_open(struct tegra_usb_phy *phy)
1109 {
1110         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1111         unsigned long parent_rate, val;
1112         int i;
1113
1114         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1115
1116         phy->utmi_pad_clk = clk_get_sys("utmip-pad", NULL);
1117         if (IS_ERR(phy->utmi_pad_clk)) {
1118                 pr_err("%s: can't get utmip pad clock\n", __func__);
1119                 return PTR_ERR(phy->utmi_pad_clk);
1120         }
1121
1122         phy->utmi_xcvr_setup = utmi_phy_xcvr_setup_value(phy);
1123
1124         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
1125         for (i = 0; i < ARRAY_SIZE(utmip_freq_table); i++) {
1126                 if (utmip_freq_table[i].freq == parent_rate) {
1127                         phy->freq = &utmip_freq_table[i];
1128                         break;
1129                 }
1130         }
1131         if (!phy->freq) {
1132                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
1133                 return -EINVAL;
1134         }
1135
1136         /* Power-up the VBUS detector for UTMIP PHY */
1137         val = readl(pmc_base + PMC_USB_AO);
1138         val &= ~(PMC_USB_AO_VBUS_WAKEUP_PD_P0 | PMC_USB_AO_ID_PD_P0);
1139         writel((val | PMC_USB_AO_PD_P2), (pmc_base + PMC_USB_AO));
1140
1141         utmip_powerup_pmc_wake_detect(phy);
1142
1143         return 0;
1144 }
1145
1146 static void utmi_phy_close(struct tegra_usb_phy *phy)
1147 {
1148         unsigned long val;
1149         void __iomem *base = phy->regs;
1150
1151         DBG("%s inst:[%d]\n", __func__, phy->inst);
1152
1153         /* Disable PHY clock valid interrupts while going into suspend*/
1154         if (phy->pdata->u_data.host.hot_plug) {
1155                 val = readl(base + USB_SUSP_CTRL);
1156                 val &= ~USB_PHY_CLK_VALID_INT_ENB;
1157                 writel(val, base + USB_SUSP_CTRL);
1158         }
1159
1160         clk_put(phy->utmi_pad_clk);
1161 }
1162
1163 static int utmi_phy_pad_power_on(struct tegra_usb_phy *phy)
1164 {
1165         unsigned long val, flags;
1166         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1167
1168         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1169
1170         clk_enable(phy->utmi_pad_clk);
1171
1172         spin_lock_irqsave(&utmip_pad_lock, flags);
1173         utmip_pad_count++;
1174
1175         val = readl(pad_base + UTMIP_BIAS_CFG0);
1176         val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
1177         val |= UTMIP_HSSQUELCH_LEVEL(0x2) | UTMIP_HSDISCON_LEVEL(0x1) |
1178                 UTMIP_HSDISCON_LEVEL_MSB;
1179         writel(val, pad_base + UTMIP_BIAS_CFG0);
1180
1181         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1182
1183         clk_disable(phy->utmi_pad_clk);
1184
1185         return 0;
1186 }
1187
1188 static int utmi_phy_pad_power_off(struct tegra_usb_phy *phy)
1189 {
1190         unsigned long val, flags;
1191         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1192
1193         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1194
1195         clk_enable(phy->utmi_pad_clk);
1196         spin_lock_irqsave(&utmip_pad_lock, flags);
1197
1198         if (!utmip_pad_count) {
1199                 pr_err("%s: utmip pad already powered off\n", __func__);
1200                 goto out;
1201         }
1202         if (--utmip_pad_count == 0) {
1203                 val = readl(pad_base + UTMIP_BIAS_CFG0);
1204                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
1205                 val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) | UTMIP_HSDISCON_LEVEL(~0) |
1206                         UTMIP_HSDISCON_LEVEL_MSB);
1207                 writel(val, pad_base + UTMIP_BIAS_CFG0);
1208         }
1209 out:
1210         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1211         clk_disable(phy->utmi_pad_clk);
1212
1213         return 0;
1214 }
1215
1216 static int utmi_phy_irq(struct tegra_usb_phy *phy)
1217 {
1218         void __iomem *base = phy->regs;
1219         unsigned long val = 0;
1220
1221         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1222         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1223                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1224         DBG("USB_USBMODE[0x%x] USB_USBCMD[0x%x]\n",
1225                         readl(base + USB_USBMODE), readl(base + USB_USBCMD));
1226
1227         usb_phy_fence_read(phy);
1228         /* check if there is any remote wake event */
1229         if (utmi_phy_remotewake_detected(phy))
1230                 pr_info("%s: utmip remote wake detected\n", __func__);
1231
1232         if (phy->pdata->u_data.host.hot_plug) {
1233                 val = readl(base + USB_SUSP_CTRL);
1234                 if ((val  & USB_PHY_CLK_VALID_INT_STS)) {
1235                         val &= ~USB_PHY_CLK_VALID_INT_ENB |
1236                                         USB_PHY_CLK_VALID_INT_STS;
1237                         writel(val , (base + USB_SUSP_CTRL));
1238                         pr_info("%s: usb device plugged-in\n", __func__);
1239                         val = readl(base + USB_USBSTS);
1240                         if (!(val  & USB_USBSTS_PCI))
1241                                 return IRQ_NONE;
1242                         val = readl(base + USB_PORTSC);
1243                         val &= ~(USB_PORTSC_WKCN | USB_PORTSC_RWC_BITS);
1244                         writel(val , (base + USB_PORTSC));
1245                 }
1246         }
1247
1248         return IRQ_HANDLED;
1249 }
1250
1251 static void utmi_phy_enable_obs_bus(struct tegra_usb_phy *phy)
1252 {
1253         unsigned long val;
1254         void __iomem *base = phy->regs;
1255
1256         /* (2LS WAR)is not required for LS and FS devices and is only for HS */
1257         if ((phy->port_speed == USB_PHY_PORT_SPEED_LOW) ||
1258                 (phy->port_speed == USB_PHY_PORT_SPEED_FULL)) {
1259                 /* do not enable the OBS bus */
1260                 val = readl(base + UTMIP_MISC_CFG0);
1261                 val &= ~(UTMIP_DPDM_OBSERVE_SEL(~0));
1262                 writel(val, base + UTMIP_MISC_CFG0);
1263                 DBG("%s(%d) Disable OBS bus\n", __func__, __LINE__);
1264                 return;
1265         }
1266         /* Force DP/DM pulldown active for Host mode */
1267         val = readl(base + UTMIP_MISC_CFG0);
1268         val |= FORCE_PULLDN_DM | FORCE_PULLDN_DP |
1269                         COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS;
1270         writel(val, base + UTMIP_MISC_CFG0);
1271         val = readl(base + UTMIP_MISC_CFG0);
1272         val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1273         if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
1274                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
1275         else
1276                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
1277         writel(val, base + UTMIP_MISC_CFG0);
1278         udelay(1);
1279
1280         val = readl(base + UTMIP_MISC_CFG0);
1281         val |= UTMIP_DPDM_OBSERVE;
1282         writel(val, base + UTMIP_MISC_CFG0);
1283         udelay(10);
1284         DBG("%s(%d) Enable OBS bus\n", __func__, __LINE__);
1285         PHY_DBG("ENABLE_OBS_BUS\n");
1286 }
1287
1288 static int utmi_phy_disable_obs_bus(struct tegra_usb_phy *phy)
1289 {
1290         unsigned long val;
1291         void __iomem *base = phy->regs;
1292         unsigned long flags;
1293
1294         /* check if OBS bus is already enabled */
1295         val = readl(base + UTMIP_MISC_CFG0);
1296         if (val & UTMIP_DPDM_OBSERVE) {
1297                 PHY_DBG("DISABLE_OBS_BUS\n");
1298
1299                 /* disable ALL interrupts on current CPU */
1300                 local_irq_save(flags);
1301
1302                 /* Change the UTMIP OBS bus to drive SE0 */
1303                 val = readl(base + UTMIP_MISC_CFG0);
1304                 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1305                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_SE0;
1306                 writel(val, base + UTMIP_MISC_CFG0);
1307
1308                 /* Wait for 3us(2 LS bit times) */
1309                 udelay(3);
1310
1311                 /* Release UTMIP OBS bus */
1312                 val = readl(base + UTMIP_MISC_CFG0);
1313                 val &= ~UTMIP_DPDM_OBSERVE;
1314                 writel(val, base + UTMIP_MISC_CFG0);
1315
1316                 /* Release DP/DM pulldown for Host mode */
1317                 val = readl(base + UTMIP_MISC_CFG0);
1318                 val &= ~(FORCE_PULLDN_DM | FORCE_PULLDN_DP |
1319                                 COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS);
1320                 writel(val, base + UTMIP_MISC_CFG0);
1321
1322                 val = readl(base + USB_USBCMD);
1323                 val |= USB_USBCMD_RS;
1324                 writel(val, base + USB_USBCMD);
1325
1326                 /* restore ALL interrupts on current CPU */
1327                 local_irq_restore(flags);
1328
1329                 if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
1330                                                          USB_USBCMD_RS, 2000)) {
1331                         pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
1332                         return -ETIMEDOUT;
1333                 }
1334         }
1335         return 0;
1336 }
1337
1338 static int utmi_phy_post_resume(struct tegra_usb_phy *phy)
1339 {
1340         unsigned long val;
1341         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1342         unsigned  int inst = phy->inst;
1343
1344         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1345         val = readl(pmc_base + PMC_SLEEP_CFG);
1346         /* if PMC is not disabled by now then disable it */
1347         if (val & UTMIP_MASTER_ENABLE(inst)) {
1348                 utmip_phy_disable_pmc_bus_ctrl(phy);
1349         }
1350
1351         utmi_phy_disable_obs_bus(phy);
1352
1353         return 0;
1354 }
1355
1356 static void phy_post_suspend(struct tegra_usb_phy *phy)
1357 {
1358
1359         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1360         /* Need a 4ms delay for controller to suspend */
1361         mdelay(4);
1362
1363 }
1364
1365 static int utmi_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1366 {
1367         unsigned long val;
1368         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1369         void __iomem *base = phy->regs;
1370         unsigned  int inst = phy->inst;
1371
1372         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1373         phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
1374                         HOSTPC1_DEVLC_PSPD_MASK;
1375
1376         if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH) {
1377                 /* Disable interrupts */
1378                 writel(0, base + USB_USBINTR);
1379                 /* Clear the run bit to stop SOFs - 2LS WAR */
1380                 val = readl(base + USB_USBCMD);
1381                 val &= ~USB_USBCMD_RS;
1382                 writel(val, base + USB_USBCMD);
1383                 if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
1384                                                          USB_USBSTS_HCH, 2000)) {
1385                         pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
1386                 }
1387         }
1388
1389         val = readl(pmc_base + PMC_SLEEP_CFG);
1390         if (val & UTMIP_MASTER_ENABLE(inst)) {
1391                 if (!remote_wakeup)
1392                         utmip_phy_disable_pmc_bus_ctrl(phy);
1393         } else {
1394                 utmi_phy_enable_obs_bus(phy);
1395         }
1396
1397         return 0;
1398 }
1399
1400 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
1401 {
1402         unsigned long val;
1403         void __iomem *base = phy->regs;
1404
1405         PHY_DBG("%s(%d) inst:[%d] BEGIN\n", __func__, __LINE__, phy->inst);
1406         if (!phy->phy_clk_on) {
1407                 PHY_DBG("%s(%d) inst:[%d] phy clk is already off\n",
1408                                         __func__, __LINE__, phy->inst);
1409                 return 0;
1410         }
1411
1412         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1413                 utmip_powerdown_pmc_wake_detect(phy);
1414
1415                 val = readl(base + USB_SUSP_CTRL);
1416                 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
1417                 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
1418                 writel(val, base + USB_SUSP_CTRL);
1419
1420                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1421                 val |= UTMIP_PD_CHRG;
1422                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1423         } else {
1424                 phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
1425                                 HOSTPC1_DEVLC_PSPD_MASK;
1426
1427                 /* Disable interrupts */
1428                 writel(0, base + USB_USBINTR);
1429
1430                 /* Clear the run bit to stop SOFs - 2LS WAR */
1431                 val = readl(base + USB_USBCMD);
1432                 val &= ~USB_USBCMD_RS;
1433                 writel(val, base + USB_USBCMD);
1434
1435                 if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
1436                                                          USB_USBSTS_HCH, 2000)) {
1437                         pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
1438                 }
1439                 utmip_setup_pmc_wake_detect(phy);
1440         }
1441
1442         if (!phy->pdata->u_data.host.hot_plug) {
1443                 val = readl(base + UTMIP_XCVR_CFG0);
1444                 val |= (UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
1445                          UTMIP_FORCE_PDZI_POWERDOWN);
1446                 writel(val, base + UTMIP_XCVR_CFG0);
1447         }
1448
1449         val = readl(base + UTMIP_XCVR_CFG1);
1450         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1451                    UTMIP_FORCE_PDDR_POWERDOWN;
1452         writel(val, base + UTMIP_XCVR_CFG1);
1453
1454         val = readl(base + UTMIP_BIAS_CFG1);
1455         val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
1456         writel(val, base + UTMIP_BIAS_CFG1);
1457
1458         utmi_phy_pad_power_off(phy);
1459
1460         if (phy->pdata->u_data.host.hot_plug) {
1461                 bool enable_hotplug = true;
1462                 /* if it is OTG port then make sure to enable hot-plug feature
1463                    only if host adaptor is connected, i.e id is low */
1464                 if (phy->pdata->port_otg) {
1465                         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1466                         enable_hotplug = (val & USB_ID_STATUS) ? false : true;
1467                 }
1468                 if (enable_hotplug) {
1469                         val = readl(base + USB_PORTSC);
1470                         val |= USB_PORTSC_WKCN;
1471                         writel(val, base + USB_PORTSC);
1472
1473                         val = readl(base + USB_SUSP_CTRL);
1474                         val |= USB_PHY_CLK_VALID_INT_ENB;
1475                         writel(val, base + USB_SUSP_CTRL);
1476                 } else {
1477                         /* Disable PHY clock valid interrupts while going into suspend*/
1478                         val = readl(base + USB_SUSP_CTRL);
1479                         val &= ~USB_PHY_CLK_VALID_INT_ENB;
1480                         writel(val, base + USB_SUSP_CTRL);
1481                 }
1482         }
1483
1484         val = readl(base + HOSTPC1_DEVLC);
1485         val |= HOSTPC1_DEVLC_PHCD;
1486         writel(val, base + HOSTPC1_DEVLC);
1487
1488         if (!phy->pdata->u_data.host.hot_plug) {
1489                 val = readl(base + USB_SUSP_CTRL);
1490                 val |= UTMIP_RESET;
1491                 writel(val, base + USB_SUSP_CTRL);
1492         }
1493
1494         phy->phy_clk_on = false;
1495         phy->hw_accessible = false;
1496
1497         PHY_DBG("%s(%d) inst:[%d] END\n", __func__, __LINE__, phy->inst);
1498
1499         return 0;
1500 }
1501
1502
1503 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
1504 {
1505         unsigned long val;
1506         void __iomem *base = phy->regs;
1507         struct tegra_utmi_config *config = &phy->pdata->u_cfg.utmi;
1508
1509         PHY_DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1510         if (phy->phy_clk_on) {
1511                 PHY_DBG("%s(%d) inst:[%d] phy clk is already On\n",
1512                                         __func__, __LINE__, phy->inst);
1513                 return 0;
1514         }
1515         val = readl(base + USB_SUSP_CTRL);
1516         val |= UTMIP_RESET;
1517         writel(val, base + USB_SUSP_CTRL);
1518
1519         val = readl(base + UTMIP_TX_CFG0);
1520         val |= UTMIP_FS_PREABMLE_J;
1521         writel(val, base + UTMIP_TX_CFG0);
1522
1523         val = readl(base + UTMIP_HSRX_CFG0);
1524         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
1525         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
1526         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
1527         writel(val, base + UTMIP_HSRX_CFG0);
1528
1529         val = readl(base + UTMIP_HSRX_CFG1);
1530         val &= ~UTMIP_HS_SYNC_START_DLY(~0);
1531         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
1532         writel(val, base + UTMIP_HSRX_CFG1);
1533
1534         val = readl(base + UTMIP_DEBOUNCE_CFG0);
1535         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
1536         val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
1537         writel(val, base + UTMIP_DEBOUNCE_CFG0);
1538
1539         val = readl(base + UTMIP_MISC_CFG0);
1540         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
1541         writel(val, base + UTMIP_MISC_CFG0);
1542
1543         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1544                 val = readl(base + USB_SUSP_CTRL);
1545                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
1546                 writel(val, base + USB_SUSP_CTRL);
1547
1548                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1549                 val &= ~UTMIP_PD_CHRG;
1550                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1551         } else {
1552                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1553                 val |= UTMIP_PD_CHRG;
1554                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1555         }
1556
1557         utmi_phy_pad_power_on(phy);
1558
1559         val = readl(base + UTMIP_XCVR_CFG0);
1560         val &= ~(UTMIP_XCVR_LSBIAS_SEL | UTMIP_FORCE_PD_POWERDOWN |
1561                  UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN |
1562                  UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_LSFSLEW(~0) |
1563                  UTMIP_XCVR_LSRSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
1564         val |= UTMIP_XCVR_SETUP(phy->utmi_xcvr_setup);
1565         val |= UTMIP_XCVR_SETUP_MSB(XCVR_SETUP_MSB_CALIB(phy->utmi_xcvr_setup));
1566         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
1567         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
1568         if (!config->xcvr_use_lsb)
1569                 val |= UTMIP_XCVR_HSSLEW_MSB(0x8);
1570         writel(val, base + UTMIP_XCVR_CFG0);
1571
1572         val = readl(base + UTMIP_XCVR_CFG1);
1573         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1574                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
1575         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
1576         writel(val, base + UTMIP_XCVR_CFG1);
1577
1578         val = readl(base + UTMIP_BIAS_CFG1);
1579         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
1580         val |= UTMIP_BIAS_PDTRK_COUNT(phy->freq->pdtrk_count);
1581         writel(val, base + UTMIP_BIAS_CFG1);
1582
1583         val = readl(base + UTMIP_SPARE_CFG0);
1584         val &= ~FUSE_SETUP_SEL;
1585         val |= FUSE_ATERM_SEL;
1586         writel(val, base + UTMIP_SPARE_CFG0);
1587
1588         val = readl(base + USB_SUSP_CTRL);
1589         val |= UTMIP_PHY_ENABLE;
1590         writel(val, base + USB_SUSP_CTRL);
1591
1592         val = readl(base + USB_SUSP_CTRL);
1593         val &= ~UTMIP_RESET;
1594         writel(val, base + USB_SUSP_CTRL);
1595
1596         val = readl(base + HOSTPC1_DEVLC);
1597         val &= ~HOSTPC1_DEVLC_PHCD;
1598         writel(val, base + HOSTPC1_DEVLC);
1599
1600         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1601                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500))
1602                 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
1603
1604         utmi_phy_enable_trking_data(phy);
1605
1606         if (phy->inst == 2)
1607                 writel(0, base + ICUSB_CTRL);
1608
1609         val = readl(base + USB_USBMODE);
1610         val &= ~USB_USBMODE_MASK;
1611         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST)
1612                 val |= USB_USBMODE_HOST;
1613         else
1614                 val |= USB_USBMODE_DEVICE;
1615         writel(val, base + USB_USBMODE);
1616
1617         val = readl(base + HOSTPC1_DEVLC);
1618         val &= ~HOSTPC1_DEVLC_PTS(~0);
1619         val |= HOSTPC1_DEVLC_STS;
1620         writel(val, base + HOSTPC1_DEVLC);
1621
1622         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE)
1623                 utmip_powerup_pmc_wake_detect(phy);
1624         phy->phy_clk_on = true;
1625         phy->hw_accessible = true;
1626         PHY_DBG("%s(%d) End inst:[%d]\n", __func__, __LINE__, phy->inst);
1627         return 0;
1628 }
1629
1630 static void utmi_phy_restore_start(struct tegra_usb_phy *phy)
1631 {
1632         unsigned long val;
1633         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1634         int inst = phy->inst;
1635
1636         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1637         val = readl(pmc_base + UTMIP_UHSIC_STATUS);
1638         /* check whether we wake up from the remote resume */
1639         if (UTMIP_WALK_PTR_VAL(inst) & val) {
1640                 phy->remote_wakeup = true;
1641         } else {
1642                 if (!((UTMIP_USBON_VAL(phy->inst) |
1643                         UTMIP_USBOP_VAL(phy->inst)) & val)) {
1644                                 utmip_phy_disable_pmc_bus_ctrl(phy);
1645                 }
1646         }
1647         utmi_phy_enable_obs_bus(phy);
1648 }
1649
1650 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
1651 {
1652         unsigned long val;
1653         void __iomem *base = phy->regs;
1654         int wait_time_us = 25000; /* FPR should be set by this time */
1655
1656         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1657         /* check whether we wake up from the remote resume */
1658         if (phy->remote_wakeup) {
1659                 /* wait until SUSPEND and RESUME bit is cleared on remote resume */
1660                 do {
1661                         val = readl(base + USB_PORTSC);
1662                         udelay(1);
1663                         if (wait_time_us == 0) {
1664                                 PHY_DBG("%s PMC REMOTE WAKEUP FPR timeout val = 0x%x instance = %d\n", __func__, val, phy->inst);
1665                                 utmip_phy_disable_pmc_bus_ctrl(phy);
1666                                 utmi_phy_post_resume(phy);
1667                                 return;
1668                         }
1669                         wait_time_us--;
1670                 } while (val & (USB_PORTSC_RESUME | USB_PORTSC_SUSP));
1671
1672                 /* wait for 25 ms to port resume complete */
1673                 msleep(25);
1674                 /* disable PMC master control */
1675                 utmip_phy_disable_pmc_bus_ctrl(phy);
1676
1677                 /* Clear PCI and SRI bits to avoid an interrupt upon resume */
1678                 val = readl(base + USB_USBSTS);
1679                 writel(val, base + USB_USBSTS);
1680                 /* wait to avoid SOF if there is any */
1681                 if (usb_phy_reg_status_wait(base + USB_USBSTS,
1682                         USB_USBSTS_SRI, USB_USBSTS_SRI, 2500) < 0) {
1683                         pr_err("%s: timeout waiting for SOF\n", __func__);
1684                 }
1685                 utmi_phy_post_resume(phy);
1686         }
1687 }
1688
1689 static int utmi_phy_resume(struct tegra_usb_phy *phy)
1690 {
1691         int status = 0;
1692         unsigned long val;
1693         void __iomem *base = phy->regs;
1694
1695         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1696         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) {
1697                 if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
1698                         utmi_phy_restore_start(phy);
1699                         usb_phy_bringup_host_controller(phy);
1700                         utmi_phy_restore_end(phy);
1701                 } else {
1702                         /* device is plugged in when system is in LP0 */
1703                         /* bring up the controller from LP0*/
1704                         val = readl(base + USB_USBCMD);
1705                         val |= USB_CMD_RESET;
1706                         writel(val, base + USB_USBCMD);
1707
1708                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1709                                 USB_CMD_RESET, 0, 2500) < 0) {
1710                                 pr_err("%s: timeout waiting for reset\n", __func__);
1711                         }
1712
1713                         val = readl(base + USB_USBMODE);
1714                         val &= ~USB_USBMODE_MASK;
1715                         val |= USB_USBMODE_HOST;
1716                         writel(val, base + USB_USBMODE);
1717
1718                         val = readl(base + HOSTPC1_DEVLC);
1719                         val &= ~HOSTPC1_DEVLC_PTS(~0);
1720                         val |= HOSTPC1_DEVLC_STS;
1721                         writel(val, base + HOSTPC1_DEVLC);
1722
1723                         writel(USB_USBCMD_RS, base + USB_USBCMD);
1724
1725                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1726                                 USB_USBCMD_RS, USB_USBCMD_RS, 2500) < 0) {
1727                                 pr_err("%s: timeout waiting for run bit\n", __func__);
1728                         }
1729
1730                         /* Enable Port Power */
1731                         val = readl(base + USB_PORTSC);
1732                         val |= USB_PORTSC_PP;
1733                         writel(val, base + USB_PORTSC);
1734                         udelay(10);
1735
1736                         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1737                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1738                 }
1739         }
1740
1741         return status;
1742 }
1743
1744 static bool utmi_phy_charger_detect(struct tegra_usb_phy *phy)
1745 {
1746         unsigned long val;
1747         void __iomem *base = phy->regs;
1748         bool status;
1749
1750         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1751         if (phy->pdata->op_mode != TEGRA_USB_OPMODE_DEVICE) {
1752                 /* Charger detection is not there for ULPI
1753                  * return Charger not available */
1754                 return false;
1755         }
1756
1757         /* Enable charger detection logic */
1758         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1759         val |= UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN;
1760         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1761
1762         /* Source should be on for 100 ms as per USB charging spec */
1763         msleep(TDP_SRC_ON_MS);
1764
1765         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1766         /* If charger is not connected disable the interrupt */
1767         val &= ~VDAT_DET_INT_EN;
1768         val |= VDAT_DET_CHG_DET;
1769         writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
1770
1771         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1772         if (val & VDAT_DET_STS)
1773                 status = true;
1774         else
1775                 status = false;
1776
1777         /* Disable charger detection logic */
1778         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1779         val &= ~(UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN);
1780         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1781
1782         /* Delay of 40 ms before we pull the D+ as per battery charger spec */
1783         msleep(TDPSRC_CON_MS);
1784
1785         return status;
1786 }
1787
1788 static void uhsic_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
1789 {
1790         unsigned long val;
1791         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1792
1793         /* turn on pad detectors for HSIC*/
1794         val = readl(pmc_base + PMC_USB_AO);
1795         val &= ~(HSIC_RESERVED_P0 | STROBE_VAL_PD_P0 | DATA_VAL_PD_P0);
1796         writel(val, pmc_base + PMC_USB_AO);
1797
1798         /* Disable PMC master mode by clearing MASTER_EN */
1799         val = readl(pmc_base + PMC_SLEEP_CFG);
1800         val &= ~(UHSIC_MASTER_ENABLE_P0);
1801         writel(val, pmc_base + PMC_SLEEP_CFG);
1802         mdelay(1);
1803 }
1804
1805 static void uhsic_setup_pmc_wake_detect(struct tegra_usb_phy *phy)
1806 {
1807         unsigned long val;
1808         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1809         void __iomem *base = phy->regs;
1810         bool port_connected;
1811
1812         DBG("%s:%d\n", __func__, __LINE__);
1813
1814         /* check for port connect status */
1815         val = readl(base + USB_PORTSC);
1816         port_connected = val & USB_PORTSC_CCS;
1817
1818         if (!port_connected)
1819                 return;
1820
1821         /*Set PMC MASTER bits to do the following
1822         * a. Take over the hsic drivers
1823         * b. set up such that it will take over resume
1824         *        if remote wakeup is detected
1825         * Prepare PMC to take over suspend-wake detect-drive resume until USB
1826         * controller ready
1827         */
1828
1829         /* disable master enable in PMC */
1830         val = readl(pmc_base + PMC_SLEEP_CFG);
1831         val &= ~UHSIC_MASTER_ENABLE_P0;
1832         writel(val, pmc_base + PMC_SLEEP_CFG);
1833
1834         /* UTMIP_PWR_PX=1 for power savings mode */
1835         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
1836         val |= UHSIC_PWR;
1837         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
1838
1839
1840         /* Enable which type of event can trigger a walk,
1841         * in this case usb_line_wake */
1842         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
1843         val |= UHSIC_LINEVAL_WALK_EN;
1844         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
1845
1846         /* program walk sequence, maintain a J, followed by a driven K
1847         * to signal a resume once an wake event is detected */
1848
1849         val = readl(pmc_base + PMC_SLEEPWALK_UHSIC);
1850
1851         val &= ~UHSIC_DATA_RPU_A;
1852         val |=  UHSIC_DATA_RPD_A;
1853         val &= ~UHSIC_STROBE_RPD_A;
1854         val |=  UHSIC_STROBE_RPU_A;
1855         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1856
1857         val &= ~UHSIC_DATA_RPD_B;
1858         val |=  UHSIC_DATA_RPU_B;
1859         val &= ~UHSIC_STROBE_RPU_B;
1860         val |=  UHSIC_STROBE_RPD_B;
1861         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1862
1863         val &= ~UHSIC_DATA_RPD_C;
1864         val |=  UHSIC_DATA_RPU_C;
1865         val &= ~UHSIC_STROBE_RPU_C;
1866         val |=  UHSIC_STROBE_RPD_C;
1867         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1868
1869         val &= ~UHSIC_DATA_RPD_D;
1870         val |=  UHSIC_DATA_RPU_D;
1871         val &= ~UHSIC_STROBE_RPU_D;
1872         val |=  UHSIC_STROBE_RPD_D;
1873         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1874
1875         /* turn on pad detectors */
1876         val = readl(pmc_base + PMC_USB_AO);
1877         val &= ~(STROBE_VAL_PD_P0 | DATA_VAL_PD_P0);
1878         writel(val, pmc_base + PMC_USB_AO);
1879         /* Add small delay before usb detectors provide stable line values */
1880         udelay(1);
1881
1882         phy->remote_wakeup = false;
1883
1884         /* Turn over pad configuration to PMC  for line wake events*/
1885         val = readl(pmc_base + PMC_SLEEP_CFG);
1886         val &= ~UHSIC_WAKE_VAL(~0);
1887         val |= UHSIC_WAKE_VAL(WAKE_VAL_SD10);
1888         val |= UHSIC_MASTER_ENABLE;
1889         writel(val, pmc_base + PMC_SLEEP_CFG);
1890
1891         val = readl(base + UHSIC_PMC_WAKEUP0);
1892         val |= EVENT_INT_ENB;
1893         writel(val, base + UHSIC_PMC_WAKEUP0);
1894
1895         DBG("%s:PMC enabled for HSIC remote wakeup\n", __func__);
1896 }
1897
1898 static void uhsic_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy)
1899 {
1900         unsigned long val;
1901         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1902         void __iomem *base = phy->regs;
1903
1904         DBG("%s (%d)\n", __func__, __LINE__);
1905         val = readl(pmc_base + PMC_SLEEP_CFG);
1906         val &= ~UHSIC_WAKE_VAL(0x0);
1907         val |= UHSIC_WAKE_VAL(WAKE_VAL_NONE);
1908         writel(val, pmc_base + PMC_SLEEP_CFG);
1909
1910         val = readl(pmc_base + PMC_TRIGGERS);
1911         val |= UHSIC_CLR_WAKE_ALARM_P0 | UHSIC_CLR_WALK_PTR_P0;
1912         writel(val, pmc_base + PMC_TRIGGERS);
1913
1914         val = readl(base + UHSIC_PMC_WAKEUP0);
1915         val &= ~EVENT_INT_ENB;
1916         writel(val, base + UHSIC_PMC_WAKEUP0);
1917
1918         /* Disable PMC master mode by clearing MASTER_EN */
1919         val = readl(pmc_base + PMC_SLEEP_CFG);
1920         val &= ~(UHSIC_MASTER_ENABLE);
1921         writel(val, pmc_base + PMC_SLEEP_CFG);
1922
1923         /* turn off pad detectors */
1924         val = readl(pmc_base + PMC_USB_AO);
1925         val |= (STROBE_VAL_PD_P0 | DATA_VAL_PD_P0);
1926         writel(val, pmc_base + PMC_USB_AO);
1927
1928         phy->remote_wakeup = false;
1929 }
1930
1931 static bool uhsic_phy_remotewake_detected(struct tegra_usb_phy *phy)
1932 {
1933         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1934         void __iomem *base = phy->regs;
1935         u32 val;
1936
1937         val = readl(base + UHSIC_PMC_WAKEUP0);
1938         if (val & EVENT_INT_ENB) {
1939                 val = readl(pmc_base + UTMIP_UHSIC_STATUS);
1940                 if (UHSIC_WAKE_ALARM & val) {
1941                         val = readl(pmc_base + PMC_SLEEP_CFG);
1942                         val &= ~UHSIC_WAKE_VAL(0x0);
1943                         val |= UHSIC_WAKE_VAL(WAKE_VAL_NONE);
1944                         writel(val, pmc_base + PMC_SLEEP_CFG);
1945
1946                         val = readl(pmc_base + PMC_TRIGGERS);
1947                         val |= UHSIC_CLR_WAKE_ALARM_P0 | UHSIC_CLR_WALK_PTR_P0;
1948                         writel(val, pmc_base + PMC_TRIGGERS);
1949
1950                         val = readl(base + UHSIC_PMC_WAKEUP0);
1951                         val &= ~EVENT_INT_ENB;
1952                         writel(val, base + UHSIC_PMC_WAKEUP0);
1953                         phy->remote_wakeup = true;
1954                         DBG("%s:PMC remote wakeup detected for HSIC\n", __func__);
1955                         return true;
1956                 }
1957         }
1958         return false;
1959 }
1960
1961 static int uhsic_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1962 {
1963         DBG("%s(%d)\n", __func__, __LINE__);
1964
1965         if (!remote_wakeup)
1966                 usb_phy_wait_for_sof(phy);
1967
1968         return 0;
1969 }
1970
1971 static int uhsic_phy_post_resume(struct tegra_usb_phy *phy)
1972 {
1973         unsigned long val;
1974         void __iomem *base = phy->regs;
1975
1976         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1977         val = readl(base + USB_TXFILLTUNING);
1978         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
1979                 val = USB_FIFO_TXFILL_THRES(0x10);
1980                 writel(val, base + USB_TXFILLTUNING);
1981         }
1982
1983         return 0;
1984 }
1985
1986 static void uhsic_phy_restore_start(struct tegra_usb_phy *phy)
1987 {
1988         unsigned long val;
1989         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1990         void __iomem *base = phy->regs;
1991
1992         val = readl(pmc_base + UTMIP_UHSIC_STATUS);
1993
1994         /* check whether we wake up from the remote resume */
1995         if (UHSIC_WALK_PTR_VAL & val) {
1996                 phy->remote_wakeup = true;
1997         } else {
1998                 if (!((UHSIC_STROBE_VAL_P0 | UHSIC_DATA_VAL_P0) & val)) {
1999                                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2000                 } else {
2001                         DBG("%s(%d): setting pretend connect\n", __func__, __LINE__);
2002                         val = readl(base + UHSIC_CMD_CFG0);
2003                         val |= UHSIC_PRETEND_CONNECT_DETECT;
2004                         writel(val, base + UHSIC_CMD_CFG0);
2005                 }
2006         }
2007 }
2008
2009 static void uhsic_phy_restore_end(struct tegra_usb_phy *phy)
2010 {
2011
2012         unsigned long val;
2013         void __iomem *base = phy->regs;
2014         int wait_time_us = 3000; /* FPR should be set by this time */
2015
2016         DBG("%s(%d)\n", __func__, __LINE__);
2017
2018         /* check whether we wake up from the remote resume */
2019         if (phy->remote_wakeup) {
2020                 /* wait until FPR bit is set automatically on remote resume */
2021                 do {
2022                         val = readl(base + USB_PORTSC);
2023                         udelay(1);
2024                         if (wait_time_us == 0) {
2025                                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2026                                 uhsic_phy_post_resume(phy);
2027                                 return;
2028                         }
2029                         wait_time_us--;
2030                 } while (!(val & USB_PORTSC_RESUME));
2031                 /* wait for 25 ms to port resume complete */
2032                 msleep(25);
2033                 /* disable PMC master control */
2034                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2035
2036                 /* Clear PCI and SRI bits to avoid an interrupt upon resume */
2037                 val = readl(base + USB_USBSTS);
2038                 writel(val, base + USB_USBSTS);
2039                 /* wait to avoid SOF if there is any */
2040                 if (usb_phy_reg_status_wait(base + USB_USBSTS,
2041                         USB_USBSTS_SRI, USB_USBSTS_SRI, 2500)) {
2042                         pr_warn("%s: timeout waiting for SOF\n", __func__);
2043                 }
2044                 uhsic_phy_post_resume(phy);
2045         } else {
2046                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2047         }
2048
2049         /* Set RUN bit */
2050         val = readl(base + USB_USBCMD);
2051         val |= USB_USBCMD_RS;
2052         writel(val, base + USB_USBCMD);
2053         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2054                                                  USB_USBCMD_RS, 2000)) {
2055                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2056                 return;
2057         }
2058 }
2059
2060 static int uhsic_phy_open(struct tegra_usb_phy *phy)
2061 {
2062         unsigned long parent_rate;
2063         int i;
2064
2065         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2066         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
2067         for (i = 0; i < ARRAY_SIZE(uhsic_freq_table); i++) {
2068                 if (uhsic_freq_table[i].freq == parent_rate) {
2069                         phy->freq = &uhsic_freq_table[i];
2070                         break;
2071                 }
2072         }
2073         if (!phy->freq) {
2074                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
2075                 return -EINVAL;
2076         }
2077
2078         uhsic_powerup_pmc_wake_detect(phy);
2079
2080         return 0;
2081 }
2082
2083 static int uhsic_phy_irq(struct tegra_usb_phy *phy)
2084 {
2085         usb_phy_fence_read(phy);
2086         /* check if there is any remote wake event */
2087         if (uhsic_phy_remotewake_detected(phy))
2088                 pr_info("%s: uhsic remote wake detected\n", __func__);
2089         return IRQ_HANDLED;
2090 }
2091
2092 static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
2093 {
2094         unsigned long val;
2095         void __iomem *base = phy->regs;
2096         struct tegra_hsic_config *config = &phy->pdata->u_cfg.hsic;
2097
2098         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2099
2100         if (phy->phy_clk_on) {
2101                 DBG("%s(%d) inst:[%d] phy clk is already On\n",
2102                                         __func__, __LINE__, phy->inst);
2103                 return 0;
2104         }
2105
2106         val = readl(base + UHSIC_PADS_CFG1);
2107         val &= ~(UHSIC_PD_BG | UHSIC_PD_TX | UHSIC_PD_TRK | UHSIC_PD_RX |
2108                         UHSIC_PD_ZI | UHSIC_RPD_DATA | UHSIC_RPD_STROBE);
2109         val |= UHSIC_RX_SEL;
2110         writel(val, base + UHSIC_PADS_CFG1);
2111         udelay(2);
2112
2113         val = readl(base + USB_SUSP_CTRL);
2114         val |= UHSIC_RESET;
2115         writel(val, base + USB_SUSP_CTRL);
2116         udelay(30);
2117
2118         val = readl(base + USB_SUSP_CTRL);
2119         val |= UHSIC_PHY_ENABLE;
2120         writel(val, base + USB_SUSP_CTRL);
2121
2122         val = readl(base + UHSIC_HSRX_CFG0);
2123         val |= UHSIC_IDLE_WAIT(config->idle_wait_delay);
2124         val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(config->elastic_underrun_limit);
2125         val |= UHSIC_ELASTIC_OVERRUN_LIMIT(config->elastic_overrun_limit);
2126         writel(val, base + UHSIC_HSRX_CFG0);
2127
2128         val = readl(base + UHSIC_HSRX_CFG1);
2129         val |= UHSIC_HS_SYNC_START_DLY(config->sync_start_delay);
2130         writel(val, base + UHSIC_HSRX_CFG1);
2131
2132         /* WAR HSIC TX */
2133         val = readl(base + UHSIC_TX_CFG0);
2134         val &= ~UHSIC_HS_READY_WAIT_FOR_VALID;
2135         writel(val, base + UHSIC_TX_CFG0);
2136
2137         val = readl(base + UHSIC_MISC_CFG0);
2138         val |= UHSIC_SUSPEND_EXIT_ON_EDGE;
2139         /* Disable generic bus reset, to allow AP30 specific bus reset*/
2140         val |= UHSIC_DISABLE_BUSRESET;
2141         writel(val, base + UHSIC_MISC_CFG0);
2142
2143         val = readl(base + UHSIC_MISC_CFG1);
2144         val |= UHSIC_PLLU_STABLE_COUNT(phy->freq->stable_count);
2145         writel(val, base + UHSIC_MISC_CFG1);
2146
2147         val = readl(base + UHSIC_PLL_CFG1);
2148         val |= UHSIC_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
2149         val |= UHSIC_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count);
2150         writel(val, base + UHSIC_PLL_CFG1);
2151
2152         val = readl(base + USB_SUSP_CTRL);
2153         val &= ~(UHSIC_RESET);
2154         writel(val, base + USB_SUSP_CTRL);
2155         udelay(2);
2156
2157         val = readl(base + USB_USBMODE);
2158         val |= USB_USBMODE_HOST;
2159         writel(val, base + USB_USBMODE);
2160
2161         /* Change the USB controller PHY type to HSIC */
2162         val = readl(base + HOSTPC1_DEVLC);
2163         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
2164         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2165         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
2166         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2167         val &= ~HOSTPC1_DEVLC_STS;
2168         writel(val, base + HOSTPC1_DEVLC);
2169
2170         val = readl(base + USB_TXFILLTUNING);
2171         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
2172                 val = USB_FIFO_TXFILL_THRES(0x10);
2173                 writel(val, base + USB_TXFILLTUNING);
2174         }
2175
2176         val = readl(base + USB_PORTSC);
2177         val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN);
2178         writel(val, base + USB_PORTSC);
2179
2180         val = readl(base + UHSIC_PADS_CFG0);
2181         val &= ~(UHSIC_TX_RTUNEN);
2182         /* set Rtune impedance to 50 ohm */
2183         val |= UHSIC_TX_RTUNE(8);
2184         writel(val, base + UHSIC_PADS_CFG0);
2185
2186         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
2187                                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500)) {
2188                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2189                 return -ETIMEDOUT;
2190         }
2191
2192         phy->phy_clk_on = true;
2193         phy->hw_accessible = true;
2194
2195         return 0;
2196 }
2197
2198 static int uhsic_phy_power_off(struct tegra_usb_phy *phy)
2199 {
2200         unsigned long val;
2201         void __iomem *base = phy->regs;
2202
2203         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2204         if (!phy->phy_clk_on) {
2205                 DBG("%s(%d) inst:[%d] phy clk is already off\n",
2206                                         __func__, __LINE__, phy->inst);
2207                 return 0;
2208         }
2209
2210         phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
2211                         HOSTPC1_DEVLC_PSPD_MASK;
2212
2213         /* Disable interrupts */
2214         writel(0, base + USB_USBINTR);
2215
2216         uhsic_setup_pmc_wake_detect(phy);
2217
2218         val = readl(base + HOSTPC1_DEVLC);
2219         val |= HOSTPC1_DEVLC_PHCD;
2220         writel(val, base + HOSTPC1_DEVLC);
2221
2222         phy->phy_clk_on = false;
2223         phy->hw_accessible = false;
2224
2225         return 0;
2226 }
2227
2228 static int uhsic_phy_bus_port_power(struct tegra_usb_phy *phy)
2229 {
2230         unsigned long val;
2231         void __iomem *base = phy->regs;
2232
2233         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2234
2235         val = readl(base + USB_USBMODE);
2236         val |= USB_USBMODE_HOST;
2237         writel(val, base + USB_USBMODE);
2238
2239         /* Change the USB controller PHY type to HSIC */
2240         val = readl(base + HOSTPC1_DEVLC);
2241         val &= ~(HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK));
2242         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2243         val &= ~(HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK));
2244         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2245         writel(val, base + HOSTPC1_DEVLC);
2246
2247         val = readl(base + UHSIC_MISC_CFG0);
2248         val |= UHSIC_DETECT_SHORT_CONNECT;
2249         writel(val, base + UHSIC_MISC_CFG0);
2250         udelay(1);
2251
2252         val = readl(base + UHSIC_MISC_CFG0);
2253         val |= UHSIC_FORCE_XCVR_MODE;
2254         writel(val, base + UHSIC_MISC_CFG0);
2255
2256         val = readl(base + UHSIC_PADS_CFG1);
2257         val &= ~UHSIC_RPD_STROBE;
2258         writel(val, base + UHSIC_PADS_CFG1);
2259
2260         if (phy->pdata->ops && phy->pdata->ops->port_power)
2261                 phy->pdata->ops->port_power();
2262
2263         if (usb_phy_reg_status_wait(base + UHSIC_STAT_CFG0,
2264                         UHSIC_CONNECT_DETECT, UHSIC_CONNECT_DETECT, 25000)) {
2265                 pr_err("%s: timeout waiting for UHSIC_CONNECT_DETECT\n",
2266                                                                 __func__);
2267                 return -ETIMEDOUT;
2268         }
2269
2270         return 0;
2271 }
2272
2273 static int uhsic_phy_bus_reset(struct tegra_usb_phy *phy)
2274 {
2275         unsigned long val;
2276         void __iomem *base = phy->regs;
2277
2278         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2279
2280         /* Change the USB controller PHY type to HSIC */
2281         val = readl(base + HOSTPC1_DEVLC);
2282         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
2283         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2284         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
2285         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2286         val &= ~HOSTPC1_DEVLC_STS;
2287         writel(val, base + HOSTPC1_DEVLC);
2288         /* wait here, otherwise HOSTPC1_DEVLC_PSPD will timeout */
2289         mdelay(5);
2290
2291         val = readl(base + USB_PORTSC);
2292         val |= USB_PORTSC_PTC(5);
2293         writel(val, base + USB_PORTSC);
2294         udelay(2);
2295
2296         val = readl(base + USB_PORTSC);
2297         val &= ~(USB_PORTSC_PTC(~0));
2298         writel(val, base + USB_PORTSC);
2299         udelay(2);
2300
2301         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_LS(0),
2302                                                  0, 2000)) {
2303                 pr_err("%s: timeout waiting for USB_PORTSC_LS\n", __func__);
2304                 return -ETIMEDOUT;
2305         }
2306
2307         /* Poll until CCS is enabled */
2308         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
2309                                                  USB_PORTSC_CCS, 2000)) {
2310                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
2311                 return -ETIMEDOUT;
2312         }
2313
2314         if (usb_phy_reg_status_wait(base + HOSTPC1_DEVLC,
2315                         HOSTPC1_DEVLC_PSPD(2),
2316                         HOSTPC1_DEVLC_PSPD(2), 2000) < 0) {
2317                 pr_err("%s: timeout waiting hsic high speed configuration\n",
2318                                                 __func__);
2319                         return -ETIMEDOUT;
2320         }
2321
2322         val = readl(base + USB_USBCMD);
2323         val &= ~USB_USBCMD_RS;
2324         writel(val, base + USB_USBCMD);
2325
2326         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
2327                                                  USB_USBSTS_HCH, 2000)) {
2328                 pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
2329                 return -ETIMEDOUT;
2330         }
2331
2332         val = readl(base + UHSIC_PADS_CFG1);
2333         val &= ~UHSIC_RPU_STROBE;
2334         val |= UHSIC_RPD_STROBE;
2335         writel(val, base + UHSIC_PADS_CFG1);
2336
2337         mdelay(50);
2338
2339         val = readl(base + UHSIC_PADS_CFG1);
2340         val &= ~UHSIC_RPD_STROBE;
2341         val |= UHSIC_RPU_STROBE;
2342         writel(val, base + UHSIC_PADS_CFG1);
2343
2344         val = readl(base + USB_USBCMD);
2345         val |= USB_USBCMD_RS;
2346         writel(val, base + USB_USBCMD);
2347
2348         val = readl(base + UHSIC_PADS_CFG1);
2349         val &= ~UHSIC_RPU_STROBE;
2350         writel(val, base + UHSIC_PADS_CFG1);
2351
2352         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2353                                                  USB_USBCMD_RS, 2000)) {
2354                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2355                 return -ETIMEDOUT;
2356         }
2357
2358         return 0;
2359 }
2360
2361 int uhsic_phy_resume(struct tegra_usb_phy *phy)
2362 {
2363         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2364
2365         uhsic_phy_restore_start(phy);
2366         usb_phy_bringup_host_controller(phy);
2367         uhsic_phy_restore_end(phy);
2368
2369         return 0;
2370 }
2371
2372 static void ulpi_set_trimmer(struct tegra_usb_phy *phy)
2373 {
2374         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2375         void __iomem *base = phy->regs;
2376         unsigned long val;
2377
2378         val = ULPI_DATA_TRIMMER_SEL(config->data_trimmer);
2379         val |= ULPI_STPDIRNXT_TRIMMER_SEL(config->stpdirnxt_trimmer);
2380         val |= ULPI_DIR_TRIMMER_SEL(config->dir_trimmer);
2381         writel(val, base + ULPI_TIMING_CTRL_1);
2382         udelay(10);
2383
2384         val |= ULPI_DATA_TRIMMER_LOAD;
2385         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
2386         val |= ULPI_DIR_TRIMMER_LOAD;
2387         writel(val, base + ULPI_TIMING_CTRL_1);
2388 }
2389
2390 static void reset_utmip_uhsic(void __iomem *base)
2391 {
2392         unsigned long val;
2393
2394         val = readl(base + USB_SUSP_CTRL);
2395         val |= UHSIC_RESET;
2396         writel(val, base + USB_SUSP_CTRL);
2397
2398         val = readl(base + USB_SUSP_CTRL);
2399         val |= UTMIP_RESET;
2400         writel(val, base + USB_SUSP_CTRL);
2401 }
2402
2403 static void ulpi_set_host(void __iomem *base)
2404 {
2405         unsigned long val;
2406
2407         val = readl(base + USB_USBMODE);
2408         val |= USB_USBMODE_HOST;
2409         writel(val, base + USB_USBMODE);
2410
2411         val = readl(base + HOSTPC1_DEVLC);
2412         val |= HOSTPC1_DEVLC_PTS(2);
2413         writel(val, base + HOSTPC1_DEVLC);
2414 }
2415
2416
2417 static int ulpi_null_phy_power_off(struct tegra_usb_phy *phy)
2418 {
2419         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2420
2421         if (!phy->phy_clk_on) {
2422                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
2423                                                         __LINE__, phy->inst);
2424                 return 0;
2425         }
2426
2427         phy->phy_clk_on = false;
2428         phy->hw_accessible = false;
2429
2430         return 0;
2431 }
2432
2433 static int ulpi_null_phy_init(struct tegra_usb_phy *phy)
2434 {
2435         unsigned long val;
2436         void __iomem *base = phy->regs;
2437
2438         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2439         val = readl(base + ULPIS2S_CTRL);
2440         val |=  ULPIS2S_SLV0_CLAMP_XMIT;
2441         writel(val, base + ULPIS2S_CTRL);
2442
2443         val = readl(base + USB_SUSP_CTRL);
2444         val |= ULPIS2S_SLV0_RESET;
2445         writel(val, base + USB_SUSP_CTRL);
2446         udelay(10);
2447
2448         return 0;
2449 }
2450
2451 static int ulpi_null_phy_irq(struct tegra_usb_phy *phy)
2452 {
2453         usb_phy_fence_read(phy);
2454         return IRQ_HANDLED;
2455 }
2456
2457 static int ulpi_null_phy_cmd_reset(struct tegra_usb_phy *phy)
2458 {
2459         unsigned long val;
2460         void __iomem *base = phy->regs;
2461
2462         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2463         ulpi_set_host(base);
2464
2465         /* remove slave0 reset */
2466         val = readl(base + USB_SUSP_CTRL);
2467         val &= ~ULPIS2S_SLV0_RESET;
2468         writel(val, base + USB_SUSP_CTRL);
2469
2470         val = readl(base + ULPIS2S_CTRL);
2471         val &=  ~ULPIS2S_SLV0_CLAMP_XMIT;
2472         writel(val, base + ULPIS2S_CTRL);
2473         udelay(10);
2474
2475         return 0;
2476 }
2477
2478 static int ulpi_null_phy_lp0_resume(struct tegra_usb_phy *phy)
2479 {
2480         unsigned long val;
2481         void __iomem *base = phy->regs;
2482
2483         ulpi_null_phy_init(phy);
2484
2485         val = readl(base + USB_USBCMD);
2486         val |= USB_CMD_RESET;
2487         writel(val, base + USB_USBCMD);
2488
2489         if (usb_phy_reg_status_wait(base + USB_USBCMD,
2490                 USB_CMD_RESET, 0, 2500) < 0) {
2491                 pr_err("%s: timeout waiting for reset\n", __func__);
2492         }
2493
2494         val = readl(base + USB_USBMODE);
2495         val &= ~USB_USBMODE_MASK;
2496         val |= USB_USBMODE_HOST;
2497         writel(val, base + USB_USBMODE);
2498
2499         ulpi_null_phy_cmd_reset(phy);
2500
2501         val = readl(base + USB_USBCMD);
2502         val |= USB_USBCMD_RS;
2503         writel(val, base + USB_USBCMD);
2504         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2505                                                  USB_USBCMD_RS, 2000)) {
2506                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2507                 return -ETIMEDOUT;
2508         }
2509
2510         /* Enable Port Power */
2511         val = readl(base + USB_PORTSC);
2512         val |= USB_PORTSC_PP;
2513         writel(val, base + USB_PORTSC);
2514         udelay(10);
2515
2516         /* disable ULPI pinmux bypass */
2517         val = readl(base + ULPI_TIMING_CTRL_0);
2518         val &= ~ULPI_OUTPUT_PINMUX_BYP;
2519         writel(val, base + ULPI_TIMING_CTRL_0);
2520
2521         return 0;
2522 }
2523
2524 static int ulpi_null_phy_power_on(struct tegra_usb_phy *phy)
2525 {
2526         unsigned long val;
2527         void __iomem *base = phy->regs;
2528         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2529         static bool cold_boot = true;
2530
2531         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2532         if (phy->phy_clk_on) {
2533                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
2534                                                         __LINE__, phy->inst);
2535                 return 0;
2536         }
2537         reset_utmip_uhsic(base);
2538
2539         /* remove ULPI PADS CLKEN reset */
2540         val = readl(base + USB_SUSP_CTRL);
2541         val &= ~ULPI_PADS_CLKEN_RESET;
2542         writel(val, base + USB_SUSP_CTRL);
2543         udelay(10);
2544
2545         val = readl(base + ULPI_TIMING_CTRL_0);
2546         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
2547         writel(val, base + ULPI_TIMING_CTRL_0);
2548
2549         val = readl(base + USB_SUSP_CTRL);
2550         val |= ULPI_PHY_ENABLE;
2551         writel(val, base + USB_SUSP_CTRL);
2552         udelay(10);
2553
2554         /* set timming parameters */
2555         val = readl(base + ULPI_TIMING_CTRL_0);
2556         val |= ULPI_SHADOW_CLK_LOOPBACK_EN;
2557         val &= ~ULPI_SHADOW_CLK_SEL;
2558         val &= ~ULPI_LBK_PAD_EN;
2559         val |= ULPI_SHADOW_CLK_DELAY(config->shadow_clk_delay);
2560         val |= ULPI_CLOCK_OUT_DELAY(config->clock_out_delay);
2561         val |= ULPI_LBK_PAD_E_INPUT_OR;
2562         writel(val, base + ULPI_TIMING_CTRL_0);
2563
2564         writel(0, base + ULPI_TIMING_CTRL_1);
2565         udelay(10);
2566
2567         /* start internal 60MHz clock */
2568         val = readl(base + ULPIS2S_CTRL);
2569         val |= ULPIS2S_ENA;
2570         val |= ULPIS2S_SUPPORT_DISCONNECT;
2571         val |= ULPIS2S_SPARE((phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) ? 3 : 1);
2572         val |= ULPIS2S_PLLU_MASTER_BLASTER60;
2573         writel(val, base + ULPIS2S_CTRL);
2574
2575         /* select ULPI_CORE_CLK_SEL to SHADOW_CLK */
2576         val = readl(base + ULPI_TIMING_CTRL_0);
2577         val |= ULPI_CORE_CLK_SEL;
2578         writel(val, base + ULPI_TIMING_CTRL_0);
2579         udelay(10);
2580
2581         /* enable ULPI null phy clock - can't set the trimmers before this */
2582         val = readl(base + ULPI_TIMING_CTRL_0);
2583         val |= ULPI_CLK_OUT_ENA;
2584         writel(val, base + ULPI_TIMING_CTRL_0);
2585         udelay(10);
2586
2587         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
2588                                                  USB_PHY_CLK_VALID, 2500)) {
2589                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2590                 return -ETIMEDOUT;
2591         }
2592
2593         /* set ULPI trimmers */
2594         ulpi_set_trimmer(phy);
2595
2596         ulpi_set_host(base);
2597
2598         /* remove slave0 reset */
2599         val = readl(base + USB_SUSP_CTRL);
2600         val &= ~ULPIS2S_SLV0_RESET;
2601         writel(val, base + USB_SUSP_CTRL);
2602
2603         /* remove slave1 and line reset */
2604         val = readl(base + USB_SUSP_CTRL);
2605         val &= ~ULPIS2S_SLV1_RESET;
2606         val &= ~ULPIS2S_LINE_RESET;
2607
2608         /* remove ULPI PADS reset */
2609         val &= ~ULPI_PADS_RESET;
2610         writel(val, base + USB_SUSP_CTRL);
2611
2612         if (cold_boot) {
2613                 val = readl(base + ULPI_TIMING_CTRL_0);
2614                 val |= ULPI_CLK_PADOUT_ENA;
2615                 writel(val, base + ULPI_TIMING_CTRL_0);
2616                 cold_boot = false;
2617         } else {
2618                 if (!readl(base + USB_ASYNCLISTADDR))
2619                         ulpi_null_phy_lp0_resume(phy);
2620         }
2621         udelay(10);
2622
2623         phy->phy_clk_on = true;
2624         phy->hw_accessible = true;
2625
2626         return 0;
2627 }
2628
2629
2630 static int ulpi_null_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
2631 {
2632         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2633
2634         usb_phy_wait_for_sof(phy);
2635         return 0;
2636 }
2637
2638 static int ulpi_null_phy_resume(struct tegra_usb_phy *phy)
2639 {
2640         unsigned long val;
2641         void __iomem *base = phy->regs;
2642
2643         if (!readl(base + USB_ASYNCLISTADDR)) {
2644                 /* enable ULPI CLK output pad */
2645                 val = readl(base + ULPI_TIMING_CTRL_0);
2646                 val |= ULPI_CLK_PADOUT_ENA;
2647                 writel(val, base + ULPI_TIMING_CTRL_0);
2648
2649                 /* enable ULPI pinmux bypass */
2650                 val = readl(base + ULPI_TIMING_CTRL_0);
2651                 val |= ULPI_OUTPUT_PINMUX_BYP;
2652                 writel(val, base + ULPI_TIMING_CTRL_0);
2653                 udelay(5);
2654 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2655                 /* remove DIR tristate */
2656                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR, TEGRA_TRI_NORMAL);
2657 #endif
2658         }
2659         return 0;
2660 }
2661
2662
2663
2664 static struct tegra_usb_phy_ops utmi_phy_ops = {
2665         .open           = utmi_phy_open,
2666         .close          = utmi_phy_close,
2667         .irq            = utmi_phy_irq,
2668         .power_on       = utmi_phy_power_on,
2669         .power_off      = utmi_phy_power_off,
2670         .pre_resume = utmi_phy_pre_resume,
2671         .resume = utmi_phy_resume,
2672         .post_resume    = utmi_phy_post_resume,
2673         .charger_detect = utmi_phy_charger_detect,
2674         .post_suspend   = phy_post_suspend,
2675 };
2676
2677 static struct tegra_usb_phy_ops uhsic_phy_ops = {
2678         .open           = uhsic_phy_open,
2679         .irq            = uhsic_phy_irq,
2680         .power_on       = uhsic_phy_power_on,
2681         .power_off      = uhsic_phy_power_off,
2682         .pre_resume = uhsic_phy_pre_resume,
2683         .resume = uhsic_phy_resume,
2684         .post_resume = uhsic_phy_post_resume,
2685         .port_power = uhsic_phy_bus_port_power,
2686         .bus_reset      = uhsic_phy_bus_reset,
2687         .post_suspend   = phy_post_suspend,
2688 };
2689
2690 static struct tegra_usb_phy_ops ulpi_null_phy_ops = {
2691         .init           = ulpi_null_phy_init,
2692         .irq            = ulpi_null_phy_irq,
2693         .power_on       = ulpi_null_phy_power_on,
2694         .power_off      = ulpi_null_phy_power_off,
2695         .pre_resume = ulpi_null_phy_pre_resume,
2696         .resume = ulpi_null_phy_resume,
2697         .reset          = ulpi_null_phy_cmd_reset,
2698         .post_suspend   = phy_post_suspend,
2699 };
2700
2701 static struct tegra_usb_phy_ops ulpi_link_phy_ops;
2702 static struct tegra_usb_phy_ops icusb_phy_ops;
2703
2704 static struct tegra_usb_phy_ops *phy_ops[] = {
2705         [TEGRA_USB_PHY_INTF_UTMI] = &utmi_phy_ops,
2706         [TEGRA_USB_PHY_INTF_ULPI_LINK] = &ulpi_link_phy_ops,
2707         [TEGRA_USB_PHY_INTF_ULPI_NULL] = &ulpi_null_phy_ops,
2708         [TEGRA_USB_PHY_INTF_HSIC] = &uhsic_phy_ops,
2709         [TEGRA_USB_PHY_INTF_ICUSB] = &icusb_phy_ops,
2710 };
2711
2712 int tegra3_usb_phy_init_ops(struct tegra_usb_phy *phy)
2713 {
2714         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2715
2716         phy->ops = phy_ops[phy->pdata->phy_intf];
2717
2718         /* FIXME: uncommenting below line to make USB host mode fail*/
2719         /* usb_phy_power_down_pmc(); */
2720
2721         return 0;
2722 }