Merge commit 'main-jb-2012.08.03-B4' into t114-0806
[linux-2.6.git] / arch / arm / mach-tegra / tegra3_usb_phy.c
1 /*
2  * arch/arm/mach-tegra/tegra3_usb_phy.c
3  *
4  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
5  *
6  *
7  * This software is licensed under the terms of the GNU General Public
8  * License version 2, as published by the Free Software Foundation, and
9  * may be copied, distributed, and modified under those terms.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17 #include <linux/resource.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/slab.h>
21 #include <linux/err.h>
22 #include <linux/platform_device.h>
23 #include <linux/io.h>
24 #include <linux/gpio.h>
25 #include <linux/interrupt.h>
26 #include <linux/clk.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <mach/clk.h>
30 #include <mach/iomap.h>
31 #include <mach/pinmux.h>
32 #include <mach/pinmux-tegra30.h>
33 #include "tegra_usb_phy.h"
34 #include "gpio-names.h"
35 #include "fuse.h"
36
37 #define USB_USBCMD              0x130
38 #define   USB_USBCMD_RS         (1 << 0)
39 #define   USB_CMD_RESET (1<<1)
40
41 #define USB_USBSTS              0x134
42 #define   USB_USBSTS_PCI        (1 << 2)
43 #define   USB_USBSTS_SRI        (1 << 7)
44 #define   USB_USBSTS_HCH        (1 << 12)
45
46 #define USB_USBINTR             0x138
47
48 #define USB_TXFILLTUNING        0x154
49 #define USB_FIFO_TXFILL_THRES(x)   (((x) & 0x1f) << 16)
50 #define USB_FIFO_TXFILL_MASK    0x1f0000
51
52 #define USB_ASYNCLISTADDR       0x148
53
54 #define ICUSB_CTRL              0x15c
55
56 #define USB_PORTSC              0x174
57 #define   USB_PORTSC_WKOC       (1 << 22)
58 #define   USB_PORTSC_WKDS       (1 << 21)
59 #define   USB_PORTSC_WKCN       (1 << 20)
60 #define   USB_PORTSC_PTC(x)     (((x) & 0xf) << 16)
61 #define   USB_PORTSC_PP (1 << 12)
62 #define   USB_PORTSC_LS(x) (((x) & 0x3) << 10)
63 #define   USB_PORTSC_SUSP       (1 << 7)
64 #define   USB_PORTSC_RESUME     (1 << 6)
65 #define   USB_PORTSC_OCC        (1 << 5)
66 #define   USB_PORTSC_PEC        (1 << 3)
67 #define   USB_PORTSC_PE         (1 << 2)
68 #define   USB_PORTSC_CSC        (1 << 1)
69 #define   USB_PORTSC_CCS        (1 << 0)
70 #define   USB_PORTSC_RWC_BITS (USB_PORTSC_CSC | USB_PORTSC_PEC | USB_PORTSC_OCC)
71
72 #define HOSTPC1_DEVLC           0x1b4
73 #define   HOSTPC1_DEVLC_PHCD            (1 << 22)
74 #define   HOSTPC1_DEVLC_PTS(x)          (((x) & 0x7) << 29)
75 #define   HOSTPC1_DEVLC_PTS_MASK        7
76 #define   HOSTPC1_DEVLC_PTS_HSIC        4
77 #define   HOSTPC1_DEVLC_STS             (1 << 28)
78 #define   HOSTPC1_DEVLC_PSPD(x)         (((x) & 0x3) << 25)
79 #define   HOSTPC1_DEVLC_PSPD_MASK       3
80 #define   HOSTPC1_DEVLC_PSPD_HIGH_SPEED 2
81
82 #define USB_USBMODE             0x1f8
83 #define   USB_USBMODE_MASK              (3 << 0)
84 #define   USB_USBMODE_HOST              (3 << 0)
85 #define   USB_USBMODE_DEVICE            (2 << 0)
86
87 #define USB_SUSP_CTRL           0x400
88 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
89 #define   USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
90 #define   USB_SUSP_CLR                  (1 << 5)
91 #define   USB_PHY_CLK_VALID             (1 << 7)
92 #define   USB_PHY_CLK_VALID_INT_ENB     (1 << 9)
93 #define   USB_PHY_CLK_VALID_INT_STS     (1 << 8)
94 #define   UTMIP_RESET                   (1 << 11)
95 #define   UTMIP_PHY_ENABLE              (1 << 12)
96 #define   ULPI_PHY_ENABLE               (1 << 13)
97 #define   UHSIC_RESET                   (1 << 14)
98 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
99 #define   UHSIC_PHY_ENABLE              (1 << 19)
100 #define   ULPIS2S_SLV0_RESET            (1 << 20)
101 #define   ULPIS2S_SLV1_RESET            (1 << 21)
102 #define   ULPIS2S_LINE_RESET            (1 << 22)
103 #define   ULPI_PADS_RESET               (1 << 23)
104 #define   ULPI_PADS_CLKEN_RESET         (1 << 24)
105
106 #define USB_PHY_VBUS_WAKEUP_ID  0x408
107 #define   VDAT_DET_INT_EN       (1 << 16)
108 #define   VDAT_DET_CHG_DET      (1 << 17)
109 #define   VDAT_DET_STS          (1 << 18)
110 #define   USB_ID_STATUS         (1 << 2)
111
112 #define ULPIS2S_CTRL            0x418
113 #define   ULPIS2S_ENA                   (1 << 0)
114 #define   ULPIS2S_SUPPORT_DISCONNECT    (1 << 2)
115 #define   ULPIS2S_PLLU_MASTER_BLASTER60 (1 << 3)
116 #define   ULPIS2S_SPARE(x)              (((x) & 0xF) << 8)
117 #define   ULPIS2S_FORCE_ULPI_CLK_OUT    (1 << 12)
118 #define   ULPIS2S_DISCON_DONT_CHECK_SE0 (1 << 13)
119 #define   ULPIS2S_SUPPORT_HS_KEEP_ALIVE (1 << 14)
120 #define   ULPIS2S_DISABLE_STP_PU        (1 << 15)
121 #define   ULPIS2S_SLV0_CLAMP_XMIT       (1 << 16)
122
123 #define ULPI_TIMING_CTRL_0      0x424
124 #define   ULPI_CLOCK_OUT_DELAY(x)       ((x) & 0x1F)
125 #define   ULPI_OUTPUT_PINMUX_BYP        (1 << 10)
126 #define   ULPI_CLKOUT_PINMUX_BYP        (1 << 11)
127 #define   ULPI_SHADOW_CLK_LOOPBACK_EN   (1 << 12)
128 #define   ULPI_SHADOW_CLK_SEL           (1 << 13)
129 #define   ULPI_CORE_CLK_SEL             (1 << 14)
130 #define   ULPI_SHADOW_CLK_DELAY(x)      (((x) & 0x1F) << 16)
131 #define   ULPI_LBK_PAD_EN               (1 << 26)
132 #define   ULPI_LBK_PAD_E_INPUT_OR       (1 << 27)
133 #define   ULPI_CLK_OUT_ENA              (1 << 28)
134 #define   ULPI_CLK_PADOUT_ENA           (1 << 29)
135
136 #define ULPI_TIMING_CTRL_1      0x428
137 #define   ULPI_DATA_TRIMMER_LOAD        (1 << 0)
138 #define   ULPI_DATA_TRIMMER_SEL(x)      (((x) & 0x7) << 1)
139 #define   ULPI_STPDIRNXT_TRIMMER_LOAD   (1 << 16)
140 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
141 #define   ULPI_DIR_TRIMMER_LOAD         (1 << 24)
142 #define   ULPI_DIR_TRIMMER_SEL(x)       (((x) & 0x7) << 25)
143
144 #define UTMIP_XCVR_CFG0         0x808
145 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
146 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
147 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
148 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
149 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
150 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
151 #define   UTMIP_XCVR_LSBIAS_SEL                 (1 << 21)
152 #define   UTMIP_XCVR_SETUP_MSB(x)               (((x) & 0x7) << 22)
153 #define   UTMIP_XCVR_HSSLEW_MSB(x)              (((x) & 0x7f) << 25)
154 #define   UTMIP_XCVR_MAX_OFFSET         2
155 #define   UTMIP_XCVR_SETUP_MAX_VALUE    0x7f
156 #define   UTMIP_XCVR_SETUP_MIN_VALUE    0
157 #define   XCVR_SETUP_MSB_CALIB(x) ((x) >> 4)
158
159 #define UTMIP_BIAS_CFG0         0x80c
160 #define   UTMIP_OTGPD                   (1 << 11)
161 #define   UTMIP_BIASPD                  (1 << 10)
162 #define   UTMIP_HSSQUELCH_LEVEL(x)      (((x) & 0x3) << 0)
163 #define   UTMIP_HSDISCON_LEVEL(x)       (((x) & 0x3) << 2)
164 #define   UTMIP_HSDISCON_LEVEL_MSB      (1 << 24)
165
166 #define UTMIP_HSRX_CFG0         0x810
167 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
168 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
169
170 #define UTMIP_HSRX_CFG1         0x814
171 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
172
173 #define UTMIP_TX_CFG0           0x820
174 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
175 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
176
177 #define UTMIP_DEBOUNCE_CFG0 0x82c
178 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
179
180 #define UTMIP_BAT_CHRG_CFG0 0x830
181 #define   UTMIP_PD_CHRG                 (1 << 0)
182 #define   UTMIP_ON_SINK_EN              (1 << 2)
183 #define   UTMIP_OP_SRC_EN               (1 << 3)
184
185 #define UTMIP_XCVR_CFG1         0x838
186 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
187 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
188 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
189 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
190
191 #define UTMIP_BIAS_CFG1         0x83c
192 #define   UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
193 #define   UTMIP_BIAS_PDTRK_POWERDOWN    (1 << 0)
194 #define   UTMIP_BIAS_PDTRK_POWERUP      (1 << 1)
195
196 #define UTMIP_MISC_CFG0         0x824
197 #define   UTMIP_DPDM_OBSERVE            (1 << 26)
198 #define   UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
199 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J   UTMIP_DPDM_OBSERVE_SEL(0xf)
200 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K   UTMIP_DPDM_OBSERVE_SEL(0xe)
201 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
202 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
203 #define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
204 #define   FORCE_PULLDN_DM       (1 << 8)
205 #define   FORCE_PULLDN_DP       (1 << 9)
206 #define   COMB_TERMS            (1 << 0)
207 #define   ALWAYS_FREE_RUNNING_TERMS (1 << 1)
208
209 #define UTMIP_SPARE_CFG0        0x834
210 #define   FUSE_SETUP_SEL                (1 << 3)
211 #define   FUSE_ATERM_SEL                (1 << 4)
212
213 #define UTMIP_PMC_WAKEUP0               0x84c
214 #define   EVENT_INT_ENB                 (1 << 0)
215
216 #define UHSIC_PMC_WAKEUP0               0xc34
217
218 #define UTMIP_BIAS_STS0                 0x840
219 #define   UTMIP_RCTRL_VAL(x)            (((x) & 0xffff) << 0)
220 #define   UTMIP_TCTRL_VAL(x)            (((x) & (0xffff << 16)) >> 16)
221
222 #define UHSIC_PLL_CFG1                          0xc04
223 #define   UHSIC_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
224 #define   UHSIC_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 14)
225
226 #define UHSIC_HSRX_CFG0                         0xc08
227 #define   UHSIC_ELASTIC_UNDERRUN_LIMIT(x)       (((x) & 0x1f) << 2)
228 #define   UHSIC_ELASTIC_OVERRUN_LIMIT(x)        (((x) & 0x1f) << 8)
229 #define   UHSIC_IDLE_WAIT(x)                    (((x) & 0x1f) << 13)
230
231 #define UHSIC_HSRX_CFG1                         0xc0c
232 #define   UHSIC_HS_SYNC_START_DLY(x)            (((x) & 0x1f) << 1)
233
234 #define UHSIC_TX_CFG0                           0xc10
235 #define UHSIC_HS_READY_WAIT_FOR_VALID   (1 << 9)
236 #define UHSIC_MISC_CFG0                         0xc14
237 #define   UHSIC_SUSPEND_EXIT_ON_EDGE            (1 << 7)
238 #define   UHSIC_DETECT_SHORT_CONNECT            (1 << 8)
239 #define   UHSIC_FORCE_XCVR_MODE                 (1 << 15)
240 #define   UHSIC_DISABLE_BUSRESET                (1 << 20)
241 #define UHSIC_MISC_CFG1                         0xc18
242 #define   UHSIC_PLLU_STABLE_COUNT(x)            (((x) & 0xfff) << 2)
243
244 #define UHSIC_PADS_CFG0                         0xc1c
245 #define   UHSIC_TX_RTUNEN                       0xf000
246 #define   UHSIC_TX_RTUNE(x)                     (((x) & 0xf) << 12)
247
248 #define UHSIC_PADS_CFG1                         0xc20
249 #define   UHSIC_PD_BG                           (1 << 2)
250 #define   UHSIC_PD_TX                           (1 << 3)
251 #define   UHSIC_PD_TRK                          (1 << 4)
252 #define   UHSIC_PD_RX                           (1 << 5)
253 #define   UHSIC_PD_ZI                           (1 << 6)
254 #define   UHSIC_RX_SEL                          (1 << 7)
255 #define   UHSIC_RPD_DATA                        (1 << 9)
256 #define   UHSIC_RPD_STROBE                      (1 << 10)
257 #define   UHSIC_RPU_DATA                        (1 << 11)
258 #define   UHSIC_RPU_STROBE                      (1 << 12)
259
260 #define UHSIC_CMD_CFG0                  0xc24
261 #define UHSIC_PRETEND_CONNECT_DETECT    (1 << 5)
262
263 #define UHSIC_STAT_CFG0         0xc28
264 #define UHSIC_CONNECT_DETECT            (1 << 0)
265
266 #define PMC_USB_DEBOUNCE                        0xec
267 #define UTMIP_LINE_DEB_CNT(x)           (((x) & 0xf) << 16)
268 #define UHSIC_LINE_DEB_CNT(x)           (((x) & 0xf) << 20)
269
270 #define PMC_USB_AO                              0xf0
271
272 #define PMC_POWER_DOWN_MASK                     0xffff
273 #define HSIC_RESERVED_P0                        (3 << 14)
274 #define STROBE_VAL_PD_P0                        (1 << 12)
275 #define DATA_VAL_PD_P0                          (1 << 13)
276
277 #define USB_ID_PD(inst)                 (1 << ((4*(inst))+3))
278 #define VBUS_WAKEUP_PD(inst)                    (1 << ((4*(inst))+2))
279 #define   USBON_VAL_PD(inst)                    (1 << ((4*(inst))+1))
280 #define   USBON_VAL_PD_P2                       (1 << 9)
281 #define   USBON_VAL_PD_P1                       (1 << 5)
282 #define   USBON_VAL_PD_P0                       (1 << 1)
283 #define   USBOP_VAL_PD(inst)                    (1 << (4*(inst)))
284 #define   USBOP_VAL_PD_P2                       (1 << 8)
285 #define   USBOP_VAL_PD_P1                       (1 << 4)
286 #define   USBOP_VAL_PD_P0                       (1 << 0)
287 #define   PMC_USB_AO_PD_P2                      (0xf << 8)
288 #define   PMC_USB_AO_ID_PD_P0                   (1 << 3)
289 #define   PMC_USB_AO_VBUS_WAKEUP_PD_P0  (1 << 2)
290
291 #define PMC_TRIGGERS                    0x1ec
292
293 #define   UHSIC_CLR_WALK_PTR_P0         (1 << 3)
294 #define   UTMIP_CLR_WALK_PTR(inst)      (1 << (inst))
295 #define   UTMIP_CLR_WALK_PTR_P2         (1 << 2)
296 #define   UTMIP_CLR_WALK_PTR_P1         (1 << 1)
297 #define   UTMIP_CLR_WALK_PTR_P0         (1 << 0)
298 #define   UTMIP_CAP_CFG(inst)   (1 << ((inst)+4))
299 #define   UTMIP_CAP_CFG_P2              (1 << 6)
300 #define   UTMIP_CAP_CFG_P1              (1 << 5)
301 #define   UTMIP_CAP_CFG_P0              (1 << 4)
302 #define   UTMIP_CLR_WAKE_ALARM(inst)    (1 << ((inst)+12))
303 #define   UHSIC_CLR_WAKE_ALARM_P0       (1 << 15)
304 #define   UTMIP_CLR_WAKE_ALARM_P2       (1 << 14)
305
306 #define PMC_PAD_CFG             (0x1f4)
307
308 #define PMC_UTMIP_TERM_PAD_CFG  0x1f8
309 #define   PMC_TCTRL_VAL(x)      (((x) & 0x1f) << 5)
310 #define   PMC_RCTRL_VAL(x)      (((x) & 0x1f) << 0)
311
312 #define PMC_SLEEP_CFG                   0x1fc
313
314 #define   UHSIC_MASTER_ENABLE                   (1 << 24)
315 #define   UHSIC_WAKE_VAL(x)             (((x) & 0xf) << 28)
316 #define   WAKE_VAL_SD10                 0x2
317 #define   UTMIP_TCTRL_USE_PMC(inst) (1 << ((8*(inst))+3))
318 #define   UTMIP_TCTRL_USE_PMC_P2                (1 << 19)
319 #define   UTMIP_TCTRL_USE_PMC_P1                (1 << 11)
320 #define   UTMIP_TCTRL_USE_PMC_P0                (1 << 3)
321 #define   UTMIP_RCTRL_USE_PMC(inst) (1 << ((8*(inst))+2))
322 #define   UTMIP_RCTRL_USE_PMC_P2                (1 << 18)
323 #define   UTMIP_RCTRL_USE_PMC_P1                (1 << 10)
324 #define   UTMIP_RCTRL_USE_PMC_P0                (1 << 2)
325 #define   UTMIP_FSLS_USE_PMC(inst)      (1 << ((8*(inst))+1))
326 #define   UTMIP_FSLS_USE_PMC_P2         (1 << 17)
327 #define   UTMIP_FSLS_USE_PMC_P1         (1 << 9)
328 #define   UTMIP_FSLS_USE_PMC_P0         (1 << 1)
329 #define   UTMIP_MASTER_ENABLE(inst) (1 << (8*(inst)))
330 #define   UTMIP_MASTER_ENABLE_P2                (1 << 16)
331 #define   UTMIP_MASTER_ENABLE_P1                (1 << 8)
332 #define   UTMIP_MASTER_ENABLE_P0                (1 << 0)
333 #define UHSIC_MASTER_ENABLE_P0          (1 << 24)
334 #define UHSIC_WAKE_VAL_P0(x)            (((x) & 0xf) << 28)
335
336 #define PMC_SLEEPWALK_CFG               0x200
337
338 #define   UHSIC_WAKE_WALK_EN_P0 (1 << 30)
339 #define   UHSIC_LINEVAL_WALK_EN (1 << 31)
340 #define   UTMIP_LINEVAL_WALK_EN(inst) (1 << ((8*(inst))+7))
341 #define   UTMIP_LINEVAL_WALK_EN_P2      (1 << 23)
342 #define   UTMIP_LINEVAL_WALK_EN_P1      (1 << 15)
343 #define   UTMIP_LINEVAL_WALK_EN_P0      (1 << 7)
344 #define   UTMIP_WAKE_VAL(inst, x) (((x) & 0xf) << ((8*(inst))+4))
345 #define   UTMIP_WAKE_VAL_P2(x)          (((x) & 0xf) << 20)
346 #define   UTMIP_WAKE_VAL_P1(x)          (((x) & 0xf) << 12)
347 #define   UTMIP_WAKE_VAL_P0(x)          (((x) & 0xf) << 4)
348 #define   WAKE_VAL_NONE         0xc
349 #define   WAKE_VAL_ANY                  0xF
350 #define   WAKE_VAL_FSJ                  0x2
351 #define   WAKE_VAL_FSK                  0x1
352 #define   WAKE_VAL_SE0                  0x0
353
354 #define PMC_SLEEPWALK_REG(inst)         (0x204 + (4*(inst)))
355 #define   UTMIP_USBOP_RPD_A     (1 << 0)
356 #define   UTMIP_USBON_RPD_A     (1 << 1)
357 #define   UTMIP_AP_A                    (1 << 4)
358 #define   UTMIP_AN_A                    (1 << 5)
359 #define   UTMIP_HIGHZ_A         (1 << 6)
360 #define   UTMIP_USBOP_RPD_B     (1 << 8)
361 #define   UTMIP_USBON_RPD_B     (1 << 9)
362 #define   UTMIP_AP_B                    (1 << 12)
363 #define   UTMIP_AN_B                    (1 << 13)
364 #define   UTMIP_HIGHZ_B         (1 << 14)
365 #define   UTMIP_USBOP_RPD_C     (1 << 16)
366 #define   UTMIP_USBON_RPD_C     (1 << 17)
367 #define   UTMIP_AP_C            (1 << 20)
368 #define   UTMIP_AN_C            (1 << 21)
369 #define   UTMIP_HIGHZ_C         (1 << 22)
370 #define   UTMIP_USBOP_RPD_D     (1 << 24)
371 #define   UTMIP_USBON_RPD_D     (1 << 25)
372 #define   UTMIP_AP_D            (1 << 28)
373 #define   UTMIP_AN_D            (1 << 29)
374 #define   UTMIP_HIGHZ_D         (1 << 30)
375
376 #define PMC_SLEEPWALK_UHSIC             0x210
377
378 #define UHSIC_STROBE_RPD_A              (1 << 0)
379 #define UHSIC_DATA_RPD_A                (1 << 1)
380 #define UHSIC_STROBE_RPU_A              (1 << 2)
381 #define UHSIC_DATA_RPU_A                (1 << 3)
382 #define UHSIC_STROBE_RPD_B              (1 << 8)
383 #define UHSIC_DATA_RPD_B                (1 << 9)
384 #define UHSIC_STROBE_RPU_B              (1 << 10)
385 #define UHSIC_DATA_RPU_B                (1 << 11)
386 #define UHSIC_STROBE_RPD_C              (1 << 16)
387 #define UHSIC_DATA_RPD_C                (1 << 17)
388 #define UHSIC_STROBE_RPU_C              (1 << 18)
389 #define UHSIC_DATA_RPU_C                (1 << 19)
390 #define UHSIC_STROBE_RPD_D              (1 << 24)
391 #define UHSIC_DATA_RPD_D                (1 << 25)
392 #define UHSIC_STROBE_RPU_D              (1 << 26)
393 #define UHSIC_DATA_RPU_D                (1 << 27)
394
395 #define UTMIP_UHSIC_STATUS              0x214
396
397 #define UTMIP_USBOP_VAL(inst)           (1 << ((2*(inst)) + 8))
398 #define UTMIP_USBOP_VAL_P2              (1 << 12)
399 #define UTMIP_USBOP_VAL_P1              (1 << 10)
400 #define UTMIP_USBOP_VAL_P0              (1 << 8)
401 #define UTMIP_USBON_VAL(inst)           (1 << ((2*(inst)) + 9))
402 #define UTMIP_USBON_VAL_P2              (1 << 13)
403 #define UTMIP_USBON_VAL_P1              (1 << 11)
404 #define UTMIP_USBON_VAL_P0              (1 << 9)
405 #define UHSIC_WAKE_ALARM                (1 << 19)
406 #define UTMIP_WAKE_ALARM(inst)          (1 << ((inst) + 16))
407 #define UTMIP_WAKE_ALARM_P2             (1 << 18)
408 #define UTMIP_WAKE_ALARM_P1             (1 << 17)
409 #define UTMIP_WAKE_ALARM_P0             (1 << 16)
410 #define UHSIC_DATA_VAL_P0               (1 << 15)
411 #define UHSIC_STROBE_VAL_P0             (1 << 14)
412 #define UTMIP_WALK_PTR_VAL(inst)        (0x3 << ((inst)*2))
413 #define UHSIC_WALK_PTR_VAL              (0x3 << 6)
414 #define UTMIP_WALK_PTR(inst)            (1 << ((inst)*2))
415 #define UTMIP_WALK_PTR_P2               (1 << 4)
416 #define UTMIP_WALK_PTR_P1               (1 << 2)
417 #define UTMIP_WALK_PTR_P0               (1 << 0)
418
419 #define USB1_PREFETCH_ID                           6
420 #define USB2_PREFETCH_ID                           18
421 #define USB3_PREFETCH_ID                           17
422
423 #define PMC_UTMIP_UHSIC_FAKE            0x218
424
425 #define UHSIC_STROBE_VAL                (1 << 12)
426 #define UHSIC_DATA_VAL                  (1 << 13)
427 #define UHSIC_STROBE_ENB                (1 << 14)
428 #define UHSIC_DATA_ENB                  (1 << 15)
429 #define   USBON_VAL(inst)       (1 << ((4*(inst))+1))
430 #define   USBON_VAL_P2                  (1 << 9)
431 #define   USBON_VAL_P1                  (1 << 5)
432 #define   USBON_VAL_P0                  (1 << 1)
433 #define   USBOP_VAL(inst)       (1 << (4*(inst)))
434 #define   USBOP_VAL_P2                  (1 << 8)
435 #define   USBOP_VAL_P1                  (1 << 4)
436 #define   USBOP_VAL_P0                  (1 << 0)
437
438 #define PMC_UTMIP_BIAS_MASTER_CNTRL 0x30c
439 #define   BIAS_MASTER_PROG_VAL          (1 << 1)
440
441 #define PMC_UTMIP_MASTER_CONFIG 0x310
442
443 #define UTMIP_PWR(inst)         (1 << (inst))
444 #define UHSIC_PWR                       (1 << 3)
445
446 #define FUSE_USB_CALIB_0                0x1F0
447 #define   XCVR_SETUP(x) (((x) & 0x7F) << 0)
448 #define   XCVR_SETUP_LSB_MASK   0xF
449 #define   XCVR_SETUP_MSB_MASK   0x70
450 #define   XCVR_SETUP_LSB_MAX_VAL        0xF
451
452 #define APB_MISC_GP_OBSCTRL_0   0x818
453 #define APB_MISC_GP_OBSDATA_0   0x81c
454
455 /* ULPI GPIO */
456 #define ULPI_STP        TEGRA_GPIO_PY3
457 #define ULPI_DIR        TEGRA_GPIO_PY1
458 #define ULPI_D0         TEGRA_GPIO_PO1
459 #define ULPI_D1         TEGRA_GPIO_PO2
460
461 /* These values (in milli second) are taken from the battery charging spec */
462 #define TDP_SRC_ON_MS    100
463 #define TDPSRC_CON_MS    40
464
465 #ifdef DEBUG
466 #define DBG(stuff...)   pr_info("tegra3_usb_phy: " stuff)
467 #else
468 #define DBG(stuff...)   do {} while (0)
469 #endif
470
471 #if 0
472 #define PHY_DBG(stuff...)       pr_info("tegra3_usb_phy: " stuff)
473 #else
474 #define PHY_DBG(stuff...)       do {} while (0)
475 #endif
476
477 /* define HSIC phy params */
478 #define HSIC_SYNC_START_DELAY           9
479 #define HSIC_IDLE_WAIT_DELAY            17
480 #define HSIC_ELASTIC_UNDERRUN_LIMIT     16
481 #define HSIC_ELASTIC_OVERRUN_LIMIT      16
482
483 static u32 utmip_rctrl_val, utmip_tctrl_val;
484 static DEFINE_SPINLOCK(utmip_pad_lock);
485 static int utmip_pad_count;
486
487 static struct tegra_xtal_freq utmip_freq_table[] = {
488         {
489                 .freq = 12000000,
490                 .enable_delay = 0x02,
491                 .stable_count = 0x2F,
492                 .active_delay = 0x04,
493                 .xtal_freq_count = 0x76,
494                 .debounce = 0x7530,
495                 .pdtrk_count = 5,
496         },
497         {
498                 .freq = 13000000,
499                 .enable_delay = 0x02,
500                 .stable_count = 0x33,
501                 .active_delay = 0x05,
502                 .xtal_freq_count = 0x7F,
503                 .debounce = 0x7EF4,
504                 .pdtrk_count = 5,
505         },
506         {
507                 .freq = 19200000,
508                 .enable_delay = 0x03,
509                 .stable_count = 0x4B,
510                 .active_delay = 0x06,
511                 .xtal_freq_count = 0xBB,
512                 .debounce = 0xBB80,
513                 .pdtrk_count = 7,
514         },
515         {
516                 .freq = 26000000,
517                 .enable_delay = 0x04,
518                 .stable_count = 0x66,
519                 .active_delay = 0x09,
520                 .xtal_freq_count = 0xFE,
521                 .debounce = 0xFDE8,
522                 .pdtrk_count = 9,
523         },
524 };
525
526 static struct tegra_xtal_freq uhsic_freq_table[] = {
527         {
528                 .freq = 12000000,
529                 .enable_delay = 0x02,
530                 .stable_count = 0x2F,
531                 .active_delay = 0x0,
532                 .xtal_freq_count = 0x1CA,
533         },
534         {
535                 .freq = 13000000,
536                 .enable_delay = 0x02,
537                 .stable_count = 0x33,
538                 .active_delay = 0x0,
539                 .xtal_freq_count = 0x1F0,
540         },
541         {
542                 .freq = 19200000,
543                 .enable_delay = 0x03,
544                 .stable_count = 0x4B,
545                 .active_delay = 0x0,
546                 .xtal_freq_count = 0x2DD,
547         },
548         {
549                 .freq = 26000000,
550                 .enable_delay = 0x04,
551                 .stable_count = 0x66,
552                 .active_delay = 0x0,
553                 .xtal_freq_count = 0x3E0,
554         },
555 };
556
557 static void usb_phy_fence_read(struct tegra_usb_phy *phy)
558 {
559         /* Fence read for coherency of AHB master intiated writes */
560         if (phy->inst == 0)
561                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB1_PREFETCH_ID));
562         else if (phy->inst == 1)
563                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB2_PREFETCH_ID));
564         else if (phy->inst == 2)
565                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB3_PREFETCH_ID));
566
567         return;
568 }
569
570 static void utmip_setup_pmc_wake_detect(struct tegra_usb_phy *phy)
571 {
572         unsigned long val, pmc_pad_cfg_val;
573         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
574         unsigned  int inst = phy->inst;
575         void __iomem *base = phy->regs;
576         bool port_connected;
577         enum usb_phy_port_speed port_speed;
578
579         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
580
581         /* check for port connect status */
582         val = readl(base + USB_PORTSC);
583         port_connected = val & USB_PORTSC_CCS;
584
585         if (!port_connected)
586                 return;
587
588         port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
589                 HOSTPC1_DEVLC_PSPD_MASK;
590         /*Set PMC MASTER bits to do the following
591         * a. Take over the UTMI drivers
592         * b. set up such that it will take over resume
593         *        if remote wakeup is detected
594         * Prepare PMC to take over suspend-wake detect-drive resume until USB
595         * controller ready
596         */
597
598         /* disable master enable in PMC */
599         val = readl(pmc_base + PMC_SLEEP_CFG);
600         val &= ~UTMIP_MASTER_ENABLE(inst);
601         writel(val, pmc_base + PMC_SLEEP_CFG);
602
603         /* UTMIP_PWR_PX=1 for power savings mode */
604         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
605         val |= UTMIP_PWR(inst);
606         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
607
608         /* config debouncer */
609         val = readl(pmc_base + PMC_USB_DEBOUNCE);
610         val &= ~UTMIP_LINE_DEB_CNT(~0);
611         val |= UTMIP_LINE_DEB_CNT(4);
612         writel(val, pmc_base + PMC_USB_DEBOUNCE);
613
614         /* Make sure nothing is happening on the line with respect to PMC */
615         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
616         val &= ~USBOP_VAL(inst);
617         val &= ~USBON_VAL(inst);
618         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
619
620         /* Make sure wake value for line is none */
621         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
622         val &= ~UTMIP_LINEVAL_WALK_EN(inst);
623         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
624         val = readl(pmc_base + PMC_SLEEP_CFG);
625         val &= ~UTMIP_WAKE_VAL(inst, ~0);
626         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
627         writel(val, pmc_base + PMC_SLEEP_CFG);
628
629         /* turn off pad detectors */
630         val = readl(pmc_base + PMC_USB_AO);
631         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
632         writel(val, pmc_base + PMC_USB_AO);
633
634         /* Remove fake values and make synchronizers work a bit */
635         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
636         val &= ~USBOP_VAL(inst);
637         val &= ~USBON_VAL(inst);
638         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
639
640         /* Enable which type of event can trigger a walk,
641         in this case usb_line_wake */
642         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
643         val |= UTMIP_LINEVAL_WALK_EN(inst);
644         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
645
646         /* Enable which type of event can trigger a walk,
647         * in this case usb_line_wake */
648         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
649         val |= UTMIP_LINEVAL_WALK_EN(inst);
650         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
651
652         /* Capture FS/LS pad configurations */
653         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
654         val = readl(pmc_base + PMC_TRIGGERS);
655         val |= UTMIP_CAP_CFG(inst);
656         writel(val, pmc_base + PMC_TRIGGERS);
657         udelay(1);
658         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
659
660         /* BIAS MASTER_ENABLE=0 */
661         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
662         val &= ~BIAS_MASTER_PROG_VAL;
663         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
664
665         /* program walk sequence, maintain a J, followed by a driven K
666         * to signal a resume once an wake event is detected */
667         val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
668         val &= ~UTMIP_AP_A;
669         val |= UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_AN_A |UTMIP_HIGHZ_A |
670                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_AP_B | UTMIP_AN_B |
671                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_AP_C | UTMIP_AN_C |
672                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_AP_D | UTMIP_AN_D;
673         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
674
675         if (port_speed == USB_PHY_PORT_SPEED_LOW) {
676                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
677                 val &= ~(UTMIP_AN_B | UTMIP_HIGHZ_B | UTMIP_AN_C |
678                         UTMIP_HIGHZ_C | UTMIP_AN_D | UTMIP_HIGHZ_D);
679                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
680         } else {
681                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
682                 val &= ~(UTMIP_AP_B | UTMIP_HIGHZ_B | UTMIP_AP_C |
683                         UTMIP_HIGHZ_C | UTMIP_AP_D | UTMIP_HIGHZ_D);
684                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
685         }
686
687         /* turn on pad detectors */
688         val = readl(pmc_base + PMC_USB_AO);
689         val &= ~(USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
690         writel(val, pmc_base + PMC_USB_AO);
691
692         /* Add small delay before usb detectors provide stable line values */
693         mdelay(1);
694
695         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
696         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
697         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
698         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
699
700         phy->remote_wakeup = false;
701
702         /* Turn over pad configuration to PMC  for line wake events*/
703         val = readl(pmc_base + PMC_SLEEP_CFG);
704         val &= ~UTMIP_WAKE_VAL(inst, ~0);
705         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_ANY);
706         val |= UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst);
707         val |= UTMIP_MASTER_ENABLE(inst) | UTMIP_FSLS_USE_PMC(inst);
708         writel(val, pmc_base + PMC_SLEEP_CFG);
709
710         val = readl(base + UTMIP_PMC_WAKEUP0);
711         val |= EVENT_INT_ENB;
712         writel(val, base + UTMIP_PMC_WAKEUP0);
713         PHY_DBG("%s ENABLE_PMC inst = %d\n", __func__, inst);
714 }
715
716 static void utmip_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy)
717 {
718         unsigned long val;
719         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
720         unsigned  int inst = phy->inst;
721         void __iomem *base = phy->regs;
722
723         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
724
725         val = readl(pmc_base + PMC_SLEEP_CFG);
726         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
727         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
728         writel(val, pmc_base + PMC_SLEEP_CFG);
729
730         val = readl(base + UTMIP_PMC_WAKEUP0);
731         val &= ~EVENT_INT_ENB;
732         writel(val, base + UTMIP_PMC_WAKEUP0);
733
734         /* Disable PMC master mode by clearing MASTER_EN */
735         val = readl(pmc_base + PMC_SLEEP_CFG);
736         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
737                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
738         writel(val, pmc_base + PMC_SLEEP_CFG);
739
740         val = readl(pmc_base + PMC_TRIGGERS);
741         val &= ~UTMIP_CAP_CFG(inst);
742         writel(val, pmc_base + PMC_TRIGGERS);
743
744         /* turn off pad detectors */
745         val = readl(pmc_base + PMC_USB_AO);
746         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
747         writel(val, pmc_base + PMC_USB_AO);
748
749         val = readl(pmc_base + PMC_TRIGGERS);
750         val |= UTMIP_CLR_WALK_PTR(inst);
751         val |= UTMIP_CLR_WAKE_ALARM(inst);
752         writel(val, pmc_base + PMC_TRIGGERS);
753
754         phy->remote_wakeup = false;
755         PHY_DBG("%s DISABLE_PMC inst = %d\n", __func__, inst);
756 }
757
758 static bool utmi_phy_remotewake_detected(struct tegra_usb_phy *phy)
759 {
760         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
761         void __iomem *base = phy->regs;
762         unsigned  int inst = phy->inst;
763         u32 val;
764
765         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
766         val = readl(base + UTMIP_PMC_WAKEUP0);
767         if (val & EVENT_INT_ENB) {
768                 val = readl(pmc_base + UTMIP_UHSIC_STATUS);
769                 if (UTMIP_WAKE_ALARM(inst) & val) {
770                         val = readl(pmc_base + PMC_SLEEP_CFG);
771                         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
772                         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
773                         writel(val, pmc_base + PMC_SLEEP_CFG);
774
775                         val = readl(pmc_base + PMC_TRIGGERS);
776                         val |= UTMIP_CLR_WAKE_ALARM(inst);
777                         writel(val, pmc_base + PMC_TRIGGERS);
778
779                         val = readl(base + UTMIP_PMC_WAKEUP0);
780                         val &= ~EVENT_INT_ENB;
781                         writel(val, base + UTMIP_PMC_WAKEUP0);
782                         phy->remote_wakeup = true;
783                         return true;
784                 }
785         }
786         return false;
787 }
788
789 static void utmi_phy_enable_trking_data(struct tegra_usb_phy *phy)
790 {
791         void __iomem *base = IO_ADDRESS(TEGRA_USB_BASE);
792         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
793         static bool init_done = false;
794         u32 val;
795
796         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
797
798         /* Should be done only once after system boot */
799         if (init_done)
800                 return;
801
802         clk_enable(phy->utmi_pad_clk);
803         /* Bias pad MASTER_ENABLE=1 */
804         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
805         val |= BIAS_MASTER_PROG_VAL;
806         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
807
808         /* Setting the tracking length time */
809         val = readl(base + UTMIP_BIAS_CFG1);
810         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
811         val |= UTMIP_BIAS_PDTRK_COUNT(5);
812         writel(val, base + UTMIP_BIAS_CFG1);
813
814         /* Bias PDTRK is Shared and MUST be done from USB1 ONLY, PD_TRK=0 */
815         val = readl(base + UTMIP_BIAS_CFG1);
816         val &= ~UTMIP_BIAS_PDTRK_POWERDOWN;
817         writel(val, base + UTMIP_BIAS_CFG1);
818
819         val = readl(base + UTMIP_BIAS_CFG1);
820         val |= UTMIP_BIAS_PDTRK_POWERUP;
821         writel(val, base + UTMIP_BIAS_CFG1);
822
823         /* Wait for 25usec */
824         udelay(25);
825
826         /* Bias pad MASTER_ENABLE=0 */
827         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
828         val &= ~BIAS_MASTER_PROG_VAL;
829         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
830
831         /* Wait for 1usec */
832         udelay(1);
833
834         /* Bias pad MASTER_ENABLE=1 */
835         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
836         val |= BIAS_MASTER_PROG_VAL;
837         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
838
839         /* Read RCTRL and TCTRL from UTMIP space */
840         val = readl(base + UTMIP_BIAS_STS0);
841         utmip_rctrl_val = ffz(UTMIP_RCTRL_VAL(val));
842         utmip_tctrl_val = ffz(UTMIP_TCTRL_VAL(val));
843
844         /* PD_TRK=1 */
845         val = readl(base + UTMIP_BIAS_CFG1);
846         val |= UTMIP_BIAS_PDTRK_POWERDOWN;
847         writel(val, base + UTMIP_BIAS_CFG1);
848
849         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
850         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
851         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
852         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
853         clk_disable(phy->utmi_pad_clk);
854         init_done = true;
855 }
856
857 static void utmip_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy)
858 {
859         unsigned long val;
860         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
861         unsigned  int inst = phy->inst;
862
863         /* power down UTMIP interfaces */
864         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
865         val |= UTMIP_PWR(inst);
866         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
867
868         /* setup sleep walk usb controller */
869         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
870                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
871                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
872                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
873         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
874
875         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
876         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
877         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
878         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
879
880         /* Turn over pad configuration to PMC */
881         val = readl(pmc_base + PMC_SLEEP_CFG);
882         val &= ~UTMIP_WAKE_VAL(inst, ~0);
883         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE) |
884                 UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
885                 UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst);
886         writel(val, pmc_base + PMC_SLEEP_CFG);
887         PHY_DBG("%s ENABLE_PMC inst = %d\n", __func__, inst);
888 }
889
890 static void utmip_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
891 {
892         unsigned long val;
893         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
894         unsigned  int inst = phy->inst;
895
896         /* Disable PMC master mode by clearing MASTER_EN */
897         val = readl(pmc_base + PMC_SLEEP_CFG);
898         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
899                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
900         writel(val, pmc_base + PMC_SLEEP_CFG);
901         mdelay(1);
902         PHY_DBG("%s DISABLE_PMC inst = %d\n", __func__, inst);
903 }
904
905
906 #ifdef KERNEL_WARNING
907 static void usb_phy_power_down_pmc(void)
908 {
909         unsigned long val;
910         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
911
912         /* power down all 3 UTMIP interfaces */
913         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
914         val |= UTMIP_PWR(0) | UTMIP_PWR(1) | UTMIP_PWR(2);
915         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
916
917         /* turn on pad detectors */
918         writel(PMC_POWER_DOWN_MASK, pmc_base + PMC_USB_AO);
919
920         /* setup sleep walk fl all 3 usb controllers */
921         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
922                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
923                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
924                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
925         writel(val, pmc_base + PMC_SLEEPWALK_REG(0));
926         writel(val, pmc_base + PMC_SLEEPWALK_REG(1));
927         writel(val, pmc_base + PMC_SLEEPWALK_REG(2));
928
929         /* enable pull downs on HSIC PMC */
930         val = UHSIC_STROBE_RPD_A | UHSIC_DATA_RPD_A | UHSIC_STROBE_RPD_B |
931                 UHSIC_DATA_RPD_B | UHSIC_STROBE_RPD_C | UHSIC_DATA_RPD_C |
932                 UHSIC_STROBE_RPD_D | UHSIC_DATA_RPD_D;
933         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
934
935         /* Turn over pad configuration to PMC */
936         val = readl(pmc_base + PMC_SLEEP_CFG);
937         val &= ~UTMIP_WAKE_VAL(0, ~0);
938         val &= ~UTMIP_WAKE_VAL(1, ~0);
939         val &= ~UTMIP_WAKE_VAL(2, ~0);
940         val &= ~UHSIC_WAKE_VAL_P0(~0);
941         val |= UTMIP_WAKE_VAL(0, WAKE_VAL_NONE) | UHSIC_WAKE_VAL_P0(WAKE_VAL_NONE) |
942         UTMIP_WAKE_VAL(1, WAKE_VAL_NONE) | UTMIP_WAKE_VAL(2, WAKE_VAL_NONE) |
943         UTMIP_RCTRL_USE_PMC(0) | UTMIP_RCTRL_USE_PMC(1) | UTMIP_RCTRL_USE_PMC(2) |
944         UTMIP_TCTRL_USE_PMC(0) | UTMIP_TCTRL_USE_PMC(1) | UTMIP_TCTRL_USE_PMC(2) |
945         UTMIP_FSLS_USE_PMC(0) | UTMIP_FSLS_USE_PMC(1) | UTMIP_FSLS_USE_PMC(2) |
946         UTMIP_MASTER_ENABLE(0) | UTMIP_MASTER_ENABLE(1) | UTMIP_MASTER_ENABLE(2) |
947         UHSIC_MASTER_ENABLE_P0;
948         writel(val, pmc_base + PMC_SLEEP_CFG);
949 }
950 #endif
951
952 static int usb_phy_bringup_host_controller(struct tegra_usb_phy *phy)
953 {
954         unsigned long val;
955         void __iomem *base = phy->regs;
956
957         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
958         PHY_DBG("[%d] USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n", __LINE__,
959                 readl(base + USB_USBSTS), readl(base + USB_PORTSC),
960                                                         phy->port_speed);
961
962         /* Device is plugged in when system is in LP0 */
963         /* Bring up the controller from LP0*/
964         val = readl(base + USB_USBCMD);
965         val |= USB_CMD_RESET;
966         writel(val, base + USB_USBCMD);
967
968         if (usb_phy_reg_status_wait(base + USB_USBCMD,
969                 USB_CMD_RESET, 0, 2500) < 0) {
970                 pr_err("%s: timeout waiting for reset\n", __func__);
971         }
972
973         val = readl(base + USB_USBMODE);
974         val &= ~USB_USBMODE_MASK;
975         val |= USB_USBMODE_HOST;
976         writel(val, base + USB_USBMODE);
977         val = readl(base + HOSTPC1_DEVLC);
978         val &= ~HOSTPC1_DEVLC_PTS(~0);
979
980         if (phy->pdata->phy_intf == TEGRA_USB_PHY_INTF_HSIC)
981                 val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
982         else
983                 val |= HOSTPC1_DEVLC_STS;
984         writel(val, base + HOSTPC1_DEVLC);
985
986         /* Enable Port Power */
987         val = readl(base + USB_PORTSC);
988         val |= USB_PORTSC_PP;
989         writel(val, base + USB_PORTSC);
990         udelay(10);
991
992         /* Check if the phy resume from LP0. When the phy resume from LP0
993          * USB register will be reset.to zero */
994         if (!readl(base + USB_ASYNCLISTADDR)) {
995                 /* Program the field PTC based on the saved speed mode */
996                 val = readl(base + USB_PORTSC);
997                 val &= ~USB_PORTSC_PTC(~0);
998                 if ((phy->port_speed == USB_PHY_PORT_SPEED_HIGH) ||
999                         (phy->pdata->phy_intf == TEGRA_USB_PHY_INTF_HSIC))
1000                         val |= USB_PORTSC_PTC(5);
1001                 else if (phy->port_speed == USB_PHY_PORT_SPEED_FULL)
1002                         val |= USB_PORTSC_PTC(6);
1003                 else if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
1004                         val |= USB_PORTSC_PTC(7);
1005                 writel(val, base + USB_PORTSC);
1006                 udelay(10);
1007
1008                 /* Disable test mode by setting PTC field to NORMAL_OP */
1009                 val = readl(base + USB_PORTSC);
1010                 val &= ~USB_PORTSC_PTC(~0);
1011                 writel(val, base + USB_PORTSC);
1012                 udelay(10);
1013         }
1014
1015         /* Poll until CCS is enabled */
1016         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
1017                                                  USB_PORTSC_CCS, 2000)) {
1018                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
1019         }
1020
1021         /* Poll until PE is enabled */
1022         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_PE,
1023                                                  USB_PORTSC_PE, 2000)) {
1024                 pr_err("%s: timeout waiting for USB_PORTSC_PE\n", __func__);
1025         }
1026
1027         /* Clear the PCI status, to avoid an interrupt taken upon resume */
1028         val = readl(base + USB_USBSTS);
1029         val |= USB_USBSTS_PCI;
1030         writel(val, base + USB_USBSTS);
1031
1032         if (!phy->remote_wakeup) {
1033                 /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
1034                 val = readl(base + USB_PORTSC);
1035                 if ((val & USB_PORTSC_PP) && (val & USB_PORTSC_PE)) {
1036                         val |= USB_PORTSC_SUSP;
1037                         writel(val, base + USB_PORTSC);
1038                         /* Need a 4ms delay before the controller goes to suspend */
1039                         mdelay(4);
1040
1041                         /* Wait until port suspend completes */
1042                         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_SUSP,
1043                                                          USB_PORTSC_SUSP, 1000)) {
1044                                 pr_err("%s: timeout waiting for PORT_SUSPEND\n",
1045                                                                         __func__);
1046                         }
1047                 }
1048         }
1049         PHY_DBG("[%d] USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n", __LINE__,
1050                 readl(base + USB_USBSTS), readl(base + USB_PORTSC),
1051                                                         phy->port_speed);
1052
1053         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1054                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1055         return 0;
1056 }
1057
1058 static void usb_phy_wait_for_sof(struct tegra_usb_phy *phy)
1059 {
1060         unsigned long val;
1061         void __iomem *base = phy->regs;
1062
1063         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1064
1065         val = readl(base + USB_USBSTS);
1066         writel(val, base + USB_USBSTS);
1067         udelay(20);
1068         /* wait for two SOFs */
1069         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1070                 USB_USBSTS_SRI, 2500))
1071                 pr_err("%s: timeout waiting for SOF\n", __func__);
1072
1073         val = readl(base + USB_USBSTS);
1074         writel(val, base + USB_USBSTS);
1075         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI, 0, 2500))
1076                 pr_err("%s: timeout waiting for SOF\n", __func__);
1077
1078         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1079                         USB_USBSTS_SRI, 2500))
1080                 pr_err("%s: timeout waiting for SOF\n", __func__);
1081
1082         udelay(20);
1083 }
1084
1085 static unsigned int utmi_phy_xcvr_setup_value(struct tegra_usb_phy *phy)
1086 {
1087         struct tegra_utmi_config *cfg = &phy->pdata->u_cfg.utmi;
1088         signed long val;
1089
1090         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1091
1092         if (cfg->xcvr_use_fuses) {
1093                 val = XCVR_SETUP(tegra_fuse_readl(FUSE_USB_CALIB_0));
1094                 if (cfg->xcvr_use_lsb) {
1095                         val = min((unsigned int) ((val & XCVR_SETUP_LSB_MASK)
1096                                 + cfg->xcvr_setup_offset),
1097                                 (unsigned int) XCVR_SETUP_LSB_MAX_VAL);
1098                         val |= (cfg->xcvr_setup & XCVR_SETUP_MSB_MASK);
1099                 } else {
1100                         if (cfg->xcvr_setup_offset <= UTMIP_XCVR_MAX_OFFSET)
1101                                 val = val + cfg->xcvr_setup_offset;
1102
1103                         if (val > UTMIP_XCVR_SETUP_MAX_VALUE) {
1104                                 val = UTMIP_XCVR_SETUP_MAX_VALUE;
1105                                 pr_info("%s: reset XCVR_SETUP to max value\n",
1106                                                 __func__);
1107                         } else if (val < UTMIP_XCVR_SETUP_MIN_VALUE) {
1108                                 val = UTMIP_XCVR_SETUP_MIN_VALUE;
1109                                 pr_info("%s: reset XCVR_SETUP to min value\n",
1110                                                 __func__);
1111                         }
1112                 }
1113         } else {
1114                 val = cfg->xcvr_setup;
1115         }
1116
1117         return (unsigned int) val;
1118 }
1119
1120 static int utmi_phy_open(struct tegra_usb_phy *phy)
1121 {
1122         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1123         unsigned long parent_rate, val;
1124         int i;
1125
1126         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1127
1128         phy->utmi_pad_clk = clk_get_sys("utmip-pad", NULL);
1129         if (IS_ERR(phy->utmi_pad_clk)) {
1130                 pr_err("%s: can't get utmip pad clock\n", __func__);
1131                 return PTR_ERR(phy->utmi_pad_clk);
1132         }
1133
1134         phy->utmi_xcvr_setup = utmi_phy_xcvr_setup_value(phy);
1135
1136         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
1137         for (i = 0; i < ARRAY_SIZE(utmip_freq_table); i++) {
1138                 if (utmip_freq_table[i].freq == parent_rate) {
1139                         phy->freq = &utmip_freq_table[i];
1140                         break;
1141                 }
1142         }
1143         if (!phy->freq) {
1144                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
1145                 return -EINVAL;
1146         }
1147
1148         /* Power-up the VBUS detector for UTMIP PHY */
1149         val = readl(pmc_base + PMC_USB_AO);
1150         val &= ~(PMC_USB_AO_VBUS_WAKEUP_PD_P0 | PMC_USB_AO_ID_PD_P0);
1151         writel((val | PMC_USB_AO_PD_P2), (pmc_base + PMC_USB_AO));
1152
1153         utmip_powerup_pmc_wake_detect(phy);
1154
1155         return 0;
1156 }
1157
1158 static void utmi_phy_close(struct tegra_usb_phy *phy)
1159 {
1160         unsigned long val;
1161         void __iomem *base = phy->regs;
1162
1163         DBG("%s inst:[%d]\n", __func__, phy->inst);
1164
1165         /* Disable PHY clock valid interrupts while going into suspend*/
1166         if (phy->pdata->u_data.host.hot_plug) {
1167                 val = readl(base + USB_SUSP_CTRL);
1168                 val &= ~USB_PHY_CLK_VALID_INT_ENB;
1169                 writel(val, base + USB_SUSP_CTRL);
1170         }
1171
1172         clk_put(phy->utmi_pad_clk);
1173 }
1174
1175 static int utmi_phy_pad_power_on(struct tegra_usb_phy *phy)
1176 {
1177         unsigned long val, flags;
1178         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1179
1180         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1181
1182         clk_enable(phy->utmi_pad_clk);
1183
1184         spin_lock_irqsave(&utmip_pad_lock, flags);
1185         utmip_pad_count++;
1186
1187         val = readl(pad_base + UTMIP_BIAS_CFG0);
1188         val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
1189         val |= UTMIP_HSSQUELCH_LEVEL(0x2) | UTMIP_HSDISCON_LEVEL(0x1) |
1190                 UTMIP_HSDISCON_LEVEL_MSB;
1191         writel(val, pad_base + UTMIP_BIAS_CFG0);
1192
1193         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1194
1195         clk_disable(phy->utmi_pad_clk);
1196
1197         return 0;
1198 }
1199
1200 static int utmi_phy_pad_power_off(struct tegra_usb_phy *phy)
1201 {
1202         unsigned long val, flags;
1203         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1204
1205         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1206
1207         clk_enable(phy->utmi_pad_clk);
1208         spin_lock_irqsave(&utmip_pad_lock, flags);
1209
1210         if (!utmip_pad_count) {
1211                 pr_err("%s: utmip pad already powered off\n", __func__);
1212                 goto out;
1213         }
1214         if (--utmip_pad_count == 0) {
1215                 val = readl(pad_base + UTMIP_BIAS_CFG0);
1216                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
1217                 val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) | UTMIP_HSDISCON_LEVEL(~0) |
1218                         UTMIP_HSDISCON_LEVEL_MSB);
1219                 writel(val, pad_base + UTMIP_BIAS_CFG0);
1220         }
1221 out:
1222         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1223         clk_disable(phy->utmi_pad_clk);
1224
1225         return 0;
1226 }
1227
1228 static int utmi_phy_irq(struct tegra_usb_phy *phy)
1229 {
1230         void __iomem *base = phy->regs;
1231         unsigned long val = 0;
1232
1233         if (phy->phy_clk_on) {
1234                 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1235                 DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1236                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1237                 DBG("USB_USBMODE[0x%x] USB_USBCMD[0x%x]\n",
1238                         readl(base + USB_USBMODE), readl(base + USB_USBCMD));
1239         }
1240
1241         usb_phy_fence_read(phy);
1242         /* check if there is any remote wake event */
1243         if (utmi_phy_remotewake_detected(phy))
1244                 pr_info("%s: utmip remote wake detected\n", __func__);
1245
1246         if (phy->pdata->u_data.host.hot_plug) {
1247                 val = readl(base + USB_SUSP_CTRL);
1248                 if ((val  & USB_PHY_CLK_VALID_INT_STS)) {
1249                         val &= ~USB_PHY_CLK_VALID_INT_ENB |
1250                                         USB_PHY_CLK_VALID_INT_STS;
1251                         writel(val , (base + USB_SUSP_CTRL));
1252                         pr_info("%s: usb device plugged-in\n", __func__);
1253                         val = readl(base + USB_USBSTS);
1254                         if (!(val  & USB_USBSTS_PCI))
1255                                 return IRQ_NONE;
1256                         val = readl(base + USB_PORTSC);
1257                         val &= ~(USB_PORTSC_WKCN | USB_PORTSC_RWC_BITS);
1258                         writel(val , (base + USB_PORTSC));
1259                 } else if (!phy->phy_clk_on) {
1260                         return IRQ_NONE;
1261                 }
1262         }
1263
1264         return IRQ_HANDLED;
1265 }
1266
1267 static void utmi_phy_enable_obs_bus(struct tegra_usb_phy *phy)
1268 {
1269         unsigned long val;
1270         void __iomem *base = phy->regs;
1271
1272         /* (2LS WAR)is not required for LS and FS devices and is only for HS */
1273         if ((phy->port_speed == USB_PHY_PORT_SPEED_LOW) ||
1274                 (phy->port_speed == USB_PHY_PORT_SPEED_FULL)) {
1275                 /* do not enable the OBS bus */
1276                 val = readl(base + UTMIP_MISC_CFG0);
1277                 val &= ~(UTMIP_DPDM_OBSERVE_SEL(~0));
1278                 writel(val, base + UTMIP_MISC_CFG0);
1279                 DBG("%s(%d) Disable OBS bus\n", __func__, __LINE__);
1280                 return;
1281         }
1282         /* Force DP/DM pulldown active for Host mode */
1283         val = readl(base + UTMIP_MISC_CFG0);
1284         val |= FORCE_PULLDN_DM | FORCE_PULLDN_DP |
1285                         COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS;
1286         writel(val, base + UTMIP_MISC_CFG0);
1287         val = readl(base + UTMIP_MISC_CFG0);
1288         val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1289         if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
1290                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
1291         else
1292                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
1293         writel(val, base + UTMIP_MISC_CFG0);
1294         udelay(1);
1295
1296         val = readl(base + UTMIP_MISC_CFG0);
1297         val |= UTMIP_DPDM_OBSERVE;
1298         writel(val, base + UTMIP_MISC_CFG0);
1299         udelay(10);
1300         DBG("%s(%d) Enable OBS bus\n", __func__, __LINE__);
1301         PHY_DBG("ENABLE_OBS_BUS\n");
1302 }
1303
1304 static int utmi_phy_disable_obs_bus(struct tegra_usb_phy *phy)
1305 {
1306         unsigned long val;
1307         void __iomem *base = phy->regs;
1308         unsigned long flags;
1309
1310         /* check if OBS bus is already enabled */
1311         val = readl(base + UTMIP_MISC_CFG0);
1312         if (val & UTMIP_DPDM_OBSERVE) {
1313                 PHY_DBG("DISABLE_OBS_BUS\n");
1314
1315                 /* disable ALL interrupts on current CPU */
1316                 local_irq_save(flags);
1317
1318                 /* Change the UTMIP OBS bus to drive SE0 */
1319                 val = readl(base + UTMIP_MISC_CFG0);
1320                 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1321                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_SE0;
1322                 writel(val, base + UTMIP_MISC_CFG0);
1323
1324                 /* Wait for 3us(2 LS bit times) */
1325                 udelay(3);
1326
1327                 /* Release UTMIP OBS bus */
1328                 val = readl(base + UTMIP_MISC_CFG0);
1329                 val &= ~UTMIP_DPDM_OBSERVE;
1330                 writel(val, base + UTMIP_MISC_CFG0);
1331
1332                 /* Release DP/DM pulldown for Host mode */
1333                 val = readl(base + UTMIP_MISC_CFG0);
1334                 val &= ~(FORCE_PULLDN_DM | FORCE_PULLDN_DP |
1335                                 COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS);
1336                 writel(val, base + UTMIP_MISC_CFG0);
1337
1338                 val = readl(base + USB_USBCMD);
1339                 val |= USB_USBCMD_RS;
1340                 writel(val, base + USB_USBCMD);
1341
1342                 /* restore ALL interrupts on current CPU */
1343                 local_irq_restore(flags);
1344
1345                 if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
1346                                                          USB_USBCMD_RS, 2000)) {
1347                         pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
1348                         return -ETIMEDOUT;
1349                 }
1350         }
1351         return 0;
1352 }
1353
1354 static int utmi_phy_post_resume(struct tegra_usb_phy *phy)
1355 {
1356         unsigned long val;
1357         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1358         unsigned  int inst = phy->inst;
1359
1360         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1361         val = readl(pmc_base + PMC_SLEEP_CFG);
1362         /* if PMC is not disabled by now then disable it */
1363         if (val & UTMIP_MASTER_ENABLE(inst)) {
1364                 utmip_phy_disable_pmc_bus_ctrl(phy);
1365         }
1366
1367         utmi_phy_disable_obs_bus(phy);
1368
1369         return 0;
1370 }
1371
1372 static int phy_post_suspend(struct tegra_usb_phy *phy)
1373 {
1374
1375         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1376         /* Need a 4ms delay for controller to suspend */
1377         mdelay(4);
1378
1379         return 0;
1380
1381 }
1382
1383 static int utmi_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1384 {
1385         unsigned long val;
1386         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1387         void __iomem *base = phy->regs;
1388         unsigned  int inst = phy->inst;
1389
1390         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1391         phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
1392                         HOSTPC1_DEVLC_PSPD_MASK;
1393
1394         if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH) {
1395                 /* Disable interrupts */
1396                 writel(0, base + USB_USBINTR);
1397                 /* Clear the run bit to stop SOFs - 2LS WAR */
1398                 val = readl(base + USB_USBCMD);
1399                 val &= ~USB_USBCMD_RS;
1400                 writel(val, base + USB_USBCMD);
1401                 if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
1402                                                          USB_USBSTS_HCH, 2000)) {
1403                         pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
1404                 }
1405         }
1406
1407         val = readl(pmc_base + PMC_SLEEP_CFG);
1408         if (val & UTMIP_MASTER_ENABLE(inst)) {
1409                 if (!remote_wakeup)
1410                         utmip_phy_disable_pmc_bus_ctrl(phy);
1411         } else {
1412                 utmi_phy_enable_obs_bus(phy);
1413         }
1414
1415         return 0;
1416 }
1417
1418 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
1419 {
1420         unsigned long val;
1421         void __iomem *base = phy->regs;
1422
1423         PHY_DBG("%s(%d) inst:[%d] BEGIN\n", __func__, __LINE__, phy->inst);
1424         if (!phy->phy_clk_on) {
1425                 PHY_DBG("%s(%d) inst:[%d] phy clk is already off\n",
1426                                         __func__, __LINE__, phy->inst);
1427                 return 0;
1428         }
1429
1430         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1431                 utmip_powerdown_pmc_wake_detect(phy);
1432
1433                 val = readl(base + USB_SUSP_CTRL);
1434                 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
1435                 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
1436                 writel(val, base + USB_SUSP_CTRL);
1437
1438                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1439                 val |= UTMIP_PD_CHRG;
1440                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1441         } else {
1442                 phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
1443                                 HOSTPC1_DEVLC_PSPD_MASK;
1444
1445                 /* Disable interrupts */
1446                 writel(0, base + USB_USBINTR);
1447
1448                 /* Clear the run bit to stop SOFs - 2LS WAR */
1449                 val = readl(base + USB_USBCMD);
1450                 val &= ~USB_USBCMD_RS;
1451                 writel(val, base + USB_USBCMD);
1452
1453                 if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
1454                                                          USB_USBSTS_HCH, 2000)) {
1455                         pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
1456                 }
1457                 utmip_setup_pmc_wake_detect(phy);
1458         }
1459
1460         if (!phy->pdata->u_data.host.hot_plug) {
1461                 val = readl(base + UTMIP_XCVR_CFG0);
1462                 val |= (UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
1463                          UTMIP_FORCE_PDZI_POWERDOWN);
1464                 writel(val, base + UTMIP_XCVR_CFG0);
1465         }
1466
1467         val = readl(base + UTMIP_XCVR_CFG1);
1468         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1469                    UTMIP_FORCE_PDDR_POWERDOWN;
1470         writel(val, base + UTMIP_XCVR_CFG1);
1471
1472         val = readl(base + UTMIP_BIAS_CFG1);
1473         val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
1474         writel(val, base + UTMIP_BIAS_CFG1);
1475
1476         utmi_phy_pad_power_off(phy);
1477
1478         if (phy->pdata->u_data.host.hot_plug) {
1479                 bool enable_hotplug = true;
1480                 /* if it is OTG port then make sure to enable hot-plug feature
1481                    only if host adaptor is connected, i.e id is low */
1482                 if (phy->pdata->port_otg) {
1483                         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1484                         enable_hotplug = (val & USB_ID_STATUS) ? false : true;
1485                 }
1486                 if (enable_hotplug) {
1487                         val = readl(base + USB_PORTSC);
1488                         val |= USB_PORTSC_WKCN;
1489                         writel(val, base + USB_PORTSC);
1490
1491                         val = readl(base + USB_SUSP_CTRL);
1492                         val |= USB_PHY_CLK_VALID_INT_ENB;
1493                         writel(val, base + USB_SUSP_CTRL);
1494                 } else {
1495                         /* Disable PHY clock valid interrupts while going into suspend*/
1496                         val = readl(base + USB_SUSP_CTRL);
1497                         val &= ~USB_PHY_CLK_VALID_INT_ENB;
1498                         writel(val, base + USB_SUSP_CTRL);
1499                 }
1500         }
1501
1502         val = readl(base + HOSTPC1_DEVLC);
1503         val |= HOSTPC1_DEVLC_PHCD;
1504         writel(val, base + HOSTPC1_DEVLC);
1505
1506         if (!phy->pdata->u_data.host.hot_plug) {
1507                 val = readl(base + USB_SUSP_CTRL);
1508                 val |= UTMIP_RESET;
1509                 writel(val, base + USB_SUSP_CTRL);
1510         }
1511
1512         phy->phy_clk_on = false;
1513         phy->hw_accessible = false;
1514
1515         PHY_DBG("%s(%d) inst:[%d] END\n", __func__, __LINE__, phy->inst);
1516
1517         return 0;
1518 }
1519
1520
1521 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
1522 {
1523         unsigned long val;
1524         void __iomem *base = phy->regs;
1525         struct tegra_utmi_config *config = &phy->pdata->u_cfg.utmi;
1526
1527         PHY_DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1528         if (phy->phy_clk_on) {
1529                 PHY_DBG("%s(%d) inst:[%d] phy clk is already On\n",
1530                                         __func__, __LINE__, phy->inst);
1531                 return 0;
1532         }
1533         val = readl(base + USB_SUSP_CTRL);
1534         val |= UTMIP_RESET;
1535         writel(val, base + USB_SUSP_CTRL);
1536
1537         val = readl(base + UTMIP_TX_CFG0);
1538         val |= UTMIP_FS_PREABMLE_J;
1539         writel(val, base + UTMIP_TX_CFG0);
1540
1541         val = readl(base + UTMIP_HSRX_CFG0);
1542         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
1543         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
1544         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
1545         writel(val, base + UTMIP_HSRX_CFG0);
1546
1547         val = readl(base + UTMIP_HSRX_CFG1);
1548         val &= ~UTMIP_HS_SYNC_START_DLY(~0);
1549         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
1550         writel(val, base + UTMIP_HSRX_CFG1);
1551
1552         val = readl(base + UTMIP_DEBOUNCE_CFG0);
1553         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
1554         val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
1555         writel(val, base + UTMIP_DEBOUNCE_CFG0);
1556
1557         val = readl(base + UTMIP_MISC_CFG0);
1558         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
1559         writel(val, base + UTMIP_MISC_CFG0);
1560
1561         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1562                 val = readl(base + USB_SUSP_CTRL);
1563                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
1564                 writel(val, base + USB_SUSP_CTRL);
1565
1566                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1567                 val &= ~UTMIP_PD_CHRG;
1568                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1569         } else {
1570                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1571                 val |= UTMIP_PD_CHRG;
1572                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1573         }
1574
1575         utmi_phy_pad_power_on(phy);
1576
1577         val = readl(base + UTMIP_XCVR_CFG0);
1578         val &= ~(UTMIP_XCVR_LSBIAS_SEL | UTMIP_FORCE_PD_POWERDOWN |
1579                  UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN |
1580                  UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_LSFSLEW(~0) |
1581                  UTMIP_XCVR_LSRSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
1582         val |= UTMIP_XCVR_SETUP(phy->utmi_xcvr_setup);
1583         val |= UTMIP_XCVR_SETUP_MSB(XCVR_SETUP_MSB_CALIB(phy->utmi_xcvr_setup));
1584         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
1585         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
1586         if (!config->xcvr_use_lsb)
1587                 val |= UTMIP_XCVR_HSSLEW_MSB(0x8);
1588         writel(val, base + UTMIP_XCVR_CFG0);
1589
1590         val = readl(base + UTMIP_XCVR_CFG1);
1591         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1592                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
1593         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
1594         writel(val, base + UTMIP_XCVR_CFG1);
1595
1596         val = readl(base + UTMIP_BIAS_CFG1);
1597         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
1598         val |= UTMIP_BIAS_PDTRK_COUNT(phy->freq->pdtrk_count);
1599         writel(val, base + UTMIP_BIAS_CFG1);
1600
1601         val = readl(base + UTMIP_SPARE_CFG0);
1602         val &= ~FUSE_SETUP_SEL;
1603         val |= FUSE_ATERM_SEL;
1604         writel(val, base + UTMIP_SPARE_CFG0);
1605
1606         val = readl(base + USB_SUSP_CTRL);
1607         val |= UTMIP_PHY_ENABLE;
1608         writel(val, base + USB_SUSP_CTRL);
1609
1610         val = readl(base + USB_SUSP_CTRL);
1611         val &= ~UTMIP_RESET;
1612         writel(val, base + USB_SUSP_CTRL);
1613
1614         val = readl(base + HOSTPC1_DEVLC);
1615         val &= ~HOSTPC1_DEVLC_PHCD;
1616         writel(val, base + HOSTPC1_DEVLC);
1617
1618         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1619                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500))
1620                 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
1621
1622         utmi_phy_enable_trking_data(phy);
1623
1624         if (phy->inst == 2)
1625                 writel(0, base + ICUSB_CTRL);
1626
1627         val = readl(base + USB_USBMODE);
1628         val &= ~USB_USBMODE_MASK;
1629         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST)
1630                 val |= USB_USBMODE_HOST;
1631         else
1632                 val |= USB_USBMODE_DEVICE;
1633         writel(val, base + USB_USBMODE);
1634
1635         val = readl(base + HOSTPC1_DEVLC);
1636         val &= ~HOSTPC1_DEVLC_PTS(~0);
1637         val |= HOSTPC1_DEVLC_STS;
1638         writel(val, base + HOSTPC1_DEVLC);
1639
1640         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE)
1641                 utmip_powerup_pmc_wake_detect(phy);
1642         phy->phy_clk_on = true;
1643         phy->hw_accessible = true;
1644         PHY_DBG("%s(%d) End inst:[%d]\n", __func__, __LINE__, phy->inst);
1645         return 0;
1646 }
1647
1648 static void utmi_phy_restore_start(struct tegra_usb_phy *phy)
1649 {
1650         unsigned long val;
1651         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1652         int inst = phy->inst;
1653
1654         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1655         val = readl(pmc_base + UTMIP_UHSIC_STATUS);
1656         /* Check whether we wake up from the remote resume.
1657            For lp1 case, pmc is not responsible for waking the
1658            system, it's the flow controller and hence
1659            UTMIP_WALK_PTR_VAL(inst) will return 0.
1660            Also, for lp1 case phy->remote_wakeup will already be set
1661            to true by utmi_phy_irq() when the remote wakeup happens.
1662            Hence change the logic in the else part to enter only
1663            if phy->remote_wakeup is not set to true by the
1664            utmi_phy_irq(). */
1665         if (UTMIP_WALK_PTR_VAL(inst) & val) {
1666                 phy->remote_wakeup = true;
1667         } else if(!phy->remote_wakeup) {
1668                 if (!((UTMIP_USBON_VAL(phy->inst) |
1669                         UTMIP_USBOP_VAL(phy->inst)) & val)) {
1670                                 utmip_phy_disable_pmc_bus_ctrl(phy);
1671                 }
1672         }
1673         utmi_phy_enable_obs_bus(phy);
1674 }
1675
1676 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
1677 {
1678         unsigned long val;
1679         void __iomem *base = phy->regs;
1680         int wait_time_us = 25000; /* FPR should be set by this time */
1681
1682         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1683         /* check whether we wake up from the remote resume */
1684         if (phy->remote_wakeup) {
1685                 /* wait until SUSPEND and RESUME bit is cleared on remote resume */
1686                 do {
1687                         val = readl(base + USB_PORTSC);
1688                         udelay(1);
1689                         if (wait_time_us == 0) {
1690                                 PHY_DBG("%s PMC REMOTE WAKEUP FPR timeout val = 0x%x instance = %d\n", __func__, val, phy->inst);
1691                                 utmip_phy_disable_pmc_bus_ctrl(phy);
1692                                 utmi_phy_post_resume(phy);
1693                                 return;
1694                         }
1695                         wait_time_us--;
1696                 } while (val & (USB_PORTSC_RESUME | USB_PORTSC_SUSP));
1697
1698                 /* wait for 25 ms to port resume complete */
1699                 msleep(25);
1700                 /* disable PMC master control */
1701                 utmip_phy_disable_pmc_bus_ctrl(phy);
1702
1703                 /* Clear PCI and SRI bits to avoid an interrupt upon resume */
1704                 val = readl(base + USB_USBSTS);
1705                 writel(val, base + USB_USBSTS);
1706                 /* wait to avoid SOF if there is any */
1707                 if (usb_phy_reg_status_wait(base + USB_USBSTS,
1708                         USB_USBSTS_SRI, USB_USBSTS_SRI, 2500) < 0) {
1709                         pr_err("%s: timeout waiting for SOF\n", __func__);
1710                 }
1711                 utmi_phy_post_resume(phy);
1712         }
1713 }
1714
1715 static int utmi_phy_resume(struct tegra_usb_phy *phy)
1716 {
1717         int status = 0;
1718         unsigned long val;
1719         void __iomem *base = phy->regs;
1720
1721         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1722         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) {
1723                 if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
1724                         utmi_phy_restore_start(phy);
1725                         usb_phy_bringup_host_controller(phy);
1726                         utmi_phy_restore_end(phy);
1727                 } else {
1728                         /* device is plugged in when system is in LP0 */
1729                         /* bring up the controller from LP0*/
1730                         val = readl(base + USB_USBCMD);
1731                         val |= USB_CMD_RESET;
1732                         writel(val, base + USB_USBCMD);
1733
1734                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1735                                 USB_CMD_RESET, 0, 2500) < 0) {
1736                                 pr_err("%s: timeout waiting for reset\n", __func__);
1737                         }
1738
1739                         val = readl(base + USB_USBMODE);
1740                         val &= ~USB_USBMODE_MASK;
1741                         val |= USB_USBMODE_HOST;
1742                         writel(val, base + USB_USBMODE);
1743
1744                         val = readl(base + HOSTPC1_DEVLC);
1745                         val &= ~HOSTPC1_DEVLC_PTS(~0);
1746                         val |= HOSTPC1_DEVLC_STS;
1747                         writel(val, base + HOSTPC1_DEVLC);
1748
1749                         writel(USB_USBCMD_RS, base + USB_USBCMD);
1750
1751                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1752                                 USB_USBCMD_RS, USB_USBCMD_RS, 2500) < 0) {
1753                                 pr_err("%s: timeout waiting for run bit\n", __func__);
1754                         }
1755
1756                         /* Enable Port Power */
1757                         val = readl(base + USB_PORTSC);
1758                         val |= USB_PORTSC_PP;
1759                         writel(val, base + USB_PORTSC);
1760                         udelay(10);
1761
1762                         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1763                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1764                 }
1765         }
1766
1767         return status;
1768 }
1769
1770 static bool utmi_phy_charger_detect(struct tegra_usb_phy *phy)
1771 {
1772         unsigned long val;
1773         void __iomem *base = phy->regs;
1774         bool status;
1775
1776         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1777         if (phy->pdata->op_mode != TEGRA_USB_OPMODE_DEVICE) {
1778                 /* Charger detection is not there for ULPI
1779                  * return Charger not available */
1780                 return false;
1781         }
1782
1783         /* Enable charger detection logic */
1784         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1785         val |= UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN;
1786         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1787
1788         /* Source should be on for 100 ms as per USB charging spec */
1789         msleep(TDP_SRC_ON_MS);
1790
1791         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1792         /* If charger is not connected disable the interrupt */
1793         val &= ~VDAT_DET_INT_EN;
1794         val |= VDAT_DET_CHG_DET;
1795         writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
1796
1797         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1798         if (val & VDAT_DET_STS)
1799                 status = true;
1800         else
1801                 status = false;
1802
1803         /* Disable charger detection logic */
1804         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1805         val &= ~(UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN);
1806         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1807
1808         /* Delay of 40 ms before we pull the D+ as per battery charger spec */
1809         msleep(TDPSRC_CON_MS);
1810
1811         return status;
1812 }
1813
1814 static void uhsic_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
1815 {
1816         unsigned long val;
1817         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1818
1819         /* turn on pad detectors for HSIC*/
1820         val = readl(pmc_base + PMC_USB_AO);
1821         val &= ~(HSIC_RESERVED_P0 | STROBE_VAL_PD_P0 | DATA_VAL_PD_P0);
1822         writel(val, pmc_base + PMC_USB_AO);
1823
1824         /* Disable PMC master mode by clearing MASTER_EN */
1825         val = readl(pmc_base + PMC_SLEEP_CFG);
1826         val &= ~(UHSIC_MASTER_ENABLE_P0);
1827         writel(val, pmc_base + PMC_SLEEP_CFG);
1828         mdelay(1);
1829 }
1830
1831 static void uhsic_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy)
1832 {
1833         unsigned long val;
1834         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1835
1836         DBG("%s:%d\n", __func__, __LINE__);
1837
1838         /* turn off pad detectors for HSIC*/
1839         val = readl(pmc_base + PMC_USB_AO);
1840         val |= (HSIC_RESERVED_P0 | STROBE_VAL_PD_P0 | DATA_VAL_PD_P0);
1841         writel(val, pmc_base + PMC_USB_AO);
1842
1843         /* enable pull downs on HSIC PMC */
1844         val = UHSIC_STROBE_RPD_A | UHSIC_DATA_RPD_A | UHSIC_STROBE_RPD_B |
1845                 UHSIC_DATA_RPD_B | UHSIC_STROBE_RPD_C | UHSIC_DATA_RPD_C |
1846                 UHSIC_STROBE_RPD_D | UHSIC_DATA_RPD_D;
1847         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1848
1849         /* Turn over pad configuration to PMC */
1850         val = readl(pmc_base + PMC_SLEEP_CFG);
1851         val &= ~UHSIC_WAKE_VAL_P0(~0);
1852         val |= UHSIC_WAKE_VAL_P0(WAKE_VAL_NONE) | UHSIC_MASTER_ENABLE_P0;
1853         writel(val, pmc_base + PMC_SLEEP_CFG);
1854 }
1855
1856 static void uhsic_setup_pmc_wake_detect(struct tegra_usb_phy *phy)
1857 {
1858         unsigned long val;
1859         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1860         void __iomem *base = phy->regs;
1861         bool port_connected;
1862
1863         DBG("%s:%d\n", __func__, __LINE__);
1864
1865         /* check for port connect status */
1866         val = readl(base + USB_PORTSC);
1867         port_connected = val & USB_PORTSC_CCS;
1868
1869         if (!port_connected)
1870                 return;
1871
1872         /*Set PMC MASTER bits to do the following
1873         * a. Take over the hsic drivers
1874         * b. set up such that it will take over resume
1875         *        if remote wakeup is detected
1876         * Prepare PMC to take over suspend-wake detect-drive resume until USB
1877         * controller ready
1878         */
1879
1880         /* disable master enable in PMC */
1881         val = readl(pmc_base + PMC_SLEEP_CFG);
1882         val &= ~UHSIC_MASTER_ENABLE_P0;
1883         writel(val, pmc_base + PMC_SLEEP_CFG);
1884
1885         /* UTMIP_PWR_PX=1 for power savings mode */
1886         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
1887         val |= UHSIC_PWR;
1888         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
1889
1890         /* Make sure nothing is happening on the line with respect to PMC */
1891         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
1892         val &= ~UHSIC_STROBE_VAL;
1893         val &= ~UHSIC_DATA_VAL;
1894         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
1895
1896         /* Clear walk enable */
1897         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
1898         val &= ~UHSIC_LINEVAL_WALK_EN;
1899         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
1900
1901         /* Make sure wake value for line is none */
1902         val = readl(pmc_base + PMC_SLEEP_CFG);
1903         val &= ~UHSIC_WAKE_VAL(WAKE_VAL_ANY);
1904         val |= UHSIC_WAKE_VAL(WAKE_VAL_NONE);
1905         writel(val, pmc_base + PMC_SLEEP_CFG);
1906
1907         /* turn on pad detectors */
1908         val = readl(pmc_base + PMC_USB_AO);
1909         val &= ~(STROBE_VAL_PD_P0 | DATA_VAL_PD_P0);
1910         writel(val, pmc_base + PMC_USB_AO);
1911
1912         /* Add small delay before usb detectors provide stable line values */
1913         udelay(1);
1914
1915         /* Enable which type of event can trigger a walk,
1916         * in this case usb_line_wake */
1917         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
1918         val |= UHSIC_LINEVAL_WALK_EN;
1919         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
1920
1921         /* program walk sequence, maintain a J, followed by a driven K
1922         * to signal a resume once an wake event is detected */
1923
1924         val = readl(pmc_base + PMC_SLEEPWALK_UHSIC);
1925
1926         val &= ~UHSIC_DATA_RPU_A;
1927         val |=  UHSIC_DATA_RPD_A;
1928         val &= ~UHSIC_STROBE_RPD_A;
1929         val |=  UHSIC_STROBE_RPU_A;
1930
1931         val &= ~UHSIC_DATA_RPD_B;
1932         val |=  UHSIC_DATA_RPU_B;
1933         val &= ~UHSIC_STROBE_RPU_B;
1934         val |=  UHSIC_STROBE_RPD_B;
1935
1936         val &= ~UHSIC_DATA_RPD_C;
1937         val |=  UHSIC_DATA_RPU_C;
1938         val &= ~UHSIC_STROBE_RPU_C;
1939         val |=  UHSIC_STROBE_RPD_C;
1940
1941         val &= ~UHSIC_DATA_RPD_D;
1942         val |=  UHSIC_DATA_RPU_D;
1943         val &= ~UHSIC_STROBE_RPU_D;
1944         val |=  UHSIC_STROBE_RPD_D;
1945         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1946
1947         phy->remote_wakeup = false;
1948
1949         /* Setting Wake event*/
1950         val = readl(pmc_base + PMC_SLEEP_CFG);
1951         val &= ~UHSIC_WAKE_VAL(WAKE_VAL_ANY);
1952         val |= UHSIC_WAKE_VAL(WAKE_VAL_SD10);
1953         writel(val, pmc_base + PMC_SLEEP_CFG);
1954
1955         /* Clear the walk pointers and wake alarm */
1956         val = readl(pmc_base + PMC_TRIGGERS);
1957         val |= UHSIC_CLR_WAKE_ALARM_P0 | UHSIC_CLR_WALK_PTR_P0;
1958         writel(val, pmc_base + PMC_TRIGGERS);
1959
1960         /* Turn over pad configuration to PMC  for line wake events*/
1961         val = readl(pmc_base + PMC_SLEEP_CFG);
1962         val |= UHSIC_MASTER_ENABLE;
1963         writel(val, pmc_base + PMC_SLEEP_CFG);
1964
1965         val = readl(base + UHSIC_PMC_WAKEUP0);
1966         val |= EVENT_INT_ENB;
1967         writel(val, base + UHSIC_PMC_WAKEUP0);
1968
1969         DBG("%s:PMC enabled for HSIC remote wakeup\n", __func__);
1970 }
1971
1972 static void uhsic_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy)
1973 {
1974         unsigned long val;
1975         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1976         void __iomem *base = phy->regs;
1977
1978         DBG("%s (%d)\n", __func__, __LINE__);
1979         val = readl(pmc_base + PMC_SLEEP_CFG);
1980         val &= ~UHSIC_WAKE_VAL(WAKE_VAL_ANY);
1981         val |= UHSIC_WAKE_VAL(WAKE_VAL_NONE);
1982         writel(val, pmc_base + PMC_SLEEP_CFG);
1983
1984         val = readl(base + UHSIC_PMC_WAKEUP0);
1985         val &= ~EVENT_INT_ENB;
1986         writel(val, base + UHSIC_PMC_WAKEUP0);
1987
1988         /* Disable PMC master mode by clearing MASTER_EN */
1989         val = readl(pmc_base + PMC_SLEEP_CFG);
1990         val &= ~(UHSIC_MASTER_ENABLE);
1991         writel(val, pmc_base + PMC_SLEEP_CFG);
1992
1993         /* turn off pad detectors */
1994         val = readl(pmc_base + PMC_USB_AO);
1995         val |= (STROBE_VAL_PD_P0 | DATA_VAL_PD_P0);
1996         writel(val, pmc_base + PMC_USB_AO);
1997
1998         val = readl(pmc_base + PMC_TRIGGERS);
1999         val |= (UHSIC_CLR_WALK_PTR_P0 | UHSIC_CLR_WAKE_ALARM_P0);
2000         writel(val, pmc_base + PMC_TRIGGERS);
2001
2002         phy->remote_wakeup = false;
2003 }
2004
2005 static bool uhsic_phy_remotewake_detected(struct tegra_usb_phy *phy)
2006 {
2007         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
2008         void __iomem *base = phy->regs;
2009         u32 val;
2010
2011         val = readl(base + UHSIC_PMC_WAKEUP0);
2012         if (val & EVENT_INT_ENB) {
2013                 val = readl(pmc_base + UTMIP_UHSIC_STATUS);
2014                 if (UHSIC_WAKE_ALARM & val) {
2015                         val = readl(pmc_base + PMC_SLEEP_CFG);
2016                         val &= ~UHSIC_WAKE_VAL(WAKE_VAL_ANY);
2017                         val |= UHSIC_WAKE_VAL(WAKE_VAL_NONE);
2018                         writel(val, pmc_base + PMC_SLEEP_CFG);
2019
2020                         val = readl(pmc_base + PMC_TRIGGERS);
2021                         val |= UHSIC_CLR_WAKE_ALARM_P0;
2022                         writel(val, pmc_base + PMC_TRIGGERS);
2023
2024                         val = readl(base + UHSIC_PMC_WAKEUP0);
2025                         val &= ~EVENT_INT_ENB;
2026                         writel(val, base + UHSIC_PMC_WAKEUP0);
2027                         phy->remote_wakeup = true;
2028                         DBG("%s:PMC remote wakeup detected for HSIC\n", __func__);
2029                         return true;
2030                 }
2031         }
2032         return false;
2033 }
2034
2035 static int uhsic_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
2036 {
2037         DBG("%s(%d)\n", __func__, __LINE__);
2038
2039         if (!remote_wakeup)
2040                 usb_phy_wait_for_sof(phy);
2041
2042         return 0;
2043 }
2044
2045 static int uhsic_phy_post_resume(struct tegra_usb_phy *phy)
2046 {
2047         unsigned long val;
2048         void __iomem *base = phy->regs;
2049
2050         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2051         val = readl(base + USB_TXFILLTUNING);
2052         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
2053                 val = USB_FIFO_TXFILL_THRES(0x10);
2054                 writel(val, base + USB_TXFILLTUNING);
2055         }
2056
2057         return 0;
2058 }
2059
2060 static void uhsic_phy_restore_start(struct tegra_usb_phy *phy)
2061 {
2062         unsigned long val;
2063         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
2064         void __iomem *base = phy->regs;
2065
2066         val = readl(pmc_base + UTMIP_UHSIC_STATUS);
2067
2068         /* check whether we wake up from the remote resume */
2069         if (UHSIC_WALK_PTR_VAL & val) {
2070                 phy->remote_wakeup = true;
2071                 pr_info("%s: uhsic remote wakeup detected\n", __func__);
2072         } else {
2073                 if (!((UHSIC_STROBE_VAL_P0 | UHSIC_DATA_VAL_P0) & val)) {
2074                                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2075                 } else {
2076                         DBG("%s(%d): setting pretend connect\n", __func__, __LINE__);
2077                         val = readl(base + UHSIC_CMD_CFG0);
2078                         val |= UHSIC_PRETEND_CONNECT_DETECT;
2079                         writel(val, base + UHSIC_CMD_CFG0);
2080                 }
2081         }
2082 }
2083
2084 static void uhsic_phy_restore_end(struct tegra_usb_phy *phy)
2085 {
2086
2087         unsigned long val;
2088         void __iomem *base = phy->regs;
2089         int wait_time_us = 25000; /* FPR should be set by this time */
2090
2091         DBG("%s(%d)\n", __func__, __LINE__);
2092
2093         /* check whether we wake up from the remote resume */
2094         if (phy->remote_wakeup) {
2095                 /* wait until FPR bit is set automatically on remote resume */
2096                 do {
2097                         val = readl(base + USB_PORTSC);
2098                         udelay(1);
2099                         if (wait_time_us == 0) {
2100                                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2101                                 uhsic_phy_post_resume(phy);
2102                                 return;
2103                         }
2104                         wait_time_us--;
2105                 } while (val & (USB_PORTSC_RESUME | USB_PORTSC_SUSP));
2106
2107                 /* wait for 25 ms to port resume complete */
2108                 msleep(25);
2109                 /* disable PMC master control */
2110                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2111
2112                 /* Clear PCI and SRI bits to avoid an interrupt upon resume */
2113                 val = readl(base + USB_USBSTS);
2114                 writel(val, base + USB_USBSTS);
2115                 /* wait to avoid SOF if there is any */
2116                 if (usb_phy_reg_status_wait(base + USB_USBSTS,
2117                         USB_USBSTS_SRI, USB_USBSTS_SRI, 2500)) {
2118                         pr_warn("%s: timeout waiting for SOF\n", __func__);
2119                 }
2120                 uhsic_phy_post_resume(phy);
2121         } else {
2122                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2123         }
2124
2125         /* Set RUN bit */
2126         val = readl(base + USB_USBCMD);
2127         val |= USB_USBCMD_RS;
2128         writel(val, base + USB_USBCMD);
2129         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2130                                                  USB_USBCMD_RS, 2000)) {
2131                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2132                 return;
2133         }
2134 }
2135
2136 static int hsic_rail_enable(struct tegra_usb_phy *phy)
2137 {
2138         int ret;
2139
2140         if (phy->hsic_reg == NULL) {
2141                 phy->hsic_reg = regulator_get(NULL, "avdd_hsic");
2142                 if (IS_ERR_OR_NULL(phy->hsic_reg)) {
2143                         pr_err("HSIC: Could not get regulator avdd_hsic\n");
2144                         phy->hsic_reg = NULL;
2145                         return PTR_ERR(phy->hsic_reg);
2146                 }
2147         }
2148
2149         ret = regulator_enable(phy->hsic_reg);
2150         if (ret < 0) {
2151                 pr_err("%s avdd_hsic could not be enabled\n", __func__);
2152                 return ret;
2153         }
2154
2155         return 0;
2156 }
2157
2158 static int hsic_rail_disable(struct tegra_usb_phy *phy)
2159 {
2160         int ret;
2161
2162         if (phy->hsic_reg == NULL) {
2163                 pr_warn("%s: unbalanced disable\n", __func__);
2164                 return -EIO;
2165         }
2166
2167         ret = regulator_disable(phy->hsic_reg);
2168         if (ret < 0) {
2169                 pr_err("HSIC regulator avdd_hsic cannot be disabled\n");
2170                 return ret;
2171         }
2172
2173         return 0;
2174 }
2175
2176 static int uhsic_phy_open(struct tegra_usb_phy *phy)
2177 {
2178         unsigned long parent_rate;
2179         int i;
2180         int ret;
2181
2182         phy->hsic_reg = NULL;
2183         ret = hsic_rail_enable(phy);
2184         if (ret < 0) {
2185                 pr_err("%s avdd_hsic could not be enabled\n", __func__);
2186                 return ret;
2187         }
2188
2189         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2190         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
2191         for (i = 0; i < ARRAY_SIZE(uhsic_freq_table); i++) {
2192                 if (uhsic_freq_table[i].freq == parent_rate) {
2193                         phy->freq = &uhsic_freq_table[i];
2194                         break;
2195                 }
2196         }
2197         if (!phy->freq) {
2198                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
2199                 return -EINVAL;
2200         }
2201
2202         uhsic_powerup_pmc_wake_detect(phy);
2203
2204         return 0;
2205 }
2206
2207 static void uhsic_phy_close(struct tegra_usb_phy *phy)
2208 {
2209         int ret;
2210
2211         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2212         uhsic_powerdown_pmc_wake_detect(phy);
2213
2214         ret = hsic_rail_disable(phy);
2215         if (ret < 0)
2216                 pr_err("%s avdd_hsic could not be disabled\n", __func__);
2217 }
2218
2219 static int uhsic_phy_irq(struct tegra_usb_phy *phy)
2220 {
2221         usb_phy_fence_read(phy);
2222         /* check if there is any remote wake event */
2223         if (uhsic_phy_remotewake_detected(phy))
2224                 pr_info("%s: uhsic remote wake detected\n", __func__);
2225         return IRQ_HANDLED;
2226 }
2227
2228 static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
2229 {
2230         unsigned long val;
2231         void __iomem *base = phy->regs;
2232
2233         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2234
2235         if (phy->phy_clk_on) {
2236                 DBG("%s(%d) inst:[%d] phy clk is already On\n",
2237                                         __func__, __LINE__, phy->inst);
2238                 return 0;
2239         }
2240
2241         val = readl(base + UHSIC_PADS_CFG1);
2242         val &= ~(UHSIC_PD_BG | UHSIC_PD_TRK | UHSIC_PD_RX |
2243                         UHSIC_PD_ZI | UHSIC_RPD_DATA | UHSIC_RPD_STROBE);
2244         val |= (UHSIC_RX_SEL | UHSIC_PD_TX);
2245         writel(val, base + UHSIC_PADS_CFG1);
2246
2247         val = readl(base + USB_SUSP_CTRL);
2248         val |= UHSIC_RESET;
2249         writel(val, base + USB_SUSP_CTRL);
2250         udelay(1);
2251
2252         val = readl(base + USB_SUSP_CTRL);
2253         val |= UHSIC_PHY_ENABLE;
2254         writel(val, base + USB_SUSP_CTRL);
2255
2256         val = readl(base + UHSIC_HSRX_CFG0);
2257         val |= UHSIC_IDLE_WAIT(HSIC_IDLE_WAIT_DELAY);
2258         val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(HSIC_ELASTIC_UNDERRUN_LIMIT);
2259         val |= UHSIC_ELASTIC_OVERRUN_LIMIT(HSIC_ELASTIC_OVERRUN_LIMIT);
2260         writel(val, base + UHSIC_HSRX_CFG0);
2261
2262         val = readl(base + UHSIC_HSRX_CFG1);
2263         val |= UHSIC_HS_SYNC_START_DLY(HSIC_SYNC_START_DELAY);
2264         writel(val, base + UHSIC_HSRX_CFG1);
2265
2266         /* WAR HSIC TX */
2267         val = readl(base + UHSIC_TX_CFG0);
2268         val &= ~UHSIC_HS_READY_WAIT_FOR_VALID;
2269         writel(val, base + UHSIC_TX_CFG0);
2270
2271         val = readl(base + UHSIC_MISC_CFG0);
2272         val |= UHSIC_SUSPEND_EXIT_ON_EDGE;
2273         /* Disable generic bus reset, to allow AP30 specific bus reset*/
2274         val |= UHSIC_DISABLE_BUSRESET;
2275         writel(val, base + UHSIC_MISC_CFG0);
2276
2277         val = readl(base + UHSIC_MISC_CFG1);
2278         val |= UHSIC_PLLU_STABLE_COUNT(phy->freq->stable_count);
2279         writel(val, base + UHSIC_MISC_CFG1);
2280
2281         val = readl(base + UHSIC_PLL_CFG1);
2282         val |= UHSIC_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
2283         val |= UHSIC_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count);
2284         writel(val, base + UHSIC_PLL_CFG1);
2285
2286         val = readl(base + USB_SUSP_CTRL);
2287         val &= ~(UHSIC_RESET);
2288         writel(val, base + USB_SUSP_CTRL);
2289         udelay(1);
2290
2291         val = readl(base + UHSIC_PADS_CFG1);
2292         val &= ~(UHSIC_PD_TX);
2293         writel(val, base + UHSIC_PADS_CFG1);
2294
2295         val = readl(base + USB_USBMODE);
2296         val |= USB_USBMODE_HOST;
2297         writel(val, base + USB_USBMODE);
2298
2299         /* Change the USB controller PHY type to HSIC */
2300         val = readl(base + HOSTPC1_DEVLC);
2301         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
2302         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2303         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
2304         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2305         val &= ~HOSTPC1_DEVLC_STS;
2306         writel(val, base + HOSTPC1_DEVLC);
2307
2308         val = readl(base + USB_TXFILLTUNING);
2309         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
2310                 val = USB_FIFO_TXFILL_THRES(0x10);
2311                 writel(val, base + USB_TXFILLTUNING);
2312         }
2313
2314         val = readl(base + USB_PORTSC);
2315         val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN);
2316         writel(val, base + USB_PORTSC);
2317
2318         val = readl(base + UHSIC_PADS_CFG0);
2319         val &= ~(UHSIC_TX_RTUNEN);
2320         /* set Rtune impedance to 50 ohm */
2321         val |= UHSIC_TX_RTUNE(8);
2322         writel(val, base + UHSIC_PADS_CFG0);
2323
2324         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
2325                                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500)) {
2326                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2327                 return -ETIMEDOUT;
2328         }
2329
2330         phy->phy_clk_on = true;
2331         phy->hw_accessible = true;
2332
2333         if (phy->pmc_sleepwalk) {
2334                 DBG("%s(%d) inst:[%d] restore phy\n", __func__, __LINE__,
2335                                         phy->inst);
2336                 uhsic_phy_restore_start(phy);
2337                 usb_phy_bringup_host_controller(phy);
2338                 uhsic_phy_restore_end(phy);
2339                 phy->pmc_sleepwalk = false;
2340         }
2341
2342         return 0;
2343 }
2344
2345 static int uhsic_phy_power_off(struct tegra_usb_phy *phy)
2346 {
2347         unsigned long val;
2348         void __iomem *base = phy->regs;
2349
2350         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2351         if (!phy->phy_clk_on) {
2352                 DBG("%s(%d) inst:[%d] phy clk is already off\n",
2353                                         __func__, __LINE__, phy->inst);
2354                 return 0;
2355         }
2356
2357         phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
2358                         HOSTPC1_DEVLC_PSPD_MASK;
2359
2360         /* Disable interrupts */
2361         writel(0, base + USB_USBINTR);
2362
2363         if (phy->pmc_sleepwalk == false) {
2364                 uhsic_setup_pmc_wake_detect(phy);
2365                 phy->pmc_sleepwalk = true;
2366         }
2367
2368         val = readl(base + HOSTPC1_DEVLC);
2369         val |= HOSTPC1_DEVLC_PHCD;
2370         writel(val, base + HOSTPC1_DEVLC);
2371
2372         /* Remove power downs for HSIC from PADS CFG1 register */
2373         val = readl(base + UHSIC_PADS_CFG1);
2374         val |= (UHSIC_PD_BG |UHSIC_PD_TRK | UHSIC_PD_RX |
2375                         UHSIC_PD_ZI | UHSIC_PD_TX);
2376         writel(val, base + UHSIC_PADS_CFG1);
2377         phy->phy_clk_on = false;
2378         phy->hw_accessible = false;
2379
2380         return 0;
2381 }
2382
2383 static int uhsic_phy_bus_port_power(struct tegra_usb_phy *phy)
2384 {
2385         unsigned long val;
2386         void __iomem *base = phy->regs;
2387
2388         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2389
2390         val = readl(base + USB_USBMODE);
2391         val |= USB_USBMODE_HOST;
2392         writel(val, base + USB_USBMODE);
2393
2394         /* Change the USB controller PHY type to HSIC */
2395         val = readl(base + HOSTPC1_DEVLC);
2396         val &= ~(HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK));
2397         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2398         val &= ~(HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK));
2399         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2400         writel(val, base + HOSTPC1_DEVLC);
2401
2402         val = readl(base + UHSIC_MISC_CFG0);
2403         val |= UHSIC_DETECT_SHORT_CONNECT;
2404         writel(val, base + UHSIC_MISC_CFG0);
2405         udelay(1);
2406
2407         val = readl(base + UHSIC_MISC_CFG0);
2408         val |= UHSIC_FORCE_XCVR_MODE;
2409         writel(val, base + UHSIC_MISC_CFG0);
2410
2411         val = readl(base + UHSIC_PADS_CFG1);
2412         val &= ~UHSIC_RPD_STROBE;
2413         writel(val, base + UHSIC_PADS_CFG1);
2414
2415         if (phy->pdata->ops && phy->pdata->ops->port_power)
2416                 phy->pdata->ops->port_power();
2417
2418         if (usb_phy_reg_status_wait(base + UHSIC_STAT_CFG0,
2419                         UHSIC_CONNECT_DETECT, UHSIC_CONNECT_DETECT, 25000)) {
2420                 pr_err("%s: timeout waiting for UHSIC_CONNECT_DETECT\n",
2421                                                                 __func__);
2422                 return -ETIMEDOUT;
2423         }
2424
2425         return 0;
2426 }
2427
2428 static int uhsic_phy_bus_reset(struct tegra_usb_phy *phy)
2429 {
2430         unsigned long val;
2431         void __iomem *base = phy->regs;
2432
2433         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2434
2435         /* Change the USB controller PHY type to HSIC */
2436         val = readl(base + HOSTPC1_DEVLC);
2437         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
2438         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2439         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
2440         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2441         val &= ~HOSTPC1_DEVLC_STS;
2442         writel(val, base + HOSTPC1_DEVLC);
2443         /* wait here, otherwise HOSTPC1_DEVLC_PSPD will timeout */
2444         mdelay(5);
2445
2446         val = readl(base + USB_PORTSC);
2447         val |= USB_PORTSC_PTC(5);
2448         writel(val, base + USB_PORTSC);
2449         udelay(2);
2450
2451         val = readl(base + USB_PORTSC);
2452         val &= ~(USB_PORTSC_PTC(~0));
2453         writel(val, base + USB_PORTSC);
2454         udelay(2);
2455
2456         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_LS(0),
2457                                                  0, 2000)) {
2458                 pr_err("%s: timeout waiting for USB_PORTSC_LS\n", __func__);
2459                 return -ETIMEDOUT;
2460         }
2461
2462         /* Poll until CCS is enabled */
2463         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
2464                                                  USB_PORTSC_CCS, 2000)) {
2465                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
2466                 return -ETIMEDOUT;
2467         }
2468
2469         if (usb_phy_reg_status_wait(base + HOSTPC1_DEVLC,
2470                         HOSTPC1_DEVLC_PSPD(2),
2471                         HOSTPC1_DEVLC_PSPD(2), 2000) < 0) {
2472                 pr_err("%s: timeout waiting hsic high speed configuration\n",
2473                                                 __func__);
2474                         return -ETIMEDOUT;
2475         }
2476
2477         val = readl(base + USB_USBCMD);
2478         val &= ~USB_USBCMD_RS;
2479         writel(val, base + USB_USBCMD);
2480
2481         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
2482                                                  USB_USBSTS_HCH, 2000)) {
2483                 pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
2484                 return -ETIMEDOUT;
2485         }
2486
2487         val = readl(base + UHSIC_PADS_CFG1);
2488         val &= ~UHSIC_RPU_STROBE;
2489         val |= UHSIC_RPD_STROBE;
2490         writel(val, base + UHSIC_PADS_CFG1);
2491
2492         mdelay(50);
2493
2494         val = readl(base + UHSIC_PADS_CFG1);
2495         val &= ~UHSIC_RPD_STROBE;
2496         val |= UHSIC_RPU_STROBE;
2497         writel(val, base + UHSIC_PADS_CFG1);
2498
2499         val = readl(base + USB_USBCMD);
2500         val |= USB_USBCMD_RS;
2501         writel(val, base + USB_USBCMD);
2502
2503         val = readl(base + UHSIC_PADS_CFG1);
2504         val &= ~UHSIC_RPU_STROBE;
2505         writel(val, base + UHSIC_PADS_CFG1);
2506
2507         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2508                                                  USB_USBCMD_RS, 2000)) {
2509                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2510                 return -ETIMEDOUT;
2511         }
2512
2513         return 0;
2514 }
2515
2516 int uhsic_phy_resume(struct tegra_usb_phy *phy)
2517 {
2518         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2519
2520         return 0;
2521 }
2522
2523 static void ulpi_set_trimmer(struct tegra_usb_phy *phy)
2524 {
2525         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2526         void __iomem *base = phy->regs;
2527         unsigned long val;
2528
2529         val = ULPI_DATA_TRIMMER_SEL(config->data_trimmer);
2530         val |= ULPI_STPDIRNXT_TRIMMER_SEL(config->stpdirnxt_trimmer);
2531         val |= ULPI_DIR_TRIMMER_SEL(config->dir_trimmer);
2532         writel(val, base + ULPI_TIMING_CTRL_1);
2533         udelay(10);
2534
2535         val |= ULPI_DATA_TRIMMER_LOAD;
2536         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
2537         val |= ULPI_DIR_TRIMMER_LOAD;
2538         writel(val, base + ULPI_TIMING_CTRL_1);
2539 }
2540
2541 static void reset_utmip_uhsic(void __iomem *base)
2542 {
2543         unsigned long val;
2544
2545         val = readl(base + USB_SUSP_CTRL);
2546         val |= UHSIC_RESET;
2547         writel(val, base + USB_SUSP_CTRL);
2548
2549         val = readl(base + USB_SUSP_CTRL);
2550         val |= UTMIP_RESET;
2551         writel(val, base + USB_SUSP_CTRL);
2552 }
2553
2554 static void ulpi_set_host(void __iomem *base)
2555 {
2556         unsigned long val;
2557
2558         val = readl(base + USB_USBMODE);
2559         val &= ~USB_USBMODE_MASK;
2560         val |= USB_USBMODE_HOST;
2561         writel(val, base + USB_USBMODE);
2562
2563         val = readl(base + HOSTPC1_DEVLC);
2564         val |= HOSTPC1_DEVLC_PTS(2);
2565         writel(val, base + HOSTPC1_DEVLC);
2566 }
2567
2568 static inline void ulpi_pinmux_bypass(struct tegra_usb_phy *phy, bool enable)
2569 {
2570         unsigned long val;
2571         void __iomem *base = phy->regs;
2572
2573         val = readl(base + ULPI_TIMING_CTRL_0);
2574
2575         if (enable)
2576                 val |= ULPI_OUTPUT_PINMUX_BYP;
2577         else
2578                 val &= ~ULPI_OUTPUT_PINMUX_BYP;
2579
2580         writel(val, base + ULPI_TIMING_CTRL_0);
2581 }
2582
2583 static inline void ulpi_null_phy_set_tristate(bool enable)
2584 {
2585 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2586         int tristate = (enable) ? TEGRA_TRI_TRISTATE : TEGRA_TRI_NORMAL;
2587
2588         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA0, tristate);
2589         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA1, tristate);
2590         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA2, tristate);
2591         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA3, tristate);
2592         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA4, tristate);
2593         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA5, tristate);
2594         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA6, tristate);
2595         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA7, tristate);
2596         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_NXT, tristate);
2597
2598         if (enable)
2599                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR, tristate);
2600 #endif
2601 }
2602
2603 static void ulpi_null_phy_obs_read(void)
2604 {
2605         static void __iomem *apb_misc;
2606         unsigned slv0_obs, s2s_obs;
2607
2608         if (!apb_misc)
2609                 apb_misc = ioremap(TEGRA_APB_MISC_BASE, TEGRA_APB_MISC_SIZE);
2610
2611         writel(0x80d1003c, apb_misc + APB_MISC_GP_OBSCTRL_0);
2612         slv0_obs = readl(apb_misc + APB_MISC_GP_OBSDATA_0);
2613
2614         writel(0x80d10040, apb_misc + APB_MISC_GP_OBSCTRL_0);
2615         s2s_obs = readl(apb_misc + APB_MISC_GP_OBSDATA_0);
2616
2617         pr_debug("slv0 obs: %08x\ns2s obs: %08x\n", slv0_obs, s2s_obs);
2618 }
2619
2620 static const struct gpio ulpi_gpios[] = {
2621         {ULPI_STP, GPIOF_IN, "ULPI_STP"},
2622         {ULPI_DIR, GPIOF_OUT_INIT_LOW, "ULPI_DIR"},
2623         {ULPI_D0, GPIOF_OUT_INIT_LOW, "ULPI_D0"},
2624         {ULPI_D1, GPIOF_OUT_INIT_LOW, "ULPI_D1"},
2625 };
2626
2627 static int ulpi_null_phy_open(struct tegra_usb_phy *phy)
2628 {
2629         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2630         int ret;
2631
2632         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2633
2634         ret = gpio_request_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
2635         if (ret)
2636                 return ret;
2637
2638         if (gpio_is_valid(config->phy_restore_gpio)) {
2639                 ret = gpio_request(config->phy_restore_gpio, "phy_restore");
2640                 if (ret)
2641                         goto err_gpio_free;
2642
2643                 gpio_direction_input(config->phy_restore_gpio);
2644         }
2645
2646         tegra_periph_reset_assert(phy->ctrlr_clk);
2647         udelay(10);
2648         tegra_periph_reset_deassert(phy->ctrlr_clk);
2649
2650         return 0;
2651
2652 err_gpio_free:
2653         gpio_free_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
2654         return ret;
2655 }
2656
2657 static void ulpi_null_phy_close(struct tegra_usb_phy *phy)
2658 {
2659         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2660
2661         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2662
2663         if (gpio_is_valid(config->phy_restore_gpio))
2664                 gpio_free(config->phy_restore_gpio);
2665
2666         gpio_free_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
2667 }
2668
2669 static int ulpi_null_phy_power_off(struct tegra_usb_phy *phy)
2670 {
2671         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2672
2673         if (!phy->phy_clk_on) {
2674                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
2675                                                         __LINE__, phy->inst);
2676                 return 0;
2677         }
2678
2679         phy->phy_clk_on = false;
2680         phy->hw_accessible = false;
2681         ulpi_null_phy_set_tristate(true);
2682         return 0;
2683 }
2684
2685 /* NOTE: this function must be called before ehci reset */
2686 static int ulpi_null_phy_init(struct tegra_usb_phy *phy)
2687 {
2688         unsigned long val;
2689         void __iomem *base = phy->regs;
2690
2691         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2692         val = readl(base + ULPIS2S_CTRL);
2693         val |=  ULPIS2S_SLV0_CLAMP_XMIT;
2694         writel(val, base + ULPIS2S_CTRL);
2695
2696         val = readl(base + USB_SUSP_CTRL);
2697         val |= ULPIS2S_SLV0_RESET;
2698         writel(val, base + USB_SUSP_CTRL);
2699         udelay(10);
2700
2701         return 0;
2702 }
2703
2704 static int ulpi_null_phy_irq(struct tegra_usb_phy *phy)
2705 {
2706         unsigned long val;
2707         void __iomem *base = phy->regs;
2708
2709         usb_phy_fence_read(phy);
2710         if (phy->bus_reseting){
2711                 val = readl(base + USB_USBCMD);
2712                 val |= USB_USBCMD_RS;
2713                 writel(val, base + USB_USBCMD);
2714                 phy->bus_reseting = false;
2715         }
2716         return IRQ_HANDLED;
2717 }
2718
2719 /* NOTE: this function must be called after ehci reset */
2720 static int ulpi_null_phy_cmd_reset(struct tegra_usb_phy *phy)
2721 {
2722         unsigned long val;
2723         void __iomem *base = phy->regs;
2724
2725         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2726         ulpi_set_host(base);
2727
2728         /* remove slave0 reset */
2729         val = readl(base + USB_SUSP_CTRL);
2730         val &= ~ULPIS2S_SLV0_RESET;
2731         writel(val, base + USB_SUSP_CTRL);
2732
2733         val = readl(base + ULPIS2S_CTRL);
2734         val &=  ~ULPIS2S_SLV0_CLAMP_XMIT;
2735         writel(val, base + ULPIS2S_CTRL);
2736         udelay(10);
2737
2738         return 0;
2739 }
2740
2741 static int ulpi_phy_bus_reset(struct tegra_usb_phy *phy)
2742 {
2743         unsigned long val;
2744         void __iomem *base = phy->regs;
2745
2746         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2747
2748         /*DISABLE RUN BIT */
2749
2750         val = readl(base + USB_USBCMD);
2751         val &= ~USB_USBCMD_RS;
2752         writel(val, base + USB_USBCMD);
2753         phy->bus_reseting = true;
2754
2755         return 0;
2756 }
2757
2758 static int ulpi_null_phy_restore(struct tegra_usb_phy *phy)
2759 {
2760         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2761         unsigned long timeout;
2762         int ulpi_stp = ULPI_STP;
2763
2764         if (gpio_is_valid(config->phy_restore_gpio))
2765                 ulpi_stp = config->phy_restore_gpio;
2766
2767         /* disable ULPI pinmux bypass */
2768         ulpi_pinmux_bypass(phy, false);
2769
2770         /* driving linstate by GPIO */
2771         gpio_set_value(ULPI_D0, 0);
2772         gpio_set_value(ULPI_D1, 0);
2773
2774         /* driving DIR high */
2775         gpio_set_value(ULPI_DIR, 1);
2776
2777         /* remove ULPI tristate */
2778         ulpi_null_phy_set_tristate(false);
2779
2780         /* wait for STP high */
2781         timeout = jiffies + msecs_to_jiffies(25);
2782
2783         while (!gpio_get_value(ulpi_stp)) {
2784                 if (time_after(jiffies, timeout)) {
2785                         pr_warn("phy restore timeout\n");
2786                         return 1;
2787                 }
2788         }
2789
2790         return 0;
2791 }
2792
2793 static int ulpi_null_phy_lp0_resume(struct tegra_usb_phy *phy)
2794 {
2795         unsigned long val;
2796         void __iomem *base = phy->regs;
2797
2798         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2799         ulpi_null_phy_init(phy);
2800
2801         val = readl(base + USB_USBCMD);
2802         val |= USB_CMD_RESET;
2803         writel(val, base + USB_USBCMD);
2804
2805         if (usb_phy_reg_status_wait(base + USB_USBCMD,
2806                 USB_CMD_RESET, 0, 2500) < 0) {
2807                 pr_err("%s: timeout waiting for reset\n", __func__);
2808         }
2809
2810         ulpi_null_phy_cmd_reset(phy);
2811
2812         val = readl(base + USB_USBCMD);
2813         val |= USB_USBCMD_RS;
2814         writel(val, base + USB_USBCMD);
2815         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2816                                                  USB_USBCMD_RS, 2000)) {
2817                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2818                 return -ETIMEDOUT;
2819         }
2820
2821         /* Enable Port Power */
2822         val = readl(base + USB_PORTSC);
2823         val |= USB_PORTSC_PP;
2824         writel(val, base + USB_PORTSC);
2825         udelay(10);
2826
2827         ulpi_null_phy_restore(phy);
2828
2829         return 0;
2830 }
2831
2832 static int ulpi_null_phy_power_on(struct tegra_usb_phy *phy)
2833 {
2834         unsigned long val;
2835         void __iomem *base = phy->regs;
2836         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2837
2838         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2839         if (phy->phy_clk_on) {
2840                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
2841                                                         __LINE__, phy->inst);
2842                 return 0;
2843         }
2844         reset_utmip_uhsic(base);
2845
2846         /* remove ULPI PADS CLKEN reset */
2847         val = readl(base + USB_SUSP_CTRL);
2848         val &= ~ULPI_PADS_CLKEN_RESET;
2849         writel(val, base + USB_SUSP_CTRL);
2850         udelay(10);
2851
2852         val = readl(base + ULPI_TIMING_CTRL_0);
2853         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
2854         writel(val, base + ULPI_TIMING_CTRL_0);
2855
2856         val = readl(base + USB_SUSP_CTRL);
2857         val |= ULPI_PHY_ENABLE;
2858         writel(val, base + USB_SUSP_CTRL);
2859         udelay(10);
2860
2861         /* set timming parameters */
2862         val = readl(base + ULPI_TIMING_CTRL_0);
2863         val |= ULPI_SHADOW_CLK_LOOPBACK_EN;
2864         val &= ~ULPI_SHADOW_CLK_SEL;
2865         val &= ~ULPI_LBK_PAD_EN;
2866         val |= ULPI_SHADOW_CLK_DELAY(config->shadow_clk_delay);
2867         val |= ULPI_CLOCK_OUT_DELAY(config->clock_out_delay);
2868         val |= ULPI_LBK_PAD_E_INPUT_OR;
2869         writel(val, base + ULPI_TIMING_CTRL_0);
2870
2871         writel(0, base + ULPI_TIMING_CTRL_1);
2872         udelay(10);
2873
2874         /* start internal 60MHz clock */
2875         val = readl(base + ULPIS2S_CTRL);
2876         val |= ULPIS2S_ENA;
2877         val |= ULPIS2S_SUPPORT_DISCONNECT;
2878         val |= ULPIS2S_SPARE((phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) ? 3 : 1);
2879         val |= ULPIS2S_PLLU_MASTER_BLASTER60;
2880         writel(val, base + ULPIS2S_CTRL);
2881
2882         /* select ULPI_CORE_CLK_SEL to SHADOW_CLK */
2883         val = readl(base + ULPI_TIMING_CTRL_0);
2884         val |= ULPI_CORE_CLK_SEL;
2885         writel(val, base + ULPI_TIMING_CTRL_0);
2886         udelay(10);
2887
2888         /* enable ULPI null phy clock - can't set the trimmers before this */
2889         val = readl(base + ULPI_TIMING_CTRL_0);
2890         val |= ULPI_CLK_OUT_ENA;
2891         writel(val, base + ULPI_TIMING_CTRL_0);
2892         udelay(10);
2893
2894         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
2895                                                  USB_PHY_CLK_VALID, 2500)) {
2896                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2897                 return -ETIMEDOUT;
2898         }
2899
2900         /* set ULPI trimmers */
2901         ulpi_set_trimmer(phy);
2902
2903         ulpi_set_host(base);
2904
2905         /* remove slave0 reset */
2906         val = readl(base + USB_SUSP_CTRL);
2907         val &= ~ULPIS2S_SLV0_RESET;
2908         writel(val, base + USB_SUSP_CTRL);
2909
2910         /* remove slave1 and line reset */
2911         val = readl(base + USB_SUSP_CTRL);
2912         val &= ~ULPIS2S_SLV1_RESET;
2913         val &= ~ULPIS2S_LINE_RESET;
2914
2915         /* remove ULPI PADS reset */
2916         val &= ~ULPI_PADS_RESET;
2917         writel(val, base + USB_SUSP_CTRL);
2918
2919         if (!phy->ulpi_clk_padout_ena) {
2920                 val = readl(base + ULPI_TIMING_CTRL_0);
2921                 val |= ULPI_CLK_PADOUT_ENA;
2922                 writel(val, base + ULPI_TIMING_CTRL_0);
2923                 phy->ulpi_clk_padout_ena = true;
2924         } else {
2925                 if (!readl(base + USB_ASYNCLISTADDR))
2926                         ulpi_null_phy_lp0_resume(phy);
2927         }
2928         udelay(10);
2929
2930         phy->bus_reseting = false;
2931         phy->phy_clk_on = true;
2932         phy->hw_accessible = true;
2933
2934         return 0;
2935 }
2936
2937 static int ulpi_null_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
2938 {
2939         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2940         ulpi_null_phy_obs_read();
2941         usb_phy_wait_for_sof(phy);
2942         ulpi_null_phy_obs_read();
2943         return 0;
2944 }
2945
2946 static int ulpi_null_phy_post_resume(struct tegra_usb_phy *phy)
2947 {
2948         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2949         ulpi_null_phy_obs_read();
2950         return 0;
2951 }
2952
2953 static int ulpi_null_phy_resume(struct tegra_usb_phy *phy)
2954 {
2955         unsigned long val;
2956         void __iomem *base = phy->regs;
2957
2958         if (!readl(base + USB_ASYNCLISTADDR)) {
2959                 /* enable ULPI CLK output pad */
2960                 val = readl(base + ULPI_TIMING_CTRL_0);
2961                 val |= ULPI_CLK_PADOUT_ENA;
2962                 writel(val, base + ULPI_TIMING_CTRL_0);
2963
2964                 /* enable ULPI pinmux bypass */
2965                 ulpi_pinmux_bypass(phy, true);
2966                 udelay(5);
2967 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2968                 /* remove DIR tristate */
2969                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR,
2970                                           TEGRA_TRI_NORMAL);
2971 #endif
2972         }
2973         return 0;
2974 }
2975
2976
2977
2978 static struct tegra_usb_phy_ops utmi_phy_ops = {
2979         .open           = utmi_phy_open,
2980         .close          = utmi_phy_close,
2981         .irq            = utmi_phy_irq,
2982         .power_on       = utmi_phy_power_on,
2983         .power_off      = utmi_phy_power_off,
2984         .pre_resume = utmi_phy_pre_resume,
2985         .resume = utmi_phy_resume,
2986         .post_resume    = utmi_phy_post_resume,
2987         .charger_detect = utmi_phy_charger_detect,
2988         .post_suspend   = phy_post_suspend,
2989 };
2990
2991 static struct tegra_usb_phy_ops uhsic_phy_ops = {
2992         .open           = uhsic_phy_open,
2993         .close          = uhsic_phy_close,
2994         .irq            = uhsic_phy_irq,
2995         .power_on       = uhsic_phy_power_on,
2996         .power_off      = uhsic_phy_power_off,
2997         .pre_resume = uhsic_phy_pre_resume,
2998         .resume = uhsic_phy_resume,
2999         .post_resume = uhsic_phy_post_resume,
3000         .port_power = uhsic_phy_bus_port_power,
3001         .bus_reset      = uhsic_phy_bus_reset,
3002         .post_suspend   = phy_post_suspend,
3003 };
3004
3005 static struct tegra_usb_phy_ops ulpi_null_phy_ops = {
3006         .open           = ulpi_null_phy_open,
3007         .close          = ulpi_null_phy_close,
3008         .init           = ulpi_null_phy_init,
3009         .irq            = ulpi_null_phy_irq,
3010         .power_on       = ulpi_null_phy_power_on,
3011         .power_off      = ulpi_null_phy_power_off,
3012         .pre_resume = ulpi_null_phy_pre_resume,
3013         .resume = ulpi_null_phy_resume,
3014         .post_resume = ulpi_null_phy_post_resume,
3015         .reset          = ulpi_null_phy_cmd_reset,
3016         .post_suspend   = phy_post_suspend,
3017         .bus_reset      = ulpi_phy_bus_reset,
3018 };
3019
3020 static struct tegra_usb_phy_ops ulpi_link_phy_ops;
3021 static struct tegra_usb_phy_ops icusb_phy_ops;
3022
3023 static struct tegra_usb_phy_ops *phy_ops[] = {
3024         [TEGRA_USB_PHY_INTF_UTMI] = &utmi_phy_ops,
3025         [TEGRA_USB_PHY_INTF_ULPI_LINK] = &ulpi_link_phy_ops,
3026         [TEGRA_USB_PHY_INTF_ULPI_NULL] = &ulpi_null_phy_ops,
3027         [TEGRA_USB_PHY_INTF_HSIC] = &uhsic_phy_ops,
3028         [TEGRA_USB_PHY_INTF_ICUSB] = &icusb_phy_ops,
3029 };
3030
3031 int tegra3_usb_phy_init_ops(struct tegra_usb_phy *phy)
3032 {
3033         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
3034
3035         phy->ops = phy_ops[phy->pdata->phy_intf];
3036
3037         /* FIXME: uncommenting below line to make USB host mode fail*/
3038         /* usb_phy_power_down_pmc(); */
3039
3040         return 0;
3041 }