be38c4fcb9e1dfb1b3a0cbbfedd900fca2fe85cd
[linux-2.6.git] / arch / arm / mach-tegra / tegra3_usb_phy.c
1 /*
2  * arch/arm/mach-tegra/tegra3_usb_phy.c
3  *
4  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
5  *
6  *
7  * This software is licensed under the terms of the GNU General Public
8  * License version 2, as published by the Free Software Foundation, and
9  * may be copied, distributed, and modified under those terms.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17 #include <linux/resource.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/slab.h>
21 #include <linux/err.h>
22 #include <linux/platform_device.h>
23 #include <linux/io.h>
24 #include <linux/gpio.h>
25 #include <linux/interrupt.h>
26 #include <linux/clk.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <mach/clk.h>
30 #include <mach/iomap.h>
31 #include <mach/pinmux.h>
32 #include <mach/pinmux-tegra30.h>
33 #include "tegra_usb_phy.h"
34 #include "gpio-names.h"
35 #include "fuse.h"
36
37 #define USB_USBCMD              0x130
38 #define   USB_USBCMD_RS         (1 << 0)
39 #define   USB_CMD_RESET (1<<1)
40
41 #define USB_USBSTS              0x134
42 #define   USB_USBSTS_PCI        (1 << 2)
43 #define   USB_USBSTS_SRI        (1 << 7)
44 #define   USB_USBSTS_HCH        (1 << 12)
45
46 #define USB_USBINTR             0x138
47
48 #define USB_TXFILLTUNING        0x154
49 #define USB_FIFO_TXFILL_THRES(x)   (((x) & 0x1f) << 16)
50 #define USB_FIFO_TXFILL_MASK    0x1f0000
51
52 #define USB_ASYNCLISTADDR       0x148
53
54 #define ICUSB_CTRL              0x15c
55
56 #define USB_PORTSC              0x174
57 #define   USB_PORTSC_WKOC       (1 << 22)
58 #define   USB_PORTSC_WKDS       (1 << 21)
59 #define   USB_PORTSC_WKCN       (1 << 20)
60 #define   USB_PORTSC_PTC(x)     (((x) & 0xf) << 16)
61 #define   USB_PORTSC_PP (1 << 12)
62 #define   USB_PORTSC_LS(x) (((x) & 0x3) << 10)
63 #define   USB_PORTSC_SUSP       (1 << 7)
64 #define   USB_PORTSC_RESUME     (1 << 6)
65 #define   USB_PORTSC_OCC        (1 << 5)
66 #define   USB_PORTSC_PEC        (1 << 3)
67 #define   USB_PORTSC_PE         (1 << 2)
68 #define   USB_PORTSC_CSC        (1 << 1)
69 #define   USB_PORTSC_CCS        (1 << 0)
70 #define   USB_PORTSC_RWC_BITS (USB_PORTSC_CSC | USB_PORTSC_PEC | USB_PORTSC_OCC)
71
72 #define HOSTPC1_DEVLC           0x1b4
73 #define   HOSTPC1_DEVLC_PHCD            (1 << 22)
74 #define   HOSTPC1_DEVLC_PTS(x)          (((x) & 0x7) << 29)
75 #define   HOSTPC1_DEVLC_PTS_MASK        7
76 #define   HOSTPC1_DEVLC_PTS_HSIC        4
77 #define   HOSTPC1_DEVLC_STS             (1 << 28)
78 #define   HOSTPC1_DEVLC_PSPD(x)         (((x) & 0x3) << 25)
79 #define   HOSTPC1_DEVLC_PSPD_MASK       3
80 #define   HOSTPC1_DEVLC_PSPD_HIGH_SPEED 2
81
82 #define USB_USBMODE             0x1f8
83 #define   USB_USBMODE_MASK              (3 << 0)
84 #define   USB_USBMODE_HOST              (3 << 0)
85 #define   USB_USBMODE_DEVICE            (2 << 0)
86
87 #define USB_SUSP_CTRL           0x400
88 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
89 #define   USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
90 #define   USB_SUSP_CLR                  (1 << 5)
91 #define   USB_PHY_CLK_VALID             (1 << 7)
92 #define   USB_PHY_CLK_VALID_INT_ENB     (1 << 9)
93 #define   USB_PHY_CLK_VALID_INT_STS     (1 << 8)
94 #define   UTMIP_RESET                   (1 << 11)
95 #define   UTMIP_PHY_ENABLE              (1 << 12)
96 #define   ULPI_PHY_ENABLE               (1 << 13)
97 #define   UHSIC_RESET                   (1 << 14)
98 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
99 #define   UHSIC_PHY_ENABLE              (1 << 19)
100 #define   ULPIS2S_SLV0_RESET            (1 << 20)
101 #define   ULPIS2S_SLV1_RESET            (1 << 21)
102 #define   ULPIS2S_LINE_RESET            (1 << 22)
103 #define   ULPI_PADS_RESET               (1 << 23)
104 #define   ULPI_PADS_CLKEN_RESET         (1 << 24)
105
106 #define USB_PHY_VBUS_WAKEUP_ID  0x408
107 #define   VDAT_DET_INT_EN       (1 << 16)
108 #define   VDAT_DET_CHG_DET      (1 << 17)
109 #define   VDAT_DET_STS          (1 << 18)
110 #define   USB_ID_STATUS         (1 << 2)
111
112 #define ULPIS2S_CTRL            0x418
113 #define   ULPIS2S_ENA                   (1 << 0)
114 #define   ULPIS2S_SUPPORT_DISCONNECT    (1 << 2)
115 #define   ULPIS2S_PLLU_MASTER_BLASTER60 (1 << 3)
116 #define   ULPIS2S_SPARE(x)              (((x) & 0xF) << 8)
117 #define   ULPIS2S_FORCE_ULPI_CLK_OUT    (1 << 12)
118 #define   ULPIS2S_DISCON_DONT_CHECK_SE0 (1 << 13)
119 #define   ULPIS2S_SUPPORT_HS_KEEP_ALIVE (1 << 14)
120 #define   ULPIS2S_DISABLE_STP_PU        (1 << 15)
121 #define   ULPIS2S_SLV0_CLAMP_XMIT       (1 << 16)
122
123 #define ULPI_TIMING_CTRL_0      0x424
124 #define   ULPI_CLOCK_OUT_DELAY(x)       ((x) & 0x1F)
125 #define   ULPI_OUTPUT_PINMUX_BYP        (1 << 10)
126 #define   ULPI_CLKOUT_PINMUX_BYP        (1 << 11)
127 #define   ULPI_SHADOW_CLK_LOOPBACK_EN   (1 << 12)
128 #define   ULPI_SHADOW_CLK_SEL           (1 << 13)
129 #define   ULPI_CORE_CLK_SEL             (1 << 14)
130 #define   ULPI_SHADOW_CLK_DELAY(x)      (((x) & 0x1F) << 16)
131 #define   ULPI_LBK_PAD_EN               (1 << 26)
132 #define   ULPI_LBK_PAD_E_INPUT_OR       (1 << 27)
133 #define   ULPI_CLK_OUT_ENA              (1 << 28)
134 #define   ULPI_CLK_PADOUT_ENA           (1 << 29)
135
136 #define ULPI_TIMING_CTRL_1      0x428
137 #define   ULPI_DATA_TRIMMER_LOAD        (1 << 0)
138 #define   ULPI_DATA_TRIMMER_SEL(x)      (((x) & 0x7) << 1)
139 #define   ULPI_STPDIRNXT_TRIMMER_LOAD   (1 << 16)
140 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
141 #define   ULPI_DIR_TRIMMER_LOAD         (1 << 24)
142 #define   ULPI_DIR_TRIMMER_SEL(x)       (((x) & 0x7) << 25)
143
144 #define UTMIP_XCVR_CFG0         0x808
145 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
146 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
147 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
148 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
149 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
150 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
151 #define   UTMIP_XCVR_LSBIAS_SEL                 (1 << 21)
152 #define   UTMIP_XCVR_SETUP_MSB(x)               (((x) & 0x7) << 22)
153 #define   UTMIP_XCVR_HSSLEW_MSB(x)              (((x) & 0x7f) << 25)
154 #define   UTMIP_XCVR_MAX_OFFSET         2
155 #define   UTMIP_XCVR_SETUP_MAX_VALUE    0x7f
156 #define   UTMIP_XCVR_SETUP_MIN_VALUE    0
157 #define   XCVR_SETUP_MSB_CALIB(x) ((x) >> 4)
158
159 #define UTMIP_BIAS_CFG0         0x80c
160 #define   UTMIP_OTGPD                   (1 << 11)
161 #define   UTMIP_BIASPD                  (1 << 10)
162 #define   UTMIP_HSSQUELCH_LEVEL(x)      (((x) & 0x3) << 0)
163 #define   UTMIP_HSDISCON_LEVEL(x)       (((x) & 0x3) << 2)
164 #define   UTMIP_HSDISCON_LEVEL_MSB      (1 << 24)
165
166 #define UTMIP_HSRX_CFG0         0x810
167 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
168 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
169
170 #define UTMIP_HSRX_CFG1         0x814
171 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
172
173 #define UTMIP_TX_CFG0           0x820
174 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
175 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
176
177 #define UTMIP_DEBOUNCE_CFG0 0x82c
178 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
179
180 #define UTMIP_BAT_CHRG_CFG0 0x830
181 #define   UTMIP_PD_CHRG                 (1 << 0)
182 #define   UTMIP_ON_SINK_EN              (1 << 2)
183 #define   UTMIP_OP_SRC_EN               (1 << 3)
184
185 #define UTMIP_XCVR_CFG1         0x838
186 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
187 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
188 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
189 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
190
191 #define UTMIP_BIAS_CFG1         0x83c
192 #define   UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
193 #define   UTMIP_BIAS_PDTRK_POWERDOWN    (1 << 0)
194 #define   UTMIP_BIAS_PDTRK_POWERUP      (1 << 1)
195
196 #define UTMIP_MISC_CFG0         0x824
197 #define   UTMIP_DPDM_OBSERVE            (1 << 26)
198 #define   UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
199 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J   UTMIP_DPDM_OBSERVE_SEL(0xf)
200 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K   UTMIP_DPDM_OBSERVE_SEL(0xe)
201 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
202 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
203 #define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
204 #define   FORCE_PULLDN_DM       (1 << 8)
205 #define   FORCE_PULLDN_DP       (1 << 9)
206 #define   COMB_TERMS            (1 << 0)
207 #define   ALWAYS_FREE_RUNNING_TERMS (1 << 1)
208
209 #define UTMIP_SPARE_CFG0        0x834
210 #define   FUSE_SETUP_SEL                (1 << 3)
211 #define   FUSE_ATERM_SEL                (1 << 4)
212
213 #define UTMIP_PMC_WAKEUP0               0x84c
214 #define   EVENT_INT_ENB                 (1 << 0)
215
216 #define UHSIC_PMC_WAKEUP0               0xc34
217
218 #define UTMIP_BIAS_STS0                 0x840
219 #define   UTMIP_RCTRL_VAL(x)            (((x) & 0xffff) << 0)
220 #define   UTMIP_TCTRL_VAL(x)            (((x) & (0xffff << 16)) >> 16)
221
222 #define UHSIC_PLL_CFG1                          0xc04
223 #define   UHSIC_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
224 #define   UHSIC_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 14)
225
226 #define UHSIC_HSRX_CFG0                         0xc08
227 #define   UHSIC_ELASTIC_UNDERRUN_LIMIT(x)       (((x) & 0x1f) << 2)
228 #define   UHSIC_ELASTIC_OVERRUN_LIMIT(x)        (((x) & 0x1f) << 8)
229 #define   UHSIC_IDLE_WAIT(x)                    (((x) & 0x1f) << 13)
230
231 #define UHSIC_HSRX_CFG1                         0xc0c
232 #define   UHSIC_HS_SYNC_START_DLY(x)            (((x) & 0x1f) << 1)
233
234 #define UHSIC_TX_CFG0                           0xc10
235 #define UHSIC_HS_READY_WAIT_FOR_VALID   (1 << 9)
236 #define UHSIC_MISC_CFG0                         0xc14
237 #define   UHSIC_SUSPEND_EXIT_ON_EDGE            (1 << 7)
238 #define   UHSIC_DETECT_SHORT_CONNECT            (1 << 8)
239 #define   UHSIC_FORCE_XCVR_MODE                 (1 << 15)
240 #define   UHSIC_DISABLE_BUSRESET                (1 << 20)
241 #define UHSIC_MISC_CFG1                         0xc18
242 #define   UHSIC_PLLU_STABLE_COUNT(x)            (((x) & 0xfff) << 2)
243
244 #define UHSIC_PADS_CFG0                         0xc1c
245 #define   UHSIC_TX_RTUNEN                       0xf000
246 #define   UHSIC_TX_RTUNE(x)                     (((x) & 0xf) << 12)
247
248 #define UHSIC_PADS_CFG1                         0xc20
249 #define   UHSIC_PD_BG                           (1 << 2)
250 #define   UHSIC_PD_TX                           (1 << 3)
251 #define   UHSIC_PD_TRK                          (1 << 4)
252 #define   UHSIC_PD_RX                           (1 << 5)
253 #define   UHSIC_PD_ZI                           (1 << 6)
254 #define   UHSIC_RX_SEL                          (1 << 7)
255 #define   UHSIC_RPD_DATA                        (1 << 9)
256 #define   UHSIC_RPD_STROBE                      (1 << 10)
257 #define   UHSIC_RPU_DATA                        (1 << 11)
258 #define   UHSIC_RPU_STROBE                      (1 << 12)
259
260 #define UHSIC_CMD_CFG0                  0xc24
261 #define UHSIC_PRETEND_CONNECT_DETECT    (1 << 5)
262
263 #define UHSIC_STAT_CFG0         0xc28
264 #define UHSIC_CONNECT_DETECT            (1 << 0)
265
266 #define PMC_USB_DEBOUNCE                        0xec
267 #define UTMIP_LINE_DEB_CNT(x)           (((x) & 0xf) << 16)
268 #define UHSIC_LINE_DEB_CNT(x)           (((x) & 0xf) << 20)
269
270 #define PMC_USB_AO                              0xf0
271
272 #define PMC_POWER_DOWN_MASK                     0xffff
273 #define HSIC_RESERVED_P0                        (3 << 14)
274 #define STROBE_VAL_PD_P0                        (1 << 12)
275 #define DATA_VAL_PD_P0                          (1 << 13)
276
277 #define USB_ID_PD(inst)                 (1 << ((4*(inst))+3))
278 #define VBUS_WAKEUP_PD(inst)                    (1 << ((4*(inst))+2))
279 #define   USBON_VAL_PD(inst)                    (1 << ((4*(inst))+1))
280 #define   USBON_VAL_PD_P2                       (1 << 9)
281 #define   USBON_VAL_PD_P1                       (1 << 5)
282 #define   USBON_VAL_PD_P0                       (1 << 1)
283 #define   USBOP_VAL_PD(inst)                    (1 << (4*(inst)))
284 #define   USBOP_VAL_PD_P2                       (1 << 8)
285 #define   USBOP_VAL_PD_P1                       (1 << 4)
286 #define   USBOP_VAL_PD_P0                       (1 << 0)
287 #define   PMC_USB_AO_PD_P2                      (0xf << 8)
288 #define   PMC_USB_AO_ID_PD_P0                   (1 << 3)
289 #define   PMC_USB_AO_VBUS_WAKEUP_PD_P0  (1 << 2)
290
291 #define PMC_TRIGGERS                    0x1ec
292
293 #define   UHSIC_CLR_WALK_PTR_P0         (1 << 3)
294 #define   UTMIP_CLR_WALK_PTR(inst)      (1 << (inst))
295 #define   UTMIP_CLR_WALK_PTR_P2         (1 << 2)
296 #define   UTMIP_CLR_WALK_PTR_P1         (1 << 1)
297 #define   UTMIP_CLR_WALK_PTR_P0         (1 << 0)
298 #define   UTMIP_CAP_CFG(inst)   (1 << ((inst)+4))
299 #define   UTMIP_CAP_CFG_P2              (1 << 6)
300 #define   UTMIP_CAP_CFG_P1              (1 << 5)
301 #define   UTMIP_CAP_CFG_P0              (1 << 4)
302 #define   UTMIP_CLR_WAKE_ALARM(inst)    (1 << ((inst)+12))
303 #define   UHSIC_CLR_WAKE_ALARM_P0       (1 << 15)
304 #define   UTMIP_CLR_WAKE_ALARM_P2       (1 << 14)
305
306 #define PMC_PAD_CFG             (0x1f4)
307
308 #define PMC_UTMIP_TERM_PAD_CFG  0x1f8
309 #define   PMC_TCTRL_VAL(x)      (((x) & 0x1f) << 5)
310 #define   PMC_RCTRL_VAL(x)      (((x) & 0x1f) << 0)
311
312 #define PMC_SLEEP_CFG                   0x1fc
313
314 #define   UHSIC_MASTER_ENABLE                   (1 << 24)
315 #define   UHSIC_WAKE_VAL(x)             (((x) & 0xf) << 28)
316 #define   WAKE_VAL_SD10                 0x2
317 #define   UTMIP_TCTRL_USE_PMC(inst) (1 << ((8*(inst))+3))
318 #define   UTMIP_TCTRL_USE_PMC_P2                (1 << 19)
319 #define   UTMIP_TCTRL_USE_PMC_P1                (1 << 11)
320 #define   UTMIP_TCTRL_USE_PMC_P0                (1 << 3)
321 #define   UTMIP_RCTRL_USE_PMC(inst) (1 << ((8*(inst))+2))
322 #define   UTMIP_RCTRL_USE_PMC_P2                (1 << 18)
323 #define   UTMIP_RCTRL_USE_PMC_P1                (1 << 10)
324 #define   UTMIP_RCTRL_USE_PMC_P0                (1 << 2)
325 #define   UTMIP_FSLS_USE_PMC(inst)      (1 << ((8*(inst))+1))
326 #define   UTMIP_FSLS_USE_PMC_P2         (1 << 17)
327 #define   UTMIP_FSLS_USE_PMC_P1         (1 << 9)
328 #define   UTMIP_FSLS_USE_PMC_P0         (1 << 1)
329 #define   UTMIP_MASTER_ENABLE(inst) (1 << (8*(inst)))
330 #define   UTMIP_MASTER_ENABLE_P2                (1 << 16)
331 #define   UTMIP_MASTER_ENABLE_P1                (1 << 8)
332 #define   UTMIP_MASTER_ENABLE_P0                (1 << 0)
333 #define UHSIC_MASTER_ENABLE_P0          (1 << 24)
334 #define UHSIC_WAKE_VAL_P0(x)            (((x) & 0xf) << 28)
335
336 #define PMC_SLEEPWALK_CFG               0x200
337
338 #define   UHSIC_WAKE_WALK_EN_P0 (1 << 30)
339 #define   UHSIC_LINEVAL_WALK_EN (1 << 31)
340 #define   UTMIP_LINEVAL_WALK_EN(inst) (1 << ((8*(inst))+7))
341 #define   UTMIP_LINEVAL_WALK_EN_P2      (1 << 23)
342 #define   UTMIP_LINEVAL_WALK_EN_P1      (1 << 15)
343 #define   UTMIP_LINEVAL_WALK_EN_P0      (1 << 7)
344 #define   UTMIP_WAKE_VAL(inst, x) (((x) & 0xf) << ((8*(inst))+4))
345 #define   UTMIP_WAKE_VAL_P2(x)          (((x) & 0xf) << 20)
346 #define   UTMIP_WAKE_VAL_P1(x)          (((x) & 0xf) << 12)
347 #define   UTMIP_WAKE_VAL_P0(x)          (((x) & 0xf) << 4)
348 #define   WAKE_VAL_NONE         0xc
349 #define   WAKE_VAL_ANY                  0xF
350 #define   WAKE_VAL_FSJ                  0x2
351 #define   WAKE_VAL_FSK                  0x1
352 #define   WAKE_VAL_SE0                  0x0
353
354 #define PMC_SLEEPWALK_REG(inst)         (0x204 + (4*(inst)))
355 #define   UTMIP_USBOP_RPD_A     (1 << 0)
356 #define   UTMIP_USBON_RPD_A     (1 << 1)
357 #define   UTMIP_AP_A                    (1 << 4)
358 #define   UTMIP_AN_A                    (1 << 5)
359 #define   UTMIP_HIGHZ_A         (1 << 6)
360 #define   UTMIP_USBOP_RPD_B     (1 << 8)
361 #define   UTMIP_USBON_RPD_B     (1 << 9)
362 #define   UTMIP_AP_B                    (1 << 12)
363 #define   UTMIP_AN_B                    (1 << 13)
364 #define   UTMIP_HIGHZ_B         (1 << 14)
365 #define   UTMIP_USBOP_RPD_C     (1 << 16)
366 #define   UTMIP_USBON_RPD_C     (1 << 17)
367 #define   UTMIP_AP_C            (1 << 20)
368 #define   UTMIP_AN_C            (1 << 21)
369 #define   UTMIP_HIGHZ_C         (1 << 22)
370 #define   UTMIP_USBOP_RPD_D     (1 << 24)
371 #define   UTMIP_USBON_RPD_D     (1 << 25)
372 #define   UTMIP_AP_D            (1 << 28)
373 #define   UTMIP_AN_D            (1 << 29)
374 #define   UTMIP_HIGHZ_D         (1 << 30)
375
376 #define PMC_SLEEPWALK_UHSIC             0x210
377
378 #define UHSIC_STROBE_RPD_A              (1 << 0)
379 #define UHSIC_DATA_RPD_A                (1 << 1)
380 #define UHSIC_STROBE_RPU_A              (1 << 2)
381 #define UHSIC_DATA_RPU_A                (1 << 3)
382 #define UHSIC_STROBE_RPD_B              (1 << 8)
383 #define UHSIC_DATA_RPD_B                (1 << 9)
384 #define UHSIC_STROBE_RPU_B              (1 << 10)
385 #define UHSIC_DATA_RPU_B                (1 << 11)
386 #define UHSIC_STROBE_RPD_C              (1 << 16)
387 #define UHSIC_DATA_RPD_C                (1 << 17)
388 #define UHSIC_STROBE_RPU_C              (1 << 18)
389 #define UHSIC_DATA_RPU_C                (1 << 19)
390 #define UHSIC_STROBE_RPD_D              (1 << 24)
391 #define UHSIC_DATA_RPD_D                (1 << 25)
392 #define UHSIC_STROBE_RPU_D              (1 << 26)
393 #define UHSIC_DATA_RPU_D                (1 << 27)
394
395 #define UTMIP_UHSIC_STATUS              0x214
396
397 #define UTMIP_USBOP_VAL(inst)           (1 << ((2*(inst)) + 8))
398 #define UTMIP_USBOP_VAL_P2              (1 << 12)
399 #define UTMIP_USBOP_VAL_P1              (1 << 10)
400 #define UTMIP_USBOP_VAL_P0              (1 << 8)
401 #define UTMIP_USBON_VAL(inst)           (1 << ((2*(inst)) + 9))
402 #define UTMIP_USBON_VAL_P2              (1 << 13)
403 #define UTMIP_USBON_VAL_P1              (1 << 11)
404 #define UTMIP_USBON_VAL_P0              (1 << 9)
405 #define UHSIC_WAKE_ALARM                (1 << 19)
406 #define UTMIP_WAKE_ALARM(inst)          (1 << ((inst) + 16))
407 #define UTMIP_WAKE_ALARM_P2             (1 << 18)
408 #define UTMIP_WAKE_ALARM_P1             (1 << 17)
409 #define UTMIP_WAKE_ALARM_P0             (1 << 16)
410 #define UHSIC_DATA_VAL_P0               (1 << 15)
411 #define UHSIC_STROBE_VAL_P0             (1 << 14)
412 #define UTMIP_WALK_PTR_VAL(inst)        (0x3 << ((inst)*2))
413 #define UHSIC_WALK_PTR_VAL              (0x3 << 6)
414 #define UTMIP_WALK_PTR(inst)            (1 << ((inst)*2))
415 #define UTMIP_WALK_PTR_P2               (1 << 4)
416 #define UTMIP_WALK_PTR_P1               (1 << 2)
417 #define UTMIP_WALK_PTR_P0               (1 << 0)
418
419 #define USB1_PREFETCH_ID                           6
420 #define USB2_PREFETCH_ID                           18
421 #define USB3_PREFETCH_ID                           17
422
423 #define PMC_UTMIP_UHSIC_FAKE            0x218
424
425 #define UHSIC_STROBE_VAL                (1 << 12)
426 #define UHSIC_DATA_VAL                  (1 << 13)
427 #define UHSIC_STROBE_ENB                (1 << 14)
428 #define UHSIC_DATA_ENB                  (1 << 15)
429 #define   USBON_VAL(inst)       (1 << ((4*(inst))+1))
430 #define   USBON_VAL_P2                  (1 << 9)
431 #define   USBON_VAL_P1                  (1 << 5)
432 #define   USBON_VAL_P0                  (1 << 1)
433 #define   USBOP_VAL(inst)       (1 << (4*(inst)))
434 #define   USBOP_VAL_P2                  (1 << 8)
435 #define   USBOP_VAL_P1                  (1 << 4)
436 #define   USBOP_VAL_P0                  (1 << 0)
437
438 #define PMC_UTMIP_BIAS_MASTER_CNTRL 0x30c
439 #define   BIAS_MASTER_PROG_VAL          (1 << 1)
440
441 #define PMC_UTMIP_MASTER_CONFIG 0x310
442
443 #define UTMIP_PWR(inst)         (1 << (inst))
444 #define UHSIC_PWR                       (1 << 3)
445
446 #define FUSE_USB_CALIB_0                0x1F0
447 #define   XCVR_SETUP(x) (((x) & 0x7F) << 0)
448 #define   XCVR_SETUP_LSB_MASK   0xF
449 #define   XCVR_SETUP_MSB_MASK   0x70
450 #define   XCVR_SETUP_LSB_MAX_VAL        0xF
451
452 #define APB_MISC_GP_OBSCTRL_0   0x818
453 #define APB_MISC_GP_OBSDATA_0   0x81c
454
455 /* ULPI GPIO */
456 #define ULPI_STP        TEGRA_GPIO_PY3
457 #define ULPI_DIR        TEGRA_GPIO_PY1
458 #define ULPI_D0         TEGRA_GPIO_PO1
459 #define ULPI_D1         TEGRA_GPIO_PO2
460
461 /* These values (in milli second) are taken from the battery charging spec */
462 #define TDP_SRC_ON_MS    100
463 #define TDPSRC_CON_MS    40
464
465 #ifdef DEBUG
466 #define DBG(stuff...)   pr_info("tegra3_usb_phy: " stuff)
467 #else
468 #define DBG(stuff...)   do {} while (0)
469 #endif
470
471 #if 0
472 #define PHY_DBG(stuff...)       pr_info("tegra3_usb_phy: " stuff)
473 #else
474 #define PHY_DBG(stuff...)       do {} while (0)
475 #endif
476
477
478 static u32 utmip_rctrl_val, utmip_tctrl_val;
479 static DEFINE_SPINLOCK(utmip_pad_lock);
480 static int utmip_pad_count;
481
482 static struct tegra_xtal_freq utmip_freq_table[] = {
483         {
484                 .freq = 12000000,
485                 .enable_delay = 0x02,
486                 .stable_count = 0x2F,
487                 .active_delay = 0x04,
488                 .xtal_freq_count = 0x76,
489                 .debounce = 0x7530,
490                 .pdtrk_count = 5,
491         },
492         {
493                 .freq = 13000000,
494                 .enable_delay = 0x02,
495                 .stable_count = 0x33,
496                 .active_delay = 0x05,
497                 .xtal_freq_count = 0x7F,
498                 .debounce = 0x7EF4,
499                 .pdtrk_count = 5,
500         },
501         {
502                 .freq = 19200000,
503                 .enable_delay = 0x03,
504                 .stable_count = 0x4B,
505                 .active_delay = 0x06,
506                 .xtal_freq_count = 0xBB,
507                 .debounce = 0xBB80,
508                 .pdtrk_count = 7,
509         },
510         {
511                 .freq = 26000000,
512                 .enable_delay = 0x04,
513                 .stable_count = 0x66,
514                 .active_delay = 0x09,
515                 .xtal_freq_count = 0xFE,
516                 .debounce = 0xFDE8,
517                 .pdtrk_count = 9,
518         },
519 };
520
521 static struct tegra_xtal_freq uhsic_freq_table[] = {
522         {
523                 .freq = 12000000,
524                 .enable_delay = 0x02,
525                 .stable_count = 0x2F,
526                 .active_delay = 0x0,
527                 .xtal_freq_count = 0x1CA,
528         },
529         {
530                 .freq = 13000000,
531                 .enable_delay = 0x02,
532                 .stable_count = 0x33,
533                 .active_delay = 0x0,
534                 .xtal_freq_count = 0x1F0,
535         },
536         {
537                 .freq = 19200000,
538                 .enable_delay = 0x03,
539                 .stable_count = 0x4B,
540                 .active_delay = 0x0,
541                 .xtal_freq_count = 0x2DD,
542         },
543         {
544                 .freq = 26000000,
545                 .enable_delay = 0x04,
546                 .stable_count = 0x66,
547                 .active_delay = 0x0,
548                 .xtal_freq_count = 0x3E0,
549         },
550 };
551
552 static void usb_phy_fence_read(struct tegra_usb_phy *phy)
553 {
554         /* Fence read for coherency of AHB master intiated writes */
555         if (phy->inst == 0)
556                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB1_PREFETCH_ID));
557         else if (phy->inst == 1)
558                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB2_PREFETCH_ID));
559         else if (phy->inst == 2)
560                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB3_PREFETCH_ID));
561
562         return;
563 }
564
565 static void utmip_setup_pmc_wake_detect(struct tegra_usb_phy *phy)
566 {
567         unsigned long val, pmc_pad_cfg_val;
568         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
569         unsigned  int inst = phy->inst;
570         void __iomem *base = phy->regs;
571         bool port_connected;
572         enum usb_phy_port_speed port_speed;
573
574         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
575
576         /* check for port connect status */
577         val = readl(base + USB_PORTSC);
578         port_connected = val & USB_PORTSC_CCS;
579
580         if (!port_connected)
581                 return;
582
583         port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
584                 HOSTPC1_DEVLC_PSPD_MASK;
585         /*Set PMC MASTER bits to do the following
586         * a. Take over the UTMI drivers
587         * b. set up such that it will take over resume
588         *        if remote wakeup is detected
589         * Prepare PMC to take over suspend-wake detect-drive resume until USB
590         * controller ready
591         */
592
593         /* disable master enable in PMC */
594         val = readl(pmc_base + PMC_SLEEP_CFG);
595         val &= ~UTMIP_MASTER_ENABLE(inst);
596         writel(val, pmc_base + PMC_SLEEP_CFG);
597
598         /* UTMIP_PWR_PX=1 for power savings mode */
599         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
600         val |= UTMIP_PWR(inst);
601         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
602
603         /* config debouncer */
604         val = readl(pmc_base + PMC_USB_DEBOUNCE);
605         val &= ~UTMIP_LINE_DEB_CNT(~0);
606         val |= UTMIP_LINE_DEB_CNT(4);
607         writel(val, pmc_base + PMC_USB_DEBOUNCE);
608
609         /* Make sure nothing is happening on the line with respect to PMC */
610         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
611         val &= ~USBOP_VAL(inst);
612         val &= ~USBON_VAL(inst);
613         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
614
615         /* Make sure wake value for line is none */
616         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
617         val &= ~UTMIP_LINEVAL_WALK_EN(inst);
618         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
619         val = readl(pmc_base + PMC_SLEEP_CFG);
620         val &= ~UTMIP_WAKE_VAL(inst, ~0);
621         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
622         writel(val, pmc_base + PMC_SLEEP_CFG);
623
624         /* turn off pad detectors */
625         val = readl(pmc_base + PMC_USB_AO);
626         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
627         writel(val, pmc_base + PMC_USB_AO);
628
629         /* Remove fake values and make synchronizers work a bit */
630         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
631         val &= ~USBOP_VAL(inst);
632         val &= ~USBON_VAL(inst);
633         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
634
635         /* Enable which type of event can trigger a walk,
636         in this case usb_line_wake */
637         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
638         val |= UTMIP_LINEVAL_WALK_EN(inst);
639         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
640
641         /* Enable which type of event can trigger a walk,
642         * in this case usb_line_wake */
643         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
644         val |= UTMIP_LINEVAL_WALK_EN(inst);
645         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
646
647         /* Clear the walk pointers and wake alarm */
648         val = readl(pmc_base + PMC_TRIGGERS);
649         val |= UTMIP_CLR_WAKE_ALARM(inst) | UTMIP_CLR_WALK_PTR(inst);
650         writel(val, pmc_base + PMC_TRIGGERS);
651
652
653         /* Capture FS/LS pad configurations */
654         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
655         val = readl(pmc_base + PMC_TRIGGERS);
656         val |= UTMIP_CAP_CFG(inst);
657         writel(val, pmc_base + PMC_TRIGGERS);
658         udelay(1);
659         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
660
661         /* BIAS MASTER_ENABLE=0 */
662         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
663         val &= ~BIAS_MASTER_PROG_VAL;
664         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
665
666         /* program walk sequence, maintain a J, followed by a driven K
667         * to signal a resume once an wake event is detected */
668         val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
669         val &= ~UTMIP_AP_A;
670         val |= UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_AN_A |UTMIP_HIGHZ_A |
671                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_AP_B | UTMIP_AN_B |
672                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_AP_C | UTMIP_AN_C |
673                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_AP_D | UTMIP_AN_D;
674         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
675
676         if (port_speed == USB_PHY_PORT_SPEED_LOW) {
677                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
678                 val &= ~(UTMIP_AN_B | UTMIP_HIGHZ_B | UTMIP_AN_C |
679                         UTMIP_HIGHZ_C | UTMIP_AN_D | UTMIP_HIGHZ_D);
680                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
681         } else {
682                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
683                 val &= ~(UTMIP_AP_B | UTMIP_HIGHZ_B | UTMIP_AP_C |
684                         UTMIP_HIGHZ_C | UTMIP_AP_D | UTMIP_HIGHZ_D);
685                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
686         }
687
688         /* turn on pad detectors */
689         val = readl(pmc_base + PMC_USB_AO);
690         val &= ~(USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
691         writel(val, pmc_base + PMC_USB_AO);
692
693         /* Add small delay before usb detectors provide stable line values */
694         mdelay(1);
695
696         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
697         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
698         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
699         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
700
701         phy->remote_wakeup = false;
702
703         /* Turn over pad configuration to PMC  for line wake events*/
704         val = readl(pmc_base + PMC_SLEEP_CFG);
705         val &= ~UTMIP_WAKE_VAL(inst, ~0);
706         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_ANY);
707         val |= UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst);
708         val |= UTMIP_MASTER_ENABLE(inst) | UTMIP_FSLS_USE_PMC(inst);
709         writel(val, pmc_base + PMC_SLEEP_CFG);
710
711         val = readl(base + UTMIP_PMC_WAKEUP0);
712         val |= EVENT_INT_ENB;
713         writel(val, base + UTMIP_PMC_WAKEUP0);
714         PHY_DBG("%s ENABLE_PMC inst = %d\n", __func__, inst);
715 }
716
717 static void utmip_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy)
718 {
719         unsigned long val;
720         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
721         unsigned  int inst = phy->inst;
722         void __iomem *base = phy->regs;
723
724         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
725
726         val = readl(pmc_base + PMC_SLEEP_CFG);
727         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
728         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
729         writel(val, pmc_base + PMC_SLEEP_CFG);
730
731         val = readl(pmc_base + PMC_TRIGGERS);
732         val |= UTMIP_CLR_WAKE_ALARM(inst) | UTMIP_CLR_WALK_PTR(inst);
733         writel(val, pmc_base + PMC_TRIGGERS);
734
735         val = readl(base + UTMIP_PMC_WAKEUP0);
736         val &= ~EVENT_INT_ENB;
737         writel(val, base + UTMIP_PMC_WAKEUP0);
738
739         /* Disable PMC master mode by clearing MASTER_EN */
740         val = readl(pmc_base + PMC_SLEEP_CFG);
741         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
742                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
743         writel(val, pmc_base + PMC_SLEEP_CFG);
744
745         val = readl(pmc_base + PMC_TRIGGERS);
746         val &= ~UTMIP_CAP_CFG(inst);
747         writel(val, pmc_base + PMC_TRIGGERS);
748
749         /* turn off pad detectors */
750         val = readl(pmc_base + PMC_USB_AO);
751         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
752         writel(val, pmc_base + PMC_USB_AO);
753
754         phy->remote_wakeup = false;
755         PHY_DBG("%s DISABLE_PMC inst = %d\n", __func__, inst);
756 }
757
758 static bool utmi_phy_remotewake_detected(struct tegra_usb_phy *phy)
759 {
760         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
761         void __iomem *base = phy->regs;
762         unsigned  int inst = phy->inst;
763         u32 val;
764
765         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
766         val = readl(base + UTMIP_PMC_WAKEUP0);
767         if (val & EVENT_INT_ENB) {
768                 val = readl(pmc_base + UTMIP_UHSIC_STATUS);
769                 if (UTMIP_WAKE_ALARM(inst) & val) {
770                         val = readl(pmc_base + PMC_SLEEP_CFG);
771                         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
772                         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
773                         writel(val, pmc_base + PMC_SLEEP_CFG);
774
775                         val = readl(pmc_base + PMC_TRIGGERS);
776                         val |= UTMIP_CLR_WAKE_ALARM(inst) |
777                                 UTMIP_CLR_WALK_PTR(inst);
778                         writel(val, pmc_base + PMC_TRIGGERS);
779
780                         val = readl(base + UTMIP_PMC_WAKEUP0);
781                         val &= ~EVENT_INT_ENB;
782                         writel(val, base + UTMIP_PMC_WAKEUP0);
783                         phy->remote_wakeup = true;
784                         return true;
785                 }
786         }
787         return false;
788 }
789
790 static void utmi_phy_enable_trking_data(struct tegra_usb_phy *phy)
791 {
792         void __iomem *base = IO_ADDRESS(TEGRA_USB_BASE);
793         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
794         static bool init_done = false;
795         u32 val;
796
797         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
798
799         /* Should be done only once after system boot */
800         if (init_done)
801                 return;
802
803         clk_enable(phy->utmi_pad_clk);
804         /* Bias pad MASTER_ENABLE=1 */
805         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
806         val |= BIAS_MASTER_PROG_VAL;
807         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
808
809         /* Setting the tracking length time */
810         val = readl(base + UTMIP_BIAS_CFG1);
811         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
812         val |= UTMIP_BIAS_PDTRK_COUNT(5);
813         writel(val, base + UTMIP_BIAS_CFG1);
814
815         /* Bias PDTRK is Shared and MUST be done from USB1 ONLY, PD_TRK=0 */
816         val = readl(base + UTMIP_BIAS_CFG1);
817         val &= ~UTMIP_BIAS_PDTRK_POWERDOWN;
818         writel(val, base + UTMIP_BIAS_CFG1);
819
820         val = readl(base + UTMIP_BIAS_CFG1);
821         val |= UTMIP_BIAS_PDTRK_POWERUP;
822         writel(val, base + UTMIP_BIAS_CFG1);
823
824         /* Wait for 25usec */
825         udelay(25);
826
827         /* Bias pad MASTER_ENABLE=0 */
828         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
829         val &= ~BIAS_MASTER_PROG_VAL;
830         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
831
832         /* Wait for 1usec */
833         udelay(1);
834
835         /* Bias pad MASTER_ENABLE=1 */
836         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
837         val |= BIAS_MASTER_PROG_VAL;
838         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
839
840         /* Read RCTRL and TCTRL from UTMIP space */
841         val = readl(base + UTMIP_BIAS_STS0);
842         utmip_rctrl_val = ffz(UTMIP_RCTRL_VAL(val));
843         utmip_tctrl_val = ffz(UTMIP_TCTRL_VAL(val));
844
845         /* PD_TRK=1 */
846         val = readl(base + UTMIP_BIAS_CFG1);
847         val |= UTMIP_BIAS_PDTRK_POWERDOWN;
848         writel(val, base + UTMIP_BIAS_CFG1);
849
850         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
851         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
852         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
853         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
854         clk_disable(phy->utmi_pad_clk);
855         init_done = true;
856 }
857
858 static void utmip_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy)
859 {
860         unsigned long val;
861         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
862         unsigned  int inst = phy->inst;
863
864         /* power down UTMIP interfaces */
865         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
866         val |= UTMIP_PWR(inst);
867         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
868
869         /* setup sleep walk usb controller */
870         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
871                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
872                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
873                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
874         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
875
876         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
877         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
878         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
879         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
880
881         /* Turn over pad configuration to PMC */
882         val = readl(pmc_base + PMC_SLEEP_CFG);
883         val &= ~UTMIP_WAKE_VAL(inst, ~0);
884         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE) |
885                 UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
886                 UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst);
887         writel(val, pmc_base + PMC_SLEEP_CFG);
888         PHY_DBG("%s ENABLE_PMC inst = %d\n", __func__, inst);
889 }
890
891 static void utmip_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
892 {
893         unsigned long val;
894         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
895         unsigned  int inst = phy->inst;
896
897         /* Disable PMC master mode by clearing MASTER_EN */
898         val = readl(pmc_base + PMC_SLEEP_CFG);
899         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
900                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
901         writel(val, pmc_base + PMC_SLEEP_CFG);
902         mdelay(1);
903         PHY_DBG("%s DISABLE_PMC inst = %d\n", __func__, inst);
904 }
905
906
907 #ifdef KERNEL_WARNING
908 static void usb_phy_power_down_pmc(void)
909 {
910         unsigned long val;
911         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
912
913         /* power down all 3 UTMIP interfaces */
914         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
915         val |= UTMIP_PWR(0) | UTMIP_PWR(1) | UTMIP_PWR(2);
916         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
917
918         /* turn on pad detectors */
919         writel(PMC_POWER_DOWN_MASK, pmc_base + PMC_USB_AO);
920
921         /* setup sleep walk fl all 3 usb controllers */
922         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
923                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
924                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
925                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
926         writel(val, pmc_base + PMC_SLEEPWALK_REG(0));
927         writel(val, pmc_base + PMC_SLEEPWALK_REG(1));
928         writel(val, pmc_base + PMC_SLEEPWALK_REG(2));
929
930         /* enable pull downs on HSIC PMC */
931         val = UHSIC_STROBE_RPD_A | UHSIC_DATA_RPD_A | UHSIC_STROBE_RPD_B |
932                 UHSIC_DATA_RPD_B | UHSIC_STROBE_RPD_C | UHSIC_DATA_RPD_C |
933                 UHSIC_STROBE_RPD_D | UHSIC_DATA_RPD_D;
934         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
935
936         /* Turn over pad configuration to PMC */
937         val = readl(pmc_base + PMC_SLEEP_CFG);
938         val &= ~UTMIP_WAKE_VAL(0, ~0);
939         val &= ~UTMIP_WAKE_VAL(1, ~0);
940         val &= ~UTMIP_WAKE_VAL(2, ~0);
941         val &= ~UHSIC_WAKE_VAL_P0(~0);
942         val |= UTMIP_WAKE_VAL(0, WAKE_VAL_NONE) | UHSIC_WAKE_VAL_P0(WAKE_VAL_NONE) |
943         UTMIP_WAKE_VAL(1, WAKE_VAL_NONE) | UTMIP_WAKE_VAL(2, WAKE_VAL_NONE) |
944         UTMIP_RCTRL_USE_PMC(0) | UTMIP_RCTRL_USE_PMC(1) | UTMIP_RCTRL_USE_PMC(2) |
945         UTMIP_TCTRL_USE_PMC(0) | UTMIP_TCTRL_USE_PMC(1) | UTMIP_TCTRL_USE_PMC(2) |
946         UTMIP_FSLS_USE_PMC(0) | UTMIP_FSLS_USE_PMC(1) | UTMIP_FSLS_USE_PMC(2) |
947         UTMIP_MASTER_ENABLE(0) | UTMIP_MASTER_ENABLE(1) | UTMIP_MASTER_ENABLE(2) |
948         UHSIC_MASTER_ENABLE_P0;
949         writel(val, pmc_base + PMC_SLEEP_CFG);
950 }
951 #endif
952
953 static int usb_phy_bringup_host_controller(struct tegra_usb_phy *phy)
954 {
955         unsigned long val;
956         void __iomem *base = phy->regs;
957
958         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
959         PHY_DBG("[%d] USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n", __LINE__,
960                 readl(base + USB_USBSTS), readl(base + USB_PORTSC),
961                                                         phy->port_speed);
962
963         /* Device is plugged in when system is in LP0 */
964         /* Bring up the controller from LP0*/
965         val = readl(base + USB_USBCMD);
966         val |= USB_CMD_RESET;
967         writel(val, base + USB_USBCMD);
968
969         if (usb_phy_reg_status_wait(base + USB_USBCMD,
970                 USB_CMD_RESET, 0, 2500) < 0) {
971                 pr_err("%s: timeout waiting for reset\n", __func__);
972         }
973
974         val = readl(base + USB_USBMODE);
975         val &= ~USB_USBMODE_MASK;
976         val |= USB_USBMODE_HOST;
977         writel(val, base + USB_USBMODE);
978         val = readl(base + HOSTPC1_DEVLC);
979         val &= ~HOSTPC1_DEVLC_PTS(~0);
980
981         if (phy->pdata->phy_intf == TEGRA_USB_PHY_INTF_HSIC)
982                 val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
983         else
984                 val |= HOSTPC1_DEVLC_STS;
985         writel(val, base + HOSTPC1_DEVLC);
986
987         /* Enable Port Power */
988         val = readl(base + USB_PORTSC);
989         val |= USB_PORTSC_PP;
990         writel(val, base + USB_PORTSC);
991         udelay(10);
992
993         /* Check if the phy resume from LP0. When the phy resume from LP0
994          * USB register will be reset.to zero */
995         if (!readl(base + USB_ASYNCLISTADDR)) {
996                 /* Program the field PTC based on the saved speed mode */
997                 val = readl(base + USB_PORTSC);
998                 val &= ~USB_PORTSC_PTC(~0);
999                 if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH)
1000                         val |= USB_PORTSC_PTC(5);
1001                 else if (phy->port_speed == USB_PHY_PORT_SPEED_FULL)
1002                         val |= USB_PORTSC_PTC(6);
1003                 else if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
1004                         val |= USB_PORTSC_PTC(7);
1005                 writel(val, base + USB_PORTSC);
1006                 udelay(10);
1007
1008                 /* Disable test mode by setting PTC field to NORMAL_OP */
1009                 val = readl(base + USB_PORTSC);
1010                 val &= ~USB_PORTSC_PTC(~0);
1011                 writel(val, base + USB_PORTSC);
1012                 udelay(10);
1013         }
1014
1015         /* Poll until CCS is enabled */
1016         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
1017                                                  USB_PORTSC_CCS, 2000)) {
1018                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
1019         }
1020
1021         /* Poll until PE is enabled */
1022         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_PE,
1023                                                  USB_PORTSC_PE, 2000)) {
1024                 pr_err("%s: timeout waiting for USB_PORTSC_PE\n", __func__);
1025         }
1026
1027         /* Clear the PCI status, to avoid an interrupt taken upon resume */
1028         val = readl(base + USB_USBSTS);
1029         val |= USB_USBSTS_PCI;
1030         writel(val, base + USB_USBSTS);
1031
1032         if (!phy->remote_wakeup) {
1033                 /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
1034                 val = readl(base + USB_PORTSC);
1035                 if ((val & USB_PORTSC_PP) && (val & USB_PORTSC_PE)) {
1036                         val |= USB_PORTSC_SUSP;
1037                         writel(val, base + USB_PORTSC);
1038                         /* Need a 4ms delay before the controller goes to suspend */
1039                         mdelay(4);
1040
1041                         /* Wait until port suspend completes */
1042                         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_SUSP,
1043                                                          USB_PORTSC_SUSP, 1000)) {
1044                                 pr_err("%s: timeout waiting for PORT_SUSPEND\n",
1045                                                                         __func__);
1046                         }
1047                 }
1048         }
1049         PHY_DBG("[%d] USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n", __LINE__,
1050                 readl(base + USB_USBSTS), readl(base + USB_PORTSC),
1051                                                         phy->port_speed);
1052
1053         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1054                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1055         return 0;
1056 }
1057
1058 static void usb_phy_wait_for_sof(struct tegra_usb_phy *phy)
1059 {
1060         unsigned long val;
1061         void __iomem *base = phy->regs;
1062
1063         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1064
1065         val = readl(base + USB_USBSTS);
1066         writel(val, base + USB_USBSTS);
1067         udelay(20);
1068         /* wait for two SOFs */
1069         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1070                 USB_USBSTS_SRI, 2500))
1071                 pr_err("%s: timeout waiting for SOF\n", __func__);
1072
1073         val = readl(base + USB_USBSTS);
1074         writel(val, base + USB_USBSTS);
1075         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI, 0, 2500))
1076                 pr_err("%s: timeout waiting for SOF\n", __func__);
1077
1078         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1079                         USB_USBSTS_SRI, 2500))
1080                 pr_err("%s: timeout waiting for SOF\n", __func__);
1081
1082         udelay(20);
1083 }
1084
1085 static unsigned int utmi_phy_xcvr_setup_value(struct tegra_usb_phy *phy)
1086 {
1087         struct tegra_utmi_config *cfg = &phy->pdata->u_cfg.utmi;
1088         signed long val;
1089
1090         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1091
1092         if (cfg->xcvr_use_fuses) {
1093                 val = XCVR_SETUP(tegra_fuse_readl(FUSE_USB_CALIB_0));
1094                 if (cfg->xcvr_use_lsb) {
1095                         val = min((unsigned int) ((val & XCVR_SETUP_LSB_MASK)
1096                                 + cfg->xcvr_setup_offset),
1097                                 (unsigned int) XCVR_SETUP_LSB_MAX_VAL);
1098                         val |= (cfg->xcvr_setup & XCVR_SETUP_MSB_MASK);
1099                 } else {
1100                         if (cfg->xcvr_setup_offset <= UTMIP_XCVR_MAX_OFFSET)
1101                                 val = val + cfg->xcvr_setup_offset;
1102
1103                         if (val > UTMIP_XCVR_SETUP_MAX_VALUE) {
1104                                 val = UTMIP_XCVR_SETUP_MAX_VALUE;
1105                                 pr_info("%s: reset XCVR_SETUP to max value\n",
1106                                                 __func__);
1107                         } else if (val < UTMIP_XCVR_SETUP_MIN_VALUE) {
1108                                 val = UTMIP_XCVR_SETUP_MIN_VALUE;
1109                                 pr_info("%s: reset XCVR_SETUP to min value\n",
1110                                                 __func__);
1111                         }
1112                 }
1113         } else {
1114                 val = cfg->xcvr_setup;
1115         }
1116
1117         return (unsigned int) val;
1118 }
1119
1120 static int utmi_phy_open(struct tegra_usb_phy *phy)
1121 {
1122         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1123         unsigned long parent_rate, val;
1124         int i;
1125
1126         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1127
1128         phy->utmi_pad_clk = clk_get_sys("utmip-pad", NULL);
1129         if (IS_ERR(phy->utmi_pad_clk)) {
1130                 pr_err("%s: can't get utmip pad clock\n", __func__);
1131                 return PTR_ERR(phy->utmi_pad_clk);
1132         }
1133
1134         phy->utmi_xcvr_setup = utmi_phy_xcvr_setup_value(phy);
1135
1136         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
1137         for (i = 0; i < ARRAY_SIZE(utmip_freq_table); i++) {
1138                 if (utmip_freq_table[i].freq == parent_rate) {
1139                         phy->freq = &utmip_freq_table[i];
1140                         break;
1141                 }
1142         }
1143         if (!phy->freq) {
1144                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
1145                 return -EINVAL;
1146         }
1147
1148         /* Power-up the VBUS detector for UTMIP PHY */
1149         val = readl(pmc_base + PMC_USB_AO);
1150         val &= ~(PMC_USB_AO_VBUS_WAKEUP_PD_P0 | PMC_USB_AO_ID_PD_P0);
1151         writel((val | PMC_USB_AO_PD_P2), (pmc_base + PMC_USB_AO));
1152
1153         utmip_powerup_pmc_wake_detect(phy);
1154
1155         return 0;
1156 }
1157
1158 static void utmi_phy_close(struct tegra_usb_phy *phy)
1159 {
1160         unsigned long val;
1161         void __iomem *base = phy->regs;
1162
1163         DBG("%s inst:[%d]\n", __func__, phy->inst);
1164
1165         /* Disable PHY clock valid interrupts while going into suspend*/
1166         if (phy->pdata->u_data.host.hot_plug) {
1167                 val = readl(base + USB_SUSP_CTRL);
1168                 val &= ~USB_PHY_CLK_VALID_INT_ENB;
1169                 writel(val, base + USB_SUSP_CTRL);
1170         }
1171
1172         clk_put(phy->utmi_pad_clk);
1173 }
1174
1175 static int utmi_phy_pad_power_on(struct tegra_usb_phy *phy)
1176 {
1177         unsigned long val, flags;
1178         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1179
1180         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1181
1182         clk_enable(phy->utmi_pad_clk);
1183
1184         spin_lock_irqsave(&utmip_pad_lock, flags);
1185         utmip_pad_count++;
1186
1187         val = readl(pad_base + UTMIP_BIAS_CFG0);
1188         val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
1189         val |= UTMIP_HSSQUELCH_LEVEL(0x2) | UTMIP_HSDISCON_LEVEL(0x1) |
1190                 UTMIP_HSDISCON_LEVEL_MSB;
1191         writel(val, pad_base + UTMIP_BIAS_CFG0);
1192
1193         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1194
1195         clk_disable(phy->utmi_pad_clk);
1196
1197         return 0;
1198 }
1199
1200 static int utmi_phy_pad_power_off(struct tegra_usb_phy *phy)
1201 {
1202         unsigned long val, flags;
1203         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1204
1205         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1206
1207         clk_enable(phy->utmi_pad_clk);
1208         spin_lock_irqsave(&utmip_pad_lock, flags);
1209
1210         if (!utmip_pad_count) {
1211                 pr_err("%s: utmip pad already powered off\n", __func__);
1212                 goto out;
1213         }
1214         if (--utmip_pad_count == 0) {
1215                 val = readl(pad_base + UTMIP_BIAS_CFG0);
1216                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
1217                 val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) | UTMIP_HSDISCON_LEVEL(~0) |
1218                         UTMIP_HSDISCON_LEVEL_MSB);
1219                 writel(val, pad_base + UTMIP_BIAS_CFG0);
1220         }
1221 out:
1222         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1223         clk_disable(phy->utmi_pad_clk);
1224
1225         return 0;
1226 }
1227
1228 static int utmi_phy_irq(struct tegra_usb_phy *phy)
1229 {
1230         void __iomem *base = phy->regs;
1231         unsigned long val = 0;
1232
1233         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1234         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1235                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1236         DBG("USB_USBMODE[0x%x] USB_USBCMD[0x%x]\n",
1237                         readl(base + USB_USBMODE), readl(base + USB_USBCMD));
1238
1239         usb_phy_fence_read(phy);
1240         /* check if there is any remote wake event */
1241         if (utmi_phy_remotewake_detected(phy))
1242                 pr_info("%s: utmip remote wake detected\n", __func__);
1243
1244         if (phy->pdata->u_data.host.hot_plug) {
1245                 val = readl(base + USB_SUSP_CTRL);
1246                 if ((val  & USB_PHY_CLK_VALID_INT_STS)) {
1247                         val &= ~USB_PHY_CLK_VALID_INT_ENB |
1248                                         USB_PHY_CLK_VALID_INT_STS;
1249                         writel(val , (base + USB_SUSP_CTRL));
1250                         pr_info("%s: usb device plugged-in\n", __func__);
1251                         val = readl(base + USB_USBSTS);
1252                         if (!(val  & USB_USBSTS_PCI))
1253                                 return IRQ_NONE;
1254                         val = readl(base + USB_PORTSC);
1255                         val &= ~(USB_PORTSC_WKCN | USB_PORTSC_RWC_BITS);
1256                         writel(val , (base + USB_PORTSC));
1257                 }
1258         }
1259
1260         return IRQ_HANDLED;
1261 }
1262
1263 static void utmi_phy_enable_obs_bus(struct tegra_usb_phy *phy)
1264 {
1265         unsigned long val;
1266         void __iomem *base = phy->regs;
1267
1268         /* (2LS WAR)is not required for LS and FS devices and is only for HS */
1269         if ((phy->port_speed == USB_PHY_PORT_SPEED_LOW) ||
1270                 (phy->port_speed == USB_PHY_PORT_SPEED_FULL)) {
1271                 /* do not enable the OBS bus */
1272                 val = readl(base + UTMIP_MISC_CFG0);
1273                 val &= ~(UTMIP_DPDM_OBSERVE_SEL(~0));
1274                 writel(val, base + UTMIP_MISC_CFG0);
1275                 DBG("%s(%d) Disable OBS bus\n", __func__, __LINE__);
1276                 return;
1277         }
1278         /* Force DP/DM pulldown active for Host mode */
1279         val = readl(base + UTMIP_MISC_CFG0);
1280         val |= FORCE_PULLDN_DM | FORCE_PULLDN_DP |
1281                         COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS;
1282         writel(val, base + UTMIP_MISC_CFG0);
1283         val = readl(base + UTMIP_MISC_CFG0);
1284         val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1285         if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
1286                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
1287         else
1288                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
1289         writel(val, base + UTMIP_MISC_CFG0);
1290         udelay(1);
1291
1292         val = readl(base + UTMIP_MISC_CFG0);
1293         val |= UTMIP_DPDM_OBSERVE;
1294         writel(val, base + UTMIP_MISC_CFG0);
1295         udelay(10);
1296         DBG("%s(%d) Enable OBS bus\n", __func__, __LINE__);
1297         PHY_DBG("ENABLE_OBS_BUS\n");
1298 }
1299
1300 static int utmi_phy_disable_obs_bus(struct tegra_usb_phy *phy)
1301 {
1302         unsigned long val;
1303         void __iomem *base = phy->regs;
1304         unsigned long flags;
1305
1306         /* check if OBS bus is already enabled */
1307         val = readl(base + UTMIP_MISC_CFG0);
1308         if (val & UTMIP_DPDM_OBSERVE) {
1309                 PHY_DBG("DISABLE_OBS_BUS\n");
1310
1311                 /* disable ALL interrupts on current CPU */
1312                 local_irq_save(flags);
1313
1314                 /* Change the UTMIP OBS bus to drive SE0 */
1315                 val = readl(base + UTMIP_MISC_CFG0);
1316                 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1317                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_SE0;
1318                 writel(val, base + UTMIP_MISC_CFG0);
1319
1320                 /* Wait for 3us(2 LS bit times) */
1321                 udelay(3);
1322
1323                 /* Release UTMIP OBS bus */
1324                 val = readl(base + UTMIP_MISC_CFG0);
1325                 val &= ~UTMIP_DPDM_OBSERVE;
1326                 writel(val, base + UTMIP_MISC_CFG0);
1327
1328                 /* Release DP/DM pulldown for Host mode */
1329                 val = readl(base + UTMIP_MISC_CFG0);
1330                 val &= ~(FORCE_PULLDN_DM | FORCE_PULLDN_DP |
1331                                 COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS);
1332                 writel(val, base + UTMIP_MISC_CFG0);
1333
1334                 val = readl(base + USB_USBCMD);
1335                 val |= USB_USBCMD_RS;
1336                 writel(val, base + USB_USBCMD);
1337
1338                 /* restore ALL interrupts on current CPU */
1339                 local_irq_restore(flags);
1340
1341                 if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
1342                                                          USB_USBCMD_RS, 2000)) {
1343                         pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
1344                         return -ETIMEDOUT;
1345                 }
1346         }
1347         return 0;
1348 }
1349
1350 static int utmi_phy_post_resume(struct tegra_usb_phy *phy)
1351 {
1352         unsigned long val;
1353         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1354         unsigned  int inst = phy->inst;
1355
1356         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1357         val = readl(pmc_base + PMC_SLEEP_CFG);
1358         /* if PMC is not disabled by now then disable it */
1359         if (val & UTMIP_MASTER_ENABLE(inst)) {
1360                 utmip_phy_disable_pmc_bus_ctrl(phy);
1361         }
1362
1363         utmi_phy_disable_obs_bus(phy);
1364
1365         return 0;
1366 }
1367
1368 static int phy_post_suspend(struct tegra_usb_phy *phy)
1369 {
1370
1371         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1372         /* Need a 4ms delay for controller to suspend */
1373         mdelay(4);
1374
1375         return 0;
1376
1377 }
1378
1379 static int utmi_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1380 {
1381         unsigned long val;
1382         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1383         void __iomem *base = phy->regs;
1384         unsigned  int inst = phy->inst;
1385
1386         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1387         phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
1388                         HOSTPC1_DEVLC_PSPD_MASK;
1389
1390         if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH) {
1391                 /* Disable interrupts */
1392                 writel(0, base + USB_USBINTR);
1393                 /* Clear the run bit to stop SOFs - 2LS WAR */
1394                 val = readl(base + USB_USBCMD);
1395                 val &= ~USB_USBCMD_RS;
1396                 writel(val, base + USB_USBCMD);
1397                 if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
1398                                                          USB_USBSTS_HCH, 2000)) {
1399                         pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
1400                 }
1401         }
1402
1403         val = readl(pmc_base + PMC_SLEEP_CFG);
1404         if (val & UTMIP_MASTER_ENABLE(inst)) {
1405                 if (!remote_wakeup)
1406                         utmip_phy_disable_pmc_bus_ctrl(phy);
1407         } else {
1408                 utmi_phy_enable_obs_bus(phy);
1409         }
1410
1411         return 0;
1412 }
1413
1414 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
1415 {
1416         unsigned long val;
1417         void __iomem *base = phy->regs;
1418
1419         PHY_DBG("%s(%d) inst:[%d] BEGIN\n", __func__, __LINE__, phy->inst);
1420         if (!phy->phy_clk_on) {
1421                 PHY_DBG("%s(%d) inst:[%d] phy clk is already off\n",
1422                                         __func__, __LINE__, phy->inst);
1423                 return 0;
1424         }
1425
1426         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1427                 utmip_powerdown_pmc_wake_detect(phy);
1428
1429                 val = readl(base + USB_SUSP_CTRL);
1430                 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
1431                 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
1432                 writel(val, base + USB_SUSP_CTRL);
1433
1434                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1435                 val |= UTMIP_PD_CHRG;
1436                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1437         } else {
1438                 phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
1439                                 HOSTPC1_DEVLC_PSPD_MASK;
1440
1441                 /* Disable interrupts */
1442                 writel(0, base + USB_USBINTR);
1443
1444                 /* Clear the run bit to stop SOFs - 2LS WAR */
1445                 val = readl(base + USB_USBCMD);
1446                 val &= ~USB_USBCMD_RS;
1447                 writel(val, base + USB_USBCMD);
1448
1449                 if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
1450                                                          USB_USBSTS_HCH, 2000)) {
1451                         pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
1452                 }
1453                 utmip_setup_pmc_wake_detect(phy);
1454         }
1455
1456         if (!phy->pdata->u_data.host.hot_plug) {
1457                 val = readl(base + UTMIP_XCVR_CFG0);
1458                 val |= (UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
1459                          UTMIP_FORCE_PDZI_POWERDOWN);
1460                 writel(val, base + UTMIP_XCVR_CFG0);
1461         }
1462
1463         val = readl(base + UTMIP_XCVR_CFG1);
1464         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1465                    UTMIP_FORCE_PDDR_POWERDOWN;
1466         writel(val, base + UTMIP_XCVR_CFG1);
1467
1468         val = readl(base + UTMIP_BIAS_CFG1);
1469         val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
1470         writel(val, base + UTMIP_BIAS_CFG1);
1471
1472         utmi_phy_pad_power_off(phy);
1473
1474         if (phy->pdata->u_data.host.hot_plug) {
1475                 bool enable_hotplug = true;
1476                 /* if it is OTG port then make sure to enable hot-plug feature
1477                    only if host adaptor is connected, i.e id is low */
1478                 if (phy->pdata->port_otg) {
1479                         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1480                         enable_hotplug = (val & USB_ID_STATUS) ? false : true;
1481                 }
1482                 if (enable_hotplug) {
1483                         val = readl(base + USB_PORTSC);
1484                         val |= USB_PORTSC_WKCN;
1485                         writel(val, base + USB_PORTSC);
1486
1487                         val = readl(base + USB_SUSP_CTRL);
1488                         val |= USB_PHY_CLK_VALID_INT_ENB;
1489                         writel(val, base + USB_SUSP_CTRL);
1490                 } else {
1491                         /* Disable PHY clock valid interrupts while going into suspend*/
1492                         val = readl(base + USB_SUSP_CTRL);
1493                         val &= ~USB_PHY_CLK_VALID_INT_ENB;
1494                         writel(val, base + USB_SUSP_CTRL);
1495                 }
1496         }
1497
1498         val = readl(base + HOSTPC1_DEVLC);
1499         val |= HOSTPC1_DEVLC_PHCD;
1500         writel(val, base + HOSTPC1_DEVLC);
1501
1502         if (!phy->pdata->u_data.host.hot_plug) {
1503                 val = readl(base + USB_SUSP_CTRL);
1504                 val |= UTMIP_RESET;
1505                 writel(val, base + USB_SUSP_CTRL);
1506         }
1507
1508         phy->phy_clk_on = false;
1509         phy->hw_accessible = false;
1510
1511         PHY_DBG("%s(%d) inst:[%d] END\n", __func__, __LINE__, phy->inst);
1512
1513         return 0;
1514 }
1515
1516
1517 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
1518 {
1519         unsigned long val;
1520         void __iomem *base = phy->regs;
1521         struct tegra_utmi_config *config = &phy->pdata->u_cfg.utmi;
1522
1523         PHY_DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1524         if (phy->phy_clk_on) {
1525                 PHY_DBG("%s(%d) inst:[%d] phy clk is already On\n",
1526                                         __func__, __LINE__, phy->inst);
1527                 return 0;
1528         }
1529         val = readl(base + USB_SUSP_CTRL);
1530         val |= UTMIP_RESET;
1531         writel(val, base + USB_SUSP_CTRL);
1532
1533         val = readl(base + UTMIP_TX_CFG0);
1534         val |= UTMIP_FS_PREABMLE_J;
1535         writel(val, base + UTMIP_TX_CFG0);
1536
1537         val = readl(base + UTMIP_HSRX_CFG0);
1538         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
1539         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
1540         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
1541         writel(val, base + UTMIP_HSRX_CFG0);
1542
1543         val = readl(base + UTMIP_HSRX_CFG1);
1544         val &= ~UTMIP_HS_SYNC_START_DLY(~0);
1545         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
1546         writel(val, base + UTMIP_HSRX_CFG1);
1547
1548         val = readl(base + UTMIP_DEBOUNCE_CFG0);
1549         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
1550         val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
1551         writel(val, base + UTMIP_DEBOUNCE_CFG0);
1552
1553         val = readl(base + UTMIP_MISC_CFG0);
1554         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
1555         writel(val, base + UTMIP_MISC_CFG0);
1556
1557         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1558                 val = readl(base + USB_SUSP_CTRL);
1559                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
1560                 writel(val, base + USB_SUSP_CTRL);
1561
1562                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1563                 val &= ~UTMIP_PD_CHRG;
1564                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1565         } else {
1566                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1567                 val |= UTMIP_PD_CHRG;
1568                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1569         }
1570
1571         utmi_phy_pad_power_on(phy);
1572
1573         val = readl(base + UTMIP_XCVR_CFG0);
1574         val &= ~(UTMIP_XCVR_LSBIAS_SEL | UTMIP_FORCE_PD_POWERDOWN |
1575                  UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN |
1576                  UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_LSFSLEW(~0) |
1577                  UTMIP_XCVR_LSRSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
1578         val |= UTMIP_XCVR_SETUP(phy->utmi_xcvr_setup);
1579         val |= UTMIP_XCVR_SETUP_MSB(XCVR_SETUP_MSB_CALIB(phy->utmi_xcvr_setup));
1580         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
1581         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
1582         if (!config->xcvr_use_lsb)
1583                 val |= UTMIP_XCVR_HSSLEW_MSB(0x8);
1584         writel(val, base + UTMIP_XCVR_CFG0);
1585
1586         val = readl(base + UTMIP_XCVR_CFG1);
1587         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1588                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
1589         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
1590         writel(val, base + UTMIP_XCVR_CFG1);
1591
1592         val = readl(base + UTMIP_BIAS_CFG1);
1593         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
1594         val |= UTMIP_BIAS_PDTRK_COUNT(phy->freq->pdtrk_count);
1595         writel(val, base + UTMIP_BIAS_CFG1);
1596
1597         val = readl(base + UTMIP_SPARE_CFG0);
1598         val &= ~FUSE_SETUP_SEL;
1599         val |= FUSE_ATERM_SEL;
1600         writel(val, base + UTMIP_SPARE_CFG0);
1601
1602         val = readl(base + USB_SUSP_CTRL);
1603         val |= UTMIP_PHY_ENABLE;
1604         writel(val, base + USB_SUSP_CTRL);
1605
1606         val = readl(base + USB_SUSP_CTRL);
1607         val &= ~UTMIP_RESET;
1608         writel(val, base + USB_SUSP_CTRL);
1609
1610         val = readl(base + HOSTPC1_DEVLC);
1611         val &= ~HOSTPC1_DEVLC_PHCD;
1612         writel(val, base + HOSTPC1_DEVLC);
1613
1614         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1615                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500))
1616                 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
1617
1618         utmi_phy_enable_trking_data(phy);
1619
1620         if (phy->inst == 2)
1621                 writel(0, base + ICUSB_CTRL);
1622
1623         val = readl(base + USB_USBMODE);
1624         val &= ~USB_USBMODE_MASK;
1625         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST)
1626                 val |= USB_USBMODE_HOST;
1627         else
1628                 val |= USB_USBMODE_DEVICE;
1629         writel(val, base + USB_USBMODE);
1630
1631         val = readl(base + HOSTPC1_DEVLC);
1632         val &= ~HOSTPC1_DEVLC_PTS(~0);
1633         val |= HOSTPC1_DEVLC_STS;
1634         writel(val, base + HOSTPC1_DEVLC);
1635
1636         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE)
1637                 utmip_powerup_pmc_wake_detect(phy);
1638         phy->phy_clk_on = true;
1639         phy->hw_accessible = true;
1640         PHY_DBG("%s(%d) End inst:[%d]\n", __func__, __LINE__, phy->inst);
1641         return 0;
1642 }
1643
1644 static void utmi_phy_restore_start(struct tegra_usb_phy *phy)
1645 {
1646         unsigned long val;
1647         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1648         int inst = phy->inst;
1649
1650         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1651         val = readl(pmc_base + UTMIP_UHSIC_STATUS);
1652         /* check whether we wake up from the remote resume */
1653         if (UTMIP_WALK_PTR_VAL(inst) & val) {
1654                 phy->remote_wakeup = true;
1655         } else {
1656                 if (!((UTMIP_USBON_VAL(phy->inst) |
1657                         UTMIP_USBOP_VAL(phy->inst)) & val)) {
1658                                 utmip_phy_disable_pmc_bus_ctrl(phy);
1659                 }
1660         }
1661         utmi_phy_enable_obs_bus(phy);
1662 }
1663
1664 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
1665 {
1666         unsigned long val;
1667         void __iomem *base = phy->regs;
1668         int wait_time_us = 25000; /* FPR should be set by this time */
1669
1670         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1671         /* check whether we wake up from the remote resume */
1672         if (phy->remote_wakeup) {
1673                 /* wait until SUSPEND and RESUME bit is cleared on remote resume */
1674                 do {
1675                         val = readl(base + USB_PORTSC);
1676                         udelay(1);
1677                         if (wait_time_us == 0) {
1678                                 PHY_DBG("%s PMC REMOTE WAKEUP FPR timeout val = 0x%x instance = %d\n", __func__, val, phy->inst);
1679                                 utmip_phy_disable_pmc_bus_ctrl(phy);
1680                                 utmi_phy_post_resume(phy);
1681                                 return;
1682                         }
1683                         wait_time_us--;
1684                 } while (val & (USB_PORTSC_RESUME | USB_PORTSC_SUSP));
1685
1686                 /* wait for 25 ms to port resume complete */
1687                 msleep(25);
1688                 /* disable PMC master control */
1689                 utmip_phy_disable_pmc_bus_ctrl(phy);
1690
1691                 /* Clear PCI and SRI bits to avoid an interrupt upon resume */
1692                 val = readl(base + USB_USBSTS);
1693                 writel(val, base + USB_USBSTS);
1694                 /* wait to avoid SOF if there is any */
1695                 if (usb_phy_reg_status_wait(base + USB_USBSTS,
1696                         USB_USBSTS_SRI, USB_USBSTS_SRI, 2500) < 0) {
1697                         pr_err("%s: timeout waiting for SOF\n", __func__);
1698                 }
1699                 utmi_phy_post_resume(phy);
1700         }
1701 }
1702
1703 static int utmi_phy_resume(struct tegra_usb_phy *phy)
1704 {
1705         int status = 0;
1706         unsigned long val;
1707         void __iomem *base = phy->regs;
1708
1709         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1710         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) {
1711                 if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
1712                         utmi_phy_restore_start(phy);
1713                         usb_phy_bringup_host_controller(phy);
1714                         utmi_phy_restore_end(phy);
1715                 } else {
1716                         /* device is plugged in when system is in LP0 */
1717                         /* bring up the controller from LP0*/
1718                         val = readl(base + USB_USBCMD);
1719                         val |= USB_CMD_RESET;
1720                         writel(val, base + USB_USBCMD);
1721
1722                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1723                                 USB_CMD_RESET, 0, 2500) < 0) {
1724                                 pr_err("%s: timeout waiting for reset\n", __func__);
1725                         }
1726
1727                         val = readl(base + USB_USBMODE);
1728                         val &= ~USB_USBMODE_MASK;
1729                         val |= USB_USBMODE_HOST;
1730                         writel(val, base + USB_USBMODE);
1731
1732                         val = readl(base + HOSTPC1_DEVLC);
1733                         val &= ~HOSTPC1_DEVLC_PTS(~0);
1734                         val |= HOSTPC1_DEVLC_STS;
1735                         writel(val, base + HOSTPC1_DEVLC);
1736
1737                         writel(USB_USBCMD_RS, base + USB_USBCMD);
1738
1739                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1740                                 USB_USBCMD_RS, USB_USBCMD_RS, 2500) < 0) {
1741                                 pr_err("%s: timeout waiting for run bit\n", __func__);
1742                         }
1743
1744                         /* Enable Port Power */
1745                         val = readl(base + USB_PORTSC);
1746                         val |= USB_PORTSC_PP;
1747                         writel(val, base + USB_PORTSC);
1748                         udelay(10);
1749
1750                         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1751                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1752                 }
1753         }
1754
1755         return status;
1756 }
1757
1758 static bool utmi_phy_charger_detect(struct tegra_usb_phy *phy)
1759 {
1760         unsigned long val;
1761         void __iomem *base = phy->regs;
1762         bool status;
1763
1764         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1765         if (phy->pdata->op_mode != TEGRA_USB_OPMODE_DEVICE) {
1766                 /* Charger detection is not there for ULPI
1767                  * return Charger not available */
1768                 return false;
1769         }
1770
1771         /* Enable charger detection logic */
1772         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1773         val |= UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN;
1774         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1775
1776         /* Source should be on for 100 ms as per USB charging spec */
1777         msleep(TDP_SRC_ON_MS);
1778
1779         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1780         /* If charger is not connected disable the interrupt */
1781         val &= ~VDAT_DET_INT_EN;
1782         val |= VDAT_DET_CHG_DET;
1783         writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
1784
1785         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1786         if (val & VDAT_DET_STS)
1787                 status = true;
1788         else
1789                 status = false;
1790
1791         /* Disable charger detection logic */
1792         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1793         val &= ~(UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN);
1794         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1795
1796         /* Delay of 40 ms before we pull the D+ as per battery charger spec */
1797         msleep(TDPSRC_CON_MS);
1798
1799         return status;
1800 }
1801
1802 static void uhsic_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
1803 {
1804         unsigned long val;
1805         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1806
1807         /* turn on pad detectors for HSIC*/
1808         val = readl(pmc_base + PMC_USB_AO);
1809         val &= ~(HSIC_RESERVED_P0 | STROBE_VAL_PD_P0 | DATA_VAL_PD_P0);
1810         writel(val, pmc_base + PMC_USB_AO);
1811
1812         /* Disable PMC master mode by clearing MASTER_EN */
1813         val = readl(pmc_base + PMC_SLEEP_CFG);
1814         val &= ~(UHSIC_MASTER_ENABLE_P0);
1815         writel(val, pmc_base + PMC_SLEEP_CFG);
1816         mdelay(1);
1817 }
1818
1819 static void uhsic_setup_pmc_wake_detect(struct tegra_usb_phy *phy)
1820 {
1821         unsigned long val;
1822         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1823         void __iomem *base = phy->regs;
1824         bool port_connected;
1825
1826         DBG("%s:%d\n", __func__, __LINE__);
1827
1828         /* check for port connect status */
1829         val = readl(base + USB_PORTSC);
1830         port_connected = val & USB_PORTSC_CCS;
1831
1832         if (!port_connected)
1833                 return;
1834
1835         /*Set PMC MASTER bits to do the following
1836         * a. Take over the hsic drivers
1837         * b. set up such that it will take over resume
1838         *        if remote wakeup is detected
1839         * Prepare PMC to take over suspend-wake detect-drive resume until USB
1840         * controller ready
1841         */
1842
1843         /* disable master enable in PMC */
1844         val = readl(pmc_base + PMC_SLEEP_CFG);
1845         val &= ~UHSIC_MASTER_ENABLE_P0;
1846         writel(val, pmc_base + PMC_SLEEP_CFG);
1847
1848         /* UTMIP_PWR_PX=1 for power savings mode */
1849         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
1850         val |= UHSIC_PWR;
1851         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
1852
1853
1854         /* Enable which type of event can trigger a walk,
1855         * in this case usb_line_wake */
1856         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
1857         val |= UHSIC_LINEVAL_WALK_EN;
1858         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
1859
1860         /* program walk sequence, maintain a J, followed by a driven K
1861         * to signal a resume once an wake event is detected */
1862
1863         val = readl(pmc_base + PMC_SLEEPWALK_UHSIC);
1864
1865         val &= ~UHSIC_DATA_RPU_A;
1866         val |=  UHSIC_DATA_RPD_A;
1867         val &= ~UHSIC_STROBE_RPD_A;
1868         val |=  UHSIC_STROBE_RPU_A;
1869         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1870
1871         val &= ~UHSIC_DATA_RPD_B;
1872         val |=  UHSIC_DATA_RPU_B;
1873         val &= ~UHSIC_STROBE_RPU_B;
1874         val |=  UHSIC_STROBE_RPD_B;
1875         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1876
1877         val &= ~UHSIC_DATA_RPD_C;
1878         val |=  UHSIC_DATA_RPU_C;
1879         val &= ~UHSIC_STROBE_RPU_C;
1880         val |=  UHSIC_STROBE_RPD_C;
1881         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1882
1883         val &= ~UHSIC_DATA_RPD_D;
1884         val |=  UHSIC_DATA_RPU_D;
1885         val &= ~UHSIC_STROBE_RPU_D;
1886         val |=  UHSIC_STROBE_RPD_D;
1887         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1888
1889         /* turn on pad detectors */
1890         val = readl(pmc_base + PMC_USB_AO);
1891         val &= ~(STROBE_VAL_PD_P0 | DATA_VAL_PD_P0);
1892         writel(val, pmc_base + PMC_USB_AO);
1893         /* Add small delay before usb detectors provide stable line values */
1894         udelay(1);
1895
1896         phy->remote_wakeup = false;
1897
1898         /* Turn over pad configuration to PMC  for line wake events*/
1899         val = readl(pmc_base + PMC_SLEEP_CFG);
1900         val &= ~UHSIC_WAKE_VAL(~0);
1901         val |= UHSIC_WAKE_VAL(WAKE_VAL_SD10);
1902         val |= UHSIC_MASTER_ENABLE;
1903         writel(val, pmc_base + PMC_SLEEP_CFG);
1904
1905         val = readl(base + UHSIC_PMC_WAKEUP0);
1906         val |= EVENT_INT_ENB;
1907         writel(val, base + UHSIC_PMC_WAKEUP0);
1908
1909         DBG("%s:PMC enabled for HSIC remote wakeup\n", __func__);
1910 }
1911
1912 static void uhsic_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy)
1913 {
1914         unsigned long val;
1915         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1916         void __iomem *base = phy->regs;
1917
1918         DBG("%s (%d)\n", __func__, __LINE__);
1919         val = readl(pmc_base + PMC_SLEEP_CFG);
1920         val &= ~UHSIC_WAKE_VAL(0x0);
1921         val |= UHSIC_WAKE_VAL(WAKE_VAL_NONE);
1922         writel(val, pmc_base + PMC_SLEEP_CFG);
1923
1924         val = readl(pmc_base + PMC_TRIGGERS);
1925         val |= UHSIC_CLR_WAKE_ALARM_P0 | UHSIC_CLR_WALK_PTR_P0;
1926         writel(val, pmc_base + PMC_TRIGGERS);
1927
1928         val = readl(base + UHSIC_PMC_WAKEUP0);
1929         val &= ~EVENT_INT_ENB;
1930         writel(val, base + UHSIC_PMC_WAKEUP0);
1931
1932         /* Disable PMC master mode by clearing MASTER_EN */
1933         val = readl(pmc_base + PMC_SLEEP_CFG);
1934         val &= ~(UHSIC_MASTER_ENABLE);
1935         writel(val, pmc_base + PMC_SLEEP_CFG);
1936
1937         /* turn off pad detectors */
1938         val = readl(pmc_base + PMC_USB_AO);
1939         val |= (STROBE_VAL_PD_P0 | DATA_VAL_PD_P0);
1940         writel(val, pmc_base + PMC_USB_AO);
1941
1942         phy->remote_wakeup = false;
1943 }
1944
1945 static bool uhsic_phy_remotewake_detected(struct tegra_usb_phy *phy)
1946 {
1947         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1948         void __iomem *base = phy->regs;
1949         u32 val;
1950
1951         val = readl(base + UHSIC_PMC_WAKEUP0);
1952         if (val & EVENT_INT_ENB) {
1953                 val = readl(pmc_base + UTMIP_UHSIC_STATUS);
1954                 if (UHSIC_WAKE_ALARM & val) {
1955                         val = readl(pmc_base + PMC_SLEEP_CFG);
1956                         val &= ~UHSIC_WAKE_VAL(0x0);
1957                         val |= UHSIC_WAKE_VAL(WAKE_VAL_NONE);
1958                         writel(val, pmc_base + PMC_SLEEP_CFG);
1959
1960                         val = readl(pmc_base + PMC_TRIGGERS);
1961                         val |= UHSIC_CLR_WAKE_ALARM_P0 | UHSIC_CLR_WALK_PTR_P0;
1962                         writel(val, pmc_base + PMC_TRIGGERS);
1963
1964                         val = readl(base + UHSIC_PMC_WAKEUP0);
1965                         val &= ~EVENT_INT_ENB;
1966                         writel(val, base + UHSIC_PMC_WAKEUP0);
1967                         phy->remote_wakeup = true;
1968                         DBG("%s:PMC remote wakeup detected for HSIC\n", __func__);
1969                         return true;
1970                 }
1971         }
1972         return false;
1973 }
1974
1975 static int uhsic_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1976 {
1977         DBG("%s(%d)\n", __func__, __LINE__);
1978
1979         if (!remote_wakeup)
1980                 usb_phy_wait_for_sof(phy);
1981
1982         return 0;
1983 }
1984
1985 static int uhsic_phy_post_resume(struct tegra_usb_phy *phy)
1986 {
1987         unsigned long val;
1988         void __iomem *base = phy->regs;
1989
1990         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1991         val = readl(base + USB_TXFILLTUNING);
1992         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
1993                 val = USB_FIFO_TXFILL_THRES(0x10);
1994                 writel(val, base + USB_TXFILLTUNING);
1995         }
1996
1997         return 0;
1998 }
1999
2000 static void uhsic_phy_restore_start(struct tegra_usb_phy *phy)
2001 {
2002         unsigned long val;
2003         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
2004         void __iomem *base = phy->regs;
2005
2006         val = readl(pmc_base + UTMIP_UHSIC_STATUS);
2007
2008         /* check whether we wake up from the remote resume */
2009         if (UHSIC_WALK_PTR_VAL & val) {
2010                 phy->remote_wakeup = true;
2011         } else {
2012                 if (!((UHSIC_STROBE_VAL_P0 | UHSIC_DATA_VAL_P0) & val)) {
2013                                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2014                 } else {
2015                         DBG("%s(%d): setting pretend connect\n", __func__, __LINE__);
2016                         val = readl(base + UHSIC_CMD_CFG0);
2017                         val |= UHSIC_PRETEND_CONNECT_DETECT;
2018                         writel(val, base + UHSIC_CMD_CFG0);
2019                 }
2020         }
2021 }
2022
2023 static void uhsic_phy_restore_end(struct tegra_usb_phy *phy)
2024 {
2025
2026         unsigned long val;
2027         void __iomem *base = phy->regs;
2028         int wait_time_us = 3000; /* FPR should be set by this time */
2029
2030         DBG("%s(%d)\n", __func__, __LINE__);
2031
2032         /* check whether we wake up from the remote resume */
2033         if (phy->remote_wakeup) {
2034                 /* wait until FPR bit is set automatically on remote resume */
2035                 do {
2036                         val = readl(base + USB_PORTSC);
2037                         udelay(1);
2038                         if (wait_time_us == 0) {
2039                                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2040                                 uhsic_phy_post_resume(phy);
2041                                 return;
2042                         }
2043                         wait_time_us--;
2044                 } while (!(val & USB_PORTSC_RESUME));
2045                 /* wait for 25 ms to port resume complete */
2046                 msleep(25);
2047                 /* disable PMC master control */
2048                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2049
2050                 /* Clear PCI and SRI bits to avoid an interrupt upon resume */
2051                 val = readl(base + USB_USBSTS);
2052                 writel(val, base + USB_USBSTS);
2053                 /* wait to avoid SOF if there is any */
2054                 if (usb_phy_reg_status_wait(base + USB_USBSTS,
2055                         USB_USBSTS_SRI, USB_USBSTS_SRI, 2500)) {
2056                         pr_warn("%s: timeout waiting for SOF\n", __func__);
2057                 }
2058                 uhsic_phy_post_resume(phy);
2059         } else {
2060                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2061         }
2062
2063         /* Set RUN bit */
2064         val = readl(base + USB_USBCMD);
2065         val |= USB_USBCMD_RS;
2066         writel(val, base + USB_USBCMD);
2067         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2068                                                  USB_USBCMD_RS, 2000)) {
2069                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2070                 return;
2071         }
2072 }
2073
2074 static int uhsic_phy_open(struct tegra_usb_phy *phy)
2075 {
2076         unsigned long parent_rate;
2077         int i;
2078
2079         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2080         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
2081         for (i = 0; i < ARRAY_SIZE(uhsic_freq_table); i++) {
2082                 if (uhsic_freq_table[i].freq == parent_rate) {
2083                         phy->freq = &uhsic_freq_table[i];
2084                         break;
2085                 }
2086         }
2087         if (!phy->freq) {
2088                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
2089                 return -EINVAL;
2090         }
2091
2092         uhsic_powerup_pmc_wake_detect(phy);
2093
2094         return 0;
2095 }
2096
2097 static int uhsic_phy_irq(struct tegra_usb_phy *phy)
2098 {
2099         usb_phy_fence_read(phy);
2100         /* check if there is any remote wake event */
2101         if (uhsic_phy_remotewake_detected(phy))
2102                 pr_info("%s: uhsic remote wake detected\n", __func__);
2103         return IRQ_HANDLED;
2104 }
2105
2106 static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
2107 {
2108         unsigned long val;
2109         void __iomem *base = phy->regs;
2110         struct tegra_hsic_config *config = &phy->pdata->u_cfg.hsic;
2111
2112         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2113
2114         if (phy->phy_clk_on) {
2115                 DBG("%s(%d) inst:[%d] phy clk is already On\n",
2116                                         __func__, __LINE__, phy->inst);
2117                 return 0;
2118         }
2119
2120         val = readl(base + UHSIC_PADS_CFG1);
2121         val &= ~(UHSIC_PD_BG | UHSIC_PD_TRK | UHSIC_PD_RX |
2122                         UHSIC_PD_ZI | UHSIC_RPD_DATA | UHSIC_RPD_STROBE);
2123         val |= (UHSIC_RX_SEL | UHSIC_PD_TX);
2124         writel(val, base + UHSIC_PADS_CFG1);
2125
2126         val = readl(base + USB_SUSP_CTRL);
2127         val |= UHSIC_RESET;
2128         writel(val, base + USB_SUSP_CTRL);
2129         udelay(1);
2130
2131         val = readl(base + USB_SUSP_CTRL);
2132         val |= UHSIC_PHY_ENABLE;
2133         writel(val, base + USB_SUSP_CTRL);
2134
2135         val = readl(base + UHSIC_HSRX_CFG0);
2136         val |= UHSIC_IDLE_WAIT(config->idle_wait_delay);
2137         val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(config->elastic_underrun_limit);
2138         val |= UHSIC_ELASTIC_OVERRUN_LIMIT(config->elastic_overrun_limit);
2139         writel(val, base + UHSIC_HSRX_CFG0);
2140
2141         val = readl(base + UHSIC_HSRX_CFG1);
2142         val |= UHSIC_HS_SYNC_START_DLY(config->sync_start_delay);
2143         writel(val, base + UHSIC_HSRX_CFG1);
2144
2145         /* WAR HSIC TX */
2146         val = readl(base + UHSIC_TX_CFG0);
2147         val &= ~UHSIC_HS_READY_WAIT_FOR_VALID;
2148         writel(val, base + UHSIC_TX_CFG0);
2149
2150         val = readl(base + UHSIC_MISC_CFG0);
2151         val |= UHSIC_SUSPEND_EXIT_ON_EDGE;
2152         /* Disable generic bus reset, to allow AP30 specific bus reset*/
2153         val |= UHSIC_DISABLE_BUSRESET;
2154         writel(val, base + UHSIC_MISC_CFG0);
2155
2156         val = readl(base + UHSIC_MISC_CFG1);
2157         val |= UHSIC_PLLU_STABLE_COUNT(phy->freq->stable_count);
2158         writel(val, base + UHSIC_MISC_CFG1);
2159
2160         val = readl(base + UHSIC_PLL_CFG1);
2161         val |= UHSIC_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
2162         val |= UHSIC_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count);
2163         writel(val, base + UHSIC_PLL_CFG1);
2164
2165         val = readl(base + USB_SUSP_CTRL);
2166         val &= ~(UHSIC_RESET);
2167         writel(val, base + USB_SUSP_CTRL);
2168         udelay(1);
2169
2170         val = readl(base + UHSIC_PADS_CFG1);
2171         val &= ~(UHSIC_PD_TX);
2172         writel(val, base + UHSIC_PADS_CFG1);
2173
2174         val = readl(base + USB_USBMODE);
2175         val |= USB_USBMODE_HOST;
2176         writel(val, base + USB_USBMODE);
2177
2178         /* Change the USB controller PHY type to HSIC */
2179         val = readl(base + HOSTPC1_DEVLC);
2180         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
2181         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2182         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
2183         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2184         val &= ~HOSTPC1_DEVLC_STS;
2185         writel(val, base + HOSTPC1_DEVLC);
2186
2187         val = readl(base + USB_TXFILLTUNING);
2188         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
2189                 val = USB_FIFO_TXFILL_THRES(0x10);
2190                 writel(val, base + USB_TXFILLTUNING);
2191         }
2192
2193         val = readl(base + USB_PORTSC);
2194         val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN);
2195         writel(val, base + USB_PORTSC);
2196
2197         val = readl(base + UHSIC_PADS_CFG0);
2198         val &= ~(UHSIC_TX_RTUNEN);
2199         /* set Rtune impedance to 50 ohm */
2200         val |= UHSIC_TX_RTUNE(8);
2201         writel(val, base + UHSIC_PADS_CFG0);
2202
2203         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
2204                                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500)) {
2205                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2206                 return -ETIMEDOUT;
2207         }
2208
2209         phy->phy_clk_on = true;
2210         phy->hw_accessible = true;
2211
2212         return 0;
2213 }
2214
2215 static int uhsic_phy_power_off(struct tegra_usb_phy *phy)
2216 {
2217         unsigned long val;
2218         void __iomem *base = phy->regs;
2219
2220         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2221         if (!phy->phy_clk_on) {
2222                 DBG("%s(%d) inst:[%d] phy clk is already off\n",
2223                                         __func__, __LINE__, phy->inst);
2224                 return 0;
2225         }
2226
2227         phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
2228                         HOSTPC1_DEVLC_PSPD_MASK;
2229
2230         /* Disable interrupts */
2231         writel(0, base + USB_USBINTR);
2232
2233         uhsic_setup_pmc_wake_detect(phy);
2234
2235         val = readl(base + HOSTPC1_DEVLC);
2236         val |= HOSTPC1_DEVLC_PHCD;
2237         writel(val, base + HOSTPC1_DEVLC);
2238
2239         phy->phy_clk_on = false;
2240         phy->hw_accessible = false;
2241
2242         return 0;
2243 }
2244
2245 static int uhsic_phy_bus_port_power(struct tegra_usb_phy *phy)
2246 {
2247         unsigned long val;
2248         void __iomem *base = phy->regs;
2249
2250         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2251
2252         val = readl(base + USB_USBMODE);
2253         val |= USB_USBMODE_HOST;
2254         writel(val, base + USB_USBMODE);
2255
2256         /* Change the USB controller PHY type to HSIC */
2257         val = readl(base + HOSTPC1_DEVLC);
2258         val &= ~(HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK));
2259         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2260         val &= ~(HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK));
2261         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2262         writel(val, base + HOSTPC1_DEVLC);
2263
2264         val = readl(base + UHSIC_MISC_CFG0);
2265         val |= UHSIC_DETECT_SHORT_CONNECT;
2266         writel(val, base + UHSIC_MISC_CFG0);
2267         udelay(1);
2268
2269         val = readl(base + UHSIC_MISC_CFG0);
2270         val |= UHSIC_FORCE_XCVR_MODE;
2271         writel(val, base + UHSIC_MISC_CFG0);
2272
2273         val = readl(base + UHSIC_PADS_CFG1);
2274         val &= ~UHSIC_RPD_STROBE;
2275         writel(val, base + UHSIC_PADS_CFG1);
2276
2277         if (phy->pdata->ops && phy->pdata->ops->port_power)
2278                 phy->pdata->ops->port_power();
2279
2280         if (usb_phy_reg_status_wait(base + UHSIC_STAT_CFG0,
2281                         UHSIC_CONNECT_DETECT, UHSIC_CONNECT_DETECT, 25000)) {
2282                 pr_err("%s: timeout waiting for UHSIC_CONNECT_DETECT\n",
2283                                                                 __func__);
2284                 return -ETIMEDOUT;
2285         }
2286
2287         return 0;
2288 }
2289
2290 static int uhsic_phy_bus_reset(struct tegra_usb_phy *phy)
2291 {
2292         unsigned long val;
2293         void __iomem *base = phy->regs;
2294
2295         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2296
2297         /* Change the USB controller PHY type to HSIC */
2298         val = readl(base + HOSTPC1_DEVLC);
2299         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
2300         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2301         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
2302         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2303         val &= ~HOSTPC1_DEVLC_STS;
2304         writel(val, base + HOSTPC1_DEVLC);
2305         /* wait here, otherwise HOSTPC1_DEVLC_PSPD will timeout */
2306         mdelay(5);
2307
2308         val = readl(base + USB_PORTSC);
2309         val |= USB_PORTSC_PTC(5);
2310         writel(val, base + USB_PORTSC);
2311         udelay(2);
2312
2313         val = readl(base + USB_PORTSC);
2314         val &= ~(USB_PORTSC_PTC(~0));
2315         writel(val, base + USB_PORTSC);
2316         udelay(2);
2317
2318         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_LS(0),
2319                                                  0, 2000)) {
2320                 pr_err("%s: timeout waiting for USB_PORTSC_LS\n", __func__);
2321                 return -ETIMEDOUT;
2322         }
2323
2324         /* Poll until CCS is enabled */
2325         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
2326                                                  USB_PORTSC_CCS, 2000)) {
2327                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
2328                 return -ETIMEDOUT;
2329         }
2330
2331         if (usb_phy_reg_status_wait(base + HOSTPC1_DEVLC,
2332                         HOSTPC1_DEVLC_PSPD(2),
2333                         HOSTPC1_DEVLC_PSPD(2), 2000) < 0) {
2334                 pr_err("%s: timeout waiting hsic high speed configuration\n",
2335                                                 __func__);
2336                         return -ETIMEDOUT;
2337         }
2338
2339         val = readl(base + USB_USBCMD);
2340         val &= ~USB_USBCMD_RS;
2341         writel(val, base + USB_USBCMD);
2342
2343         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
2344                                                  USB_USBSTS_HCH, 2000)) {
2345                 pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
2346                 return -ETIMEDOUT;
2347         }
2348
2349         val = readl(base + UHSIC_PADS_CFG1);
2350         val &= ~UHSIC_RPU_STROBE;
2351         val |= UHSIC_RPD_STROBE;
2352         writel(val, base + UHSIC_PADS_CFG1);
2353
2354         mdelay(50);
2355
2356         val = readl(base + UHSIC_PADS_CFG1);
2357         val &= ~UHSIC_RPD_STROBE;
2358         val |= UHSIC_RPU_STROBE;
2359         writel(val, base + UHSIC_PADS_CFG1);
2360
2361         val = readl(base + USB_USBCMD);
2362         val |= USB_USBCMD_RS;
2363         writel(val, base + USB_USBCMD);
2364
2365         val = readl(base + UHSIC_PADS_CFG1);
2366         val &= ~UHSIC_RPU_STROBE;
2367         writel(val, base + UHSIC_PADS_CFG1);
2368
2369         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2370                                                  USB_USBCMD_RS, 2000)) {
2371                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2372                 return -ETIMEDOUT;
2373         }
2374
2375         return 0;
2376 }
2377
2378 int uhsic_phy_resume(struct tegra_usb_phy *phy)
2379 {
2380         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2381
2382         uhsic_phy_restore_start(phy);
2383         usb_phy_bringup_host_controller(phy);
2384         uhsic_phy_restore_end(phy);
2385
2386         return 0;
2387 }
2388
2389 static void ulpi_set_trimmer(struct tegra_usb_phy *phy)
2390 {
2391         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2392         void __iomem *base = phy->regs;
2393         unsigned long val;
2394
2395         val = ULPI_DATA_TRIMMER_SEL(config->data_trimmer);
2396         val |= ULPI_STPDIRNXT_TRIMMER_SEL(config->stpdirnxt_trimmer);
2397         val |= ULPI_DIR_TRIMMER_SEL(config->dir_trimmer);
2398         writel(val, base + ULPI_TIMING_CTRL_1);
2399         udelay(10);
2400
2401         val |= ULPI_DATA_TRIMMER_LOAD;
2402         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
2403         val |= ULPI_DIR_TRIMMER_LOAD;
2404         writel(val, base + ULPI_TIMING_CTRL_1);
2405 }
2406
2407 static void reset_utmip_uhsic(void __iomem *base)
2408 {
2409         unsigned long val;
2410
2411         val = readl(base + USB_SUSP_CTRL);
2412         val |= UHSIC_RESET;
2413         writel(val, base + USB_SUSP_CTRL);
2414
2415         val = readl(base + USB_SUSP_CTRL);
2416         val |= UTMIP_RESET;
2417         writel(val, base + USB_SUSP_CTRL);
2418 }
2419
2420 static void ulpi_set_host(void __iomem *base)
2421 {
2422         unsigned long val;
2423
2424         val = readl(base + USB_USBMODE);
2425         val &= ~USB_USBMODE_MASK;
2426         val |= USB_USBMODE_HOST;
2427         writel(val, base + USB_USBMODE);
2428
2429         val = readl(base + HOSTPC1_DEVLC);
2430         val |= HOSTPC1_DEVLC_PTS(2);
2431         writel(val, base + HOSTPC1_DEVLC);
2432 }
2433
2434 static inline void ulpi_pinmux_bypass(struct tegra_usb_phy *phy, bool enable)
2435 {
2436         unsigned long val;
2437         void __iomem *base = phy->regs;
2438
2439         val = readl(base + ULPI_TIMING_CTRL_0);
2440
2441         if (enable)
2442                 val |= ULPI_OUTPUT_PINMUX_BYP;
2443         else
2444                 val &= ~ULPI_OUTPUT_PINMUX_BYP;
2445
2446         writel(val, base + ULPI_TIMING_CTRL_0);
2447 }
2448
2449 static inline void ulpi_null_phy_set_tristate(bool enable)
2450 {
2451 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2452         int tristate = (enable) ? TEGRA_TRI_TRISTATE : TEGRA_TRI_NORMAL;
2453
2454         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA0, tristate);
2455         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA1, tristate);
2456         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA2, tristate);
2457         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA3, tristate);
2458         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA4, tristate);
2459         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA5, tristate);
2460         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA6, tristate);
2461         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA7, tristate);
2462         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_NXT, tristate);
2463
2464         if (enable)
2465                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR, tristate);
2466 #endif
2467 }
2468
2469 static void ulpi_null_phy_obs_read(void)
2470 {
2471         static void __iomem *apb_misc;
2472         unsigned slv0_obs, s2s_obs;
2473
2474         if (!apb_misc)
2475                 apb_misc = ioremap(TEGRA_APB_MISC_BASE, TEGRA_APB_MISC_SIZE);
2476
2477         writel(0x80d1003c, apb_misc + APB_MISC_GP_OBSCTRL_0);
2478         slv0_obs = readl(apb_misc + APB_MISC_GP_OBSDATA_0);
2479
2480         writel(0x80d10040, apb_misc + APB_MISC_GP_OBSCTRL_0);
2481         s2s_obs = readl(apb_misc + APB_MISC_GP_OBSDATA_0);
2482
2483         pr_debug("slv0 obs: %08x\ns2s obs: %08x\n", slv0_obs, s2s_obs);
2484 }
2485
2486 static const struct gpio ulpi_gpios[] = {
2487         {ULPI_STP, GPIOF_IN, "ULPI_STP"},
2488         {ULPI_DIR, GPIOF_OUT_INIT_LOW, "ULPI_DIR"},
2489         {ULPI_D0, GPIOF_OUT_INIT_LOW, "ULPI_D0"},
2490         {ULPI_D1, GPIOF_OUT_INIT_LOW, "ULPI_D1"},
2491 };
2492
2493 static int ulpi_null_phy_open(struct tegra_usb_phy *phy)
2494 {
2495         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2496         int ret;
2497
2498         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2499
2500         ret = gpio_request_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
2501         if (ret)
2502                 return ret;
2503
2504         if (gpio_is_valid(config->phy_restore_gpio)) {
2505                 ret = gpio_request(config->phy_restore_gpio, "phy_restore");
2506                 if (ret)
2507                         goto err_gpio_free;
2508
2509                 gpio_direction_input(config->phy_restore_gpio);
2510         }
2511
2512         tegra_periph_reset_assert(phy->ctrlr_clk);
2513         udelay(10);
2514         tegra_periph_reset_deassert(phy->ctrlr_clk);
2515
2516         return 0;
2517
2518 err_gpio_free:
2519         gpio_free_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
2520         return ret;
2521 }
2522
2523 static void ulpi_null_phy_close(struct tegra_usb_phy *phy)
2524 {
2525         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2526
2527         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2528
2529         if (gpio_is_valid(config->phy_restore_gpio))
2530                 gpio_free(config->phy_restore_gpio);
2531
2532         gpio_free_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
2533 }
2534
2535 static int ulpi_null_phy_power_off(struct tegra_usb_phy *phy)
2536 {
2537         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2538
2539         if (!phy->phy_clk_on) {
2540                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
2541                                                         __LINE__, phy->inst);
2542                 return 0;
2543         }
2544
2545         phy->phy_clk_on = false;
2546         phy->hw_accessible = false;
2547         ulpi_null_phy_set_tristate(true);
2548         return 0;
2549 }
2550
2551 /* NOTE: this function must be called before ehci reset */
2552 static int ulpi_null_phy_init(struct tegra_usb_phy *phy)
2553 {
2554         unsigned long val;
2555         void __iomem *base = phy->regs;
2556
2557         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2558         val = readl(base + ULPIS2S_CTRL);
2559         val |=  ULPIS2S_SLV0_CLAMP_XMIT;
2560         writel(val, base + ULPIS2S_CTRL);
2561
2562         val = readl(base + USB_SUSP_CTRL);
2563         val |= ULPIS2S_SLV0_RESET;
2564         writel(val, base + USB_SUSP_CTRL);
2565         udelay(10);
2566
2567         return 0;
2568 }
2569
2570 static int ulpi_null_phy_irq(struct tegra_usb_phy *phy)
2571 {
2572         usb_phy_fence_read(phy);
2573         return IRQ_HANDLED;
2574 }
2575
2576 /* NOTE: this function must be called after ehci reset */
2577 static int ulpi_null_phy_cmd_reset(struct tegra_usb_phy *phy)
2578 {
2579         unsigned long val;
2580         void __iomem *base = phy->regs;
2581
2582         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2583         ulpi_set_host(base);
2584
2585         /* remove slave0 reset */
2586         val = readl(base + USB_SUSP_CTRL);
2587         val &= ~ULPIS2S_SLV0_RESET;
2588         writel(val, base + USB_SUSP_CTRL);
2589
2590         val = readl(base + ULPIS2S_CTRL);
2591         val &=  ~ULPIS2S_SLV0_CLAMP_XMIT;
2592         writel(val, base + ULPIS2S_CTRL);
2593         udelay(10);
2594
2595         return 0;
2596 }
2597
2598 static int ulpi_null_phy_restore(struct tegra_usb_phy *phy)
2599 {
2600         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2601         unsigned long timeout;
2602         int ulpi_stp = ULPI_STP;
2603
2604         if (gpio_is_valid(config->phy_restore_gpio))
2605                 ulpi_stp = config->phy_restore_gpio;
2606
2607         /* disable ULPI pinmux bypass */
2608         ulpi_pinmux_bypass(phy, false);
2609
2610         /* driving linstate by GPIO */
2611         gpio_set_value(ULPI_D0, 0);
2612         gpio_set_value(ULPI_D1, 0);
2613
2614         /* driving DIR high */
2615         gpio_set_value(ULPI_DIR, 1);
2616
2617         /* remove ULPI tristate */
2618         ulpi_null_phy_set_tristate(false);
2619
2620         /* wait for STP high */
2621         timeout = jiffies + msecs_to_jiffies(25);
2622
2623         while (!gpio_get_value(ulpi_stp)) {
2624                 if (time_after(jiffies, timeout)) {
2625                         pr_warn("phy restore timeout\n");
2626                         return 1;
2627                 }
2628         }
2629
2630         return 0;
2631 }
2632
2633 static int ulpi_null_phy_lp0_resume(struct tegra_usb_phy *phy)
2634 {
2635         unsigned long val;
2636         void __iomem *base = phy->regs;
2637
2638         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2639         ulpi_null_phy_init(phy);
2640
2641         val = readl(base + USB_USBCMD);
2642         val |= USB_CMD_RESET;
2643         writel(val, base + USB_USBCMD);
2644
2645         if (usb_phy_reg_status_wait(base + USB_USBCMD,
2646                 USB_CMD_RESET, 0, 2500) < 0) {
2647                 pr_err("%s: timeout waiting for reset\n", __func__);
2648         }
2649
2650         ulpi_null_phy_cmd_reset(phy);
2651
2652         val = readl(base + USB_USBCMD);
2653         val |= USB_USBCMD_RS;
2654         writel(val, base + USB_USBCMD);
2655         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2656                                                  USB_USBCMD_RS, 2000)) {
2657                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2658                 return -ETIMEDOUT;
2659         }
2660
2661         /* Enable Port Power */
2662         val = readl(base + USB_PORTSC);
2663         val |= USB_PORTSC_PP;
2664         writel(val, base + USB_PORTSC);
2665         udelay(10);
2666
2667         ulpi_null_phy_restore(phy);
2668
2669         return 0;
2670 }
2671
2672 static int ulpi_null_phy_power_on(struct tegra_usb_phy *phy)
2673 {
2674         unsigned long val;
2675         void __iomem *base = phy->regs;
2676         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2677
2678         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2679         if (phy->phy_clk_on) {
2680                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
2681                                                         __LINE__, phy->inst);
2682                 return 0;
2683         }
2684         reset_utmip_uhsic(base);
2685
2686         /* remove ULPI PADS CLKEN reset */
2687         val = readl(base + USB_SUSP_CTRL);
2688         val &= ~ULPI_PADS_CLKEN_RESET;
2689         writel(val, base + USB_SUSP_CTRL);
2690         udelay(10);
2691
2692         val = readl(base + ULPI_TIMING_CTRL_0);
2693         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
2694         writel(val, base + ULPI_TIMING_CTRL_0);
2695
2696         val = readl(base + USB_SUSP_CTRL);
2697         val |= ULPI_PHY_ENABLE;
2698         writel(val, base + USB_SUSP_CTRL);
2699         udelay(10);
2700
2701         /* set timming parameters */
2702         val = readl(base + ULPI_TIMING_CTRL_0);
2703         val |= ULPI_SHADOW_CLK_LOOPBACK_EN;
2704         val &= ~ULPI_SHADOW_CLK_SEL;
2705         val &= ~ULPI_LBK_PAD_EN;
2706         val |= ULPI_SHADOW_CLK_DELAY(config->shadow_clk_delay);
2707         val |= ULPI_CLOCK_OUT_DELAY(config->clock_out_delay);
2708         val |= ULPI_LBK_PAD_E_INPUT_OR;
2709         writel(val, base + ULPI_TIMING_CTRL_0);
2710
2711         writel(0, base + ULPI_TIMING_CTRL_1);
2712         udelay(10);
2713
2714         /* start internal 60MHz clock */
2715         val = readl(base + ULPIS2S_CTRL);
2716         val |= ULPIS2S_ENA;
2717         val |= ULPIS2S_SUPPORT_DISCONNECT;
2718         val |= ULPIS2S_SPARE((phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) ? 3 : 1);
2719         val |= ULPIS2S_PLLU_MASTER_BLASTER60;
2720         writel(val, base + ULPIS2S_CTRL);
2721
2722         /* select ULPI_CORE_CLK_SEL to SHADOW_CLK */
2723         val = readl(base + ULPI_TIMING_CTRL_0);
2724         val |= ULPI_CORE_CLK_SEL;
2725         writel(val, base + ULPI_TIMING_CTRL_0);
2726         udelay(10);
2727
2728         /* enable ULPI null phy clock - can't set the trimmers before this */
2729         val = readl(base + ULPI_TIMING_CTRL_0);
2730         val |= ULPI_CLK_OUT_ENA;
2731         writel(val, base + ULPI_TIMING_CTRL_0);
2732         udelay(10);
2733
2734         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
2735                                                  USB_PHY_CLK_VALID, 2500)) {
2736                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2737                 return -ETIMEDOUT;
2738         }
2739
2740         /* set ULPI trimmers */
2741         ulpi_set_trimmer(phy);
2742
2743         ulpi_set_host(base);
2744
2745         /* remove slave0 reset */
2746         val = readl(base + USB_SUSP_CTRL);
2747         val &= ~ULPIS2S_SLV0_RESET;
2748         writel(val, base + USB_SUSP_CTRL);
2749
2750         /* remove slave1 and line reset */
2751         val = readl(base + USB_SUSP_CTRL);
2752         val &= ~ULPIS2S_SLV1_RESET;
2753         val &= ~ULPIS2S_LINE_RESET;
2754
2755         /* remove ULPI PADS reset */
2756         val &= ~ULPI_PADS_RESET;
2757         writel(val, base + USB_SUSP_CTRL);
2758
2759         if (!phy->ulpi_clk_padout_ena) {
2760                 val = readl(base + ULPI_TIMING_CTRL_0);
2761                 val |= ULPI_CLK_PADOUT_ENA;
2762                 writel(val, base + ULPI_TIMING_CTRL_0);
2763                 phy->ulpi_clk_padout_ena = true;
2764         } else {
2765                 if (!readl(base + USB_ASYNCLISTADDR))
2766                         ulpi_null_phy_lp0_resume(phy);
2767         }
2768         udelay(10);
2769
2770         phy->phy_clk_on = true;
2771         phy->hw_accessible = true;
2772
2773         return 0;
2774 }
2775
2776 static int ulpi_null_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
2777 {
2778         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2779         ulpi_null_phy_obs_read();
2780         usb_phy_wait_for_sof(phy);
2781         ulpi_null_phy_obs_read();
2782         return 0;
2783 }
2784
2785 static int ulpi_null_phy_post_resume(struct tegra_usb_phy *phy)
2786 {
2787         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2788         ulpi_null_phy_obs_read();
2789         return 0;
2790 }
2791
2792 static int ulpi_null_phy_resume(struct tegra_usb_phy *phy)
2793 {
2794         unsigned long val;
2795         void __iomem *base = phy->regs;
2796
2797         if (!readl(base + USB_ASYNCLISTADDR)) {
2798                 /* enable ULPI CLK output pad */
2799                 val = readl(base + ULPI_TIMING_CTRL_0);
2800                 val |= ULPI_CLK_PADOUT_ENA;
2801                 writel(val, base + ULPI_TIMING_CTRL_0);
2802
2803                 /* enable ULPI pinmux bypass */
2804                 ulpi_pinmux_bypass(phy, true);
2805                 udelay(5);
2806 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2807                 /* remove DIR tristate */
2808                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR,
2809                                           TEGRA_TRI_NORMAL);
2810 #endif
2811         }
2812         return 0;
2813 }
2814
2815
2816
2817 static struct tegra_usb_phy_ops utmi_phy_ops = {
2818         .open           = utmi_phy_open,
2819         .close          = utmi_phy_close,
2820         .irq            = utmi_phy_irq,
2821         .power_on       = utmi_phy_power_on,
2822         .power_off      = utmi_phy_power_off,
2823         .pre_resume = utmi_phy_pre_resume,
2824         .resume = utmi_phy_resume,
2825         .post_resume    = utmi_phy_post_resume,
2826         .charger_detect = utmi_phy_charger_detect,
2827         .post_suspend   = phy_post_suspend,
2828 };
2829
2830 static struct tegra_usb_phy_ops uhsic_phy_ops = {
2831         .open           = uhsic_phy_open,
2832         .irq            = uhsic_phy_irq,
2833         .power_on       = uhsic_phy_power_on,
2834         .power_off      = uhsic_phy_power_off,
2835         .pre_resume = uhsic_phy_pre_resume,
2836         .resume = uhsic_phy_resume,
2837         .post_resume = uhsic_phy_post_resume,
2838         .port_power = uhsic_phy_bus_port_power,
2839         .bus_reset      = uhsic_phy_bus_reset,
2840         .post_suspend   = phy_post_suspend,
2841 };
2842
2843 static struct tegra_usb_phy_ops ulpi_null_phy_ops = {
2844         .open           = ulpi_null_phy_open,
2845         .close          = ulpi_null_phy_close,
2846         .init           = ulpi_null_phy_init,
2847         .irq            = ulpi_null_phy_irq,
2848         .power_on       = ulpi_null_phy_power_on,
2849         .power_off      = ulpi_null_phy_power_off,
2850         .pre_resume = ulpi_null_phy_pre_resume,
2851         .resume = ulpi_null_phy_resume,
2852         .post_resume = ulpi_null_phy_post_resume,
2853         .reset          = ulpi_null_phy_cmd_reset,
2854         .post_suspend   = phy_post_suspend,
2855 };
2856
2857 static struct tegra_usb_phy_ops ulpi_link_phy_ops;
2858 static struct tegra_usb_phy_ops icusb_phy_ops;
2859
2860 static struct tegra_usb_phy_ops *phy_ops[] = {
2861         [TEGRA_USB_PHY_INTF_UTMI] = &utmi_phy_ops,
2862         [TEGRA_USB_PHY_INTF_ULPI_LINK] = &ulpi_link_phy_ops,
2863         [TEGRA_USB_PHY_INTF_ULPI_NULL] = &ulpi_null_phy_ops,
2864         [TEGRA_USB_PHY_INTF_HSIC] = &uhsic_phy_ops,
2865         [TEGRA_USB_PHY_INTF_ICUSB] = &icusb_phy_ops,
2866 };
2867
2868 int tegra3_usb_phy_init_ops(struct tegra_usb_phy *phy)
2869 {
2870         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2871
2872         phy->ops = phy_ops[phy->pdata->phy_intf];
2873
2874         /* FIXME: uncommenting below line to make USB host mode fail*/
2875         /* usb_phy_power_down_pmc(); */
2876
2877         return 0;
2878 }