9f36413ee2bcb4c0508c7c6000dd9ed39de99a81
[linux-2.6.git] / arch / arm / mach-tegra / tegra3_usb_phy.c
1 /*
2  * arch/arm/mach-tegra/tegra3_usb_phy.c
3  *
4  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
5  *
6  *
7  * This software is licensed under the terms of the GNU General Public
8  * License version 2, as published by the Free Software Foundation, and
9  * may be copied, distributed, and modified under those terms.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17 #include <linux/resource.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/slab.h>
21 #include <linux/err.h>
22 #include <linux/platform_device.h>
23 #include <linux/io.h>
24 #include <linux/gpio.h>
25 #include <linux/interrupt.h>
26 #include <linux/clk.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <mach/clk.h>
30 #include <mach/iomap.h>
31 #include <mach/pinmux.h>
32 #include <mach/pinmux-tegra30.h>
33 #include "tegra_usb_phy.h"
34 #include "gpio-names.h"
35 #include "fuse.h"
36
37 #define USB_USBCMD              0x130
38 #define   USB_USBCMD_RS         (1 << 0)
39 #define   USB_CMD_RESET (1<<1)
40
41 #define USB_USBSTS              0x134
42 #define   USB_USBSTS_PCI        (1 << 2)
43 #define   USB_USBSTS_SRI        (1 << 7)
44 #define   USB_USBSTS_HCH        (1 << 12)
45
46 #define USB_USBINTR             0x138
47
48 #define USB_TXFILLTUNING        0x154
49 #define USB_FIFO_TXFILL_THRES(x)   (((x) & 0x1f) << 16)
50 #define USB_FIFO_TXFILL_MASK    0x1f0000
51
52 #define USB_ASYNCLISTADDR       0x148
53
54 #define ICUSB_CTRL              0x15c
55
56 #define USB_PORTSC              0x174
57 #define   USB_PORTSC_WKOC       (1 << 22)
58 #define   USB_PORTSC_WKDS       (1 << 21)
59 #define   USB_PORTSC_WKCN       (1 << 20)
60 #define   USB_PORTSC_PTC(x)     (((x) & 0xf) << 16)
61 #define   USB_PORTSC_PP (1 << 12)
62 #define   USB_PORTSC_LS(x) (((x) & 0x3) << 10)
63 #define   USB_PORTSC_SUSP       (1 << 7)
64 #define   USB_PORTSC_RESUME     (1 << 6)
65 #define   USB_PORTSC_OCC        (1 << 5)
66 #define   USB_PORTSC_PEC        (1 << 3)
67 #define   USB_PORTSC_PE         (1 << 2)
68 #define   USB_PORTSC_CSC        (1 << 1)
69 #define   USB_PORTSC_CCS        (1 << 0)
70 #define   USB_PORTSC_RWC_BITS (USB_PORTSC_CSC | USB_PORTSC_PEC | USB_PORTSC_OCC)
71
72 #define HOSTPC1_DEVLC           0x1b4
73 #define   HOSTPC1_DEVLC_PHCD            (1 << 22)
74 #define   HOSTPC1_DEVLC_PTS(x)          (((x) & 0x7) << 29)
75 #define   HOSTPC1_DEVLC_PTS_MASK        7
76 #define   HOSTPC1_DEVLC_PTS_HSIC        4
77 #define   HOSTPC1_DEVLC_STS             (1 << 28)
78 #define   HOSTPC1_DEVLC_PSPD(x)         (((x) & 0x3) << 25)
79 #define   HOSTPC1_DEVLC_PSPD_MASK       3
80 #define   HOSTPC1_DEVLC_PSPD_HIGH_SPEED 2
81
82 #define USB_USBMODE             0x1f8
83 #define   USB_USBMODE_MASK              (3 << 0)
84 #define   USB_USBMODE_HOST              (3 << 0)
85 #define   USB_USBMODE_DEVICE            (2 << 0)
86
87 #define USB_SUSP_CTRL           0x400
88 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
89 #define   USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
90 #define   USB_SUSP_CLR                  (1 << 5)
91 #define   USB_PHY_CLK_VALID             (1 << 7)
92 #define   USB_PHY_CLK_VALID_INT_ENB     (1 << 9)
93 #define   USB_PHY_CLK_VALID_INT_STS     (1 << 8)
94 #define   UTMIP_RESET                   (1 << 11)
95 #define   UTMIP_PHY_ENABLE              (1 << 12)
96 #define   ULPI_PHY_ENABLE               (1 << 13)
97 #define   UHSIC_RESET                   (1 << 14)
98 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
99 #define   UHSIC_PHY_ENABLE              (1 << 19)
100 #define   ULPIS2S_SLV0_RESET            (1 << 20)
101 #define   ULPIS2S_SLV1_RESET            (1 << 21)
102 #define   ULPIS2S_LINE_RESET            (1 << 22)
103 #define   ULPI_PADS_RESET               (1 << 23)
104 #define   ULPI_PADS_CLKEN_RESET         (1 << 24)
105
106 #define USB_PHY_VBUS_WAKEUP_ID  0x408
107 #define   VDAT_DET_INT_EN       (1 << 16)
108 #define   VDAT_DET_CHG_DET      (1 << 17)
109 #define   VDAT_DET_STS          (1 << 18)
110 #define   USB_ID_STATUS         (1 << 2)
111
112 #define ULPIS2S_CTRL            0x418
113 #define   ULPIS2S_ENA                   (1 << 0)
114 #define   ULPIS2S_SUPPORT_DISCONNECT    (1 << 2)
115 #define   ULPIS2S_PLLU_MASTER_BLASTER60 (1 << 3)
116 #define   ULPIS2S_SPARE(x)              (((x) & 0xF) << 8)
117 #define   ULPIS2S_FORCE_ULPI_CLK_OUT    (1 << 12)
118 #define   ULPIS2S_DISCON_DONT_CHECK_SE0 (1 << 13)
119 #define   ULPIS2S_SUPPORT_HS_KEEP_ALIVE (1 << 14)
120 #define   ULPIS2S_DISABLE_STP_PU        (1 << 15)
121 #define   ULPIS2S_SLV0_CLAMP_XMIT       (1 << 16)
122
123 #define ULPI_TIMING_CTRL_0      0x424
124 #define   ULPI_CLOCK_OUT_DELAY(x)       ((x) & 0x1F)
125 #define   ULPI_OUTPUT_PINMUX_BYP        (1 << 10)
126 #define   ULPI_CLKOUT_PINMUX_BYP        (1 << 11)
127 #define   ULPI_SHADOW_CLK_LOOPBACK_EN   (1 << 12)
128 #define   ULPI_SHADOW_CLK_SEL           (1 << 13)
129 #define   ULPI_CORE_CLK_SEL             (1 << 14)
130 #define   ULPI_SHADOW_CLK_DELAY(x)      (((x) & 0x1F) << 16)
131 #define   ULPI_LBK_PAD_EN               (1 << 26)
132 #define   ULPI_LBK_PAD_E_INPUT_OR       (1 << 27)
133 #define   ULPI_CLK_OUT_ENA              (1 << 28)
134 #define   ULPI_CLK_PADOUT_ENA           (1 << 29)
135
136 #define ULPI_TIMING_CTRL_1      0x428
137 #define   ULPI_DATA_TRIMMER_LOAD        (1 << 0)
138 #define   ULPI_DATA_TRIMMER_SEL(x)      (((x) & 0x7) << 1)
139 #define   ULPI_STPDIRNXT_TRIMMER_LOAD   (1 << 16)
140 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
141 #define   ULPI_DIR_TRIMMER_LOAD         (1 << 24)
142 #define   ULPI_DIR_TRIMMER_SEL(x)       (((x) & 0x7) << 25)
143
144 #define UTMIP_XCVR_CFG0         0x808
145 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
146 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
147 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
148 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
149 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
150 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
151 #define   UTMIP_XCVR_LSBIAS_SEL                 (1 << 21)
152 #define   UTMIP_XCVR_SETUP_MSB(x)               (((x) & 0x7) << 22)
153 #define   UTMIP_XCVR_HSSLEW_MSB(x)              (((x) & 0x7f) << 25)
154 #define   UTMIP_XCVR_MAX_OFFSET         2
155 #define   UTMIP_XCVR_SETUP_MAX_VALUE    0x7f
156 #define   UTMIP_XCVR_SETUP_MIN_VALUE    0
157 #define   XCVR_SETUP_MSB_CALIB(x) ((x) >> 4)
158
159 #define UTMIP_BIAS_CFG0         0x80c
160 #define   UTMIP_OTGPD                   (1 << 11)
161 #define   UTMIP_BIASPD                  (1 << 10)
162 #define   UTMIP_HSSQUELCH_LEVEL(x)      (((x) & 0x3) << 0)
163 #define   UTMIP_HSDISCON_LEVEL(x)       (((x) & 0x3) << 2)
164 #define   UTMIP_HSDISCON_LEVEL_MSB      (1 << 24)
165
166 #define UTMIP_HSRX_CFG0         0x810
167 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
168 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
169
170 #define UTMIP_HSRX_CFG1         0x814
171 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
172
173 #define UTMIP_TX_CFG0           0x820
174 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
175 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
176
177 #define UTMIP_DEBOUNCE_CFG0 0x82c
178 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
179
180 #define UTMIP_BAT_CHRG_CFG0 0x830
181 #define   UTMIP_PD_CHRG                 (1 << 0)
182 #define   UTMIP_ON_SINK_EN              (1 << 2)
183 #define   UTMIP_OP_SRC_EN               (1 << 3)
184
185 #define UTMIP_XCVR_CFG1         0x838
186 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
187 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
188 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
189 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
190
191 #define UTMIP_BIAS_CFG1         0x83c
192 #define   UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
193 #define   UTMIP_BIAS_PDTRK_POWERDOWN    (1 << 0)
194 #define   UTMIP_BIAS_PDTRK_POWERUP      (1 << 1)
195
196 #define UTMIP_MISC_CFG0         0x824
197 #define   UTMIP_DPDM_OBSERVE            (1 << 26)
198 #define   UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
199 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J   UTMIP_DPDM_OBSERVE_SEL(0xf)
200 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K   UTMIP_DPDM_OBSERVE_SEL(0xe)
201 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
202 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
203 #define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
204 #define   FORCE_PULLDN_DM       (1 << 8)
205 #define   FORCE_PULLDN_DP       (1 << 9)
206 #define   COMB_TERMS            (1 << 0)
207 #define   ALWAYS_FREE_RUNNING_TERMS (1 << 1)
208
209 #define UTMIP_SPARE_CFG0        0x834
210 #define   FUSE_SETUP_SEL                (1 << 3)
211 #define   FUSE_ATERM_SEL                (1 << 4)
212
213 #define UTMIP_PMC_WAKEUP0               0x84c
214 #define   EVENT_INT_ENB                 (1 << 0)
215
216 #define UHSIC_PMC_WAKEUP0               0xc34
217
218 #define UTMIP_BIAS_STS0                 0x840
219 #define   UTMIP_RCTRL_VAL(x)            (((x) & 0xffff) << 0)
220 #define   UTMIP_TCTRL_VAL(x)            (((x) & (0xffff << 16)) >> 16)
221
222 #define UHSIC_PLL_CFG1                          0xc04
223 #define   UHSIC_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
224 #define   UHSIC_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 14)
225
226 #define UHSIC_HSRX_CFG0                         0xc08
227 #define   UHSIC_ELASTIC_UNDERRUN_LIMIT(x)       (((x) & 0x1f) << 2)
228 #define   UHSIC_ELASTIC_OVERRUN_LIMIT(x)        (((x) & 0x1f) << 8)
229 #define   UHSIC_IDLE_WAIT(x)                    (((x) & 0x1f) << 13)
230
231 #define UHSIC_HSRX_CFG1                         0xc0c
232 #define   UHSIC_HS_SYNC_START_DLY(x)            (((x) & 0x1f) << 1)
233
234 #define UHSIC_TX_CFG0                           0xc10
235 #define UHSIC_HS_READY_WAIT_FOR_VALID   (1 << 9)
236 #define UHSIC_MISC_CFG0                         0xc14
237 #define   UHSIC_SUSPEND_EXIT_ON_EDGE            (1 << 7)
238 #define   UHSIC_DETECT_SHORT_CONNECT            (1 << 8)
239 #define   UHSIC_FORCE_XCVR_MODE                 (1 << 15)
240 #define   UHSIC_DISABLE_BUSRESET                (1 << 20)
241 #define UHSIC_MISC_CFG1                         0xc18
242 #define   UHSIC_PLLU_STABLE_COUNT(x)            (((x) & 0xfff) << 2)
243
244 #define UHSIC_PADS_CFG0                         0xc1c
245 #define   UHSIC_TX_RTUNEN                       0xf000
246 #define   UHSIC_TX_RTUNE(x)                     (((x) & 0xf) << 12)
247
248 #define UHSIC_PADS_CFG1                         0xc20
249 #define   UHSIC_PD_BG                           (1 << 2)
250 #define   UHSIC_PD_TX                           (1 << 3)
251 #define   UHSIC_PD_TRK                          (1 << 4)
252 #define   UHSIC_PD_RX                           (1 << 5)
253 #define   UHSIC_PD_ZI                           (1 << 6)
254 #define   UHSIC_RX_SEL                          (1 << 7)
255 #define   UHSIC_RPD_DATA                        (1 << 9)
256 #define   UHSIC_RPD_STROBE                      (1 << 10)
257 #define   UHSIC_RPU_DATA                        (1 << 11)
258 #define   UHSIC_RPU_STROBE                      (1 << 12)
259
260 #define UHSIC_CMD_CFG0                  0xc24
261 #define UHSIC_PRETEND_CONNECT_DETECT    (1 << 5)
262
263 #define UHSIC_STAT_CFG0         0xc28
264 #define UHSIC_CONNECT_DETECT            (1 << 0)
265
266 #define PMC_USB_DEBOUNCE                        0xec
267 #define UTMIP_LINE_DEB_CNT(x)           (((x) & 0xf) << 16)
268 #define UHSIC_LINE_DEB_CNT(x)           (((x) & 0xf) << 20)
269
270 #define PMC_USB_AO                              0xf0
271
272 #define PMC_POWER_DOWN_MASK                     0xffff
273 #define HSIC_RESERVED_P0                        (3 << 14)
274 #define STROBE_VAL_PD_P0                        (1 << 12)
275 #define DATA_VAL_PD_P0                          (1 << 13)
276
277 #define USB_ID_PD(inst)                 (1 << ((4*(inst))+3))
278 #define VBUS_WAKEUP_PD(inst)                    (1 << ((4*(inst))+2))
279 #define   USBON_VAL_PD(inst)                    (1 << ((4*(inst))+1))
280 #define   USBON_VAL_PD_P2                       (1 << 9)
281 #define   USBON_VAL_PD_P1                       (1 << 5)
282 #define   USBON_VAL_PD_P0                       (1 << 1)
283 #define   USBOP_VAL_PD(inst)                    (1 << (4*(inst)))
284 #define   USBOP_VAL_PD_P2                       (1 << 8)
285 #define   USBOP_VAL_PD_P1                       (1 << 4)
286 #define   USBOP_VAL_PD_P0                       (1 << 0)
287 #define   PMC_USB_AO_PD_P2                      (0xf << 8)
288 #define   PMC_USB_AO_ID_PD_P0                   (1 << 3)
289 #define   PMC_USB_AO_VBUS_WAKEUP_PD_P0  (1 << 2)
290
291 #define PMC_TRIGGERS                    0x1ec
292
293 #define   UHSIC_CLR_WALK_PTR_P0         (1 << 3)
294 #define   UTMIP_CLR_WALK_PTR(inst)      (1 << (inst))
295 #define   UTMIP_CLR_WALK_PTR_P2         (1 << 2)
296 #define   UTMIP_CLR_WALK_PTR_P1         (1 << 1)
297 #define   UTMIP_CLR_WALK_PTR_P0         (1 << 0)
298 #define   UTMIP_CAP_CFG(inst)   (1 << ((inst)+4))
299 #define   UTMIP_CAP_CFG_P2              (1 << 6)
300 #define   UTMIP_CAP_CFG_P1              (1 << 5)
301 #define   UTMIP_CAP_CFG_P0              (1 << 4)
302 #define   UTMIP_CLR_WAKE_ALARM(inst)    (1 << ((inst)+12))
303 #define   UHSIC_CLR_WAKE_ALARM_P0       (1 << 15)
304 #define   UTMIP_CLR_WAKE_ALARM_P2       (1 << 14)
305
306 #define PMC_PAD_CFG             (0x1f4)
307
308 #define PMC_UTMIP_TERM_PAD_CFG  0x1f8
309 #define   PMC_TCTRL_VAL(x)      (((x) & 0x1f) << 5)
310 #define   PMC_RCTRL_VAL(x)      (((x) & 0x1f) << 0)
311
312 #define PMC_SLEEP_CFG                   0x1fc
313
314 #define   UHSIC_MASTER_ENABLE                   (1 << 24)
315 #define   UHSIC_WAKE_VAL(x)             (((x) & 0xf) << 28)
316 #define   WAKE_VAL_SD10                 0x2
317 #define   UTMIP_TCTRL_USE_PMC(inst) (1 << ((8*(inst))+3))
318 #define   UTMIP_TCTRL_USE_PMC_P2                (1 << 19)
319 #define   UTMIP_TCTRL_USE_PMC_P1                (1 << 11)
320 #define   UTMIP_TCTRL_USE_PMC_P0                (1 << 3)
321 #define   UTMIP_RCTRL_USE_PMC(inst) (1 << ((8*(inst))+2))
322 #define   UTMIP_RCTRL_USE_PMC_P2                (1 << 18)
323 #define   UTMIP_RCTRL_USE_PMC_P1                (1 << 10)
324 #define   UTMIP_RCTRL_USE_PMC_P0                (1 << 2)
325 #define   UTMIP_FSLS_USE_PMC(inst)      (1 << ((8*(inst))+1))
326 #define   UTMIP_FSLS_USE_PMC_P2         (1 << 17)
327 #define   UTMIP_FSLS_USE_PMC_P1         (1 << 9)
328 #define   UTMIP_FSLS_USE_PMC_P0         (1 << 1)
329 #define   UTMIP_MASTER_ENABLE(inst) (1 << (8*(inst)))
330 #define   UTMIP_MASTER_ENABLE_P2                (1 << 16)
331 #define   UTMIP_MASTER_ENABLE_P1                (1 << 8)
332 #define   UTMIP_MASTER_ENABLE_P0                (1 << 0)
333 #define UHSIC_MASTER_ENABLE_P0          (1 << 24)
334 #define UHSIC_WAKE_VAL_P0(x)            (((x) & 0xf) << 28)
335
336 #define PMC_SLEEPWALK_CFG               0x200
337
338 #define   UHSIC_WAKE_WALK_EN_P0 (1 << 30)
339 #define   UHSIC_LINEVAL_WALK_EN (1 << 31)
340 #define   UTMIP_LINEVAL_WALK_EN(inst) (1 << ((8*(inst))+7))
341 #define   UTMIP_LINEVAL_WALK_EN_P2      (1 << 23)
342 #define   UTMIP_LINEVAL_WALK_EN_P1      (1 << 15)
343 #define   UTMIP_LINEVAL_WALK_EN_P0      (1 << 7)
344 #define   UTMIP_WAKE_VAL(inst, x) (((x) & 0xf) << ((8*(inst))+4))
345 #define   UTMIP_WAKE_VAL_P2(x)          (((x) & 0xf) << 20)
346 #define   UTMIP_WAKE_VAL_P1(x)          (((x) & 0xf) << 12)
347 #define   UTMIP_WAKE_VAL_P0(x)          (((x) & 0xf) << 4)
348 #define   WAKE_VAL_NONE         0xc
349 #define   WAKE_VAL_ANY                  0xF
350 #define   WAKE_VAL_FSJ                  0x2
351 #define   WAKE_VAL_FSK                  0x1
352 #define   WAKE_VAL_SE0                  0x0
353
354 #define PMC_SLEEPWALK_REG(inst)         (0x204 + (4*(inst)))
355 #define   UTMIP_USBOP_RPD_A     (1 << 0)
356 #define   UTMIP_USBON_RPD_A     (1 << 1)
357 #define   UTMIP_AP_A                    (1 << 4)
358 #define   UTMIP_AN_A                    (1 << 5)
359 #define   UTMIP_HIGHZ_A         (1 << 6)
360 #define   UTMIP_USBOP_RPD_B     (1 << 8)
361 #define   UTMIP_USBON_RPD_B     (1 << 9)
362 #define   UTMIP_AP_B                    (1 << 12)
363 #define   UTMIP_AN_B                    (1 << 13)
364 #define   UTMIP_HIGHZ_B         (1 << 14)
365 #define   UTMIP_USBOP_RPD_C     (1 << 16)
366 #define   UTMIP_USBON_RPD_C     (1 << 17)
367 #define   UTMIP_AP_C            (1 << 20)
368 #define   UTMIP_AN_C            (1 << 21)
369 #define   UTMIP_HIGHZ_C         (1 << 22)
370 #define   UTMIP_USBOP_RPD_D     (1 << 24)
371 #define   UTMIP_USBON_RPD_D     (1 << 25)
372 #define   UTMIP_AP_D            (1 << 28)
373 #define   UTMIP_AN_D            (1 << 29)
374 #define   UTMIP_HIGHZ_D         (1 << 30)
375
376 #define PMC_SLEEPWALK_UHSIC             0x210
377
378 #define UHSIC_STROBE_RPD_A              (1 << 0)
379 #define UHSIC_DATA_RPD_A                (1 << 1)
380 #define UHSIC_STROBE_RPU_A              (1 << 2)
381 #define UHSIC_DATA_RPU_A                (1 << 3)
382 #define UHSIC_STROBE_RPD_B              (1 << 8)
383 #define UHSIC_DATA_RPD_B                (1 << 9)
384 #define UHSIC_STROBE_RPU_B              (1 << 10)
385 #define UHSIC_DATA_RPU_B                (1 << 11)
386 #define UHSIC_STROBE_RPD_C              (1 << 16)
387 #define UHSIC_DATA_RPD_C                (1 << 17)
388 #define UHSIC_STROBE_RPU_C              (1 << 18)
389 #define UHSIC_DATA_RPU_C                (1 << 19)
390 #define UHSIC_STROBE_RPD_D              (1 << 24)
391 #define UHSIC_DATA_RPD_D                (1 << 25)
392 #define UHSIC_STROBE_RPU_D              (1 << 26)
393 #define UHSIC_DATA_RPU_D                (1 << 27)
394
395 #define UTMIP_UHSIC_STATUS              0x214
396
397 #define UTMIP_USBOP_VAL(inst)           (1 << ((2*(inst)) + 8))
398 #define UTMIP_USBOP_VAL_P2              (1 << 12)
399 #define UTMIP_USBOP_VAL_P1              (1 << 10)
400 #define UTMIP_USBOP_VAL_P0              (1 << 8)
401 #define UTMIP_USBON_VAL(inst)           (1 << ((2*(inst)) + 9))
402 #define UTMIP_USBON_VAL_P2              (1 << 13)
403 #define UTMIP_USBON_VAL_P1              (1 << 11)
404 #define UTMIP_USBON_VAL_P0              (1 << 9)
405 #define UHSIC_WAKE_ALARM                (1 << 19)
406 #define UTMIP_WAKE_ALARM(inst)          (1 << ((inst) + 16))
407 #define UTMIP_WAKE_ALARM_P2             (1 << 18)
408 #define UTMIP_WAKE_ALARM_P1             (1 << 17)
409 #define UTMIP_WAKE_ALARM_P0             (1 << 16)
410 #define UHSIC_DATA_VAL_P0               (1 << 15)
411 #define UHSIC_STROBE_VAL_P0             (1 << 14)
412 #define UTMIP_WALK_PTR_VAL(inst)        (0x3 << ((inst)*2))
413 #define UHSIC_WALK_PTR_VAL              (0x3 << 6)
414 #define UTMIP_WALK_PTR(inst)            (1 << ((inst)*2))
415 #define UTMIP_WALK_PTR_P2               (1 << 4)
416 #define UTMIP_WALK_PTR_P1               (1 << 2)
417 #define UTMIP_WALK_PTR_P0               (1 << 0)
418
419 #define USB1_PREFETCH_ID                           6
420 #define USB2_PREFETCH_ID                           18
421 #define USB3_PREFETCH_ID                           17
422
423 #define PMC_UTMIP_UHSIC_FAKE            0x218
424
425 #define UHSIC_STROBE_VAL                (1 << 12)
426 #define UHSIC_DATA_VAL                  (1 << 13)
427 #define UHSIC_STROBE_ENB                (1 << 14)
428 #define UHSIC_DATA_ENB                  (1 << 15)
429 #define   USBON_VAL(inst)       (1 << ((4*(inst))+1))
430 #define   USBON_VAL_P2                  (1 << 9)
431 #define   USBON_VAL_P1                  (1 << 5)
432 #define   USBON_VAL_P0                  (1 << 1)
433 #define   USBOP_VAL(inst)       (1 << (4*(inst)))
434 #define   USBOP_VAL_P2                  (1 << 8)
435 #define   USBOP_VAL_P1                  (1 << 4)
436 #define   USBOP_VAL_P0                  (1 << 0)
437
438 #define PMC_UTMIP_BIAS_MASTER_CNTRL 0x30c
439 #define   BIAS_MASTER_PROG_VAL          (1 << 1)
440
441 #define PMC_UTMIP_MASTER_CONFIG 0x310
442
443 #define UTMIP_PWR(inst)         (1 << (inst))
444 #define UHSIC_PWR                       (1 << 3)
445
446 #define FUSE_USB_CALIB_0                0x1F0
447 #define   XCVR_SETUP(x) (((x) & 0x7F) << 0)
448 #define   XCVR_SETUP_LSB_MASK   0xF
449 #define   XCVR_SETUP_MSB_MASK   0x70
450 #define   XCVR_SETUP_LSB_MAX_VAL        0xF
451
452 #define APB_MISC_GP_OBSCTRL_0   0x818
453 #define APB_MISC_GP_OBSDATA_0   0x81c
454
455 /* ULPI GPIO */
456 #define ULPI_STP        TEGRA_GPIO_PY3
457 #define ULPI_DIR        TEGRA_GPIO_PY1
458 #define ULPI_D0         TEGRA_GPIO_PO1
459 #define ULPI_D1         TEGRA_GPIO_PO2
460
461 /* These values (in milli second) are taken from the battery charging spec */
462 #define TDP_SRC_ON_MS    100
463 #define TDPSRC_CON_MS    40
464
465 #ifdef DEBUG
466 #define DBG(stuff...)   pr_info("tegra3_usb_phy: " stuff)
467 #else
468 #define DBG(stuff...)   do {} while (0)
469 #endif
470
471 #if 0
472 #define PHY_DBG(stuff...)       pr_info("tegra3_usb_phy: " stuff)
473 #else
474 #define PHY_DBG(stuff...)       do {} while (0)
475 #endif
476
477
478 static u32 utmip_rctrl_val, utmip_tctrl_val;
479 static DEFINE_SPINLOCK(utmip_pad_lock);
480 static int utmip_pad_count;
481
482 static struct tegra_xtal_freq utmip_freq_table[] = {
483         {
484                 .freq = 12000000,
485                 .enable_delay = 0x02,
486                 .stable_count = 0x2F,
487                 .active_delay = 0x04,
488                 .xtal_freq_count = 0x76,
489                 .debounce = 0x7530,
490                 .pdtrk_count = 5,
491         },
492         {
493                 .freq = 13000000,
494                 .enable_delay = 0x02,
495                 .stable_count = 0x33,
496                 .active_delay = 0x05,
497                 .xtal_freq_count = 0x7F,
498                 .debounce = 0x7EF4,
499                 .pdtrk_count = 5,
500         },
501         {
502                 .freq = 19200000,
503                 .enable_delay = 0x03,
504                 .stable_count = 0x4B,
505                 .active_delay = 0x06,
506                 .xtal_freq_count = 0xBB,
507                 .debounce = 0xBB80,
508                 .pdtrk_count = 7,
509         },
510         {
511                 .freq = 26000000,
512                 .enable_delay = 0x04,
513                 .stable_count = 0x66,
514                 .active_delay = 0x09,
515                 .xtal_freq_count = 0xFE,
516                 .debounce = 0xFDE8,
517                 .pdtrk_count = 9,
518         },
519 };
520
521 static struct tegra_xtal_freq uhsic_freq_table[] = {
522         {
523                 .freq = 12000000,
524                 .enable_delay = 0x02,
525                 .stable_count = 0x2F,
526                 .active_delay = 0x0,
527                 .xtal_freq_count = 0x1CA,
528         },
529         {
530                 .freq = 13000000,
531                 .enable_delay = 0x02,
532                 .stable_count = 0x33,
533                 .active_delay = 0x0,
534                 .xtal_freq_count = 0x1F0,
535         },
536         {
537                 .freq = 19200000,
538                 .enable_delay = 0x03,
539                 .stable_count = 0x4B,
540                 .active_delay = 0x0,
541                 .xtal_freq_count = 0x2DD,
542         },
543         {
544                 .freq = 26000000,
545                 .enable_delay = 0x04,
546                 .stable_count = 0x66,
547                 .active_delay = 0x0,
548                 .xtal_freq_count = 0x3E0,
549         },
550 };
551
552 static void usb_phy_fence_read(struct tegra_usb_phy *phy)
553 {
554         /* Fence read for coherency of AHB master intiated writes */
555         if (phy->inst == 0)
556                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB1_PREFETCH_ID));
557         else if (phy->inst == 1)
558                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB2_PREFETCH_ID));
559         else if (phy->inst == 2)
560                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB3_PREFETCH_ID));
561
562         return;
563 }
564
565 static void utmip_setup_pmc_wake_detect(struct tegra_usb_phy *phy)
566 {
567         unsigned long val, pmc_pad_cfg_val;
568         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
569         unsigned  int inst = phy->inst;
570         void __iomem *base = phy->regs;
571         bool port_connected;
572         enum usb_phy_port_speed port_speed;
573
574         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
575
576         /* check for port connect status */
577         val = readl(base + USB_PORTSC);
578         port_connected = val & USB_PORTSC_CCS;
579
580         if (!port_connected)
581                 return;
582
583         port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
584                 HOSTPC1_DEVLC_PSPD_MASK;
585         /*Set PMC MASTER bits to do the following
586         * a. Take over the UTMI drivers
587         * b. set up such that it will take over resume
588         *        if remote wakeup is detected
589         * Prepare PMC to take over suspend-wake detect-drive resume until USB
590         * controller ready
591         */
592
593         /* disable master enable in PMC */
594         val = readl(pmc_base + PMC_SLEEP_CFG);
595         val &= ~UTMIP_MASTER_ENABLE(inst);
596         writel(val, pmc_base + PMC_SLEEP_CFG);
597
598         /* UTMIP_PWR_PX=1 for power savings mode */
599         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
600         val |= UTMIP_PWR(inst);
601         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
602
603         /* config debouncer */
604         val = readl(pmc_base + PMC_USB_DEBOUNCE);
605         val &= ~UTMIP_LINE_DEB_CNT(~0);
606         val |= UTMIP_LINE_DEB_CNT(4);
607         writel(val, pmc_base + PMC_USB_DEBOUNCE);
608
609         /* Make sure nothing is happening on the line with respect to PMC */
610         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
611         val &= ~USBOP_VAL(inst);
612         val &= ~USBON_VAL(inst);
613         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
614
615         /* Make sure wake value for line is none */
616         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
617         val &= ~UTMIP_LINEVAL_WALK_EN(inst);
618         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
619         val = readl(pmc_base + PMC_SLEEP_CFG);
620         val &= ~UTMIP_WAKE_VAL(inst, ~0);
621         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
622         writel(val, pmc_base + PMC_SLEEP_CFG);
623
624         /* turn off pad detectors */
625         val = readl(pmc_base + PMC_USB_AO);
626         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
627         writel(val, pmc_base + PMC_USB_AO);
628
629         /* Remove fake values and make synchronizers work a bit */
630         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
631         val &= ~USBOP_VAL(inst);
632         val &= ~USBON_VAL(inst);
633         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
634
635         /* Enable which type of event can trigger a walk,
636         in this case usb_line_wake */
637         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
638         val |= UTMIP_LINEVAL_WALK_EN(inst);
639         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
640
641         /* Enable which type of event can trigger a walk,
642         * in this case usb_line_wake */
643         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
644         val |= UTMIP_LINEVAL_WALK_EN(inst);
645         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
646
647         /* Capture FS/LS pad configurations */
648         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
649         val = readl(pmc_base + PMC_TRIGGERS);
650         val |= UTMIP_CAP_CFG(inst);
651         writel(val, pmc_base + PMC_TRIGGERS);
652         udelay(1);
653         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
654
655         /* BIAS MASTER_ENABLE=0 */
656         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
657         val &= ~BIAS_MASTER_PROG_VAL;
658         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
659
660         /* program walk sequence, maintain a J, followed by a driven K
661         * to signal a resume once an wake event is detected */
662         val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
663         val &= ~UTMIP_AP_A;
664         val |= UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_AN_A |UTMIP_HIGHZ_A |
665                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_AP_B | UTMIP_AN_B |
666                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_AP_C | UTMIP_AN_C |
667                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_AP_D | UTMIP_AN_D;
668         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
669
670         if (port_speed == USB_PHY_PORT_SPEED_LOW) {
671                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
672                 val &= ~(UTMIP_AN_B | UTMIP_HIGHZ_B | UTMIP_AN_C |
673                         UTMIP_HIGHZ_C | UTMIP_AN_D | UTMIP_HIGHZ_D);
674                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
675         } else {
676                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
677                 val &= ~(UTMIP_AP_B | UTMIP_HIGHZ_B | UTMIP_AP_C |
678                         UTMIP_HIGHZ_C | UTMIP_AP_D | UTMIP_HIGHZ_D);
679                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
680         }
681
682         /* turn on pad detectors */
683         val = readl(pmc_base + PMC_USB_AO);
684         val &= ~(USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
685         writel(val, pmc_base + PMC_USB_AO);
686
687         /* Add small delay before usb detectors provide stable line values */
688         mdelay(1);
689
690         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
691         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
692         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
693         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
694
695         phy->remote_wakeup = false;
696
697         /* Turn over pad configuration to PMC  for line wake events*/
698         val = readl(pmc_base + PMC_SLEEP_CFG);
699         val &= ~UTMIP_WAKE_VAL(inst, ~0);
700         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_ANY);
701         val |= UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst);
702         val |= UTMIP_MASTER_ENABLE(inst) | UTMIP_FSLS_USE_PMC(inst);
703         writel(val, pmc_base + PMC_SLEEP_CFG);
704
705         val = readl(base + UTMIP_PMC_WAKEUP0);
706         val |= EVENT_INT_ENB;
707         writel(val, base + UTMIP_PMC_WAKEUP0);
708         PHY_DBG("%s ENABLE_PMC inst = %d\n", __func__, inst);
709 }
710
711 static void utmip_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy)
712 {
713         unsigned long val;
714         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
715         unsigned  int inst = phy->inst;
716         void __iomem *base = phy->regs;
717
718         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
719
720         val = readl(pmc_base + PMC_SLEEP_CFG);
721         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
722         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
723         writel(val, pmc_base + PMC_SLEEP_CFG);
724
725         val = readl(pmc_base + PMC_TRIGGERS);
726         val |= UTMIP_CLR_WAKE_ALARM(inst) | UTMIP_CLR_WALK_PTR(inst);
727         writel(val, pmc_base + PMC_TRIGGERS);
728
729         val = readl(base + UTMIP_PMC_WAKEUP0);
730         val &= ~EVENT_INT_ENB;
731         writel(val, base + UTMIP_PMC_WAKEUP0);
732
733         /* Disable PMC master mode by clearing MASTER_EN */
734         val = readl(pmc_base + PMC_SLEEP_CFG);
735         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
736                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
737         writel(val, pmc_base + PMC_SLEEP_CFG);
738
739         val = readl(pmc_base + PMC_TRIGGERS);
740         val &= ~UTMIP_CAP_CFG(inst);
741         writel(val, pmc_base + PMC_TRIGGERS);
742
743         /* turn off pad detectors */
744         val = readl(pmc_base + PMC_USB_AO);
745         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
746         writel(val, pmc_base + PMC_USB_AO);
747
748         phy->remote_wakeup = false;
749         PHY_DBG("%s DISABLE_PMC inst = %d\n", __func__, inst);
750 }
751
752 static bool utmi_phy_remotewake_detected(struct tegra_usb_phy *phy)
753 {
754         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
755         void __iomem *base = phy->regs;
756         unsigned  int inst = phy->inst;
757         u32 val;
758
759         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
760         val = readl(base + UTMIP_PMC_WAKEUP0);
761         if (val & EVENT_INT_ENB) {
762                 val = readl(pmc_base + UTMIP_UHSIC_STATUS);
763                 if (UTMIP_WAKE_ALARM(inst) & val) {
764                         val = readl(pmc_base + PMC_SLEEP_CFG);
765                         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
766                         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
767                         writel(val, pmc_base + PMC_SLEEP_CFG);
768
769                         val = readl(pmc_base + PMC_TRIGGERS);
770                         val |= UTMIP_CLR_WAKE_ALARM(inst) |
771                                 UTMIP_CLR_WALK_PTR(inst);
772                         writel(val, pmc_base + PMC_TRIGGERS);
773
774                         val = readl(base + UTMIP_PMC_WAKEUP0);
775                         val &= ~EVENT_INT_ENB;
776                         writel(val, base + UTMIP_PMC_WAKEUP0);
777                         phy->remote_wakeup = true;
778                         return true;
779                 }
780         }
781         return false;
782 }
783
784 static void utmi_phy_enable_trking_data(struct tegra_usb_phy *phy)
785 {
786         void __iomem *base = IO_ADDRESS(TEGRA_USB_BASE);
787         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
788         static bool init_done = false;
789         u32 val;
790
791         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
792
793         /* Should be done only once after system boot */
794         if (init_done)
795                 return;
796
797         clk_enable(phy->utmi_pad_clk);
798         /* Bias pad MASTER_ENABLE=1 */
799         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
800         val |= BIAS_MASTER_PROG_VAL;
801         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
802
803         /* Setting the tracking length time */
804         val = readl(base + UTMIP_BIAS_CFG1);
805         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
806         val |= UTMIP_BIAS_PDTRK_COUNT(5);
807         writel(val, base + UTMIP_BIAS_CFG1);
808
809         /* Bias PDTRK is Shared and MUST be done from USB1 ONLY, PD_TRK=0 */
810         val = readl(base + UTMIP_BIAS_CFG1);
811         val &= ~UTMIP_BIAS_PDTRK_POWERDOWN;
812         writel(val, base + UTMIP_BIAS_CFG1);
813
814         val = readl(base + UTMIP_BIAS_CFG1);
815         val |= UTMIP_BIAS_PDTRK_POWERUP;
816         writel(val, base + UTMIP_BIAS_CFG1);
817
818         /* Wait for 25usec */
819         udelay(25);
820
821         /* Bias pad MASTER_ENABLE=0 */
822         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
823         val &= ~BIAS_MASTER_PROG_VAL;
824         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
825
826         /* Wait for 1usec */
827         udelay(1);
828
829         /* Bias pad MASTER_ENABLE=1 */
830         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
831         val |= BIAS_MASTER_PROG_VAL;
832         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
833
834         /* Read RCTRL and TCTRL from UTMIP space */
835         val = readl(base + UTMIP_BIAS_STS0);
836         utmip_rctrl_val = ffz(UTMIP_RCTRL_VAL(val));
837         utmip_tctrl_val = ffz(UTMIP_TCTRL_VAL(val));
838
839         /* PD_TRK=1 */
840         val = readl(base + UTMIP_BIAS_CFG1);
841         val |= UTMIP_BIAS_PDTRK_POWERDOWN;
842         writel(val, base + UTMIP_BIAS_CFG1);
843
844         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
845         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
846         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
847         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
848         clk_disable(phy->utmi_pad_clk);
849         init_done = true;
850 }
851
852 static void utmip_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy)
853 {
854         unsigned long val;
855         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
856         unsigned  int inst = phy->inst;
857
858         /* power down UTMIP interfaces */
859         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
860         val |= UTMIP_PWR(inst);
861         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
862
863         /* setup sleep walk usb controller */
864         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
865                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
866                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
867                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
868         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
869
870         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
871         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
872         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
873         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
874
875         /* Turn over pad configuration to PMC */
876         val = readl(pmc_base + PMC_SLEEP_CFG);
877         val &= ~UTMIP_WAKE_VAL(inst, ~0);
878         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE) |
879                 UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
880                 UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst);
881         writel(val, pmc_base + PMC_SLEEP_CFG);
882         PHY_DBG("%s ENABLE_PMC inst = %d\n", __func__, inst);
883 }
884
885 static void utmip_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
886 {
887         unsigned long val;
888         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
889         unsigned  int inst = phy->inst;
890
891         /* Disable PMC master mode by clearing MASTER_EN */
892         val = readl(pmc_base + PMC_SLEEP_CFG);
893         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
894                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
895         writel(val, pmc_base + PMC_SLEEP_CFG);
896         mdelay(1);
897         PHY_DBG("%s DISABLE_PMC inst = %d\n", __func__, inst);
898 }
899
900
901 #ifdef KERNEL_WARNING
902 static void usb_phy_power_down_pmc(void)
903 {
904         unsigned long val;
905         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
906
907         /* power down all 3 UTMIP interfaces */
908         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
909         val |= UTMIP_PWR(0) | UTMIP_PWR(1) | UTMIP_PWR(2);
910         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
911
912         /* turn on pad detectors */
913         writel(PMC_POWER_DOWN_MASK, pmc_base + PMC_USB_AO);
914
915         /* setup sleep walk fl all 3 usb controllers */
916         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
917                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
918                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
919                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
920         writel(val, pmc_base + PMC_SLEEPWALK_REG(0));
921         writel(val, pmc_base + PMC_SLEEPWALK_REG(1));
922         writel(val, pmc_base + PMC_SLEEPWALK_REG(2));
923
924         /* enable pull downs on HSIC PMC */
925         val = UHSIC_STROBE_RPD_A | UHSIC_DATA_RPD_A | UHSIC_STROBE_RPD_B |
926                 UHSIC_DATA_RPD_B | UHSIC_STROBE_RPD_C | UHSIC_DATA_RPD_C |
927                 UHSIC_STROBE_RPD_D | UHSIC_DATA_RPD_D;
928         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
929
930         /* Turn over pad configuration to PMC */
931         val = readl(pmc_base + PMC_SLEEP_CFG);
932         val &= ~UTMIP_WAKE_VAL(0, ~0);
933         val &= ~UTMIP_WAKE_VAL(1, ~0);
934         val &= ~UTMIP_WAKE_VAL(2, ~0);
935         val &= ~UHSIC_WAKE_VAL_P0(~0);
936         val |= UTMIP_WAKE_VAL(0, WAKE_VAL_NONE) | UHSIC_WAKE_VAL_P0(WAKE_VAL_NONE) |
937         UTMIP_WAKE_VAL(1, WAKE_VAL_NONE) | UTMIP_WAKE_VAL(2, WAKE_VAL_NONE) |
938         UTMIP_RCTRL_USE_PMC(0) | UTMIP_RCTRL_USE_PMC(1) | UTMIP_RCTRL_USE_PMC(2) |
939         UTMIP_TCTRL_USE_PMC(0) | UTMIP_TCTRL_USE_PMC(1) | UTMIP_TCTRL_USE_PMC(2) |
940         UTMIP_FSLS_USE_PMC(0) | UTMIP_FSLS_USE_PMC(1) | UTMIP_FSLS_USE_PMC(2) |
941         UTMIP_MASTER_ENABLE(0) | UTMIP_MASTER_ENABLE(1) | UTMIP_MASTER_ENABLE(2) |
942         UHSIC_MASTER_ENABLE_P0;
943         writel(val, pmc_base + PMC_SLEEP_CFG);
944 }
945 #endif
946
947 static int usb_phy_bringup_host_controller(struct tegra_usb_phy *phy)
948 {
949         unsigned long val;
950         void __iomem *base = phy->regs;
951
952         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
953         PHY_DBG("[%d] USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n", __LINE__,
954                 readl(base + USB_USBSTS), readl(base + USB_PORTSC),
955                                                         phy->port_speed);
956
957         /* Device is plugged in when system is in LP0 */
958         /* Bring up the controller from LP0*/
959         val = readl(base + USB_USBCMD);
960         val |= USB_CMD_RESET;
961         writel(val, base + USB_USBCMD);
962
963         if (usb_phy_reg_status_wait(base + USB_USBCMD,
964                 USB_CMD_RESET, 0, 2500) < 0) {
965                 pr_err("%s: timeout waiting for reset\n", __func__);
966         }
967
968         val = readl(base + USB_USBMODE);
969         val &= ~USB_USBMODE_MASK;
970         val |= USB_USBMODE_HOST;
971         writel(val, base + USB_USBMODE);
972         val = readl(base + HOSTPC1_DEVLC);
973         val &= ~HOSTPC1_DEVLC_PTS(~0);
974
975         if (phy->pdata->phy_intf == TEGRA_USB_PHY_INTF_HSIC)
976                 val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
977         else
978                 val |= HOSTPC1_DEVLC_STS;
979         writel(val, base + HOSTPC1_DEVLC);
980
981         /* Enable Port Power */
982         val = readl(base + USB_PORTSC);
983         val |= USB_PORTSC_PP;
984         writel(val, base + USB_PORTSC);
985         udelay(10);
986
987         /* Check if the phy resume from LP0. When the phy resume from LP0
988          * USB register will be reset.to zero */
989         if (!readl(base + USB_ASYNCLISTADDR)) {
990                 /* Program the field PTC based on the saved speed mode */
991                 val = readl(base + USB_PORTSC);
992                 val &= ~USB_PORTSC_PTC(~0);
993                 if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH)
994                         val |= USB_PORTSC_PTC(5);
995                 else if (phy->port_speed == USB_PHY_PORT_SPEED_FULL)
996                         val |= USB_PORTSC_PTC(6);
997                 else if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
998                         val |= USB_PORTSC_PTC(7);
999                 writel(val, base + USB_PORTSC);
1000                 udelay(10);
1001
1002                 /* Disable test mode by setting PTC field to NORMAL_OP */
1003                 val = readl(base + USB_PORTSC);
1004                 val &= ~USB_PORTSC_PTC(~0);
1005                 writel(val, base + USB_PORTSC);
1006                 udelay(10);
1007         }
1008
1009         /* Poll until CCS is enabled */
1010         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
1011                                                  USB_PORTSC_CCS, 2000)) {
1012                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
1013         }
1014
1015         /* Poll until PE is enabled */
1016         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_PE,
1017                                                  USB_PORTSC_PE, 2000)) {
1018                 pr_err("%s: timeout waiting for USB_PORTSC_PE\n", __func__);
1019         }
1020
1021         /* Clear the PCI status, to avoid an interrupt taken upon resume */
1022         val = readl(base + USB_USBSTS);
1023         val |= USB_USBSTS_PCI;
1024         writel(val, base + USB_USBSTS);
1025
1026         if (!phy->remote_wakeup) {
1027                 /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
1028                 val = readl(base + USB_PORTSC);
1029                 if ((val & USB_PORTSC_PP) && (val & USB_PORTSC_PE)) {
1030                         val |= USB_PORTSC_SUSP;
1031                         writel(val, base + USB_PORTSC);
1032                         /* Need a 4ms delay before the controller goes to suspend */
1033                         mdelay(4);
1034
1035                         /* Wait until port suspend completes */
1036                         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_SUSP,
1037                                                          USB_PORTSC_SUSP, 1000)) {
1038                                 pr_err("%s: timeout waiting for PORT_SUSPEND\n",
1039                                                                         __func__);
1040                         }
1041                 }
1042         }
1043         PHY_DBG("[%d] USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n", __LINE__,
1044                 readl(base + USB_USBSTS), readl(base + USB_PORTSC),
1045                                                         phy->port_speed);
1046
1047         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1048                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1049         return 0;
1050 }
1051
1052 static void usb_phy_wait_for_sof(struct tegra_usb_phy *phy)
1053 {
1054         unsigned long val;
1055         void __iomem *base = phy->regs;
1056
1057         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1058
1059         val = readl(base + USB_USBSTS);
1060         writel(val, base + USB_USBSTS);
1061         udelay(20);
1062         /* wait for two SOFs */
1063         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1064                 USB_USBSTS_SRI, 2500))
1065                 pr_err("%s: timeout waiting for SOF\n", __func__);
1066
1067         val = readl(base + USB_USBSTS);
1068         writel(val, base + USB_USBSTS);
1069         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI, 0, 2500))
1070                 pr_err("%s: timeout waiting for SOF\n", __func__);
1071
1072         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1073                         USB_USBSTS_SRI, 2500))
1074                 pr_err("%s: timeout waiting for SOF\n", __func__);
1075
1076         udelay(20);
1077 }
1078
1079 static unsigned int utmi_phy_xcvr_setup_value(struct tegra_usb_phy *phy)
1080 {
1081         struct tegra_utmi_config *cfg = &phy->pdata->u_cfg.utmi;
1082         signed long val;
1083
1084         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1085
1086         if (cfg->xcvr_use_fuses) {
1087                 val = XCVR_SETUP(tegra_fuse_readl(FUSE_USB_CALIB_0));
1088                 if (cfg->xcvr_use_lsb) {
1089                         val = min((unsigned int) ((val & XCVR_SETUP_LSB_MASK)
1090                                 + cfg->xcvr_setup_offset),
1091                                 (unsigned int) XCVR_SETUP_LSB_MAX_VAL);
1092                         val |= (cfg->xcvr_setup & XCVR_SETUP_MSB_MASK);
1093                 } else {
1094                         if (cfg->xcvr_setup_offset <= UTMIP_XCVR_MAX_OFFSET)
1095                                 val = val + cfg->xcvr_setup_offset;
1096
1097                         if (val > UTMIP_XCVR_SETUP_MAX_VALUE) {
1098                                 val = UTMIP_XCVR_SETUP_MAX_VALUE;
1099                                 pr_info("%s: reset XCVR_SETUP to max value\n",
1100                                                 __func__);
1101                         } else if (val < UTMIP_XCVR_SETUP_MIN_VALUE) {
1102                                 val = UTMIP_XCVR_SETUP_MIN_VALUE;
1103                                 pr_info("%s: reset XCVR_SETUP to min value\n",
1104                                                 __func__);
1105                         }
1106                 }
1107         } else {
1108                 val = cfg->xcvr_setup;
1109         }
1110
1111         return (unsigned int) val;
1112 }
1113
1114 static int utmi_phy_open(struct tegra_usb_phy *phy)
1115 {
1116         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1117         unsigned long parent_rate, val;
1118         int i;
1119
1120         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1121
1122         phy->utmi_pad_clk = clk_get_sys("utmip-pad", NULL);
1123         if (IS_ERR(phy->utmi_pad_clk)) {
1124                 pr_err("%s: can't get utmip pad clock\n", __func__);
1125                 return PTR_ERR(phy->utmi_pad_clk);
1126         }
1127
1128         phy->utmi_xcvr_setup = utmi_phy_xcvr_setup_value(phy);
1129
1130         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
1131         for (i = 0; i < ARRAY_SIZE(utmip_freq_table); i++) {
1132                 if (utmip_freq_table[i].freq == parent_rate) {
1133                         phy->freq = &utmip_freq_table[i];
1134                         break;
1135                 }
1136         }
1137         if (!phy->freq) {
1138                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
1139                 return -EINVAL;
1140         }
1141
1142         /* Power-up the VBUS detector for UTMIP PHY */
1143         val = readl(pmc_base + PMC_USB_AO);
1144         val &= ~(PMC_USB_AO_VBUS_WAKEUP_PD_P0 | PMC_USB_AO_ID_PD_P0);
1145         writel((val | PMC_USB_AO_PD_P2), (pmc_base + PMC_USB_AO));
1146
1147         utmip_powerup_pmc_wake_detect(phy);
1148
1149         return 0;
1150 }
1151
1152 static void utmi_phy_close(struct tegra_usb_phy *phy)
1153 {
1154         unsigned long val;
1155         void __iomem *base = phy->regs;
1156
1157         DBG("%s inst:[%d]\n", __func__, phy->inst);
1158
1159         /* Disable PHY clock valid interrupts while going into suspend*/
1160         if (phy->pdata->u_data.host.hot_plug) {
1161                 val = readl(base + USB_SUSP_CTRL);
1162                 val &= ~USB_PHY_CLK_VALID_INT_ENB;
1163                 writel(val, base + USB_SUSP_CTRL);
1164         }
1165
1166         clk_put(phy->utmi_pad_clk);
1167 }
1168
1169 static int utmi_phy_pad_power_on(struct tegra_usb_phy *phy)
1170 {
1171         unsigned long val, flags;
1172         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1173
1174         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1175
1176         clk_enable(phy->utmi_pad_clk);
1177
1178         spin_lock_irqsave(&utmip_pad_lock, flags);
1179         utmip_pad_count++;
1180
1181         val = readl(pad_base + UTMIP_BIAS_CFG0);
1182         val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
1183         val |= UTMIP_HSSQUELCH_LEVEL(0x2) | UTMIP_HSDISCON_LEVEL(0x1) |
1184                 UTMIP_HSDISCON_LEVEL_MSB;
1185         writel(val, pad_base + UTMIP_BIAS_CFG0);
1186
1187         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1188
1189         clk_disable(phy->utmi_pad_clk);
1190
1191         return 0;
1192 }
1193
1194 static int utmi_phy_pad_power_off(struct tegra_usb_phy *phy)
1195 {
1196         unsigned long val, flags;
1197         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1198
1199         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1200
1201         clk_enable(phy->utmi_pad_clk);
1202         spin_lock_irqsave(&utmip_pad_lock, flags);
1203
1204         if (!utmip_pad_count) {
1205                 pr_err("%s: utmip pad already powered off\n", __func__);
1206                 goto out;
1207         }
1208         if (--utmip_pad_count == 0) {
1209                 val = readl(pad_base + UTMIP_BIAS_CFG0);
1210                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
1211                 val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) | UTMIP_HSDISCON_LEVEL(~0) |
1212                         UTMIP_HSDISCON_LEVEL_MSB);
1213                 writel(val, pad_base + UTMIP_BIAS_CFG0);
1214         }
1215 out:
1216         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1217         clk_disable(phy->utmi_pad_clk);
1218
1219         return 0;
1220 }
1221
1222 static int utmi_phy_irq(struct tegra_usb_phy *phy)
1223 {
1224         void __iomem *base = phy->regs;
1225         unsigned long val = 0;
1226
1227         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1228         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1229                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1230         DBG("USB_USBMODE[0x%x] USB_USBCMD[0x%x]\n",
1231                         readl(base + USB_USBMODE), readl(base + USB_USBCMD));
1232
1233         usb_phy_fence_read(phy);
1234         /* check if there is any remote wake event */
1235         if (utmi_phy_remotewake_detected(phy))
1236                 pr_info("%s: utmip remote wake detected\n", __func__);
1237
1238         if (phy->pdata->u_data.host.hot_plug) {
1239                 val = readl(base + USB_SUSP_CTRL);
1240                 if ((val  & USB_PHY_CLK_VALID_INT_STS)) {
1241                         val &= ~USB_PHY_CLK_VALID_INT_ENB |
1242                                         USB_PHY_CLK_VALID_INT_STS;
1243                         writel(val , (base + USB_SUSP_CTRL));
1244                         pr_info("%s: usb device plugged-in\n", __func__);
1245                         val = readl(base + USB_USBSTS);
1246                         if (!(val  & USB_USBSTS_PCI))
1247                                 return IRQ_NONE;
1248                         val = readl(base + USB_PORTSC);
1249                         val &= ~(USB_PORTSC_WKCN | USB_PORTSC_RWC_BITS);
1250                         writel(val , (base + USB_PORTSC));
1251                 }
1252         }
1253
1254         return IRQ_HANDLED;
1255 }
1256
1257 static void utmi_phy_enable_obs_bus(struct tegra_usb_phy *phy)
1258 {
1259         unsigned long val;
1260         void __iomem *base = phy->regs;
1261
1262         /* (2LS WAR)is not required for LS and FS devices and is only for HS */
1263         if ((phy->port_speed == USB_PHY_PORT_SPEED_LOW) ||
1264                 (phy->port_speed == USB_PHY_PORT_SPEED_FULL)) {
1265                 /* do not enable the OBS bus */
1266                 val = readl(base + UTMIP_MISC_CFG0);
1267                 val &= ~(UTMIP_DPDM_OBSERVE_SEL(~0));
1268                 writel(val, base + UTMIP_MISC_CFG0);
1269                 DBG("%s(%d) Disable OBS bus\n", __func__, __LINE__);
1270                 return;
1271         }
1272         /* Force DP/DM pulldown active for Host mode */
1273         val = readl(base + UTMIP_MISC_CFG0);
1274         val |= FORCE_PULLDN_DM | FORCE_PULLDN_DP |
1275                         COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS;
1276         writel(val, base + UTMIP_MISC_CFG0);
1277         val = readl(base + UTMIP_MISC_CFG0);
1278         val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1279         if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
1280                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
1281         else
1282                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
1283         writel(val, base + UTMIP_MISC_CFG0);
1284         udelay(1);
1285
1286         val = readl(base + UTMIP_MISC_CFG0);
1287         val |= UTMIP_DPDM_OBSERVE;
1288         writel(val, base + UTMIP_MISC_CFG0);
1289         udelay(10);
1290         DBG("%s(%d) Enable OBS bus\n", __func__, __LINE__);
1291         PHY_DBG("ENABLE_OBS_BUS\n");
1292 }
1293
1294 static int utmi_phy_disable_obs_bus(struct tegra_usb_phy *phy)
1295 {
1296         unsigned long val;
1297         void __iomem *base = phy->regs;
1298         unsigned long flags;
1299
1300         /* check if OBS bus is already enabled */
1301         val = readl(base + UTMIP_MISC_CFG0);
1302         if (val & UTMIP_DPDM_OBSERVE) {
1303                 PHY_DBG("DISABLE_OBS_BUS\n");
1304
1305                 /* disable ALL interrupts on current CPU */
1306                 local_irq_save(flags);
1307
1308                 /* Change the UTMIP OBS bus to drive SE0 */
1309                 val = readl(base + UTMIP_MISC_CFG0);
1310                 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1311                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_SE0;
1312                 writel(val, base + UTMIP_MISC_CFG0);
1313
1314                 /* Wait for 3us(2 LS bit times) */
1315                 udelay(3);
1316
1317                 /* Release UTMIP OBS bus */
1318                 val = readl(base + UTMIP_MISC_CFG0);
1319                 val &= ~UTMIP_DPDM_OBSERVE;
1320                 writel(val, base + UTMIP_MISC_CFG0);
1321
1322                 /* Release DP/DM pulldown for Host mode */
1323                 val = readl(base + UTMIP_MISC_CFG0);
1324                 val &= ~(FORCE_PULLDN_DM | FORCE_PULLDN_DP |
1325                                 COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS);
1326                 writel(val, base + UTMIP_MISC_CFG0);
1327
1328                 val = readl(base + USB_USBCMD);
1329                 val |= USB_USBCMD_RS;
1330                 writel(val, base + USB_USBCMD);
1331
1332                 /* restore ALL interrupts on current CPU */
1333                 local_irq_restore(flags);
1334
1335                 if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
1336                                                          USB_USBCMD_RS, 2000)) {
1337                         pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
1338                         return -ETIMEDOUT;
1339                 }
1340         }
1341         return 0;
1342 }
1343
1344 static int utmi_phy_post_resume(struct tegra_usb_phy *phy)
1345 {
1346         unsigned long val;
1347         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1348         unsigned  int inst = phy->inst;
1349
1350         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1351         val = readl(pmc_base + PMC_SLEEP_CFG);
1352         /* if PMC is not disabled by now then disable it */
1353         if (val & UTMIP_MASTER_ENABLE(inst)) {
1354                 utmip_phy_disable_pmc_bus_ctrl(phy);
1355         }
1356
1357         utmi_phy_disable_obs_bus(phy);
1358
1359         return 0;
1360 }
1361
1362 static int phy_post_suspend(struct tegra_usb_phy *phy)
1363 {
1364
1365         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1366         /* Need a 4ms delay for controller to suspend */
1367         mdelay(4);
1368
1369         return 0;
1370
1371 }
1372
1373 static int utmi_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1374 {
1375         unsigned long val;
1376         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1377         void __iomem *base = phy->regs;
1378         unsigned  int inst = phy->inst;
1379
1380         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1381         phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
1382                         HOSTPC1_DEVLC_PSPD_MASK;
1383
1384         if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH) {
1385                 /* Disable interrupts */
1386                 writel(0, base + USB_USBINTR);
1387                 /* Clear the run bit to stop SOFs - 2LS WAR */
1388                 val = readl(base + USB_USBCMD);
1389                 val &= ~USB_USBCMD_RS;
1390                 writel(val, base + USB_USBCMD);
1391                 if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
1392                                                          USB_USBSTS_HCH, 2000)) {
1393                         pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
1394                 }
1395         }
1396
1397         val = readl(pmc_base + PMC_SLEEP_CFG);
1398         if (val & UTMIP_MASTER_ENABLE(inst)) {
1399                 if (!remote_wakeup)
1400                         utmip_phy_disable_pmc_bus_ctrl(phy);
1401         } else {
1402                 utmi_phy_enable_obs_bus(phy);
1403         }
1404
1405         return 0;
1406 }
1407
1408 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
1409 {
1410         unsigned long val;
1411         void __iomem *base = phy->regs;
1412
1413         PHY_DBG("%s(%d) inst:[%d] BEGIN\n", __func__, __LINE__, phy->inst);
1414         if (!phy->phy_clk_on) {
1415                 PHY_DBG("%s(%d) inst:[%d] phy clk is already off\n",
1416                                         __func__, __LINE__, phy->inst);
1417                 return 0;
1418         }
1419
1420         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1421                 utmip_powerdown_pmc_wake_detect(phy);
1422
1423                 val = readl(base + USB_SUSP_CTRL);
1424                 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
1425                 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
1426                 writel(val, base + USB_SUSP_CTRL);
1427
1428                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1429                 val |= UTMIP_PD_CHRG;
1430                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1431         } else {
1432                 phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
1433                                 HOSTPC1_DEVLC_PSPD_MASK;
1434
1435                 /* Disable interrupts */
1436                 writel(0, base + USB_USBINTR);
1437
1438                 /* Clear the run bit to stop SOFs - 2LS WAR */
1439                 val = readl(base + USB_USBCMD);
1440                 val &= ~USB_USBCMD_RS;
1441                 writel(val, base + USB_USBCMD);
1442
1443                 if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
1444                                                          USB_USBSTS_HCH, 2000)) {
1445                         pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
1446                 }
1447                 utmip_setup_pmc_wake_detect(phy);
1448         }
1449
1450         if (!phy->pdata->u_data.host.hot_plug) {
1451                 val = readl(base + UTMIP_XCVR_CFG0);
1452                 val |= (UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
1453                          UTMIP_FORCE_PDZI_POWERDOWN);
1454                 writel(val, base + UTMIP_XCVR_CFG0);
1455         }
1456
1457         val = readl(base + UTMIP_XCVR_CFG1);
1458         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1459                    UTMIP_FORCE_PDDR_POWERDOWN;
1460         writel(val, base + UTMIP_XCVR_CFG1);
1461
1462         val = readl(base + UTMIP_BIAS_CFG1);
1463         val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
1464         writel(val, base + UTMIP_BIAS_CFG1);
1465
1466         utmi_phy_pad_power_off(phy);
1467
1468         if (phy->pdata->u_data.host.hot_plug) {
1469                 bool enable_hotplug = true;
1470                 /* if it is OTG port then make sure to enable hot-plug feature
1471                    only if host adaptor is connected, i.e id is low */
1472                 if (phy->pdata->port_otg) {
1473                         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1474                         enable_hotplug = (val & USB_ID_STATUS) ? false : true;
1475                 }
1476                 if (enable_hotplug) {
1477                         val = readl(base + USB_PORTSC);
1478                         val |= USB_PORTSC_WKCN;
1479                         writel(val, base + USB_PORTSC);
1480
1481                         val = readl(base + USB_SUSP_CTRL);
1482                         val |= USB_PHY_CLK_VALID_INT_ENB;
1483                         writel(val, base + USB_SUSP_CTRL);
1484                 } else {
1485                         /* Disable PHY clock valid interrupts while going into suspend*/
1486                         val = readl(base + USB_SUSP_CTRL);
1487                         val &= ~USB_PHY_CLK_VALID_INT_ENB;
1488                         writel(val, base + USB_SUSP_CTRL);
1489                 }
1490         }
1491
1492         val = readl(base + HOSTPC1_DEVLC);
1493         val |= HOSTPC1_DEVLC_PHCD;
1494         writel(val, base + HOSTPC1_DEVLC);
1495
1496         if (!phy->pdata->u_data.host.hot_plug) {
1497                 val = readl(base + USB_SUSP_CTRL);
1498                 val |= UTMIP_RESET;
1499                 writel(val, base + USB_SUSP_CTRL);
1500         }
1501
1502         phy->phy_clk_on = false;
1503         phy->hw_accessible = false;
1504
1505         PHY_DBG("%s(%d) inst:[%d] END\n", __func__, __LINE__, phy->inst);
1506
1507         return 0;
1508 }
1509
1510
1511 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
1512 {
1513         unsigned long val;
1514         void __iomem *base = phy->regs;
1515         struct tegra_utmi_config *config = &phy->pdata->u_cfg.utmi;
1516
1517         PHY_DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1518         if (phy->phy_clk_on) {
1519                 PHY_DBG("%s(%d) inst:[%d] phy clk is already On\n",
1520                                         __func__, __LINE__, phy->inst);
1521                 return 0;
1522         }
1523         val = readl(base + USB_SUSP_CTRL);
1524         val |= UTMIP_RESET;
1525         writel(val, base + USB_SUSP_CTRL);
1526
1527         val = readl(base + UTMIP_TX_CFG0);
1528         val |= UTMIP_FS_PREABMLE_J;
1529         writel(val, base + UTMIP_TX_CFG0);
1530
1531         val = readl(base + UTMIP_HSRX_CFG0);
1532         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
1533         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
1534         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
1535         writel(val, base + UTMIP_HSRX_CFG0);
1536
1537         val = readl(base + UTMIP_HSRX_CFG1);
1538         val &= ~UTMIP_HS_SYNC_START_DLY(~0);
1539         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
1540         writel(val, base + UTMIP_HSRX_CFG1);
1541
1542         val = readl(base + UTMIP_DEBOUNCE_CFG0);
1543         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
1544         val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
1545         writel(val, base + UTMIP_DEBOUNCE_CFG0);
1546
1547         val = readl(base + UTMIP_MISC_CFG0);
1548         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
1549         writel(val, base + UTMIP_MISC_CFG0);
1550
1551         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1552                 val = readl(base + USB_SUSP_CTRL);
1553                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
1554                 writel(val, base + USB_SUSP_CTRL);
1555
1556                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1557                 val &= ~UTMIP_PD_CHRG;
1558                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1559         } else {
1560                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1561                 val |= UTMIP_PD_CHRG;
1562                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1563         }
1564
1565         utmi_phy_pad_power_on(phy);
1566
1567         val = readl(base + UTMIP_XCVR_CFG0);
1568         val &= ~(UTMIP_XCVR_LSBIAS_SEL | UTMIP_FORCE_PD_POWERDOWN |
1569                  UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN |
1570                  UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_LSFSLEW(~0) |
1571                  UTMIP_XCVR_LSRSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
1572         val |= UTMIP_XCVR_SETUP(phy->utmi_xcvr_setup);
1573         val |= UTMIP_XCVR_SETUP_MSB(XCVR_SETUP_MSB_CALIB(phy->utmi_xcvr_setup));
1574         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
1575         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
1576         if (!config->xcvr_use_lsb)
1577                 val |= UTMIP_XCVR_HSSLEW_MSB(0x8);
1578         writel(val, base + UTMIP_XCVR_CFG0);
1579
1580         val = readl(base + UTMIP_XCVR_CFG1);
1581         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1582                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
1583         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
1584         writel(val, base + UTMIP_XCVR_CFG1);
1585
1586         val = readl(base + UTMIP_BIAS_CFG1);
1587         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
1588         val |= UTMIP_BIAS_PDTRK_COUNT(phy->freq->pdtrk_count);
1589         writel(val, base + UTMIP_BIAS_CFG1);
1590
1591         val = readl(base + UTMIP_SPARE_CFG0);
1592         val &= ~FUSE_SETUP_SEL;
1593         val |= FUSE_ATERM_SEL;
1594         writel(val, base + UTMIP_SPARE_CFG0);
1595
1596         val = readl(base + USB_SUSP_CTRL);
1597         val |= UTMIP_PHY_ENABLE;
1598         writel(val, base + USB_SUSP_CTRL);
1599
1600         val = readl(base + USB_SUSP_CTRL);
1601         val &= ~UTMIP_RESET;
1602         writel(val, base + USB_SUSP_CTRL);
1603
1604         val = readl(base + HOSTPC1_DEVLC);
1605         val &= ~HOSTPC1_DEVLC_PHCD;
1606         writel(val, base + HOSTPC1_DEVLC);
1607
1608         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1609                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500))
1610                 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
1611
1612         utmi_phy_enable_trking_data(phy);
1613
1614         if (phy->inst == 2)
1615                 writel(0, base + ICUSB_CTRL);
1616
1617         val = readl(base + USB_USBMODE);
1618         val &= ~USB_USBMODE_MASK;
1619         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST)
1620                 val |= USB_USBMODE_HOST;
1621         else
1622                 val |= USB_USBMODE_DEVICE;
1623         writel(val, base + USB_USBMODE);
1624
1625         val = readl(base + HOSTPC1_DEVLC);
1626         val &= ~HOSTPC1_DEVLC_PTS(~0);
1627         val |= HOSTPC1_DEVLC_STS;
1628         writel(val, base + HOSTPC1_DEVLC);
1629
1630         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE)
1631                 utmip_powerup_pmc_wake_detect(phy);
1632         phy->phy_clk_on = true;
1633         phy->hw_accessible = true;
1634         PHY_DBG("%s(%d) End inst:[%d]\n", __func__, __LINE__, phy->inst);
1635         return 0;
1636 }
1637
1638 static void utmi_phy_restore_start(struct tegra_usb_phy *phy)
1639 {
1640         unsigned long val;
1641         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1642         int inst = phy->inst;
1643
1644         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1645         val = readl(pmc_base + UTMIP_UHSIC_STATUS);
1646         /* Check whether we wake up from the remote resume.
1647            For lp1 case, pmc is not responsible for waking the
1648            system, it's the flow controller and hence
1649            UTMIP_WALK_PTR_VAL(inst) will return 0.
1650            Also, for lp1 case phy->remote_wakeup will already be set
1651            to true by utmi_phy_irq() when the remote wakeup happens.
1652            Hence change the logic in the else part to enter only
1653            if phy->remote_wakeup is not set to true by the
1654            utmi_phy_irq(). */
1655         if (UTMIP_WALK_PTR_VAL(inst) & val) {
1656                 phy->remote_wakeup = true;
1657         } else if(!phy->remote_wakeup) {
1658                 if (!((UTMIP_USBON_VAL(phy->inst) |
1659                         UTMIP_USBOP_VAL(phy->inst)) & val)) {
1660                                 utmip_phy_disable_pmc_bus_ctrl(phy);
1661                 }
1662         }
1663         utmi_phy_enable_obs_bus(phy);
1664 }
1665
1666 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
1667 {
1668         unsigned long val;
1669         void __iomem *base = phy->regs;
1670         int wait_time_us = 25000; /* FPR should be set by this time */
1671
1672         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1673         /* check whether we wake up from the remote resume */
1674         if (phy->remote_wakeup) {
1675                 /* wait until SUSPEND and RESUME bit is cleared on remote resume */
1676                 do {
1677                         val = readl(base + USB_PORTSC);
1678                         udelay(1);
1679                         if (wait_time_us == 0) {
1680                                 PHY_DBG("%s PMC REMOTE WAKEUP FPR timeout val = 0x%x instance = %d\n", __func__, val, phy->inst);
1681                                 utmip_phy_disable_pmc_bus_ctrl(phy);
1682                                 utmi_phy_post_resume(phy);
1683                                 return;
1684                         }
1685                         wait_time_us--;
1686                 } while (val & (USB_PORTSC_RESUME | USB_PORTSC_SUSP));
1687
1688                 /* wait for 25 ms to port resume complete */
1689                 msleep(25);
1690                 /* disable PMC master control */
1691                 utmip_phy_disable_pmc_bus_ctrl(phy);
1692
1693                 /* Clear PCI and SRI bits to avoid an interrupt upon resume */
1694                 val = readl(base + USB_USBSTS);
1695                 writel(val, base + USB_USBSTS);
1696                 /* wait to avoid SOF if there is any */
1697                 if (usb_phy_reg_status_wait(base + USB_USBSTS,
1698                         USB_USBSTS_SRI, USB_USBSTS_SRI, 2500) < 0) {
1699                         pr_err("%s: timeout waiting for SOF\n", __func__);
1700                 }
1701                 utmi_phy_post_resume(phy);
1702         }
1703 }
1704
1705 static int utmi_phy_resume(struct tegra_usb_phy *phy)
1706 {
1707         int status = 0;
1708         unsigned long val;
1709         void __iomem *base = phy->regs;
1710
1711         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1712         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) {
1713                 if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
1714                         utmi_phy_restore_start(phy);
1715                         usb_phy_bringup_host_controller(phy);
1716                         utmi_phy_restore_end(phy);
1717                 } else {
1718                         /* device is plugged in when system is in LP0 */
1719                         /* bring up the controller from LP0*/
1720                         val = readl(base + USB_USBCMD);
1721                         val |= USB_CMD_RESET;
1722                         writel(val, base + USB_USBCMD);
1723
1724                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1725                                 USB_CMD_RESET, 0, 2500) < 0) {
1726                                 pr_err("%s: timeout waiting for reset\n", __func__);
1727                         }
1728
1729                         val = readl(base + USB_USBMODE);
1730                         val &= ~USB_USBMODE_MASK;
1731                         val |= USB_USBMODE_HOST;
1732                         writel(val, base + USB_USBMODE);
1733
1734                         val = readl(base + HOSTPC1_DEVLC);
1735                         val &= ~HOSTPC1_DEVLC_PTS(~0);
1736                         val |= HOSTPC1_DEVLC_STS;
1737                         writel(val, base + HOSTPC1_DEVLC);
1738
1739                         writel(USB_USBCMD_RS, base + USB_USBCMD);
1740
1741                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1742                                 USB_USBCMD_RS, USB_USBCMD_RS, 2500) < 0) {
1743                                 pr_err("%s: timeout waiting for run bit\n", __func__);
1744                         }
1745
1746                         /* Enable Port Power */
1747                         val = readl(base + USB_PORTSC);
1748                         val |= USB_PORTSC_PP;
1749                         writel(val, base + USB_PORTSC);
1750                         udelay(10);
1751
1752                         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1753                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1754                 }
1755         }
1756
1757         return status;
1758 }
1759
1760 static bool utmi_phy_charger_detect(struct tegra_usb_phy *phy)
1761 {
1762         unsigned long val;
1763         void __iomem *base = phy->regs;
1764         bool status;
1765
1766         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1767         if (phy->pdata->op_mode != TEGRA_USB_OPMODE_DEVICE) {
1768                 /* Charger detection is not there for ULPI
1769                  * return Charger not available */
1770                 return false;
1771         }
1772
1773         /* Enable charger detection logic */
1774         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1775         val |= UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN;
1776         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1777
1778         /* Source should be on for 100 ms as per USB charging spec */
1779         msleep(TDP_SRC_ON_MS);
1780
1781         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1782         /* If charger is not connected disable the interrupt */
1783         val &= ~VDAT_DET_INT_EN;
1784         val |= VDAT_DET_CHG_DET;
1785         writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
1786
1787         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1788         if (val & VDAT_DET_STS)
1789                 status = true;
1790         else
1791                 status = false;
1792
1793         /* Disable charger detection logic */
1794         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1795         val &= ~(UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN);
1796         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1797
1798         /* Delay of 40 ms before we pull the D+ as per battery charger spec */
1799         msleep(TDPSRC_CON_MS);
1800
1801         return status;
1802 }
1803
1804 static void uhsic_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
1805 {
1806         unsigned long val;
1807         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1808
1809         /* turn on pad detectors for HSIC*/
1810         val = readl(pmc_base + PMC_USB_AO);
1811         val &= ~(HSIC_RESERVED_P0 | STROBE_VAL_PD_P0 | DATA_VAL_PD_P0);
1812         writel(val, pmc_base + PMC_USB_AO);
1813
1814         /* Disable PMC master mode by clearing MASTER_EN */
1815         val = readl(pmc_base + PMC_SLEEP_CFG);
1816         val &= ~(UHSIC_MASTER_ENABLE_P0);
1817         writel(val, pmc_base + PMC_SLEEP_CFG);
1818         mdelay(1);
1819 }
1820
1821 static void uhsic_setup_pmc_wake_detect(struct tegra_usb_phy *phy)
1822 {
1823         unsigned long val;
1824         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1825         void __iomem *base = phy->regs;
1826         bool port_connected;
1827
1828         DBG("%s:%d\n", __func__, __LINE__);
1829
1830         /* check for port connect status */
1831         val = readl(base + USB_PORTSC);
1832         port_connected = val & USB_PORTSC_CCS;
1833
1834         if (!port_connected)
1835                 return;
1836
1837         /*Set PMC MASTER bits to do the following
1838         * a. Take over the hsic drivers
1839         * b. set up such that it will take over resume
1840         *        if remote wakeup is detected
1841         * Prepare PMC to take over suspend-wake detect-drive resume until USB
1842         * controller ready
1843         */
1844
1845         /* disable master enable in PMC */
1846         val = readl(pmc_base + PMC_SLEEP_CFG);
1847         val &= ~UHSIC_MASTER_ENABLE_P0;
1848         writel(val, pmc_base + PMC_SLEEP_CFG);
1849
1850         /* UTMIP_PWR_PX=1 for power savings mode */
1851         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
1852         val |= UHSIC_PWR;
1853         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
1854
1855
1856         /* Enable which type of event can trigger a walk,
1857         * in this case usb_line_wake */
1858         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
1859         val |= UHSIC_LINEVAL_WALK_EN;
1860         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
1861
1862         /* program walk sequence, maintain a J, followed by a driven K
1863         * to signal a resume once an wake event is detected */
1864
1865         val = readl(pmc_base + PMC_SLEEPWALK_UHSIC);
1866
1867         val &= ~UHSIC_DATA_RPU_A;
1868         val |=  UHSIC_DATA_RPD_A;
1869         val &= ~UHSIC_STROBE_RPD_A;
1870         val |=  UHSIC_STROBE_RPU_A;
1871         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1872
1873         val &= ~UHSIC_DATA_RPD_B;
1874         val |=  UHSIC_DATA_RPU_B;
1875         val &= ~UHSIC_STROBE_RPU_B;
1876         val |=  UHSIC_STROBE_RPD_B;
1877         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1878
1879         val &= ~UHSIC_DATA_RPD_C;
1880         val |=  UHSIC_DATA_RPU_C;
1881         val &= ~UHSIC_STROBE_RPU_C;
1882         val |=  UHSIC_STROBE_RPD_C;
1883         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1884
1885         val &= ~UHSIC_DATA_RPD_D;
1886         val |=  UHSIC_DATA_RPU_D;
1887         val &= ~UHSIC_STROBE_RPU_D;
1888         val |=  UHSIC_STROBE_RPD_D;
1889         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1890
1891         /* turn on pad detectors */
1892         val = readl(pmc_base + PMC_USB_AO);
1893         val &= ~(STROBE_VAL_PD_P0 | DATA_VAL_PD_P0);
1894         writel(val, pmc_base + PMC_USB_AO);
1895         /* Add small delay before usb detectors provide stable line values */
1896         udelay(1);
1897
1898         phy->remote_wakeup = false;
1899
1900         /* Turn over pad configuration to PMC  for line wake events*/
1901         val = readl(pmc_base + PMC_SLEEP_CFG);
1902         val &= ~UHSIC_WAKE_VAL(~0);
1903         val |= UHSIC_WAKE_VAL(WAKE_VAL_SD10);
1904         val |= UHSIC_MASTER_ENABLE;
1905         writel(val, pmc_base + PMC_SLEEP_CFG);
1906
1907         val = readl(base + UHSIC_PMC_WAKEUP0);
1908         val |= EVENT_INT_ENB;
1909         writel(val, base + UHSIC_PMC_WAKEUP0);
1910
1911         DBG("%s:PMC enabled for HSIC remote wakeup\n", __func__);
1912 }
1913
1914 static void uhsic_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy)
1915 {
1916         unsigned long val;
1917         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1918         void __iomem *base = phy->regs;
1919
1920         DBG("%s (%d)\n", __func__, __LINE__);
1921         val = readl(pmc_base + PMC_SLEEP_CFG);
1922         val &= ~UHSIC_WAKE_VAL(0x0);
1923         val |= UHSIC_WAKE_VAL(WAKE_VAL_NONE);
1924         writel(val, pmc_base + PMC_SLEEP_CFG);
1925
1926         val = readl(pmc_base + PMC_TRIGGERS);
1927         val |= UHSIC_CLR_WAKE_ALARM_P0 | UHSIC_CLR_WALK_PTR_P0;
1928         writel(val, pmc_base + PMC_TRIGGERS);
1929
1930         val = readl(base + UHSIC_PMC_WAKEUP0);
1931         val &= ~EVENT_INT_ENB;
1932         writel(val, base + UHSIC_PMC_WAKEUP0);
1933
1934         /* Disable PMC master mode by clearing MASTER_EN */
1935         val = readl(pmc_base + PMC_SLEEP_CFG);
1936         val &= ~(UHSIC_MASTER_ENABLE);
1937         writel(val, pmc_base + PMC_SLEEP_CFG);
1938
1939         /* turn off pad detectors */
1940         val = readl(pmc_base + PMC_USB_AO);
1941         val |= (STROBE_VAL_PD_P0 | DATA_VAL_PD_P0);
1942         writel(val, pmc_base + PMC_USB_AO);
1943
1944         phy->remote_wakeup = false;
1945 }
1946
1947 static bool uhsic_phy_remotewake_detected(struct tegra_usb_phy *phy)
1948 {
1949         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1950         void __iomem *base = phy->regs;
1951         u32 val;
1952
1953         val = readl(base + UHSIC_PMC_WAKEUP0);
1954         if (val & EVENT_INT_ENB) {
1955                 val = readl(pmc_base + UTMIP_UHSIC_STATUS);
1956                 if (UHSIC_WAKE_ALARM & val) {
1957                         val = readl(pmc_base + PMC_SLEEP_CFG);
1958                         val &= ~UHSIC_WAKE_VAL(0x0);
1959                         val |= UHSIC_WAKE_VAL(WAKE_VAL_NONE);
1960                         writel(val, pmc_base + PMC_SLEEP_CFG);
1961
1962                         val = readl(pmc_base + PMC_TRIGGERS);
1963                         val |= UHSIC_CLR_WAKE_ALARM_P0 | UHSIC_CLR_WALK_PTR_P0;
1964                         writel(val, pmc_base + PMC_TRIGGERS);
1965
1966                         val = readl(base + UHSIC_PMC_WAKEUP0);
1967                         val &= ~EVENT_INT_ENB;
1968                         writel(val, base + UHSIC_PMC_WAKEUP0);
1969                         phy->remote_wakeup = true;
1970                         DBG("%s:PMC remote wakeup detected for HSIC\n", __func__);
1971                         return true;
1972                 }
1973         }
1974         return false;
1975 }
1976
1977 static int uhsic_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1978 {
1979         DBG("%s(%d)\n", __func__, __LINE__);
1980
1981         if (!remote_wakeup)
1982                 usb_phy_wait_for_sof(phy);
1983
1984         return 0;
1985 }
1986
1987 static int uhsic_phy_post_resume(struct tegra_usb_phy *phy)
1988 {
1989         unsigned long val;
1990         void __iomem *base = phy->regs;
1991
1992         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1993         val = readl(base + USB_TXFILLTUNING);
1994         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
1995                 val = USB_FIFO_TXFILL_THRES(0x10);
1996                 writel(val, base + USB_TXFILLTUNING);
1997         }
1998
1999         return 0;
2000 }
2001
2002 static void uhsic_phy_restore_start(struct tegra_usb_phy *phy)
2003 {
2004         unsigned long val;
2005         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
2006         void __iomem *base = phy->regs;
2007
2008         val = readl(pmc_base + UTMIP_UHSIC_STATUS);
2009
2010         /* check whether we wake up from the remote resume */
2011         if (UHSIC_WALK_PTR_VAL & val) {
2012                 phy->remote_wakeup = true;
2013         } else {
2014                 if (!((UHSIC_STROBE_VAL_P0 | UHSIC_DATA_VAL_P0) & val)) {
2015                                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2016                 } else {
2017                         DBG("%s(%d): setting pretend connect\n", __func__, __LINE__);
2018                         val = readl(base + UHSIC_CMD_CFG0);
2019                         val |= UHSIC_PRETEND_CONNECT_DETECT;
2020                         writel(val, base + UHSIC_CMD_CFG0);
2021                 }
2022         }
2023 }
2024
2025 static void uhsic_phy_restore_end(struct tegra_usb_phy *phy)
2026 {
2027
2028         unsigned long val;
2029         void __iomem *base = phy->regs;
2030         int wait_time_us = 3000; /* FPR should be set by this time */
2031
2032         DBG("%s(%d)\n", __func__, __LINE__);
2033
2034         /* check whether we wake up from the remote resume */
2035         if (phy->remote_wakeup) {
2036                 /* wait until FPR bit is set automatically on remote resume */
2037                 do {
2038                         val = readl(base + USB_PORTSC);
2039                         udelay(1);
2040                         if (wait_time_us == 0) {
2041                                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2042                                 uhsic_phy_post_resume(phy);
2043                                 return;
2044                         }
2045                         wait_time_us--;
2046                 } while (!(val & USB_PORTSC_RESUME));
2047                 /* wait for 25 ms to port resume complete */
2048                 msleep(25);
2049                 /* disable PMC master control */
2050                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2051
2052                 /* Clear PCI and SRI bits to avoid an interrupt upon resume */
2053                 val = readl(base + USB_USBSTS);
2054                 writel(val, base + USB_USBSTS);
2055                 /* wait to avoid SOF if there is any */
2056                 if (usb_phy_reg_status_wait(base + USB_USBSTS,
2057                         USB_USBSTS_SRI, USB_USBSTS_SRI, 2500)) {
2058                         pr_warn("%s: timeout waiting for SOF\n", __func__);
2059                 }
2060                 uhsic_phy_post_resume(phy);
2061         } else {
2062                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2063         }
2064
2065         /* Set RUN bit */
2066         val = readl(base + USB_USBCMD);
2067         val |= USB_USBCMD_RS;
2068         writel(val, base + USB_USBCMD);
2069         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2070                                                  USB_USBCMD_RS, 2000)) {
2071                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2072                 return;
2073         }
2074 }
2075
2076 static int uhsic_phy_open(struct tegra_usb_phy *phy)
2077 {
2078         unsigned long parent_rate;
2079         int i;
2080
2081         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2082         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
2083         for (i = 0; i < ARRAY_SIZE(uhsic_freq_table); i++) {
2084                 if (uhsic_freq_table[i].freq == parent_rate) {
2085                         phy->freq = &uhsic_freq_table[i];
2086                         break;
2087                 }
2088         }
2089         if (!phy->freq) {
2090                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
2091                 return -EINVAL;
2092         }
2093
2094         uhsic_powerup_pmc_wake_detect(phy);
2095
2096         return 0;
2097 }
2098
2099 static int uhsic_phy_irq(struct tegra_usb_phy *phy)
2100 {
2101         usb_phy_fence_read(phy);
2102         /* check if there is any remote wake event */
2103         if (uhsic_phy_remotewake_detected(phy))
2104                 pr_info("%s: uhsic remote wake detected\n", __func__);
2105         return IRQ_HANDLED;
2106 }
2107
2108 static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
2109 {
2110         unsigned long val;
2111         void __iomem *base = phy->regs;
2112         struct tegra_hsic_config *config = &phy->pdata->u_cfg.hsic;
2113
2114         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2115
2116         if (phy->phy_clk_on) {
2117                 DBG("%s(%d) inst:[%d] phy clk is already On\n",
2118                                         __func__, __LINE__, phy->inst);
2119                 return 0;
2120         }
2121
2122         val = readl(base + UHSIC_PADS_CFG1);
2123         val &= ~(UHSIC_PD_BG | UHSIC_PD_TRK | UHSIC_PD_RX |
2124                         UHSIC_PD_ZI | UHSIC_RPD_DATA | UHSIC_RPD_STROBE);
2125         val |= (UHSIC_RX_SEL | UHSIC_PD_TX);
2126         writel(val, base + UHSIC_PADS_CFG1);
2127
2128         val = readl(base + USB_SUSP_CTRL);
2129         val |= UHSIC_RESET;
2130         writel(val, base + USB_SUSP_CTRL);
2131         udelay(1);
2132
2133         val = readl(base + USB_SUSP_CTRL);
2134         val |= UHSIC_PHY_ENABLE;
2135         writel(val, base + USB_SUSP_CTRL);
2136
2137         val = readl(base + UHSIC_HSRX_CFG0);
2138         val |= UHSIC_IDLE_WAIT(config->idle_wait_delay);
2139         val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(config->elastic_underrun_limit);
2140         val |= UHSIC_ELASTIC_OVERRUN_LIMIT(config->elastic_overrun_limit);
2141         writel(val, base + UHSIC_HSRX_CFG0);
2142
2143         val = readl(base + UHSIC_HSRX_CFG1);
2144         val |= UHSIC_HS_SYNC_START_DLY(config->sync_start_delay);
2145         writel(val, base + UHSIC_HSRX_CFG1);
2146
2147         /* WAR HSIC TX */
2148         val = readl(base + UHSIC_TX_CFG0);
2149         val &= ~UHSIC_HS_READY_WAIT_FOR_VALID;
2150         writel(val, base + UHSIC_TX_CFG0);
2151
2152         val = readl(base + UHSIC_MISC_CFG0);
2153         val |= UHSIC_SUSPEND_EXIT_ON_EDGE;
2154         /* Disable generic bus reset, to allow AP30 specific bus reset*/
2155         val |= UHSIC_DISABLE_BUSRESET;
2156         writel(val, base + UHSIC_MISC_CFG0);
2157
2158         val = readl(base + UHSIC_MISC_CFG1);
2159         val |= UHSIC_PLLU_STABLE_COUNT(phy->freq->stable_count);
2160         writel(val, base + UHSIC_MISC_CFG1);
2161
2162         val = readl(base + UHSIC_PLL_CFG1);
2163         val |= UHSIC_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
2164         val |= UHSIC_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count);
2165         writel(val, base + UHSIC_PLL_CFG1);
2166
2167         val = readl(base + USB_SUSP_CTRL);
2168         val &= ~(UHSIC_RESET);
2169         writel(val, base + USB_SUSP_CTRL);
2170         udelay(1);
2171
2172         val = readl(base + UHSIC_PADS_CFG1);
2173         val &= ~(UHSIC_PD_TX);
2174         writel(val, base + UHSIC_PADS_CFG1);
2175
2176         val = readl(base + USB_USBMODE);
2177         val |= USB_USBMODE_HOST;
2178         writel(val, base + USB_USBMODE);
2179
2180         /* Change the USB controller PHY type to HSIC */
2181         val = readl(base + HOSTPC1_DEVLC);
2182         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
2183         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2184         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
2185         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2186         val &= ~HOSTPC1_DEVLC_STS;
2187         writel(val, base + HOSTPC1_DEVLC);
2188
2189         val = readl(base + USB_TXFILLTUNING);
2190         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
2191                 val = USB_FIFO_TXFILL_THRES(0x10);
2192                 writel(val, base + USB_TXFILLTUNING);
2193         }
2194
2195         val = readl(base + USB_PORTSC);
2196         val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN);
2197         writel(val, base + USB_PORTSC);
2198
2199         val = readl(base + UHSIC_PADS_CFG0);
2200         val &= ~(UHSIC_TX_RTUNEN);
2201         /* set Rtune impedance to 50 ohm */
2202         val |= UHSIC_TX_RTUNE(8);
2203         writel(val, base + UHSIC_PADS_CFG0);
2204
2205         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
2206                                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500)) {
2207                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2208                 return -ETIMEDOUT;
2209         }
2210
2211         phy->phy_clk_on = true;
2212         phy->hw_accessible = true;
2213
2214         return 0;
2215 }
2216
2217 static int uhsic_phy_power_off(struct tegra_usb_phy *phy)
2218 {
2219         unsigned long val;
2220         void __iomem *base = phy->regs;
2221
2222         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2223         if (!phy->phy_clk_on) {
2224                 DBG("%s(%d) inst:[%d] phy clk is already off\n",
2225                                         __func__, __LINE__, phy->inst);
2226                 return 0;
2227         }
2228
2229         phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
2230                         HOSTPC1_DEVLC_PSPD_MASK;
2231
2232         /* Disable interrupts */
2233         writel(0, base + USB_USBINTR);
2234
2235         uhsic_setup_pmc_wake_detect(phy);
2236
2237         val = readl(base + HOSTPC1_DEVLC);
2238         val |= HOSTPC1_DEVLC_PHCD;
2239         writel(val, base + HOSTPC1_DEVLC);
2240
2241         phy->phy_clk_on = false;
2242         phy->hw_accessible = false;
2243
2244         return 0;
2245 }
2246
2247 static int uhsic_phy_bus_port_power(struct tegra_usb_phy *phy)
2248 {
2249         unsigned long val;
2250         void __iomem *base = phy->regs;
2251
2252         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2253
2254         val = readl(base + USB_USBMODE);
2255         val |= USB_USBMODE_HOST;
2256         writel(val, base + USB_USBMODE);
2257
2258         /* Change the USB controller PHY type to HSIC */
2259         val = readl(base + HOSTPC1_DEVLC);
2260         val &= ~(HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK));
2261         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2262         val &= ~(HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK));
2263         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2264         writel(val, base + HOSTPC1_DEVLC);
2265
2266         val = readl(base + UHSIC_MISC_CFG0);
2267         val |= UHSIC_DETECT_SHORT_CONNECT;
2268         writel(val, base + UHSIC_MISC_CFG0);
2269         udelay(1);
2270
2271         val = readl(base + UHSIC_MISC_CFG0);
2272         val |= UHSIC_FORCE_XCVR_MODE;
2273         writel(val, base + UHSIC_MISC_CFG0);
2274
2275         val = readl(base + UHSIC_PADS_CFG1);
2276         val &= ~UHSIC_RPD_STROBE;
2277         writel(val, base + UHSIC_PADS_CFG1);
2278
2279         if (phy->pdata->ops && phy->pdata->ops->port_power)
2280                 phy->pdata->ops->port_power();
2281
2282         if (usb_phy_reg_status_wait(base + UHSIC_STAT_CFG0,
2283                         UHSIC_CONNECT_DETECT, UHSIC_CONNECT_DETECT, 25000)) {
2284                 pr_err("%s: timeout waiting for UHSIC_CONNECT_DETECT\n",
2285                                                                 __func__);
2286                 return -ETIMEDOUT;
2287         }
2288
2289         return 0;
2290 }
2291
2292 static int uhsic_phy_bus_reset(struct tegra_usb_phy *phy)
2293 {
2294         unsigned long val;
2295         void __iomem *base = phy->regs;
2296
2297         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2298
2299         /* Change the USB controller PHY type to HSIC */
2300         val = readl(base + HOSTPC1_DEVLC);
2301         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
2302         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2303         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
2304         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2305         val &= ~HOSTPC1_DEVLC_STS;
2306         writel(val, base + HOSTPC1_DEVLC);
2307         /* wait here, otherwise HOSTPC1_DEVLC_PSPD will timeout */
2308         mdelay(5);
2309
2310         val = readl(base + USB_PORTSC);
2311         val |= USB_PORTSC_PTC(5);
2312         writel(val, base + USB_PORTSC);
2313         udelay(2);
2314
2315         val = readl(base + USB_PORTSC);
2316         val &= ~(USB_PORTSC_PTC(~0));
2317         writel(val, base + USB_PORTSC);
2318         udelay(2);
2319
2320         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_LS(0),
2321                                                  0, 2000)) {
2322                 pr_err("%s: timeout waiting for USB_PORTSC_LS\n", __func__);
2323                 return -ETIMEDOUT;
2324         }
2325
2326         /* Poll until CCS is enabled */
2327         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
2328                                                  USB_PORTSC_CCS, 2000)) {
2329                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
2330                 return -ETIMEDOUT;
2331         }
2332
2333         if (usb_phy_reg_status_wait(base + HOSTPC1_DEVLC,
2334                         HOSTPC1_DEVLC_PSPD(2),
2335                         HOSTPC1_DEVLC_PSPD(2), 2000) < 0) {
2336                 pr_err("%s: timeout waiting hsic high speed configuration\n",
2337                                                 __func__);
2338                         return -ETIMEDOUT;
2339         }
2340
2341         val = readl(base + USB_USBCMD);
2342         val &= ~USB_USBCMD_RS;
2343         writel(val, base + USB_USBCMD);
2344
2345         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
2346                                                  USB_USBSTS_HCH, 2000)) {
2347                 pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
2348                 return -ETIMEDOUT;
2349         }
2350
2351         val = readl(base + UHSIC_PADS_CFG1);
2352         val &= ~UHSIC_RPU_STROBE;
2353         val |= UHSIC_RPD_STROBE;
2354         writel(val, base + UHSIC_PADS_CFG1);
2355
2356         mdelay(50);
2357
2358         val = readl(base + UHSIC_PADS_CFG1);
2359         val &= ~UHSIC_RPD_STROBE;
2360         val |= UHSIC_RPU_STROBE;
2361         writel(val, base + UHSIC_PADS_CFG1);
2362
2363         val = readl(base + USB_USBCMD);
2364         val |= USB_USBCMD_RS;
2365         writel(val, base + USB_USBCMD);
2366
2367         val = readl(base + UHSIC_PADS_CFG1);
2368         val &= ~UHSIC_RPU_STROBE;
2369         writel(val, base + UHSIC_PADS_CFG1);
2370
2371         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2372                                                  USB_USBCMD_RS, 2000)) {
2373                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2374                 return -ETIMEDOUT;
2375         }
2376
2377         return 0;
2378 }
2379
2380 int uhsic_phy_resume(struct tegra_usb_phy *phy)
2381 {
2382         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2383
2384         uhsic_phy_restore_start(phy);
2385         usb_phy_bringup_host_controller(phy);
2386         uhsic_phy_restore_end(phy);
2387
2388         return 0;
2389 }
2390
2391 static void ulpi_set_trimmer(struct tegra_usb_phy *phy)
2392 {
2393         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2394         void __iomem *base = phy->regs;
2395         unsigned long val;
2396
2397         val = ULPI_DATA_TRIMMER_SEL(config->data_trimmer);
2398         val |= ULPI_STPDIRNXT_TRIMMER_SEL(config->stpdirnxt_trimmer);
2399         val |= ULPI_DIR_TRIMMER_SEL(config->dir_trimmer);
2400         writel(val, base + ULPI_TIMING_CTRL_1);
2401         udelay(10);
2402
2403         val |= ULPI_DATA_TRIMMER_LOAD;
2404         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
2405         val |= ULPI_DIR_TRIMMER_LOAD;
2406         writel(val, base + ULPI_TIMING_CTRL_1);
2407 }
2408
2409 static void reset_utmip_uhsic(void __iomem *base)
2410 {
2411         unsigned long val;
2412
2413         val = readl(base + USB_SUSP_CTRL);
2414         val |= UHSIC_RESET;
2415         writel(val, base + USB_SUSP_CTRL);
2416
2417         val = readl(base + USB_SUSP_CTRL);
2418         val |= UTMIP_RESET;
2419         writel(val, base + USB_SUSP_CTRL);
2420 }
2421
2422 static void ulpi_set_host(void __iomem *base)
2423 {
2424         unsigned long val;
2425
2426         val = readl(base + USB_USBMODE);
2427         val &= ~USB_USBMODE_MASK;
2428         val |= USB_USBMODE_HOST;
2429         writel(val, base + USB_USBMODE);
2430
2431         val = readl(base + HOSTPC1_DEVLC);
2432         val |= HOSTPC1_DEVLC_PTS(2);
2433         writel(val, base + HOSTPC1_DEVLC);
2434 }
2435
2436 static inline void ulpi_pinmux_bypass(struct tegra_usb_phy *phy, bool enable)
2437 {
2438         unsigned long val;
2439         void __iomem *base = phy->regs;
2440
2441         val = readl(base + ULPI_TIMING_CTRL_0);
2442
2443         if (enable)
2444                 val |= ULPI_OUTPUT_PINMUX_BYP;
2445         else
2446                 val &= ~ULPI_OUTPUT_PINMUX_BYP;
2447
2448         writel(val, base + ULPI_TIMING_CTRL_0);
2449 }
2450
2451 static inline void ulpi_null_phy_set_tristate(bool enable)
2452 {
2453 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2454         int tristate = (enable) ? TEGRA_TRI_TRISTATE : TEGRA_TRI_NORMAL;
2455
2456         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA0, tristate);
2457         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA1, tristate);
2458         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA2, tristate);
2459         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA3, tristate);
2460         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA4, tristate);
2461         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA5, tristate);
2462         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA6, tristate);
2463         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA7, tristate);
2464         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_NXT, tristate);
2465
2466         if (enable)
2467                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR, tristate);
2468 #endif
2469 }
2470
2471 static void ulpi_null_phy_obs_read(void)
2472 {
2473         static void __iomem *apb_misc;
2474         unsigned slv0_obs, s2s_obs;
2475
2476         if (!apb_misc)
2477                 apb_misc = ioremap(TEGRA_APB_MISC_BASE, TEGRA_APB_MISC_SIZE);
2478
2479         writel(0x80d1003c, apb_misc + APB_MISC_GP_OBSCTRL_0);
2480         slv0_obs = readl(apb_misc + APB_MISC_GP_OBSDATA_0);
2481
2482         writel(0x80d10040, apb_misc + APB_MISC_GP_OBSCTRL_0);
2483         s2s_obs = readl(apb_misc + APB_MISC_GP_OBSDATA_0);
2484
2485         pr_debug("slv0 obs: %08x\ns2s obs: %08x\n", slv0_obs, s2s_obs);
2486 }
2487
2488 static const struct gpio ulpi_gpios[] = {
2489         {ULPI_STP, GPIOF_IN, "ULPI_STP"},
2490         {ULPI_DIR, GPIOF_OUT_INIT_LOW, "ULPI_DIR"},
2491         {ULPI_D0, GPIOF_OUT_INIT_LOW, "ULPI_D0"},
2492         {ULPI_D1, GPIOF_OUT_INIT_LOW, "ULPI_D1"},
2493 };
2494
2495 static int ulpi_null_phy_open(struct tegra_usb_phy *phy)
2496 {
2497         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2498         int ret;
2499
2500         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2501
2502         ret = gpio_request_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
2503         if (ret)
2504                 return ret;
2505
2506         if (gpio_is_valid(config->phy_restore_gpio)) {
2507                 ret = gpio_request(config->phy_restore_gpio, "phy_restore");
2508                 if (ret)
2509                         goto err_gpio_free;
2510
2511                 gpio_direction_input(config->phy_restore_gpio);
2512         }
2513
2514         tegra_periph_reset_assert(phy->ctrlr_clk);
2515         udelay(10);
2516         tegra_periph_reset_deassert(phy->ctrlr_clk);
2517
2518         return 0;
2519
2520 err_gpio_free:
2521         gpio_free_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
2522         return ret;
2523 }
2524
2525 static void ulpi_null_phy_close(struct tegra_usb_phy *phy)
2526 {
2527         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2528
2529         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2530
2531         if (gpio_is_valid(config->phy_restore_gpio))
2532                 gpio_free(config->phy_restore_gpio);
2533
2534         gpio_free_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
2535 }
2536
2537 static int ulpi_null_phy_power_off(struct tegra_usb_phy *phy)
2538 {
2539         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2540
2541         if (!phy->phy_clk_on) {
2542                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
2543                                                         __LINE__, phy->inst);
2544                 return 0;
2545         }
2546
2547         phy->phy_clk_on = false;
2548         phy->hw_accessible = false;
2549         ulpi_null_phy_set_tristate(true);
2550         return 0;
2551 }
2552
2553 /* NOTE: this function must be called before ehci reset */
2554 static int ulpi_null_phy_init(struct tegra_usb_phy *phy)
2555 {
2556         unsigned long val;
2557         void __iomem *base = phy->regs;
2558
2559         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2560         val = readl(base + ULPIS2S_CTRL);
2561         val |=  ULPIS2S_SLV0_CLAMP_XMIT;
2562         writel(val, base + ULPIS2S_CTRL);
2563
2564         val = readl(base + USB_SUSP_CTRL);
2565         val |= ULPIS2S_SLV0_RESET;
2566         writel(val, base + USB_SUSP_CTRL);
2567         udelay(10);
2568
2569         return 0;
2570 }
2571
2572 static int ulpi_null_phy_irq(struct tegra_usb_phy *phy)
2573 {
2574         usb_phy_fence_read(phy);
2575         return IRQ_HANDLED;
2576 }
2577
2578 /* NOTE: this function must be called after ehci reset */
2579 static int ulpi_null_phy_cmd_reset(struct tegra_usb_phy *phy)
2580 {
2581         unsigned long val;
2582         void __iomem *base = phy->regs;
2583
2584         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2585         ulpi_set_host(base);
2586
2587         /* remove slave0 reset */
2588         val = readl(base + USB_SUSP_CTRL);
2589         val &= ~ULPIS2S_SLV0_RESET;
2590         writel(val, base + USB_SUSP_CTRL);
2591
2592         val = readl(base + ULPIS2S_CTRL);
2593         val &=  ~ULPIS2S_SLV0_CLAMP_XMIT;
2594         writel(val, base + ULPIS2S_CTRL);
2595         udelay(10);
2596
2597         return 0;
2598 }
2599
2600 static int ulpi_null_phy_restore(struct tegra_usb_phy *phy)
2601 {
2602         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2603         unsigned long timeout;
2604         int ulpi_stp = ULPI_STP;
2605
2606         if (gpio_is_valid(config->phy_restore_gpio))
2607                 ulpi_stp = config->phy_restore_gpio;
2608
2609         /* disable ULPI pinmux bypass */
2610         ulpi_pinmux_bypass(phy, false);
2611
2612         /* driving linstate by GPIO */
2613         gpio_set_value(ULPI_D0, 0);
2614         gpio_set_value(ULPI_D1, 0);
2615
2616         /* driving DIR high */
2617         gpio_set_value(ULPI_DIR, 1);
2618
2619         /* remove ULPI tristate */
2620         ulpi_null_phy_set_tristate(false);
2621
2622         /* wait for STP high */
2623         timeout = jiffies + msecs_to_jiffies(25);
2624
2625         while (!gpio_get_value(ulpi_stp)) {
2626                 if (time_after(jiffies, timeout)) {
2627                         pr_warn("phy restore timeout\n");
2628                         return 1;
2629                 }
2630         }
2631
2632         return 0;
2633 }
2634
2635 static int ulpi_null_phy_lp0_resume(struct tegra_usb_phy *phy)
2636 {
2637         unsigned long val;
2638         void __iomem *base = phy->regs;
2639
2640         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2641         ulpi_null_phy_init(phy);
2642
2643         val = readl(base + USB_USBCMD);
2644         val |= USB_CMD_RESET;
2645         writel(val, base + USB_USBCMD);
2646
2647         if (usb_phy_reg_status_wait(base + USB_USBCMD,
2648                 USB_CMD_RESET, 0, 2500) < 0) {
2649                 pr_err("%s: timeout waiting for reset\n", __func__);
2650         }
2651
2652         ulpi_null_phy_cmd_reset(phy);
2653
2654         val = readl(base + USB_USBCMD);
2655         val |= USB_USBCMD_RS;
2656         writel(val, base + USB_USBCMD);
2657         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2658                                                  USB_USBCMD_RS, 2000)) {
2659                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2660                 return -ETIMEDOUT;
2661         }
2662
2663         /* Enable Port Power */
2664         val = readl(base + USB_PORTSC);
2665         val |= USB_PORTSC_PP;
2666         writel(val, base + USB_PORTSC);
2667         udelay(10);
2668
2669         ulpi_null_phy_restore(phy);
2670
2671         return 0;
2672 }
2673
2674 static int ulpi_null_phy_power_on(struct tegra_usb_phy *phy)
2675 {
2676         unsigned long val;
2677         void __iomem *base = phy->regs;
2678         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2679
2680         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2681         if (phy->phy_clk_on) {
2682                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
2683                                                         __LINE__, phy->inst);
2684                 return 0;
2685         }
2686         reset_utmip_uhsic(base);
2687
2688         /* remove ULPI PADS CLKEN reset */
2689         val = readl(base + USB_SUSP_CTRL);
2690         val &= ~ULPI_PADS_CLKEN_RESET;
2691         writel(val, base + USB_SUSP_CTRL);
2692         udelay(10);
2693
2694         val = readl(base + ULPI_TIMING_CTRL_0);
2695         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
2696         writel(val, base + ULPI_TIMING_CTRL_0);
2697
2698         val = readl(base + USB_SUSP_CTRL);
2699         val |= ULPI_PHY_ENABLE;
2700         writel(val, base + USB_SUSP_CTRL);
2701         udelay(10);
2702
2703         /* set timming parameters */
2704         val = readl(base + ULPI_TIMING_CTRL_0);
2705         val |= ULPI_SHADOW_CLK_LOOPBACK_EN;
2706         val &= ~ULPI_SHADOW_CLK_SEL;
2707         val &= ~ULPI_LBK_PAD_EN;
2708         val |= ULPI_SHADOW_CLK_DELAY(config->shadow_clk_delay);
2709         val |= ULPI_CLOCK_OUT_DELAY(config->clock_out_delay);
2710         val |= ULPI_LBK_PAD_E_INPUT_OR;
2711         writel(val, base + ULPI_TIMING_CTRL_0);
2712
2713         writel(0, base + ULPI_TIMING_CTRL_1);
2714         udelay(10);
2715
2716         /* start internal 60MHz clock */
2717         val = readl(base + ULPIS2S_CTRL);
2718         val |= ULPIS2S_ENA;
2719         val |= ULPIS2S_SUPPORT_DISCONNECT;
2720         val |= ULPIS2S_SPARE((phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) ? 3 : 1);
2721         val |= ULPIS2S_PLLU_MASTER_BLASTER60;
2722         writel(val, base + ULPIS2S_CTRL);
2723
2724         /* select ULPI_CORE_CLK_SEL to SHADOW_CLK */
2725         val = readl(base + ULPI_TIMING_CTRL_0);
2726         val |= ULPI_CORE_CLK_SEL;
2727         writel(val, base + ULPI_TIMING_CTRL_0);
2728         udelay(10);
2729
2730         /* enable ULPI null phy clock - can't set the trimmers before this */
2731         val = readl(base + ULPI_TIMING_CTRL_0);
2732         val |= ULPI_CLK_OUT_ENA;
2733         writel(val, base + ULPI_TIMING_CTRL_0);
2734         udelay(10);
2735
2736         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
2737                                                  USB_PHY_CLK_VALID, 2500)) {
2738                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2739                 return -ETIMEDOUT;
2740         }
2741
2742         /* set ULPI trimmers */
2743         ulpi_set_trimmer(phy);
2744
2745         ulpi_set_host(base);
2746
2747         /* remove slave0 reset */
2748         val = readl(base + USB_SUSP_CTRL);
2749         val &= ~ULPIS2S_SLV0_RESET;
2750         writel(val, base + USB_SUSP_CTRL);
2751
2752         /* remove slave1 and line reset */
2753         val = readl(base + USB_SUSP_CTRL);
2754         val &= ~ULPIS2S_SLV1_RESET;
2755         val &= ~ULPIS2S_LINE_RESET;
2756
2757         /* remove ULPI PADS reset */
2758         val &= ~ULPI_PADS_RESET;
2759         writel(val, base + USB_SUSP_CTRL);
2760
2761         if (!phy->ulpi_clk_padout_ena) {
2762                 val = readl(base + ULPI_TIMING_CTRL_0);
2763                 val |= ULPI_CLK_PADOUT_ENA;
2764                 writel(val, base + ULPI_TIMING_CTRL_0);
2765                 phy->ulpi_clk_padout_ena = true;
2766         } else {
2767                 if (!readl(base + USB_ASYNCLISTADDR))
2768                         ulpi_null_phy_lp0_resume(phy);
2769         }
2770         udelay(10);
2771
2772         phy->phy_clk_on = true;
2773         phy->hw_accessible = true;
2774
2775         return 0;
2776 }
2777
2778 static int ulpi_null_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
2779 {
2780         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2781         ulpi_null_phy_obs_read();
2782         usb_phy_wait_for_sof(phy);
2783         ulpi_null_phy_obs_read();
2784         return 0;
2785 }
2786
2787 static int ulpi_null_phy_post_resume(struct tegra_usb_phy *phy)
2788 {
2789         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2790         ulpi_null_phy_obs_read();
2791         return 0;
2792 }
2793
2794 static int ulpi_null_phy_resume(struct tegra_usb_phy *phy)
2795 {
2796         unsigned long val;
2797         void __iomem *base = phy->regs;
2798
2799         if (!readl(base + USB_ASYNCLISTADDR)) {
2800                 /* enable ULPI CLK output pad */
2801                 val = readl(base + ULPI_TIMING_CTRL_0);
2802                 val |= ULPI_CLK_PADOUT_ENA;
2803                 writel(val, base + ULPI_TIMING_CTRL_0);
2804
2805                 /* enable ULPI pinmux bypass */
2806                 ulpi_pinmux_bypass(phy, true);
2807                 udelay(5);
2808 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2809                 /* remove DIR tristate */
2810                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR,
2811                                           TEGRA_TRI_NORMAL);
2812 #endif
2813         }
2814         return 0;
2815 }
2816
2817
2818
2819 static struct tegra_usb_phy_ops utmi_phy_ops = {
2820         .open           = utmi_phy_open,
2821         .close          = utmi_phy_close,
2822         .irq            = utmi_phy_irq,
2823         .power_on       = utmi_phy_power_on,
2824         .power_off      = utmi_phy_power_off,
2825         .pre_resume = utmi_phy_pre_resume,
2826         .resume = utmi_phy_resume,
2827         .post_resume    = utmi_phy_post_resume,
2828         .charger_detect = utmi_phy_charger_detect,
2829         .post_suspend   = phy_post_suspend,
2830 };
2831
2832 static struct tegra_usb_phy_ops uhsic_phy_ops = {
2833         .open           = uhsic_phy_open,
2834         .irq            = uhsic_phy_irq,
2835         .power_on       = uhsic_phy_power_on,
2836         .power_off      = uhsic_phy_power_off,
2837         .pre_resume = uhsic_phy_pre_resume,
2838         .resume = uhsic_phy_resume,
2839         .post_resume = uhsic_phy_post_resume,
2840         .port_power = uhsic_phy_bus_port_power,
2841         .bus_reset      = uhsic_phy_bus_reset,
2842         .post_suspend   = phy_post_suspend,
2843 };
2844
2845 static struct tegra_usb_phy_ops ulpi_null_phy_ops = {
2846         .open           = ulpi_null_phy_open,
2847         .close          = ulpi_null_phy_close,
2848         .init           = ulpi_null_phy_init,
2849         .irq            = ulpi_null_phy_irq,
2850         .power_on       = ulpi_null_phy_power_on,
2851         .power_off      = ulpi_null_phy_power_off,
2852         .pre_resume = ulpi_null_phy_pre_resume,
2853         .resume = ulpi_null_phy_resume,
2854         .post_resume = ulpi_null_phy_post_resume,
2855         .reset          = ulpi_null_phy_cmd_reset,
2856         .post_suspend   = phy_post_suspend,
2857 };
2858
2859 static struct tegra_usb_phy_ops ulpi_link_phy_ops;
2860 static struct tegra_usb_phy_ops icusb_phy_ops;
2861
2862 static struct tegra_usb_phy_ops *phy_ops[] = {
2863         [TEGRA_USB_PHY_INTF_UTMI] = &utmi_phy_ops,
2864         [TEGRA_USB_PHY_INTF_ULPI_LINK] = &ulpi_link_phy_ops,
2865         [TEGRA_USB_PHY_INTF_ULPI_NULL] = &ulpi_null_phy_ops,
2866         [TEGRA_USB_PHY_INTF_HSIC] = &uhsic_phy_ops,
2867         [TEGRA_USB_PHY_INTF_ICUSB] = &icusb_phy_ops,
2868 };
2869
2870 int tegra3_usb_phy_init_ops(struct tegra_usb_phy *phy)
2871 {
2872         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2873
2874         phy->ops = phy_ops[phy->pdata->phy_intf];
2875
2876         /* FIXME: uncommenting below line to make USB host mode fail*/
2877         /* usb_phy_power_down_pmc(); */
2878
2879         return 0;
2880 }