rtc: tps80031: register as mfd sub device
[linux-2.6.git] / arch / arm / mach-tegra / tegra3_usb_phy.c
1 /*
2  * arch/arm/mach-tegra/tegra3_usb_phy.c
3  *
4  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
5  *
6  *
7  * This software is licensed under the terms of the GNU General Public
8  * License version 2, as published by the Free Software Foundation, and
9  * may be copied, distributed, and modified under those terms.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17 #include <linux/resource.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/slab.h>
21 #include <linux/err.h>
22 #include <linux/platform_device.h>
23 #include <linux/io.h>
24 #include <linux/gpio.h>
25 #include <linux/interrupt.h>
26 #include <linux/clk.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <mach/clk.h>
30 #include <mach/iomap.h>
31 #include <mach/pinmux.h>
32 #include "tegra_usb_phy.h"
33 #include "gpio-names.h"
34 #include "fuse.h"
35
36 #define USB_USBCMD              0x130
37 #define   USB_USBCMD_RS         (1 << 0)
38 #define   USB_CMD_RESET (1<<1)
39
40 #define USB_USBSTS              0x134
41 #define   USB_USBSTS_PCI        (1 << 2)
42 #define   USB_USBSTS_SRI        (1 << 7)
43 #define   USB_USBSTS_HCH        (1 << 12)
44
45 #define USB_USBINTR             0x138
46
47 #define USB_TXFILLTUNING        0x154
48 #define USB_FIFO_TXFILL_THRES(x)   (((x) & 0x1f) << 16)
49 #define USB_FIFO_TXFILL_MASK    0x1f0000
50
51 #define USB_ASYNCLISTADDR       0x148
52
53 #define ICUSB_CTRL              0x15c
54
55 #define USB_PORTSC              0x174
56 #define   USB_PORTSC_WKOC       (1 << 22)
57 #define   USB_PORTSC_WKDS       (1 << 21)
58 #define   USB_PORTSC_WKCN       (1 << 20)
59 #define   USB_PORTSC_PTC(x)     (((x) & 0xf) << 16)
60 #define   USB_PORTSC_PP (1 << 12)
61 #define   USB_PORTSC_LS(x) (((x) & 0x3) << 10)
62 #define   USB_PORTSC_SUSP       (1 << 7)
63 #define   USB_PORTSC_RESUME     (1 << 6)
64 #define   USB_PORTSC_OCC        (1 << 5)
65 #define   USB_PORTSC_PEC        (1 << 3)
66 #define   USB_PORTSC_PE         (1 << 2)
67 #define   USB_PORTSC_CSC        (1 << 1)
68 #define   USB_PORTSC_CCS        (1 << 0)
69 #define   USB_PORTSC_RWC_BITS (USB_PORTSC_CSC | USB_PORTSC_PEC | USB_PORTSC_OCC)
70
71 #define HOSTPC1_DEVLC           0x1b4
72 #define   HOSTPC1_DEVLC_PHCD            (1 << 22)
73 #define   HOSTPC1_DEVLC_PTS(x)          (((x) & 0x7) << 29)
74 #define   HOSTPC1_DEVLC_PTS_MASK        7
75 #define   HOSTPC1_DEVLC_PTS_HSIC        4
76 #define   HOSTPC1_DEVLC_STS             (1 << 28)
77 #define   HOSTPC1_DEVLC_PSPD(x)         (((x) & 0x3) << 25)
78 #define   HOSTPC1_DEVLC_PSPD_MASK       3
79 #define   HOSTPC1_DEVLC_PSPD_HIGH_SPEED 2
80
81 #define USB_USBMODE             0x1f8
82 #define   USB_USBMODE_MASK              (3 << 0)
83 #define   USB_USBMODE_HOST              (3 << 0)
84 #define   USB_USBMODE_DEVICE            (2 << 0)
85
86 #define USB_SUSP_CTRL           0x400
87 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
88 #define   USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
89 #define   USB_SUSP_CLR                  (1 << 5)
90 #define   USB_PHY_CLK_VALID             (1 << 7)
91 #define   USB_PHY_CLK_VALID_INT_ENB     (1 << 9)
92 #define   USB_PHY_CLK_VALID_INT_STS     (1 << 8)
93 #define   UTMIP_RESET                   (1 << 11)
94 #define   UTMIP_PHY_ENABLE              (1 << 12)
95 #define   ULPI_PHY_ENABLE               (1 << 13)
96 #define   UHSIC_RESET                   (1 << 14)
97 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
98 #define   UHSIC_PHY_ENABLE              (1 << 19)
99 #define   ULPIS2S_SLV0_RESET            (1 << 20)
100 #define   ULPIS2S_SLV1_RESET            (1 << 21)
101 #define   ULPIS2S_LINE_RESET            (1 << 22)
102 #define   ULPI_PADS_RESET               (1 << 23)
103 #define   ULPI_PADS_CLKEN_RESET         (1 << 24)
104
105 #define USB_PHY_VBUS_WAKEUP_ID  0x408
106 #define   VDAT_DET_INT_EN       (1 << 16)
107 #define   VDAT_DET_CHG_DET      (1 << 17)
108 #define   VDAT_DET_STS          (1 << 18)
109 #define   USB_ID_STATUS         (1 << 2)
110
111 #define ULPIS2S_CTRL            0x418
112 #define   ULPIS2S_ENA                   (1 << 0)
113 #define   ULPIS2S_SUPPORT_DISCONNECT    (1 << 2)
114 #define   ULPIS2S_PLLU_MASTER_BLASTER60 (1 << 3)
115 #define   ULPIS2S_SPARE(x)              (((x) & 0xF) << 8)
116 #define   ULPIS2S_FORCE_ULPI_CLK_OUT    (1 << 12)
117 #define   ULPIS2S_DISCON_DONT_CHECK_SE0 (1 << 13)
118 #define   ULPIS2S_SUPPORT_HS_KEEP_ALIVE (1 << 14)
119 #define   ULPIS2S_DISABLE_STP_PU        (1 << 15)
120 #define   ULPIS2S_SLV0_CLAMP_XMIT       (1 << 16)
121
122 #define ULPI_TIMING_CTRL_0      0x424
123 #define   ULPI_CLOCK_OUT_DELAY(x)       ((x) & 0x1F)
124 #define   ULPI_OUTPUT_PINMUX_BYP        (1 << 10)
125 #define   ULPI_CLKOUT_PINMUX_BYP        (1 << 11)
126 #define   ULPI_SHADOW_CLK_LOOPBACK_EN   (1 << 12)
127 #define   ULPI_SHADOW_CLK_SEL           (1 << 13)
128 #define   ULPI_CORE_CLK_SEL             (1 << 14)
129 #define   ULPI_SHADOW_CLK_DELAY(x)      (((x) & 0x1F) << 16)
130 #define   ULPI_LBK_PAD_EN               (1 << 26)
131 #define   ULPI_LBK_PAD_E_INPUT_OR       (1 << 27)
132 #define   ULPI_CLK_OUT_ENA              (1 << 28)
133 #define   ULPI_CLK_PADOUT_ENA           (1 << 29)
134
135 #define ULPI_TIMING_CTRL_1      0x428
136 #define   ULPI_DATA_TRIMMER_LOAD        (1 << 0)
137 #define   ULPI_DATA_TRIMMER_SEL(x)      (((x) & 0x7) << 1)
138 #define   ULPI_STPDIRNXT_TRIMMER_LOAD   (1 << 16)
139 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
140 #define   ULPI_DIR_TRIMMER_LOAD         (1 << 24)
141 #define   ULPI_DIR_TRIMMER_SEL(x)       (((x) & 0x7) << 25)
142
143 #define UTMIP_XCVR_CFG0         0x808
144 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
145 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
146 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
147 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
148 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
149 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
150 #define   UTMIP_XCVR_LSBIAS_SEL                 (1 << 21)
151 #define   UTMIP_XCVR_SETUP_MSB(x)               (((x) & 0x7) << 22)
152 #define   UTMIP_XCVR_HSSLEW_MSB(x)              (((x) & 0x7f) << 25)
153 #define   UTMIP_XCVR_MAX_OFFSET         2
154 #define   UTMIP_XCVR_SETUP_MAX_VALUE    0x7f
155 #define   UTMIP_XCVR_SETUP_MIN_VALUE    0
156 #define   XCVR_SETUP_MSB_CALIB(x) ((x) >> 4)
157
158 #define UTMIP_BIAS_CFG0         0x80c
159 #define   UTMIP_OTGPD                   (1 << 11)
160 #define   UTMIP_BIASPD                  (1 << 10)
161 #define   UTMIP_HSSQUELCH_LEVEL(x)      (((x) & 0x3) << 0)
162 #define   UTMIP_HSDISCON_LEVEL(x)       (((x) & 0x3) << 2)
163 #define   UTMIP_HSDISCON_LEVEL_MSB      (1 << 24)
164
165 #define UTMIP_HSRX_CFG0         0x810
166 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
167 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
168
169 #define UTMIP_HSRX_CFG1         0x814
170 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
171
172 #define UTMIP_TX_CFG0           0x820
173 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
174 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
175
176 #define UTMIP_DEBOUNCE_CFG0 0x82c
177 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
178
179 #define UTMIP_BAT_CHRG_CFG0 0x830
180 #define   UTMIP_PD_CHRG                 (1 << 0)
181 #define   UTMIP_ON_SINK_EN              (1 << 2)
182 #define   UTMIP_OP_SRC_EN               (1 << 3)
183
184 #define UTMIP_XCVR_CFG1         0x838
185 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
186 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
187 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
188 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
189
190 #define UTMIP_BIAS_CFG1         0x83c
191 #define   UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
192 #define   UTMIP_BIAS_PDTRK_POWERDOWN    (1 << 0)
193 #define   UTMIP_BIAS_PDTRK_POWERUP      (1 << 1)
194
195 #define UTMIP_MISC_CFG0         0x824
196 #define   UTMIP_DPDM_OBSERVE            (1 << 26)
197 #define   UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
198 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J   UTMIP_DPDM_OBSERVE_SEL(0xf)
199 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K   UTMIP_DPDM_OBSERVE_SEL(0xe)
200 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
201 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
202 #define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
203 #define   FORCE_PULLDN_DM       (1 << 8)
204 #define   FORCE_PULLDN_DP       (1 << 9)
205 #define   COMB_TERMS            (1 << 0)
206 #define   ALWAYS_FREE_RUNNING_TERMS (1 << 1)
207
208 #define UTMIP_SPARE_CFG0        0x834
209 #define   FUSE_SETUP_SEL                (1 << 3)
210 #define   FUSE_ATERM_SEL                (1 << 4)
211
212 #define UTMIP_PMC_WAKEUP0               0x84c
213 #define   EVENT_INT_ENB                 (1 << 0)
214
215 #define UHSIC_PMC_WAKEUP0               0xc34
216
217 #define UTMIP_BIAS_STS0                 0x840
218 #define   UTMIP_RCTRL_VAL(x)            (((x) & 0xffff) << 0)
219 #define   UTMIP_TCTRL_VAL(x)            (((x) & (0xffff << 16)) >> 16)
220
221 #define UHSIC_PLL_CFG1                          0xc04
222 #define   UHSIC_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
223 #define   UHSIC_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 14)
224
225 #define UHSIC_HSRX_CFG0                         0xc08
226 #define   UHSIC_ELASTIC_UNDERRUN_LIMIT(x)       (((x) & 0x1f) << 2)
227 #define   UHSIC_ELASTIC_OVERRUN_LIMIT(x)        (((x) & 0x1f) << 8)
228 #define   UHSIC_IDLE_WAIT(x)                    (((x) & 0x1f) << 13)
229
230 #define UHSIC_HSRX_CFG1                         0xc0c
231 #define   UHSIC_HS_SYNC_START_DLY(x)            (((x) & 0x1f) << 1)
232
233 #define UHSIC_TX_CFG0                           0xc10
234 #define UHSIC_HS_READY_WAIT_FOR_VALID   (1 << 9)
235 #define UHSIC_MISC_CFG0                         0xc14
236 #define   UHSIC_SUSPEND_EXIT_ON_EDGE            (1 << 7)
237 #define   UHSIC_DETECT_SHORT_CONNECT            (1 << 8)
238 #define   UHSIC_FORCE_XCVR_MODE                 (1 << 15)
239 #define   UHSIC_DISABLE_BUSRESET                (1 << 20)
240 #define UHSIC_MISC_CFG1                         0xc18
241 #define   UHSIC_PLLU_STABLE_COUNT(x)            (((x) & 0xfff) << 2)
242
243 #define UHSIC_PADS_CFG0                         0xc1c
244 #define   UHSIC_TX_RTUNEN                       0xf000
245 #define   UHSIC_TX_RTUNE(x)                     (((x) & 0xf) << 12)
246
247 #define UHSIC_PADS_CFG1                         0xc20
248 #define   UHSIC_PD_BG                           (1 << 2)
249 #define   UHSIC_PD_TX                           (1 << 3)
250 #define   UHSIC_PD_TRK                          (1 << 4)
251 #define   UHSIC_PD_RX                           (1 << 5)
252 #define   UHSIC_PD_ZI                           (1 << 6)
253 #define   UHSIC_RX_SEL                          (1 << 7)
254 #define   UHSIC_RPD_DATA                        (1 << 9)
255 #define   UHSIC_RPD_STROBE                      (1 << 10)
256 #define   UHSIC_RPU_DATA                        (1 << 11)
257 #define   UHSIC_RPU_STROBE                      (1 << 12)
258
259 #define UHSIC_CMD_CFG0                  0xc24
260 #define UHSIC_PRETEND_CONNECT_DETECT    (1 << 5)
261
262 #define UHSIC_STAT_CFG0         0xc28
263 #define UHSIC_CONNECT_DETECT            (1 << 0)
264
265 #define PMC_USB_DEBOUNCE                        0xec
266 #define UTMIP_LINE_DEB_CNT(x)           (((x) & 0xf) << 16)
267 #define UHSIC_LINE_DEB_CNT(x)           (((x) & 0xf) << 20)
268
269 #define PMC_USB_AO                              0xf0
270
271 #define PMC_POWER_DOWN_MASK                     0xffff
272 #define HSIC_RESERVED_P0                        (3 << 14)
273 #define STROBE_VAL_PD_P0                        (1 << 12)
274 #define DATA_VAL_PD_P0                          (1 << 13)
275
276 #define USB_ID_PD(inst)                 (1 << ((4*(inst))+3))
277 #define VBUS_WAKEUP_PD(inst)                    (1 << ((4*(inst))+2))
278 #define   USBON_VAL_PD(inst)                    (1 << ((4*(inst))+1))
279 #define   USBON_VAL_PD_P2                       (1 << 9)
280 #define   USBON_VAL_PD_P1                       (1 << 5)
281 #define   USBON_VAL_PD_P0                       (1 << 1)
282 #define   USBOP_VAL_PD(inst)                    (1 << (4*(inst)))
283 #define   USBOP_VAL_PD_P2                       (1 << 8)
284 #define   USBOP_VAL_PD_P1                       (1 << 4)
285 #define   USBOP_VAL_PD_P0                       (1 << 0)
286 #define   PMC_USB_AO_PD_P2                      (0xf << 8)
287 #define   PMC_USB_AO_ID_PD_P0                   (1 << 3)
288 #define   PMC_USB_AO_VBUS_WAKEUP_PD_P0  (1 << 2)
289
290 #define PMC_TRIGGERS                    0x1ec
291
292 #define   UHSIC_CLR_WALK_PTR_P0         (1 << 3)
293 #define   UTMIP_CLR_WALK_PTR(inst)      (1 << (inst))
294 #define   UTMIP_CLR_WALK_PTR_P2         (1 << 2)
295 #define   UTMIP_CLR_WALK_PTR_P1         (1 << 1)
296 #define   UTMIP_CLR_WALK_PTR_P0         (1 << 0)
297 #define   UTMIP_CAP_CFG(inst)   (1 << ((inst)+4))
298 #define   UTMIP_CAP_CFG_P2              (1 << 6)
299 #define   UTMIP_CAP_CFG_P1              (1 << 5)
300 #define   UTMIP_CAP_CFG_P0              (1 << 4)
301 #define   UTMIP_CLR_WAKE_ALARM(inst)    (1 << ((inst)+12))
302 #define   UHSIC_CLR_WAKE_ALARM_P0       (1 << 15)
303 #define   UTMIP_CLR_WAKE_ALARM_P2       (1 << 14)
304
305 #define PMC_PAD_CFG             (0x1f4)
306
307 #define PMC_UTMIP_TERM_PAD_CFG  0x1f8
308 #define   PMC_TCTRL_VAL(x)      (((x) & 0x1f) << 5)
309 #define   PMC_RCTRL_VAL(x)      (((x) & 0x1f) << 0)
310
311 #define PMC_SLEEP_CFG                   0x1fc
312
313 #define   UHSIC_MASTER_ENABLE                   (1 << 24)
314 #define   UHSIC_WAKE_VAL(x)             (((x) & 0xf) << 28)
315 #define   WAKE_VAL_SD10                 0x2
316 #define   UTMIP_TCTRL_USE_PMC(inst) (1 << ((8*(inst))+3))
317 #define   UTMIP_TCTRL_USE_PMC_P2                (1 << 19)
318 #define   UTMIP_TCTRL_USE_PMC_P1                (1 << 11)
319 #define   UTMIP_TCTRL_USE_PMC_P0                (1 << 3)
320 #define   UTMIP_RCTRL_USE_PMC(inst) (1 << ((8*(inst))+2))
321 #define   UTMIP_RCTRL_USE_PMC_P2                (1 << 18)
322 #define   UTMIP_RCTRL_USE_PMC_P1                (1 << 10)
323 #define   UTMIP_RCTRL_USE_PMC_P0                (1 << 2)
324 #define   UTMIP_FSLS_USE_PMC(inst)      (1 << ((8*(inst))+1))
325 #define   UTMIP_FSLS_USE_PMC_P2         (1 << 17)
326 #define   UTMIP_FSLS_USE_PMC_P1         (1 << 9)
327 #define   UTMIP_FSLS_USE_PMC_P0         (1 << 1)
328 #define   UTMIP_MASTER_ENABLE(inst) (1 << (8*(inst)))
329 #define   UTMIP_MASTER_ENABLE_P2                (1 << 16)
330 #define   UTMIP_MASTER_ENABLE_P1                (1 << 8)
331 #define   UTMIP_MASTER_ENABLE_P0                (1 << 0)
332 #define UHSIC_MASTER_ENABLE_P0          (1 << 24)
333 #define UHSIC_WAKE_VAL_P0(x)            (((x) & 0xf) << 28)
334
335 #define PMC_SLEEPWALK_CFG               0x200
336
337 #define   UHSIC_WAKE_WALK_EN_P0 (1 << 30)
338 #define   UHSIC_LINEVAL_WALK_EN (1 << 31)
339 #define   UTMIP_LINEVAL_WALK_EN(inst) (1 << ((8*(inst))+7))
340 #define   UTMIP_LINEVAL_WALK_EN_P2      (1 << 23)
341 #define   UTMIP_LINEVAL_WALK_EN_P1      (1 << 15)
342 #define   UTMIP_LINEVAL_WALK_EN_P0      (1 << 7)
343 #define   UTMIP_WAKE_VAL(inst, x) (((x) & 0xf) << ((8*(inst))+4))
344 #define   UTMIP_WAKE_VAL_P2(x)          (((x) & 0xf) << 20)
345 #define   UTMIP_WAKE_VAL_P1(x)          (((x) & 0xf) << 12)
346 #define   UTMIP_WAKE_VAL_P0(x)          (((x) & 0xf) << 4)
347 #define   WAKE_VAL_NONE         0xc
348 #define   WAKE_VAL_ANY                  0xF
349 #define   WAKE_VAL_FSJ                  0x2
350 #define   WAKE_VAL_FSK                  0x1
351 #define   WAKE_VAL_SE0                  0x0
352
353 #define PMC_SLEEPWALK_REG(inst)         (0x204 + (4*(inst)))
354 #define   UTMIP_USBOP_RPD_A     (1 << 0)
355 #define   UTMIP_USBON_RPD_A     (1 << 1)
356 #define   UTMIP_AP_A                    (1 << 4)
357 #define   UTMIP_AN_A                    (1 << 5)
358 #define   UTMIP_HIGHZ_A         (1 << 6)
359 #define   UTMIP_USBOP_RPD_B     (1 << 8)
360 #define   UTMIP_USBON_RPD_B     (1 << 9)
361 #define   UTMIP_AP_B                    (1 << 12)
362 #define   UTMIP_AN_B                    (1 << 13)
363 #define   UTMIP_HIGHZ_B         (1 << 14)
364 #define   UTMIP_USBOP_RPD_C     (1 << 16)
365 #define   UTMIP_USBON_RPD_C     (1 << 17)
366 #define   UTMIP_AP_C            (1 << 20)
367 #define   UTMIP_AN_C            (1 << 21)
368 #define   UTMIP_HIGHZ_C         (1 << 22)
369 #define   UTMIP_USBOP_RPD_D     (1 << 24)
370 #define   UTMIP_USBON_RPD_D     (1 << 25)
371 #define   UTMIP_AP_D            (1 << 28)
372 #define   UTMIP_AN_D            (1 << 29)
373 #define   UTMIP_HIGHZ_D         (1 << 30)
374
375 #define PMC_SLEEPWALK_UHSIC             0x210
376
377 #define UHSIC_STROBE_RPD_A              (1 << 0)
378 #define UHSIC_DATA_RPD_A                (1 << 1)
379 #define UHSIC_STROBE_RPU_A              (1 << 2)
380 #define UHSIC_DATA_RPU_A                (1 << 3)
381 #define UHSIC_STROBE_RPD_B              (1 << 8)
382 #define UHSIC_DATA_RPD_B                (1 << 9)
383 #define UHSIC_STROBE_RPU_B              (1 << 10)
384 #define UHSIC_DATA_RPU_B                (1 << 11)
385 #define UHSIC_STROBE_RPD_C              (1 << 16)
386 #define UHSIC_DATA_RPD_C                (1 << 17)
387 #define UHSIC_STROBE_RPU_C              (1 << 18)
388 #define UHSIC_DATA_RPU_C                (1 << 19)
389 #define UHSIC_STROBE_RPD_D              (1 << 24)
390 #define UHSIC_DATA_RPD_D                (1 << 25)
391 #define UHSIC_STROBE_RPU_D              (1 << 26)
392 #define UHSIC_DATA_RPU_D                (1 << 27)
393
394 #define UTMIP_UHSIC_STATUS              0x214
395
396 #define UTMIP_USBOP_VAL(inst)           (1 << ((2*(inst)) + 8))
397 #define UTMIP_USBOP_VAL_P2              (1 << 12)
398 #define UTMIP_USBOP_VAL_P1              (1 << 10)
399 #define UTMIP_USBOP_VAL_P0              (1 << 8)
400 #define UTMIP_USBON_VAL(inst)           (1 << ((2*(inst)) + 9))
401 #define UTMIP_USBON_VAL_P2              (1 << 13)
402 #define UTMIP_USBON_VAL_P1              (1 << 11)
403 #define UTMIP_USBON_VAL_P0              (1 << 9)
404 #define UHSIC_WAKE_ALARM                (1 << 19)
405 #define UTMIP_WAKE_ALARM(inst)          (1 << ((inst) + 16))
406 #define UTMIP_WAKE_ALARM_P2             (1 << 18)
407 #define UTMIP_WAKE_ALARM_P1             (1 << 17)
408 #define UTMIP_WAKE_ALARM_P0             (1 << 16)
409 #define UHSIC_DATA_VAL_P0               (1 << 15)
410 #define UHSIC_STROBE_VAL_P0             (1 << 14)
411 #define UTMIP_WALK_PTR_VAL(inst)        (0x3 << ((inst)*2))
412 #define UHSIC_WALK_PTR_VAL              (0x3 << 6)
413 #define UTMIP_WALK_PTR(inst)            (1 << ((inst)*2))
414 #define UTMIP_WALK_PTR_P2               (1 << 4)
415 #define UTMIP_WALK_PTR_P1               (1 << 2)
416 #define UTMIP_WALK_PTR_P0               (1 << 0)
417
418 #define USB1_PREFETCH_ID                           6
419 #define USB2_PREFETCH_ID                           18
420 #define USB3_PREFETCH_ID                           17
421
422 #define PMC_UTMIP_UHSIC_FAKE            0x218
423
424 #define UHSIC_STROBE_VAL                (1 << 12)
425 #define UHSIC_DATA_VAL                  (1 << 13)
426 #define UHSIC_STROBE_ENB                (1 << 14)
427 #define UHSIC_DATA_ENB                  (1 << 15)
428 #define   USBON_VAL(inst)       (1 << ((4*(inst))+1))
429 #define   USBON_VAL_P2                  (1 << 9)
430 #define   USBON_VAL_P1                  (1 << 5)
431 #define   USBON_VAL_P0                  (1 << 1)
432 #define   USBOP_VAL(inst)       (1 << (4*(inst)))
433 #define   USBOP_VAL_P2                  (1 << 8)
434 #define   USBOP_VAL_P1                  (1 << 4)
435 #define   USBOP_VAL_P0                  (1 << 0)
436
437 #define PMC_UTMIP_BIAS_MASTER_CNTRL 0x30c
438 #define   BIAS_MASTER_PROG_VAL          (1 << 1)
439
440 #define PMC_UTMIP_MASTER_CONFIG 0x310
441
442 #define UTMIP_PWR(inst)         (1 << (inst))
443 #define UHSIC_PWR                       (1 << 3)
444
445 #define FUSE_USB_CALIB_0                0x1F0
446 #define   XCVR_SETUP(x) (((x) & 0x7F) << 0)
447 #define   XCVR_SETUP_LSB_MASK   0xF
448 #define   XCVR_SETUP_MSB_MASK   0x70
449 #define   XCVR_SETUP_LSB_MAX_VAL        0xF
450
451 #define APB_MISC_GP_OBSCTRL_0   0x818
452 #define APB_MISC_GP_OBSDATA_0   0x81c
453
454 /* ULPI GPIO */
455 #define ULPI_STP        TEGRA_GPIO_PY3
456 #define ULPI_DIR        TEGRA_GPIO_PY1
457 #define ULPI_D0         TEGRA_GPIO_PO1
458 #define ULPI_D1         TEGRA_GPIO_PO2
459
460 /* These values (in milli second) are taken from the battery charging spec */
461 #define TDP_SRC_ON_MS    100
462 #define TDPSRC_CON_MS    40
463
464 #ifdef DEBUG
465 #define DBG(stuff...)   pr_info("tegra3_usb_phy: " stuff)
466 #else
467 #define DBG(stuff...)   do {} while (0)
468 #endif
469
470 #if 0
471 #define PHY_DBG(stuff...)       pr_info("tegra3_usb_phy: " stuff)
472 #else
473 #define PHY_DBG(stuff...)       do {} while (0)
474 #endif
475
476 /* define HSIC phy params */
477 #define HSIC_SYNC_START_DELAY           9
478 #define HSIC_IDLE_WAIT_DELAY            17
479 #define HSIC_ELASTIC_UNDERRUN_LIMIT     16
480 #define HSIC_ELASTIC_OVERRUN_LIMIT      16
481
482 static u32 utmip_rctrl_val, utmip_tctrl_val;
483 static DEFINE_SPINLOCK(utmip_pad_lock);
484 static int utmip_pad_count;
485
486 static struct tegra_xtal_freq utmip_freq_table[] = {
487         {
488                 .freq = 12000000,
489                 .enable_delay = 0x02,
490                 .stable_count = 0x2F,
491                 .active_delay = 0x04,
492                 .xtal_freq_count = 0x76,
493                 .debounce = 0x7530,
494                 .pdtrk_count = 5,
495         },
496         {
497                 .freq = 13000000,
498                 .enable_delay = 0x02,
499                 .stable_count = 0x33,
500                 .active_delay = 0x05,
501                 .xtal_freq_count = 0x7F,
502                 .debounce = 0x7EF4,
503                 .pdtrk_count = 5,
504         },
505         {
506                 .freq = 19200000,
507                 .enable_delay = 0x03,
508                 .stable_count = 0x4B,
509                 .active_delay = 0x06,
510                 .xtal_freq_count = 0xBB,
511                 .debounce = 0xBB80,
512                 .pdtrk_count = 7,
513         },
514         {
515                 .freq = 26000000,
516                 .enable_delay = 0x04,
517                 .stable_count = 0x66,
518                 .active_delay = 0x09,
519                 .xtal_freq_count = 0xFE,
520                 .debounce = 0xFDE8,
521                 .pdtrk_count = 9,
522         },
523 };
524
525 static struct tegra_xtal_freq uhsic_freq_table[] = {
526         {
527                 .freq = 12000000,
528                 .enable_delay = 0x02,
529                 .stable_count = 0x2F,
530                 .active_delay = 0x0,
531                 .xtal_freq_count = 0x1CA,
532         },
533         {
534                 .freq = 13000000,
535                 .enable_delay = 0x02,
536                 .stable_count = 0x33,
537                 .active_delay = 0x0,
538                 .xtal_freq_count = 0x1F0,
539         },
540         {
541                 .freq = 19200000,
542                 .enable_delay = 0x03,
543                 .stable_count = 0x4B,
544                 .active_delay = 0x0,
545                 .xtal_freq_count = 0x2DD,
546         },
547         {
548                 .freq = 26000000,
549                 .enable_delay = 0x04,
550                 .stable_count = 0x66,
551                 .active_delay = 0x0,
552                 .xtal_freq_count = 0x3E0,
553         },
554 };
555
556 static void usb_phy_fence_read(struct tegra_usb_phy *phy)
557 {
558         /* Fence read for coherency of AHB master intiated writes */
559         if (phy->inst == 0)
560                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB1_PREFETCH_ID));
561         else if (phy->inst == 1)
562                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB2_PREFETCH_ID));
563         else if (phy->inst == 2)
564                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB3_PREFETCH_ID));
565
566         return;
567 }
568
569 static void utmip_setup_pmc_wake_detect(struct tegra_usb_phy *phy)
570 {
571         unsigned long val, pmc_pad_cfg_val;
572         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
573         unsigned  int inst = phy->inst;
574         void __iomem *base = phy->regs;
575         bool port_connected;
576         enum usb_phy_port_speed port_speed;
577
578         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
579
580         /* check for port connect status */
581         val = readl(base + USB_PORTSC);
582         port_connected = val & USB_PORTSC_CCS;
583
584         if (!port_connected)
585                 return;
586
587         port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
588                 HOSTPC1_DEVLC_PSPD_MASK;
589         /*Set PMC MASTER bits to do the following
590         * a. Take over the UTMI drivers
591         * b. set up such that it will take over resume
592         *        if remote wakeup is detected
593         * Prepare PMC to take over suspend-wake detect-drive resume until USB
594         * controller ready
595         */
596
597         /* disable master enable in PMC */
598         val = readl(pmc_base + PMC_SLEEP_CFG);
599         val &= ~UTMIP_MASTER_ENABLE(inst);
600         writel(val, pmc_base + PMC_SLEEP_CFG);
601
602         /* UTMIP_PWR_PX=1 for power savings mode */
603         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
604         val |= UTMIP_PWR(inst);
605         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
606
607         /* config debouncer */
608         val = readl(pmc_base + PMC_USB_DEBOUNCE);
609         val &= ~UTMIP_LINE_DEB_CNT(~0);
610         val |= UTMIP_LINE_DEB_CNT(4);
611         writel(val, pmc_base + PMC_USB_DEBOUNCE);
612
613         /* Make sure nothing is happening on the line with respect to PMC */
614         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
615         val &= ~USBOP_VAL(inst);
616         val &= ~USBON_VAL(inst);
617         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
618
619         /* Make sure wake value for line is none */
620         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
621         val &= ~UTMIP_LINEVAL_WALK_EN(inst);
622         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
623         val = readl(pmc_base + PMC_SLEEP_CFG);
624         val &= ~UTMIP_WAKE_VAL(inst, ~0);
625         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
626         writel(val, pmc_base + PMC_SLEEP_CFG);
627
628         /* turn off pad detectors */
629         val = readl(pmc_base + PMC_USB_AO);
630         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
631         writel(val, pmc_base + PMC_USB_AO);
632
633         /* Remove fake values and make synchronizers work a bit */
634         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
635         val &= ~USBOP_VAL(inst);
636         val &= ~USBON_VAL(inst);
637         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
638
639         /* Enable which type of event can trigger a walk,
640         in this case usb_line_wake */
641         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
642         val |= UTMIP_LINEVAL_WALK_EN(inst);
643         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
644
645         /* Enable which type of event can trigger a walk,
646         * in this case usb_line_wake */
647         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
648         val |= UTMIP_LINEVAL_WALK_EN(inst);
649         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
650
651         /* Capture FS/LS pad configurations */
652         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
653         val = readl(pmc_base + PMC_TRIGGERS);
654         val |= UTMIP_CAP_CFG(inst);
655         writel(val, pmc_base + PMC_TRIGGERS);
656         udelay(1);
657         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
658
659         /* BIAS MASTER_ENABLE=0 */
660         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
661         val &= ~BIAS_MASTER_PROG_VAL;
662         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
663
664         /* program walk sequence, maintain a J, followed by a driven K
665         * to signal a resume once an wake event is detected */
666         val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
667         val &= ~UTMIP_AP_A;
668         val |= UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_AN_A |UTMIP_HIGHZ_A |
669                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_AP_B | UTMIP_AN_B |
670                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_AP_C | UTMIP_AN_C |
671                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_AP_D | UTMIP_AN_D;
672         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
673
674         if (port_speed == USB_PHY_PORT_SPEED_LOW) {
675                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
676                 val &= ~(UTMIP_AN_B | UTMIP_HIGHZ_B | UTMIP_AN_C |
677                         UTMIP_HIGHZ_C | UTMIP_AN_D | UTMIP_HIGHZ_D);
678                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
679         } else {
680                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
681                 val &= ~(UTMIP_AP_B | UTMIP_HIGHZ_B | UTMIP_AP_C |
682                         UTMIP_HIGHZ_C | UTMIP_AP_D | UTMIP_HIGHZ_D);
683                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
684         }
685
686         /* turn on pad detectors */
687         val = readl(pmc_base + PMC_USB_AO);
688         val &= ~(USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
689         writel(val, pmc_base + PMC_USB_AO);
690
691         /* Add small delay before usb detectors provide stable line values */
692         mdelay(1);
693
694         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
695         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
696         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
697         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
698
699         phy->remote_wakeup = false;
700
701         /* Turn over pad configuration to PMC  for line wake events*/
702         val = readl(pmc_base + PMC_SLEEP_CFG);
703         val &= ~UTMIP_WAKE_VAL(inst, ~0);
704         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_ANY);
705         val |= UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst);
706         val |= UTMIP_MASTER_ENABLE(inst) | UTMIP_FSLS_USE_PMC(inst);
707         writel(val, pmc_base + PMC_SLEEP_CFG);
708
709         val = readl(base + UTMIP_PMC_WAKEUP0);
710         val |= EVENT_INT_ENB;
711         writel(val, base + UTMIP_PMC_WAKEUP0);
712         PHY_DBG("%s ENABLE_PMC inst = %d\n", __func__, inst);
713 }
714
715 static void utmip_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy)
716 {
717         unsigned long val;
718         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
719         unsigned  int inst = phy->inst;
720         void __iomem *base = phy->regs;
721
722         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
723
724         val = readl(pmc_base + PMC_SLEEP_CFG);
725         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
726         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
727         writel(val, pmc_base + PMC_SLEEP_CFG);
728
729         val = readl(base + UTMIP_PMC_WAKEUP0);
730         val &= ~EVENT_INT_ENB;
731         writel(val, base + UTMIP_PMC_WAKEUP0);
732
733         /* Disable PMC master mode by clearing MASTER_EN */
734         val = readl(pmc_base + PMC_SLEEP_CFG);
735         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
736                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
737         writel(val, pmc_base + PMC_SLEEP_CFG);
738
739         val = readl(pmc_base + PMC_TRIGGERS);
740         val &= ~UTMIP_CAP_CFG(inst);
741         writel(val, pmc_base + PMC_TRIGGERS);
742
743         /* turn off pad detectors */
744         val = readl(pmc_base + PMC_USB_AO);
745         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
746         writel(val, pmc_base + PMC_USB_AO);
747
748         val = readl(pmc_base + PMC_TRIGGERS);
749         val |= UTMIP_CLR_WALK_PTR(inst);
750         val |= UTMIP_CLR_WAKE_ALARM(inst);
751         writel(val, pmc_base + PMC_TRIGGERS);
752
753         phy->remote_wakeup = false;
754         PHY_DBG("%s DISABLE_PMC inst = %d\n", __func__, inst);
755 }
756
757 bool utmi_phy_remotewake_detected(struct tegra_usb_phy *phy)
758 {
759         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
760         void __iomem *base = phy->regs;
761         unsigned  int inst = phy->inst;
762         u32 val;
763
764         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
765         val = readl(base + UTMIP_PMC_WAKEUP0);
766         if (val & EVENT_INT_ENB) {
767                 val = readl(pmc_base + UTMIP_UHSIC_STATUS);
768                 if (UTMIP_WAKE_ALARM(inst) & val) {
769                         val = readl(pmc_base + PMC_SLEEP_CFG);
770                         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
771                         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
772                         writel(val, pmc_base + PMC_SLEEP_CFG);
773
774                         val = readl(pmc_base + PMC_TRIGGERS);
775                         val |= UTMIP_CLR_WAKE_ALARM(inst);
776                         writel(val, pmc_base + PMC_TRIGGERS);
777
778                         val = readl(base + UTMIP_PMC_WAKEUP0);
779                         val &= ~EVENT_INT_ENB;
780                         writel(val, base + UTMIP_PMC_WAKEUP0);
781                         phy->remote_wakeup = true;
782                         return true;
783                 }
784         }
785         return false;
786 }
787
788 static void utmi_phy_enable_trking_data(struct tegra_usb_phy *phy)
789 {
790         void __iomem *base = IO_ADDRESS(TEGRA_USB_BASE);
791         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
792         static bool init_done = false;
793         u32 val;
794
795         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
796
797         /* Should be done only once after system boot */
798         if (init_done)
799                 return;
800
801         clk_enable(phy->utmi_pad_clk);
802         /* Bias pad MASTER_ENABLE=1 */
803         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
804         val |= BIAS_MASTER_PROG_VAL;
805         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
806
807         /* Setting the tracking length time */
808         val = readl(base + UTMIP_BIAS_CFG1);
809         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
810         val |= UTMIP_BIAS_PDTRK_COUNT(5);
811         writel(val, base + UTMIP_BIAS_CFG1);
812
813         /* Bias PDTRK is Shared and MUST be done from USB1 ONLY, PD_TRK=0 */
814         val = readl(base + UTMIP_BIAS_CFG1);
815         val &= ~UTMIP_BIAS_PDTRK_POWERDOWN;
816         writel(val, base + UTMIP_BIAS_CFG1);
817
818         val = readl(base + UTMIP_BIAS_CFG1);
819         val |= UTMIP_BIAS_PDTRK_POWERUP;
820         writel(val, base + UTMIP_BIAS_CFG1);
821
822         /* Wait for 25usec */
823         udelay(25);
824
825         /* Bias pad MASTER_ENABLE=0 */
826         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
827         val &= ~BIAS_MASTER_PROG_VAL;
828         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
829
830         /* Wait for 1usec */
831         udelay(1);
832
833         /* Bias pad MASTER_ENABLE=1 */
834         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
835         val |= BIAS_MASTER_PROG_VAL;
836         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
837
838         /* Read RCTRL and TCTRL from UTMIP space */
839         val = readl(base + UTMIP_BIAS_STS0);
840         utmip_rctrl_val = ffz(UTMIP_RCTRL_VAL(val));
841         utmip_tctrl_val = ffz(UTMIP_TCTRL_VAL(val));
842
843         /* PD_TRK=1 */
844         val = readl(base + UTMIP_BIAS_CFG1);
845         val |= UTMIP_BIAS_PDTRK_POWERDOWN;
846         writel(val, base + UTMIP_BIAS_CFG1);
847
848         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
849         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
850         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
851         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
852         clk_disable(phy->utmi_pad_clk);
853         init_done = true;
854 }
855
856 static void utmip_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy)
857 {
858         unsigned long val;
859         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
860         unsigned  int inst = phy->inst;
861
862         /* power down UTMIP interfaces */
863         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
864         val |= UTMIP_PWR(inst);
865         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
866
867         /* setup sleep walk usb controller */
868         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
869                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
870                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
871                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
872         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
873
874         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
875         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
876         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
877         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
878
879         /* Turn over pad configuration to PMC */
880         val = readl(pmc_base + PMC_SLEEP_CFG);
881         val &= ~UTMIP_WAKE_VAL(inst, ~0);
882         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE) |
883                 UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
884                 UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst);
885         writel(val, pmc_base + PMC_SLEEP_CFG);
886         PHY_DBG("%s ENABLE_PMC inst = %d\n", __func__, inst);
887 }
888
889 static void utmip_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
890 {
891         unsigned long val;
892         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
893         unsigned  int inst = phy->inst;
894
895         /* Disable PMC master mode by clearing MASTER_EN */
896         val = readl(pmc_base + PMC_SLEEP_CFG);
897         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
898                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
899         writel(val, pmc_base + PMC_SLEEP_CFG);
900         mdelay(1);
901         PHY_DBG("%s DISABLE_PMC inst = %d\n", __func__, inst);
902 }
903
904
905 #ifdef KERNEL_WARNING
906 static void usb_phy_power_down_pmc(void)
907 {
908         unsigned long val;
909         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
910
911         /* power down all 3 UTMIP interfaces */
912         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
913         val |= UTMIP_PWR(0) | UTMIP_PWR(1) | UTMIP_PWR(2);
914         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
915
916         /* turn on pad detectors */
917         writel(PMC_POWER_DOWN_MASK, pmc_base + PMC_USB_AO);
918
919         /* setup sleep walk fl all 3 usb controllers */
920         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
921                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
922                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
923                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
924         writel(val, pmc_base + PMC_SLEEPWALK_REG(0));
925         writel(val, pmc_base + PMC_SLEEPWALK_REG(1));
926         writel(val, pmc_base + PMC_SLEEPWALK_REG(2));
927
928         /* enable pull downs on HSIC PMC */
929         val = UHSIC_STROBE_RPD_A | UHSIC_DATA_RPD_A | UHSIC_STROBE_RPD_B |
930                 UHSIC_DATA_RPD_B | UHSIC_STROBE_RPD_C | UHSIC_DATA_RPD_C |
931                 UHSIC_STROBE_RPD_D | UHSIC_DATA_RPD_D;
932         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
933
934         /* Turn over pad configuration to PMC */
935         val = readl(pmc_base + PMC_SLEEP_CFG);
936         val &= ~UTMIP_WAKE_VAL(0, ~0);
937         val &= ~UTMIP_WAKE_VAL(1, ~0);
938         val &= ~UTMIP_WAKE_VAL(2, ~0);
939         val &= ~UHSIC_WAKE_VAL_P0(~0);
940         val |= UTMIP_WAKE_VAL(0, WAKE_VAL_NONE) | UHSIC_WAKE_VAL_P0(WAKE_VAL_NONE) |
941         UTMIP_WAKE_VAL(1, WAKE_VAL_NONE) | UTMIP_WAKE_VAL(2, WAKE_VAL_NONE) |
942         UTMIP_RCTRL_USE_PMC(0) | UTMIP_RCTRL_USE_PMC(1) | UTMIP_RCTRL_USE_PMC(2) |
943         UTMIP_TCTRL_USE_PMC(0) | UTMIP_TCTRL_USE_PMC(1) | UTMIP_TCTRL_USE_PMC(2) |
944         UTMIP_FSLS_USE_PMC(0) | UTMIP_FSLS_USE_PMC(1) | UTMIP_FSLS_USE_PMC(2) |
945         UTMIP_MASTER_ENABLE(0) | UTMIP_MASTER_ENABLE(1) | UTMIP_MASTER_ENABLE(2) |
946         UHSIC_MASTER_ENABLE_P0;
947         writel(val, pmc_base + PMC_SLEEP_CFG);
948 }
949 #endif
950
951 static int usb_phy_bringup_host_controller(struct tegra_usb_phy *phy)
952 {
953         unsigned long val;
954         void __iomem *base = phy->regs;
955
956         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
957         PHY_DBG("[%d] USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n", __LINE__,
958                 readl(base + USB_USBSTS), readl(base + USB_PORTSC),
959                                                         phy->port_speed);
960
961         /* Device is plugged in when system is in LP0 */
962         /* Bring up the controller from LP0*/
963         val = readl(base + USB_USBCMD);
964         val |= USB_CMD_RESET;
965         writel(val, base + USB_USBCMD);
966
967         if (usb_phy_reg_status_wait(base + USB_USBCMD,
968                 USB_CMD_RESET, 0, 2500) < 0) {
969                 pr_err("%s: timeout waiting for reset\n", __func__);
970         }
971
972         val = readl(base + USB_USBMODE);
973         val &= ~USB_USBMODE_MASK;
974         val |= USB_USBMODE_HOST;
975         writel(val, base + USB_USBMODE);
976         val = readl(base + HOSTPC1_DEVLC);
977         val &= ~HOSTPC1_DEVLC_PTS(~0);
978
979         if (phy->pdata->phy_intf == TEGRA_USB_PHY_INTF_HSIC)
980                 val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
981         else
982                 val |= HOSTPC1_DEVLC_STS;
983         writel(val, base + HOSTPC1_DEVLC);
984
985         /* Enable Port Power */
986         val = readl(base + USB_PORTSC);
987         val |= USB_PORTSC_PP;
988         writel(val, base + USB_PORTSC);
989         udelay(10);
990
991         /* Check if the phy resume from LP0. When the phy resume from LP0
992          * USB register will be reset.to zero */
993         if (!readl(base + USB_ASYNCLISTADDR)) {
994                 /* Program the field PTC based on the saved speed mode */
995                 val = readl(base + USB_PORTSC);
996                 val &= ~USB_PORTSC_PTC(~0);
997                 if ((phy->port_speed == USB_PHY_PORT_SPEED_HIGH) ||
998                         (phy->pdata->phy_intf == TEGRA_USB_PHY_INTF_HSIC))
999                         val |= USB_PORTSC_PTC(5);
1000                 else if (phy->port_speed == USB_PHY_PORT_SPEED_FULL)
1001                         val |= USB_PORTSC_PTC(6);
1002                 else if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
1003                         val |= USB_PORTSC_PTC(7);
1004                 writel(val, base + USB_PORTSC);
1005                 udelay(10);
1006
1007                 /* Disable test mode by setting PTC field to NORMAL_OP */
1008                 val = readl(base + USB_PORTSC);
1009                 val &= ~USB_PORTSC_PTC(~0);
1010                 writel(val, base + USB_PORTSC);
1011                 udelay(10);
1012         }
1013
1014         /* Poll until CCS is enabled */
1015         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
1016                                                  USB_PORTSC_CCS, 2000)) {
1017                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
1018         }
1019
1020         /* Poll until PE is enabled */
1021         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_PE,
1022                                                  USB_PORTSC_PE, 2000)) {
1023                 pr_err("%s: timeout waiting for USB_PORTSC_PE\n", __func__);
1024         }
1025
1026         /* Clear the PCI status, to avoid an interrupt taken upon resume */
1027         val = readl(base + USB_USBSTS);
1028         val |= USB_USBSTS_PCI;
1029         writel(val, base + USB_USBSTS);
1030
1031         if (!phy->remote_wakeup) {
1032                 /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
1033                 val = readl(base + USB_PORTSC);
1034                 if ((val & USB_PORTSC_PP) && (val & USB_PORTSC_PE)) {
1035                         val |= USB_PORTSC_SUSP;
1036                         writel(val, base + USB_PORTSC);
1037                         /* Need a 4ms delay before the controller goes to suspend */
1038                         mdelay(4);
1039
1040                         /* Wait until port suspend completes */
1041                         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_SUSP,
1042                                                          USB_PORTSC_SUSP, 1000)) {
1043                                 pr_err("%s: timeout waiting for PORT_SUSPEND\n",
1044                                                                         __func__);
1045                         }
1046                 }
1047         }
1048         PHY_DBG("[%d] USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n", __LINE__,
1049                 readl(base + USB_USBSTS), readl(base + USB_PORTSC),
1050                                                         phy->port_speed);
1051
1052         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1053                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1054         return 0;
1055 }
1056
1057 static void usb_phy_wait_for_sof(struct tegra_usb_phy *phy)
1058 {
1059         unsigned long val;
1060         void __iomem *base = phy->regs;
1061
1062         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1063
1064         val = readl(base + USB_USBSTS);
1065         writel(val, base + USB_USBSTS);
1066         udelay(20);
1067         /* wait for two SOFs */
1068         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1069                 USB_USBSTS_SRI, 2500))
1070                 pr_err("%s: timeout waiting for SOF\n", __func__);
1071
1072         val = readl(base + USB_USBSTS);
1073         writel(val, base + USB_USBSTS);
1074         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI, 0, 2500))
1075                 pr_err("%s: timeout waiting for SOF\n", __func__);
1076
1077         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1078                         USB_USBSTS_SRI, 2500))
1079                 pr_err("%s: timeout waiting for SOF\n", __func__);
1080
1081         udelay(20);
1082 }
1083
1084 static unsigned int utmi_phy_xcvr_setup_value(struct tegra_usb_phy *phy)
1085 {
1086         struct tegra_utmi_config *cfg = &phy->pdata->u_cfg.utmi;
1087         signed long val;
1088
1089         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1090
1091         if (cfg->xcvr_use_fuses) {
1092                 val = XCVR_SETUP(tegra_fuse_readl(FUSE_USB_CALIB_0));
1093                 if (cfg->xcvr_use_lsb) {
1094                         val = min((unsigned int) ((val & XCVR_SETUP_LSB_MASK)
1095                                 + cfg->xcvr_setup_offset),
1096                                 (unsigned int) XCVR_SETUP_LSB_MAX_VAL);
1097                         val |= (cfg->xcvr_setup & XCVR_SETUP_MSB_MASK);
1098                 } else {
1099                         if (cfg->xcvr_setup_offset <= UTMIP_XCVR_MAX_OFFSET)
1100                                 val = val + cfg->xcvr_setup_offset;
1101
1102                         if (val > UTMIP_XCVR_SETUP_MAX_VALUE) {
1103                                 val = UTMIP_XCVR_SETUP_MAX_VALUE;
1104                                 pr_info("%s: reset XCVR_SETUP to max value\n",
1105                                                 __func__);
1106                         } else if (val < UTMIP_XCVR_SETUP_MIN_VALUE) {
1107                                 val = UTMIP_XCVR_SETUP_MIN_VALUE;
1108                                 pr_info("%s: reset XCVR_SETUP to min value\n",
1109                                                 __func__);
1110                         }
1111                 }
1112         } else {
1113                 val = cfg->xcvr_setup;
1114         }
1115
1116         return (unsigned int) val;
1117 }
1118
1119 static int utmi_phy_open(struct tegra_usb_phy *phy)
1120 {
1121         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1122         unsigned long parent_rate, val;
1123         int i;
1124
1125         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1126
1127         phy->utmi_pad_clk = clk_get_sys("utmip-pad", NULL);
1128         if (IS_ERR(phy->utmi_pad_clk)) {
1129                 pr_err("%s: can't get utmip pad clock\n", __func__);
1130                 return PTR_ERR(phy->utmi_pad_clk);
1131         }
1132
1133         phy->utmi_xcvr_setup = utmi_phy_xcvr_setup_value(phy);
1134
1135         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
1136         for (i = 0; i < ARRAY_SIZE(utmip_freq_table); i++) {
1137                 if (utmip_freq_table[i].freq == parent_rate) {
1138                         phy->freq = &utmip_freq_table[i];
1139                         break;
1140                 }
1141         }
1142         if (!phy->freq) {
1143                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
1144                 return -EINVAL;
1145         }
1146
1147         /* Power-up the VBUS detector for UTMIP PHY */
1148         val = readl(pmc_base + PMC_USB_AO);
1149         val &= ~(PMC_USB_AO_VBUS_WAKEUP_PD_P0 | PMC_USB_AO_ID_PD_P0);
1150         writel((val | PMC_USB_AO_PD_P2), (pmc_base + PMC_USB_AO));
1151
1152         utmip_powerup_pmc_wake_detect(phy);
1153
1154         return 0;
1155 }
1156
1157 static void utmi_phy_close(struct tegra_usb_phy *phy)
1158 {
1159         unsigned long val;
1160         void __iomem *base = phy->regs;
1161
1162         DBG("%s inst:[%d]\n", __func__, phy->inst);
1163
1164         /* Disable PHY clock valid interrupts while going into suspend*/
1165         if (phy->pdata->u_data.host.hot_plug) {
1166                 val = readl(base + USB_SUSP_CTRL);
1167                 val &= ~USB_PHY_CLK_VALID_INT_ENB;
1168                 writel(val, base + USB_SUSP_CTRL);
1169         }
1170
1171         clk_put(phy->utmi_pad_clk);
1172 }
1173
1174 static int utmi_phy_pad_power_on(struct tegra_usb_phy *phy)
1175 {
1176         unsigned long val, flags;
1177         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1178
1179         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1180
1181         clk_enable(phy->utmi_pad_clk);
1182
1183         spin_lock_irqsave(&utmip_pad_lock, flags);
1184         utmip_pad_count++;
1185
1186         val = readl(pad_base + UTMIP_BIAS_CFG0);
1187         val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
1188         val |= UTMIP_HSSQUELCH_LEVEL(0x2) | UTMIP_HSDISCON_LEVEL(0x1) |
1189                 UTMIP_HSDISCON_LEVEL_MSB;
1190         writel(val, pad_base + UTMIP_BIAS_CFG0);
1191
1192         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1193
1194         clk_disable(phy->utmi_pad_clk);
1195
1196         return 0;
1197 }
1198
1199 static int utmi_phy_pad_power_off(struct tegra_usb_phy *phy)
1200 {
1201         unsigned long val, flags;
1202         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1203
1204         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1205
1206         clk_enable(phy->utmi_pad_clk);
1207         spin_lock_irqsave(&utmip_pad_lock, flags);
1208
1209         if (!utmip_pad_count) {
1210                 pr_err("%s: utmip pad already powered off\n", __func__);
1211                 goto out;
1212         }
1213         if (--utmip_pad_count == 0) {
1214                 val = readl(pad_base + UTMIP_BIAS_CFG0);
1215                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
1216                 val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) | UTMIP_HSDISCON_LEVEL(~0) |
1217                         UTMIP_HSDISCON_LEVEL_MSB);
1218                 writel(val, pad_base + UTMIP_BIAS_CFG0);
1219         }
1220 out:
1221         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1222         clk_disable(phy->utmi_pad_clk);
1223
1224         return 0;
1225 }
1226
1227 static int utmi_phy_irq(struct tegra_usb_phy *phy)
1228 {
1229         void __iomem *base = phy->regs;
1230         unsigned long val = 0;
1231
1232         if (phy->phy_clk_on) {
1233                 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1234                 DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1235                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1236                 DBG("USB_USBMODE[0x%x] USB_USBCMD[0x%x]\n",
1237                         readl(base + USB_USBMODE), readl(base + USB_USBCMD));
1238         }
1239
1240         usb_phy_fence_read(phy);
1241         /* check if there is any remote wake event */
1242         if (utmi_phy_remotewake_detected(phy))
1243                 pr_info("%s: utmip remote wake detected\n", __func__);
1244
1245         if (phy->pdata->u_data.host.hot_plug) {
1246                 val = readl(base + USB_SUSP_CTRL);
1247                 if ((val  & USB_PHY_CLK_VALID_INT_STS)) {
1248                         val &= ~USB_PHY_CLK_VALID_INT_ENB |
1249                                         USB_PHY_CLK_VALID_INT_STS;
1250                         writel(val , (base + USB_SUSP_CTRL));
1251                         pr_info("%s: usb device plugged-in\n", __func__);
1252                         val = readl(base + USB_USBSTS);
1253                         if (!(val  & USB_USBSTS_PCI))
1254                                 return IRQ_NONE;
1255                         val = readl(base + USB_PORTSC);
1256                         val &= ~(USB_PORTSC_WKCN | USB_PORTSC_RWC_BITS);
1257                         writel(val , (base + USB_PORTSC));
1258                 } else if (!phy->phy_clk_on) {
1259                         return IRQ_NONE;
1260                 }
1261         }
1262
1263         return IRQ_HANDLED;
1264 }
1265
1266 static void utmi_phy_enable_obs_bus(struct tegra_usb_phy *phy)
1267 {
1268         unsigned long val;
1269         void __iomem *base = phy->regs;
1270
1271         /* (2LS WAR)is not required for LS and FS devices and is only for HS */
1272         if ((phy->port_speed == USB_PHY_PORT_SPEED_LOW) ||
1273                 (phy->port_speed == USB_PHY_PORT_SPEED_FULL)) {
1274                 /* do not enable the OBS bus */
1275                 val = readl(base + UTMIP_MISC_CFG0);
1276                 val &= ~(UTMIP_DPDM_OBSERVE_SEL(~0));
1277                 writel(val, base + UTMIP_MISC_CFG0);
1278                 DBG("%s(%d) Disable OBS bus\n", __func__, __LINE__);
1279                 return;
1280         }
1281         /* Force DP/DM pulldown active for Host mode */
1282         val = readl(base + UTMIP_MISC_CFG0);
1283         val |= FORCE_PULLDN_DM | FORCE_PULLDN_DP |
1284                         COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS;
1285         writel(val, base + UTMIP_MISC_CFG0);
1286         val = readl(base + UTMIP_MISC_CFG0);
1287         val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1288         if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
1289                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
1290         else
1291                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
1292         writel(val, base + UTMIP_MISC_CFG0);
1293         udelay(1);
1294
1295         val = readl(base + UTMIP_MISC_CFG0);
1296         val |= UTMIP_DPDM_OBSERVE;
1297         writel(val, base + UTMIP_MISC_CFG0);
1298         udelay(10);
1299         DBG("%s(%d) Enable OBS bus\n", __func__, __LINE__);
1300         PHY_DBG("ENABLE_OBS_BUS\n");
1301 }
1302
1303 static int utmi_phy_disable_obs_bus(struct tegra_usb_phy *phy)
1304 {
1305         unsigned long val;
1306         void __iomem *base = phy->regs;
1307         unsigned long flags;
1308
1309         /* check if OBS bus is already enabled */
1310         val = readl(base + UTMIP_MISC_CFG0);
1311         if (val & UTMIP_DPDM_OBSERVE) {
1312                 PHY_DBG("DISABLE_OBS_BUS\n");
1313
1314                 /* disable ALL interrupts on current CPU */
1315                 local_irq_save(flags);
1316
1317                 /* Change the UTMIP OBS bus to drive SE0 */
1318                 val = readl(base + UTMIP_MISC_CFG0);
1319                 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1320                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_SE0;
1321                 writel(val, base + UTMIP_MISC_CFG0);
1322
1323                 /* Wait for 3us(2 LS bit times) */
1324                 udelay(3);
1325
1326                 /* Release UTMIP OBS bus */
1327                 val = readl(base + UTMIP_MISC_CFG0);
1328                 val &= ~UTMIP_DPDM_OBSERVE;
1329                 writel(val, base + UTMIP_MISC_CFG0);
1330
1331                 /* Release DP/DM pulldown for Host mode */
1332                 val = readl(base + UTMIP_MISC_CFG0);
1333                 val &= ~(FORCE_PULLDN_DM | FORCE_PULLDN_DP |
1334                                 COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS);
1335                 writel(val, base + UTMIP_MISC_CFG0);
1336
1337                 val = readl(base + USB_USBCMD);
1338                 val |= USB_USBCMD_RS;
1339                 writel(val, base + USB_USBCMD);
1340
1341                 /* restore ALL interrupts on current CPU */
1342                 local_irq_restore(flags);
1343
1344                 if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
1345                                                          USB_USBCMD_RS, 2000)) {
1346                         pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
1347                         return -ETIMEDOUT;
1348                 }
1349         }
1350         return 0;
1351 }
1352
1353 static int utmi_phy_post_resume(struct tegra_usb_phy *phy)
1354 {
1355         unsigned long val;
1356         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1357         unsigned  int inst = phy->inst;
1358
1359         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1360         val = readl(pmc_base + PMC_SLEEP_CFG);
1361         /* if PMC is not disabled by now then disable it */
1362         if (val & UTMIP_MASTER_ENABLE(inst)) {
1363                 utmip_phy_disable_pmc_bus_ctrl(phy);
1364         }
1365
1366         utmi_phy_disable_obs_bus(phy);
1367
1368         return 0;
1369 }
1370
1371 static int utmi_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1372 {
1373         unsigned long val;
1374         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1375         void __iomem *base = phy->regs;
1376         unsigned  int inst = phy->inst;
1377
1378         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1379         phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
1380                         HOSTPC1_DEVLC_PSPD_MASK;
1381
1382         if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH) {
1383                 /* Disable interrupts */
1384                 writel(0, base + USB_USBINTR);
1385                 /* Clear the run bit to stop SOFs - 2LS WAR */
1386                 val = readl(base + USB_USBCMD);
1387                 val &= ~USB_USBCMD_RS;
1388                 writel(val, base + USB_USBCMD);
1389                 if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
1390                                                          USB_USBSTS_HCH, 2000)) {
1391                         pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
1392                 }
1393         }
1394
1395         val = readl(pmc_base + PMC_SLEEP_CFG);
1396         if (val & UTMIP_MASTER_ENABLE(inst)) {
1397                 if (!remote_wakeup)
1398                         utmip_phy_disable_pmc_bus_ctrl(phy);
1399         } else {
1400                 utmi_phy_enable_obs_bus(phy);
1401         }
1402
1403         return 0;
1404 }
1405
1406 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
1407 {
1408         unsigned long val;
1409         void __iomem *base = phy->regs;
1410
1411         PHY_DBG("%s(%d) inst:[%d] BEGIN\n", __func__, __LINE__, phy->inst);
1412         if (!phy->phy_clk_on) {
1413                 PHY_DBG("%s(%d) inst:[%d] phy clk is already off\n",
1414                                         __func__, __LINE__, phy->inst);
1415                 return 0;
1416         }
1417
1418         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1419                 utmip_powerdown_pmc_wake_detect(phy);
1420
1421                 val = readl(base + USB_SUSP_CTRL);
1422                 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
1423                 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
1424                 writel(val, base + USB_SUSP_CTRL);
1425
1426                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1427                 val |= UTMIP_PD_CHRG;
1428                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1429         } else {
1430                 phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
1431                                 HOSTPC1_DEVLC_PSPD_MASK;
1432
1433                 /* Disable interrupts */
1434                 writel(0, base + USB_USBINTR);
1435
1436                 /* Clear the run bit to stop SOFs - 2LS WAR */
1437                 val = readl(base + USB_USBCMD);
1438                 val &= ~USB_USBCMD_RS;
1439                 writel(val, base + USB_USBCMD);
1440
1441                 if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
1442                                                          USB_USBSTS_HCH, 2000)) {
1443                         pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
1444                 }
1445                 utmip_setup_pmc_wake_detect(phy);
1446         }
1447
1448         if (!phy->pdata->u_data.host.hot_plug) {
1449                 val = readl(base + UTMIP_XCVR_CFG0);
1450                 val |= (UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
1451                          UTMIP_FORCE_PDZI_POWERDOWN);
1452                 writel(val, base + UTMIP_XCVR_CFG0);
1453         }
1454
1455         val = readl(base + UTMIP_XCVR_CFG1);
1456         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1457                    UTMIP_FORCE_PDDR_POWERDOWN;
1458         writel(val, base + UTMIP_XCVR_CFG1);
1459
1460         val = readl(base + UTMIP_BIAS_CFG1);
1461         val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
1462         writel(val, base + UTMIP_BIAS_CFG1);
1463
1464         utmi_phy_pad_power_off(phy);
1465
1466         if (phy->pdata->u_data.host.hot_plug) {
1467                 bool enable_hotplug = true;
1468                 /* if it is OTG port then make sure to enable hot-plug feature
1469                    only if host adaptor is connected, i.e id is low */
1470                 if (phy->pdata->port_otg) {
1471                         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1472                         enable_hotplug = (val & USB_ID_STATUS) ? false : true;
1473                 }
1474                 if (enable_hotplug) {
1475                         val = readl(base + USB_PORTSC);
1476                         val |= USB_PORTSC_WKCN;
1477                         writel(val, base + USB_PORTSC);
1478
1479                         val = readl(base + USB_SUSP_CTRL);
1480                         val |= USB_PHY_CLK_VALID_INT_ENB;
1481                         writel(val, base + USB_SUSP_CTRL);
1482                 } else {
1483                         /* Disable PHY clock valid interrupts while going into suspend*/
1484                         val = readl(base + USB_SUSP_CTRL);
1485                         val &= ~USB_PHY_CLK_VALID_INT_ENB;
1486                         writel(val, base + USB_SUSP_CTRL);
1487                 }
1488         }
1489
1490         val = readl(base + HOSTPC1_DEVLC);
1491         val |= HOSTPC1_DEVLC_PHCD;
1492         writel(val, base + HOSTPC1_DEVLC);
1493
1494         if (!phy->pdata->u_data.host.hot_plug) {
1495                 val = readl(base + USB_SUSP_CTRL);
1496                 val |= UTMIP_RESET;
1497                 writel(val, base + USB_SUSP_CTRL);
1498         }
1499
1500         phy->phy_clk_on = false;
1501         phy->hw_accessible = false;
1502
1503         PHY_DBG("%s(%d) inst:[%d] END\n", __func__, __LINE__, phy->inst);
1504
1505         return 0;
1506 }
1507
1508
1509 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
1510 {
1511         unsigned long val;
1512         void __iomem *base = phy->regs;
1513         struct tegra_utmi_config *config = &phy->pdata->u_cfg.utmi;
1514
1515         PHY_DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1516         if (phy->phy_clk_on) {
1517                 PHY_DBG("%s(%d) inst:[%d] phy clk is already On\n",
1518                                         __func__, __LINE__, phy->inst);
1519                 return 0;
1520         }
1521         val = readl(base + USB_SUSP_CTRL);
1522         val |= UTMIP_RESET;
1523         writel(val, base + USB_SUSP_CTRL);
1524
1525         val = readl(base + UTMIP_TX_CFG0);
1526         val |= UTMIP_FS_PREABMLE_J;
1527         writel(val, base + UTMIP_TX_CFG0);
1528
1529         val = readl(base + UTMIP_HSRX_CFG0);
1530         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
1531         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
1532         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
1533         writel(val, base + UTMIP_HSRX_CFG0);
1534
1535         val = readl(base + UTMIP_HSRX_CFG1);
1536         val &= ~UTMIP_HS_SYNC_START_DLY(~0);
1537         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
1538         writel(val, base + UTMIP_HSRX_CFG1);
1539
1540         val = readl(base + UTMIP_DEBOUNCE_CFG0);
1541         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
1542         val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
1543         writel(val, base + UTMIP_DEBOUNCE_CFG0);
1544
1545         val = readl(base + UTMIP_MISC_CFG0);
1546         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
1547         writel(val, base + UTMIP_MISC_CFG0);
1548
1549         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1550                 val = readl(base + USB_SUSP_CTRL);
1551                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
1552                 writel(val, base + USB_SUSP_CTRL);
1553
1554                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1555                 val &= ~UTMIP_PD_CHRG;
1556                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1557         } else {
1558                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1559                 val |= UTMIP_PD_CHRG;
1560                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1561         }
1562
1563         utmi_phy_pad_power_on(phy);
1564
1565         val = readl(base + UTMIP_XCVR_CFG0);
1566         val &= ~(UTMIP_XCVR_LSBIAS_SEL | UTMIP_FORCE_PD_POWERDOWN |
1567                  UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN |
1568                  UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_LSFSLEW(~0) |
1569                  UTMIP_XCVR_LSRSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
1570         val |= UTMIP_XCVR_SETUP(phy->utmi_xcvr_setup);
1571         val |= UTMIP_XCVR_SETUP_MSB(XCVR_SETUP_MSB_CALIB(phy->utmi_xcvr_setup));
1572         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
1573         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
1574         if (!config->xcvr_use_lsb)
1575                 val |= UTMIP_XCVR_HSSLEW_MSB(0x8);
1576         writel(val, base + UTMIP_XCVR_CFG0);
1577
1578         val = readl(base + UTMIP_XCVR_CFG1);
1579         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1580                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
1581         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
1582         writel(val, base + UTMIP_XCVR_CFG1);
1583
1584         val = readl(base + UTMIP_BIAS_CFG1);
1585         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
1586         val |= UTMIP_BIAS_PDTRK_COUNT(phy->freq->pdtrk_count);
1587         writel(val, base + UTMIP_BIAS_CFG1);
1588
1589         val = readl(base + UTMIP_SPARE_CFG0);
1590         val &= ~FUSE_SETUP_SEL;
1591         val |= FUSE_ATERM_SEL;
1592         writel(val, base + UTMIP_SPARE_CFG0);
1593
1594         val = readl(base + USB_SUSP_CTRL);
1595         val |= UTMIP_PHY_ENABLE;
1596         writel(val, base + USB_SUSP_CTRL);
1597
1598         val = readl(base + USB_SUSP_CTRL);
1599         val &= ~UTMIP_RESET;
1600         writel(val, base + USB_SUSP_CTRL);
1601
1602         val = readl(base + HOSTPC1_DEVLC);
1603         val &= ~HOSTPC1_DEVLC_PHCD;
1604         writel(val, base + HOSTPC1_DEVLC);
1605
1606         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1607                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500))
1608                 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
1609
1610         utmi_phy_enable_trking_data(phy);
1611
1612         if (phy->inst == 2)
1613                 writel(0, base + ICUSB_CTRL);
1614
1615         val = readl(base + USB_USBMODE);
1616         val &= ~USB_USBMODE_MASK;
1617         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST)
1618                 val |= USB_USBMODE_HOST;
1619         else
1620                 val |= USB_USBMODE_DEVICE;
1621         writel(val, base + USB_USBMODE);
1622
1623         val = readl(base + HOSTPC1_DEVLC);
1624         val &= ~HOSTPC1_DEVLC_PTS(~0);
1625         val |= HOSTPC1_DEVLC_STS;
1626         writel(val, base + HOSTPC1_DEVLC);
1627
1628         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE)
1629                 utmip_powerup_pmc_wake_detect(phy);
1630         phy->phy_clk_on = true;
1631         phy->hw_accessible = true;
1632         PHY_DBG("%s(%d) End inst:[%d]\n", __func__, __LINE__, phy->inst);
1633         return 0;
1634 }
1635
1636 static void utmi_phy_restore_start(struct tegra_usb_phy *phy)
1637 {
1638         unsigned long val;
1639         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1640         int inst = phy->inst;
1641
1642         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1643         val = readl(pmc_base + UTMIP_UHSIC_STATUS);
1644         /* Check whether we wake up from the remote resume.
1645            For lp1 case, pmc is not responsible for waking the
1646            system, it's the flow controller and hence
1647            UTMIP_WALK_PTR_VAL(inst) will return 0.
1648            Also, for lp1 case phy->remote_wakeup will already be set
1649            to true by utmi_phy_irq() when the remote wakeup happens.
1650            Hence change the logic in the else part to enter only
1651            if phy->remote_wakeup is not set to true by the
1652            utmi_phy_irq(). */
1653         if (UTMIP_WALK_PTR_VAL(inst) & val) {
1654                 phy->remote_wakeup = true;
1655         } else if(!phy->remote_wakeup) {
1656                 if (!((UTMIP_USBON_VAL(phy->inst) |
1657                         UTMIP_USBOP_VAL(phy->inst)) & val)) {
1658                                 utmip_phy_disable_pmc_bus_ctrl(phy);
1659                 }
1660         }
1661         utmi_phy_enable_obs_bus(phy);
1662 }
1663
1664 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
1665 {
1666         unsigned long val;
1667         void __iomem *base = phy->regs;
1668         int wait_time_us = 25000; /* FPR should be set by this time */
1669
1670         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1671         /* check whether we wake up from the remote resume */
1672         if (phy->remote_wakeup) {
1673                 /* wait until SUSPEND and RESUME bit is cleared on remote resume */
1674                 do {
1675                         val = readl(base + USB_PORTSC);
1676                         udelay(1);
1677                         if (wait_time_us == 0) {
1678                                 PHY_DBG("%s PMC REMOTE WAKEUP FPR timeout val = 0x%x instance = %d\n", __func__, val, phy->inst);
1679                                 utmip_phy_disable_pmc_bus_ctrl(phy);
1680                                 utmi_phy_post_resume(phy);
1681                                 return;
1682                         }
1683                         wait_time_us--;
1684                 } while (val & (USB_PORTSC_RESUME | USB_PORTSC_SUSP));
1685
1686                 /* wait for 25 ms to port resume complete */
1687                 msleep(25);
1688                 /* disable PMC master control */
1689                 utmip_phy_disable_pmc_bus_ctrl(phy);
1690
1691                 /* Clear PCI and SRI bits to avoid an interrupt upon resume */
1692                 val = readl(base + USB_USBSTS);
1693                 writel(val, base + USB_USBSTS);
1694                 /* wait to avoid SOF if there is any */
1695                 if (usb_phy_reg_status_wait(base + USB_USBSTS,
1696                         USB_USBSTS_SRI, USB_USBSTS_SRI, 2500) < 0) {
1697                         pr_err("%s: timeout waiting for SOF\n", __func__);
1698                 }
1699                 utmi_phy_post_resume(phy);
1700         }
1701 }
1702
1703 static int utmi_phy_resume(struct tegra_usb_phy *phy)
1704 {
1705         int status = 0;
1706         unsigned long val;
1707         void __iomem *base = phy->regs;
1708
1709         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1710         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) {
1711                 if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
1712                         utmi_phy_restore_start(phy);
1713                         usb_phy_bringup_host_controller(phy);
1714                         utmi_phy_restore_end(phy);
1715                 } else {
1716                         /* device is plugged in when system is in LP0 */
1717                         /* bring up the controller from LP0*/
1718                         val = readl(base + USB_USBCMD);
1719                         val |= USB_CMD_RESET;
1720                         writel(val, base + USB_USBCMD);
1721
1722                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1723                                 USB_CMD_RESET, 0, 2500) < 0) {
1724                                 pr_err("%s: timeout waiting for reset\n", __func__);
1725                         }
1726
1727                         val = readl(base + USB_USBMODE);
1728                         val &= ~USB_USBMODE_MASK;
1729                         val |= USB_USBMODE_HOST;
1730                         writel(val, base + USB_USBMODE);
1731
1732                         val = readl(base + HOSTPC1_DEVLC);
1733                         val &= ~HOSTPC1_DEVLC_PTS(~0);
1734                         val |= HOSTPC1_DEVLC_STS;
1735                         writel(val, base + HOSTPC1_DEVLC);
1736
1737                         writel(USB_USBCMD_RS, base + USB_USBCMD);
1738
1739                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1740                                 USB_USBCMD_RS, USB_USBCMD_RS, 2500) < 0) {
1741                                 pr_err("%s: timeout waiting for run bit\n", __func__);
1742                         }
1743
1744                         /* Enable Port Power */
1745                         val = readl(base + USB_PORTSC);
1746                         val |= USB_PORTSC_PP;
1747                         writel(val, base + USB_PORTSC);
1748                         udelay(10);
1749
1750                         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1751                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1752                 }
1753         }
1754
1755         return status;
1756 }
1757
1758 bool utmi_phy_charger_detect(struct tegra_usb_phy *phy)
1759 {
1760         unsigned long val;
1761         void __iomem *base = phy->regs;
1762         bool status;
1763
1764         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1765         if (phy->pdata->op_mode != TEGRA_USB_OPMODE_DEVICE) {
1766                 /* Charger detection is not there for ULPI
1767                  * return Charger not available */
1768                 return false;
1769         }
1770
1771         /* Enable charger detection logic */
1772         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1773         val |= UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN;
1774         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1775
1776         /* Source should be on for 100 ms as per USB charging spec */
1777         msleep(TDP_SRC_ON_MS);
1778
1779         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1780         /* If charger is not connected disable the interrupt */
1781         val &= ~VDAT_DET_INT_EN;
1782         val |= VDAT_DET_CHG_DET;
1783         writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
1784
1785         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1786         if (val & VDAT_DET_STS)
1787                 status = true;
1788         else
1789                 status = false;
1790
1791         /* Disable charger detection logic */
1792         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1793         val &= ~(UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN);
1794         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1795
1796         /* Delay of 40 ms before we pull the D+ as per battery charger spec */
1797         msleep(TDPSRC_CON_MS);
1798
1799         return status;
1800 }
1801
1802 static void uhsic_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
1803 {
1804         unsigned long val;
1805         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1806
1807         /* turn on pad detectors for HSIC*/
1808         val = readl(pmc_base + PMC_USB_AO);
1809         val &= ~(HSIC_RESERVED_P0 | STROBE_VAL_PD_P0 | DATA_VAL_PD_P0);
1810         writel(val, pmc_base + PMC_USB_AO);
1811
1812         /* Disable PMC master mode by clearing MASTER_EN */
1813         val = readl(pmc_base + PMC_SLEEP_CFG);
1814         val &= ~(UHSIC_MASTER_ENABLE_P0);
1815         writel(val, pmc_base + PMC_SLEEP_CFG);
1816         mdelay(1);
1817 }
1818
1819 static void uhsic_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy)
1820 {
1821         unsigned long val;
1822         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1823
1824         DBG("%s:%d\n", __func__, __LINE__);
1825
1826         /* turn off pad detectors for HSIC*/
1827         val = readl(pmc_base + PMC_USB_AO);
1828         val |= (HSIC_RESERVED_P0 | STROBE_VAL_PD_P0 | DATA_VAL_PD_P0);
1829         writel(val, pmc_base + PMC_USB_AO);
1830
1831         /* enable pull downs on HSIC PMC */
1832         val = UHSIC_STROBE_RPD_A | UHSIC_DATA_RPD_A | UHSIC_STROBE_RPD_B |
1833                 UHSIC_DATA_RPD_B | UHSIC_STROBE_RPD_C | UHSIC_DATA_RPD_C |
1834                 UHSIC_STROBE_RPD_D | UHSIC_DATA_RPD_D;
1835         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1836
1837         /* Turn over pad configuration to PMC */
1838         val = readl(pmc_base + PMC_SLEEP_CFG);
1839         val &= ~UHSIC_WAKE_VAL_P0(~0);
1840         val |= UHSIC_WAKE_VAL_P0(WAKE_VAL_NONE) | UHSIC_MASTER_ENABLE_P0;
1841         writel(val, pmc_base + PMC_SLEEP_CFG);
1842 }
1843
1844 static void uhsic_setup_pmc_wake_detect(struct tegra_usb_phy *phy)
1845 {
1846         unsigned long val;
1847         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1848         void __iomem *base = phy->regs;
1849         bool port_connected;
1850
1851         DBG("%s:%d\n", __func__, __LINE__);
1852
1853         /* check for port connect status */
1854         val = readl(base + USB_PORTSC);
1855         port_connected = val & USB_PORTSC_CCS;
1856
1857         if (!port_connected)
1858                 return;
1859
1860         /*Set PMC MASTER bits to do the following
1861         * a. Take over the hsic drivers
1862         * b. set up such that it will take over resume
1863         *        if remote wakeup is detected
1864         * Prepare PMC to take over suspend-wake detect-drive resume until USB
1865         * controller ready
1866         */
1867
1868         /* disable master enable in PMC */
1869         val = readl(pmc_base + PMC_SLEEP_CFG);
1870         val &= ~UHSIC_MASTER_ENABLE_P0;
1871         writel(val, pmc_base + PMC_SLEEP_CFG);
1872
1873         /* UTMIP_PWR_PX=1 for power savings mode */
1874         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
1875         val |= UHSIC_PWR;
1876         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
1877
1878         /* Make sure nothing is happening on the line with respect to PMC */
1879         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
1880         val &= ~UHSIC_STROBE_VAL;
1881         val &= ~UHSIC_DATA_VAL;
1882         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
1883
1884         /* Clear walk enable */
1885         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
1886         val &= ~UHSIC_LINEVAL_WALK_EN;
1887         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
1888
1889         /* Make sure wake value for line is none */
1890         val = readl(pmc_base + PMC_SLEEP_CFG);
1891         val &= ~UHSIC_WAKE_VAL(WAKE_VAL_ANY);
1892         val |= UHSIC_WAKE_VAL(WAKE_VAL_NONE);
1893         writel(val, pmc_base + PMC_SLEEP_CFG);
1894
1895         /* turn on pad detectors */
1896         val = readl(pmc_base + PMC_USB_AO);
1897         val &= ~(STROBE_VAL_PD_P0 | DATA_VAL_PD_P0);
1898         writel(val, pmc_base + PMC_USB_AO);
1899
1900         /* Add small delay before usb detectors provide stable line values */
1901         udelay(1);
1902
1903         /* Enable which type of event can trigger a walk,
1904         * in this case usb_line_wake */
1905         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
1906         val |= UHSIC_LINEVAL_WALK_EN;
1907         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
1908
1909         /* program walk sequence, maintain a J, followed by a driven K
1910         * to signal a resume once an wake event is detected */
1911
1912         val = readl(pmc_base + PMC_SLEEPWALK_UHSIC);
1913
1914         val &= ~UHSIC_DATA_RPU_A;
1915         val |=  UHSIC_DATA_RPD_A;
1916         val &= ~UHSIC_STROBE_RPD_A;
1917         val |=  UHSIC_STROBE_RPU_A;
1918
1919         val &= ~UHSIC_DATA_RPD_B;
1920         val |=  UHSIC_DATA_RPU_B;
1921         val &= ~UHSIC_STROBE_RPU_B;
1922         val |=  UHSIC_STROBE_RPD_B;
1923
1924         val &= ~UHSIC_DATA_RPD_C;
1925         val |=  UHSIC_DATA_RPU_C;
1926         val &= ~UHSIC_STROBE_RPU_C;
1927         val |=  UHSIC_STROBE_RPD_C;
1928
1929         val &= ~UHSIC_DATA_RPD_D;
1930         val |=  UHSIC_DATA_RPU_D;
1931         val &= ~UHSIC_STROBE_RPU_D;
1932         val |=  UHSIC_STROBE_RPD_D;
1933         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1934
1935         phy->remote_wakeup = false;
1936
1937         /* Setting Wake event*/
1938         val = readl(pmc_base + PMC_SLEEP_CFG);
1939         val &= ~UHSIC_WAKE_VAL(WAKE_VAL_ANY);
1940         val |= UHSIC_WAKE_VAL(WAKE_VAL_SD10);
1941         writel(val, pmc_base + PMC_SLEEP_CFG);
1942
1943         /* Clear the walk pointers and wake alarm */
1944         val = readl(pmc_base + PMC_TRIGGERS);
1945         val |= UHSIC_CLR_WAKE_ALARM_P0 | UHSIC_CLR_WALK_PTR_P0;
1946         writel(val, pmc_base + PMC_TRIGGERS);
1947
1948         /* Turn over pad configuration to PMC  for line wake events*/
1949         val = readl(pmc_base + PMC_SLEEP_CFG);
1950         val |= UHSIC_MASTER_ENABLE;
1951         writel(val, pmc_base + PMC_SLEEP_CFG);
1952
1953         val = readl(base + UHSIC_PMC_WAKEUP0);
1954         val |= EVENT_INT_ENB;
1955         writel(val, base + UHSIC_PMC_WAKEUP0);
1956
1957         DBG("%s:PMC enabled for HSIC remote wakeup\n", __func__);
1958 }
1959
1960 static void uhsic_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy)
1961 {
1962         unsigned long val;
1963         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1964         void __iomem *base = phy->regs;
1965
1966         DBG("%s (%d)\n", __func__, __LINE__);
1967         val = readl(pmc_base + PMC_SLEEP_CFG);
1968         val &= ~UHSIC_WAKE_VAL(WAKE_VAL_ANY);
1969         val |= UHSIC_WAKE_VAL(WAKE_VAL_NONE);
1970         writel(val, pmc_base + PMC_SLEEP_CFG);
1971
1972         val = readl(base + UHSIC_PMC_WAKEUP0);
1973         val &= ~EVENT_INT_ENB;
1974         writel(val, base + UHSIC_PMC_WAKEUP0);
1975
1976         /* Disable PMC master mode by clearing MASTER_EN */
1977         val = readl(pmc_base + PMC_SLEEP_CFG);
1978         val &= ~(UHSIC_MASTER_ENABLE);
1979         writel(val, pmc_base + PMC_SLEEP_CFG);
1980
1981         /* turn off pad detectors */
1982         val = readl(pmc_base + PMC_USB_AO);
1983         val |= (STROBE_VAL_PD_P0 | DATA_VAL_PD_P0);
1984         writel(val, pmc_base + PMC_USB_AO);
1985
1986         val = readl(pmc_base + PMC_TRIGGERS);
1987         val |= (UHSIC_CLR_WALK_PTR_P0 | UHSIC_CLR_WAKE_ALARM_P0);
1988         writel(val, pmc_base + PMC_TRIGGERS);
1989
1990         phy->remote_wakeup = false;
1991 }
1992
1993 static bool uhsic_phy_remotewake_detected(struct tegra_usb_phy *phy)
1994 {
1995         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1996         void __iomem *base = phy->regs;
1997         u32 val;
1998
1999         val = readl(base + UHSIC_PMC_WAKEUP0);
2000         if (val & EVENT_INT_ENB) {
2001                 val = readl(pmc_base + UTMIP_UHSIC_STATUS);
2002                 if (UHSIC_WAKE_ALARM & val) {
2003                         val = readl(pmc_base + PMC_SLEEP_CFG);
2004                         val &= ~UHSIC_WAKE_VAL(WAKE_VAL_ANY);
2005                         val |= UHSIC_WAKE_VAL(WAKE_VAL_NONE);
2006                         writel(val, pmc_base + PMC_SLEEP_CFG);
2007
2008                         val = readl(pmc_base + PMC_TRIGGERS);
2009                         val |= UHSIC_CLR_WAKE_ALARM_P0;
2010                         writel(val, pmc_base + PMC_TRIGGERS);
2011
2012                         val = readl(base + UHSIC_PMC_WAKEUP0);
2013                         val &= ~EVENT_INT_ENB;
2014                         writel(val, base + UHSIC_PMC_WAKEUP0);
2015                         phy->remote_wakeup = true;
2016                         DBG("%s:PMC remote wakeup detected for HSIC\n", __func__);
2017                         return true;
2018                 }
2019         }
2020         return false;
2021 }
2022
2023 static int uhsic_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
2024 {
2025         DBG("%s(%d)\n", __func__, __LINE__);
2026
2027         if (!remote_wakeup)
2028                 usb_phy_wait_for_sof(phy);
2029
2030         return 0;
2031 }
2032
2033 static int uhsic_phy_post_resume(struct tegra_usb_phy *phy)
2034 {
2035         unsigned long val;
2036         void __iomem *base = phy->regs;
2037
2038         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2039         val = readl(base + USB_TXFILLTUNING);
2040         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
2041                 val = USB_FIFO_TXFILL_THRES(0x10);
2042                 writel(val, base + USB_TXFILLTUNING);
2043         }
2044
2045         return 0;
2046 }
2047
2048 static void uhsic_phy_restore_start(struct tegra_usb_phy *phy)
2049 {
2050         unsigned long val;
2051         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
2052         void __iomem *base = phy->regs;
2053
2054         val = readl(pmc_base + UTMIP_UHSIC_STATUS);
2055
2056         /* check whether we wake up from the remote resume */
2057         if (UHSIC_WALK_PTR_VAL & val) {
2058                 phy->remote_wakeup = true;
2059                 pr_info("%s: uhsic remote wakeup detected\n", __func__);
2060         } else {
2061                 if (!((UHSIC_STROBE_VAL_P0 | UHSIC_DATA_VAL_P0) & val)) {
2062                                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2063                 } else {
2064                         DBG("%s(%d): setting pretend connect\n", __func__, __LINE__);
2065                         val = readl(base + UHSIC_CMD_CFG0);
2066                         val |= UHSIC_PRETEND_CONNECT_DETECT;
2067                         writel(val, base + UHSIC_CMD_CFG0);
2068                 }
2069         }
2070 }
2071
2072 static void uhsic_phy_restore_end(struct tegra_usb_phy *phy)
2073 {
2074
2075         unsigned long val;
2076         void __iomem *base = phy->regs;
2077         int wait_time_us = 25000; /* FPR should be set by this time */
2078
2079         DBG("%s(%d)\n", __func__, __LINE__);
2080
2081         /* check whether we wake up from the remote resume */
2082         if (phy->remote_wakeup) {
2083                 /* wait until FPR bit is set automatically on remote resume */
2084                 do {
2085                         val = readl(base + USB_PORTSC);
2086                         udelay(1);
2087                         if (wait_time_us == 0) {
2088                                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2089                                 uhsic_phy_post_resume(phy);
2090                                 return;
2091                         }
2092                         wait_time_us--;
2093                 } while (val & (USB_PORTSC_RESUME | USB_PORTSC_SUSP));
2094
2095                 /* wait for 25 ms to port resume complete */
2096                 msleep(25);
2097                 /* disable PMC master control */
2098                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2099
2100                 /* Clear PCI and SRI bits to avoid an interrupt upon resume */
2101                 val = readl(base + USB_USBSTS);
2102                 writel(val, base + USB_USBSTS);
2103                 /* wait to avoid SOF if there is any */
2104                 if (usb_phy_reg_status_wait(base + USB_USBSTS,
2105                         USB_USBSTS_SRI, USB_USBSTS_SRI, 2500)) {
2106                         pr_warn("%s: timeout waiting for SOF\n", __func__);
2107                 }
2108                 uhsic_phy_post_resume(phy);
2109         } else {
2110                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2111         }
2112
2113         /* Set RUN bit */
2114         val = readl(base + USB_USBCMD);
2115         val |= USB_USBCMD_RS;
2116         writel(val, base + USB_USBCMD);
2117         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2118                                                  USB_USBCMD_RS, 2000)) {
2119                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2120                 return;
2121         }
2122 }
2123
2124 static int hsic_rail_enable(struct tegra_usb_phy *phy)
2125 {
2126         int ret;
2127
2128         if (phy->hsic_reg == NULL) {
2129                 phy->hsic_reg = regulator_get(NULL, "avdd_hsic");
2130                 if (IS_ERR_OR_NULL(phy->hsic_reg)) {
2131                         pr_err("HSIC: Could not get regulator avdd_hsic\n");
2132                         phy->hsic_reg = NULL;
2133                         return PTR_ERR(phy->hsic_reg);
2134                 }
2135         }
2136
2137         ret = regulator_enable(phy->hsic_reg);
2138         if (ret < 0) {
2139                 pr_err("%s avdd_hsic could not be enabled\n", __func__);
2140                 return ret;
2141         }
2142
2143         return 0;
2144 }
2145
2146 static int hsic_rail_disable(struct tegra_usb_phy *phy)
2147 {
2148         int ret;
2149
2150         if (phy->hsic_reg == NULL) {
2151                 pr_warn("%s: unbalanced disable\n", __func__);
2152                 return -EIO;
2153         }
2154
2155         ret = regulator_disable(phy->hsic_reg);
2156         if (ret < 0) {
2157                 pr_err("HSIC regulator avdd_hsic cannot be disabled\n");
2158                 return ret;
2159         }
2160
2161         return 0;
2162 }
2163
2164 static int uhsic_phy_open(struct tegra_usb_phy *phy)
2165 {
2166         unsigned long parent_rate;
2167         int i;
2168         int ret;
2169
2170         phy->hsic_reg = NULL;
2171         ret = hsic_rail_enable(phy);
2172         if (ret < 0) {
2173                 pr_err("%s avdd_hsic could not be enabled\n", __func__);
2174                 return ret;
2175         }
2176
2177         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2178         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
2179         for (i = 0; i < ARRAY_SIZE(uhsic_freq_table); i++) {
2180                 if (uhsic_freq_table[i].freq == parent_rate) {
2181                         phy->freq = &uhsic_freq_table[i];
2182                         break;
2183                 }
2184         }
2185         if (!phy->freq) {
2186                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
2187                 return -EINVAL;
2188         }
2189
2190         uhsic_powerup_pmc_wake_detect(phy);
2191
2192         return 0;
2193 }
2194
2195 static void uhsic_phy_close(struct tegra_usb_phy *phy)
2196 {
2197         int ret;
2198
2199         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2200         uhsic_powerdown_pmc_wake_detect(phy);
2201
2202         ret = hsic_rail_disable(phy);
2203         if (ret < 0)
2204                 pr_err("%s avdd_hsic could not be disabled\n", __func__);
2205 }
2206
2207 static int uhsic_phy_irq(struct tegra_usb_phy *phy)
2208 {
2209         usb_phy_fence_read(phy);
2210         /* check if there is any remote wake event */
2211         if (uhsic_phy_remotewake_detected(phy))
2212                 pr_info("%s: uhsic remote wake detected\n", __func__);
2213         return IRQ_HANDLED;
2214 }
2215
2216 static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
2217 {
2218         unsigned long val;
2219         void __iomem *base = phy->regs;
2220
2221         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2222
2223         if (phy->phy_clk_on) {
2224                 DBG("%s(%d) inst:[%d] phy clk is already On\n",
2225                                         __func__, __LINE__, phy->inst);
2226                 return 0;
2227         }
2228
2229         val = readl(base + UHSIC_PADS_CFG1);
2230         val &= ~(UHSIC_PD_BG | UHSIC_PD_TRK | UHSIC_PD_RX |
2231                         UHSIC_PD_ZI | UHSIC_RPD_DATA | UHSIC_RPD_STROBE);
2232         val |= (UHSIC_RX_SEL | UHSIC_PD_TX);
2233         writel(val, base + UHSIC_PADS_CFG1);
2234
2235         val = readl(base + USB_SUSP_CTRL);
2236         val |= UHSIC_RESET;
2237         writel(val, base + USB_SUSP_CTRL);
2238         udelay(1);
2239
2240         val = readl(base + USB_SUSP_CTRL);
2241         val |= UHSIC_PHY_ENABLE;
2242         writel(val, base + USB_SUSP_CTRL);
2243
2244         val = readl(base + UHSIC_HSRX_CFG0);
2245         val |= UHSIC_IDLE_WAIT(HSIC_IDLE_WAIT_DELAY);
2246         val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(HSIC_ELASTIC_UNDERRUN_LIMIT);
2247         val |= UHSIC_ELASTIC_OVERRUN_LIMIT(HSIC_ELASTIC_OVERRUN_LIMIT);
2248         writel(val, base + UHSIC_HSRX_CFG0);
2249
2250         val = readl(base + UHSIC_HSRX_CFG1);
2251         val |= UHSIC_HS_SYNC_START_DLY(HSIC_SYNC_START_DELAY);
2252         writel(val, base + UHSIC_HSRX_CFG1);
2253
2254         /* WAR HSIC TX */
2255         val = readl(base + UHSIC_TX_CFG0);
2256         val &= ~UHSIC_HS_READY_WAIT_FOR_VALID;
2257         writel(val, base + UHSIC_TX_CFG0);
2258
2259         val = readl(base + UHSIC_MISC_CFG0);
2260         val |= UHSIC_SUSPEND_EXIT_ON_EDGE;
2261         /* Disable generic bus reset, to allow AP30 specific bus reset*/
2262         val |= UHSIC_DISABLE_BUSRESET;
2263         writel(val, base + UHSIC_MISC_CFG0);
2264
2265         val = readl(base + UHSIC_MISC_CFG1);
2266         val |= UHSIC_PLLU_STABLE_COUNT(phy->freq->stable_count);
2267         writel(val, base + UHSIC_MISC_CFG1);
2268
2269         val = readl(base + UHSIC_PLL_CFG1);
2270         val |= UHSIC_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
2271         val |= UHSIC_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count);
2272         writel(val, base + UHSIC_PLL_CFG1);
2273
2274         val = readl(base + USB_SUSP_CTRL);
2275         val &= ~(UHSIC_RESET);
2276         writel(val, base + USB_SUSP_CTRL);
2277         udelay(1);
2278
2279         val = readl(base + UHSIC_PADS_CFG1);
2280         val &= ~(UHSIC_PD_TX);
2281         writel(val, base + UHSIC_PADS_CFG1);
2282
2283         val = readl(base + USB_USBMODE);
2284         val |= USB_USBMODE_HOST;
2285         writel(val, base + USB_USBMODE);
2286
2287         /* Change the USB controller PHY type to HSIC */
2288         val = readl(base + HOSTPC1_DEVLC);
2289         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
2290         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2291         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
2292         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2293         val &= ~HOSTPC1_DEVLC_STS;
2294         writel(val, base + HOSTPC1_DEVLC);
2295
2296         val = readl(base + USB_TXFILLTUNING);
2297         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
2298                 val = USB_FIFO_TXFILL_THRES(0x10);
2299                 writel(val, base + USB_TXFILLTUNING);
2300         }
2301
2302         val = readl(base + USB_PORTSC);
2303         val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN);
2304         writel(val, base + USB_PORTSC);
2305
2306         val = readl(base + UHSIC_PADS_CFG0);
2307         val &= ~(UHSIC_TX_RTUNEN);
2308         /* set Rtune impedance to 50 ohm */
2309         val |= UHSIC_TX_RTUNE(8);
2310         writel(val, base + UHSIC_PADS_CFG0);
2311
2312         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
2313                                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500)) {
2314                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2315                 return -ETIMEDOUT;
2316         }
2317
2318         phy->phy_clk_on = true;
2319         phy->hw_accessible = true;
2320
2321         if (phy->pmc_sleepwalk) {
2322                 DBG("%s(%d) inst:[%d] restore phy\n", __func__, __LINE__,
2323                                         phy->inst);
2324                 uhsic_phy_restore_start(phy);
2325                 usb_phy_bringup_host_controller(phy);
2326                 uhsic_phy_restore_end(phy);
2327                 phy->pmc_sleepwalk = false;
2328         }
2329
2330         return 0;
2331 }
2332
2333 static int uhsic_phy_power_off(struct tegra_usb_phy *phy)
2334 {
2335         unsigned long val;
2336         void __iomem *base = phy->regs;
2337
2338         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2339         if (!phy->phy_clk_on) {
2340                 DBG("%s(%d) inst:[%d] phy clk is already off\n",
2341                                         __func__, __LINE__, phy->inst);
2342                 return 0;
2343         }
2344
2345         phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
2346                         HOSTPC1_DEVLC_PSPD_MASK;
2347
2348         /* Disable interrupts */
2349         writel(0, base + USB_USBINTR);
2350
2351         if (phy->pmc_sleepwalk == false) {
2352                 uhsic_setup_pmc_wake_detect(phy);
2353                 phy->pmc_sleepwalk = true;
2354         }
2355
2356         val = readl(base + HOSTPC1_DEVLC);
2357         val |= HOSTPC1_DEVLC_PHCD;
2358         writel(val, base + HOSTPC1_DEVLC);
2359
2360         /* Remove power downs for HSIC from PADS CFG1 register */
2361         val = readl(base + UHSIC_PADS_CFG1);
2362         val |= (UHSIC_PD_BG |UHSIC_PD_TRK | UHSIC_PD_RX |
2363                         UHSIC_PD_ZI | UHSIC_PD_TX);
2364         writel(val, base + UHSIC_PADS_CFG1);
2365         phy->phy_clk_on = false;
2366         phy->hw_accessible = false;
2367
2368         return 0;
2369 }
2370
2371 int uhsic_phy_bus_port_power(struct tegra_usb_phy *phy)
2372 {
2373         unsigned long val;
2374         void __iomem *base = phy->regs;
2375
2376         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2377
2378         val = readl(base + USB_USBMODE);
2379         val |= USB_USBMODE_HOST;
2380         writel(val, base + USB_USBMODE);
2381
2382         /* Change the USB controller PHY type to HSIC */
2383         val = readl(base + HOSTPC1_DEVLC);
2384         val &= ~(HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK));
2385         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2386         val &= ~(HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK));
2387         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2388         writel(val, base + HOSTPC1_DEVLC);
2389
2390         val = readl(base + UHSIC_MISC_CFG0);
2391         val |= UHSIC_DETECT_SHORT_CONNECT;
2392         writel(val, base + UHSIC_MISC_CFG0);
2393         udelay(1);
2394
2395         val = readl(base + UHSIC_MISC_CFG0);
2396         val |= UHSIC_FORCE_XCVR_MODE;
2397         writel(val, base + UHSIC_MISC_CFG0);
2398
2399         val = readl(base + UHSIC_PADS_CFG1);
2400         val &= ~UHSIC_RPD_STROBE;
2401         writel(val, base + UHSIC_PADS_CFG1);
2402
2403         if (phy->pdata->ops && phy->pdata->ops->port_power)
2404                 phy->pdata->ops->port_power();
2405
2406         if (usb_phy_reg_status_wait(base + UHSIC_STAT_CFG0,
2407                         UHSIC_CONNECT_DETECT, UHSIC_CONNECT_DETECT, 25000)) {
2408                 pr_err("%s: timeout waiting for UHSIC_CONNECT_DETECT\n",
2409                                                                 __func__);
2410                 return -ETIMEDOUT;
2411         }
2412
2413         return 0;
2414 }
2415
2416 static int uhsic_phy_bus_reset(struct tegra_usb_phy *phy)
2417 {
2418         unsigned long val;
2419         void __iomem *base = phy->regs;
2420
2421         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2422
2423         /* Change the USB controller PHY type to HSIC */
2424         val = readl(base + HOSTPC1_DEVLC);
2425         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
2426         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2427         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
2428         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2429         val &= ~HOSTPC1_DEVLC_STS;
2430         writel(val, base + HOSTPC1_DEVLC);
2431         /* wait here, otherwise HOSTPC1_DEVLC_PSPD will timeout */
2432         mdelay(5);
2433
2434         val = readl(base + USB_PORTSC);
2435         val |= USB_PORTSC_PTC(5);
2436         writel(val, base + USB_PORTSC);
2437         udelay(2);
2438
2439         val = readl(base + USB_PORTSC);
2440         val &= ~(USB_PORTSC_PTC(~0));
2441         writel(val, base + USB_PORTSC);
2442         udelay(2);
2443
2444         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_LS(0),
2445                                                  0, 2000)) {
2446                 pr_err("%s: timeout waiting for USB_PORTSC_LS\n", __func__);
2447                 return -ETIMEDOUT;
2448         }
2449
2450         /* Poll until CCS is enabled */
2451         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
2452                                                  USB_PORTSC_CCS, 2000)) {
2453                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
2454                 return -ETIMEDOUT;
2455         }
2456
2457         if (usb_phy_reg_status_wait(base + HOSTPC1_DEVLC,
2458                         HOSTPC1_DEVLC_PSPD(2),
2459                         HOSTPC1_DEVLC_PSPD(2), 2000) < 0) {
2460                 pr_err("%s: timeout waiting hsic high speed configuration\n",
2461                                                 __func__);
2462                         return -ETIMEDOUT;
2463         }
2464
2465         val = readl(base + USB_USBCMD);
2466         val &= ~USB_USBCMD_RS;
2467         writel(val, base + USB_USBCMD);
2468
2469         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
2470                                                  USB_USBSTS_HCH, 2000)) {
2471                 pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
2472                 return -ETIMEDOUT;
2473         }
2474
2475         val = readl(base + UHSIC_PADS_CFG1);
2476         val &= ~UHSIC_RPU_STROBE;
2477         val |= UHSIC_RPD_STROBE;
2478         writel(val, base + UHSIC_PADS_CFG1);
2479
2480         mdelay(50);
2481
2482         val = readl(base + UHSIC_PADS_CFG1);
2483         val &= ~UHSIC_RPD_STROBE;
2484         val |= UHSIC_RPU_STROBE;
2485         writel(val, base + UHSIC_PADS_CFG1);
2486
2487         val = readl(base + USB_USBCMD);
2488         val |= USB_USBCMD_RS;
2489         writel(val, base + USB_USBCMD);
2490
2491         val = readl(base + UHSIC_PADS_CFG1);
2492         val &= ~UHSIC_RPU_STROBE;
2493         writel(val, base + UHSIC_PADS_CFG1);
2494
2495         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2496                                                  USB_USBCMD_RS, 2000)) {
2497                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2498                 return -ETIMEDOUT;
2499         }
2500
2501         return 0;
2502 }
2503
2504 int uhsic_phy_resume(struct tegra_usb_phy *phy)
2505 {
2506         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2507
2508         return 0;
2509 }
2510
2511 static void ulpi_set_trimmer(struct tegra_usb_phy *phy)
2512 {
2513         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2514         void __iomem *base = phy->regs;
2515         unsigned long val;
2516
2517         val = ULPI_DATA_TRIMMER_SEL(config->data_trimmer);
2518         val |= ULPI_STPDIRNXT_TRIMMER_SEL(config->stpdirnxt_trimmer);
2519         val |= ULPI_DIR_TRIMMER_SEL(config->dir_trimmer);
2520         writel(val, base + ULPI_TIMING_CTRL_1);
2521         udelay(10);
2522
2523         val |= ULPI_DATA_TRIMMER_LOAD;
2524         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
2525         val |= ULPI_DIR_TRIMMER_LOAD;
2526         writel(val, base + ULPI_TIMING_CTRL_1);
2527 }
2528
2529 static void reset_utmip_uhsic(void __iomem *base)
2530 {
2531         unsigned long val;
2532
2533         val = readl(base + USB_SUSP_CTRL);
2534         val |= UHSIC_RESET;
2535         writel(val, base + USB_SUSP_CTRL);
2536
2537         val = readl(base + USB_SUSP_CTRL);
2538         val |= UTMIP_RESET;
2539         writel(val, base + USB_SUSP_CTRL);
2540 }
2541
2542 static void ulpi_set_host(void __iomem *base)
2543 {
2544         unsigned long val;
2545
2546         val = readl(base + USB_USBMODE);
2547         val &= ~USB_USBMODE_MASK;
2548         val |= USB_USBMODE_HOST;
2549         writel(val, base + USB_USBMODE);
2550
2551         val = readl(base + HOSTPC1_DEVLC);
2552         val |= HOSTPC1_DEVLC_PTS(2);
2553         writel(val, base + HOSTPC1_DEVLC);
2554 }
2555
2556 static inline void ulpi_pinmux_bypass(struct tegra_usb_phy *phy, bool enable)
2557 {
2558         unsigned long val;
2559         void __iomem *base = phy->regs;
2560
2561         val = readl(base + ULPI_TIMING_CTRL_0);
2562
2563         if (enable)
2564                 val |= ULPI_OUTPUT_PINMUX_BYP;
2565         else
2566                 val &= ~ULPI_OUTPUT_PINMUX_BYP;
2567
2568         writel(val, base + ULPI_TIMING_CTRL_0);
2569 }
2570
2571 static inline void ulpi_null_phy_set_tristate(bool enable)
2572 {
2573 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2574         int tristate = (enable) ? TEGRA_TRI_TRISTATE : TEGRA_TRI_NORMAL;
2575
2576         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA0, tristate);
2577         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA1, tristate);
2578         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA2, tristate);
2579         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA3, tristate);
2580         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA4, tristate);
2581         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA5, tristate);
2582         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA6, tristate);
2583         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA7, tristate);
2584         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_NXT, tristate);
2585
2586         if (enable)
2587                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR, tristate);
2588 #endif
2589 }
2590
2591 static void ulpi_null_phy_obs_read(void)
2592 {
2593         static void __iomem *apb_misc;
2594         unsigned slv0_obs, s2s_obs;
2595
2596         if (!apb_misc)
2597                 apb_misc = ioremap(TEGRA_APB_MISC_BASE, TEGRA_APB_MISC_SIZE);
2598
2599         writel(0x80d1003c, apb_misc + APB_MISC_GP_OBSCTRL_0);
2600         slv0_obs = readl(apb_misc + APB_MISC_GP_OBSDATA_0);
2601
2602         writel(0x80d10040, apb_misc + APB_MISC_GP_OBSCTRL_0);
2603         s2s_obs = readl(apb_misc + APB_MISC_GP_OBSDATA_0);
2604
2605         pr_debug("slv0 obs: %08x\ns2s obs: %08x\n", slv0_obs, s2s_obs);
2606 }
2607
2608 static const struct gpio ulpi_gpios[] = {
2609         {ULPI_STP, GPIOF_IN, "ULPI_STP"},
2610         {ULPI_DIR, GPIOF_OUT_INIT_LOW, "ULPI_DIR"},
2611         {ULPI_D0, GPIOF_OUT_INIT_LOW, "ULPI_D0"},
2612         {ULPI_D1, GPIOF_OUT_INIT_LOW, "ULPI_D1"},
2613 };
2614
2615 static int ulpi_null_phy_open(struct tegra_usb_phy *phy)
2616 {
2617         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2618         int ret;
2619
2620         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2621
2622         ret = gpio_request_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
2623         if (ret)
2624                 return ret;
2625
2626         if (gpio_is_valid(config->phy_restore_gpio)) {
2627                 ret = gpio_request(config->phy_restore_gpio, "phy_restore");
2628                 if (ret)
2629                         goto err_gpio_free;
2630
2631                 gpio_direction_input(config->phy_restore_gpio);
2632         }
2633
2634         tegra_periph_reset_assert(phy->ctrlr_clk);
2635         udelay(10);
2636         tegra_periph_reset_deassert(phy->ctrlr_clk);
2637
2638         return 0;
2639
2640 err_gpio_free:
2641         gpio_free_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
2642         return ret;
2643 }
2644
2645 static void ulpi_null_phy_close(struct tegra_usb_phy *phy)
2646 {
2647         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2648
2649         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2650
2651         if (gpio_is_valid(config->phy_restore_gpio))
2652                 gpio_free(config->phy_restore_gpio);
2653
2654         gpio_free_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
2655 }
2656
2657 static int ulpi_null_phy_power_off(struct tegra_usb_phy *phy)
2658 {
2659         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2660
2661         if (!phy->phy_clk_on) {
2662                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
2663                                                         __LINE__, phy->inst);
2664                 return 0;
2665         }
2666
2667         phy->phy_clk_on = false;
2668         phy->hw_accessible = false;
2669         ulpi_null_phy_set_tristate(true);
2670         return 0;
2671 }
2672
2673 /* NOTE: this function must be called before ehci reset */
2674 static int ulpi_null_phy_init(struct tegra_usb_phy *phy)
2675 {
2676         unsigned long val;
2677         void __iomem *base = phy->regs;
2678
2679         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2680         val = readl(base + ULPIS2S_CTRL);
2681         val |=  ULPIS2S_SLV0_CLAMP_XMIT;
2682         writel(val, base + ULPIS2S_CTRL);
2683
2684         val = readl(base + USB_SUSP_CTRL);
2685         val |= ULPIS2S_SLV0_RESET;
2686         writel(val, base + USB_SUSP_CTRL);
2687         udelay(10);
2688
2689         return 0;
2690 }
2691
2692 static int ulpi_null_phy_irq(struct tegra_usb_phy *phy)
2693 {
2694         unsigned long val;
2695         void __iomem *base = phy->regs;
2696
2697         usb_phy_fence_read(phy);
2698         if (phy->bus_reseting){
2699                 val = readl(base + USB_USBCMD);
2700                 val |= USB_USBCMD_RS;
2701                 writel(val, base + USB_USBCMD);
2702                 phy->bus_reseting = false;
2703         }
2704         return IRQ_HANDLED;
2705 }
2706
2707 /* NOTE: this function must be called after ehci reset */
2708 static int ulpi_null_phy_cmd_reset(struct tegra_usb_phy *phy)
2709 {
2710         unsigned long val;
2711         void __iomem *base = phy->regs;
2712
2713         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2714         ulpi_set_host(base);
2715
2716         /* remove slave0 reset */
2717         val = readl(base + USB_SUSP_CTRL);
2718         val &= ~ULPIS2S_SLV0_RESET;
2719         writel(val, base + USB_SUSP_CTRL);
2720
2721         val = readl(base + ULPIS2S_CTRL);
2722         val &=  ~ULPIS2S_SLV0_CLAMP_XMIT;
2723         writel(val, base + ULPIS2S_CTRL);
2724         udelay(10);
2725
2726         return 0;
2727 }
2728
2729 static int ulpi_phy_bus_reset(struct tegra_usb_phy *phy)
2730 {
2731         unsigned long val;
2732         void __iomem *base = phy->regs;
2733
2734         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2735
2736         /*DISABLE RUN BIT */
2737
2738         val = readl(base + USB_USBCMD);
2739         val &= ~USB_USBCMD_RS;
2740         writel(val, base + USB_USBCMD);
2741         phy->bus_reseting = true;
2742
2743         return 0;
2744 }
2745
2746 static int ulpi_null_phy_restore(struct tegra_usb_phy *phy)
2747 {
2748         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2749         unsigned long timeout;
2750         int ulpi_stp = ULPI_STP;
2751
2752         if (gpio_is_valid(config->phy_restore_gpio))
2753                 ulpi_stp = config->phy_restore_gpio;
2754
2755         /* disable ULPI pinmux bypass */
2756         ulpi_pinmux_bypass(phy, false);
2757
2758         /* driving linstate by GPIO */
2759         gpio_set_value(ULPI_D0, 0);
2760         gpio_set_value(ULPI_D1, 0);
2761
2762         /* driving DIR high */
2763         gpio_set_value(ULPI_DIR, 1);
2764
2765         /* remove ULPI tristate */
2766         ulpi_null_phy_set_tristate(false);
2767
2768         /* wait for STP high */
2769         timeout = jiffies + msecs_to_jiffies(25);
2770
2771         while (!gpio_get_value(ulpi_stp)) {
2772                 if (time_after(jiffies, timeout)) {
2773                         pr_warn("phy restore timeout\n");
2774                         return 1;
2775                 }
2776         }
2777
2778         return 0;
2779 }
2780
2781 static int ulpi_null_phy_lp0_resume(struct tegra_usb_phy *phy)
2782 {
2783         unsigned long val;
2784         void __iomem *base = phy->regs;
2785
2786         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2787         ulpi_null_phy_init(phy);
2788
2789         val = readl(base + USB_USBCMD);
2790         val |= USB_CMD_RESET;
2791         writel(val, base + USB_USBCMD);
2792
2793         if (usb_phy_reg_status_wait(base + USB_USBCMD,
2794                 USB_CMD_RESET, 0, 2500) < 0) {
2795                 pr_err("%s: timeout waiting for reset\n", __func__);
2796         }
2797
2798         ulpi_null_phy_cmd_reset(phy);
2799
2800         val = readl(base + USB_USBCMD);
2801         val |= USB_USBCMD_RS;
2802         writel(val, base + USB_USBCMD);
2803         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2804                                                  USB_USBCMD_RS, 2000)) {
2805                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2806                 return -ETIMEDOUT;
2807         }
2808
2809         /* Enable Port Power */
2810         val = readl(base + USB_PORTSC);
2811         val |= USB_PORTSC_PP;
2812         writel(val, base + USB_PORTSC);
2813         udelay(10);
2814
2815         ulpi_null_phy_restore(phy);
2816
2817         return 0;
2818 }
2819
2820 static int ulpi_null_phy_power_on(struct tegra_usb_phy *phy)
2821 {
2822         unsigned long val;
2823         void __iomem *base = phy->regs;
2824         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2825
2826         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2827         if (phy->phy_clk_on) {
2828                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
2829                                                         __LINE__, phy->inst);
2830                 return 0;
2831         }
2832         reset_utmip_uhsic(base);
2833
2834         /* remove ULPI PADS CLKEN reset */
2835         val = readl(base + USB_SUSP_CTRL);
2836         val &= ~ULPI_PADS_CLKEN_RESET;
2837         writel(val, base + USB_SUSP_CTRL);
2838         udelay(10);
2839
2840         val = readl(base + ULPI_TIMING_CTRL_0);
2841         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
2842         writel(val, base + ULPI_TIMING_CTRL_0);
2843
2844         val = readl(base + USB_SUSP_CTRL);
2845         val |= ULPI_PHY_ENABLE;
2846         writel(val, base + USB_SUSP_CTRL);
2847         udelay(10);
2848
2849         /* set timming parameters */
2850         val = readl(base + ULPI_TIMING_CTRL_0);
2851         val |= ULPI_SHADOW_CLK_LOOPBACK_EN;
2852         val &= ~ULPI_SHADOW_CLK_SEL;
2853         val &= ~ULPI_LBK_PAD_EN;
2854         val |= ULPI_SHADOW_CLK_DELAY(config->shadow_clk_delay);
2855         val |= ULPI_CLOCK_OUT_DELAY(config->clock_out_delay);
2856         val |= ULPI_LBK_PAD_E_INPUT_OR;
2857         writel(val, base + ULPI_TIMING_CTRL_0);
2858
2859         writel(0, base + ULPI_TIMING_CTRL_1);
2860         udelay(10);
2861
2862         /* start internal 60MHz clock */
2863         val = readl(base + ULPIS2S_CTRL);
2864         val |= ULPIS2S_ENA;
2865         val |= ULPIS2S_SUPPORT_DISCONNECT;
2866         val |= ULPIS2S_SPARE((phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) ? 3 : 1);
2867         val |= ULPIS2S_PLLU_MASTER_BLASTER60;
2868         writel(val, base + ULPIS2S_CTRL);
2869
2870         /* select ULPI_CORE_CLK_SEL to SHADOW_CLK */
2871         val = readl(base + ULPI_TIMING_CTRL_0);
2872         val |= ULPI_CORE_CLK_SEL;
2873         writel(val, base + ULPI_TIMING_CTRL_0);
2874         udelay(10);
2875
2876         /* enable ULPI null phy clock - can't set the trimmers before this */
2877         val = readl(base + ULPI_TIMING_CTRL_0);
2878         val |= ULPI_CLK_OUT_ENA;
2879         writel(val, base + ULPI_TIMING_CTRL_0);
2880         udelay(10);
2881
2882         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
2883                                                  USB_PHY_CLK_VALID, 2500)) {
2884                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2885                 return -ETIMEDOUT;
2886         }
2887
2888         /* set ULPI trimmers */
2889         ulpi_set_trimmer(phy);
2890
2891         ulpi_set_host(base);
2892
2893         /* remove slave0 reset */
2894         val = readl(base + USB_SUSP_CTRL);
2895         val &= ~ULPIS2S_SLV0_RESET;
2896         writel(val, base + USB_SUSP_CTRL);
2897
2898         /* remove slave1 and line reset */
2899         val = readl(base + USB_SUSP_CTRL);
2900         val &= ~ULPIS2S_SLV1_RESET;
2901         val &= ~ULPIS2S_LINE_RESET;
2902
2903         /* remove ULPI PADS reset */
2904         val &= ~ULPI_PADS_RESET;
2905         writel(val, base + USB_SUSP_CTRL);
2906
2907         if (!phy->ulpi_clk_padout_ena) {
2908                 val = readl(base + ULPI_TIMING_CTRL_0);
2909                 val |= ULPI_CLK_PADOUT_ENA;
2910                 writel(val, base + ULPI_TIMING_CTRL_0);
2911                 phy->ulpi_clk_padout_ena = true;
2912         } else {
2913                 if (!readl(base + USB_ASYNCLISTADDR))
2914                         ulpi_null_phy_lp0_resume(phy);
2915         }
2916         udelay(10);
2917
2918         phy->bus_reseting = false;
2919         phy->phy_clk_on = true;
2920         phy->hw_accessible = true;
2921
2922         return 0;
2923 }
2924
2925 static int ulpi_null_phy_pre_resume(struct tegra_usb_phy *phy,
2926                                     bool remote_wakeup)
2927 {
2928         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2929         ulpi_null_phy_obs_read();
2930         usb_phy_wait_for_sof(phy);
2931         ulpi_null_phy_obs_read();
2932         return 0;
2933 }
2934
2935 static int ulpi_null_phy_post_resume(struct tegra_usb_phy *phy)
2936 {
2937         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2938         ulpi_null_phy_obs_read();
2939         return 0;
2940 }
2941
2942 static int ulpi_null_phy_resume(struct tegra_usb_phy *phy)
2943 {
2944         unsigned long val;
2945         void __iomem *base = phy->regs;
2946
2947         if (!readl(base + USB_ASYNCLISTADDR)) {
2948                 /* enable ULPI CLK output pad */
2949                 val = readl(base + ULPI_TIMING_CTRL_0);
2950                 val |= ULPI_CLK_PADOUT_ENA;
2951                 writel(val, base + ULPI_TIMING_CTRL_0);
2952
2953                 /* enable ULPI pinmux bypass */
2954                 ulpi_pinmux_bypass(phy, true);
2955                 udelay(5);
2956 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2957                 /* remove DIR tristate */
2958                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR,
2959                                           TEGRA_TRI_NORMAL);
2960 #endif
2961         }
2962         return 0;
2963 }
2964
2965
2966
2967 static struct tegra_usb_phy_ops utmi_phy_ops = {
2968         .open           = utmi_phy_open,
2969         .close          = utmi_phy_close,
2970         .irq            = utmi_phy_irq,
2971         .power_on       = utmi_phy_power_on,
2972         .power_off      = utmi_phy_power_off,
2973         .pre_resume = utmi_phy_pre_resume,
2974         .resume = utmi_phy_resume,
2975         .post_resume    = utmi_phy_post_resume,
2976         .charger_detect = utmi_phy_charger_detect,
2977 };
2978
2979 static struct tegra_usb_phy_ops uhsic_phy_ops = {
2980         .open           = uhsic_phy_open,
2981         .close          = uhsic_phy_close,
2982         .irq            = uhsic_phy_irq,
2983         .power_on       = uhsic_phy_power_on,
2984         .power_off      = uhsic_phy_power_off,
2985         .pre_resume = uhsic_phy_pre_resume,
2986         .resume = uhsic_phy_resume,
2987         .post_resume = uhsic_phy_post_resume,
2988         .port_power = uhsic_phy_bus_port_power,
2989         .bus_reset      = uhsic_phy_bus_reset,
2990 };
2991
2992 static struct tegra_usb_phy_ops ulpi_null_phy_ops = {
2993         .open           = ulpi_null_phy_open,
2994         .close          = ulpi_null_phy_close,
2995         .init           = ulpi_null_phy_init,
2996         .irq            = ulpi_null_phy_irq,
2997         .power_on       = ulpi_null_phy_power_on,
2998         .power_off      = ulpi_null_phy_power_off,
2999         .pre_resume = ulpi_null_phy_pre_resume,
3000         .resume = ulpi_null_phy_resume,
3001         .post_resume = ulpi_null_phy_post_resume,
3002         .reset          = ulpi_null_phy_cmd_reset,
3003         .bus_reset      = ulpi_phy_bus_reset,
3004 };
3005
3006 static struct tegra_usb_phy_ops ulpi_link_phy_ops;
3007 static struct tegra_usb_phy_ops icusb_phy_ops;
3008
3009 static struct tegra_usb_phy_ops *phy_ops[] = {
3010         [TEGRA_USB_PHY_INTF_UTMI] = &utmi_phy_ops,
3011         [TEGRA_USB_PHY_INTF_ULPI_LINK] = &ulpi_link_phy_ops,
3012         [TEGRA_USB_PHY_INTF_ULPI_NULL] = &ulpi_null_phy_ops,
3013         [TEGRA_USB_PHY_INTF_HSIC] = &uhsic_phy_ops,
3014         [TEGRA_USB_PHY_INTF_ICUSB] = &icusb_phy_ops,
3015 };
3016
3017 int tegra3_usb_phy_init_ops(struct tegra_usb_phy *phy)
3018 {
3019         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
3020
3021         phy->ops = phy_ops[phy->pdata->phy_intf];
3022
3023         /* FIXME: uncommenting below line to make USB host mode fail*/
3024         /* usb_phy_power_down_pmc(); */
3025
3026         return 0;
3027 }