Revert "Merge commit 'main-jb-2012.08.03-B4' into t114-0806"
[linux-2.6.git] / arch / arm / mach-tegra / tegra3_usb_phy.c
1 /*
2  * arch/arm/mach-tegra/tegra3_usb_phy.c
3  *
4  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
5  *
6  *
7  * This software is licensed under the terms of the GNU General Public
8  * License version 2, as published by the Free Software Foundation, and
9  * may be copied, distributed, and modified under those terms.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17 #include <linux/resource.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/slab.h>
21 #include <linux/err.h>
22 #include <linux/platform_device.h>
23 #include <linux/io.h>
24 #include <linux/gpio.h>
25 #include <linux/interrupt.h>
26 #include <linux/clk.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <mach/clk.h>
30 #include <mach/iomap.h>
31 #include <mach/pinmux.h>
32 #include <mach/pinmux-tegra30.h>
33 #include "tegra_usb_phy.h"
34 #include "gpio-names.h"
35 #include "fuse.h"
36
37 #define USB_USBCMD              0x130
38 #define   USB_USBCMD_RS         (1 << 0)
39 #define   USB_CMD_RESET (1<<1)
40
41 #define USB_USBSTS              0x134
42 #define   USB_USBSTS_PCI        (1 << 2)
43 #define   USB_USBSTS_SRI        (1 << 7)
44 #define   USB_USBSTS_HCH        (1 << 12)
45
46 #define USB_USBINTR             0x138
47
48 #define USB_TXFILLTUNING        0x154
49 #define USB_FIFO_TXFILL_THRES(x)   (((x) & 0x1f) << 16)
50 #define USB_FIFO_TXFILL_MASK    0x1f0000
51
52 #define USB_ASYNCLISTADDR       0x148
53
54 #define ICUSB_CTRL              0x15c
55
56 #define USB_PORTSC              0x174
57 #define   USB_PORTSC_WKOC       (1 << 22)
58 #define   USB_PORTSC_WKDS       (1 << 21)
59 #define   USB_PORTSC_WKCN       (1 << 20)
60 #define   USB_PORTSC_PTC(x)     (((x) & 0xf) << 16)
61 #define   USB_PORTSC_PP (1 << 12)
62 #define   USB_PORTSC_LS(x) (((x) & 0x3) << 10)
63 #define   USB_PORTSC_SUSP       (1 << 7)
64 #define   USB_PORTSC_RESUME     (1 << 6)
65 #define   USB_PORTSC_OCC        (1 << 5)
66 #define   USB_PORTSC_PEC        (1 << 3)
67 #define   USB_PORTSC_PE         (1 << 2)
68 #define   USB_PORTSC_CSC        (1 << 1)
69 #define   USB_PORTSC_CCS        (1 << 0)
70 #define   USB_PORTSC_RWC_BITS (USB_PORTSC_CSC | USB_PORTSC_PEC | USB_PORTSC_OCC)
71
72 #define HOSTPC1_DEVLC           0x1b4
73 #define   HOSTPC1_DEVLC_PHCD            (1 << 22)
74 #define   HOSTPC1_DEVLC_PTS(x)          (((x) & 0x7) << 29)
75 #define   HOSTPC1_DEVLC_PTS_MASK        7
76 #define   HOSTPC1_DEVLC_PTS_HSIC        4
77 #define   HOSTPC1_DEVLC_STS             (1 << 28)
78 #define   HOSTPC1_DEVLC_PSPD(x)         (((x) & 0x3) << 25)
79 #define   HOSTPC1_DEVLC_PSPD_MASK       3
80 #define   HOSTPC1_DEVLC_PSPD_HIGH_SPEED 2
81
82 #define USB_USBMODE             0x1f8
83 #define   USB_USBMODE_MASK              (3 << 0)
84 #define   USB_USBMODE_HOST              (3 << 0)
85 #define   USB_USBMODE_DEVICE            (2 << 0)
86
87 #define USB_SUSP_CTRL           0x400
88 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
89 #define   USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
90 #define   USB_SUSP_CLR                  (1 << 5)
91 #define   USB_PHY_CLK_VALID             (1 << 7)
92 #define   USB_PHY_CLK_VALID_INT_ENB     (1 << 9)
93 #define   USB_PHY_CLK_VALID_INT_STS     (1 << 8)
94 #define   UTMIP_RESET                   (1 << 11)
95 #define   UTMIP_PHY_ENABLE              (1 << 12)
96 #define   ULPI_PHY_ENABLE               (1 << 13)
97 #define   UHSIC_RESET                   (1 << 14)
98 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
99 #define   UHSIC_PHY_ENABLE              (1 << 19)
100 #define   ULPIS2S_SLV0_RESET            (1 << 20)
101 #define   ULPIS2S_SLV1_RESET            (1 << 21)
102 #define   ULPIS2S_LINE_RESET            (1 << 22)
103 #define   ULPI_PADS_RESET               (1 << 23)
104 #define   ULPI_PADS_CLKEN_RESET         (1 << 24)
105
106 #define USB_PHY_VBUS_WAKEUP_ID  0x408
107 #define   VDAT_DET_INT_EN       (1 << 16)
108 #define   VDAT_DET_CHG_DET      (1 << 17)
109 #define   VDAT_DET_STS          (1 << 18)
110 #define   USB_ID_STATUS         (1 << 2)
111
112 #define ULPIS2S_CTRL            0x418
113 #define   ULPIS2S_ENA                   (1 << 0)
114 #define   ULPIS2S_SUPPORT_DISCONNECT    (1 << 2)
115 #define   ULPIS2S_PLLU_MASTER_BLASTER60 (1 << 3)
116 #define   ULPIS2S_SPARE(x)              (((x) & 0xF) << 8)
117 #define   ULPIS2S_FORCE_ULPI_CLK_OUT    (1 << 12)
118 #define   ULPIS2S_DISCON_DONT_CHECK_SE0 (1 << 13)
119 #define   ULPIS2S_SUPPORT_HS_KEEP_ALIVE (1 << 14)
120 #define   ULPIS2S_DISABLE_STP_PU        (1 << 15)
121 #define   ULPIS2S_SLV0_CLAMP_XMIT       (1 << 16)
122
123 #define ULPI_TIMING_CTRL_0      0x424
124 #define   ULPI_CLOCK_OUT_DELAY(x)       ((x) & 0x1F)
125 #define   ULPI_OUTPUT_PINMUX_BYP        (1 << 10)
126 #define   ULPI_CLKOUT_PINMUX_BYP        (1 << 11)
127 #define   ULPI_SHADOW_CLK_LOOPBACK_EN   (1 << 12)
128 #define   ULPI_SHADOW_CLK_SEL           (1 << 13)
129 #define   ULPI_CORE_CLK_SEL             (1 << 14)
130 #define   ULPI_SHADOW_CLK_DELAY(x)      (((x) & 0x1F) << 16)
131 #define   ULPI_LBK_PAD_EN               (1 << 26)
132 #define   ULPI_LBK_PAD_E_INPUT_OR       (1 << 27)
133 #define   ULPI_CLK_OUT_ENA              (1 << 28)
134 #define   ULPI_CLK_PADOUT_ENA           (1 << 29)
135
136 #define ULPI_TIMING_CTRL_1      0x428
137 #define   ULPI_DATA_TRIMMER_LOAD        (1 << 0)
138 #define   ULPI_DATA_TRIMMER_SEL(x)      (((x) & 0x7) << 1)
139 #define   ULPI_STPDIRNXT_TRIMMER_LOAD   (1 << 16)
140 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
141 #define   ULPI_DIR_TRIMMER_LOAD         (1 << 24)
142 #define   ULPI_DIR_TRIMMER_SEL(x)       (((x) & 0x7) << 25)
143
144 #define UTMIP_XCVR_CFG0         0x808
145 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
146 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
147 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
148 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
149 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
150 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
151 #define   UTMIP_XCVR_LSBIAS_SEL                 (1 << 21)
152 #define   UTMIP_XCVR_SETUP_MSB(x)               (((x) & 0x7) << 22)
153 #define   UTMIP_XCVR_HSSLEW_MSB(x)              (((x) & 0x7f) << 25)
154 #define   UTMIP_XCVR_MAX_OFFSET         2
155 #define   UTMIP_XCVR_SETUP_MAX_VALUE    0x7f
156 #define   UTMIP_XCVR_SETUP_MIN_VALUE    0
157 #define   XCVR_SETUP_MSB_CALIB(x) ((x) >> 4)
158
159 #define UTMIP_BIAS_CFG0         0x80c
160 #define   UTMIP_OTGPD                   (1 << 11)
161 #define   UTMIP_BIASPD                  (1 << 10)
162 #define   UTMIP_HSSQUELCH_LEVEL(x)      (((x) & 0x3) << 0)
163 #define   UTMIP_HSDISCON_LEVEL(x)       (((x) & 0x3) << 2)
164 #define   UTMIP_HSDISCON_LEVEL_MSB      (1 << 24)
165
166 #define UTMIP_HSRX_CFG0         0x810
167 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
168 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
169
170 #define UTMIP_HSRX_CFG1         0x814
171 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
172
173 #define UTMIP_TX_CFG0           0x820
174 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
175 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
176
177 #define UTMIP_DEBOUNCE_CFG0 0x82c
178 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
179
180 #define UTMIP_BAT_CHRG_CFG0 0x830
181 #define   UTMIP_PD_CHRG                 (1 << 0)
182 #define   UTMIP_ON_SINK_EN              (1 << 2)
183 #define   UTMIP_OP_SRC_EN               (1 << 3)
184
185 #define UTMIP_XCVR_CFG1         0x838
186 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
187 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
188 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
189 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
190
191 #define UTMIP_BIAS_CFG1         0x83c
192 #define   UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
193 #define   UTMIP_BIAS_PDTRK_POWERDOWN    (1 << 0)
194 #define   UTMIP_BIAS_PDTRK_POWERUP      (1 << 1)
195
196 #define UTMIP_MISC_CFG0         0x824
197 #define   UTMIP_DPDM_OBSERVE            (1 << 26)
198 #define   UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
199 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J   UTMIP_DPDM_OBSERVE_SEL(0xf)
200 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K   UTMIP_DPDM_OBSERVE_SEL(0xe)
201 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
202 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
203 #define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
204 #define   FORCE_PULLDN_DM       (1 << 8)
205 #define   FORCE_PULLDN_DP       (1 << 9)
206 #define   COMB_TERMS            (1 << 0)
207 #define   ALWAYS_FREE_RUNNING_TERMS (1 << 1)
208
209 #define UTMIP_SPARE_CFG0        0x834
210 #define   FUSE_SETUP_SEL                (1 << 3)
211 #define   FUSE_ATERM_SEL                (1 << 4)
212
213 #define UTMIP_PMC_WAKEUP0               0x84c
214 #define   EVENT_INT_ENB                 (1 << 0)
215
216 #define UHSIC_PMC_WAKEUP0               0xc34
217
218 #define UTMIP_BIAS_STS0                 0x840
219 #define   UTMIP_RCTRL_VAL(x)            (((x) & 0xffff) << 0)
220 #define   UTMIP_TCTRL_VAL(x)            (((x) & (0xffff << 16)) >> 16)
221
222 #define UHSIC_PLL_CFG1                          0xc04
223 #define   UHSIC_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
224 #define   UHSIC_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 14)
225
226 #define UHSIC_HSRX_CFG0                         0xc08
227 #define   UHSIC_ELASTIC_UNDERRUN_LIMIT(x)       (((x) & 0x1f) << 2)
228 #define   UHSIC_ELASTIC_OVERRUN_LIMIT(x)        (((x) & 0x1f) << 8)
229 #define   UHSIC_IDLE_WAIT(x)                    (((x) & 0x1f) << 13)
230
231 #define UHSIC_HSRX_CFG1                         0xc0c
232 #define   UHSIC_HS_SYNC_START_DLY(x)            (((x) & 0x1f) << 1)
233
234 #define UHSIC_TX_CFG0                           0xc10
235 #define UHSIC_HS_READY_WAIT_FOR_VALID   (1 << 9)
236 #define UHSIC_MISC_CFG0                         0xc14
237 #define   UHSIC_SUSPEND_EXIT_ON_EDGE            (1 << 7)
238 #define   UHSIC_DETECT_SHORT_CONNECT            (1 << 8)
239 #define   UHSIC_FORCE_XCVR_MODE                 (1 << 15)
240 #define   UHSIC_DISABLE_BUSRESET                (1 << 20)
241 #define UHSIC_MISC_CFG1                         0xc18
242 #define   UHSIC_PLLU_STABLE_COUNT(x)            (((x) & 0xfff) << 2)
243
244 #define UHSIC_PADS_CFG0                         0xc1c
245 #define   UHSIC_TX_RTUNEN                       0xf000
246 #define   UHSIC_TX_RTUNE(x)                     (((x) & 0xf) << 12)
247
248 #define UHSIC_PADS_CFG1                         0xc20
249 #define   UHSIC_PD_BG                           (1 << 2)
250 #define   UHSIC_PD_TX                           (1 << 3)
251 #define   UHSIC_PD_TRK                          (1 << 4)
252 #define   UHSIC_PD_RX                           (1 << 5)
253 #define   UHSIC_PD_ZI                           (1 << 6)
254 #define   UHSIC_RX_SEL                          (1 << 7)
255 #define   UHSIC_RPD_DATA                        (1 << 9)
256 #define   UHSIC_RPD_STROBE                      (1 << 10)
257 #define   UHSIC_RPU_DATA                        (1 << 11)
258 #define   UHSIC_RPU_STROBE                      (1 << 12)
259
260 #define UHSIC_CMD_CFG0                  0xc24
261 #define UHSIC_PRETEND_CONNECT_DETECT    (1 << 5)
262
263 #define UHSIC_STAT_CFG0         0xc28
264 #define UHSIC_CONNECT_DETECT            (1 << 0)
265
266 #define PMC_USB_DEBOUNCE                        0xec
267 #define UTMIP_LINE_DEB_CNT(x)           (((x) & 0xf) << 16)
268 #define UHSIC_LINE_DEB_CNT(x)           (((x) & 0xf) << 20)
269
270 #define PMC_USB_AO                              0xf0
271
272 #define PMC_POWER_DOWN_MASK                     0xffff
273 #define HSIC_RESERVED_P0                        (3 << 14)
274 #define STROBE_VAL_PD_P0                        (1 << 12)
275 #define DATA_VAL_PD_P0                          (1 << 13)
276
277 #define USB_ID_PD(inst)                 (1 << ((4*(inst))+3))
278 #define VBUS_WAKEUP_PD(inst)                    (1 << ((4*(inst))+2))
279 #define   USBON_VAL_PD(inst)                    (1 << ((4*(inst))+1))
280 #define   USBON_VAL_PD_P2                       (1 << 9)
281 #define   USBON_VAL_PD_P1                       (1 << 5)
282 #define   USBON_VAL_PD_P0                       (1 << 1)
283 #define   USBOP_VAL_PD(inst)                    (1 << (4*(inst)))
284 #define   USBOP_VAL_PD_P2                       (1 << 8)
285 #define   USBOP_VAL_PD_P1                       (1 << 4)
286 #define   USBOP_VAL_PD_P0                       (1 << 0)
287 #define   PMC_USB_AO_PD_P2                      (0xf << 8)
288 #define   PMC_USB_AO_ID_PD_P0                   (1 << 3)
289 #define   PMC_USB_AO_VBUS_WAKEUP_PD_P0  (1 << 2)
290
291 #define PMC_TRIGGERS                    0x1ec
292
293 #define   UHSIC_CLR_WALK_PTR_P0         (1 << 3)
294 #define   UTMIP_CLR_WALK_PTR(inst)      (1 << (inst))
295 #define   UTMIP_CLR_WALK_PTR_P2         (1 << 2)
296 #define   UTMIP_CLR_WALK_PTR_P1         (1 << 1)
297 #define   UTMIP_CLR_WALK_PTR_P0         (1 << 0)
298 #define   UTMIP_CAP_CFG(inst)   (1 << ((inst)+4))
299 #define   UTMIP_CAP_CFG_P2              (1 << 6)
300 #define   UTMIP_CAP_CFG_P1              (1 << 5)
301 #define   UTMIP_CAP_CFG_P0              (1 << 4)
302 #define   UTMIP_CLR_WAKE_ALARM(inst)    (1 << ((inst)+12))
303 #define   UHSIC_CLR_WAKE_ALARM_P0       (1 << 15)
304 #define   UTMIP_CLR_WAKE_ALARM_P2       (1 << 14)
305
306 #define PMC_PAD_CFG             (0x1f4)
307
308 #define PMC_UTMIP_TERM_PAD_CFG  0x1f8
309 #define   PMC_TCTRL_VAL(x)      (((x) & 0x1f) << 5)
310 #define   PMC_RCTRL_VAL(x)      (((x) & 0x1f) << 0)
311
312 #define PMC_SLEEP_CFG                   0x1fc
313
314 #define   UHSIC_MASTER_ENABLE                   (1 << 24)
315 #define   UHSIC_WAKE_VAL(x)             (((x) & 0xf) << 28)
316 #define   WAKE_VAL_SD10                 0x2
317 #define   UTMIP_TCTRL_USE_PMC(inst) (1 << ((8*(inst))+3))
318 #define   UTMIP_TCTRL_USE_PMC_P2                (1 << 19)
319 #define   UTMIP_TCTRL_USE_PMC_P1                (1 << 11)
320 #define   UTMIP_TCTRL_USE_PMC_P0                (1 << 3)
321 #define   UTMIP_RCTRL_USE_PMC(inst) (1 << ((8*(inst))+2))
322 #define   UTMIP_RCTRL_USE_PMC_P2                (1 << 18)
323 #define   UTMIP_RCTRL_USE_PMC_P1                (1 << 10)
324 #define   UTMIP_RCTRL_USE_PMC_P0                (1 << 2)
325 #define   UTMIP_FSLS_USE_PMC(inst)      (1 << ((8*(inst))+1))
326 #define   UTMIP_FSLS_USE_PMC_P2         (1 << 17)
327 #define   UTMIP_FSLS_USE_PMC_P1         (1 << 9)
328 #define   UTMIP_FSLS_USE_PMC_P0         (1 << 1)
329 #define   UTMIP_MASTER_ENABLE(inst) (1 << (8*(inst)))
330 #define   UTMIP_MASTER_ENABLE_P2                (1 << 16)
331 #define   UTMIP_MASTER_ENABLE_P1                (1 << 8)
332 #define   UTMIP_MASTER_ENABLE_P0                (1 << 0)
333 #define UHSIC_MASTER_ENABLE_P0          (1 << 24)
334 #define UHSIC_WAKE_VAL_P0(x)            (((x) & 0xf) << 28)
335
336 #define PMC_SLEEPWALK_CFG               0x200
337
338 #define   UHSIC_WAKE_WALK_EN_P0 (1 << 30)
339 #define   UHSIC_LINEVAL_WALK_EN (1 << 31)
340 #define   UTMIP_LINEVAL_WALK_EN(inst) (1 << ((8*(inst))+7))
341 #define   UTMIP_LINEVAL_WALK_EN_P2      (1 << 23)
342 #define   UTMIP_LINEVAL_WALK_EN_P1      (1 << 15)
343 #define   UTMIP_LINEVAL_WALK_EN_P0      (1 << 7)
344 #define   UTMIP_WAKE_VAL(inst, x) (((x) & 0xf) << ((8*(inst))+4))
345 #define   UTMIP_WAKE_VAL_P2(x)          (((x) & 0xf) << 20)
346 #define   UTMIP_WAKE_VAL_P1(x)          (((x) & 0xf) << 12)
347 #define   UTMIP_WAKE_VAL_P0(x)          (((x) & 0xf) << 4)
348 #define   WAKE_VAL_NONE         0xc
349 #define   WAKE_VAL_ANY                  0xF
350 #define   WAKE_VAL_FSJ                  0x2
351 #define   WAKE_VAL_FSK                  0x1
352 #define   WAKE_VAL_SE0                  0x0
353
354 #define PMC_SLEEPWALK_REG(inst)         (0x204 + (4*(inst)))
355 #define   UTMIP_USBOP_RPD_A     (1 << 0)
356 #define   UTMIP_USBON_RPD_A     (1 << 1)
357 #define   UTMIP_AP_A                    (1 << 4)
358 #define   UTMIP_AN_A                    (1 << 5)
359 #define   UTMIP_HIGHZ_A         (1 << 6)
360 #define   UTMIP_USBOP_RPD_B     (1 << 8)
361 #define   UTMIP_USBON_RPD_B     (1 << 9)
362 #define   UTMIP_AP_B                    (1 << 12)
363 #define   UTMIP_AN_B                    (1 << 13)
364 #define   UTMIP_HIGHZ_B         (1 << 14)
365 #define   UTMIP_USBOP_RPD_C     (1 << 16)
366 #define   UTMIP_USBON_RPD_C     (1 << 17)
367 #define   UTMIP_AP_C            (1 << 20)
368 #define   UTMIP_AN_C            (1 << 21)
369 #define   UTMIP_HIGHZ_C         (1 << 22)
370 #define   UTMIP_USBOP_RPD_D     (1 << 24)
371 #define   UTMIP_USBON_RPD_D     (1 << 25)
372 #define   UTMIP_AP_D            (1 << 28)
373 #define   UTMIP_AN_D            (1 << 29)
374 #define   UTMIP_HIGHZ_D         (1 << 30)
375
376 #define PMC_SLEEPWALK_UHSIC             0x210
377
378 #define UHSIC_STROBE_RPD_A              (1 << 0)
379 #define UHSIC_DATA_RPD_A                (1 << 1)
380 #define UHSIC_STROBE_RPU_A              (1 << 2)
381 #define UHSIC_DATA_RPU_A                (1 << 3)
382 #define UHSIC_STROBE_RPD_B              (1 << 8)
383 #define UHSIC_DATA_RPD_B                (1 << 9)
384 #define UHSIC_STROBE_RPU_B              (1 << 10)
385 #define UHSIC_DATA_RPU_B                (1 << 11)
386 #define UHSIC_STROBE_RPD_C              (1 << 16)
387 #define UHSIC_DATA_RPD_C                (1 << 17)
388 #define UHSIC_STROBE_RPU_C              (1 << 18)
389 #define UHSIC_DATA_RPU_C                (1 << 19)
390 #define UHSIC_STROBE_RPD_D              (1 << 24)
391 #define UHSIC_DATA_RPD_D                (1 << 25)
392 #define UHSIC_STROBE_RPU_D              (1 << 26)
393 #define UHSIC_DATA_RPU_D                (1 << 27)
394
395 #define UTMIP_UHSIC_STATUS              0x214
396
397 #define UTMIP_USBOP_VAL(inst)           (1 << ((2*(inst)) + 8))
398 #define UTMIP_USBOP_VAL_P2              (1 << 12)
399 #define UTMIP_USBOP_VAL_P1              (1 << 10)
400 #define UTMIP_USBOP_VAL_P0              (1 << 8)
401 #define UTMIP_USBON_VAL(inst)           (1 << ((2*(inst)) + 9))
402 #define UTMIP_USBON_VAL_P2              (1 << 13)
403 #define UTMIP_USBON_VAL_P1              (1 << 11)
404 #define UTMIP_USBON_VAL_P0              (1 << 9)
405 #define UHSIC_WAKE_ALARM                (1 << 19)
406 #define UTMIP_WAKE_ALARM(inst)          (1 << ((inst) + 16))
407 #define UTMIP_WAKE_ALARM_P2             (1 << 18)
408 #define UTMIP_WAKE_ALARM_P1             (1 << 17)
409 #define UTMIP_WAKE_ALARM_P0             (1 << 16)
410 #define UHSIC_DATA_VAL_P0               (1 << 15)
411 #define UHSIC_STROBE_VAL_P0             (1 << 14)
412 #define UTMIP_WALK_PTR_VAL(inst)        (0x3 << ((inst)*2))
413 #define UHSIC_WALK_PTR_VAL              (0x3 << 6)
414 #define UTMIP_WALK_PTR(inst)            (1 << ((inst)*2))
415 #define UTMIP_WALK_PTR_P2               (1 << 4)
416 #define UTMIP_WALK_PTR_P1               (1 << 2)
417 #define UTMIP_WALK_PTR_P0               (1 << 0)
418
419 #define USB1_PREFETCH_ID                           6
420 #define USB2_PREFETCH_ID                           18
421 #define USB3_PREFETCH_ID                           17
422
423 #define PMC_UTMIP_UHSIC_FAKE            0x218
424
425 #define UHSIC_STROBE_VAL                (1 << 12)
426 #define UHSIC_DATA_VAL                  (1 << 13)
427 #define UHSIC_STROBE_ENB                (1 << 14)
428 #define UHSIC_DATA_ENB                  (1 << 15)
429 #define   USBON_VAL(inst)       (1 << ((4*(inst))+1))
430 #define   USBON_VAL_P2                  (1 << 9)
431 #define   USBON_VAL_P1                  (1 << 5)
432 #define   USBON_VAL_P0                  (1 << 1)
433 #define   USBOP_VAL(inst)       (1 << (4*(inst)))
434 #define   USBOP_VAL_P2                  (1 << 8)
435 #define   USBOP_VAL_P1                  (1 << 4)
436 #define   USBOP_VAL_P0                  (1 << 0)
437
438 #define PMC_UTMIP_BIAS_MASTER_CNTRL 0x30c
439 #define   BIAS_MASTER_PROG_VAL          (1 << 1)
440
441 #define PMC_UTMIP_MASTER_CONFIG 0x310
442
443 #define UTMIP_PWR(inst)         (1 << (inst))
444 #define UHSIC_PWR                       (1 << 3)
445
446 #define FUSE_USB_CALIB_0                0x1F0
447 #define   XCVR_SETUP(x) (((x) & 0x7F) << 0)
448 #define   XCVR_SETUP_LSB_MASK   0xF
449 #define   XCVR_SETUP_MSB_MASK   0x70
450 #define   XCVR_SETUP_LSB_MAX_VAL        0xF
451
452 #define APB_MISC_GP_OBSCTRL_0   0x818
453 #define APB_MISC_GP_OBSDATA_0   0x81c
454
455 /* ULPI GPIO */
456 #define ULPI_STP        TEGRA_GPIO_PY3
457 #define ULPI_DIR        TEGRA_GPIO_PY1
458 #define ULPI_D0         TEGRA_GPIO_PO1
459 #define ULPI_D1         TEGRA_GPIO_PO2
460
461 /* These values (in milli second) are taken from the battery charging spec */
462 #define TDP_SRC_ON_MS    100
463 #define TDPSRC_CON_MS    40
464
465 #ifdef DEBUG
466 #define DBG(stuff...)   pr_info("tegra3_usb_phy: " stuff)
467 #else
468 #define DBG(stuff...)   do {} while (0)
469 #endif
470
471 #if 0
472 #define PHY_DBG(stuff...)       pr_info("tegra3_usb_phy: " stuff)
473 #else
474 #define PHY_DBG(stuff...)       do {} while (0)
475 #endif
476
477
478 static u32 utmip_rctrl_val, utmip_tctrl_val;
479 static DEFINE_SPINLOCK(utmip_pad_lock);
480 static int utmip_pad_count;
481
482 static struct tegra_xtal_freq utmip_freq_table[] = {
483         {
484                 .freq = 12000000,
485                 .enable_delay = 0x02,
486                 .stable_count = 0x2F,
487                 .active_delay = 0x04,
488                 .xtal_freq_count = 0x76,
489                 .debounce = 0x7530,
490                 .pdtrk_count = 5,
491         },
492         {
493                 .freq = 13000000,
494                 .enable_delay = 0x02,
495                 .stable_count = 0x33,
496                 .active_delay = 0x05,
497                 .xtal_freq_count = 0x7F,
498                 .debounce = 0x7EF4,
499                 .pdtrk_count = 5,
500         },
501         {
502                 .freq = 19200000,
503                 .enable_delay = 0x03,
504                 .stable_count = 0x4B,
505                 .active_delay = 0x06,
506                 .xtal_freq_count = 0xBB,
507                 .debounce = 0xBB80,
508                 .pdtrk_count = 7,
509         },
510         {
511                 .freq = 26000000,
512                 .enable_delay = 0x04,
513                 .stable_count = 0x66,
514                 .active_delay = 0x09,
515                 .xtal_freq_count = 0xFE,
516                 .debounce = 0xFDE8,
517                 .pdtrk_count = 9,
518         },
519 };
520
521 static struct tegra_xtal_freq uhsic_freq_table[] = {
522         {
523                 .freq = 12000000,
524                 .enable_delay = 0x02,
525                 .stable_count = 0x2F,
526                 .active_delay = 0x0,
527                 .xtal_freq_count = 0x1CA,
528         },
529         {
530                 .freq = 13000000,
531                 .enable_delay = 0x02,
532                 .stable_count = 0x33,
533                 .active_delay = 0x0,
534                 .xtal_freq_count = 0x1F0,
535         },
536         {
537                 .freq = 19200000,
538                 .enable_delay = 0x03,
539                 .stable_count = 0x4B,
540                 .active_delay = 0x0,
541                 .xtal_freq_count = 0x2DD,
542         },
543         {
544                 .freq = 26000000,
545                 .enable_delay = 0x04,
546                 .stable_count = 0x66,
547                 .active_delay = 0x0,
548                 .xtal_freq_count = 0x3E0,
549         },
550 };
551
552 static void usb_phy_fence_read(struct tegra_usb_phy *phy)
553 {
554         /* Fence read for coherency of AHB master intiated writes */
555         if (phy->inst == 0)
556                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB1_PREFETCH_ID));
557         else if (phy->inst == 1)
558                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB2_PREFETCH_ID));
559         else if (phy->inst == 2)
560                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB3_PREFETCH_ID));
561
562         return;
563 }
564
565 static void utmip_setup_pmc_wake_detect(struct tegra_usb_phy *phy)
566 {
567         unsigned long val, pmc_pad_cfg_val;
568         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
569         unsigned  int inst = phy->inst;
570         void __iomem *base = phy->regs;
571         bool port_connected;
572         enum usb_phy_port_speed port_speed;
573
574         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
575
576         /* check for port connect status */
577         val = readl(base + USB_PORTSC);
578         port_connected = val & USB_PORTSC_CCS;
579
580         if (!port_connected)
581                 return;
582
583         port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
584                 HOSTPC1_DEVLC_PSPD_MASK;
585         /*Set PMC MASTER bits to do the following
586         * a. Take over the UTMI drivers
587         * b. set up such that it will take over resume
588         *        if remote wakeup is detected
589         * Prepare PMC to take over suspend-wake detect-drive resume until USB
590         * controller ready
591         */
592
593         /* disable master enable in PMC */
594         val = readl(pmc_base + PMC_SLEEP_CFG);
595         val &= ~UTMIP_MASTER_ENABLE(inst);
596         writel(val, pmc_base + PMC_SLEEP_CFG);
597
598         /* UTMIP_PWR_PX=1 for power savings mode */
599         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
600         val |= UTMIP_PWR(inst);
601         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
602
603         /* config debouncer */
604         val = readl(pmc_base + PMC_USB_DEBOUNCE);
605         val &= ~UTMIP_LINE_DEB_CNT(~0);
606         val |= UTMIP_LINE_DEB_CNT(4);
607         writel(val, pmc_base + PMC_USB_DEBOUNCE);
608
609         /* Make sure nothing is happening on the line with respect to PMC */
610         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
611         val &= ~USBOP_VAL(inst);
612         val &= ~USBON_VAL(inst);
613         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
614
615         /* Make sure wake value for line is none */
616         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
617         val &= ~UTMIP_LINEVAL_WALK_EN(inst);
618         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
619         val = readl(pmc_base + PMC_SLEEP_CFG);
620         val &= ~UTMIP_WAKE_VAL(inst, ~0);
621         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
622         writel(val, pmc_base + PMC_SLEEP_CFG);
623
624         /* turn off pad detectors */
625         val = readl(pmc_base + PMC_USB_AO);
626         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
627         writel(val, pmc_base + PMC_USB_AO);
628
629         /* Remove fake values and make synchronizers work a bit */
630         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
631         val &= ~USBOP_VAL(inst);
632         val &= ~USBON_VAL(inst);
633         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
634
635         /* Enable which type of event can trigger a walk,
636         in this case usb_line_wake */
637         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
638         val |= UTMIP_LINEVAL_WALK_EN(inst);
639         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
640
641         /* Enable which type of event can trigger a walk,
642         * in this case usb_line_wake */
643         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
644         val |= UTMIP_LINEVAL_WALK_EN(inst);
645         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
646
647         /* Capture FS/LS pad configurations */
648         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
649         val = readl(pmc_base + PMC_TRIGGERS);
650         val |= UTMIP_CAP_CFG(inst);
651         writel(val, pmc_base + PMC_TRIGGERS);
652         udelay(1);
653         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
654
655         /* BIAS MASTER_ENABLE=0 */
656         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
657         val &= ~BIAS_MASTER_PROG_VAL;
658         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
659
660         /* program walk sequence, maintain a J, followed by a driven K
661         * to signal a resume once an wake event is detected */
662         val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
663         val &= ~UTMIP_AP_A;
664         val |= UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_AN_A |UTMIP_HIGHZ_A |
665                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_AP_B | UTMIP_AN_B |
666                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_AP_C | UTMIP_AN_C |
667                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_AP_D | UTMIP_AN_D;
668         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
669
670         if (port_speed == USB_PHY_PORT_SPEED_LOW) {
671                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
672                 val &= ~(UTMIP_AN_B | UTMIP_HIGHZ_B | UTMIP_AN_C |
673                         UTMIP_HIGHZ_C | UTMIP_AN_D | UTMIP_HIGHZ_D);
674                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
675         } else {
676                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
677                 val &= ~(UTMIP_AP_B | UTMIP_HIGHZ_B | UTMIP_AP_C |
678                         UTMIP_HIGHZ_C | UTMIP_AP_D | UTMIP_HIGHZ_D);
679                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
680         }
681
682         /* turn on pad detectors */
683         val = readl(pmc_base + PMC_USB_AO);
684         val &= ~(USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
685         writel(val, pmc_base + PMC_USB_AO);
686
687         /* Add small delay before usb detectors provide stable line values */
688         mdelay(1);
689
690         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
691         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
692         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
693         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
694
695         phy->remote_wakeup = false;
696
697         /* Turn over pad configuration to PMC  for line wake events*/
698         val = readl(pmc_base + PMC_SLEEP_CFG);
699         val &= ~UTMIP_WAKE_VAL(inst, ~0);
700         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_ANY);
701         val |= UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst);
702         val |= UTMIP_MASTER_ENABLE(inst) | UTMIP_FSLS_USE_PMC(inst);
703         writel(val, pmc_base + PMC_SLEEP_CFG);
704
705         val = readl(base + UTMIP_PMC_WAKEUP0);
706         val |= EVENT_INT_ENB;
707         writel(val, base + UTMIP_PMC_WAKEUP0);
708         PHY_DBG("%s ENABLE_PMC inst = %d\n", __func__, inst);
709 }
710
711 static void utmip_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy)
712 {
713         unsigned long val;
714         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
715         unsigned  int inst = phy->inst;
716         void __iomem *base = phy->regs;
717
718         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
719
720         val = readl(pmc_base + PMC_SLEEP_CFG);
721         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
722         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
723         writel(val, pmc_base + PMC_SLEEP_CFG);
724
725         val = readl(base + UTMIP_PMC_WAKEUP0);
726         val &= ~EVENT_INT_ENB;
727         writel(val, base + UTMIP_PMC_WAKEUP0);
728
729         /* Disable PMC master mode by clearing MASTER_EN */
730         val = readl(pmc_base + PMC_SLEEP_CFG);
731         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
732                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
733         writel(val, pmc_base + PMC_SLEEP_CFG);
734
735         val = readl(pmc_base + PMC_TRIGGERS);
736         val &= ~UTMIP_CAP_CFG(inst);
737         writel(val, pmc_base + PMC_TRIGGERS);
738
739         /* turn off pad detectors */
740         val = readl(pmc_base + PMC_USB_AO);
741         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
742         writel(val, pmc_base + PMC_USB_AO);
743
744         val = readl(pmc_base + PMC_TRIGGERS);
745         val |= UTMIP_CLR_WALK_PTR(inst);
746         writel(val, pmc_base + PMC_TRIGGERS);
747
748         phy->remote_wakeup = false;
749         PHY_DBG("%s DISABLE_PMC inst = %d\n", __func__, inst);
750 }
751
752 static bool utmi_phy_remotewake_detected(struct tegra_usb_phy *phy)
753 {
754         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
755         void __iomem *base = phy->regs;
756         unsigned  int inst = phy->inst;
757         u32 val;
758
759         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
760         val = readl(base + UTMIP_PMC_WAKEUP0);
761         if (val & EVENT_INT_ENB) {
762                 val = readl(pmc_base + UTMIP_UHSIC_STATUS);
763                 if (UTMIP_WAKE_ALARM(inst) & val) {
764                         val = readl(pmc_base + PMC_SLEEP_CFG);
765                         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
766                         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
767                         writel(val, pmc_base + PMC_SLEEP_CFG);
768
769                         val = readl(pmc_base + PMC_TRIGGERS);
770                         val |= UTMIP_CLR_WAKE_ALARM(inst);
771                         writel(val, pmc_base + PMC_TRIGGERS);
772
773                         val = readl(base + UTMIP_PMC_WAKEUP0);
774                         val &= ~EVENT_INT_ENB;
775                         writel(val, base + UTMIP_PMC_WAKEUP0);
776                         phy->remote_wakeup = true;
777                         return true;
778                 }
779         }
780         return false;
781 }
782
783 static void utmi_phy_enable_trking_data(struct tegra_usb_phy *phy)
784 {
785         void __iomem *base = IO_ADDRESS(TEGRA_USB_BASE);
786         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
787         static bool init_done = false;
788         u32 val;
789
790         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
791
792         /* Should be done only once after system boot */
793         if (init_done)
794                 return;
795
796         clk_enable(phy->utmi_pad_clk);
797         /* Bias pad MASTER_ENABLE=1 */
798         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
799         val |= BIAS_MASTER_PROG_VAL;
800         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
801
802         /* Setting the tracking length time */
803         val = readl(base + UTMIP_BIAS_CFG1);
804         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
805         val |= UTMIP_BIAS_PDTRK_COUNT(5);
806         writel(val, base + UTMIP_BIAS_CFG1);
807
808         /* Bias PDTRK is Shared and MUST be done from USB1 ONLY, PD_TRK=0 */
809         val = readl(base + UTMIP_BIAS_CFG1);
810         val &= ~UTMIP_BIAS_PDTRK_POWERDOWN;
811         writel(val, base + UTMIP_BIAS_CFG1);
812
813         val = readl(base + UTMIP_BIAS_CFG1);
814         val |= UTMIP_BIAS_PDTRK_POWERUP;
815         writel(val, base + UTMIP_BIAS_CFG1);
816
817         /* Wait for 25usec */
818         udelay(25);
819
820         /* Bias pad MASTER_ENABLE=0 */
821         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
822         val &= ~BIAS_MASTER_PROG_VAL;
823         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
824
825         /* Wait for 1usec */
826         udelay(1);
827
828         /* Bias pad MASTER_ENABLE=1 */
829         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
830         val |= BIAS_MASTER_PROG_VAL;
831         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
832
833         /* Read RCTRL and TCTRL from UTMIP space */
834         val = readl(base + UTMIP_BIAS_STS0);
835         utmip_rctrl_val = ffz(UTMIP_RCTRL_VAL(val));
836         utmip_tctrl_val = ffz(UTMIP_TCTRL_VAL(val));
837
838         /* PD_TRK=1 */
839         val = readl(base + UTMIP_BIAS_CFG1);
840         val |= UTMIP_BIAS_PDTRK_POWERDOWN;
841         writel(val, base + UTMIP_BIAS_CFG1);
842
843         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
844         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
845         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
846         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
847         clk_disable(phy->utmi_pad_clk);
848         init_done = true;
849 }
850
851 static void utmip_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy)
852 {
853         unsigned long val;
854         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
855         unsigned  int inst = phy->inst;
856
857         /* power down UTMIP interfaces */
858         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
859         val |= UTMIP_PWR(inst);
860         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
861
862         /* setup sleep walk usb controller */
863         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
864                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
865                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
866                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
867         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
868
869         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
870         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
871         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
872         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
873
874         /* Turn over pad configuration to PMC */
875         val = readl(pmc_base + PMC_SLEEP_CFG);
876         val &= ~UTMIP_WAKE_VAL(inst, ~0);
877         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE) |
878                 UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
879                 UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst);
880         writel(val, pmc_base + PMC_SLEEP_CFG);
881         PHY_DBG("%s ENABLE_PMC inst = %d\n", __func__, inst);
882 }
883
884 static void utmip_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
885 {
886         unsigned long val;
887         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
888         unsigned  int inst = phy->inst;
889
890         /* Disable PMC master mode by clearing MASTER_EN */
891         val = readl(pmc_base + PMC_SLEEP_CFG);
892         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
893                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
894         writel(val, pmc_base + PMC_SLEEP_CFG);
895         mdelay(1);
896         PHY_DBG("%s DISABLE_PMC inst = %d\n", __func__, inst);
897 }
898
899
900 #ifdef KERNEL_WARNING
901 static void usb_phy_power_down_pmc(void)
902 {
903         unsigned long val;
904         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
905
906         /* power down all 3 UTMIP interfaces */
907         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
908         val |= UTMIP_PWR(0) | UTMIP_PWR(1) | UTMIP_PWR(2);
909         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
910
911         /* turn on pad detectors */
912         writel(PMC_POWER_DOWN_MASK, pmc_base + PMC_USB_AO);
913
914         /* setup sleep walk fl all 3 usb controllers */
915         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
916                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
917                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
918                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
919         writel(val, pmc_base + PMC_SLEEPWALK_REG(0));
920         writel(val, pmc_base + PMC_SLEEPWALK_REG(1));
921         writel(val, pmc_base + PMC_SLEEPWALK_REG(2));
922
923         /* enable pull downs on HSIC PMC */
924         val = UHSIC_STROBE_RPD_A | UHSIC_DATA_RPD_A | UHSIC_STROBE_RPD_B |
925                 UHSIC_DATA_RPD_B | UHSIC_STROBE_RPD_C | UHSIC_DATA_RPD_C |
926                 UHSIC_STROBE_RPD_D | UHSIC_DATA_RPD_D;
927         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
928
929         /* Turn over pad configuration to PMC */
930         val = readl(pmc_base + PMC_SLEEP_CFG);
931         val &= ~UTMIP_WAKE_VAL(0, ~0);
932         val &= ~UTMIP_WAKE_VAL(1, ~0);
933         val &= ~UTMIP_WAKE_VAL(2, ~0);
934         val &= ~UHSIC_WAKE_VAL_P0(~0);
935         val |= UTMIP_WAKE_VAL(0, WAKE_VAL_NONE) | UHSIC_WAKE_VAL_P0(WAKE_VAL_NONE) |
936         UTMIP_WAKE_VAL(1, WAKE_VAL_NONE) | UTMIP_WAKE_VAL(2, WAKE_VAL_NONE) |
937         UTMIP_RCTRL_USE_PMC(0) | UTMIP_RCTRL_USE_PMC(1) | UTMIP_RCTRL_USE_PMC(2) |
938         UTMIP_TCTRL_USE_PMC(0) | UTMIP_TCTRL_USE_PMC(1) | UTMIP_TCTRL_USE_PMC(2) |
939         UTMIP_FSLS_USE_PMC(0) | UTMIP_FSLS_USE_PMC(1) | UTMIP_FSLS_USE_PMC(2) |
940         UTMIP_MASTER_ENABLE(0) | UTMIP_MASTER_ENABLE(1) | UTMIP_MASTER_ENABLE(2) |
941         UHSIC_MASTER_ENABLE_P0;
942         writel(val, pmc_base + PMC_SLEEP_CFG);
943 }
944 #endif
945
946 static int usb_phy_bringup_host_controller(struct tegra_usb_phy *phy)
947 {
948         unsigned long val;
949         void __iomem *base = phy->regs;
950
951         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
952         PHY_DBG("[%d] USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n", __LINE__,
953                 readl(base + USB_USBSTS), readl(base + USB_PORTSC),
954                                                         phy->port_speed);
955
956         /* Device is plugged in when system is in LP0 */
957         /* Bring up the controller from LP0*/
958         val = readl(base + USB_USBCMD);
959         val |= USB_CMD_RESET;
960         writel(val, base + USB_USBCMD);
961
962         if (usb_phy_reg_status_wait(base + USB_USBCMD,
963                 USB_CMD_RESET, 0, 2500) < 0) {
964                 pr_err("%s: timeout waiting for reset\n", __func__);
965         }
966
967         val = readl(base + USB_USBMODE);
968         val &= ~USB_USBMODE_MASK;
969         val |= USB_USBMODE_HOST;
970         writel(val, base + USB_USBMODE);
971         val = readl(base + HOSTPC1_DEVLC);
972         val &= ~HOSTPC1_DEVLC_PTS(~0);
973
974         if (phy->pdata->phy_intf == TEGRA_USB_PHY_INTF_HSIC)
975                 val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
976         else
977                 val |= HOSTPC1_DEVLC_STS;
978         writel(val, base + HOSTPC1_DEVLC);
979
980         /* Enable Port Power */
981         val = readl(base + USB_PORTSC);
982         val |= USB_PORTSC_PP;
983         writel(val, base + USB_PORTSC);
984         udelay(10);
985
986         /* Check if the phy resume from LP0. When the phy resume from LP0
987          * USB register will be reset.to zero */
988         if (!readl(base + USB_ASYNCLISTADDR)) {
989                 /* Program the field PTC based on the saved speed mode */
990                 val = readl(base + USB_PORTSC);
991                 val &= ~USB_PORTSC_PTC(~0);
992                 if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH)
993                         val |= USB_PORTSC_PTC(5);
994                 else if (phy->port_speed == USB_PHY_PORT_SPEED_FULL)
995                         val |= USB_PORTSC_PTC(6);
996                 else if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
997                         val |= USB_PORTSC_PTC(7);
998                 writel(val, base + USB_PORTSC);
999                 udelay(10);
1000
1001                 /* Disable test mode by setting PTC field to NORMAL_OP */
1002                 val = readl(base + USB_PORTSC);
1003                 val &= ~USB_PORTSC_PTC(~0);
1004                 writel(val, base + USB_PORTSC);
1005                 udelay(10);
1006         }
1007
1008         /* Poll until CCS is enabled */
1009         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
1010                                                  USB_PORTSC_CCS, 2000)) {
1011                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
1012         }
1013
1014         /* Poll until PE is enabled */
1015         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_PE,
1016                                                  USB_PORTSC_PE, 2000)) {
1017                 pr_err("%s: timeout waiting for USB_PORTSC_PE\n", __func__);
1018         }
1019
1020         /* Clear the PCI status, to avoid an interrupt taken upon resume */
1021         val = readl(base + USB_USBSTS);
1022         val |= USB_USBSTS_PCI;
1023         writel(val, base + USB_USBSTS);
1024
1025         if (!phy->remote_wakeup) {
1026                 /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
1027                 val = readl(base + USB_PORTSC);
1028                 if ((val & USB_PORTSC_PP) && (val & USB_PORTSC_PE)) {
1029                         val |= USB_PORTSC_SUSP;
1030                         writel(val, base + USB_PORTSC);
1031                         /* Need a 4ms delay before the controller goes to suspend */
1032                         mdelay(4);
1033
1034                         /* Wait until port suspend completes */
1035                         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_SUSP,
1036                                                          USB_PORTSC_SUSP, 1000)) {
1037                                 pr_err("%s: timeout waiting for PORT_SUSPEND\n",
1038                                                                         __func__);
1039                         }
1040                 }
1041         }
1042         PHY_DBG("[%d] USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n", __LINE__,
1043                 readl(base + USB_USBSTS), readl(base + USB_PORTSC),
1044                                                         phy->port_speed);
1045
1046         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1047                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1048         return 0;
1049 }
1050
1051 static void usb_phy_wait_for_sof(struct tegra_usb_phy *phy)
1052 {
1053         unsigned long val;
1054         void __iomem *base = phy->regs;
1055
1056         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1057
1058         val = readl(base + USB_USBSTS);
1059         writel(val, base + USB_USBSTS);
1060         udelay(20);
1061         /* wait for two SOFs */
1062         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1063                 USB_USBSTS_SRI, 2500))
1064                 pr_err("%s: timeout waiting for SOF\n", __func__);
1065
1066         val = readl(base + USB_USBSTS);
1067         writel(val, base + USB_USBSTS);
1068         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI, 0, 2500))
1069                 pr_err("%s: timeout waiting for SOF\n", __func__);
1070
1071         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1072                         USB_USBSTS_SRI, 2500))
1073                 pr_err("%s: timeout waiting for SOF\n", __func__);
1074
1075         udelay(20);
1076 }
1077
1078 static unsigned int utmi_phy_xcvr_setup_value(struct tegra_usb_phy *phy)
1079 {
1080         struct tegra_utmi_config *cfg = &phy->pdata->u_cfg.utmi;
1081         signed long val;
1082
1083         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1084
1085         if (cfg->xcvr_use_fuses) {
1086                 val = XCVR_SETUP(tegra_fuse_readl(FUSE_USB_CALIB_0));
1087                 if (cfg->xcvr_use_lsb) {
1088                         val = min((unsigned int) ((val & XCVR_SETUP_LSB_MASK)
1089                                 + cfg->xcvr_setup_offset),
1090                                 (unsigned int) XCVR_SETUP_LSB_MAX_VAL);
1091                         val |= (cfg->xcvr_setup & XCVR_SETUP_MSB_MASK);
1092                 } else {
1093                         if (cfg->xcvr_setup_offset <= UTMIP_XCVR_MAX_OFFSET)
1094                                 val = val + cfg->xcvr_setup_offset;
1095
1096                         if (val > UTMIP_XCVR_SETUP_MAX_VALUE) {
1097                                 val = UTMIP_XCVR_SETUP_MAX_VALUE;
1098                                 pr_info("%s: reset XCVR_SETUP to max value\n",
1099                                                 __func__);
1100                         } else if (val < UTMIP_XCVR_SETUP_MIN_VALUE) {
1101                                 val = UTMIP_XCVR_SETUP_MIN_VALUE;
1102                                 pr_info("%s: reset XCVR_SETUP to min value\n",
1103                                                 __func__);
1104                         }
1105                 }
1106         } else {
1107                 val = cfg->xcvr_setup;
1108         }
1109
1110         return (unsigned int) val;
1111 }
1112
1113 static int utmi_phy_open(struct tegra_usb_phy *phy)
1114 {
1115         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1116         unsigned long parent_rate, val;
1117         int i;
1118
1119         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1120
1121         phy->utmi_pad_clk = clk_get_sys("utmip-pad", NULL);
1122         if (IS_ERR(phy->utmi_pad_clk)) {
1123                 pr_err("%s: can't get utmip pad clock\n", __func__);
1124                 return PTR_ERR(phy->utmi_pad_clk);
1125         }
1126
1127         phy->utmi_xcvr_setup = utmi_phy_xcvr_setup_value(phy);
1128
1129         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
1130         for (i = 0; i < ARRAY_SIZE(utmip_freq_table); i++) {
1131                 if (utmip_freq_table[i].freq == parent_rate) {
1132                         phy->freq = &utmip_freq_table[i];
1133                         break;
1134                 }
1135         }
1136         if (!phy->freq) {
1137                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
1138                 return -EINVAL;
1139         }
1140
1141         /* Power-up the VBUS detector for UTMIP PHY */
1142         val = readl(pmc_base + PMC_USB_AO);
1143         val &= ~(PMC_USB_AO_VBUS_WAKEUP_PD_P0 | PMC_USB_AO_ID_PD_P0);
1144         writel((val | PMC_USB_AO_PD_P2), (pmc_base + PMC_USB_AO));
1145
1146         utmip_powerup_pmc_wake_detect(phy);
1147
1148         return 0;
1149 }
1150
1151 static void utmi_phy_close(struct tegra_usb_phy *phy)
1152 {
1153         unsigned long val;
1154         void __iomem *base = phy->regs;
1155
1156         DBG("%s inst:[%d]\n", __func__, phy->inst);
1157
1158         /* Disable PHY clock valid interrupts while going into suspend*/
1159         if (phy->pdata->u_data.host.hot_plug) {
1160                 val = readl(base + USB_SUSP_CTRL);
1161                 val &= ~USB_PHY_CLK_VALID_INT_ENB;
1162                 writel(val, base + USB_SUSP_CTRL);
1163         }
1164
1165         clk_put(phy->utmi_pad_clk);
1166 }
1167
1168 static int utmi_phy_pad_power_on(struct tegra_usb_phy *phy)
1169 {
1170         unsigned long val, flags;
1171         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1172
1173         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1174
1175         clk_enable(phy->utmi_pad_clk);
1176
1177         spin_lock_irqsave(&utmip_pad_lock, flags);
1178         utmip_pad_count++;
1179
1180         val = readl(pad_base + UTMIP_BIAS_CFG0);
1181         val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
1182         val |= UTMIP_HSSQUELCH_LEVEL(0x2) | UTMIP_HSDISCON_LEVEL(0x1) |
1183                 UTMIP_HSDISCON_LEVEL_MSB;
1184         writel(val, pad_base + UTMIP_BIAS_CFG0);
1185
1186         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1187
1188         clk_disable(phy->utmi_pad_clk);
1189
1190         return 0;
1191 }
1192
1193 static int utmi_phy_pad_power_off(struct tegra_usb_phy *phy)
1194 {
1195         unsigned long val, flags;
1196         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1197
1198         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1199
1200         clk_enable(phy->utmi_pad_clk);
1201         spin_lock_irqsave(&utmip_pad_lock, flags);
1202
1203         if (!utmip_pad_count) {
1204                 pr_err("%s: utmip pad already powered off\n", __func__);
1205                 goto out;
1206         }
1207         if (--utmip_pad_count == 0) {
1208                 val = readl(pad_base + UTMIP_BIAS_CFG0);
1209                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
1210                 val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) | UTMIP_HSDISCON_LEVEL(~0) |
1211                         UTMIP_HSDISCON_LEVEL_MSB);
1212                 writel(val, pad_base + UTMIP_BIAS_CFG0);
1213         }
1214 out:
1215         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1216         clk_disable(phy->utmi_pad_clk);
1217
1218         return 0;
1219 }
1220
1221 static int utmi_phy_irq(struct tegra_usb_phy *phy)
1222 {
1223         void __iomem *base = phy->regs;
1224         unsigned long val = 0;
1225
1226         if (phy->phy_clk_on) {
1227                 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1228                 DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1229                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1230                 DBG("USB_USBMODE[0x%x] USB_USBCMD[0x%x]\n",
1231                         readl(base + USB_USBMODE), readl(base + USB_USBCMD));
1232         }
1233
1234         usb_phy_fence_read(phy);
1235         /* check if there is any remote wake event */
1236         if (utmi_phy_remotewake_detected(phy))
1237                 pr_info("%s: utmip remote wake detected\n", __func__);
1238
1239         if (phy->pdata->u_data.host.hot_plug) {
1240                 val = readl(base + USB_SUSP_CTRL);
1241                 if ((val  & USB_PHY_CLK_VALID_INT_STS)) {
1242                         val &= ~USB_PHY_CLK_VALID_INT_ENB |
1243                                         USB_PHY_CLK_VALID_INT_STS;
1244                         writel(val , (base + USB_SUSP_CTRL));
1245                         pr_info("%s: usb device plugged-in\n", __func__);
1246                         val = readl(base + USB_USBSTS);
1247                         if (!(val  & USB_USBSTS_PCI))
1248                                 return IRQ_NONE;
1249                         val = readl(base + USB_PORTSC);
1250                         val &= ~(USB_PORTSC_WKCN | USB_PORTSC_RWC_BITS);
1251                         writel(val , (base + USB_PORTSC));
1252                 } else if (!phy->phy_clk_on) {
1253                         return IRQ_NONE;
1254                 }
1255         }
1256
1257         return IRQ_HANDLED;
1258 }
1259
1260 static void utmi_phy_enable_obs_bus(struct tegra_usb_phy *phy)
1261 {
1262         unsigned long val;
1263         void __iomem *base = phy->regs;
1264
1265         /* (2LS WAR)is not required for LS and FS devices and is only for HS */
1266         if ((phy->port_speed == USB_PHY_PORT_SPEED_LOW) ||
1267                 (phy->port_speed == USB_PHY_PORT_SPEED_FULL)) {
1268                 /* do not enable the OBS bus */
1269                 val = readl(base + UTMIP_MISC_CFG0);
1270                 val &= ~(UTMIP_DPDM_OBSERVE_SEL(~0));
1271                 writel(val, base + UTMIP_MISC_CFG0);
1272                 DBG("%s(%d) Disable OBS bus\n", __func__, __LINE__);
1273                 return;
1274         }
1275         /* Force DP/DM pulldown active for Host mode */
1276         val = readl(base + UTMIP_MISC_CFG0);
1277         val |= FORCE_PULLDN_DM | FORCE_PULLDN_DP |
1278                         COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS;
1279         writel(val, base + UTMIP_MISC_CFG0);
1280         val = readl(base + UTMIP_MISC_CFG0);
1281         val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1282         if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
1283                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
1284         else
1285                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
1286         writel(val, base + UTMIP_MISC_CFG0);
1287         udelay(1);
1288
1289         val = readl(base + UTMIP_MISC_CFG0);
1290         val |= UTMIP_DPDM_OBSERVE;
1291         writel(val, base + UTMIP_MISC_CFG0);
1292         udelay(10);
1293         DBG("%s(%d) Enable OBS bus\n", __func__, __LINE__);
1294         PHY_DBG("ENABLE_OBS_BUS\n");
1295 }
1296
1297 static int utmi_phy_disable_obs_bus(struct tegra_usb_phy *phy)
1298 {
1299         unsigned long val;
1300         void __iomem *base = phy->regs;
1301         unsigned long flags;
1302
1303         /* check if OBS bus is already enabled */
1304         val = readl(base + UTMIP_MISC_CFG0);
1305         if (val & UTMIP_DPDM_OBSERVE) {
1306                 PHY_DBG("DISABLE_OBS_BUS\n");
1307
1308                 /* disable ALL interrupts on current CPU */
1309                 local_irq_save(flags);
1310
1311                 /* Change the UTMIP OBS bus to drive SE0 */
1312                 val = readl(base + UTMIP_MISC_CFG0);
1313                 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1314                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_SE0;
1315                 writel(val, base + UTMIP_MISC_CFG0);
1316
1317                 /* Wait for 3us(2 LS bit times) */
1318                 udelay(3);
1319
1320                 /* Release UTMIP OBS bus */
1321                 val = readl(base + UTMIP_MISC_CFG0);
1322                 val &= ~UTMIP_DPDM_OBSERVE;
1323                 writel(val, base + UTMIP_MISC_CFG0);
1324
1325                 /* Release DP/DM pulldown for Host mode */
1326                 val = readl(base + UTMIP_MISC_CFG0);
1327                 val &= ~(FORCE_PULLDN_DM | FORCE_PULLDN_DP |
1328                                 COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS);
1329                 writel(val, base + UTMIP_MISC_CFG0);
1330
1331                 val = readl(base + USB_USBCMD);
1332                 val |= USB_USBCMD_RS;
1333                 writel(val, base + USB_USBCMD);
1334
1335                 /* restore ALL interrupts on current CPU */
1336                 local_irq_restore(flags);
1337
1338                 if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
1339                                                          USB_USBCMD_RS, 2000)) {
1340                         pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
1341                         return -ETIMEDOUT;
1342                 }
1343         }
1344         return 0;
1345 }
1346
1347 static int utmi_phy_post_resume(struct tegra_usb_phy *phy)
1348 {
1349         unsigned long val;
1350         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1351         unsigned  int inst = phy->inst;
1352
1353         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1354         val = readl(pmc_base + PMC_SLEEP_CFG);
1355         /* if PMC is not disabled by now then disable it */
1356         if (val & UTMIP_MASTER_ENABLE(inst)) {
1357                 utmip_phy_disable_pmc_bus_ctrl(phy);
1358         }
1359
1360         utmi_phy_disable_obs_bus(phy);
1361
1362         return 0;
1363 }
1364
1365 static int phy_post_suspend(struct tegra_usb_phy *phy)
1366 {
1367
1368         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1369         /* Need a 4ms delay for controller to suspend */
1370         mdelay(4);
1371
1372         return 0;
1373
1374 }
1375
1376 static int utmi_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1377 {
1378         unsigned long val;
1379         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1380         void __iomem *base = phy->regs;
1381         unsigned  int inst = phy->inst;
1382
1383         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1384         phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
1385                         HOSTPC1_DEVLC_PSPD_MASK;
1386
1387         if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH) {
1388                 /* Disable interrupts */
1389                 writel(0, base + USB_USBINTR);
1390                 /* Clear the run bit to stop SOFs - 2LS WAR */
1391                 val = readl(base + USB_USBCMD);
1392                 val &= ~USB_USBCMD_RS;
1393                 writel(val, base + USB_USBCMD);
1394                 if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
1395                                                          USB_USBSTS_HCH, 2000)) {
1396                         pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
1397                 }
1398         }
1399
1400         val = readl(pmc_base + PMC_SLEEP_CFG);
1401         if (val & UTMIP_MASTER_ENABLE(inst)) {
1402                 if (!remote_wakeup)
1403                         utmip_phy_disable_pmc_bus_ctrl(phy);
1404         } else {
1405                 utmi_phy_enable_obs_bus(phy);
1406         }
1407
1408         return 0;
1409 }
1410
1411 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
1412 {
1413         unsigned long val;
1414         void __iomem *base = phy->regs;
1415
1416         PHY_DBG("%s(%d) inst:[%d] BEGIN\n", __func__, __LINE__, phy->inst);
1417         if (!phy->phy_clk_on) {
1418                 PHY_DBG("%s(%d) inst:[%d] phy clk is already off\n",
1419                                         __func__, __LINE__, phy->inst);
1420                 return 0;
1421         }
1422
1423         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1424                 utmip_powerdown_pmc_wake_detect(phy);
1425
1426                 val = readl(base + USB_SUSP_CTRL);
1427                 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
1428                 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
1429                 writel(val, base + USB_SUSP_CTRL);
1430
1431                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1432                 val |= UTMIP_PD_CHRG;
1433                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1434         } else {
1435                 phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
1436                                 HOSTPC1_DEVLC_PSPD_MASK;
1437
1438                 /* Disable interrupts */
1439                 writel(0, base + USB_USBINTR);
1440
1441                 /* Clear the run bit to stop SOFs - 2LS WAR */
1442                 val = readl(base + USB_USBCMD);
1443                 val &= ~USB_USBCMD_RS;
1444                 writel(val, base + USB_USBCMD);
1445
1446                 if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
1447                                                          USB_USBSTS_HCH, 2000)) {
1448                         pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
1449                 }
1450                 utmip_setup_pmc_wake_detect(phy);
1451         }
1452
1453         if (!phy->pdata->u_data.host.hot_plug) {
1454                 val = readl(base + UTMIP_XCVR_CFG0);
1455                 val |= (UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
1456                          UTMIP_FORCE_PDZI_POWERDOWN);
1457                 writel(val, base + UTMIP_XCVR_CFG0);
1458         }
1459
1460         val = readl(base + UTMIP_XCVR_CFG1);
1461         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1462                    UTMIP_FORCE_PDDR_POWERDOWN;
1463         writel(val, base + UTMIP_XCVR_CFG1);
1464
1465         val = readl(base + UTMIP_BIAS_CFG1);
1466         val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
1467         writel(val, base + UTMIP_BIAS_CFG1);
1468
1469         utmi_phy_pad_power_off(phy);
1470
1471         if (phy->pdata->u_data.host.hot_plug) {
1472                 bool enable_hotplug = true;
1473                 /* if it is OTG port then make sure to enable hot-plug feature
1474                    only if host adaptor is connected, i.e id is low */
1475                 if (phy->pdata->port_otg) {
1476                         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1477                         enable_hotplug = (val & USB_ID_STATUS) ? false : true;
1478                 }
1479                 if (enable_hotplug) {
1480                         val = readl(base + USB_PORTSC);
1481                         val |= USB_PORTSC_WKCN;
1482                         writel(val, base + USB_PORTSC);
1483
1484                         val = readl(base + USB_SUSP_CTRL);
1485                         val |= USB_PHY_CLK_VALID_INT_ENB;
1486                         writel(val, base + USB_SUSP_CTRL);
1487                 } else {
1488                         /* Disable PHY clock valid interrupts while going into suspend*/
1489                         val = readl(base + USB_SUSP_CTRL);
1490                         val &= ~USB_PHY_CLK_VALID_INT_ENB;
1491                         writel(val, base + USB_SUSP_CTRL);
1492                 }
1493         }
1494
1495         val = readl(base + HOSTPC1_DEVLC);
1496         val |= HOSTPC1_DEVLC_PHCD;
1497         writel(val, base + HOSTPC1_DEVLC);
1498
1499         if (!phy->pdata->u_data.host.hot_plug) {
1500                 val = readl(base + USB_SUSP_CTRL);
1501                 val |= UTMIP_RESET;
1502                 writel(val, base + USB_SUSP_CTRL);
1503         }
1504
1505         phy->phy_clk_on = false;
1506         phy->hw_accessible = false;
1507
1508         PHY_DBG("%s(%d) inst:[%d] END\n", __func__, __LINE__, phy->inst);
1509
1510         return 0;
1511 }
1512
1513
1514 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
1515 {
1516         unsigned long val;
1517         void __iomem *base = phy->regs;
1518         struct tegra_utmi_config *config = &phy->pdata->u_cfg.utmi;
1519
1520         PHY_DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1521         if (phy->phy_clk_on) {
1522                 PHY_DBG("%s(%d) inst:[%d] phy clk is already On\n",
1523                                         __func__, __LINE__, phy->inst);
1524                 return 0;
1525         }
1526         val = readl(base + USB_SUSP_CTRL);
1527         val |= UTMIP_RESET;
1528         writel(val, base + USB_SUSP_CTRL);
1529
1530         val = readl(base + UTMIP_TX_CFG0);
1531         val |= UTMIP_FS_PREABMLE_J;
1532         writel(val, base + UTMIP_TX_CFG0);
1533
1534         val = readl(base + UTMIP_HSRX_CFG0);
1535         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
1536         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
1537         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
1538         writel(val, base + UTMIP_HSRX_CFG0);
1539
1540         val = readl(base + UTMIP_HSRX_CFG1);
1541         val &= ~UTMIP_HS_SYNC_START_DLY(~0);
1542         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
1543         writel(val, base + UTMIP_HSRX_CFG1);
1544
1545         val = readl(base + UTMIP_DEBOUNCE_CFG0);
1546         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
1547         val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
1548         writel(val, base + UTMIP_DEBOUNCE_CFG0);
1549
1550         val = readl(base + UTMIP_MISC_CFG0);
1551         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
1552         writel(val, base + UTMIP_MISC_CFG0);
1553
1554         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1555                 val = readl(base + USB_SUSP_CTRL);
1556                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
1557                 writel(val, base + USB_SUSP_CTRL);
1558
1559                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1560                 val &= ~UTMIP_PD_CHRG;
1561                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1562         } else {
1563                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1564                 val |= UTMIP_PD_CHRG;
1565                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1566         }
1567
1568         utmi_phy_pad_power_on(phy);
1569
1570         val = readl(base + UTMIP_XCVR_CFG0);
1571         val &= ~(UTMIP_XCVR_LSBIAS_SEL | UTMIP_FORCE_PD_POWERDOWN |
1572                  UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN |
1573                  UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_LSFSLEW(~0) |
1574                  UTMIP_XCVR_LSRSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
1575         val |= UTMIP_XCVR_SETUP(phy->utmi_xcvr_setup);
1576         val |= UTMIP_XCVR_SETUP_MSB(XCVR_SETUP_MSB_CALIB(phy->utmi_xcvr_setup));
1577         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
1578         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
1579         if (!config->xcvr_use_lsb)
1580                 val |= UTMIP_XCVR_HSSLEW_MSB(0x8);
1581         writel(val, base + UTMIP_XCVR_CFG0);
1582
1583         val = readl(base + UTMIP_XCVR_CFG1);
1584         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1585                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
1586         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
1587         writel(val, base + UTMIP_XCVR_CFG1);
1588
1589         val = readl(base + UTMIP_BIAS_CFG1);
1590         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
1591         val |= UTMIP_BIAS_PDTRK_COUNT(phy->freq->pdtrk_count);
1592         writel(val, base + UTMIP_BIAS_CFG1);
1593
1594         val = readl(base + UTMIP_SPARE_CFG0);
1595         val &= ~FUSE_SETUP_SEL;
1596         val |= FUSE_ATERM_SEL;
1597         writel(val, base + UTMIP_SPARE_CFG0);
1598
1599         val = readl(base + USB_SUSP_CTRL);
1600         val |= UTMIP_PHY_ENABLE;
1601         writel(val, base + USB_SUSP_CTRL);
1602
1603         val = readl(base + USB_SUSP_CTRL);
1604         val &= ~UTMIP_RESET;
1605         writel(val, base + USB_SUSP_CTRL);
1606
1607         val = readl(base + HOSTPC1_DEVLC);
1608         val &= ~HOSTPC1_DEVLC_PHCD;
1609         writel(val, base + HOSTPC1_DEVLC);
1610
1611         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1612                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500))
1613                 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
1614
1615         utmi_phy_enable_trking_data(phy);
1616
1617         if (phy->inst == 2)
1618                 writel(0, base + ICUSB_CTRL);
1619
1620         val = readl(base + USB_USBMODE);
1621         val &= ~USB_USBMODE_MASK;
1622         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST)
1623                 val |= USB_USBMODE_HOST;
1624         else
1625                 val |= USB_USBMODE_DEVICE;
1626         writel(val, base + USB_USBMODE);
1627
1628         val = readl(base + HOSTPC1_DEVLC);
1629         val &= ~HOSTPC1_DEVLC_PTS(~0);
1630         val |= HOSTPC1_DEVLC_STS;
1631         writel(val, base + HOSTPC1_DEVLC);
1632
1633         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE)
1634                 utmip_powerup_pmc_wake_detect(phy);
1635         phy->phy_clk_on = true;
1636         phy->hw_accessible = true;
1637         PHY_DBG("%s(%d) End inst:[%d]\n", __func__, __LINE__, phy->inst);
1638         return 0;
1639 }
1640
1641 static void utmi_phy_restore_start(struct tegra_usb_phy *phy)
1642 {
1643         unsigned long val;
1644         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1645         int inst = phy->inst;
1646
1647         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1648         val = readl(pmc_base + UTMIP_UHSIC_STATUS);
1649         /* Check whether we wake up from the remote resume.
1650            For lp1 case, pmc is not responsible for waking the
1651            system, it's the flow controller and hence
1652            UTMIP_WALK_PTR_VAL(inst) will return 0.
1653            Also, for lp1 case phy->remote_wakeup will already be set
1654            to true by utmi_phy_irq() when the remote wakeup happens.
1655            Hence change the logic in the else part to enter only
1656            if phy->remote_wakeup is not set to true by the
1657            utmi_phy_irq(). */
1658         if (UTMIP_WALK_PTR_VAL(inst) & val) {
1659                 phy->remote_wakeup = true;
1660         } else if(!phy->remote_wakeup) {
1661                 if (!((UTMIP_USBON_VAL(phy->inst) |
1662                         UTMIP_USBOP_VAL(phy->inst)) & val)) {
1663                                 utmip_phy_disable_pmc_bus_ctrl(phy);
1664                 }
1665         }
1666         utmi_phy_enable_obs_bus(phy);
1667 }
1668
1669 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
1670 {
1671         unsigned long val;
1672         void __iomem *base = phy->regs;
1673         int wait_time_us = 25000; /* FPR should be set by this time */
1674
1675         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1676         /* check whether we wake up from the remote resume */
1677         if (phy->remote_wakeup) {
1678                 /* wait until SUSPEND and RESUME bit is cleared on remote resume */
1679                 do {
1680                         val = readl(base + USB_PORTSC);
1681                         udelay(1);
1682                         if (wait_time_us == 0) {
1683                                 PHY_DBG("%s PMC REMOTE WAKEUP FPR timeout val = 0x%x instance = %d\n", __func__, val, phy->inst);
1684                                 utmip_phy_disable_pmc_bus_ctrl(phy);
1685                                 utmi_phy_post_resume(phy);
1686                                 return;
1687                         }
1688                         wait_time_us--;
1689                 } while (val & (USB_PORTSC_RESUME | USB_PORTSC_SUSP));
1690
1691                 /* wait for 25 ms to port resume complete */
1692                 msleep(25);
1693                 /* disable PMC master control */
1694                 utmip_phy_disable_pmc_bus_ctrl(phy);
1695
1696                 /* Clear PCI and SRI bits to avoid an interrupt upon resume */
1697                 val = readl(base + USB_USBSTS);
1698                 writel(val, base + USB_USBSTS);
1699                 /* wait to avoid SOF if there is any */
1700                 if (usb_phy_reg_status_wait(base + USB_USBSTS,
1701                         USB_USBSTS_SRI, USB_USBSTS_SRI, 2500) < 0) {
1702                         pr_err("%s: timeout waiting for SOF\n", __func__);
1703                 }
1704                 utmi_phy_post_resume(phy);
1705         }
1706 }
1707
1708 static int utmi_phy_resume(struct tegra_usb_phy *phy)
1709 {
1710         int status = 0;
1711         unsigned long val;
1712         void __iomem *base = phy->regs;
1713
1714         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1715         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) {
1716                 if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
1717                         utmi_phy_restore_start(phy);
1718                         usb_phy_bringup_host_controller(phy);
1719                         utmi_phy_restore_end(phy);
1720                 } else {
1721                         /* device is plugged in when system is in LP0 */
1722                         /* bring up the controller from LP0*/
1723                         val = readl(base + USB_USBCMD);
1724                         val |= USB_CMD_RESET;
1725                         writel(val, base + USB_USBCMD);
1726
1727                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1728                                 USB_CMD_RESET, 0, 2500) < 0) {
1729                                 pr_err("%s: timeout waiting for reset\n", __func__);
1730                         }
1731
1732                         val = readl(base + USB_USBMODE);
1733                         val &= ~USB_USBMODE_MASK;
1734                         val |= USB_USBMODE_HOST;
1735                         writel(val, base + USB_USBMODE);
1736
1737                         val = readl(base + HOSTPC1_DEVLC);
1738                         val &= ~HOSTPC1_DEVLC_PTS(~0);
1739                         val |= HOSTPC1_DEVLC_STS;
1740                         writel(val, base + HOSTPC1_DEVLC);
1741
1742                         writel(USB_USBCMD_RS, base + USB_USBCMD);
1743
1744                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1745                                 USB_USBCMD_RS, USB_USBCMD_RS, 2500) < 0) {
1746                                 pr_err("%s: timeout waiting for run bit\n", __func__);
1747                         }
1748
1749                         /* Enable Port Power */
1750                         val = readl(base + USB_PORTSC);
1751                         val |= USB_PORTSC_PP;
1752                         writel(val, base + USB_PORTSC);
1753                         udelay(10);
1754
1755                         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1756                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1757                 }
1758         }
1759
1760         return status;
1761 }
1762
1763 static bool utmi_phy_charger_detect(struct tegra_usb_phy *phy)
1764 {
1765         unsigned long val;
1766         void __iomem *base = phy->regs;
1767         bool status;
1768
1769         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1770         if (phy->pdata->op_mode != TEGRA_USB_OPMODE_DEVICE) {
1771                 /* Charger detection is not there for ULPI
1772                  * return Charger not available */
1773                 return false;
1774         }
1775
1776         /* Enable charger detection logic */
1777         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1778         val |= UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN;
1779         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1780
1781         /* Source should be on for 100 ms as per USB charging spec */
1782         msleep(TDP_SRC_ON_MS);
1783
1784         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1785         /* If charger is not connected disable the interrupt */
1786         val &= ~VDAT_DET_INT_EN;
1787         val |= VDAT_DET_CHG_DET;
1788         writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
1789
1790         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1791         if (val & VDAT_DET_STS)
1792                 status = true;
1793         else
1794                 status = false;
1795
1796         /* Disable charger detection logic */
1797         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1798         val &= ~(UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN);
1799         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1800
1801         /* Delay of 40 ms before we pull the D+ as per battery charger spec */
1802         msleep(TDPSRC_CON_MS);
1803
1804         return status;
1805 }
1806
1807 static void uhsic_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
1808 {
1809         unsigned long val;
1810         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1811
1812         /* turn on pad detectors for HSIC*/
1813         val = readl(pmc_base + PMC_USB_AO);
1814         val &= ~(HSIC_RESERVED_P0 | STROBE_VAL_PD_P0 | DATA_VAL_PD_P0);
1815         writel(val, pmc_base + PMC_USB_AO);
1816
1817         /* Disable PMC master mode by clearing MASTER_EN */
1818         val = readl(pmc_base + PMC_SLEEP_CFG);
1819         val &= ~(UHSIC_MASTER_ENABLE_P0);
1820         writel(val, pmc_base + PMC_SLEEP_CFG);
1821         mdelay(1);
1822 }
1823
1824 static void uhsic_setup_pmc_wake_detect(struct tegra_usb_phy *phy)
1825 {
1826         unsigned long val;
1827         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1828         void __iomem *base = phy->regs;
1829         bool port_connected;
1830
1831         DBG("%s:%d\n", __func__, __LINE__);
1832
1833         /* check for port connect status */
1834         val = readl(base + USB_PORTSC);
1835         port_connected = val & USB_PORTSC_CCS;
1836
1837         if (!port_connected)
1838                 return;
1839
1840         /*Set PMC MASTER bits to do the following
1841         * a. Take over the hsic drivers
1842         * b. set up such that it will take over resume
1843         *        if remote wakeup is detected
1844         * Prepare PMC to take over suspend-wake detect-drive resume until USB
1845         * controller ready
1846         */
1847
1848         /* disable master enable in PMC */
1849         val = readl(pmc_base + PMC_SLEEP_CFG);
1850         val &= ~UHSIC_MASTER_ENABLE_P0;
1851         writel(val, pmc_base + PMC_SLEEP_CFG);
1852
1853         /* UTMIP_PWR_PX=1 for power savings mode */
1854         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
1855         val |= UHSIC_PWR;
1856         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
1857
1858
1859         /* Enable which type of event can trigger a walk,
1860         * in this case usb_line_wake */
1861         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
1862         val |= UHSIC_LINEVAL_WALK_EN;
1863         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
1864
1865         /* program walk sequence, maintain a J, followed by a driven K
1866         * to signal a resume once an wake event is detected */
1867
1868         val = readl(pmc_base + PMC_SLEEPWALK_UHSIC);
1869
1870         val &= ~UHSIC_DATA_RPU_A;
1871         val |=  UHSIC_DATA_RPD_A;
1872         val &= ~UHSIC_STROBE_RPD_A;
1873         val |=  UHSIC_STROBE_RPU_A;
1874         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1875
1876         val &= ~UHSIC_DATA_RPD_B;
1877         val |=  UHSIC_DATA_RPU_B;
1878         val &= ~UHSIC_STROBE_RPU_B;
1879         val |=  UHSIC_STROBE_RPD_B;
1880         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1881
1882         val &= ~UHSIC_DATA_RPD_C;
1883         val |=  UHSIC_DATA_RPU_C;
1884         val &= ~UHSIC_STROBE_RPU_C;
1885         val |=  UHSIC_STROBE_RPD_C;
1886         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1887
1888         val &= ~UHSIC_DATA_RPD_D;
1889         val |=  UHSIC_DATA_RPU_D;
1890         val &= ~UHSIC_STROBE_RPU_D;
1891         val |=  UHSIC_STROBE_RPD_D;
1892         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1893
1894         /* turn on pad detectors */
1895         val = readl(pmc_base + PMC_USB_AO);
1896         val &= ~(STROBE_VAL_PD_P0 | DATA_VAL_PD_P0);
1897         writel(val, pmc_base + PMC_USB_AO);
1898         /* Add small delay before usb detectors provide stable line values */
1899         udelay(1);
1900
1901         phy->remote_wakeup = false;
1902
1903         /* Turn over pad configuration to PMC  for line wake events*/
1904         val = readl(pmc_base + PMC_SLEEP_CFG);
1905         val &= ~UHSIC_WAKE_VAL(~0);
1906         val |= UHSIC_WAKE_VAL(WAKE_VAL_SD10);
1907         val |= UHSIC_MASTER_ENABLE;
1908         writel(val, pmc_base + PMC_SLEEP_CFG);
1909
1910         val = readl(base + UHSIC_PMC_WAKEUP0);
1911         val |= EVENT_INT_ENB;
1912         writel(val, base + UHSIC_PMC_WAKEUP0);
1913
1914         DBG("%s:PMC enabled for HSIC remote wakeup\n", __func__);
1915 }
1916
1917 static void uhsic_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy)
1918 {
1919         unsigned long val;
1920         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1921         void __iomem *base = phy->regs;
1922
1923         DBG("%s (%d)\n", __func__, __LINE__);
1924         val = readl(pmc_base + PMC_SLEEP_CFG);
1925         val &= ~UHSIC_WAKE_VAL(0x0);
1926         val |= UHSIC_WAKE_VAL(WAKE_VAL_NONE);
1927         writel(val, pmc_base + PMC_SLEEP_CFG);
1928
1929         val = readl(pmc_base + PMC_TRIGGERS);
1930         val |= UHSIC_CLR_WAKE_ALARM_P0 | UHSIC_CLR_WALK_PTR_P0;
1931         writel(val, pmc_base + PMC_TRIGGERS);
1932
1933         val = readl(base + UHSIC_PMC_WAKEUP0);
1934         val &= ~EVENT_INT_ENB;
1935         writel(val, base + UHSIC_PMC_WAKEUP0);
1936
1937         /* Disable PMC master mode by clearing MASTER_EN */
1938         val = readl(pmc_base + PMC_SLEEP_CFG);
1939         val &= ~(UHSIC_MASTER_ENABLE);
1940         writel(val, pmc_base + PMC_SLEEP_CFG);
1941
1942         /* turn off pad detectors */
1943         val = readl(pmc_base + PMC_USB_AO);
1944         val |= (STROBE_VAL_PD_P0 | DATA_VAL_PD_P0);
1945         writel(val, pmc_base + PMC_USB_AO);
1946
1947         phy->remote_wakeup = false;
1948 }
1949
1950 static bool uhsic_phy_remotewake_detected(struct tegra_usb_phy *phy)
1951 {
1952         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1953         void __iomem *base = phy->regs;
1954         u32 val;
1955
1956         val = readl(base + UHSIC_PMC_WAKEUP0);
1957         if (val & EVENT_INT_ENB) {
1958                 val = readl(pmc_base + UTMIP_UHSIC_STATUS);
1959                 if (UHSIC_WAKE_ALARM & val) {
1960                         val = readl(pmc_base + PMC_SLEEP_CFG);
1961                         val &= ~UHSIC_WAKE_VAL(0x0);
1962                         val |= UHSIC_WAKE_VAL(WAKE_VAL_NONE);
1963                         writel(val, pmc_base + PMC_SLEEP_CFG);
1964
1965                         val = readl(pmc_base + PMC_TRIGGERS);
1966                         val |= UHSIC_CLR_WAKE_ALARM_P0 | UHSIC_CLR_WALK_PTR_P0;
1967                         writel(val, pmc_base + PMC_TRIGGERS);
1968
1969                         val = readl(base + UHSIC_PMC_WAKEUP0);
1970                         val &= ~EVENT_INT_ENB;
1971                         writel(val, base + UHSIC_PMC_WAKEUP0);
1972                         phy->remote_wakeup = true;
1973                         DBG("%s:PMC remote wakeup detected for HSIC\n", __func__);
1974                         return true;
1975                 }
1976         }
1977         return false;
1978 }
1979
1980 static int uhsic_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1981 {
1982         DBG("%s(%d)\n", __func__, __LINE__);
1983
1984         if (!remote_wakeup)
1985                 usb_phy_wait_for_sof(phy);
1986
1987         return 0;
1988 }
1989
1990 static int uhsic_phy_post_resume(struct tegra_usb_phy *phy)
1991 {
1992         unsigned long val;
1993         void __iomem *base = phy->regs;
1994
1995         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1996         val = readl(base + USB_TXFILLTUNING);
1997         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
1998                 val = USB_FIFO_TXFILL_THRES(0x10);
1999                 writel(val, base + USB_TXFILLTUNING);
2000         }
2001
2002         return 0;
2003 }
2004
2005 static void uhsic_phy_restore_start(struct tegra_usb_phy *phy)
2006 {
2007         unsigned long val;
2008         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
2009         void __iomem *base = phy->regs;
2010
2011         val = readl(pmc_base + UTMIP_UHSIC_STATUS);
2012
2013         /* check whether we wake up from the remote resume */
2014         if (UHSIC_WALK_PTR_VAL & val) {
2015                 phy->remote_wakeup = true;
2016                 pr_info("%s: uhsic remote wakeup detected\n", __func__);
2017         } else {
2018                 if (!((UHSIC_STROBE_VAL_P0 | UHSIC_DATA_VAL_P0) & val)) {
2019                                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2020                 } else {
2021                         DBG("%s(%d): setting pretend connect\n", __func__, __LINE__);
2022                         val = readl(base + UHSIC_CMD_CFG0);
2023                         val |= UHSIC_PRETEND_CONNECT_DETECT;
2024                         writel(val, base + UHSIC_CMD_CFG0);
2025                 }
2026         }
2027 }
2028
2029 static void uhsic_phy_restore_end(struct tegra_usb_phy *phy)
2030 {
2031
2032         unsigned long val;
2033         void __iomem *base = phy->regs;
2034         int wait_time_us = 3000; /* FPR should be set by this time */
2035
2036         DBG("%s(%d)\n", __func__, __LINE__);
2037
2038         /* check whether we wake up from the remote resume */
2039         if (phy->remote_wakeup) {
2040                 /* wait until FPR bit is set automatically on remote resume */
2041                 do {
2042                         val = readl(base + USB_PORTSC);
2043                         udelay(1);
2044                         if (wait_time_us == 0) {
2045                                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2046                                 uhsic_phy_post_resume(phy);
2047                                 return;
2048                         }
2049                         wait_time_us--;
2050                 } while (!(val & USB_PORTSC_RESUME));
2051                 /* wait for 25 ms to port resume complete */
2052                 msleep(25);
2053                 /* disable PMC master control */
2054                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2055
2056                 /* Clear PCI and SRI bits to avoid an interrupt upon resume */
2057                 val = readl(base + USB_USBSTS);
2058                 writel(val, base + USB_USBSTS);
2059                 /* wait to avoid SOF if there is any */
2060                 if (usb_phy_reg_status_wait(base + USB_USBSTS,
2061                         USB_USBSTS_SRI, USB_USBSTS_SRI, 2500)) {
2062                         pr_warn("%s: timeout waiting for SOF\n", __func__);
2063                 }
2064                 uhsic_phy_post_resume(phy);
2065         } else {
2066                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2067         }
2068
2069         /* Set RUN bit */
2070         val = readl(base + USB_USBCMD);
2071         val |= USB_USBCMD_RS;
2072         writel(val, base + USB_USBCMD);
2073         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2074                                                  USB_USBCMD_RS, 2000)) {
2075                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2076                 return;
2077         }
2078 }
2079
2080 static int uhsic_phy_open(struct tegra_usb_phy *phy)
2081 {
2082         unsigned long parent_rate;
2083         int i;
2084
2085         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2086         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
2087         for (i = 0; i < ARRAY_SIZE(uhsic_freq_table); i++) {
2088                 if (uhsic_freq_table[i].freq == parent_rate) {
2089                         phy->freq = &uhsic_freq_table[i];
2090                         break;
2091                 }
2092         }
2093         if (!phy->freq) {
2094                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
2095                 return -EINVAL;
2096         }
2097
2098         uhsic_powerup_pmc_wake_detect(phy);
2099
2100         return 0;
2101 }
2102
2103 static int uhsic_phy_irq(struct tegra_usb_phy *phy)
2104 {
2105         usb_phy_fence_read(phy);
2106         /* check if there is any remote wake event */
2107         if (uhsic_phy_remotewake_detected(phy))
2108                 pr_info("%s: uhsic remote wake detected\n", __func__);
2109         return IRQ_HANDLED;
2110 }
2111
2112 static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
2113 {
2114         unsigned long val;
2115         void __iomem *base = phy->regs;
2116         struct tegra_hsic_config *config = &phy->pdata->u_cfg.hsic;
2117
2118         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2119
2120         if (phy->phy_clk_on) {
2121                 DBG("%s(%d) inst:[%d] phy clk is already On\n",
2122                                         __func__, __LINE__, phy->inst);
2123                 return 0;
2124         }
2125
2126         val = readl(base + UHSIC_PADS_CFG1);
2127         val &= ~(UHSIC_PD_BG | UHSIC_PD_TRK | UHSIC_PD_RX |
2128                         UHSIC_PD_ZI | UHSIC_RPD_DATA | UHSIC_RPD_STROBE);
2129         val |= (UHSIC_RX_SEL | UHSIC_PD_TX);
2130         writel(val, base + UHSIC_PADS_CFG1);
2131
2132         val = readl(base + USB_SUSP_CTRL);
2133         val |= UHSIC_RESET;
2134         writel(val, base + USB_SUSP_CTRL);
2135         udelay(1);
2136
2137         val = readl(base + USB_SUSP_CTRL);
2138         val |= UHSIC_PHY_ENABLE;
2139         writel(val, base + USB_SUSP_CTRL);
2140
2141         val = readl(base + UHSIC_HSRX_CFG0);
2142         val |= UHSIC_IDLE_WAIT(config->idle_wait_delay);
2143         val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(config->elastic_underrun_limit);
2144         val |= UHSIC_ELASTIC_OVERRUN_LIMIT(config->elastic_overrun_limit);
2145         writel(val, base + UHSIC_HSRX_CFG0);
2146
2147         val = readl(base + UHSIC_HSRX_CFG1);
2148         val |= UHSIC_HS_SYNC_START_DLY(config->sync_start_delay);
2149         writel(val, base + UHSIC_HSRX_CFG1);
2150
2151         /* WAR HSIC TX */
2152         val = readl(base + UHSIC_TX_CFG0);
2153         val &= ~UHSIC_HS_READY_WAIT_FOR_VALID;
2154         writel(val, base + UHSIC_TX_CFG0);
2155
2156         val = readl(base + UHSIC_MISC_CFG0);
2157         val |= UHSIC_SUSPEND_EXIT_ON_EDGE;
2158         /* Disable generic bus reset, to allow AP30 specific bus reset*/
2159         val |= UHSIC_DISABLE_BUSRESET;
2160         writel(val, base + UHSIC_MISC_CFG0);
2161
2162         val = readl(base + UHSIC_MISC_CFG1);
2163         val |= UHSIC_PLLU_STABLE_COUNT(phy->freq->stable_count);
2164         writel(val, base + UHSIC_MISC_CFG1);
2165
2166         val = readl(base + UHSIC_PLL_CFG1);
2167         val |= UHSIC_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
2168         val |= UHSIC_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count);
2169         writel(val, base + UHSIC_PLL_CFG1);
2170
2171         val = readl(base + USB_SUSP_CTRL);
2172         val &= ~(UHSIC_RESET);
2173         writel(val, base + USB_SUSP_CTRL);
2174         udelay(1);
2175
2176         val = readl(base + UHSIC_PADS_CFG1);
2177         val &= ~(UHSIC_PD_TX);
2178         writel(val, base + UHSIC_PADS_CFG1);
2179
2180         val = readl(base + USB_USBMODE);
2181         val |= USB_USBMODE_HOST;
2182         writel(val, base + USB_USBMODE);
2183
2184         /* Change the USB controller PHY type to HSIC */
2185         val = readl(base + HOSTPC1_DEVLC);
2186         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
2187         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2188         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
2189         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2190         val &= ~HOSTPC1_DEVLC_STS;
2191         writel(val, base + HOSTPC1_DEVLC);
2192
2193         val = readl(base + USB_TXFILLTUNING);
2194         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
2195                 val = USB_FIFO_TXFILL_THRES(0x10);
2196                 writel(val, base + USB_TXFILLTUNING);
2197         }
2198
2199         val = readl(base + USB_PORTSC);
2200         val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN);
2201         writel(val, base + USB_PORTSC);
2202
2203         val = readl(base + UHSIC_PADS_CFG0);
2204         val &= ~(UHSIC_TX_RTUNEN);
2205         /* set Rtune impedance to 50 ohm */
2206         val |= UHSIC_TX_RTUNE(8);
2207         writel(val, base + UHSIC_PADS_CFG0);
2208
2209         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
2210                                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500)) {
2211                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2212                 return -ETIMEDOUT;
2213         }
2214
2215         phy->phy_clk_on = true;
2216         phy->hw_accessible = true;
2217
2218         if (phy->pmc_sleepwalk) {
2219                 DBG("%s(%d) inst:[%d] restore phy\n", __func__, __LINE__,
2220                                         phy->inst);
2221                 uhsic_phy_restore_start(phy);
2222                 usb_phy_bringup_host_controller(phy);
2223                 uhsic_phy_restore_end(phy);
2224                 phy->pmc_sleepwalk = false;
2225         }
2226
2227         return 0;
2228 }
2229
2230 static int uhsic_phy_power_off(struct tegra_usb_phy *phy)
2231 {
2232         unsigned long val;
2233         void __iomem *base = phy->regs;
2234
2235         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2236         if (!phy->phy_clk_on) {
2237                 DBG("%s(%d) inst:[%d] phy clk is already off\n",
2238                                         __func__, __LINE__, phy->inst);
2239                 return 0;
2240         }
2241
2242         phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
2243                         HOSTPC1_DEVLC_PSPD_MASK;
2244
2245         /* Disable interrupts */
2246         writel(0, base + USB_USBINTR);
2247
2248         if (phy->pmc_sleepwalk == false) {
2249                 uhsic_setup_pmc_wake_detect(phy);
2250                 phy->pmc_sleepwalk = true;
2251         }
2252
2253         val = readl(base + HOSTPC1_DEVLC);
2254         val |= HOSTPC1_DEVLC_PHCD;
2255         writel(val, base + HOSTPC1_DEVLC);
2256
2257         /* Remove power downs for HSIC from PADS CFG1 register */
2258         val = readl(base + UHSIC_PADS_CFG1);
2259         val |= (UHSIC_PD_BG |UHSIC_PD_TRK | UHSIC_PD_RX |
2260                         UHSIC_PD_ZI | UHSIC_PD_TX);
2261         writel(val, base + UHSIC_PADS_CFG1);
2262         phy->phy_clk_on = false;
2263         phy->hw_accessible = false;
2264
2265         return 0;
2266 }
2267
2268 static int uhsic_phy_bus_port_power(struct tegra_usb_phy *phy)
2269 {
2270         unsigned long val;
2271         void __iomem *base = phy->regs;
2272
2273         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2274
2275         val = readl(base + USB_USBMODE);
2276         val |= USB_USBMODE_HOST;
2277         writel(val, base + USB_USBMODE);
2278
2279         /* Change the USB controller PHY type to HSIC */
2280         val = readl(base + HOSTPC1_DEVLC);
2281         val &= ~(HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK));
2282         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2283         val &= ~(HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK));
2284         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2285         writel(val, base + HOSTPC1_DEVLC);
2286
2287         val = readl(base + UHSIC_MISC_CFG0);
2288         val |= UHSIC_DETECT_SHORT_CONNECT;
2289         writel(val, base + UHSIC_MISC_CFG0);
2290         udelay(1);
2291
2292         val = readl(base + UHSIC_MISC_CFG0);
2293         val |= UHSIC_FORCE_XCVR_MODE;
2294         writel(val, base + UHSIC_MISC_CFG0);
2295
2296         val = readl(base + UHSIC_PADS_CFG1);
2297         val &= ~UHSIC_RPD_STROBE;
2298         writel(val, base + UHSIC_PADS_CFG1);
2299
2300         if (phy->pdata->ops && phy->pdata->ops->port_power)
2301                 phy->pdata->ops->port_power();
2302
2303         if (usb_phy_reg_status_wait(base + UHSIC_STAT_CFG0,
2304                         UHSIC_CONNECT_DETECT, UHSIC_CONNECT_DETECT, 25000)) {
2305                 pr_err("%s: timeout waiting for UHSIC_CONNECT_DETECT\n",
2306                                                                 __func__);
2307                 return -ETIMEDOUT;
2308         }
2309
2310         return 0;
2311 }
2312
2313 static int uhsic_phy_bus_reset(struct tegra_usb_phy *phy)
2314 {
2315         unsigned long val;
2316         void __iomem *base = phy->regs;
2317
2318         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2319
2320         /* Change the USB controller PHY type to HSIC */
2321         val = readl(base + HOSTPC1_DEVLC);
2322         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
2323         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2324         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
2325         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2326         val &= ~HOSTPC1_DEVLC_STS;
2327         writel(val, base + HOSTPC1_DEVLC);
2328         /* wait here, otherwise HOSTPC1_DEVLC_PSPD will timeout */
2329         mdelay(5);
2330
2331         val = readl(base + USB_PORTSC);
2332         val |= USB_PORTSC_PTC(5);
2333         writel(val, base + USB_PORTSC);
2334         udelay(2);
2335
2336         val = readl(base + USB_PORTSC);
2337         val &= ~(USB_PORTSC_PTC(~0));
2338         writel(val, base + USB_PORTSC);
2339         udelay(2);
2340
2341         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_LS(0),
2342                                                  0, 2000)) {
2343                 pr_err("%s: timeout waiting for USB_PORTSC_LS\n", __func__);
2344                 return -ETIMEDOUT;
2345         }
2346
2347         /* Poll until CCS is enabled */
2348         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
2349                                                  USB_PORTSC_CCS, 2000)) {
2350                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
2351                 return -ETIMEDOUT;
2352         }
2353
2354         if (usb_phy_reg_status_wait(base + HOSTPC1_DEVLC,
2355                         HOSTPC1_DEVLC_PSPD(2),
2356                         HOSTPC1_DEVLC_PSPD(2), 2000) < 0) {
2357                 pr_err("%s: timeout waiting hsic high speed configuration\n",
2358                                                 __func__);
2359                         return -ETIMEDOUT;
2360         }
2361
2362         val = readl(base + USB_USBCMD);
2363         val &= ~USB_USBCMD_RS;
2364         writel(val, base + USB_USBCMD);
2365
2366         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
2367                                                  USB_USBSTS_HCH, 2000)) {
2368                 pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
2369                 return -ETIMEDOUT;
2370         }
2371
2372         val = readl(base + UHSIC_PADS_CFG1);
2373         val &= ~UHSIC_RPU_STROBE;
2374         val |= UHSIC_RPD_STROBE;
2375         writel(val, base + UHSIC_PADS_CFG1);
2376
2377         mdelay(50);
2378
2379         val = readl(base + UHSIC_PADS_CFG1);
2380         val &= ~UHSIC_RPD_STROBE;
2381         val |= UHSIC_RPU_STROBE;
2382         writel(val, base + UHSIC_PADS_CFG1);
2383
2384         val = readl(base + USB_USBCMD);
2385         val |= USB_USBCMD_RS;
2386         writel(val, base + USB_USBCMD);
2387
2388         val = readl(base + UHSIC_PADS_CFG1);
2389         val &= ~UHSIC_RPU_STROBE;
2390         writel(val, base + UHSIC_PADS_CFG1);
2391
2392         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2393                                                  USB_USBCMD_RS, 2000)) {
2394                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2395                 return -ETIMEDOUT;
2396         }
2397
2398         return 0;
2399 }
2400
2401 int uhsic_phy_resume(struct tegra_usb_phy *phy)
2402 {
2403         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2404
2405         return 0;
2406 }
2407
2408 static void ulpi_set_trimmer(struct tegra_usb_phy *phy)
2409 {
2410         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2411         void __iomem *base = phy->regs;
2412         unsigned long val;
2413
2414         val = ULPI_DATA_TRIMMER_SEL(config->data_trimmer);
2415         val |= ULPI_STPDIRNXT_TRIMMER_SEL(config->stpdirnxt_trimmer);
2416         val |= ULPI_DIR_TRIMMER_SEL(config->dir_trimmer);
2417         writel(val, base + ULPI_TIMING_CTRL_1);
2418         udelay(10);
2419
2420         val |= ULPI_DATA_TRIMMER_LOAD;
2421         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
2422         val |= ULPI_DIR_TRIMMER_LOAD;
2423         writel(val, base + ULPI_TIMING_CTRL_1);
2424 }
2425
2426 static void reset_utmip_uhsic(void __iomem *base)
2427 {
2428         unsigned long val;
2429
2430         val = readl(base + USB_SUSP_CTRL);
2431         val |= UHSIC_RESET;
2432         writel(val, base + USB_SUSP_CTRL);
2433
2434         val = readl(base + USB_SUSP_CTRL);
2435         val |= UTMIP_RESET;
2436         writel(val, base + USB_SUSP_CTRL);
2437 }
2438
2439 static void ulpi_set_host(void __iomem *base)
2440 {
2441         unsigned long val;
2442
2443         val = readl(base + USB_USBMODE);
2444         val &= ~USB_USBMODE_MASK;
2445         val |= USB_USBMODE_HOST;
2446         writel(val, base + USB_USBMODE);
2447
2448         val = readl(base + HOSTPC1_DEVLC);
2449         val |= HOSTPC1_DEVLC_PTS(2);
2450         writel(val, base + HOSTPC1_DEVLC);
2451 }
2452
2453 static inline void ulpi_pinmux_bypass(struct tegra_usb_phy *phy, bool enable)
2454 {
2455         unsigned long val;
2456         void __iomem *base = phy->regs;
2457
2458         val = readl(base + ULPI_TIMING_CTRL_0);
2459
2460         if (enable)
2461                 val |= ULPI_OUTPUT_PINMUX_BYP;
2462         else
2463                 val &= ~ULPI_OUTPUT_PINMUX_BYP;
2464
2465         writel(val, base + ULPI_TIMING_CTRL_0);
2466 }
2467
2468 static inline void ulpi_null_phy_set_tristate(bool enable)
2469 {
2470 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2471         int tristate = (enable) ? TEGRA_TRI_TRISTATE : TEGRA_TRI_NORMAL;
2472
2473         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA0, tristate);
2474         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA1, tristate);
2475         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA2, tristate);
2476         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA3, tristate);
2477         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA4, tristate);
2478         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA5, tristate);
2479         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA6, tristate);
2480         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA7, tristate);
2481         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_NXT, tristate);
2482
2483         if (enable)
2484                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR, tristate);
2485 #endif
2486 }
2487
2488 static void ulpi_null_phy_obs_read(void)
2489 {
2490         static void __iomem *apb_misc;
2491         unsigned slv0_obs, s2s_obs;
2492
2493         if (!apb_misc)
2494                 apb_misc = ioremap(TEGRA_APB_MISC_BASE, TEGRA_APB_MISC_SIZE);
2495
2496         writel(0x80d1003c, apb_misc + APB_MISC_GP_OBSCTRL_0);
2497         slv0_obs = readl(apb_misc + APB_MISC_GP_OBSDATA_0);
2498
2499         writel(0x80d10040, apb_misc + APB_MISC_GP_OBSCTRL_0);
2500         s2s_obs = readl(apb_misc + APB_MISC_GP_OBSDATA_0);
2501
2502         pr_debug("slv0 obs: %08x\ns2s obs: %08x\n", slv0_obs, s2s_obs);
2503 }
2504
2505 static const struct gpio ulpi_gpios[] = {
2506         {ULPI_STP, GPIOF_IN, "ULPI_STP"},
2507         {ULPI_DIR, GPIOF_OUT_INIT_LOW, "ULPI_DIR"},
2508         {ULPI_D0, GPIOF_OUT_INIT_LOW, "ULPI_D0"},
2509         {ULPI_D1, GPIOF_OUT_INIT_LOW, "ULPI_D1"},
2510 };
2511
2512 static int ulpi_null_phy_open(struct tegra_usb_phy *phy)
2513 {
2514         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2515         int ret;
2516
2517         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2518
2519         ret = gpio_request_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
2520         if (ret)
2521                 return ret;
2522
2523         if (gpio_is_valid(config->phy_restore_gpio)) {
2524                 ret = gpio_request(config->phy_restore_gpio, "phy_restore");
2525                 if (ret)
2526                         goto err_gpio_free;
2527
2528                 gpio_direction_input(config->phy_restore_gpio);
2529         }
2530
2531         tegra_periph_reset_assert(phy->ctrlr_clk);
2532         udelay(10);
2533         tegra_periph_reset_deassert(phy->ctrlr_clk);
2534
2535         return 0;
2536
2537 err_gpio_free:
2538         gpio_free_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
2539         return ret;
2540 }
2541
2542 static void ulpi_null_phy_close(struct tegra_usb_phy *phy)
2543 {
2544         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2545
2546         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2547
2548         if (gpio_is_valid(config->phy_restore_gpio))
2549                 gpio_free(config->phy_restore_gpio);
2550
2551         gpio_free_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
2552 }
2553
2554 static int ulpi_null_phy_power_off(struct tegra_usb_phy *phy)
2555 {
2556         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2557
2558         if (!phy->phy_clk_on) {
2559                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
2560                                                         __LINE__, phy->inst);
2561                 return 0;
2562         }
2563
2564         phy->phy_clk_on = false;
2565         phy->hw_accessible = false;
2566         ulpi_null_phy_set_tristate(true);
2567         return 0;
2568 }
2569
2570 /* NOTE: this function must be called before ehci reset */
2571 static int ulpi_null_phy_init(struct tegra_usb_phy *phy)
2572 {
2573         unsigned long val;
2574         void __iomem *base = phy->regs;
2575
2576         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2577         val = readl(base + ULPIS2S_CTRL);
2578         val |=  ULPIS2S_SLV0_CLAMP_XMIT;
2579         writel(val, base + ULPIS2S_CTRL);
2580
2581         val = readl(base + USB_SUSP_CTRL);
2582         val |= ULPIS2S_SLV0_RESET;
2583         writel(val, base + USB_SUSP_CTRL);
2584         udelay(10);
2585
2586         return 0;
2587 }
2588
2589 static int ulpi_null_phy_irq(struct tegra_usb_phy *phy)
2590 {
2591         unsigned long val;
2592         void __iomem *base = phy->regs;
2593
2594         usb_phy_fence_read(phy);
2595         if (phy->bus_reseting){
2596                 val = readl(base + USB_USBCMD);
2597                 val |= USB_USBCMD_RS;
2598                 writel(val, base + USB_USBCMD);
2599                 phy->bus_reseting = false;
2600         }
2601         return IRQ_HANDLED;
2602 }
2603
2604 /* NOTE: this function must be called after ehci reset */
2605 static int ulpi_null_phy_cmd_reset(struct tegra_usb_phy *phy)
2606 {
2607         unsigned long val;
2608         void __iomem *base = phy->regs;
2609
2610         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2611         ulpi_set_host(base);
2612
2613         /* remove slave0 reset */
2614         val = readl(base + USB_SUSP_CTRL);
2615         val &= ~ULPIS2S_SLV0_RESET;
2616         writel(val, base + USB_SUSP_CTRL);
2617
2618         val = readl(base + ULPIS2S_CTRL);
2619         val &=  ~ULPIS2S_SLV0_CLAMP_XMIT;
2620         writel(val, base + ULPIS2S_CTRL);
2621         udelay(10);
2622
2623         return 0;
2624 }
2625
2626 static int ulpi_phy_bus_reset(struct tegra_usb_phy *phy)
2627 {
2628         unsigned long val;
2629         void __iomem *base = phy->regs;
2630
2631         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2632
2633         /*DISABLE RUN BIT */
2634
2635         val = readl(base + USB_USBCMD);
2636         val &= ~USB_USBCMD_RS;
2637         writel(val, base + USB_USBCMD);
2638         phy->bus_reseting = true;
2639
2640         return 0;
2641 }
2642
2643 static int ulpi_null_phy_restore(struct tegra_usb_phy *phy)
2644 {
2645         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2646         unsigned long timeout;
2647         int ulpi_stp = ULPI_STP;
2648
2649         if (gpio_is_valid(config->phy_restore_gpio))
2650                 ulpi_stp = config->phy_restore_gpio;
2651
2652         /* disable ULPI pinmux bypass */
2653         ulpi_pinmux_bypass(phy, false);
2654
2655         /* driving linstate by GPIO */
2656         gpio_set_value(ULPI_D0, 0);
2657         gpio_set_value(ULPI_D1, 0);
2658
2659         /* driving DIR high */
2660         gpio_set_value(ULPI_DIR, 1);
2661
2662         /* remove ULPI tristate */
2663         ulpi_null_phy_set_tristate(false);
2664
2665         /* wait for STP high */
2666         timeout = jiffies + msecs_to_jiffies(25);
2667
2668         while (!gpio_get_value(ulpi_stp)) {
2669                 if (time_after(jiffies, timeout)) {
2670                         pr_warn("phy restore timeout\n");
2671                         return 1;
2672                 }
2673         }
2674
2675         return 0;
2676 }
2677
2678 static int ulpi_null_phy_lp0_resume(struct tegra_usb_phy *phy)
2679 {
2680         unsigned long val;
2681         void __iomem *base = phy->regs;
2682
2683         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2684         ulpi_null_phy_init(phy);
2685
2686         val = readl(base + USB_USBCMD);
2687         val |= USB_CMD_RESET;
2688         writel(val, base + USB_USBCMD);
2689
2690         if (usb_phy_reg_status_wait(base + USB_USBCMD,
2691                 USB_CMD_RESET, 0, 2500) < 0) {
2692                 pr_err("%s: timeout waiting for reset\n", __func__);
2693         }
2694
2695         ulpi_null_phy_cmd_reset(phy);
2696
2697         val = readl(base + USB_USBCMD);
2698         val |= USB_USBCMD_RS;
2699         writel(val, base + USB_USBCMD);
2700         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2701                                                  USB_USBCMD_RS, 2000)) {
2702                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2703                 return -ETIMEDOUT;
2704         }
2705
2706         /* Enable Port Power */
2707         val = readl(base + USB_PORTSC);
2708         val |= USB_PORTSC_PP;
2709         writel(val, base + USB_PORTSC);
2710         udelay(10);
2711
2712         ulpi_null_phy_restore(phy);
2713
2714         return 0;
2715 }
2716
2717 static int ulpi_null_phy_power_on(struct tegra_usb_phy *phy)
2718 {
2719         unsigned long val;
2720         void __iomem *base = phy->regs;
2721         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2722
2723         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2724         if (phy->phy_clk_on) {
2725                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
2726                                                         __LINE__, phy->inst);
2727                 return 0;
2728         }
2729         reset_utmip_uhsic(base);
2730
2731         /* remove ULPI PADS CLKEN reset */
2732         val = readl(base + USB_SUSP_CTRL);
2733         val &= ~ULPI_PADS_CLKEN_RESET;
2734         writel(val, base + USB_SUSP_CTRL);
2735         udelay(10);
2736
2737         val = readl(base + ULPI_TIMING_CTRL_0);
2738         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
2739         writel(val, base + ULPI_TIMING_CTRL_0);
2740
2741         val = readl(base + USB_SUSP_CTRL);
2742         val |= ULPI_PHY_ENABLE;
2743         writel(val, base + USB_SUSP_CTRL);
2744         udelay(10);
2745
2746         /* set timming parameters */
2747         val = readl(base + ULPI_TIMING_CTRL_0);
2748         val |= ULPI_SHADOW_CLK_LOOPBACK_EN;
2749         val &= ~ULPI_SHADOW_CLK_SEL;
2750         val &= ~ULPI_LBK_PAD_EN;
2751         val |= ULPI_SHADOW_CLK_DELAY(config->shadow_clk_delay);
2752         val |= ULPI_CLOCK_OUT_DELAY(config->clock_out_delay);
2753         val |= ULPI_LBK_PAD_E_INPUT_OR;
2754         writel(val, base + ULPI_TIMING_CTRL_0);
2755
2756         writel(0, base + ULPI_TIMING_CTRL_1);
2757         udelay(10);
2758
2759         /* start internal 60MHz clock */
2760         val = readl(base + ULPIS2S_CTRL);
2761         val |= ULPIS2S_ENA;
2762         val |= ULPIS2S_SUPPORT_DISCONNECT;
2763         val |= ULPIS2S_SPARE((phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) ? 3 : 1);
2764         val |= ULPIS2S_PLLU_MASTER_BLASTER60;
2765         writel(val, base + ULPIS2S_CTRL);
2766
2767         /* select ULPI_CORE_CLK_SEL to SHADOW_CLK */
2768         val = readl(base + ULPI_TIMING_CTRL_0);
2769         val |= ULPI_CORE_CLK_SEL;
2770         writel(val, base + ULPI_TIMING_CTRL_0);
2771         udelay(10);
2772
2773         /* enable ULPI null phy clock - can't set the trimmers before this */
2774         val = readl(base + ULPI_TIMING_CTRL_0);
2775         val |= ULPI_CLK_OUT_ENA;
2776         writel(val, base + ULPI_TIMING_CTRL_0);
2777         udelay(10);
2778
2779         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
2780                                                  USB_PHY_CLK_VALID, 2500)) {
2781                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2782                 return -ETIMEDOUT;
2783         }
2784
2785         /* set ULPI trimmers */
2786         ulpi_set_trimmer(phy);
2787
2788         ulpi_set_host(base);
2789
2790         /* remove slave0 reset */
2791         val = readl(base + USB_SUSP_CTRL);
2792         val &= ~ULPIS2S_SLV0_RESET;
2793         writel(val, base + USB_SUSP_CTRL);
2794
2795         /* remove slave1 and line reset */
2796         val = readl(base + USB_SUSP_CTRL);
2797         val &= ~ULPIS2S_SLV1_RESET;
2798         val &= ~ULPIS2S_LINE_RESET;
2799
2800         /* remove ULPI PADS reset */
2801         val &= ~ULPI_PADS_RESET;
2802         writel(val, base + USB_SUSP_CTRL);
2803
2804         if (!phy->ulpi_clk_padout_ena) {
2805                 val = readl(base + ULPI_TIMING_CTRL_0);
2806                 val |= ULPI_CLK_PADOUT_ENA;
2807                 writel(val, base + ULPI_TIMING_CTRL_0);
2808                 phy->ulpi_clk_padout_ena = true;
2809         } else {
2810                 if (!readl(base + USB_ASYNCLISTADDR))
2811                         ulpi_null_phy_lp0_resume(phy);
2812         }
2813         udelay(10);
2814
2815         phy->bus_reseting = false;
2816         phy->phy_clk_on = true;
2817         phy->hw_accessible = true;
2818
2819         return 0;
2820 }
2821
2822 static int ulpi_null_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
2823 {
2824         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2825         ulpi_null_phy_obs_read();
2826         usb_phy_wait_for_sof(phy);
2827         ulpi_null_phy_obs_read();
2828         return 0;
2829 }
2830
2831 static int ulpi_null_phy_post_resume(struct tegra_usb_phy *phy)
2832 {
2833         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2834         ulpi_null_phy_obs_read();
2835         return 0;
2836 }
2837
2838 static int ulpi_null_phy_resume(struct tegra_usb_phy *phy)
2839 {
2840         unsigned long val;
2841         void __iomem *base = phy->regs;
2842
2843         if (!readl(base + USB_ASYNCLISTADDR)) {
2844                 /* enable ULPI CLK output pad */
2845                 val = readl(base + ULPI_TIMING_CTRL_0);
2846                 val |= ULPI_CLK_PADOUT_ENA;
2847                 writel(val, base + ULPI_TIMING_CTRL_0);
2848
2849                 /* enable ULPI pinmux bypass */
2850                 ulpi_pinmux_bypass(phy, true);
2851                 udelay(5);
2852 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2853                 /* remove DIR tristate */
2854                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR,
2855                                           TEGRA_TRI_NORMAL);
2856 #endif
2857         }
2858         return 0;
2859 }
2860
2861
2862
2863 static struct tegra_usb_phy_ops utmi_phy_ops = {
2864         .open           = utmi_phy_open,
2865         .close          = utmi_phy_close,
2866         .irq            = utmi_phy_irq,
2867         .power_on       = utmi_phy_power_on,
2868         .power_off      = utmi_phy_power_off,
2869         .pre_resume = utmi_phy_pre_resume,
2870         .resume = utmi_phy_resume,
2871         .post_resume    = utmi_phy_post_resume,
2872         .charger_detect = utmi_phy_charger_detect,
2873         .post_suspend   = phy_post_suspend,
2874 };
2875
2876 static struct tegra_usb_phy_ops uhsic_phy_ops = {
2877         .open           = uhsic_phy_open,
2878         .irq            = uhsic_phy_irq,
2879         .power_on       = uhsic_phy_power_on,
2880         .power_off      = uhsic_phy_power_off,
2881         .pre_resume = uhsic_phy_pre_resume,
2882         .resume = uhsic_phy_resume,
2883         .post_resume = uhsic_phy_post_resume,
2884         .port_power = uhsic_phy_bus_port_power,
2885         .bus_reset      = uhsic_phy_bus_reset,
2886         .post_suspend   = phy_post_suspend,
2887 };
2888
2889 static struct tegra_usb_phy_ops ulpi_null_phy_ops = {
2890         .open           = ulpi_null_phy_open,
2891         .close          = ulpi_null_phy_close,
2892         .init           = ulpi_null_phy_init,
2893         .irq            = ulpi_null_phy_irq,
2894         .power_on       = ulpi_null_phy_power_on,
2895         .power_off      = ulpi_null_phy_power_off,
2896         .pre_resume = ulpi_null_phy_pre_resume,
2897         .resume = ulpi_null_phy_resume,
2898         .post_resume = ulpi_null_phy_post_resume,
2899         .reset          = ulpi_null_phy_cmd_reset,
2900         .post_suspend   = phy_post_suspend,
2901         .bus_reset      = ulpi_phy_bus_reset,
2902 };
2903
2904 static struct tegra_usb_phy_ops ulpi_link_phy_ops;
2905 static struct tegra_usb_phy_ops icusb_phy_ops;
2906
2907 static struct tegra_usb_phy_ops *phy_ops[] = {
2908         [TEGRA_USB_PHY_INTF_UTMI] = &utmi_phy_ops,
2909         [TEGRA_USB_PHY_INTF_ULPI_LINK] = &ulpi_link_phy_ops,
2910         [TEGRA_USB_PHY_INTF_ULPI_NULL] = &ulpi_null_phy_ops,
2911         [TEGRA_USB_PHY_INTF_HSIC] = &uhsic_phy_ops,
2912         [TEGRA_USB_PHY_INTF_ICUSB] = &icusb_phy_ops,
2913 };
2914
2915 int tegra3_usb_phy_init_ops(struct tegra_usb_phy *phy)
2916 {
2917         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2918
2919         phy->ops = phy_ops[phy->pdata->phy_intf];
2920
2921         /* FIXME: uncommenting below line to make USB host mode fail*/
2922         /* usb_phy_power_down_pmc(); */
2923
2924         return 0;
2925 }