171e2ec91ada4a3d5a7c0585f4d176edd914138e
[linux-2.6.git] / arch / arm / mach-tegra / tegra3_usb_phy.c
1 /*
2  * arch/arm/mach-tegra/tegra3_usb_phy.c
3  *
4  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
5  *
6  *
7  * This software is licensed under the terms of the GNU General Public
8  * License version 2, as published by the Free Software Foundation, and
9  * may be copied, distributed, and modified under those terms.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17 #include <linux/resource.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/slab.h>
21 #include <linux/err.h>
22 #include <linux/platform_device.h>
23 #include <linux/io.h>
24 #include <linux/gpio.h>
25 #include <linux/interrupt.h>
26 #include <linux/clk.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <mach/clk.h>
30 #include <mach/iomap.h>
31 #include <mach/pinmux.h>
32 #include "tegra_usb_phy.h"
33 #include "gpio-names.h"
34 #include "fuse.h"
35
36 #define USB_USBCMD              0x130
37 #define   USB_USBCMD_RS         (1 << 0)
38 #define   USB_CMD_RESET (1<<1)
39
40 #define USB_USBSTS              0x134
41 #define   USB_USBSTS_PCI        (1 << 2)
42 #define   USB_USBSTS_SRI        (1 << 7)
43 #define   USB_USBSTS_HCH        (1 << 12)
44
45 #define USB_USBINTR             0x138
46
47 #define USB_TXFILLTUNING        0x154
48 #define USB_FIFO_TXFILL_THRES(x)   (((x) & 0x1f) << 16)
49 #define USB_FIFO_TXFILL_MASK    0x1f0000
50
51 #define USB_ASYNCLISTADDR       0x148
52
53 #define ICUSB_CTRL              0x15c
54
55 #define USB_PORTSC              0x174
56 #define   USB_PORTSC_WKOC       (1 << 22)
57 #define   USB_PORTSC_WKDS       (1 << 21)
58 #define   USB_PORTSC_WKCN       (1 << 20)
59 #define   USB_PORTSC_PTC(x)     (((x) & 0xf) << 16)
60 #define   USB_PORTSC_PP (1 << 12)
61 #define   USB_PORTSC_LS(x) (((x) & 0x3) << 10)
62 #define   USB_PORTSC_SUSP       (1 << 7)
63 #define   USB_PORTSC_RESUME     (1 << 6)
64 #define   USB_PORTSC_OCC        (1 << 5)
65 #define   USB_PORTSC_PEC        (1 << 3)
66 #define   USB_PORTSC_PE         (1 << 2)
67 #define   USB_PORTSC_CSC        (1 << 1)
68 #define   USB_PORTSC_CCS        (1 << 0)
69 #define   USB_PORTSC_RWC_BITS (USB_PORTSC_CSC | USB_PORTSC_PEC | USB_PORTSC_OCC)
70
71 #define HOSTPC1_DEVLC           0x1b4
72 #define   HOSTPC1_DEVLC_PHCD            (1 << 22)
73 #define   HOSTPC1_DEVLC_PTS(x)          (((x) & 0x7) << 29)
74 #define   HOSTPC1_DEVLC_PTS_MASK        7
75 #define   HOSTPC1_DEVLC_PTS_HSIC        4
76 #define   HOSTPC1_DEVLC_STS             (1 << 28)
77 #define   HOSTPC1_DEVLC_PSPD(x)         (((x) & 0x3) << 25)
78 #define   HOSTPC1_DEVLC_PSPD_MASK       3
79 #define   HOSTPC1_DEVLC_PSPD_HIGH_SPEED 2
80
81 #define USB_USBMODE             0x1f8
82 #define   USB_USBMODE_MASK              (3 << 0)
83 #define   USB_USBMODE_HOST              (3 << 0)
84 #define   USB_USBMODE_DEVICE            (2 << 0)
85
86 #define USB_SUSP_CTRL           0x400
87 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
88 #define   USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
89 #define   USB_SUSP_CLR                  (1 << 5)
90 #define   USB_PHY_CLK_VALID             (1 << 7)
91 #define   USB_PHY_CLK_VALID_INT_ENB     (1 << 9)
92 #define   USB_PHY_CLK_VALID_INT_STS     (1 << 8)
93 #define   UTMIP_RESET                   (1 << 11)
94 #define   UTMIP_PHY_ENABLE              (1 << 12)
95 #define   ULPI_PHY_ENABLE               (1 << 13)
96 #define   UHSIC_RESET                   (1 << 14)
97 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
98 #define   UHSIC_PHY_ENABLE              (1 << 19)
99 #define   ULPIS2S_SLV0_RESET            (1 << 20)
100 #define   ULPIS2S_SLV1_RESET            (1 << 21)
101 #define   ULPIS2S_LINE_RESET            (1 << 22)
102 #define   ULPI_PADS_RESET               (1 << 23)
103 #define   ULPI_PADS_CLKEN_RESET         (1 << 24)
104
105 #define USB_PHY_VBUS_WAKEUP_ID  0x408
106 #define   VDAT_DET_INT_EN       (1 << 16)
107 #define   VDAT_DET_CHG_DET      (1 << 17)
108 #define   VDAT_DET_STS          (1 << 18)
109 #define   USB_ID_STATUS         (1 << 2)
110
111 #define ULPIS2S_CTRL            0x418
112 #define   ULPIS2S_ENA                   (1 << 0)
113 #define   ULPIS2S_SUPPORT_DISCONNECT    (1 << 2)
114 #define   ULPIS2S_PLLU_MASTER_BLASTER60 (1 << 3)
115 #define   ULPIS2S_SPARE(x)              (((x) & 0xF) << 8)
116 #define   ULPIS2S_FORCE_ULPI_CLK_OUT    (1 << 12)
117 #define   ULPIS2S_DISCON_DONT_CHECK_SE0 (1 << 13)
118 #define   ULPIS2S_SUPPORT_HS_KEEP_ALIVE (1 << 14)
119 #define   ULPIS2S_DISABLE_STP_PU        (1 << 15)
120 #define   ULPIS2S_SLV0_CLAMP_XMIT       (1 << 16)
121
122 #define ULPI_TIMING_CTRL_0      0x424
123 #define   ULPI_CLOCK_OUT_DELAY(x)       ((x) & 0x1F)
124 #define   ULPI_OUTPUT_PINMUX_BYP        (1 << 10)
125 #define   ULPI_CLKOUT_PINMUX_BYP        (1 << 11)
126 #define   ULPI_SHADOW_CLK_LOOPBACK_EN   (1 << 12)
127 #define   ULPI_SHADOW_CLK_SEL           (1 << 13)
128 #define   ULPI_CORE_CLK_SEL             (1 << 14)
129 #define   ULPI_SHADOW_CLK_DELAY(x)      (((x) & 0x1F) << 16)
130 #define   ULPI_LBK_PAD_EN               (1 << 26)
131 #define   ULPI_LBK_PAD_E_INPUT_OR       (1 << 27)
132 #define   ULPI_CLK_OUT_ENA              (1 << 28)
133 #define   ULPI_CLK_PADOUT_ENA           (1 << 29)
134
135 #define ULPI_TIMING_CTRL_1      0x428
136 #define   ULPI_DATA_TRIMMER_LOAD        (1 << 0)
137 #define   ULPI_DATA_TRIMMER_SEL(x)      (((x) & 0x7) << 1)
138 #define   ULPI_STPDIRNXT_TRIMMER_LOAD   (1 << 16)
139 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
140 #define   ULPI_DIR_TRIMMER_LOAD         (1 << 24)
141 #define   ULPI_DIR_TRIMMER_SEL(x)       (((x) & 0x7) << 25)
142
143 #define UTMIP_XCVR_CFG0         0x808
144 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
145 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
146 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
147 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
148 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
149 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
150 #define   UTMIP_XCVR_LSBIAS_SEL                 (1 << 21)
151 #define   UTMIP_XCVR_SETUP_MSB(x)               (((x) & 0x7) << 22)
152 #define   UTMIP_XCVR_HSSLEW_MSB(x)              (((x) & 0x7f) << 25)
153 #define   UTMIP_XCVR_MAX_OFFSET         2
154 #define   UTMIP_XCVR_SETUP_MAX_VALUE    0x7f
155 #define   UTMIP_XCVR_SETUP_MIN_VALUE    0
156 #define   XCVR_SETUP_MSB_CALIB(x) ((x) >> 4)
157
158 #define UTMIP_BIAS_CFG0         0x80c
159 #define   UTMIP_OTGPD                   (1 << 11)
160 #define   UTMIP_BIASPD                  (1 << 10)
161 #define   UTMIP_HSSQUELCH_LEVEL(x)      (((x) & 0x3) << 0)
162 #define   UTMIP_HSDISCON_LEVEL(x)       (((x) & 0x3) << 2)
163 #define   UTMIP_HSDISCON_LEVEL_MSB      (1 << 24)
164
165 #define UTMIP_HSRX_CFG0         0x810
166 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
167 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
168
169 #define UTMIP_HSRX_CFG1         0x814
170 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
171
172 #define UTMIP_TX_CFG0           0x820
173 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
174 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
175
176 #define UTMIP_DEBOUNCE_CFG0 0x82c
177 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
178
179 #define UTMIP_BAT_CHRG_CFG0 0x830
180 #define   UTMIP_PD_CHRG                 (1 << 0)
181 #define   UTMIP_ON_SINK_EN              (1 << 2)
182 #define   UTMIP_OP_SRC_EN               (1 << 3)
183
184 #define UTMIP_XCVR_CFG1         0x838
185 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
186 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
187 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
188 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
189
190 #define UTMIP_BIAS_CFG1         0x83c
191 #define   UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
192 #define   UTMIP_BIAS_PDTRK_POWERDOWN    (1 << 0)
193 #define   UTMIP_BIAS_PDTRK_POWERUP      (1 << 1)
194
195 #define UTMIP_MISC_CFG0         0x824
196 #define   UTMIP_DPDM_OBSERVE            (1 << 26)
197 #define   UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
198 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J   UTMIP_DPDM_OBSERVE_SEL(0xf)
199 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K   UTMIP_DPDM_OBSERVE_SEL(0xe)
200 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
201 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
202 #define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
203 #define   FORCE_PULLDN_DM       (1 << 8)
204 #define   FORCE_PULLDN_DP       (1 << 9)
205 #define   COMB_TERMS            (1 << 0)
206 #define   ALWAYS_FREE_RUNNING_TERMS (1 << 1)
207
208 #define UTMIP_SPARE_CFG0        0x834
209 #define   FUSE_SETUP_SEL                (1 << 3)
210 #define   FUSE_ATERM_SEL                (1 << 4)
211
212 #define UTMIP_PMC_WAKEUP0               0x84c
213 #define   EVENT_INT_ENB                 (1 << 0)
214
215 #define UHSIC_PMC_WAKEUP0               0xc34
216
217 #define UTMIP_BIAS_STS0                 0x840
218 #define   UTMIP_RCTRL_VAL(x)            (((x) & 0xffff) << 0)
219 #define   UTMIP_TCTRL_VAL(x)            (((x) & (0xffff << 16)) >> 16)
220
221 #define UHSIC_PLL_CFG1                          0xc04
222 #define   UHSIC_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
223 #define   UHSIC_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 14)
224
225 #define UHSIC_HSRX_CFG0                         0xc08
226 #define   UHSIC_ELASTIC_UNDERRUN_LIMIT(x)       (((x) & 0x1f) << 2)
227 #define   UHSIC_ELASTIC_OVERRUN_LIMIT(x)        (((x) & 0x1f) << 8)
228 #define   UHSIC_IDLE_WAIT(x)                    (((x) & 0x1f) << 13)
229
230 #define UHSIC_HSRX_CFG1                         0xc0c
231 #define   UHSIC_HS_SYNC_START_DLY(x)            (((x) & 0x1f) << 1)
232
233 #define UHSIC_TX_CFG0                           0xc10
234 #define UHSIC_HS_READY_WAIT_FOR_VALID   (1 << 9)
235 #define UHSIC_MISC_CFG0                         0xc14
236 #define   UHSIC_SUSPEND_EXIT_ON_EDGE            (1 << 7)
237 #define   UHSIC_DETECT_SHORT_CONNECT            (1 << 8)
238 #define   UHSIC_FORCE_XCVR_MODE                 (1 << 15)
239 #define   UHSIC_DISABLE_BUSRESET                (1 << 20)
240 #define UHSIC_MISC_CFG1                         0xc18
241 #define   UHSIC_PLLU_STABLE_COUNT(x)            (((x) & 0xfff) << 2)
242
243 #define UHSIC_PADS_CFG0                         0xc1c
244 #define   UHSIC_TX_RTUNEN                       0xf000
245 #define   UHSIC_TX_RTUNE(x)                     (((x) & 0xf) << 12)
246
247 #define UHSIC_PADS_CFG1                         0xc20
248 #define   UHSIC_PD_BG                           (1 << 2)
249 #define   UHSIC_PD_TX                           (1 << 3)
250 #define   UHSIC_PD_TRK                          (1 << 4)
251 #define   UHSIC_PD_RX                           (1 << 5)
252 #define   UHSIC_PD_ZI                           (1 << 6)
253 #define   UHSIC_RX_SEL                          (1 << 7)
254 #define   UHSIC_RPD_DATA                        (1 << 9)
255 #define   UHSIC_RPD_STROBE                      (1 << 10)
256 #define   UHSIC_RPU_DATA                        (1 << 11)
257 #define   UHSIC_RPU_STROBE                      (1 << 12)
258
259 #define UHSIC_CMD_CFG0                  0xc24
260 #define UHSIC_PRETEND_CONNECT_DETECT    (1 << 5)
261
262 #define UHSIC_STAT_CFG0         0xc28
263 #define UHSIC_CONNECT_DETECT            (1 << 0)
264
265 #define PMC_USB_DEBOUNCE                        0xec
266 #define UTMIP_LINE_DEB_CNT(x)           (((x) & 0xf) << 16)
267 #define UHSIC_LINE_DEB_CNT(x)           (((x) & 0xf) << 20)
268
269 #define PMC_USB_AO                              0xf0
270
271 #define PMC_POWER_DOWN_MASK                     0xffff
272 #define HSIC_RESERVED_P0                        (3 << 14)
273 #define STROBE_VAL_PD_P0                        (1 << 12)
274 #define DATA_VAL_PD_P0                          (1 << 13)
275
276 #define USB_ID_PD(inst)                 (1 << ((4*(inst))+3))
277 #define VBUS_WAKEUP_PD(inst)                    (1 << ((4*(inst))+2))
278 #define   USBON_VAL_PD(inst)                    (1 << ((4*(inst))+1))
279 #define   USBON_VAL_PD_P2                       (1 << 9)
280 #define   USBON_VAL_PD_P1                       (1 << 5)
281 #define   USBON_VAL_PD_P0                       (1 << 1)
282 #define   USBOP_VAL_PD(inst)                    (1 << (4*(inst)))
283 #define   USBOP_VAL_PD_P2                       (1 << 8)
284 #define   USBOP_VAL_PD_P1                       (1 << 4)
285 #define   USBOP_VAL_PD_P0                       (1 << 0)
286 #define   PMC_USB_AO_PD_P2                      (0xf << 8)
287 #define   PMC_USB_AO_ID_PD_P0                   (1 << 3)
288 #define   PMC_USB_AO_VBUS_WAKEUP_PD_P0  (1 << 2)
289
290 #define PMC_TRIGGERS                    0x1ec
291
292 #define   UHSIC_CLR_WALK_PTR_P0         (1 << 3)
293 #define   UTMIP_CLR_WALK_PTR(inst)      (1 << (inst))
294 #define   UTMIP_CLR_WALK_PTR_P2         (1 << 2)
295 #define   UTMIP_CLR_WALK_PTR_P1         (1 << 1)
296 #define   UTMIP_CLR_WALK_PTR_P0         (1 << 0)
297 #define   UTMIP_CAP_CFG(inst)   (1 << ((inst)+4))
298 #define   UTMIP_CAP_CFG_P2              (1 << 6)
299 #define   UTMIP_CAP_CFG_P1              (1 << 5)
300 #define   UTMIP_CAP_CFG_P0              (1 << 4)
301 #define   UTMIP_CLR_WAKE_ALARM(inst)    (1 << ((inst)+12))
302 #define   UHSIC_CLR_WAKE_ALARM_P0       (1 << 15)
303 #define   UTMIP_CLR_WAKE_ALARM_P2       (1 << 14)
304
305 #define PMC_PAD_CFG             (0x1f4)
306
307 #define PMC_UTMIP_TERM_PAD_CFG  0x1f8
308 #define   PMC_TCTRL_VAL(x)      (((x) & 0x1f) << 5)
309 #define   PMC_RCTRL_VAL(x)      (((x) & 0x1f) << 0)
310
311 #define PMC_SLEEP_CFG                   0x1fc
312
313 #define   UHSIC_MASTER_ENABLE                   (1 << 24)
314 #define   UHSIC_WAKE_VAL(x)             (((x) & 0xf) << 28)
315 #define   WAKE_VAL_SD10                 0x2
316 #define   UTMIP_TCTRL_USE_PMC(inst) (1 << ((8*(inst))+3))
317 #define   UTMIP_TCTRL_USE_PMC_P2                (1 << 19)
318 #define   UTMIP_TCTRL_USE_PMC_P1                (1 << 11)
319 #define   UTMIP_TCTRL_USE_PMC_P0                (1 << 3)
320 #define   UTMIP_RCTRL_USE_PMC(inst) (1 << ((8*(inst))+2))
321 #define   UTMIP_RCTRL_USE_PMC_P2                (1 << 18)
322 #define   UTMIP_RCTRL_USE_PMC_P1                (1 << 10)
323 #define   UTMIP_RCTRL_USE_PMC_P0                (1 << 2)
324 #define   UTMIP_FSLS_USE_PMC(inst)      (1 << ((8*(inst))+1))
325 #define   UTMIP_FSLS_USE_PMC_P2         (1 << 17)
326 #define   UTMIP_FSLS_USE_PMC_P1         (1 << 9)
327 #define   UTMIP_FSLS_USE_PMC_P0         (1 << 1)
328 #define   UTMIP_MASTER_ENABLE(inst) (1 << (8*(inst)))
329 #define   UTMIP_MASTER_ENABLE_P2                (1 << 16)
330 #define   UTMIP_MASTER_ENABLE_P1                (1 << 8)
331 #define   UTMIP_MASTER_ENABLE_P0                (1 << 0)
332 #define UHSIC_MASTER_ENABLE_P0          (1 << 24)
333 #define UHSIC_WAKE_VAL_P0(x)            (((x) & 0xf) << 28)
334
335 #define PMC_SLEEPWALK_CFG               0x200
336
337 #define   UHSIC_WAKE_WALK_EN_P0 (1 << 30)
338 #define   UHSIC_LINEVAL_WALK_EN (1 << 31)
339 #define   UTMIP_LINEVAL_WALK_EN(inst) (1 << ((8*(inst))+7))
340 #define   UTMIP_LINEVAL_WALK_EN_P2      (1 << 23)
341 #define   UTMIP_LINEVAL_WALK_EN_P1      (1 << 15)
342 #define   UTMIP_LINEVAL_WALK_EN_P0      (1 << 7)
343 #define   UTMIP_WAKE_VAL(inst, x) (((x) & 0xf) << ((8*(inst))+4))
344 #define   UTMIP_WAKE_VAL_P2(x)          (((x) & 0xf) << 20)
345 #define   UTMIP_WAKE_VAL_P1(x)          (((x) & 0xf) << 12)
346 #define   UTMIP_WAKE_VAL_P0(x)          (((x) & 0xf) << 4)
347 #define   WAKE_VAL_NONE         0xc
348 #define   WAKE_VAL_ANY                  0xF
349 #define   WAKE_VAL_FSJ                  0x2
350 #define   WAKE_VAL_FSK                  0x1
351 #define   WAKE_VAL_SE0                  0x0
352
353 #define PMC_SLEEPWALK_REG(inst)         (0x204 + (4*(inst)))
354 #define   UTMIP_USBOP_RPD_A     (1 << 0)
355 #define   UTMIP_USBON_RPD_A     (1 << 1)
356 #define   UTMIP_AP_A                    (1 << 4)
357 #define   UTMIP_AN_A                    (1 << 5)
358 #define   UTMIP_HIGHZ_A         (1 << 6)
359 #define   UTMIP_USBOP_RPD_B     (1 << 8)
360 #define   UTMIP_USBON_RPD_B     (1 << 9)
361 #define   UTMIP_AP_B                    (1 << 12)
362 #define   UTMIP_AN_B                    (1 << 13)
363 #define   UTMIP_HIGHZ_B         (1 << 14)
364 #define   UTMIP_USBOP_RPD_C     (1 << 16)
365 #define   UTMIP_USBON_RPD_C     (1 << 17)
366 #define   UTMIP_AP_C            (1 << 20)
367 #define   UTMIP_AN_C            (1 << 21)
368 #define   UTMIP_HIGHZ_C         (1 << 22)
369 #define   UTMIP_USBOP_RPD_D     (1 << 24)
370 #define   UTMIP_USBON_RPD_D     (1 << 25)
371 #define   UTMIP_AP_D            (1 << 28)
372 #define   UTMIP_AN_D            (1 << 29)
373 #define   UTMIP_HIGHZ_D         (1 << 30)
374
375 #define PMC_SLEEPWALK_UHSIC             0x210
376
377 #define UHSIC_STROBE_RPD_A              (1 << 0)
378 #define UHSIC_DATA_RPD_A                (1 << 1)
379 #define UHSIC_STROBE_RPU_A              (1 << 2)
380 #define UHSIC_DATA_RPU_A                (1 << 3)
381 #define UHSIC_STROBE_RPD_B              (1 << 8)
382 #define UHSIC_DATA_RPD_B                (1 << 9)
383 #define UHSIC_STROBE_RPU_B              (1 << 10)
384 #define UHSIC_DATA_RPU_B                (1 << 11)
385 #define UHSIC_STROBE_RPD_C              (1 << 16)
386 #define UHSIC_DATA_RPD_C                (1 << 17)
387 #define UHSIC_STROBE_RPU_C              (1 << 18)
388 #define UHSIC_DATA_RPU_C                (1 << 19)
389 #define UHSIC_STROBE_RPD_D              (1 << 24)
390 #define UHSIC_DATA_RPD_D                (1 << 25)
391 #define UHSIC_STROBE_RPU_D              (1 << 26)
392 #define UHSIC_DATA_RPU_D                (1 << 27)
393
394 #define UTMIP_UHSIC_STATUS              0x214
395
396 #define UTMIP_USBOP_VAL(inst)           (1 << ((2*(inst)) + 8))
397 #define UTMIP_USBOP_VAL_P2              (1 << 12)
398 #define UTMIP_USBOP_VAL_P1              (1 << 10)
399 #define UTMIP_USBOP_VAL_P0              (1 << 8)
400 #define UTMIP_USBON_VAL(inst)           (1 << ((2*(inst)) + 9))
401 #define UTMIP_USBON_VAL_P2              (1 << 13)
402 #define UTMIP_USBON_VAL_P1              (1 << 11)
403 #define UTMIP_USBON_VAL_P0              (1 << 9)
404 #define UHSIC_WAKE_ALARM                (1 << 19)
405 #define UTMIP_WAKE_ALARM(inst)          (1 << ((inst) + 16))
406 #define UTMIP_WAKE_ALARM_P2             (1 << 18)
407 #define UTMIP_WAKE_ALARM_P1             (1 << 17)
408 #define UTMIP_WAKE_ALARM_P0             (1 << 16)
409 #define UHSIC_DATA_VAL_P0               (1 << 15)
410 #define UHSIC_STROBE_VAL_P0             (1 << 14)
411 #define UTMIP_WALK_PTR_VAL(inst)        (0x3 << ((inst)*2))
412 #define UHSIC_WALK_PTR_VAL              (0x3 << 6)
413 #define UTMIP_WALK_PTR(inst)            (1 << ((inst)*2))
414 #define UTMIP_WALK_PTR_P2               (1 << 4)
415 #define UTMIP_WALK_PTR_P1               (1 << 2)
416 #define UTMIP_WALK_PTR_P0               (1 << 0)
417
418 #define USB1_PREFETCH_ID                           6
419 #define USB2_PREFETCH_ID                           18
420 #define USB3_PREFETCH_ID                           17
421
422 #define PMC_UTMIP_UHSIC_FAKE            0x218
423
424 #define UHSIC_STROBE_VAL                (1 << 12)
425 #define UHSIC_DATA_VAL                  (1 << 13)
426 #define UHSIC_STROBE_ENB                (1 << 14)
427 #define UHSIC_DATA_ENB                  (1 << 15)
428 #define   USBON_VAL(inst)       (1 << ((4*(inst))+1))
429 #define   USBON_VAL_P2                  (1 << 9)
430 #define   USBON_VAL_P1                  (1 << 5)
431 #define   USBON_VAL_P0                  (1 << 1)
432 #define   USBOP_VAL(inst)       (1 << (4*(inst)))
433 #define   USBOP_VAL_P2                  (1 << 8)
434 #define   USBOP_VAL_P1                  (1 << 4)
435 #define   USBOP_VAL_P0                  (1 << 0)
436
437 #define PMC_UTMIP_BIAS_MASTER_CNTRL 0x30c
438 #define   BIAS_MASTER_PROG_VAL          (1 << 1)
439
440 #define PMC_UTMIP_MASTER_CONFIG 0x310
441
442 #define UTMIP_PWR(inst)         (1 << (inst))
443 #define UHSIC_PWR                       (1 << 3)
444
445 #define FUSE_USB_CALIB_0                0x1F0
446 #define   XCVR_SETUP(x) (((x) & 0x7F) << 0)
447 #define   XCVR_SETUP_LSB_MASK   0xF
448 #define   XCVR_SETUP_MSB_MASK   0x70
449 #define   XCVR_SETUP_LSB_MAX_VAL        0xF
450
451 #define APB_MISC_GP_OBSCTRL_0   0x818
452 #define APB_MISC_GP_OBSDATA_0   0x81c
453
454 /* ULPI GPIO */
455 #define ULPI_STP        TEGRA_GPIO_PY3
456 #define ULPI_DIR        TEGRA_GPIO_PY1
457 #define ULPI_D0         TEGRA_GPIO_PO1
458 #define ULPI_D1         TEGRA_GPIO_PO2
459
460 /* These values (in milli second) are taken from the battery charging spec */
461 #define TDP_SRC_ON_MS    100
462 #define TDPSRC_CON_MS    40
463
464 #ifdef DEBUG
465 #define DBG(stuff...)   pr_info("tegra3_usb_phy: " stuff)
466 #else
467 #define DBG(stuff...)   do {} while (0)
468 #endif
469
470 #if 0
471 #define PHY_DBG(stuff...)       pr_info("tegra3_usb_phy: " stuff)
472 #else
473 #define PHY_DBG(stuff...)       do {} while (0)
474 #endif
475
476
477 static u32 utmip_rctrl_val, utmip_tctrl_val;
478 static DEFINE_SPINLOCK(utmip_pad_lock);
479 static int utmip_pad_count;
480
481 static struct tegra_xtal_freq utmip_freq_table[] = {
482         {
483                 .freq = 12000000,
484                 .enable_delay = 0x02,
485                 .stable_count = 0x2F,
486                 .active_delay = 0x04,
487                 .xtal_freq_count = 0x76,
488                 .debounce = 0x7530,
489                 .pdtrk_count = 5,
490         },
491         {
492                 .freq = 13000000,
493                 .enable_delay = 0x02,
494                 .stable_count = 0x33,
495                 .active_delay = 0x05,
496                 .xtal_freq_count = 0x7F,
497                 .debounce = 0x7EF4,
498                 .pdtrk_count = 5,
499         },
500         {
501                 .freq = 19200000,
502                 .enable_delay = 0x03,
503                 .stable_count = 0x4B,
504                 .active_delay = 0x06,
505                 .xtal_freq_count = 0xBB,
506                 .debounce = 0xBB80,
507                 .pdtrk_count = 7,
508         },
509         {
510                 .freq = 26000000,
511                 .enable_delay = 0x04,
512                 .stable_count = 0x66,
513                 .active_delay = 0x09,
514                 .xtal_freq_count = 0xFE,
515                 .debounce = 0xFDE8,
516                 .pdtrk_count = 9,
517         },
518 };
519
520 static struct tegra_xtal_freq uhsic_freq_table[] = {
521         {
522                 .freq = 12000000,
523                 .enable_delay = 0x02,
524                 .stable_count = 0x2F,
525                 .active_delay = 0x0,
526                 .xtal_freq_count = 0x1CA,
527         },
528         {
529                 .freq = 13000000,
530                 .enable_delay = 0x02,
531                 .stable_count = 0x33,
532                 .active_delay = 0x0,
533                 .xtal_freq_count = 0x1F0,
534         },
535         {
536                 .freq = 19200000,
537                 .enable_delay = 0x03,
538                 .stable_count = 0x4B,
539                 .active_delay = 0x0,
540                 .xtal_freq_count = 0x2DD,
541         },
542         {
543                 .freq = 26000000,
544                 .enable_delay = 0x04,
545                 .stable_count = 0x66,
546                 .active_delay = 0x0,
547                 .xtal_freq_count = 0x3E0,
548         },
549 };
550
551 static void usb_phy_fence_read(struct tegra_usb_phy *phy)
552 {
553         /* Fence read for coherency of AHB master intiated writes */
554         if (phy->inst == 0)
555                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB1_PREFETCH_ID));
556         else if (phy->inst == 1)
557                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB2_PREFETCH_ID));
558         else if (phy->inst == 2)
559                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB3_PREFETCH_ID));
560
561         return;
562 }
563
564 static void utmip_setup_pmc_wake_detect(struct tegra_usb_phy *phy)
565 {
566         unsigned long val, pmc_pad_cfg_val;
567         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
568         unsigned  int inst = phy->inst;
569         void __iomem *base = phy->regs;
570         bool port_connected;
571         enum usb_phy_port_speed port_speed;
572
573         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
574
575         /* check for port connect status */
576         val = readl(base + USB_PORTSC);
577         port_connected = val & USB_PORTSC_CCS;
578
579         if (!port_connected)
580                 return;
581
582         port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
583                 HOSTPC1_DEVLC_PSPD_MASK;
584         /*Set PMC MASTER bits to do the following
585         * a. Take over the UTMI drivers
586         * b. set up such that it will take over resume
587         *        if remote wakeup is detected
588         * Prepare PMC to take over suspend-wake detect-drive resume until USB
589         * controller ready
590         */
591
592         /* disable master enable in PMC */
593         val = readl(pmc_base + PMC_SLEEP_CFG);
594         val &= ~UTMIP_MASTER_ENABLE(inst);
595         writel(val, pmc_base + PMC_SLEEP_CFG);
596
597         /* UTMIP_PWR_PX=1 for power savings mode */
598         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
599         val |= UTMIP_PWR(inst);
600         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
601
602         /* config debouncer */
603         val = readl(pmc_base + PMC_USB_DEBOUNCE);
604         val &= ~UTMIP_LINE_DEB_CNT(~0);
605         val |= UTMIP_LINE_DEB_CNT(4);
606         writel(val, pmc_base + PMC_USB_DEBOUNCE);
607
608         /* Make sure nothing is happening on the line with respect to PMC */
609         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
610         val &= ~USBOP_VAL(inst);
611         val &= ~USBON_VAL(inst);
612         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
613
614         /* Make sure wake value for line is none */
615         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
616         val &= ~UTMIP_LINEVAL_WALK_EN(inst);
617         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
618         val = readl(pmc_base + PMC_SLEEP_CFG);
619         val &= ~UTMIP_WAKE_VAL(inst, ~0);
620         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
621         writel(val, pmc_base + PMC_SLEEP_CFG);
622
623         /* turn off pad detectors */
624         val = readl(pmc_base + PMC_USB_AO);
625         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
626         writel(val, pmc_base + PMC_USB_AO);
627
628         /* Remove fake values and make synchronizers work a bit */
629         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
630         val &= ~USBOP_VAL(inst);
631         val &= ~USBON_VAL(inst);
632         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
633
634         /* Enable which type of event can trigger a walk,
635         in this case usb_line_wake */
636         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
637         val |= UTMIP_LINEVAL_WALK_EN(inst);
638         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
639
640         /* Enable which type of event can trigger a walk,
641         * in this case usb_line_wake */
642         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
643         val |= UTMIP_LINEVAL_WALK_EN(inst);
644         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
645
646         /* Capture FS/LS pad configurations */
647         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
648         val = readl(pmc_base + PMC_TRIGGERS);
649         val |= UTMIP_CAP_CFG(inst);
650         writel(val, pmc_base + PMC_TRIGGERS);
651         udelay(1);
652         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
653
654         /* BIAS MASTER_ENABLE=0 */
655         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
656         val &= ~BIAS_MASTER_PROG_VAL;
657         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
658
659         /* program walk sequence, maintain a J, followed by a driven K
660         * to signal a resume once an wake event is detected */
661         val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
662         val &= ~UTMIP_AP_A;
663         val |= UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_AN_A |UTMIP_HIGHZ_A |
664                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_AP_B | UTMIP_AN_B |
665                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_AP_C | UTMIP_AN_C |
666                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_AP_D | UTMIP_AN_D;
667         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
668
669         if (port_speed == USB_PHY_PORT_SPEED_LOW) {
670                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
671                 val &= ~(UTMIP_AN_B | UTMIP_HIGHZ_B | UTMIP_AN_C |
672                         UTMIP_HIGHZ_C | UTMIP_AN_D | UTMIP_HIGHZ_D);
673                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
674         } else {
675                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
676                 val &= ~(UTMIP_AP_B | UTMIP_HIGHZ_B | UTMIP_AP_C |
677                         UTMIP_HIGHZ_C | UTMIP_AP_D | UTMIP_HIGHZ_D);
678                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
679         }
680
681         /* turn on pad detectors */
682         val = readl(pmc_base + PMC_USB_AO);
683         val &= ~(USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
684         writel(val, pmc_base + PMC_USB_AO);
685
686         /* Add small delay before usb detectors provide stable line values */
687         mdelay(1);
688
689         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
690         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
691         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
692         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
693
694         phy->remote_wakeup = false;
695
696         /* Turn over pad configuration to PMC  for line wake events*/
697         val = readl(pmc_base + PMC_SLEEP_CFG);
698         val &= ~UTMIP_WAKE_VAL(inst, ~0);
699         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_ANY);
700         val |= UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst);
701         val |= UTMIP_MASTER_ENABLE(inst) | UTMIP_FSLS_USE_PMC(inst);
702         writel(val, pmc_base + PMC_SLEEP_CFG);
703
704         val = readl(base + UTMIP_PMC_WAKEUP0);
705         val |= EVENT_INT_ENB;
706         writel(val, base + UTMIP_PMC_WAKEUP0);
707         PHY_DBG("%s ENABLE_PMC inst = %d\n", __func__, inst);
708 }
709
710 static void utmip_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy)
711 {
712         unsigned long val;
713         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
714         unsigned  int inst = phy->inst;
715         void __iomem *base = phy->regs;
716
717         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
718
719         val = readl(pmc_base + PMC_SLEEP_CFG);
720         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
721         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
722         writel(val, pmc_base + PMC_SLEEP_CFG);
723
724         val = readl(base + UTMIP_PMC_WAKEUP0);
725         val &= ~EVENT_INT_ENB;
726         writel(val, base + UTMIP_PMC_WAKEUP0);
727
728         /* Disable PMC master mode by clearing MASTER_EN */
729         val = readl(pmc_base + PMC_SLEEP_CFG);
730         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
731                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
732         writel(val, pmc_base + PMC_SLEEP_CFG);
733
734         val = readl(pmc_base + PMC_TRIGGERS);
735         val &= ~UTMIP_CAP_CFG(inst);
736         writel(val, pmc_base + PMC_TRIGGERS);
737
738         /* turn off pad detectors */
739         val = readl(pmc_base + PMC_USB_AO);
740         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
741         writel(val, pmc_base + PMC_USB_AO);
742
743         val = readl(pmc_base + PMC_TRIGGERS);
744         val |= UTMIP_CLR_WALK_PTR(inst);
745         writel(val, pmc_base + PMC_TRIGGERS);
746
747         phy->remote_wakeup = false;
748         PHY_DBG("%s DISABLE_PMC inst = %d\n", __func__, inst);
749 }
750
751 bool utmi_phy_remotewake_detected(struct tegra_usb_phy *phy)
752 {
753         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
754         void __iomem *base = phy->regs;
755         unsigned  int inst = phy->inst;
756         u32 val;
757
758         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
759         val = readl(base + UTMIP_PMC_WAKEUP0);
760         if (val & EVENT_INT_ENB) {
761                 val = readl(pmc_base + UTMIP_UHSIC_STATUS);
762                 if (UTMIP_WAKE_ALARM(inst) & val) {
763                         val = readl(pmc_base + PMC_SLEEP_CFG);
764                         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
765                         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
766                         writel(val, pmc_base + PMC_SLEEP_CFG);
767
768                         val = readl(pmc_base + PMC_TRIGGERS);
769                         val |= UTMIP_CLR_WAKE_ALARM(inst);
770                         writel(val, pmc_base + PMC_TRIGGERS);
771
772                         val = readl(base + UTMIP_PMC_WAKEUP0);
773                         val &= ~EVENT_INT_ENB;
774                         writel(val, base + UTMIP_PMC_WAKEUP0);
775                         phy->remote_wakeup = true;
776                         return true;
777                 }
778         }
779         return false;
780 }
781
782 static void utmi_phy_enable_trking_data(struct tegra_usb_phy *phy)
783 {
784         void __iomem *base = IO_ADDRESS(TEGRA_USB_BASE);
785         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
786         static bool init_done = false;
787         u32 val;
788
789         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
790
791         /* Should be done only once after system boot */
792         if (init_done)
793                 return;
794
795         clk_enable(phy->utmi_pad_clk);
796         /* Bias pad MASTER_ENABLE=1 */
797         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
798         val |= BIAS_MASTER_PROG_VAL;
799         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
800
801         /* Setting the tracking length time */
802         val = readl(base + UTMIP_BIAS_CFG1);
803         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
804         val |= UTMIP_BIAS_PDTRK_COUNT(5);
805         writel(val, base + UTMIP_BIAS_CFG1);
806
807         /* Bias PDTRK is Shared and MUST be done from USB1 ONLY, PD_TRK=0 */
808         val = readl(base + UTMIP_BIAS_CFG1);
809         val &= ~UTMIP_BIAS_PDTRK_POWERDOWN;
810         writel(val, base + UTMIP_BIAS_CFG1);
811
812         val = readl(base + UTMIP_BIAS_CFG1);
813         val |= UTMIP_BIAS_PDTRK_POWERUP;
814         writel(val, base + UTMIP_BIAS_CFG1);
815
816         /* Wait for 25usec */
817         udelay(25);
818
819         /* Bias pad MASTER_ENABLE=0 */
820         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
821         val &= ~BIAS_MASTER_PROG_VAL;
822         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
823
824         /* Wait for 1usec */
825         udelay(1);
826
827         /* Bias pad MASTER_ENABLE=1 */
828         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
829         val |= BIAS_MASTER_PROG_VAL;
830         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
831
832         /* Read RCTRL and TCTRL from UTMIP space */
833         val = readl(base + UTMIP_BIAS_STS0);
834         utmip_rctrl_val = ffz(UTMIP_RCTRL_VAL(val));
835         utmip_tctrl_val = ffz(UTMIP_TCTRL_VAL(val));
836
837         /* PD_TRK=1 */
838         val = readl(base + UTMIP_BIAS_CFG1);
839         val |= UTMIP_BIAS_PDTRK_POWERDOWN;
840         writel(val, base + UTMIP_BIAS_CFG1);
841
842         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
843         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
844         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
845         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
846         clk_disable(phy->utmi_pad_clk);
847         init_done = true;
848 }
849
850 static void utmip_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy)
851 {
852         unsigned long val;
853         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
854         unsigned  int inst = phy->inst;
855
856         /* power down UTMIP interfaces */
857         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
858         val |= UTMIP_PWR(inst);
859         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
860
861         /* setup sleep walk usb controller */
862         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
863                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
864                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
865                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
866         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
867
868         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
869         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
870         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
871         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
872
873         /* Turn over pad configuration to PMC */
874         val = readl(pmc_base + PMC_SLEEP_CFG);
875         val &= ~UTMIP_WAKE_VAL(inst, ~0);
876         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE) |
877                 UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
878                 UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst);
879         writel(val, pmc_base + PMC_SLEEP_CFG);
880         PHY_DBG("%s ENABLE_PMC inst = %d\n", __func__, inst);
881 }
882
883 static void utmip_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
884 {
885         unsigned long val;
886         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
887         unsigned  int inst = phy->inst;
888
889         /* Disable PMC master mode by clearing MASTER_EN */
890         val = readl(pmc_base + PMC_SLEEP_CFG);
891         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
892                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
893         writel(val, pmc_base + PMC_SLEEP_CFG);
894         mdelay(1);
895         PHY_DBG("%s DISABLE_PMC inst = %d\n", __func__, inst);
896 }
897
898
899 #ifdef KERNEL_WARNING
900 static void usb_phy_power_down_pmc(void)
901 {
902         unsigned long val;
903         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
904
905         /* power down all 3 UTMIP interfaces */
906         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
907         val |= UTMIP_PWR(0) | UTMIP_PWR(1) | UTMIP_PWR(2);
908         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
909
910         /* turn on pad detectors */
911         writel(PMC_POWER_DOWN_MASK, pmc_base + PMC_USB_AO);
912
913         /* setup sleep walk fl all 3 usb controllers */
914         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
915                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
916                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
917                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
918         writel(val, pmc_base + PMC_SLEEPWALK_REG(0));
919         writel(val, pmc_base + PMC_SLEEPWALK_REG(1));
920         writel(val, pmc_base + PMC_SLEEPWALK_REG(2));
921
922         /* enable pull downs on HSIC PMC */
923         val = UHSIC_STROBE_RPD_A | UHSIC_DATA_RPD_A | UHSIC_STROBE_RPD_B |
924                 UHSIC_DATA_RPD_B | UHSIC_STROBE_RPD_C | UHSIC_DATA_RPD_C |
925                 UHSIC_STROBE_RPD_D | UHSIC_DATA_RPD_D;
926         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
927
928         /* Turn over pad configuration to PMC */
929         val = readl(pmc_base + PMC_SLEEP_CFG);
930         val &= ~UTMIP_WAKE_VAL(0, ~0);
931         val &= ~UTMIP_WAKE_VAL(1, ~0);
932         val &= ~UTMIP_WAKE_VAL(2, ~0);
933         val &= ~UHSIC_WAKE_VAL_P0(~0);
934         val |= UTMIP_WAKE_VAL(0, WAKE_VAL_NONE) | UHSIC_WAKE_VAL_P0(WAKE_VAL_NONE) |
935         UTMIP_WAKE_VAL(1, WAKE_VAL_NONE) | UTMIP_WAKE_VAL(2, WAKE_VAL_NONE) |
936         UTMIP_RCTRL_USE_PMC(0) | UTMIP_RCTRL_USE_PMC(1) | UTMIP_RCTRL_USE_PMC(2) |
937         UTMIP_TCTRL_USE_PMC(0) | UTMIP_TCTRL_USE_PMC(1) | UTMIP_TCTRL_USE_PMC(2) |
938         UTMIP_FSLS_USE_PMC(0) | UTMIP_FSLS_USE_PMC(1) | UTMIP_FSLS_USE_PMC(2) |
939         UTMIP_MASTER_ENABLE(0) | UTMIP_MASTER_ENABLE(1) | UTMIP_MASTER_ENABLE(2) |
940         UHSIC_MASTER_ENABLE_P0;
941         writel(val, pmc_base + PMC_SLEEP_CFG);
942 }
943 #endif
944
945 static int usb_phy_bringup_host_controller(struct tegra_usb_phy *phy)
946 {
947         unsigned long val;
948         void __iomem *base = phy->regs;
949
950         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
951         PHY_DBG("[%d] USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n", __LINE__,
952                 readl(base + USB_USBSTS), readl(base + USB_PORTSC),
953                                                         phy->port_speed);
954
955         /* Device is plugged in when system is in LP0 */
956         /* Bring up the controller from LP0*/
957         val = readl(base + USB_USBCMD);
958         val |= USB_CMD_RESET;
959         writel(val, base + USB_USBCMD);
960
961         if (usb_phy_reg_status_wait(base + USB_USBCMD,
962                 USB_CMD_RESET, 0, 2500) < 0) {
963                 pr_err("%s: timeout waiting for reset\n", __func__);
964         }
965
966         val = readl(base + USB_USBMODE);
967         val &= ~USB_USBMODE_MASK;
968         val |= USB_USBMODE_HOST;
969         writel(val, base + USB_USBMODE);
970         val = readl(base + HOSTPC1_DEVLC);
971         val &= ~HOSTPC1_DEVLC_PTS(~0);
972
973         if (phy->pdata->phy_intf == TEGRA_USB_PHY_INTF_HSIC)
974                 val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
975         else
976                 val |= HOSTPC1_DEVLC_STS;
977         writel(val, base + HOSTPC1_DEVLC);
978
979         /* Enable Port Power */
980         val = readl(base + USB_PORTSC);
981         val |= USB_PORTSC_PP;
982         writel(val, base + USB_PORTSC);
983         udelay(10);
984
985         /* Check if the phy resume from LP0. When the phy resume from LP0
986          * USB register will be reset.to zero */
987         if (!readl(base + USB_ASYNCLISTADDR)) {
988                 /* Program the field PTC based on the saved speed mode */
989                 val = readl(base + USB_PORTSC);
990                 val &= ~USB_PORTSC_PTC(~0);
991                 if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH)
992                         val |= USB_PORTSC_PTC(5);
993                 else if (phy->port_speed == USB_PHY_PORT_SPEED_FULL)
994                         val |= USB_PORTSC_PTC(6);
995                 else if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
996                         val |= USB_PORTSC_PTC(7);
997                 writel(val, base + USB_PORTSC);
998                 udelay(10);
999
1000                 /* Disable test mode by setting PTC field to NORMAL_OP */
1001                 val = readl(base + USB_PORTSC);
1002                 val &= ~USB_PORTSC_PTC(~0);
1003                 writel(val, base + USB_PORTSC);
1004                 udelay(10);
1005         }
1006
1007         /* Poll until CCS is enabled */
1008         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
1009                                                  USB_PORTSC_CCS, 2000)) {
1010                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
1011         }
1012
1013         /* Poll until PE is enabled */
1014         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_PE,
1015                                                  USB_PORTSC_PE, 2000)) {
1016                 pr_err("%s: timeout waiting for USB_PORTSC_PE\n", __func__);
1017         }
1018
1019         /* Clear the PCI status, to avoid an interrupt taken upon resume */
1020         val = readl(base + USB_USBSTS);
1021         val |= USB_USBSTS_PCI;
1022         writel(val, base + USB_USBSTS);
1023
1024         if (!phy->remote_wakeup) {
1025                 /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
1026                 val = readl(base + USB_PORTSC);
1027                 if ((val & USB_PORTSC_PP) && (val & USB_PORTSC_PE)) {
1028                         val |= USB_PORTSC_SUSP;
1029                         writel(val, base + USB_PORTSC);
1030                         /* Need a 4ms delay before the controller goes to suspend */
1031                         mdelay(4);
1032
1033                         /* Wait until port suspend completes */
1034                         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_SUSP,
1035                                                          USB_PORTSC_SUSP, 1000)) {
1036                                 pr_err("%s: timeout waiting for PORT_SUSPEND\n",
1037                                                                         __func__);
1038                         }
1039                 }
1040         }
1041         PHY_DBG("[%d] USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n", __LINE__,
1042                 readl(base + USB_USBSTS), readl(base + USB_PORTSC),
1043                                                         phy->port_speed);
1044
1045         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1046                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1047         return 0;
1048 }
1049
1050 static void usb_phy_wait_for_sof(struct tegra_usb_phy *phy)
1051 {
1052         unsigned long val;
1053         void __iomem *base = phy->regs;
1054
1055         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1056
1057         val = readl(base + USB_USBSTS);
1058         writel(val, base + USB_USBSTS);
1059         udelay(20);
1060         /* wait for two SOFs */
1061         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1062                 USB_USBSTS_SRI, 2500))
1063                 pr_err("%s: timeout waiting for SOF\n", __func__);
1064
1065         val = readl(base + USB_USBSTS);
1066         writel(val, base + USB_USBSTS);
1067         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI, 0, 2500))
1068                 pr_err("%s: timeout waiting for SOF\n", __func__);
1069
1070         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1071                         USB_USBSTS_SRI, 2500))
1072                 pr_err("%s: timeout waiting for SOF\n", __func__);
1073
1074         udelay(20);
1075 }
1076
1077 static unsigned int utmi_phy_xcvr_setup_value(struct tegra_usb_phy *phy)
1078 {
1079         struct tegra_utmi_config *cfg = &phy->pdata->u_cfg.utmi;
1080         signed long val;
1081
1082         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1083
1084         if (cfg->xcvr_use_fuses) {
1085                 val = XCVR_SETUP(tegra_fuse_readl(FUSE_USB_CALIB_0));
1086                 if (cfg->xcvr_use_lsb) {
1087                         val = min((unsigned int) ((val & XCVR_SETUP_LSB_MASK)
1088                                 + cfg->xcvr_setup_offset),
1089                                 (unsigned int) XCVR_SETUP_LSB_MAX_VAL);
1090                         val |= (cfg->xcvr_setup & XCVR_SETUP_MSB_MASK);
1091                 } else {
1092                         if (cfg->xcvr_setup_offset <= UTMIP_XCVR_MAX_OFFSET)
1093                                 val = val + cfg->xcvr_setup_offset;
1094
1095                         if (val > UTMIP_XCVR_SETUP_MAX_VALUE) {
1096                                 val = UTMIP_XCVR_SETUP_MAX_VALUE;
1097                                 pr_info("%s: reset XCVR_SETUP to max value\n",
1098                                                 __func__);
1099                         } else if (val < UTMIP_XCVR_SETUP_MIN_VALUE) {
1100                                 val = UTMIP_XCVR_SETUP_MIN_VALUE;
1101                                 pr_info("%s: reset XCVR_SETUP to min value\n",
1102                                                 __func__);
1103                         }
1104                 }
1105         } else {
1106                 val = cfg->xcvr_setup;
1107         }
1108
1109         return (unsigned int) val;
1110 }
1111
1112 static int utmi_phy_open(struct tegra_usb_phy *phy)
1113 {
1114         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1115         unsigned long parent_rate, val;
1116         int i;
1117
1118         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1119
1120         phy->utmi_pad_clk = clk_get_sys("utmip-pad", NULL);
1121         if (IS_ERR(phy->utmi_pad_clk)) {
1122                 pr_err("%s: can't get utmip pad clock\n", __func__);
1123                 return PTR_ERR(phy->utmi_pad_clk);
1124         }
1125
1126         phy->utmi_xcvr_setup = utmi_phy_xcvr_setup_value(phy);
1127
1128         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
1129         for (i = 0; i < ARRAY_SIZE(utmip_freq_table); i++) {
1130                 if (utmip_freq_table[i].freq == parent_rate) {
1131                         phy->freq = &utmip_freq_table[i];
1132                         break;
1133                 }
1134         }
1135         if (!phy->freq) {
1136                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
1137                 return -EINVAL;
1138         }
1139
1140         /* Power-up the VBUS detector for UTMIP PHY */
1141         val = readl(pmc_base + PMC_USB_AO);
1142         val &= ~(PMC_USB_AO_VBUS_WAKEUP_PD_P0 | PMC_USB_AO_ID_PD_P0);
1143         writel((val | PMC_USB_AO_PD_P2), (pmc_base + PMC_USB_AO));
1144
1145         utmip_powerup_pmc_wake_detect(phy);
1146
1147         return 0;
1148 }
1149
1150 static void utmi_phy_close(struct tegra_usb_phy *phy)
1151 {
1152         unsigned long val;
1153         void __iomem *base = phy->regs;
1154
1155         DBG("%s inst:[%d]\n", __func__, phy->inst);
1156
1157         /* Disable PHY clock valid interrupts while going into suspend*/
1158         if (phy->pdata->u_data.host.hot_plug) {
1159                 val = readl(base + USB_SUSP_CTRL);
1160                 val &= ~USB_PHY_CLK_VALID_INT_ENB;
1161                 writel(val, base + USB_SUSP_CTRL);
1162         }
1163
1164         clk_put(phy->utmi_pad_clk);
1165 }
1166
1167 static int utmi_phy_pad_power_on(struct tegra_usb_phy *phy)
1168 {
1169         unsigned long val, flags;
1170         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1171
1172         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1173
1174         clk_enable(phy->utmi_pad_clk);
1175
1176         spin_lock_irqsave(&utmip_pad_lock, flags);
1177         utmip_pad_count++;
1178
1179         val = readl(pad_base + UTMIP_BIAS_CFG0);
1180         val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
1181         val |= UTMIP_HSSQUELCH_LEVEL(0x2) | UTMIP_HSDISCON_LEVEL(0x1) |
1182                 UTMIP_HSDISCON_LEVEL_MSB;
1183         writel(val, pad_base + UTMIP_BIAS_CFG0);
1184
1185         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1186
1187         clk_disable(phy->utmi_pad_clk);
1188
1189         return 0;
1190 }
1191
1192 static int utmi_phy_pad_power_off(struct tegra_usb_phy *phy)
1193 {
1194         unsigned long val, flags;
1195         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1196
1197         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1198
1199         clk_enable(phy->utmi_pad_clk);
1200         spin_lock_irqsave(&utmip_pad_lock, flags);
1201
1202         if (!utmip_pad_count) {
1203                 pr_err("%s: utmip pad already powered off\n", __func__);
1204                 goto out;
1205         }
1206         if (--utmip_pad_count == 0) {
1207                 val = readl(pad_base + UTMIP_BIAS_CFG0);
1208                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
1209                 val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) | UTMIP_HSDISCON_LEVEL(~0) |
1210                         UTMIP_HSDISCON_LEVEL_MSB);
1211                 writel(val, pad_base + UTMIP_BIAS_CFG0);
1212         }
1213 out:
1214         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1215         clk_disable(phy->utmi_pad_clk);
1216
1217         return 0;
1218 }
1219
1220 static int utmi_phy_irq(struct tegra_usb_phy *phy)
1221 {
1222         void __iomem *base = phy->regs;
1223         unsigned long val = 0;
1224
1225         if (phy->phy_clk_on) {
1226                 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1227                 DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1228                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1229                 DBG("USB_USBMODE[0x%x] USB_USBCMD[0x%x]\n",
1230                         readl(base + USB_USBMODE), readl(base + USB_USBCMD));
1231         }
1232
1233         usb_phy_fence_read(phy);
1234         /* check if there is any remote wake event */
1235         if (utmi_phy_remotewake_detected(phy))
1236                 pr_info("%s: utmip remote wake detected\n", __func__);
1237
1238         if (phy->pdata->u_data.host.hot_plug) {
1239                 val = readl(base + USB_SUSP_CTRL);
1240                 if ((val  & USB_PHY_CLK_VALID_INT_STS)) {
1241                         val &= ~USB_PHY_CLK_VALID_INT_ENB |
1242                                         USB_PHY_CLK_VALID_INT_STS;
1243                         writel(val , (base + USB_SUSP_CTRL));
1244                         pr_info("%s: usb device plugged-in\n", __func__);
1245                         val = readl(base + USB_USBSTS);
1246                         if (!(val  & USB_USBSTS_PCI))
1247                                 return IRQ_NONE;
1248                         val = readl(base + USB_PORTSC);
1249                         val &= ~(USB_PORTSC_WKCN | USB_PORTSC_RWC_BITS);
1250                         writel(val , (base + USB_PORTSC));
1251                 } else if (!phy->phy_clk_on) {
1252                         return IRQ_NONE;
1253                 }
1254         }
1255
1256         return IRQ_HANDLED;
1257 }
1258
1259 static void utmi_phy_enable_obs_bus(struct tegra_usb_phy *phy)
1260 {
1261         unsigned long val;
1262         void __iomem *base = phy->regs;
1263
1264         /* (2LS WAR)is not required for LS and FS devices and is only for HS */
1265         if ((phy->port_speed == USB_PHY_PORT_SPEED_LOW) ||
1266                 (phy->port_speed == USB_PHY_PORT_SPEED_FULL)) {
1267                 /* do not enable the OBS bus */
1268                 val = readl(base + UTMIP_MISC_CFG0);
1269                 val &= ~(UTMIP_DPDM_OBSERVE_SEL(~0));
1270                 writel(val, base + UTMIP_MISC_CFG0);
1271                 DBG("%s(%d) Disable OBS bus\n", __func__, __LINE__);
1272                 return;
1273         }
1274         /* Force DP/DM pulldown active for Host mode */
1275         val = readl(base + UTMIP_MISC_CFG0);
1276         val |= FORCE_PULLDN_DM | FORCE_PULLDN_DP |
1277                         COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS;
1278         writel(val, base + UTMIP_MISC_CFG0);
1279         val = readl(base + UTMIP_MISC_CFG0);
1280         val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1281         if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
1282                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
1283         else
1284                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
1285         writel(val, base + UTMIP_MISC_CFG0);
1286         udelay(1);
1287
1288         val = readl(base + UTMIP_MISC_CFG0);
1289         val |= UTMIP_DPDM_OBSERVE;
1290         writel(val, base + UTMIP_MISC_CFG0);
1291         udelay(10);
1292         DBG("%s(%d) Enable OBS bus\n", __func__, __LINE__);
1293         PHY_DBG("ENABLE_OBS_BUS\n");
1294 }
1295
1296 static int utmi_phy_disable_obs_bus(struct tegra_usb_phy *phy)
1297 {
1298         unsigned long val;
1299         void __iomem *base = phy->regs;
1300         unsigned long flags;
1301
1302         /* check if OBS bus is already enabled */
1303         val = readl(base + UTMIP_MISC_CFG0);
1304         if (val & UTMIP_DPDM_OBSERVE) {
1305                 PHY_DBG("DISABLE_OBS_BUS\n");
1306
1307                 /* disable ALL interrupts on current CPU */
1308                 local_irq_save(flags);
1309
1310                 /* Change the UTMIP OBS bus to drive SE0 */
1311                 val = readl(base + UTMIP_MISC_CFG0);
1312                 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1313                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_SE0;
1314                 writel(val, base + UTMIP_MISC_CFG0);
1315
1316                 /* Wait for 3us(2 LS bit times) */
1317                 udelay(3);
1318
1319                 /* Release UTMIP OBS bus */
1320                 val = readl(base + UTMIP_MISC_CFG0);
1321                 val &= ~UTMIP_DPDM_OBSERVE;
1322                 writel(val, base + UTMIP_MISC_CFG0);
1323
1324                 /* Release DP/DM pulldown for Host mode */
1325                 val = readl(base + UTMIP_MISC_CFG0);
1326                 val &= ~(FORCE_PULLDN_DM | FORCE_PULLDN_DP |
1327                                 COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS);
1328                 writel(val, base + UTMIP_MISC_CFG0);
1329
1330                 val = readl(base + USB_USBCMD);
1331                 val |= USB_USBCMD_RS;
1332                 writel(val, base + USB_USBCMD);
1333
1334                 /* restore ALL interrupts on current CPU */
1335                 local_irq_restore(flags);
1336
1337                 if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
1338                                                          USB_USBCMD_RS, 2000)) {
1339                         pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
1340                         return -ETIMEDOUT;
1341                 }
1342         }
1343         return 0;
1344 }
1345
1346 static int utmi_phy_post_resume(struct tegra_usb_phy *phy)
1347 {
1348         unsigned long val;
1349         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1350         unsigned  int inst = phy->inst;
1351
1352         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1353         val = readl(pmc_base + PMC_SLEEP_CFG);
1354         /* if PMC is not disabled by now then disable it */
1355         if (val & UTMIP_MASTER_ENABLE(inst)) {
1356                 utmip_phy_disable_pmc_bus_ctrl(phy);
1357         }
1358
1359         utmi_phy_disable_obs_bus(phy);
1360
1361         return 0;
1362 }
1363
1364 static int utmi_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1365 {
1366         unsigned long val;
1367         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1368         void __iomem *base = phy->regs;
1369         unsigned  int inst = phy->inst;
1370
1371         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1372         phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
1373                         HOSTPC1_DEVLC_PSPD_MASK;
1374
1375         if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH) {
1376                 /* Disable interrupts */
1377                 writel(0, base + USB_USBINTR);
1378                 /* Clear the run bit to stop SOFs - 2LS WAR */
1379                 val = readl(base + USB_USBCMD);
1380                 val &= ~USB_USBCMD_RS;
1381                 writel(val, base + USB_USBCMD);
1382                 if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
1383                                                          USB_USBSTS_HCH, 2000)) {
1384                         pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
1385                 }
1386         }
1387
1388         val = readl(pmc_base + PMC_SLEEP_CFG);
1389         if (val & UTMIP_MASTER_ENABLE(inst)) {
1390                 if (!remote_wakeup)
1391                         utmip_phy_disable_pmc_bus_ctrl(phy);
1392         } else {
1393                 utmi_phy_enable_obs_bus(phy);
1394         }
1395
1396         return 0;
1397 }
1398
1399 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
1400 {
1401         unsigned long val;
1402         void __iomem *base = phy->regs;
1403
1404         PHY_DBG("%s(%d) inst:[%d] BEGIN\n", __func__, __LINE__, phy->inst);
1405         if (!phy->phy_clk_on) {
1406                 PHY_DBG("%s(%d) inst:[%d] phy clk is already off\n",
1407                                         __func__, __LINE__, phy->inst);
1408                 return 0;
1409         }
1410
1411         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1412                 utmip_powerdown_pmc_wake_detect(phy);
1413
1414                 val = readl(base + USB_SUSP_CTRL);
1415                 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
1416                 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
1417                 writel(val, base + USB_SUSP_CTRL);
1418
1419                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1420                 val |= UTMIP_PD_CHRG;
1421                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1422         } else {
1423                 phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
1424                                 HOSTPC1_DEVLC_PSPD_MASK;
1425
1426                 /* Disable interrupts */
1427                 writel(0, base + USB_USBINTR);
1428
1429                 /* Clear the run bit to stop SOFs - 2LS WAR */
1430                 val = readl(base + USB_USBCMD);
1431                 val &= ~USB_USBCMD_RS;
1432                 writel(val, base + USB_USBCMD);
1433
1434                 if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
1435                                                          USB_USBSTS_HCH, 2000)) {
1436                         pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
1437                 }
1438                 utmip_setup_pmc_wake_detect(phy);
1439         }
1440
1441         if (!phy->pdata->u_data.host.hot_plug) {
1442                 val = readl(base + UTMIP_XCVR_CFG0);
1443                 val |= (UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
1444                          UTMIP_FORCE_PDZI_POWERDOWN);
1445                 writel(val, base + UTMIP_XCVR_CFG0);
1446         }
1447
1448         val = readl(base + UTMIP_XCVR_CFG1);
1449         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1450                    UTMIP_FORCE_PDDR_POWERDOWN;
1451         writel(val, base + UTMIP_XCVR_CFG1);
1452
1453         val = readl(base + UTMIP_BIAS_CFG1);
1454         val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
1455         writel(val, base + UTMIP_BIAS_CFG1);
1456
1457         utmi_phy_pad_power_off(phy);
1458
1459         if (phy->pdata->u_data.host.hot_plug) {
1460                 bool enable_hotplug = true;
1461                 /* if it is OTG port then make sure to enable hot-plug feature
1462                    only if host adaptor is connected, i.e id is low */
1463                 if (phy->pdata->port_otg) {
1464                         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1465                         enable_hotplug = (val & USB_ID_STATUS) ? false : true;
1466                 }
1467                 if (enable_hotplug) {
1468                         val = readl(base + USB_PORTSC);
1469                         val |= USB_PORTSC_WKCN;
1470                         writel(val, base + USB_PORTSC);
1471
1472                         val = readl(base + USB_SUSP_CTRL);
1473                         val |= USB_PHY_CLK_VALID_INT_ENB;
1474                         writel(val, base + USB_SUSP_CTRL);
1475                 } else {
1476                         /* Disable PHY clock valid interrupts while going into suspend*/
1477                         val = readl(base + USB_SUSP_CTRL);
1478                         val &= ~USB_PHY_CLK_VALID_INT_ENB;
1479                         writel(val, base + USB_SUSP_CTRL);
1480                 }
1481         }
1482
1483         val = readl(base + HOSTPC1_DEVLC);
1484         val |= HOSTPC1_DEVLC_PHCD;
1485         writel(val, base + HOSTPC1_DEVLC);
1486
1487         if (!phy->pdata->u_data.host.hot_plug) {
1488                 val = readl(base + USB_SUSP_CTRL);
1489                 val |= UTMIP_RESET;
1490                 writel(val, base + USB_SUSP_CTRL);
1491         }
1492
1493         phy->phy_clk_on = false;
1494         phy->hw_accessible = false;
1495
1496         PHY_DBG("%s(%d) inst:[%d] END\n", __func__, __LINE__, phy->inst);
1497
1498         return 0;
1499 }
1500
1501
1502 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
1503 {
1504         unsigned long val;
1505         void __iomem *base = phy->regs;
1506         struct tegra_utmi_config *config = &phy->pdata->u_cfg.utmi;
1507
1508         PHY_DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1509         if (phy->phy_clk_on) {
1510                 PHY_DBG("%s(%d) inst:[%d] phy clk is already On\n",
1511                                         __func__, __LINE__, phy->inst);
1512                 return 0;
1513         }
1514         val = readl(base + USB_SUSP_CTRL);
1515         val |= UTMIP_RESET;
1516         writel(val, base + USB_SUSP_CTRL);
1517
1518         val = readl(base + UTMIP_TX_CFG0);
1519         val |= UTMIP_FS_PREABMLE_J;
1520         writel(val, base + UTMIP_TX_CFG0);
1521
1522         val = readl(base + UTMIP_HSRX_CFG0);
1523         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
1524         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
1525         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
1526         writel(val, base + UTMIP_HSRX_CFG0);
1527
1528         val = readl(base + UTMIP_HSRX_CFG1);
1529         val &= ~UTMIP_HS_SYNC_START_DLY(~0);
1530         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
1531         writel(val, base + UTMIP_HSRX_CFG1);
1532
1533         val = readl(base + UTMIP_DEBOUNCE_CFG0);
1534         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
1535         val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
1536         writel(val, base + UTMIP_DEBOUNCE_CFG0);
1537
1538         val = readl(base + UTMIP_MISC_CFG0);
1539         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
1540         writel(val, base + UTMIP_MISC_CFG0);
1541
1542         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1543                 val = readl(base + USB_SUSP_CTRL);
1544                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
1545                 writel(val, base + USB_SUSP_CTRL);
1546
1547                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1548                 val &= ~UTMIP_PD_CHRG;
1549                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1550         } else {
1551                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1552                 val |= UTMIP_PD_CHRG;
1553                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1554         }
1555
1556         utmi_phy_pad_power_on(phy);
1557
1558         val = readl(base + UTMIP_XCVR_CFG0);
1559         val &= ~(UTMIP_XCVR_LSBIAS_SEL | UTMIP_FORCE_PD_POWERDOWN |
1560                  UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN |
1561                  UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_LSFSLEW(~0) |
1562                  UTMIP_XCVR_LSRSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
1563         val |= UTMIP_XCVR_SETUP(phy->utmi_xcvr_setup);
1564         val |= UTMIP_XCVR_SETUP_MSB(XCVR_SETUP_MSB_CALIB(phy->utmi_xcvr_setup));
1565         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
1566         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
1567         if (!config->xcvr_use_lsb)
1568                 val |= UTMIP_XCVR_HSSLEW_MSB(0x8);
1569         writel(val, base + UTMIP_XCVR_CFG0);
1570
1571         val = readl(base + UTMIP_XCVR_CFG1);
1572         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1573                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
1574         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
1575         writel(val, base + UTMIP_XCVR_CFG1);
1576
1577         val = readl(base + UTMIP_BIAS_CFG1);
1578         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
1579         val |= UTMIP_BIAS_PDTRK_COUNT(phy->freq->pdtrk_count);
1580         writel(val, base + UTMIP_BIAS_CFG1);
1581
1582         val = readl(base + UTMIP_SPARE_CFG0);
1583         val &= ~FUSE_SETUP_SEL;
1584         val |= FUSE_ATERM_SEL;
1585         writel(val, base + UTMIP_SPARE_CFG0);
1586
1587         val = readl(base + USB_SUSP_CTRL);
1588         val |= UTMIP_PHY_ENABLE;
1589         writel(val, base + USB_SUSP_CTRL);
1590
1591         val = readl(base + USB_SUSP_CTRL);
1592         val &= ~UTMIP_RESET;
1593         writel(val, base + USB_SUSP_CTRL);
1594
1595         val = readl(base + HOSTPC1_DEVLC);
1596         val &= ~HOSTPC1_DEVLC_PHCD;
1597         writel(val, base + HOSTPC1_DEVLC);
1598
1599         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1600                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500))
1601                 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
1602
1603         utmi_phy_enable_trking_data(phy);
1604
1605         if (phy->inst == 2)
1606                 writel(0, base + ICUSB_CTRL);
1607
1608         val = readl(base + USB_USBMODE);
1609         val &= ~USB_USBMODE_MASK;
1610         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST)
1611                 val |= USB_USBMODE_HOST;
1612         else
1613                 val |= USB_USBMODE_DEVICE;
1614         writel(val, base + USB_USBMODE);
1615
1616         val = readl(base + HOSTPC1_DEVLC);
1617         val &= ~HOSTPC1_DEVLC_PTS(~0);
1618         val |= HOSTPC1_DEVLC_STS;
1619         writel(val, base + HOSTPC1_DEVLC);
1620
1621         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE)
1622                 utmip_powerup_pmc_wake_detect(phy);
1623         phy->phy_clk_on = true;
1624         phy->hw_accessible = true;
1625         PHY_DBG("%s(%d) End inst:[%d]\n", __func__, __LINE__, phy->inst);
1626         return 0;
1627 }
1628
1629 static void utmi_phy_restore_start(struct tegra_usb_phy *phy)
1630 {
1631         unsigned long val;
1632         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1633         int inst = phy->inst;
1634
1635         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1636         val = readl(pmc_base + UTMIP_UHSIC_STATUS);
1637         /* Check whether we wake up from the remote resume.
1638            For lp1 case, pmc is not responsible for waking the
1639            system, it's the flow controller and hence
1640            UTMIP_WALK_PTR_VAL(inst) will return 0.
1641            Also, for lp1 case phy->remote_wakeup will already be set
1642            to true by utmi_phy_irq() when the remote wakeup happens.
1643            Hence change the logic in the else part to enter only
1644            if phy->remote_wakeup is not set to true by the
1645            utmi_phy_irq(). */
1646         if (UTMIP_WALK_PTR_VAL(inst) & val) {
1647                 phy->remote_wakeup = true;
1648         } else if(!phy->remote_wakeup) {
1649                 if (!((UTMIP_USBON_VAL(phy->inst) |
1650                         UTMIP_USBOP_VAL(phy->inst)) & val)) {
1651                                 utmip_phy_disable_pmc_bus_ctrl(phy);
1652                 }
1653         }
1654         utmi_phy_enable_obs_bus(phy);
1655 }
1656
1657 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
1658 {
1659         unsigned long val;
1660         void __iomem *base = phy->regs;
1661         int wait_time_us = 25000; /* FPR should be set by this time */
1662
1663         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1664         /* check whether we wake up from the remote resume */
1665         if (phy->remote_wakeup) {
1666                 /* wait until SUSPEND and RESUME bit is cleared on remote resume */
1667                 do {
1668                         val = readl(base + USB_PORTSC);
1669                         udelay(1);
1670                         if (wait_time_us == 0) {
1671                                 PHY_DBG("%s PMC REMOTE WAKEUP FPR timeout val = 0x%x instance = %d\n", __func__, val, phy->inst);
1672                                 utmip_phy_disable_pmc_bus_ctrl(phy);
1673                                 utmi_phy_post_resume(phy);
1674                                 return;
1675                         }
1676                         wait_time_us--;
1677                 } while (val & (USB_PORTSC_RESUME | USB_PORTSC_SUSP));
1678
1679                 /* wait for 25 ms to port resume complete */
1680                 msleep(25);
1681                 /* disable PMC master control */
1682                 utmip_phy_disable_pmc_bus_ctrl(phy);
1683
1684                 /* Clear PCI and SRI bits to avoid an interrupt upon resume */
1685                 val = readl(base + USB_USBSTS);
1686                 writel(val, base + USB_USBSTS);
1687                 /* wait to avoid SOF if there is any */
1688                 if (usb_phy_reg_status_wait(base + USB_USBSTS,
1689                         USB_USBSTS_SRI, USB_USBSTS_SRI, 2500) < 0) {
1690                         pr_err("%s: timeout waiting for SOF\n", __func__);
1691                 }
1692                 utmi_phy_post_resume(phy);
1693         }
1694 }
1695
1696 static int utmi_phy_resume(struct tegra_usb_phy *phy)
1697 {
1698         int status = 0;
1699         unsigned long val;
1700         void __iomem *base = phy->regs;
1701
1702         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1703         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) {
1704                 if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
1705                         utmi_phy_restore_start(phy);
1706                         usb_phy_bringup_host_controller(phy);
1707                         utmi_phy_restore_end(phy);
1708                 } else {
1709                         /* device is plugged in when system is in LP0 */
1710                         /* bring up the controller from LP0*/
1711                         val = readl(base + USB_USBCMD);
1712                         val |= USB_CMD_RESET;
1713                         writel(val, base + USB_USBCMD);
1714
1715                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1716                                 USB_CMD_RESET, 0, 2500) < 0) {
1717                                 pr_err("%s: timeout waiting for reset\n", __func__);
1718                         }
1719
1720                         val = readl(base + USB_USBMODE);
1721                         val &= ~USB_USBMODE_MASK;
1722                         val |= USB_USBMODE_HOST;
1723                         writel(val, base + USB_USBMODE);
1724
1725                         val = readl(base + HOSTPC1_DEVLC);
1726                         val &= ~HOSTPC1_DEVLC_PTS(~0);
1727                         val |= HOSTPC1_DEVLC_STS;
1728                         writel(val, base + HOSTPC1_DEVLC);
1729
1730                         writel(USB_USBCMD_RS, base + USB_USBCMD);
1731
1732                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1733                                 USB_USBCMD_RS, USB_USBCMD_RS, 2500) < 0) {
1734                                 pr_err("%s: timeout waiting for run bit\n", __func__);
1735                         }
1736
1737                         /* Enable Port Power */
1738                         val = readl(base + USB_PORTSC);
1739                         val |= USB_PORTSC_PP;
1740                         writel(val, base + USB_PORTSC);
1741                         udelay(10);
1742
1743                         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1744                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1745                 }
1746         }
1747
1748         return status;
1749 }
1750
1751 bool utmi_phy_charger_detect(struct tegra_usb_phy *phy)
1752 {
1753         unsigned long val;
1754         void __iomem *base = phy->regs;
1755         bool status;
1756
1757         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1758         if (phy->pdata->op_mode != TEGRA_USB_OPMODE_DEVICE) {
1759                 /* Charger detection is not there for ULPI
1760                  * return Charger not available */
1761                 return false;
1762         }
1763
1764         /* Enable charger detection logic */
1765         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1766         val |= UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN;
1767         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1768
1769         /* Source should be on for 100 ms as per USB charging spec */
1770         msleep(TDP_SRC_ON_MS);
1771
1772         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1773         /* If charger is not connected disable the interrupt */
1774         val &= ~VDAT_DET_INT_EN;
1775         val |= VDAT_DET_CHG_DET;
1776         writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
1777
1778         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1779         if (val & VDAT_DET_STS)
1780                 status = true;
1781         else
1782                 status = false;
1783
1784         /* Disable charger detection logic */
1785         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1786         val &= ~(UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN);
1787         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1788
1789         /* Delay of 40 ms before we pull the D+ as per battery charger spec */
1790         msleep(TDPSRC_CON_MS);
1791
1792         return status;
1793 }
1794
1795 static void uhsic_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
1796 {
1797         unsigned long val;
1798         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1799
1800         /* turn on pad detectors for HSIC*/
1801         val = readl(pmc_base + PMC_USB_AO);
1802         val &= ~(HSIC_RESERVED_P0 | STROBE_VAL_PD_P0 | DATA_VAL_PD_P0);
1803         writel(val, pmc_base + PMC_USB_AO);
1804
1805         /* Disable PMC master mode by clearing MASTER_EN */
1806         val = readl(pmc_base + PMC_SLEEP_CFG);
1807         val &= ~(UHSIC_MASTER_ENABLE_P0);
1808         writel(val, pmc_base + PMC_SLEEP_CFG);
1809         mdelay(1);
1810 }
1811
1812 static void uhsic_setup_pmc_wake_detect(struct tegra_usb_phy *phy)
1813 {
1814         unsigned long val;
1815         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1816         void __iomem *base = phy->regs;
1817         bool port_connected;
1818
1819         DBG("%s:%d\n", __func__, __LINE__);
1820
1821         /* check for port connect status */
1822         val = readl(base + USB_PORTSC);
1823         port_connected = val & USB_PORTSC_CCS;
1824
1825         if (!port_connected)
1826                 return;
1827
1828         /*Set PMC MASTER bits to do the following
1829         * a. Take over the hsic drivers
1830         * b. set up such that it will take over resume
1831         *        if remote wakeup is detected
1832         * Prepare PMC to take over suspend-wake detect-drive resume until USB
1833         * controller ready
1834         */
1835
1836         /* disable master enable in PMC */
1837         val = readl(pmc_base + PMC_SLEEP_CFG);
1838         val &= ~UHSIC_MASTER_ENABLE_P0;
1839         writel(val, pmc_base + PMC_SLEEP_CFG);
1840
1841         /* UTMIP_PWR_PX=1 for power savings mode */
1842         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
1843         val |= UHSIC_PWR;
1844         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
1845
1846
1847         /* Enable which type of event can trigger a walk,
1848         * in this case usb_line_wake */
1849         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
1850         val |= UHSIC_LINEVAL_WALK_EN;
1851         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
1852
1853         /* program walk sequence, maintain a J, followed by a driven K
1854         * to signal a resume once an wake event is detected */
1855
1856         val = readl(pmc_base + PMC_SLEEPWALK_UHSIC);
1857
1858         val &= ~UHSIC_DATA_RPU_A;
1859         val |=  UHSIC_DATA_RPD_A;
1860         val &= ~UHSIC_STROBE_RPD_A;
1861         val |=  UHSIC_STROBE_RPU_A;
1862         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1863
1864         val &= ~UHSIC_DATA_RPD_B;
1865         val |=  UHSIC_DATA_RPU_B;
1866         val &= ~UHSIC_STROBE_RPU_B;
1867         val |=  UHSIC_STROBE_RPD_B;
1868         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1869
1870         val &= ~UHSIC_DATA_RPD_C;
1871         val |=  UHSIC_DATA_RPU_C;
1872         val &= ~UHSIC_STROBE_RPU_C;
1873         val |=  UHSIC_STROBE_RPD_C;
1874         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1875
1876         val &= ~UHSIC_DATA_RPD_D;
1877         val |=  UHSIC_DATA_RPU_D;
1878         val &= ~UHSIC_STROBE_RPU_D;
1879         val |=  UHSIC_STROBE_RPD_D;
1880         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1881
1882         /* turn on pad detectors */
1883         val = readl(pmc_base + PMC_USB_AO);
1884         val &= ~(STROBE_VAL_PD_P0 | DATA_VAL_PD_P0);
1885         writel(val, pmc_base + PMC_USB_AO);
1886         /* Add small delay before usb detectors provide stable line values */
1887         udelay(1);
1888
1889         phy->remote_wakeup = false;
1890
1891         /* Turn over pad configuration to PMC  for line wake events*/
1892         val = readl(pmc_base + PMC_SLEEP_CFG);
1893         val &= ~UHSIC_WAKE_VAL(~0);
1894         val |= UHSIC_WAKE_VAL(WAKE_VAL_SD10);
1895         val |= UHSIC_MASTER_ENABLE;
1896         writel(val, pmc_base + PMC_SLEEP_CFG);
1897
1898         val = readl(base + UHSIC_PMC_WAKEUP0);
1899         val |= EVENT_INT_ENB;
1900         writel(val, base + UHSIC_PMC_WAKEUP0);
1901
1902         DBG("%s:PMC enabled for HSIC remote wakeup\n", __func__);
1903 }
1904
1905 static void uhsic_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy)
1906 {
1907         unsigned long val;
1908         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1909         void __iomem *base = phy->regs;
1910
1911         DBG("%s (%d)\n", __func__, __LINE__);
1912         val = readl(pmc_base + PMC_SLEEP_CFG);
1913         val &= ~UHSIC_WAKE_VAL(0x0);
1914         val |= UHSIC_WAKE_VAL(WAKE_VAL_NONE);
1915         writel(val, pmc_base + PMC_SLEEP_CFG);
1916
1917         val = readl(pmc_base + PMC_TRIGGERS);
1918         val |= UHSIC_CLR_WAKE_ALARM_P0 | UHSIC_CLR_WALK_PTR_P0;
1919         writel(val, pmc_base + PMC_TRIGGERS);
1920
1921         val = readl(base + UHSIC_PMC_WAKEUP0);
1922         val &= ~EVENT_INT_ENB;
1923         writel(val, base + UHSIC_PMC_WAKEUP0);
1924
1925         /* Disable PMC master mode by clearing MASTER_EN */
1926         val = readl(pmc_base + PMC_SLEEP_CFG);
1927         val &= ~(UHSIC_MASTER_ENABLE);
1928         writel(val, pmc_base + PMC_SLEEP_CFG);
1929
1930         /* turn off pad detectors */
1931         val = readl(pmc_base + PMC_USB_AO);
1932         val |= (STROBE_VAL_PD_P0 | DATA_VAL_PD_P0);
1933         writel(val, pmc_base + PMC_USB_AO);
1934
1935         phy->remote_wakeup = false;
1936 }
1937
1938 static bool uhsic_phy_remotewake_detected(struct tegra_usb_phy *phy)
1939 {
1940         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1941         void __iomem *base = phy->regs;
1942         u32 val;
1943
1944         val = readl(base + UHSIC_PMC_WAKEUP0);
1945         if (val & EVENT_INT_ENB) {
1946                 val = readl(pmc_base + UTMIP_UHSIC_STATUS);
1947                 if (UHSIC_WAKE_ALARM & val) {
1948                         val = readl(pmc_base + PMC_SLEEP_CFG);
1949                         val &= ~UHSIC_WAKE_VAL(0x0);
1950                         val |= UHSIC_WAKE_VAL(WAKE_VAL_NONE);
1951                         writel(val, pmc_base + PMC_SLEEP_CFG);
1952
1953                         val = readl(pmc_base + PMC_TRIGGERS);
1954                         val |= UHSIC_CLR_WAKE_ALARM_P0 | UHSIC_CLR_WALK_PTR_P0;
1955                         writel(val, pmc_base + PMC_TRIGGERS);
1956
1957                         val = readl(base + UHSIC_PMC_WAKEUP0);
1958                         val &= ~EVENT_INT_ENB;
1959                         writel(val, base + UHSIC_PMC_WAKEUP0);
1960                         phy->remote_wakeup = true;
1961                         DBG("%s:PMC remote wakeup detected for HSIC\n", __func__);
1962                         return true;
1963                 }
1964         }
1965         return false;
1966 }
1967
1968 static int uhsic_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1969 {
1970         DBG("%s(%d)\n", __func__, __LINE__);
1971
1972         if (!remote_wakeup)
1973                 usb_phy_wait_for_sof(phy);
1974
1975         return 0;
1976 }
1977
1978 static int uhsic_phy_post_resume(struct tegra_usb_phy *phy)
1979 {
1980         unsigned long val;
1981         void __iomem *base = phy->regs;
1982
1983         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1984         val = readl(base + USB_TXFILLTUNING);
1985         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
1986                 val = USB_FIFO_TXFILL_THRES(0x10);
1987                 writel(val, base + USB_TXFILLTUNING);
1988         }
1989
1990         return 0;
1991 }
1992
1993 static void uhsic_phy_restore_start(struct tegra_usb_phy *phy)
1994 {
1995         unsigned long val;
1996         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1997         void __iomem *base = phy->regs;
1998
1999         val = readl(pmc_base + UTMIP_UHSIC_STATUS);
2000
2001         /* check whether we wake up from the remote resume */
2002         if (UHSIC_WALK_PTR_VAL & val) {
2003                 phy->remote_wakeup = true;
2004                 pr_info("%s: uhsic remote wakeup detected\n", __func__);
2005         } else {
2006                 if (!((UHSIC_STROBE_VAL_P0 | UHSIC_DATA_VAL_P0) & val)) {
2007                                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2008                 } else {
2009                         DBG("%s(%d): setting pretend connect\n", __func__, __LINE__);
2010                         val = readl(base + UHSIC_CMD_CFG0);
2011                         val |= UHSIC_PRETEND_CONNECT_DETECT;
2012                         writel(val, base + UHSIC_CMD_CFG0);
2013                 }
2014         }
2015 }
2016
2017 static void uhsic_phy_restore_end(struct tegra_usb_phy *phy)
2018 {
2019
2020         unsigned long val;
2021         void __iomem *base = phy->regs;
2022         int wait_time_us = 3000; /* FPR should be set by this time */
2023
2024         DBG("%s(%d)\n", __func__, __LINE__);
2025
2026         /* check whether we wake up from the remote resume */
2027         if (phy->remote_wakeup) {
2028                 /* wait until FPR bit is set automatically on remote resume */
2029                 do {
2030                         val = readl(base + USB_PORTSC);
2031                         udelay(1);
2032                         if (wait_time_us == 0) {
2033                                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2034                                 uhsic_phy_post_resume(phy);
2035                                 return;
2036                         }
2037                         wait_time_us--;
2038                 } while (!(val & USB_PORTSC_RESUME));
2039                 /* wait for 25 ms to port resume complete */
2040                 msleep(25);
2041                 /* disable PMC master control */
2042                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2043
2044                 /* Clear PCI and SRI bits to avoid an interrupt upon resume */
2045                 val = readl(base + USB_USBSTS);
2046                 writel(val, base + USB_USBSTS);
2047                 /* wait to avoid SOF if there is any */
2048                 if (usb_phy_reg_status_wait(base + USB_USBSTS,
2049                         USB_USBSTS_SRI, USB_USBSTS_SRI, 2500)) {
2050                         pr_warn("%s: timeout waiting for SOF\n", __func__);
2051                 }
2052                 uhsic_phy_post_resume(phy);
2053         } else {
2054                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2055         }
2056
2057         /* Set RUN bit */
2058         val = readl(base + USB_USBCMD);
2059         val |= USB_USBCMD_RS;
2060         writel(val, base + USB_USBCMD);
2061         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2062                                                  USB_USBCMD_RS, 2000)) {
2063                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2064                 return;
2065         }
2066 }
2067
2068 static int hsic_rail_enable(struct tegra_usb_phy *phy)
2069 {
2070         int ret;
2071
2072         if (phy->hsic_reg == NULL) {
2073                 phy->hsic_reg = regulator_get(NULL, "avdd_hsic");
2074                 if (IS_ERR_OR_NULL(phy->hsic_reg)) {
2075                         pr_err("HSIC: Could not get regulator avdd_hsic\n");
2076                         phy->hsic_reg = NULL;
2077                         return PTR_ERR(phy->hsic_reg);
2078                 }
2079         }
2080
2081         ret = regulator_enable(phy->hsic_reg);
2082         if (ret < 0) {
2083                 pr_err("%s avdd_hsic could not be enabled\n", __func__);
2084                 return ret;
2085         }
2086
2087         return 0;
2088 }
2089
2090 static int hsic_rail_disable(struct tegra_usb_phy *phy)
2091 {
2092         int ret;
2093
2094         if (phy->hsic_reg == NULL) {
2095                 pr_warn("%s: unbalanced disable\n", __func__);
2096                 return -EIO;
2097         }
2098
2099         ret = regulator_disable(phy->hsic_reg);
2100         if (ret < 0) {
2101                 pr_err("HSIC regulator avdd_hsic cannot be disabled\n");
2102                 return ret;
2103         }
2104
2105         return 0;
2106 }
2107
2108 static int uhsic_phy_open(struct tegra_usb_phy *phy)
2109 {
2110         unsigned long parent_rate;
2111         int i;
2112         int ret;
2113
2114         phy->hsic_reg = NULL;
2115         ret = hsic_rail_enable(phy);
2116         if (ret < 0) {
2117                 pr_err("%s avdd_hsic could not be enabled\n", __func__);
2118                 return ret;
2119         }
2120
2121         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2122         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
2123         for (i = 0; i < ARRAY_SIZE(uhsic_freq_table); i++) {
2124                 if (uhsic_freq_table[i].freq == parent_rate) {
2125                         phy->freq = &uhsic_freq_table[i];
2126                         break;
2127                 }
2128         }
2129         if (!phy->freq) {
2130                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
2131                 return -EINVAL;
2132         }
2133
2134         uhsic_powerup_pmc_wake_detect(phy);
2135
2136         return 0;
2137 }
2138
2139 static void uhsic_phy_close(struct tegra_usb_phy *phy)
2140 {
2141         int ret;
2142
2143         ret = hsic_rail_disable(phy);
2144         if (ret < 0)
2145                 pr_err("%s avdd_hsic could not be disabled\n", __func__);
2146 }
2147
2148 static int uhsic_phy_irq(struct tegra_usb_phy *phy)
2149 {
2150         usb_phy_fence_read(phy);
2151         /* check if there is any remote wake event */
2152         if (uhsic_phy_remotewake_detected(phy))
2153                 pr_info("%s: uhsic remote wake detected\n", __func__);
2154         return IRQ_HANDLED;
2155 }
2156
2157 static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
2158 {
2159         unsigned long val;
2160         void __iomem *base = phy->regs;
2161         struct tegra_hsic_config *config = &phy->pdata->u_cfg.hsic;
2162
2163         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2164
2165         if (phy->phy_clk_on) {
2166                 DBG("%s(%d) inst:[%d] phy clk is already On\n",
2167                                         __func__, __LINE__, phy->inst);
2168                 return 0;
2169         }
2170
2171         val = readl(base + UHSIC_PADS_CFG1);
2172         val &= ~(UHSIC_PD_BG | UHSIC_PD_TRK | UHSIC_PD_RX |
2173                         UHSIC_PD_ZI | UHSIC_RPD_DATA | UHSIC_RPD_STROBE);
2174         val |= (UHSIC_RX_SEL | UHSIC_PD_TX);
2175         writel(val, base + UHSIC_PADS_CFG1);
2176
2177         val = readl(base + USB_SUSP_CTRL);
2178         val |= UHSIC_RESET;
2179         writel(val, base + USB_SUSP_CTRL);
2180         udelay(1);
2181
2182         val = readl(base + USB_SUSP_CTRL);
2183         val |= UHSIC_PHY_ENABLE;
2184         writel(val, base + USB_SUSP_CTRL);
2185
2186         val = readl(base + UHSIC_HSRX_CFG0);
2187         val |= UHSIC_IDLE_WAIT(config->idle_wait_delay);
2188         val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(config->elastic_underrun_limit);
2189         val |= UHSIC_ELASTIC_OVERRUN_LIMIT(config->elastic_overrun_limit);
2190         writel(val, base + UHSIC_HSRX_CFG0);
2191
2192         val = readl(base + UHSIC_HSRX_CFG1);
2193         val |= UHSIC_HS_SYNC_START_DLY(config->sync_start_delay);
2194         writel(val, base + UHSIC_HSRX_CFG1);
2195
2196         /* WAR HSIC TX */
2197         val = readl(base + UHSIC_TX_CFG0);
2198         val &= ~UHSIC_HS_READY_WAIT_FOR_VALID;
2199         writel(val, base + UHSIC_TX_CFG0);
2200
2201         val = readl(base + UHSIC_MISC_CFG0);
2202         val |= UHSIC_SUSPEND_EXIT_ON_EDGE;
2203         /* Disable generic bus reset, to allow AP30 specific bus reset*/
2204         val |= UHSIC_DISABLE_BUSRESET;
2205         writel(val, base + UHSIC_MISC_CFG0);
2206
2207         val = readl(base + UHSIC_MISC_CFG1);
2208         val |= UHSIC_PLLU_STABLE_COUNT(phy->freq->stable_count);
2209         writel(val, base + UHSIC_MISC_CFG1);
2210
2211         val = readl(base + UHSIC_PLL_CFG1);
2212         val |= UHSIC_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
2213         val |= UHSIC_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count);
2214         writel(val, base + UHSIC_PLL_CFG1);
2215
2216         val = readl(base + USB_SUSP_CTRL);
2217         val &= ~(UHSIC_RESET);
2218         writel(val, base + USB_SUSP_CTRL);
2219         udelay(1);
2220
2221         val = readl(base + UHSIC_PADS_CFG1);
2222         val &= ~(UHSIC_PD_TX);
2223         writel(val, base + UHSIC_PADS_CFG1);
2224
2225         val = readl(base + USB_USBMODE);
2226         val |= USB_USBMODE_HOST;
2227         writel(val, base + USB_USBMODE);
2228
2229         /* Change the USB controller PHY type to HSIC */
2230         val = readl(base + HOSTPC1_DEVLC);
2231         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
2232         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2233         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
2234         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2235         val &= ~HOSTPC1_DEVLC_STS;
2236         writel(val, base + HOSTPC1_DEVLC);
2237
2238         val = readl(base + USB_TXFILLTUNING);
2239         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
2240                 val = USB_FIFO_TXFILL_THRES(0x10);
2241                 writel(val, base + USB_TXFILLTUNING);
2242         }
2243
2244         val = readl(base + USB_PORTSC);
2245         val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN);
2246         writel(val, base + USB_PORTSC);
2247
2248         val = readl(base + UHSIC_PADS_CFG0);
2249         val &= ~(UHSIC_TX_RTUNEN);
2250         /* set Rtune impedance to 50 ohm */
2251         val |= UHSIC_TX_RTUNE(8);
2252         writel(val, base + UHSIC_PADS_CFG0);
2253
2254         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
2255                                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500)) {
2256                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2257                 return -ETIMEDOUT;
2258         }
2259
2260         phy->phy_clk_on = true;
2261         phy->hw_accessible = true;
2262
2263         if (phy->pmc_sleepwalk) {
2264                 DBG("%s(%d) inst:[%d] restore phy\n", __func__, __LINE__,
2265                                         phy->inst);
2266                 uhsic_phy_restore_start(phy);
2267                 usb_phy_bringup_host_controller(phy);
2268                 uhsic_phy_restore_end(phy);
2269                 phy->pmc_sleepwalk = false;
2270         }
2271
2272         return 0;
2273 }
2274
2275 static int uhsic_phy_power_off(struct tegra_usb_phy *phy)
2276 {
2277         unsigned long val;
2278         void __iomem *base = phy->regs;
2279
2280         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2281         if (!phy->phy_clk_on) {
2282                 DBG("%s(%d) inst:[%d] phy clk is already off\n",
2283                                         __func__, __LINE__, phy->inst);
2284                 return 0;
2285         }
2286
2287         phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
2288                         HOSTPC1_DEVLC_PSPD_MASK;
2289
2290         /* Disable interrupts */
2291         writel(0, base + USB_USBINTR);
2292
2293         if (phy->pmc_sleepwalk == false) {
2294                 uhsic_setup_pmc_wake_detect(phy);
2295                 phy->pmc_sleepwalk = true;
2296         }
2297
2298         val = readl(base + HOSTPC1_DEVLC);
2299         val |= HOSTPC1_DEVLC_PHCD;
2300         writel(val, base + HOSTPC1_DEVLC);
2301
2302         /* Remove power downs for HSIC from PADS CFG1 register */
2303         val = readl(base + UHSIC_PADS_CFG1);
2304         val |= (UHSIC_PD_BG |UHSIC_PD_TRK | UHSIC_PD_RX |
2305                         UHSIC_PD_ZI | UHSIC_PD_TX);
2306         writel(val, base + UHSIC_PADS_CFG1);
2307         phy->phy_clk_on = false;
2308         phy->hw_accessible = false;
2309
2310         return 0;
2311 }
2312
2313 int uhsic_phy_bus_port_power(struct tegra_usb_phy *phy)
2314 {
2315         unsigned long val;
2316         void __iomem *base = phy->regs;
2317
2318         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2319
2320         val = readl(base + USB_USBMODE);
2321         val |= USB_USBMODE_HOST;
2322         writel(val, base + USB_USBMODE);
2323
2324         /* Change the USB controller PHY type to HSIC */
2325         val = readl(base + HOSTPC1_DEVLC);
2326         val &= ~(HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK));
2327         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2328         val &= ~(HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK));
2329         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2330         writel(val, base + HOSTPC1_DEVLC);
2331
2332         val = readl(base + UHSIC_MISC_CFG0);
2333         val |= UHSIC_DETECT_SHORT_CONNECT;
2334         writel(val, base + UHSIC_MISC_CFG0);
2335         udelay(1);
2336
2337         val = readl(base + UHSIC_MISC_CFG0);
2338         val |= UHSIC_FORCE_XCVR_MODE;
2339         writel(val, base + UHSIC_MISC_CFG0);
2340
2341         val = readl(base + UHSIC_PADS_CFG1);
2342         val &= ~UHSIC_RPD_STROBE;
2343         writel(val, base + UHSIC_PADS_CFG1);
2344
2345         if (phy->pdata->ops && phy->pdata->ops->port_power)
2346                 phy->pdata->ops->port_power();
2347
2348         if (usb_phy_reg_status_wait(base + UHSIC_STAT_CFG0,
2349                         UHSIC_CONNECT_DETECT, UHSIC_CONNECT_DETECT, 25000)) {
2350                 pr_err("%s: timeout waiting for UHSIC_CONNECT_DETECT\n",
2351                                                                 __func__);
2352                 return -ETIMEDOUT;
2353         }
2354
2355         return 0;
2356 }
2357
2358 static int uhsic_phy_bus_reset(struct tegra_usb_phy *phy)
2359 {
2360         unsigned long val;
2361         void __iomem *base = phy->regs;
2362
2363         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2364
2365         /* Change the USB controller PHY type to HSIC */
2366         val = readl(base + HOSTPC1_DEVLC);
2367         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
2368         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2369         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
2370         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2371         val &= ~HOSTPC1_DEVLC_STS;
2372         writel(val, base + HOSTPC1_DEVLC);
2373         /* wait here, otherwise HOSTPC1_DEVLC_PSPD will timeout */
2374         mdelay(5);
2375
2376         val = readl(base + USB_PORTSC);
2377         val |= USB_PORTSC_PTC(5);
2378         writel(val, base + USB_PORTSC);
2379         udelay(2);
2380
2381         val = readl(base + USB_PORTSC);
2382         val &= ~(USB_PORTSC_PTC(~0));
2383         writel(val, base + USB_PORTSC);
2384         udelay(2);
2385
2386         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_LS(0),
2387                                                  0, 2000)) {
2388                 pr_err("%s: timeout waiting for USB_PORTSC_LS\n", __func__);
2389                 return -ETIMEDOUT;
2390         }
2391
2392         /* Poll until CCS is enabled */
2393         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
2394                                                  USB_PORTSC_CCS, 2000)) {
2395                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
2396                 return -ETIMEDOUT;
2397         }
2398
2399         if (usb_phy_reg_status_wait(base + HOSTPC1_DEVLC,
2400                         HOSTPC1_DEVLC_PSPD(2),
2401                         HOSTPC1_DEVLC_PSPD(2), 2000) < 0) {
2402                 pr_err("%s: timeout waiting hsic high speed configuration\n",
2403                                                 __func__);
2404                         return -ETIMEDOUT;
2405         }
2406
2407         val = readl(base + USB_USBCMD);
2408         val &= ~USB_USBCMD_RS;
2409         writel(val, base + USB_USBCMD);
2410
2411         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
2412                                                  USB_USBSTS_HCH, 2000)) {
2413                 pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
2414                 return -ETIMEDOUT;
2415         }
2416
2417         val = readl(base + UHSIC_PADS_CFG1);
2418         val &= ~UHSIC_RPU_STROBE;
2419         val |= UHSIC_RPD_STROBE;
2420         writel(val, base + UHSIC_PADS_CFG1);
2421
2422         mdelay(50);
2423
2424         val = readl(base + UHSIC_PADS_CFG1);
2425         val &= ~UHSIC_RPD_STROBE;
2426         val |= UHSIC_RPU_STROBE;
2427         writel(val, base + UHSIC_PADS_CFG1);
2428
2429         val = readl(base + USB_USBCMD);
2430         val |= USB_USBCMD_RS;
2431         writel(val, base + USB_USBCMD);
2432
2433         val = readl(base + UHSIC_PADS_CFG1);
2434         val &= ~UHSIC_RPU_STROBE;
2435         writel(val, base + UHSIC_PADS_CFG1);
2436
2437         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2438                                                  USB_USBCMD_RS, 2000)) {
2439                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2440                 return -ETIMEDOUT;
2441         }
2442
2443         return 0;
2444 }
2445
2446 int uhsic_phy_resume(struct tegra_usb_phy *phy)
2447 {
2448         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2449
2450         return 0;
2451 }
2452
2453 static void ulpi_set_trimmer(struct tegra_usb_phy *phy)
2454 {
2455         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2456         void __iomem *base = phy->regs;
2457         unsigned long val;
2458
2459         val = ULPI_DATA_TRIMMER_SEL(config->data_trimmer);
2460         val |= ULPI_STPDIRNXT_TRIMMER_SEL(config->stpdirnxt_trimmer);
2461         val |= ULPI_DIR_TRIMMER_SEL(config->dir_trimmer);
2462         writel(val, base + ULPI_TIMING_CTRL_1);
2463         udelay(10);
2464
2465         val |= ULPI_DATA_TRIMMER_LOAD;
2466         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
2467         val |= ULPI_DIR_TRIMMER_LOAD;
2468         writel(val, base + ULPI_TIMING_CTRL_1);
2469 }
2470
2471 static void reset_utmip_uhsic(void __iomem *base)
2472 {
2473         unsigned long val;
2474
2475         val = readl(base + USB_SUSP_CTRL);
2476         val |= UHSIC_RESET;
2477         writel(val, base + USB_SUSP_CTRL);
2478
2479         val = readl(base + USB_SUSP_CTRL);
2480         val |= UTMIP_RESET;
2481         writel(val, base + USB_SUSP_CTRL);
2482 }
2483
2484 static void ulpi_set_host(void __iomem *base)
2485 {
2486         unsigned long val;
2487
2488         val = readl(base + USB_USBMODE);
2489         val &= ~USB_USBMODE_MASK;
2490         val |= USB_USBMODE_HOST;
2491         writel(val, base + USB_USBMODE);
2492
2493         val = readl(base + HOSTPC1_DEVLC);
2494         val |= HOSTPC1_DEVLC_PTS(2);
2495         writel(val, base + HOSTPC1_DEVLC);
2496 }
2497
2498 static inline void ulpi_pinmux_bypass(struct tegra_usb_phy *phy, bool enable)
2499 {
2500         unsigned long val;
2501         void __iomem *base = phy->regs;
2502
2503         val = readl(base + ULPI_TIMING_CTRL_0);
2504
2505         if (enable)
2506                 val |= ULPI_OUTPUT_PINMUX_BYP;
2507         else
2508                 val &= ~ULPI_OUTPUT_PINMUX_BYP;
2509
2510         writel(val, base + ULPI_TIMING_CTRL_0);
2511 }
2512
2513 static inline void ulpi_null_phy_set_tristate(bool enable)
2514 {
2515 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2516         int tristate = (enable) ? TEGRA_TRI_TRISTATE : TEGRA_TRI_NORMAL;
2517
2518         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA0, tristate);
2519         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA1, tristate);
2520         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA2, tristate);
2521         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA3, tristate);
2522         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA4, tristate);
2523         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA5, tristate);
2524         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA6, tristate);
2525         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA7, tristate);
2526         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_NXT, tristate);
2527
2528         if (enable)
2529                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR, tristate);
2530 #endif
2531 }
2532
2533 static void ulpi_null_phy_obs_read(void)
2534 {
2535         static void __iomem *apb_misc;
2536         unsigned slv0_obs, s2s_obs;
2537
2538         if (!apb_misc)
2539                 apb_misc = ioremap(TEGRA_APB_MISC_BASE, TEGRA_APB_MISC_SIZE);
2540
2541         writel(0x80d1003c, apb_misc + APB_MISC_GP_OBSCTRL_0);
2542         slv0_obs = readl(apb_misc + APB_MISC_GP_OBSDATA_0);
2543
2544         writel(0x80d10040, apb_misc + APB_MISC_GP_OBSCTRL_0);
2545         s2s_obs = readl(apb_misc + APB_MISC_GP_OBSDATA_0);
2546
2547         pr_debug("slv0 obs: %08x\ns2s obs: %08x\n", slv0_obs, s2s_obs);
2548 }
2549
2550 static const struct gpio ulpi_gpios[] = {
2551         {ULPI_STP, GPIOF_IN, "ULPI_STP"},
2552         {ULPI_DIR, GPIOF_OUT_INIT_LOW, "ULPI_DIR"},
2553         {ULPI_D0, GPIOF_OUT_INIT_LOW, "ULPI_D0"},
2554         {ULPI_D1, GPIOF_OUT_INIT_LOW, "ULPI_D1"},
2555 };
2556
2557 static int ulpi_null_phy_open(struct tegra_usb_phy *phy)
2558 {
2559         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2560         int ret;
2561
2562         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2563
2564         ret = gpio_request_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
2565         if (ret)
2566                 return ret;
2567
2568         if (gpio_is_valid(config->phy_restore_gpio)) {
2569                 ret = gpio_request(config->phy_restore_gpio, "phy_restore");
2570                 if (ret)
2571                         goto err_gpio_free;
2572
2573                 gpio_direction_input(config->phy_restore_gpio);
2574         }
2575
2576         tegra_periph_reset_assert(phy->ctrlr_clk);
2577         udelay(10);
2578         tegra_periph_reset_deassert(phy->ctrlr_clk);
2579
2580         return 0;
2581
2582 err_gpio_free:
2583         gpio_free_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
2584         return ret;
2585 }
2586
2587 static void ulpi_null_phy_close(struct tegra_usb_phy *phy)
2588 {
2589         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2590
2591         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2592
2593         if (gpio_is_valid(config->phy_restore_gpio))
2594                 gpio_free(config->phy_restore_gpio);
2595
2596         gpio_free_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
2597 }
2598
2599 static int ulpi_null_phy_power_off(struct tegra_usb_phy *phy)
2600 {
2601         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2602
2603         if (!phy->phy_clk_on) {
2604                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
2605                                                         __LINE__, phy->inst);
2606                 return 0;
2607         }
2608
2609         phy->phy_clk_on = false;
2610         phy->hw_accessible = false;
2611         ulpi_null_phy_set_tristate(true);
2612         return 0;
2613 }
2614
2615 /* NOTE: this function must be called before ehci reset */
2616 static int ulpi_null_phy_init(struct tegra_usb_phy *phy)
2617 {
2618         unsigned long val;
2619         void __iomem *base = phy->regs;
2620
2621         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2622         val = readl(base + ULPIS2S_CTRL);
2623         val |=  ULPIS2S_SLV0_CLAMP_XMIT;
2624         writel(val, base + ULPIS2S_CTRL);
2625
2626         val = readl(base + USB_SUSP_CTRL);
2627         val |= ULPIS2S_SLV0_RESET;
2628         writel(val, base + USB_SUSP_CTRL);
2629         udelay(10);
2630
2631         return 0;
2632 }
2633
2634 static int ulpi_null_phy_irq(struct tegra_usb_phy *phy)
2635 {
2636         unsigned long val;
2637         void __iomem *base = phy->regs;
2638
2639         usb_phy_fence_read(phy);
2640         if (phy->bus_reseting){
2641                 val = readl(base + USB_USBCMD);
2642                 val |= USB_USBCMD_RS;
2643                 writel(val, base + USB_USBCMD);
2644                 phy->bus_reseting = false;
2645         }
2646         return IRQ_HANDLED;
2647 }
2648
2649 /* NOTE: this function must be called after ehci reset */
2650 static int ulpi_null_phy_cmd_reset(struct tegra_usb_phy *phy)
2651 {
2652         unsigned long val;
2653         void __iomem *base = phy->regs;
2654
2655         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2656         ulpi_set_host(base);
2657
2658         /* remove slave0 reset */
2659         val = readl(base + USB_SUSP_CTRL);
2660         val &= ~ULPIS2S_SLV0_RESET;
2661         writel(val, base + USB_SUSP_CTRL);
2662
2663         val = readl(base + ULPIS2S_CTRL);
2664         val &=  ~ULPIS2S_SLV0_CLAMP_XMIT;
2665         writel(val, base + ULPIS2S_CTRL);
2666         udelay(10);
2667
2668         return 0;
2669 }
2670
2671 static int ulpi_phy_bus_reset(struct tegra_usb_phy *phy)
2672 {
2673         unsigned long val;
2674         void __iomem *base = phy->regs;
2675
2676         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2677
2678         /*DISABLE RUN BIT */
2679
2680         val = readl(base + USB_USBCMD);
2681         val &= ~USB_USBCMD_RS;
2682         writel(val, base + USB_USBCMD);
2683         phy->bus_reseting = true;
2684
2685         return 0;
2686 }
2687
2688 static int ulpi_null_phy_restore(struct tegra_usb_phy *phy)
2689 {
2690         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2691         unsigned long timeout;
2692         int ulpi_stp = ULPI_STP;
2693
2694         if (gpio_is_valid(config->phy_restore_gpio))
2695                 ulpi_stp = config->phy_restore_gpio;
2696
2697         /* disable ULPI pinmux bypass */
2698         ulpi_pinmux_bypass(phy, false);
2699
2700         /* driving linstate by GPIO */
2701         gpio_set_value(ULPI_D0, 0);
2702         gpio_set_value(ULPI_D1, 0);
2703
2704         /* driving DIR high */
2705         gpio_set_value(ULPI_DIR, 1);
2706
2707         /* remove ULPI tristate */
2708         ulpi_null_phy_set_tristate(false);
2709
2710         /* wait for STP high */
2711         timeout = jiffies + msecs_to_jiffies(25);
2712
2713         while (!gpio_get_value(ulpi_stp)) {
2714                 if (time_after(jiffies, timeout)) {
2715                         pr_warn("phy restore timeout\n");
2716                         return 1;
2717                 }
2718         }
2719
2720         return 0;
2721 }
2722
2723 static int ulpi_null_phy_lp0_resume(struct tegra_usb_phy *phy)
2724 {
2725         unsigned long val;
2726         void __iomem *base = phy->regs;
2727
2728         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2729         ulpi_null_phy_init(phy);
2730
2731         val = readl(base + USB_USBCMD);
2732         val |= USB_CMD_RESET;
2733         writel(val, base + USB_USBCMD);
2734
2735         if (usb_phy_reg_status_wait(base + USB_USBCMD,
2736                 USB_CMD_RESET, 0, 2500) < 0) {
2737                 pr_err("%s: timeout waiting for reset\n", __func__);
2738         }
2739
2740         ulpi_null_phy_cmd_reset(phy);
2741
2742         val = readl(base + USB_USBCMD);
2743         val |= USB_USBCMD_RS;
2744         writel(val, base + USB_USBCMD);
2745         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2746                                                  USB_USBCMD_RS, 2000)) {
2747                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2748                 return -ETIMEDOUT;
2749         }
2750
2751         /* Enable Port Power */
2752         val = readl(base + USB_PORTSC);
2753         val |= USB_PORTSC_PP;
2754         writel(val, base + USB_PORTSC);
2755         udelay(10);
2756
2757         ulpi_null_phy_restore(phy);
2758
2759         return 0;
2760 }
2761
2762 static int ulpi_null_phy_power_on(struct tegra_usb_phy *phy)
2763 {
2764         unsigned long val;
2765         void __iomem *base = phy->regs;
2766         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2767
2768         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2769         if (phy->phy_clk_on) {
2770                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
2771                                                         __LINE__, phy->inst);
2772                 return 0;
2773         }
2774         reset_utmip_uhsic(base);
2775
2776         /* remove ULPI PADS CLKEN reset */
2777         val = readl(base + USB_SUSP_CTRL);
2778         val &= ~ULPI_PADS_CLKEN_RESET;
2779         writel(val, base + USB_SUSP_CTRL);
2780         udelay(10);
2781
2782         val = readl(base + ULPI_TIMING_CTRL_0);
2783         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
2784         writel(val, base + ULPI_TIMING_CTRL_0);
2785
2786         val = readl(base + USB_SUSP_CTRL);
2787         val |= ULPI_PHY_ENABLE;
2788         writel(val, base + USB_SUSP_CTRL);
2789         udelay(10);
2790
2791         /* set timming parameters */
2792         val = readl(base + ULPI_TIMING_CTRL_0);
2793         val |= ULPI_SHADOW_CLK_LOOPBACK_EN;
2794         val &= ~ULPI_SHADOW_CLK_SEL;
2795         val &= ~ULPI_LBK_PAD_EN;
2796         val |= ULPI_SHADOW_CLK_DELAY(config->shadow_clk_delay);
2797         val |= ULPI_CLOCK_OUT_DELAY(config->clock_out_delay);
2798         val |= ULPI_LBK_PAD_E_INPUT_OR;
2799         writel(val, base + ULPI_TIMING_CTRL_0);
2800
2801         writel(0, base + ULPI_TIMING_CTRL_1);
2802         udelay(10);
2803
2804         /* start internal 60MHz clock */
2805         val = readl(base + ULPIS2S_CTRL);
2806         val |= ULPIS2S_ENA;
2807         val |= ULPIS2S_SUPPORT_DISCONNECT;
2808         val |= ULPIS2S_SPARE((phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) ? 3 : 1);
2809         val |= ULPIS2S_PLLU_MASTER_BLASTER60;
2810         writel(val, base + ULPIS2S_CTRL);
2811
2812         /* select ULPI_CORE_CLK_SEL to SHADOW_CLK */
2813         val = readl(base + ULPI_TIMING_CTRL_0);
2814         val |= ULPI_CORE_CLK_SEL;
2815         writel(val, base + ULPI_TIMING_CTRL_0);
2816         udelay(10);
2817
2818         /* enable ULPI null phy clock - can't set the trimmers before this */
2819         val = readl(base + ULPI_TIMING_CTRL_0);
2820         val |= ULPI_CLK_OUT_ENA;
2821         writel(val, base + ULPI_TIMING_CTRL_0);
2822         udelay(10);
2823
2824         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
2825                                                  USB_PHY_CLK_VALID, 2500)) {
2826                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2827                 return -ETIMEDOUT;
2828         }
2829
2830         /* set ULPI trimmers */
2831         ulpi_set_trimmer(phy);
2832
2833         ulpi_set_host(base);
2834
2835         /* remove slave0 reset */
2836         val = readl(base + USB_SUSP_CTRL);
2837         val &= ~ULPIS2S_SLV0_RESET;
2838         writel(val, base + USB_SUSP_CTRL);
2839
2840         /* remove slave1 and line reset */
2841         val = readl(base + USB_SUSP_CTRL);
2842         val &= ~ULPIS2S_SLV1_RESET;
2843         val &= ~ULPIS2S_LINE_RESET;
2844
2845         /* remove ULPI PADS reset */
2846         val &= ~ULPI_PADS_RESET;
2847         writel(val, base + USB_SUSP_CTRL);
2848
2849         if (!phy->ulpi_clk_padout_ena) {
2850                 val = readl(base + ULPI_TIMING_CTRL_0);
2851                 val |= ULPI_CLK_PADOUT_ENA;
2852                 writel(val, base + ULPI_TIMING_CTRL_0);
2853                 phy->ulpi_clk_padout_ena = true;
2854         } else {
2855                 if (!readl(base + USB_ASYNCLISTADDR))
2856                         ulpi_null_phy_lp0_resume(phy);
2857         }
2858         udelay(10);
2859
2860         phy->bus_reseting = false;
2861         phy->phy_clk_on = true;
2862         phy->hw_accessible = true;
2863
2864         return 0;
2865 }
2866
2867 static int ulpi_null_phy_pre_resume(struct tegra_usb_phy *phy,
2868                                     bool remote_wakeup)
2869 {
2870         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2871         ulpi_null_phy_obs_read();
2872         usb_phy_wait_for_sof(phy);
2873         ulpi_null_phy_obs_read();
2874         return 0;
2875 }
2876
2877 static int ulpi_null_phy_post_resume(struct tegra_usb_phy *phy)
2878 {
2879         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2880         ulpi_null_phy_obs_read();
2881         return 0;
2882 }
2883
2884 static int ulpi_null_phy_resume(struct tegra_usb_phy *phy)
2885 {
2886         unsigned long val;
2887         void __iomem *base = phy->regs;
2888
2889         if (!readl(base + USB_ASYNCLISTADDR)) {
2890                 /* enable ULPI CLK output pad */
2891                 val = readl(base + ULPI_TIMING_CTRL_0);
2892                 val |= ULPI_CLK_PADOUT_ENA;
2893                 writel(val, base + ULPI_TIMING_CTRL_0);
2894
2895                 /* enable ULPI pinmux bypass */
2896                 ulpi_pinmux_bypass(phy, true);
2897                 udelay(5);
2898 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2899                 /* remove DIR tristate */
2900                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR,
2901                                           TEGRA_TRI_NORMAL);
2902 #endif
2903         }
2904         return 0;
2905 }
2906
2907
2908
2909 static struct tegra_usb_phy_ops utmi_phy_ops = {
2910         .open           = utmi_phy_open,
2911         .close          = utmi_phy_close,
2912         .irq            = utmi_phy_irq,
2913         .power_on       = utmi_phy_power_on,
2914         .power_off      = utmi_phy_power_off,
2915         .pre_resume = utmi_phy_pre_resume,
2916         .resume = utmi_phy_resume,
2917         .post_resume    = utmi_phy_post_resume,
2918         .charger_detect = utmi_phy_charger_detect,
2919 };
2920
2921 static struct tegra_usb_phy_ops uhsic_phy_ops = {
2922         .open           = uhsic_phy_open,
2923         .close          = uhsic_phy_close,
2924         .irq            = uhsic_phy_irq,
2925         .power_on       = uhsic_phy_power_on,
2926         .power_off      = uhsic_phy_power_off,
2927         .pre_resume = uhsic_phy_pre_resume,
2928         .resume = uhsic_phy_resume,
2929         .post_resume = uhsic_phy_post_resume,
2930         .port_power = uhsic_phy_bus_port_power,
2931         .bus_reset      = uhsic_phy_bus_reset,
2932 };
2933
2934 static struct tegra_usb_phy_ops ulpi_null_phy_ops = {
2935         .open           = ulpi_null_phy_open,
2936         .close          = ulpi_null_phy_close,
2937         .init           = ulpi_null_phy_init,
2938         .irq            = ulpi_null_phy_irq,
2939         .power_on       = ulpi_null_phy_power_on,
2940         .power_off      = ulpi_null_phy_power_off,
2941         .pre_resume = ulpi_null_phy_pre_resume,
2942         .resume = ulpi_null_phy_resume,
2943         .post_resume = ulpi_null_phy_post_resume,
2944         .reset          = ulpi_null_phy_cmd_reset,
2945         .bus_reset      = ulpi_phy_bus_reset,
2946 };
2947
2948 static struct tegra_usb_phy_ops ulpi_link_phy_ops;
2949 static struct tegra_usb_phy_ops icusb_phy_ops;
2950
2951 static struct tegra_usb_phy_ops *phy_ops[] = {
2952         [TEGRA_USB_PHY_INTF_UTMI] = &utmi_phy_ops,
2953         [TEGRA_USB_PHY_INTF_ULPI_LINK] = &ulpi_link_phy_ops,
2954         [TEGRA_USB_PHY_INTF_ULPI_NULL] = &ulpi_null_phy_ops,
2955         [TEGRA_USB_PHY_INTF_HSIC] = &uhsic_phy_ops,
2956         [TEGRA_USB_PHY_INTF_ICUSB] = &icusb_phy_ops,
2957 };
2958
2959 int tegra3_usb_phy_init_ops(struct tegra_usb_phy *phy)
2960 {
2961         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2962
2963         phy->ops = phy_ops[phy->pdata->phy_intf];
2964
2965         /* FIXME: uncommenting below line to make USB host mode fail*/
2966         /* usb_phy_power_down_pmc(); */
2967
2968         return 0;
2969 }