arm: tegra: phy: enable wakeup event for usb phy
[linux-2.6.git] / arch / arm / mach-tegra / tegra3_usb_phy.c
1 /*
2  * arch/arm/mach-tegra/tegra3_usb_phy.c
3  *
4  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
5  *
6  *
7  * This software is licensed under the terms of the GNU General Public
8  * License version 2, as published by the Free Software Foundation, and
9  * may be copied, distributed, and modified under those terms.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17 #include <linux/resource.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/slab.h>
21 #include <linux/err.h>
22 #include <linux/platform_device.h>
23 #include <linux/io.h>
24 #include <linux/gpio.h>
25 #include <linux/interrupt.h>
26 #include <linux/clk.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <mach/clk.h>
30 #include <mach/iomap.h>
31 #include <mach/pinmux.h>
32 #include <mach/pinmux-tegra30.h>
33 #include "tegra_usb_phy.h"
34 #include "gpio-names.h"
35 #include "fuse.h"
36
37 #define USB_USBCMD              0x130
38 #define   USB_USBCMD_RS         (1 << 0)
39 #define   USB_CMD_RESET (1<<1)
40
41 #define USB_USBSTS              0x134
42 #define   USB_USBSTS_PCI        (1 << 2)
43 #define   USB_USBSTS_SRI        (1 << 7)
44 #define   USB_USBSTS_HCH        (1 << 12)
45
46 #define USB_USBINTR             0x138
47
48 #define USB_TXFILLTUNING        0x154
49 #define USB_FIFO_TXFILL_THRES(x)   (((x) & 0x1f) << 16)
50 #define USB_FIFO_TXFILL_MASK    0x1f0000
51
52 #define USB_ASYNCLISTADDR       0x148
53
54 #define ICUSB_CTRL              0x15c
55
56 #define USB_PORTSC              0x174
57 #define   USB_PORTSC_WKOC       (1 << 22)
58 #define   USB_PORTSC_WKDS       (1 << 21)
59 #define   USB_PORTSC_WKCN       (1 << 20)
60 #define   USB_PORTSC_PTC(x)     (((x) & 0xf) << 16)
61 #define   USB_PORTSC_PP (1 << 12)
62 #define   USB_PORTSC_LS(x) (((x) & 0x3) << 10)
63 #define   USB_PORTSC_SUSP       (1 << 7)
64 #define   USB_PORTSC_RESUME     (1 << 6)
65 #define   USB_PORTSC_OCC        (1 << 5)
66 #define   USB_PORTSC_PEC        (1 << 3)
67 #define   USB_PORTSC_PE         (1 << 2)
68 #define   USB_PORTSC_CSC        (1 << 1)
69 #define   USB_PORTSC_CCS        (1 << 0)
70 #define   USB_PORTSC_RWC_BITS (USB_PORTSC_CSC | USB_PORTSC_PEC | USB_PORTSC_OCC)
71
72 #define HOSTPC1_DEVLC           0x1b4
73 #define   HOSTPC1_DEVLC_PHCD            (1 << 22)
74 #define   HOSTPC1_DEVLC_PTS(x)          (((x) & 0x7) << 29)
75 #define   HOSTPC1_DEVLC_PTS_MASK        7
76 #define   HOSTPC1_DEVLC_PTS_HSIC        4
77 #define   HOSTPC1_DEVLC_STS             (1 << 28)
78 #define   HOSTPC1_DEVLC_PSPD(x)         (((x) & 0x3) << 25)
79 #define   HOSTPC1_DEVLC_PSPD_MASK       3
80 #define   HOSTPC1_DEVLC_PSPD_HIGH_SPEED 2
81
82 #define USB_USBMODE             0x1f8
83 #define   USB_USBMODE_MASK              (3 << 0)
84 #define   USB_USBMODE_HOST              (3 << 0)
85 #define   USB_USBMODE_DEVICE            (2 << 0)
86
87 #define USB_SUSP_CTRL           0x400
88 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
89 #define   USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
90 #define   USB_SUSP_CLR                  (1 << 5)
91 #define   USB_PHY_CLK_VALID             (1 << 7)
92 #define   USB_PHY_CLK_VALID_INT_ENB     (1 << 9)
93 #define   USB_PHY_CLK_VALID_INT_STS     (1 << 8)
94 #define   UTMIP_RESET                   (1 << 11)
95 #define   UTMIP_PHY_ENABLE              (1 << 12)
96 #define   ULPI_PHY_ENABLE               (1 << 13)
97 #define   UHSIC_RESET                   (1 << 14)
98 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
99 #define   UHSIC_PHY_ENABLE              (1 << 19)
100 #define   ULPIS2S_SLV0_RESET            (1 << 20)
101 #define   ULPIS2S_SLV1_RESET            (1 << 21)
102 #define   ULPIS2S_LINE_RESET            (1 << 22)
103 #define   ULPI_PADS_RESET               (1 << 23)
104 #define   ULPI_PADS_CLKEN_RESET         (1 << 24)
105
106 #define USB_PHY_VBUS_WAKEUP_ID  0x408
107 #define   VDAT_DET_INT_EN       (1 << 16)
108 #define   VDAT_DET_CHG_DET      (1 << 17)
109 #define   VDAT_DET_STS          (1 << 18)
110 #define   USB_ID_STATUS         (1 << 2)
111
112 #define ULPIS2S_CTRL            0x418
113 #define   ULPIS2S_ENA                   (1 << 0)
114 #define   ULPIS2S_SUPPORT_DISCONNECT    (1 << 2)
115 #define   ULPIS2S_PLLU_MASTER_BLASTER60 (1 << 3)
116 #define   ULPIS2S_SPARE(x)              (((x) & 0xF) << 8)
117 #define   ULPIS2S_FORCE_ULPI_CLK_OUT    (1 << 12)
118 #define   ULPIS2S_DISCON_DONT_CHECK_SE0 (1 << 13)
119 #define   ULPIS2S_SUPPORT_HS_KEEP_ALIVE (1 << 14)
120 #define   ULPIS2S_DISABLE_STP_PU        (1 << 15)
121 #define   ULPIS2S_SLV0_CLAMP_XMIT       (1 << 16)
122
123 #define ULPI_TIMING_CTRL_0      0x424
124 #define   ULPI_CLOCK_OUT_DELAY(x)       ((x) & 0x1F)
125 #define   ULPI_OUTPUT_PINMUX_BYP        (1 << 10)
126 #define   ULPI_CLKOUT_PINMUX_BYP        (1 << 11)
127 #define   ULPI_SHADOW_CLK_LOOPBACK_EN   (1 << 12)
128 #define   ULPI_SHADOW_CLK_SEL           (1 << 13)
129 #define   ULPI_CORE_CLK_SEL             (1 << 14)
130 #define   ULPI_SHADOW_CLK_DELAY(x)      (((x) & 0x1F) << 16)
131 #define   ULPI_LBK_PAD_EN               (1 << 26)
132 #define   ULPI_LBK_PAD_E_INPUT_OR       (1 << 27)
133 #define   ULPI_CLK_OUT_ENA              (1 << 28)
134 #define   ULPI_CLK_PADOUT_ENA           (1 << 29)
135
136 #define ULPI_TIMING_CTRL_1      0x428
137 #define   ULPI_DATA_TRIMMER_LOAD        (1 << 0)
138 #define   ULPI_DATA_TRIMMER_SEL(x)      (((x) & 0x7) << 1)
139 #define   ULPI_STPDIRNXT_TRIMMER_LOAD   (1 << 16)
140 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
141 #define   ULPI_DIR_TRIMMER_LOAD         (1 << 24)
142 #define   ULPI_DIR_TRIMMER_SEL(x)       (((x) & 0x7) << 25)
143
144 #define UTMIP_XCVR_CFG0         0x808
145 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
146 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
147 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
148 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
149 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
150 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
151 #define   UTMIP_XCVR_LSBIAS_SEL                 (1 << 21)
152 #define   UTMIP_XCVR_SETUP_MSB(x)               (((x) & 0x7) << 22)
153 #define   UTMIP_XCVR_HSSLEW_MSB(x)              (((x) & 0x7f) << 25)
154 #define   UTMIP_XCVR_MAX_OFFSET         2
155 #define   UTMIP_XCVR_SETUP_MAX_VALUE    0x7f
156 #define   UTMIP_XCVR_SETUP_MIN_VALUE    0
157 #define   XCVR_SETUP_MSB_CALIB(x) ((x) >> 4)
158
159 #define UTMIP_BIAS_CFG0         0x80c
160 #define   UTMIP_OTGPD                   (1 << 11)
161 #define   UTMIP_BIASPD                  (1 << 10)
162 #define   UTMIP_HSSQUELCH_LEVEL(x)      (((x) & 0x3) << 0)
163 #define   UTMIP_HSDISCON_LEVEL(x)       (((x) & 0x3) << 2)
164 #define   UTMIP_HSDISCON_LEVEL_MSB      (1 << 24)
165
166 #define UTMIP_HSRX_CFG0         0x810
167 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
168 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
169
170 #define UTMIP_HSRX_CFG1         0x814
171 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
172
173 #define UTMIP_TX_CFG0           0x820
174 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
175 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
176
177 #define UTMIP_DEBOUNCE_CFG0 0x82c
178 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
179
180 #define UTMIP_BAT_CHRG_CFG0 0x830
181 #define   UTMIP_PD_CHRG                 (1 << 0)
182 #define   UTMIP_ON_SINK_EN              (1 << 2)
183 #define   UTMIP_OP_SRC_EN               (1 << 3)
184
185 #define UTMIP_XCVR_CFG1         0x838
186 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
187 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
188 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
189 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
190
191 #define UTMIP_BIAS_CFG1         0x83c
192 #define   UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
193 #define   UTMIP_BIAS_PDTRK_POWERDOWN    (1 << 0)
194 #define   UTMIP_BIAS_PDTRK_POWERUP      (1 << 1)
195
196 #define UTMIP_MISC_CFG0         0x824
197 #define   UTMIP_DPDM_OBSERVE            (1 << 26)
198 #define   UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
199 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J   UTMIP_DPDM_OBSERVE_SEL(0xf)
200 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K   UTMIP_DPDM_OBSERVE_SEL(0xe)
201 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
202 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
203 #define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
204 #define   FORCE_PULLDN_DM       (1 << 8)
205 #define   FORCE_PULLDN_DP       (1 << 9)
206 #define   COMB_TERMS            (1 << 0)
207 #define   ALWAYS_FREE_RUNNING_TERMS (1 << 1)
208
209 #define UTMIP_SPARE_CFG0        0x834
210 #define   FUSE_SETUP_SEL                (1 << 3)
211 #define   FUSE_ATERM_SEL                (1 << 4)
212
213 #define UTMIP_PMC_WAKEUP0               0x84c
214 #define   EVENT_INT_ENB                 (1 << 0)
215
216 #define UHSIC_PMC_WAKEUP0               0xc34
217
218 #define UTMIP_BIAS_STS0                 0x840
219 #define   UTMIP_RCTRL_VAL(x)            (((x) & 0xffff) << 0)
220 #define   UTMIP_TCTRL_VAL(x)            (((x) & (0xffff << 16)) >> 16)
221
222 #define UHSIC_PLL_CFG1                          0xc04
223 #define   UHSIC_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
224 #define   UHSIC_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 14)
225
226 #define UHSIC_HSRX_CFG0                         0xc08
227 #define   UHSIC_ELASTIC_UNDERRUN_LIMIT(x)       (((x) & 0x1f) << 2)
228 #define   UHSIC_ELASTIC_OVERRUN_LIMIT(x)        (((x) & 0x1f) << 8)
229 #define   UHSIC_IDLE_WAIT(x)                    (((x) & 0x1f) << 13)
230
231 #define UHSIC_HSRX_CFG1                         0xc0c
232 #define   UHSIC_HS_SYNC_START_DLY(x)            (((x) & 0x1f) << 1)
233
234 #define UHSIC_TX_CFG0                           0xc10
235 #define UHSIC_HS_READY_WAIT_FOR_VALID   (1 << 9)
236 #define UHSIC_MISC_CFG0                         0xc14
237 #define   UHSIC_SUSPEND_EXIT_ON_EDGE            (1 << 7)
238 #define   UHSIC_DETECT_SHORT_CONNECT            (1 << 8)
239 #define   UHSIC_FORCE_XCVR_MODE                 (1 << 15)
240 #define   UHSIC_DISABLE_BUSRESET                (1 << 20)
241 #define UHSIC_MISC_CFG1                         0xc18
242 #define   UHSIC_PLLU_STABLE_COUNT(x)            (((x) & 0xfff) << 2)
243
244 #define UHSIC_PADS_CFG0                         0xc1c
245 #define   UHSIC_TX_RTUNEN                       0xf000
246 #define   UHSIC_TX_RTUNE(x)                     (((x) & 0xf) << 12)
247
248 #define UHSIC_PADS_CFG1                         0xc20
249 #define   UHSIC_PD_BG                           (1 << 2)
250 #define   UHSIC_PD_TX                           (1 << 3)
251 #define   UHSIC_PD_TRK                          (1 << 4)
252 #define   UHSIC_PD_RX                           (1 << 5)
253 #define   UHSIC_PD_ZI                           (1 << 6)
254 #define   UHSIC_RX_SEL                          (1 << 7)
255 #define   UHSIC_RPD_DATA                        (1 << 9)
256 #define   UHSIC_RPD_STROBE                      (1 << 10)
257 #define   UHSIC_RPU_DATA                        (1 << 11)
258 #define   UHSIC_RPU_STROBE                      (1 << 12)
259
260 #define UHSIC_CMD_CFG0                  0xc24
261 #define UHSIC_PRETEND_CONNECT_DETECT    (1 << 5)
262
263 #define UHSIC_STAT_CFG0         0xc28
264 #define UHSIC_CONNECT_DETECT            (1 << 0)
265
266 #define PMC_USB_DEBOUNCE                        0xec
267 #define UTMIP_LINE_DEB_CNT(x)           (((x) & 0xf) << 16)
268 #define UHSIC_LINE_DEB_CNT(x)           (((x) & 0xf) << 20)
269
270 #define PMC_USB_AO                              0xf0
271
272 #define PMC_POWER_DOWN_MASK                     0xffff
273 #define HSIC_RESERVED_P0                        (3 << 14)
274 #define STROBE_VAL_PD_P0                        (1 << 12)
275 #define DATA_VAL_PD_P0                          (1 << 13)
276
277 #define USB_ID_PD(inst)                 (1 << ((4*(inst))+3))
278 #define VBUS_WAKEUP_PD(inst)                    (1 << ((4*(inst))+2))
279 #define   USBON_VAL_PD(inst)                    (1 << ((4*(inst))+1))
280 #define   USBON_VAL_PD_P2                       (1 << 9)
281 #define   USBON_VAL_PD_P1                       (1 << 5)
282 #define   USBON_VAL_PD_P0                       (1 << 1)
283 #define   USBOP_VAL_PD(inst)                    (1 << (4*(inst)))
284 #define   USBOP_VAL_PD_P2                       (1 << 8)
285 #define   USBOP_VAL_PD_P1                       (1 << 4)
286 #define   USBOP_VAL_PD_P0                       (1 << 0)
287 #define   PMC_USB_AO_PD_P2                      (0xf << 8)
288 #define   PMC_USB_AO_ID_PD_P0                   (1 << 3)
289 #define   PMC_USB_AO_VBUS_WAKEUP_PD_P0  (1 << 2)
290
291 #define PMC_TRIGGERS                    0x1ec
292
293 #define   UHSIC_CLR_WALK_PTR_P0         (1 << 3)
294 #define   UTMIP_CLR_WALK_PTR(inst)      (1 << (inst))
295 #define   UTMIP_CLR_WALK_PTR_P2         (1 << 2)
296 #define   UTMIP_CLR_WALK_PTR_P1         (1 << 1)
297 #define   UTMIP_CLR_WALK_PTR_P0         (1 << 0)
298 #define   UTMIP_CAP_CFG(inst)   (1 << ((inst)+4))
299 #define   UTMIP_CAP_CFG_P2              (1 << 6)
300 #define   UTMIP_CAP_CFG_P1              (1 << 5)
301 #define   UTMIP_CAP_CFG_P0              (1 << 4)
302 #define   UTMIP_CLR_WAKE_ALARM(inst)    (1 << ((inst)+12))
303 #define   UHSIC_CLR_WAKE_ALARM_P0       (1 << 15)
304 #define   UTMIP_CLR_WAKE_ALARM_P2       (1 << 14)
305
306 #define PMC_PAD_CFG             (0x1f4)
307
308 #define PMC_UTMIP_TERM_PAD_CFG  0x1f8
309 #define   PMC_TCTRL_VAL(x)      (((x) & 0x1f) << 5)
310 #define   PMC_RCTRL_VAL(x)      (((x) & 0x1f) << 0)
311
312 #define PMC_SLEEP_CFG                   0x1fc
313
314 #define   UHSIC_MASTER_ENABLE                   (1 << 24)
315 #define   UHSIC_WAKE_VAL(x)             (((x) & 0xf) << 28)
316 #define   WAKE_VAL_SD10                 0x2
317 #define   UTMIP_TCTRL_USE_PMC(inst) (1 << ((8*(inst))+3))
318 #define   UTMIP_TCTRL_USE_PMC_P2                (1 << 19)
319 #define   UTMIP_TCTRL_USE_PMC_P1                (1 << 11)
320 #define   UTMIP_TCTRL_USE_PMC_P0                (1 << 3)
321 #define   UTMIP_RCTRL_USE_PMC(inst) (1 << ((8*(inst))+2))
322 #define   UTMIP_RCTRL_USE_PMC_P2                (1 << 18)
323 #define   UTMIP_RCTRL_USE_PMC_P1                (1 << 10)
324 #define   UTMIP_RCTRL_USE_PMC_P0                (1 << 2)
325 #define   UTMIP_FSLS_USE_PMC(inst)      (1 << ((8*(inst))+1))
326 #define   UTMIP_FSLS_USE_PMC_P2         (1 << 17)
327 #define   UTMIP_FSLS_USE_PMC_P1         (1 << 9)
328 #define   UTMIP_FSLS_USE_PMC_P0         (1 << 1)
329 #define   UTMIP_MASTER_ENABLE(inst) (1 << (8*(inst)))
330 #define   UTMIP_MASTER_ENABLE_P2                (1 << 16)
331 #define   UTMIP_MASTER_ENABLE_P1                (1 << 8)
332 #define   UTMIP_MASTER_ENABLE_P0                (1 << 0)
333 #define UHSIC_MASTER_ENABLE_P0          (1 << 24)
334 #define UHSIC_WAKE_VAL_P0(x)            (((x) & 0xf) << 28)
335
336 #define PMC_SLEEPWALK_CFG               0x200
337
338 #define   UHSIC_WAKE_WALK_EN_P0 (1 << 30)
339 #define   UHSIC_LINEVAL_WALK_EN (1 << 31)
340 #define   UTMIP_LINEVAL_WALK_EN(inst) (1 << ((8*(inst))+7))
341 #define   UTMIP_LINEVAL_WALK_EN_P2      (1 << 23)
342 #define   UTMIP_LINEVAL_WALK_EN_P1      (1 << 15)
343 #define   UTMIP_LINEVAL_WALK_EN_P0      (1 << 7)
344 #define   UTMIP_WAKE_VAL(inst, x) (((x) & 0xf) << ((8*(inst))+4))
345 #define   UTMIP_WAKE_VAL_P2(x)          (((x) & 0xf) << 20)
346 #define   UTMIP_WAKE_VAL_P1(x)          (((x) & 0xf) << 12)
347 #define   UTMIP_WAKE_VAL_P0(x)          (((x) & 0xf) << 4)
348 #define   WAKE_VAL_NONE         0xc
349 #define   WAKE_VAL_ANY                  0xF
350 #define   WAKE_VAL_FSJ                  0x2
351 #define   WAKE_VAL_FSK                  0x1
352 #define   WAKE_VAL_SE0                  0x0
353
354 #define PMC_SLEEPWALK_REG(inst)         (0x204 + (4*(inst)))
355 #define   UTMIP_USBOP_RPD_A     (1 << 0)
356 #define   UTMIP_USBON_RPD_A     (1 << 1)
357 #define   UTMIP_AP_A                    (1 << 4)
358 #define   UTMIP_AN_A                    (1 << 5)
359 #define   UTMIP_HIGHZ_A         (1 << 6)
360 #define   UTMIP_USBOP_RPD_B     (1 << 8)
361 #define   UTMIP_USBON_RPD_B     (1 << 9)
362 #define   UTMIP_AP_B                    (1 << 12)
363 #define   UTMIP_AN_B                    (1 << 13)
364 #define   UTMIP_HIGHZ_B         (1 << 14)
365 #define   UTMIP_USBOP_RPD_C     (1 << 16)
366 #define   UTMIP_USBON_RPD_C     (1 << 17)
367 #define   UTMIP_AP_C            (1 << 20)
368 #define   UTMIP_AN_C            (1 << 21)
369 #define   UTMIP_HIGHZ_C         (1 << 22)
370 #define   UTMIP_USBOP_RPD_D     (1 << 24)
371 #define   UTMIP_USBON_RPD_D     (1 << 25)
372 #define   UTMIP_AP_D            (1 << 28)
373 #define   UTMIP_AN_D            (1 << 29)
374 #define   UTMIP_HIGHZ_D         (1 << 30)
375
376 #define PMC_SLEEPWALK_UHSIC             0x210
377
378 #define UHSIC_STROBE_RPD_A              (1 << 0)
379 #define UHSIC_DATA_RPD_A                (1 << 1)
380 #define UHSIC_STROBE_RPU_A              (1 << 2)
381 #define UHSIC_DATA_RPU_A                (1 << 3)
382 #define UHSIC_STROBE_RPD_B              (1 << 8)
383 #define UHSIC_DATA_RPD_B                (1 << 9)
384 #define UHSIC_STROBE_RPU_B              (1 << 10)
385 #define UHSIC_DATA_RPU_B                (1 << 11)
386 #define UHSIC_STROBE_RPD_C              (1 << 16)
387 #define UHSIC_DATA_RPD_C                (1 << 17)
388 #define UHSIC_STROBE_RPU_C              (1 << 18)
389 #define UHSIC_DATA_RPU_C                (1 << 19)
390 #define UHSIC_STROBE_RPD_D              (1 << 24)
391 #define UHSIC_DATA_RPD_D                (1 << 25)
392 #define UHSIC_STROBE_RPU_D              (1 << 26)
393 #define UHSIC_DATA_RPU_D                (1 << 27)
394
395 #define UTMIP_UHSIC_STATUS              0x214
396
397 #define UTMIP_USBOP_VAL(inst)           (1 << ((2*(inst)) + 8))
398 #define UTMIP_USBOP_VAL_P2              (1 << 12)
399 #define UTMIP_USBOP_VAL_P1              (1 << 10)
400 #define UTMIP_USBOP_VAL_P0              (1 << 8)
401 #define UTMIP_USBON_VAL(inst)           (1 << ((2*(inst)) + 9))
402 #define UTMIP_USBON_VAL_P2              (1 << 13)
403 #define UTMIP_USBON_VAL_P1              (1 << 11)
404 #define UTMIP_USBON_VAL_P0              (1 << 9)
405 #define UHSIC_WAKE_ALARM                (1 << 19)
406 #define UTMIP_WAKE_ALARM(inst)          (1 << ((inst) + 16))
407 #define UTMIP_WAKE_ALARM_P2             (1 << 18)
408 #define UTMIP_WAKE_ALARM_P1             (1 << 17)
409 #define UTMIP_WAKE_ALARM_P0             (1 << 16)
410 #define UHSIC_DATA_VAL_P0               (1 << 15)
411 #define UHSIC_STROBE_VAL_P0             (1 << 14)
412 #define UTMIP_WALK_PTR_VAL(inst)        (0x3 << ((inst)*2))
413 #define UHSIC_WALK_PTR_VAL              (0x3 << 6)
414 #define UTMIP_WALK_PTR(inst)            (1 << ((inst)*2))
415 #define UTMIP_WALK_PTR_P2               (1 << 4)
416 #define UTMIP_WALK_PTR_P1               (1 << 2)
417 #define UTMIP_WALK_PTR_P0               (1 << 0)
418
419 #define USB1_PREFETCH_ID                           6
420 #define USB2_PREFETCH_ID                           18
421 #define USB3_PREFETCH_ID                           17
422
423 #define PMC_UTMIP_UHSIC_FAKE            0x218
424
425 #define UHSIC_STROBE_VAL                (1 << 12)
426 #define UHSIC_DATA_VAL                  (1 << 13)
427 #define UHSIC_STROBE_ENB                (1 << 14)
428 #define UHSIC_DATA_ENB                  (1 << 15)
429 #define   USBON_VAL(inst)       (1 << ((4*(inst))+1))
430 #define   USBON_VAL_P2                  (1 << 9)
431 #define   USBON_VAL_P1                  (1 << 5)
432 #define   USBON_VAL_P0                  (1 << 1)
433 #define   USBOP_VAL(inst)       (1 << (4*(inst)))
434 #define   USBOP_VAL_P2                  (1 << 8)
435 #define   USBOP_VAL_P1                  (1 << 4)
436 #define   USBOP_VAL_P0                  (1 << 0)
437
438 #define PMC_UTMIP_BIAS_MASTER_CNTRL 0x30c
439 #define   BIAS_MASTER_PROG_VAL          (1 << 1)
440
441 #define PMC_UTMIP_MASTER_CONFIG 0x310
442
443 #define UTMIP_PWR(inst)         (1 << (inst))
444 #define UHSIC_PWR                       (1 << 3)
445
446 #define FUSE_USB_CALIB_0                0x1F0
447 #define   XCVR_SETUP(x) (((x) & 0x7F) << 0)
448 #define   XCVR_SETUP_LSB_MASK   0xF
449 #define   XCVR_SETUP_MSB_MASK   0x70
450 #define   XCVR_SETUP_LSB_MAX_VAL        0xF
451
452 #define APB_MISC_GP_OBSCTRL_0   0x818
453 #define APB_MISC_GP_OBSDATA_0   0x81c
454
455 /* ULPI GPIO */
456 #define ULPI_STP        TEGRA_GPIO_PY3
457 #define ULPI_DIR        TEGRA_GPIO_PY1
458 #define ULPI_D0         TEGRA_GPIO_PO1
459 #define ULPI_D1         TEGRA_GPIO_PO2
460
461 /* These values (in milli second) are taken from the battery charging spec */
462 #define TDP_SRC_ON_MS    100
463 #define TDPSRC_CON_MS    40
464
465 #ifdef DEBUG
466 #define DBG(stuff...)   pr_info("tegra3_usb_phy: " stuff)
467 #else
468 #define DBG(stuff...)   do {} while (0)
469 #endif
470
471 #if 0
472 #define PHY_DBG(stuff...)       pr_info("tegra3_usb_phy: " stuff)
473 #else
474 #define PHY_DBG(stuff...)       do {} while (0)
475 #endif
476
477 /* define HSIC phy params */
478 #define HSIC_SYNC_START_DELAY           9
479 #define HSIC_IDLE_WAIT_DELAY            17
480 #define HSIC_ELASTIC_UNDERRUN_LIMIT     16
481 #define HSIC_ELASTIC_OVERRUN_LIMIT      16
482
483 static u32 utmip_rctrl_val, utmip_tctrl_val;
484 static DEFINE_SPINLOCK(utmip_pad_lock);
485 static int utmip_pad_count;
486
487 static struct tegra_xtal_freq utmip_freq_table[] = {
488         {
489                 .freq = 12000000,
490                 .enable_delay = 0x02,
491                 .stable_count = 0x2F,
492                 .active_delay = 0x04,
493                 .xtal_freq_count = 0x76,
494                 .debounce = 0x7530,
495                 .pdtrk_count = 5,
496         },
497         {
498                 .freq = 13000000,
499                 .enable_delay = 0x02,
500                 .stable_count = 0x33,
501                 .active_delay = 0x05,
502                 .xtal_freq_count = 0x7F,
503                 .debounce = 0x7EF4,
504                 .pdtrk_count = 5,
505         },
506         {
507                 .freq = 19200000,
508                 .enable_delay = 0x03,
509                 .stable_count = 0x4B,
510                 .active_delay = 0x06,
511                 .xtal_freq_count = 0xBB,
512                 .debounce = 0xBB80,
513                 .pdtrk_count = 7,
514         },
515         {
516                 .freq = 26000000,
517                 .enable_delay = 0x04,
518                 .stable_count = 0x66,
519                 .active_delay = 0x09,
520                 .xtal_freq_count = 0xFE,
521                 .debounce = 0xFDE8,
522                 .pdtrk_count = 9,
523         },
524 };
525
526 static struct tegra_xtal_freq uhsic_freq_table[] = {
527         {
528                 .freq = 12000000,
529                 .enable_delay = 0x02,
530                 .stable_count = 0x2F,
531                 .active_delay = 0x0,
532                 .xtal_freq_count = 0x1CA,
533         },
534         {
535                 .freq = 13000000,
536                 .enable_delay = 0x02,
537                 .stable_count = 0x33,
538                 .active_delay = 0x0,
539                 .xtal_freq_count = 0x1F0,
540         },
541         {
542                 .freq = 19200000,
543                 .enable_delay = 0x03,
544                 .stable_count = 0x4B,
545                 .active_delay = 0x0,
546                 .xtal_freq_count = 0x2DD,
547         },
548         {
549                 .freq = 26000000,
550                 .enable_delay = 0x04,
551                 .stable_count = 0x66,
552                 .active_delay = 0x0,
553                 .xtal_freq_count = 0x3E0,
554         },
555 };
556
557 static void usb_phy_fence_read(struct tegra_usb_phy *phy)
558 {
559         /* Fence read for coherency of AHB master intiated writes */
560         if (phy->inst == 0)
561                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB1_PREFETCH_ID));
562         else if (phy->inst == 1)
563                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB2_PREFETCH_ID));
564         else if (phy->inst == 2)
565                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB3_PREFETCH_ID));
566
567         return;
568 }
569
570 static void utmip_setup_pmc_wake_detect(struct tegra_usb_phy *phy)
571 {
572         unsigned long val, pmc_pad_cfg_val;
573         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
574         unsigned  int inst = phy->inst;
575         void __iomem *base = phy->regs;
576         bool port_connected;
577         enum usb_phy_port_speed port_speed;
578
579         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
580
581         /* check for port connect status */
582         val = readl(base + USB_PORTSC);
583         port_connected = val & USB_PORTSC_CCS;
584
585         if (!port_connected)
586                 return;
587
588         port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
589                 HOSTPC1_DEVLC_PSPD_MASK;
590         /*Set PMC MASTER bits to do the following
591         * a. Take over the UTMI drivers
592         * b. set up such that it will take over resume
593         *        if remote wakeup is detected
594         * Prepare PMC to take over suspend-wake detect-drive resume until USB
595         * controller ready
596         */
597
598         /* disable master enable in PMC */
599         val = readl(pmc_base + PMC_SLEEP_CFG);
600         val &= ~UTMIP_MASTER_ENABLE(inst);
601         writel(val, pmc_base + PMC_SLEEP_CFG);
602
603         /* UTMIP_PWR_PX=1 for power savings mode */
604         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
605         val |= UTMIP_PWR(inst);
606         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
607
608         /* config debouncer */
609         val = readl(pmc_base + PMC_USB_DEBOUNCE);
610         val &= ~UTMIP_LINE_DEB_CNT(~0);
611         val |= UTMIP_LINE_DEB_CNT(4);
612         writel(val, pmc_base + PMC_USB_DEBOUNCE);
613
614         /* Make sure nothing is happening on the line with respect to PMC */
615         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
616         val &= ~USBOP_VAL(inst);
617         val &= ~USBON_VAL(inst);
618         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
619
620         /* Make sure wake value for line is none */
621         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
622         val &= ~UTMIP_LINEVAL_WALK_EN(inst);
623         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
624         val = readl(pmc_base + PMC_SLEEP_CFG);
625         val &= ~UTMIP_WAKE_VAL(inst, ~0);
626         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
627         writel(val, pmc_base + PMC_SLEEP_CFG);
628
629         /* turn off pad detectors */
630         val = readl(pmc_base + PMC_USB_AO);
631         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
632         writel(val, pmc_base + PMC_USB_AO);
633
634         /* Remove fake values and make synchronizers work a bit */
635         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
636         val &= ~USBOP_VAL(inst);
637         val &= ~USBON_VAL(inst);
638         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
639
640         /* Enable which type of event can trigger a walk,
641         * in this case usb_line_wake */
642         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
643         val |= UTMIP_LINEVAL_WALK_EN(inst);
644         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
645
646         /* Capture FS/LS pad configurations */
647         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
648         val = readl(pmc_base + PMC_TRIGGERS);
649         val |= UTMIP_CAP_CFG(inst);
650         writel(val, pmc_base + PMC_TRIGGERS);
651         udelay(1);
652         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
653
654         /* BIAS MASTER_ENABLE=0 */
655         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
656         val &= ~BIAS_MASTER_PROG_VAL;
657         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
658
659         /* program walk sequence, maintain a J, followed by a driven K
660         * to signal a resume once an wake event is detected */
661         val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
662         val &= ~UTMIP_AP_A;
663         val |= UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_AN_A |UTMIP_HIGHZ_A |
664                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_AP_B | UTMIP_AN_B |
665                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_AP_C | UTMIP_AN_C |
666                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_AP_D | UTMIP_AN_D;
667         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
668
669         if (port_speed == USB_PHY_PORT_SPEED_LOW) {
670                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
671                 val &= ~(UTMIP_AN_B | UTMIP_HIGHZ_B | UTMIP_AN_C |
672                         UTMIP_HIGHZ_C | UTMIP_AN_D | UTMIP_HIGHZ_D);
673                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
674         } else {
675                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
676                 val &= ~(UTMIP_AP_B | UTMIP_HIGHZ_B | UTMIP_AP_C |
677                         UTMIP_HIGHZ_C | UTMIP_AP_D | UTMIP_HIGHZ_D);
678                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
679         }
680
681         /* turn on pad detectors */
682         val = readl(pmc_base + PMC_USB_AO);
683         val &= ~(USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
684         writel(val, pmc_base + PMC_USB_AO);
685
686         /* Add small delay before usb detectors provide stable line values */
687         mdelay(1);
688
689         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
690         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
691         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
692         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
693
694         phy->remote_wakeup = false;
695
696         /* Turn over pad configuration to PMC  for line wake events*/
697         val = readl(pmc_base + PMC_SLEEP_CFG);
698         val &= ~UTMIP_WAKE_VAL(inst, ~0);
699         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_ANY);
700         val |= UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst);
701         val |= UTMIP_MASTER_ENABLE(inst) | UTMIP_FSLS_USE_PMC(inst);
702         writel(val, pmc_base + PMC_SLEEP_CFG);
703
704         val = readl(base + UTMIP_PMC_WAKEUP0);
705         val |= EVENT_INT_ENB;
706         writel(val, base + UTMIP_PMC_WAKEUP0);
707         PHY_DBG("%s ENABLE_PMC inst = %d\n", __func__, inst);
708 }
709
710 static void utmip_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy)
711 {
712         unsigned long val;
713         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
714         unsigned  int inst = phy->inst;
715         void __iomem *base = phy->regs;
716
717         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
718
719         val = readl(pmc_base + PMC_SLEEP_CFG);
720         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
721         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
722         writel(val, pmc_base + PMC_SLEEP_CFG);
723
724         val = readl(base + UTMIP_PMC_WAKEUP0);
725         val &= ~EVENT_INT_ENB;
726         writel(val, base + UTMIP_PMC_WAKEUP0);
727
728         /* Disable PMC master mode by clearing MASTER_EN */
729         val = readl(pmc_base + PMC_SLEEP_CFG);
730         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
731                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
732         writel(val, pmc_base + PMC_SLEEP_CFG);
733
734         val = readl(pmc_base + PMC_TRIGGERS);
735         val &= ~UTMIP_CAP_CFG(inst);
736         writel(val, pmc_base + PMC_TRIGGERS);
737
738         /* turn off pad detectors */
739         val = readl(pmc_base + PMC_USB_AO);
740         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
741         writel(val, pmc_base + PMC_USB_AO);
742
743         val = readl(pmc_base + PMC_TRIGGERS);
744         val |= UTMIP_CLR_WALK_PTR(inst);
745         val |= UTMIP_CLR_WAKE_ALARM(inst);
746         writel(val, pmc_base + PMC_TRIGGERS);
747
748         phy->remote_wakeup = false;
749         PHY_DBG("%s DISABLE_PMC inst = %d\n", __func__, inst);
750 }
751
752 static bool utmi_phy_remotewake_detected(struct tegra_usb_phy *phy)
753 {
754         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
755         void __iomem *base = phy->regs;
756         unsigned  int inst = phy->inst;
757         u32 val;
758
759         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
760         val = readl(base + UTMIP_PMC_WAKEUP0);
761         if (val & EVENT_INT_ENB) {
762                 val = readl(pmc_base + UTMIP_UHSIC_STATUS);
763                 if (UTMIP_WAKE_ALARM(inst) & val) {
764                         val = readl(pmc_base + PMC_SLEEP_CFG);
765                         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
766                         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
767                         writel(val, pmc_base + PMC_SLEEP_CFG);
768
769                         val = readl(pmc_base + PMC_TRIGGERS);
770                         val |= UTMIP_CLR_WAKE_ALARM(inst);
771                         writel(val, pmc_base + PMC_TRIGGERS);
772
773                         val = readl(base + UTMIP_PMC_WAKEUP0);
774                         val &= ~EVENT_INT_ENB;
775                         writel(val, base + UTMIP_PMC_WAKEUP0);
776                         phy->remote_wakeup = true;
777                         return true;
778                 }
779         }
780         return false;
781 }
782
783 static void utmi_phy_enable_trking_data(struct tegra_usb_phy *phy)
784 {
785         void __iomem *base = IO_ADDRESS(TEGRA_USB_BASE);
786         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
787         static bool init_done = false;
788         u32 val;
789
790         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
791
792         /* Should be done only once after system boot */
793         if (init_done)
794                 return;
795
796         clk_enable(phy->utmi_pad_clk);
797         /* Bias pad MASTER_ENABLE=1 */
798         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
799         val |= BIAS_MASTER_PROG_VAL;
800         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
801
802         /* Setting the tracking length time */
803         val = readl(base + UTMIP_BIAS_CFG1);
804         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
805         val |= UTMIP_BIAS_PDTRK_COUNT(5);
806         writel(val, base + UTMIP_BIAS_CFG1);
807
808         /* Bias PDTRK is Shared and MUST be done from USB1 ONLY, PD_TRK=0 */
809         val = readl(base + UTMIP_BIAS_CFG1);
810         val &= ~UTMIP_BIAS_PDTRK_POWERDOWN;
811         writel(val, base + UTMIP_BIAS_CFG1);
812
813         val = readl(base + UTMIP_BIAS_CFG1);
814         val |= UTMIP_BIAS_PDTRK_POWERUP;
815         writel(val, base + UTMIP_BIAS_CFG1);
816
817         /* Wait for 25usec */
818         udelay(25);
819
820         /* Bias pad MASTER_ENABLE=0 */
821         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
822         val &= ~BIAS_MASTER_PROG_VAL;
823         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
824
825         /* Wait for 1usec */
826         udelay(1);
827
828         /* Bias pad MASTER_ENABLE=1 */
829         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
830         val |= BIAS_MASTER_PROG_VAL;
831         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
832
833         /* Read RCTRL and TCTRL from UTMIP space */
834         val = readl(base + UTMIP_BIAS_STS0);
835         utmip_rctrl_val = ffz(UTMIP_RCTRL_VAL(val));
836         utmip_tctrl_val = ffz(UTMIP_TCTRL_VAL(val));
837
838         /* PD_TRK=1 */
839         val = readl(base + UTMIP_BIAS_CFG1);
840         val |= UTMIP_BIAS_PDTRK_POWERDOWN;
841         writel(val, base + UTMIP_BIAS_CFG1);
842
843         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
844         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
845         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
846         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
847         clk_disable(phy->utmi_pad_clk);
848         init_done = true;
849 }
850
851 static void utmip_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy)
852 {
853         unsigned long val;
854         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
855         unsigned  int inst = phy->inst;
856
857         /* power down UTMIP interfaces */
858         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
859         val |= UTMIP_PWR(inst);
860         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
861
862         /* setup sleep walk usb controller */
863         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
864                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
865                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
866                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
867         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
868
869         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
870         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
871         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
872         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
873
874         /* Turn over pad configuration to PMC */
875         val = readl(pmc_base + PMC_SLEEP_CFG);
876         val &= ~UTMIP_WAKE_VAL(inst, ~0);
877         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE) |
878                 UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
879                 UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst);
880         writel(val, pmc_base + PMC_SLEEP_CFG);
881         PHY_DBG("%s ENABLE_PMC inst = %d\n", __func__, inst);
882 }
883
884 static void utmip_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
885 {
886         unsigned long val;
887         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
888         unsigned  int inst = phy->inst;
889
890         /* Disable PMC master mode by clearing MASTER_EN */
891         val = readl(pmc_base + PMC_SLEEP_CFG);
892         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
893                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
894         writel(val, pmc_base + PMC_SLEEP_CFG);
895         mdelay(1);
896         PHY_DBG("%s DISABLE_PMC inst = %d\n", __func__, inst);
897 }
898
899
900 #ifdef KERNEL_WARNING
901 static void usb_phy_power_down_pmc(void)
902 {
903         unsigned long val;
904         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
905
906         /* power down all 3 UTMIP interfaces */
907         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
908         val |= UTMIP_PWR(0) | UTMIP_PWR(1) | UTMIP_PWR(2);
909         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
910
911         /* turn on pad detectors */
912         writel(PMC_POWER_DOWN_MASK, pmc_base + PMC_USB_AO);
913
914         /* setup sleep walk fl all 3 usb controllers */
915         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
916                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
917                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
918                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
919         writel(val, pmc_base + PMC_SLEEPWALK_REG(0));
920         writel(val, pmc_base + PMC_SLEEPWALK_REG(1));
921         writel(val, pmc_base + PMC_SLEEPWALK_REG(2));
922
923         /* enable pull downs on HSIC PMC */
924         val = UHSIC_STROBE_RPD_A | UHSIC_DATA_RPD_A | UHSIC_STROBE_RPD_B |
925                 UHSIC_DATA_RPD_B | UHSIC_STROBE_RPD_C | UHSIC_DATA_RPD_C |
926                 UHSIC_STROBE_RPD_D | UHSIC_DATA_RPD_D;
927         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
928
929         /* Turn over pad configuration to PMC */
930         val = readl(pmc_base + PMC_SLEEP_CFG);
931         val &= ~UTMIP_WAKE_VAL(0, ~0);
932         val &= ~UTMIP_WAKE_VAL(1, ~0);
933         val &= ~UTMIP_WAKE_VAL(2, ~0);
934         val &= ~UHSIC_WAKE_VAL_P0(~0);
935         val |= UTMIP_WAKE_VAL(0, WAKE_VAL_NONE) | UHSIC_WAKE_VAL_P0(WAKE_VAL_NONE) |
936         UTMIP_WAKE_VAL(1, WAKE_VAL_NONE) | UTMIP_WAKE_VAL(2, WAKE_VAL_NONE) |
937         UTMIP_RCTRL_USE_PMC(0) | UTMIP_RCTRL_USE_PMC(1) | UTMIP_RCTRL_USE_PMC(2) |
938         UTMIP_TCTRL_USE_PMC(0) | UTMIP_TCTRL_USE_PMC(1) | UTMIP_TCTRL_USE_PMC(2) |
939         UTMIP_FSLS_USE_PMC(0) | UTMIP_FSLS_USE_PMC(1) | UTMIP_FSLS_USE_PMC(2) |
940         UTMIP_MASTER_ENABLE(0) | UTMIP_MASTER_ENABLE(1) | UTMIP_MASTER_ENABLE(2) |
941         UHSIC_MASTER_ENABLE_P0;
942         writel(val, pmc_base + PMC_SLEEP_CFG);
943 }
944 #endif
945
946 static int usb_phy_bringup_host_controller(struct tegra_usb_phy *phy)
947 {
948         unsigned long val;
949         void __iomem *base = phy->regs;
950
951         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
952         PHY_DBG("[%d] USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n", __LINE__,
953                 readl(base + USB_USBSTS), readl(base + USB_PORTSC),
954                                                         phy->port_speed);
955
956         /* Device is plugged in when system is in LP0 */
957         /* Bring up the controller from LP0*/
958         val = readl(base + USB_USBCMD);
959         val |= USB_CMD_RESET;
960         writel(val, base + USB_USBCMD);
961
962         if (usb_phy_reg_status_wait(base + USB_USBCMD,
963                 USB_CMD_RESET, 0, 2500) < 0) {
964                 pr_err("%s: timeout waiting for reset\n", __func__);
965         }
966
967         val = readl(base + USB_USBMODE);
968         val &= ~USB_USBMODE_MASK;
969         val |= USB_USBMODE_HOST;
970         writel(val, base + USB_USBMODE);
971         val = readl(base + HOSTPC1_DEVLC);
972         val &= ~HOSTPC1_DEVLC_PTS(~0);
973
974         if (phy->pdata->phy_intf == TEGRA_USB_PHY_INTF_HSIC)
975                 val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
976         else
977                 val |= HOSTPC1_DEVLC_STS;
978         writel(val, base + HOSTPC1_DEVLC);
979
980         /* Enable Port Power */
981         val = readl(base + USB_PORTSC);
982         val |= USB_PORTSC_PP;
983         writel(val, base + USB_PORTSC);
984         udelay(10);
985
986         /* Check if the phy resume from LP0. When the phy resume from LP0
987          * USB register will be reset.to zero */
988         if (!readl(base + USB_ASYNCLISTADDR)) {
989                 /* Program the field PTC based on the saved speed mode */
990                 val = readl(base + USB_PORTSC);
991                 val &= ~USB_PORTSC_PTC(~0);
992                 if ((phy->port_speed == USB_PHY_PORT_SPEED_HIGH) ||
993                         (phy->pdata->phy_intf == TEGRA_USB_PHY_INTF_HSIC))
994                         val |= USB_PORTSC_PTC(5);
995                 else if (phy->port_speed == USB_PHY_PORT_SPEED_FULL)
996                         val |= USB_PORTSC_PTC(6);
997                 else if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
998                         val |= USB_PORTSC_PTC(7);
999                 writel(val, base + USB_PORTSC);
1000                 udelay(10);
1001
1002                 /* Disable test mode by setting PTC field to NORMAL_OP */
1003                 val = readl(base + USB_PORTSC);
1004                 val &= ~USB_PORTSC_PTC(~0);
1005                 writel(val, base + USB_PORTSC);
1006                 udelay(10);
1007         }
1008
1009         /* Poll until CCS is enabled */
1010         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
1011                                                  USB_PORTSC_CCS, 2000)) {
1012                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
1013         }
1014
1015         /* Poll until PE is enabled */
1016         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_PE,
1017                                                  USB_PORTSC_PE, 2000)) {
1018                 pr_err("%s: timeout waiting for USB_PORTSC_PE\n", __func__);
1019         }
1020
1021         /* Clear the PCI status, to avoid an interrupt taken upon resume */
1022         val = readl(base + USB_USBSTS);
1023         val |= USB_USBSTS_PCI;
1024         writel(val, base + USB_USBSTS);
1025
1026         if (!phy->remote_wakeup) {
1027                 /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
1028                 val = readl(base + USB_PORTSC);
1029                 if ((val & USB_PORTSC_PP) && (val & USB_PORTSC_PE)) {
1030                         val |= USB_PORTSC_SUSP;
1031                         writel(val, base + USB_PORTSC);
1032                         /* Need a 4ms delay before the controller goes to suspend */
1033                         mdelay(4);
1034
1035                         /* Wait until port suspend completes */
1036                         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_SUSP,
1037                                                          USB_PORTSC_SUSP, 1000)) {
1038                                 pr_err("%s: timeout waiting for PORT_SUSPEND\n",
1039                                                                         __func__);
1040                         }
1041                 }
1042         }
1043         PHY_DBG("[%d] USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n", __LINE__,
1044                 readl(base + USB_USBSTS), readl(base + USB_PORTSC),
1045                                                         phy->port_speed);
1046
1047         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1048                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1049         return 0;
1050 }
1051
1052 static void usb_phy_wait_for_sof(struct tegra_usb_phy *phy)
1053 {
1054         unsigned long val;
1055         void __iomem *base = phy->regs;
1056
1057         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1058
1059         val = readl(base + USB_USBSTS);
1060         writel(val, base + USB_USBSTS);
1061         udelay(20);
1062         /* wait for two SOFs */
1063         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1064                 USB_USBSTS_SRI, 2500))
1065                 pr_err("%s: timeout waiting for SOF\n", __func__);
1066
1067         val = readl(base + USB_USBSTS);
1068         writel(val, base + USB_USBSTS);
1069         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI, 0, 2500))
1070                 pr_err("%s: timeout waiting for SOF\n", __func__);
1071
1072         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1073                         USB_USBSTS_SRI, 2500))
1074                 pr_err("%s: timeout waiting for SOF\n", __func__);
1075
1076         udelay(20);
1077 }
1078
1079 static unsigned int utmi_phy_xcvr_setup_value(struct tegra_usb_phy *phy)
1080 {
1081         struct tegra_utmi_config *cfg = &phy->pdata->u_cfg.utmi;
1082         signed long val;
1083
1084         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1085
1086         if (cfg->xcvr_use_fuses) {
1087                 val = XCVR_SETUP(tegra_fuse_readl(FUSE_USB_CALIB_0));
1088                 if (cfg->xcvr_use_lsb) {
1089                         val = min((unsigned int) ((val & XCVR_SETUP_LSB_MASK)
1090                                 + cfg->xcvr_setup_offset),
1091                                 (unsigned int) XCVR_SETUP_LSB_MAX_VAL);
1092                         val |= (cfg->xcvr_setup & XCVR_SETUP_MSB_MASK);
1093                 } else {
1094                         if (cfg->xcvr_setup_offset <= UTMIP_XCVR_MAX_OFFSET)
1095                                 val = val + cfg->xcvr_setup_offset;
1096
1097                         if (val > UTMIP_XCVR_SETUP_MAX_VALUE) {
1098                                 val = UTMIP_XCVR_SETUP_MAX_VALUE;
1099                                 pr_info("%s: reset XCVR_SETUP to max value\n",
1100                                                 __func__);
1101                         } else if (val < UTMIP_XCVR_SETUP_MIN_VALUE) {
1102                                 val = UTMIP_XCVR_SETUP_MIN_VALUE;
1103                                 pr_info("%s: reset XCVR_SETUP to min value\n",
1104                                                 __func__);
1105                         }
1106                 }
1107         } else {
1108                 val = cfg->xcvr_setup;
1109         }
1110
1111         return (unsigned int) val;
1112 }
1113
1114 static int utmi_phy_open(struct tegra_usb_phy *phy)
1115 {
1116         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1117         unsigned long parent_rate, val;
1118         int i;
1119
1120         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1121
1122         phy->utmi_pad_clk = clk_get_sys("utmip-pad", NULL);
1123         if (IS_ERR(phy->utmi_pad_clk)) {
1124                 pr_err("%s: can't get utmip pad clock\n", __func__);
1125                 return PTR_ERR(phy->utmi_pad_clk);
1126         }
1127
1128         phy->utmi_xcvr_setup = utmi_phy_xcvr_setup_value(phy);
1129
1130         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
1131         for (i = 0; i < ARRAY_SIZE(utmip_freq_table); i++) {
1132                 if (utmip_freq_table[i].freq == parent_rate) {
1133                         phy->freq = &utmip_freq_table[i];
1134                         break;
1135                 }
1136         }
1137         if (!phy->freq) {
1138                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
1139                 return -EINVAL;
1140         }
1141
1142         /* Power-up the VBUS detector for UTMIP PHY */
1143         val = readl(pmc_base + PMC_USB_AO);
1144         val &= ~(PMC_USB_AO_VBUS_WAKEUP_PD_P0 | PMC_USB_AO_ID_PD_P0);
1145         writel((val | PMC_USB_AO_PD_P2), (pmc_base + PMC_USB_AO));
1146
1147         utmip_powerup_pmc_wake_detect(phy);
1148
1149         return 0;
1150 }
1151
1152 static void utmi_phy_close(struct tegra_usb_phy *phy)
1153 {
1154         unsigned long val;
1155         void __iomem *base = phy->regs;
1156
1157         DBG("%s inst:[%d]\n", __func__, phy->inst);
1158
1159         /* Disable PHY clock valid interrupts while going into suspend*/
1160         if (phy->pdata->u_data.host.hot_plug) {
1161                 val = readl(base + USB_SUSP_CTRL);
1162                 val &= ~USB_PHY_CLK_VALID_INT_ENB;
1163                 writel(val, base + USB_SUSP_CTRL);
1164         }
1165
1166         clk_put(phy->utmi_pad_clk);
1167 }
1168
1169 static int utmi_phy_pad_power_on(struct tegra_usb_phy *phy)
1170 {
1171         unsigned long val, flags;
1172         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1173
1174         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1175
1176         clk_enable(phy->utmi_pad_clk);
1177
1178         spin_lock_irqsave(&utmip_pad_lock, flags);
1179         utmip_pad_count++;
1180
1181         val = readl(pad_base + UTMIP_BIAS_CFG0);
1182         val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
1183         val |= UTMIP_HSSQUELCH_LEVEL(0x2) | UTMIP_HSDISCON_LEVEL(0x1) |
1184                 UTMIP_HSDISCON_LEVEL_MSB;
1185         writel(val, pad_base + UTMIP_BIAS_CFG0);
1186
1187         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1188
1189         clk_disable(phy->utmi_pad_clk);
1190
1191         return 0;
1192 }
1193
1194 static int utmi_phy_pad_power_off(struct tegra_usb_phy *phy)
1195 {
1196         unsigned long val, flags;
1197         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1198
1199         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1200
1201         clk_enable(phy->utmi_pad_clk);
1202         spin_lock_irqsave(&utmip_pad_lock, flags);
1203
1204         if (!utmip_pad_count) {
1205                 pr_err("%s: utmip pad already powered off\n", __func__);
1206                 goto out;
1207         }
1208         if (--utmip_pad_count == 0) {
1209                 val = readl(pad_base + UTMIP_BIAS_CFG0);
1210                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
1211                 val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) | UTMIP_HSDISCON_LEVEL(~0) |
1212                         UTMIP_HSDISCON_LEVEL_MSB);
1213                 writel(val, pad_base + UTMIP_BIAS_CFG0);
1214         }
1215 out:
1216         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1217         clk_disable(phy->utmi_pad_clk);
1218
1219         return 0;
1220 }
1221
1222 static int utmi_phy_irq(struct tegra_usb_phy *phy)
1223 {
1224         void __iomem *base = phy->regs;
1225         unsigned long val = 0;
1226         bool remote_wakeup = false;
1227         int irq_status = IRQ_HANDLED;
1228
1229         if (phy->phy_clk_on) {
1230                 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1231                 DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1232                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1233                 DBG("USB_USBMODE[0x%x] USB_USBCMD[0x%x]\n",
1234                         readl(base + USB_USBMODE), readl(base + USB_USBCMD));
1235         }
1236
1237         usb_phy_fence_read(phy);
1238         /* check if there is any remote wake event */
1239         if (utmi_phy_remotewake_detected(phy)) {
1240                 pr_info("%s: utmip remote wake detected\n", __func__);
1241                 remote_wakeup = true;
1242         }
1243
1244         if (phy->pdata->u_data.host.hot_plug) {
1245                 val = readl(base + USB_SUSP_CTRL);
1246                 if ((val  & USB_PHY_CLK_VALID_INT_STS)) {
1247                         val &= ~USB_PHY_CLK_VALID_INT_ENB |
1248                                         USB_PHY_CLK_VALID_INT_STS;
1249                         writel(val , (base + USB_SUSP_CTRL));
1250
1251                         /* In case of remote wakeup PHY clock will not up
1252                            immediately, so should not access any controller
1253                            register but normal plug-in/plug-out should be
1254                            executed */
1255                         if (!remote_wakeup) {
1256                                 val = readl(base + USB_USBSTS);
1257                                 if (!(val  & USB_USBSTS_PCI)) {
1258                                         irq_status = IRQ_NONE;
1259                                         goto exit;
1260                                 }
1261
1262                                 val = readl(base + USB_PORTSC);
1263                                 if (val & USB_PORTSC_CCS)
1264                                         val &= ~USB_PORTSC_WKCN;
1265                                 else
1266                                         val &= ~USB_PORTSC_WKDS;
1267                                 val &= ~USB_PORTSC_RWC_BITS;
1268                                 writel(val , (base + USB_PORTSC));
1269                         }
1270                 } else if (!phy->phy_clk_on) {
1271                         if (remote_wakeup)
1272                                 irq_status = IRQ_HANDLED;
1273                         else
1274                                 irq_status = IRQ_NONE;
1275                         goto exit;
1276                 }
1277         }
1278 exit:
1279         return irq_status;
1280 }
1281
1282 static void utmi_phy_enable_obs_bus(struct tegra_usb_phy *phy)
1283 {
1284         unsigned long val;
1285         void __iomem *base = phy->regs;
1286
1287         /* (2LS WAR)is not required for LS and FS devices and is only for HS */
1288         if ((phy->port_speed == USB_PHY_PORT_SPEED_LOW) ||
1289                 (phy->port_speed == USB_PHY_PORT_SPEED_FULL)) {
1290                 /* do not enable the OBS bus */
1291                 val = readl(base + UTMIP_MISC_CFG0);
1292                 val &= ~(UTMIP_DPDM_OBSERVE_SEL(~0));
1293                 writel(val, base + UTMIP_MISC_CFG0);
1294                 DBG("%s(%d) Disable OBS bus\n", __func__, __LINE__);
1295                 return;
1296         }
1297         /* Force DP/DM pulldown active for Host mode */
1298         val = readl(base + UTMIP_MISC_CFG0);
1299         val |= FORCE_PULLDN_DM | FORCE_PULLDN_DP |
1300                         COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS;
1301         writel(val, base + UTMIP_MISC_CFG0);
1302         val = readl(base + UTMIP_MISC_CFG0);
1303         val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1304         if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
1305                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
1306         else
1307                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
1308         writel(val, base + UTMIP_MISC_CFG0);
1309         udelay(1);
1310
1311         val = readl(base + UTMIP_MISC_CFG0);
1312         val |= UTMIP_DPDM_OBSERVE;
1313         writel(val, base + UTMIP_MISC_CFG0);
1314         udelay(10);
1315         DBG("%s(%d) Enable OBS bus\n", __func__, __LINE__);
1316         PHY_DBG("ENABLE_OBS_BUS\n");
1317 }
1318
1319 static int utmi_phy_disable_obs_bus(struct tegra_usb_phy *phy)
1320 {
1321         unsigned long val;
1322         void __iomem *base = phy->regs;
1323         unsigned long flags;
1324
1325         /* check if OBS bus is already enabled */
1326         val = readl(base + UTMIP_MISC_CFG0);
1327         if (val & UTMIP_DPDM_OBSERVE) {
1328                 PHY_DBG("DISABLE_OBS_BUS\n");
1329
1330                 /* disable ALL interrupts on current CPU */
1331                 local_irq_save(flags);
1332
1333                 /* Change the UTMIP OBS bus to drive SE0 */
1334                 val = readl(base + UTMIP_MISC_CFG0);
1335                 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
1336                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_SE0;
1337                 writel(val, base + UTMIP_MISC_CFG0);
1338
1339                 /* Wait for 3us(2 LS bit times) */
1340                 udelay(3);
1341
1342                 /* Release UTMIP OBS bus */
1343                 val = readl(base + UTMIP_MISC_CFG0);
1344                 val &= ~UTMIP_DPDM_OBSERVE;
1345                 writel(val, base + UTMIP_MISC_CFG0);
1346
1347                 /* Release DP/DM pulldown for Host mode */
1348                 val = readl(base + UTMIP_MISC_CFG0);
1349                 val &= ~(FORCE_PULLDN_DM | FORCE_PULLDN_DP |
1350                                 COMB_TERMS | ALWAYS_FREE_RUNNING_TERMS);
1351                 writel(val, base + UTMIP_MISC_CFG0);
1352
1353                 val = readl(base + USB_USBCMD);
1354                 val |= USB_USBCMD_RS;
1355                 writel(val, base + USB_USBCMD);
1356
1357                 /* restore ALL interrupts on current CPU */
1358                 local_irq_restore(flags);
1359
1360                 if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
1361                                                          USB_USBCMD_RS, 2000)) {
1362                         pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
1363                         return -ETIMEDOUT;
1364                 }
1365         }
1366         return 0;
1367 }
1368
1369 static int utmi_phy_post_resume(struct tegra_usb_phy *phy)
1370 {
1371         unsigned long val;
1372         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1373         unsigned  int inst = phy->inst;
1374
1375         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1376         val = readl(pmc_base + PMC_SLEEP_CFG);
1377         /* if PMC is not disabled by now then disable it */
1378         if (val & UTMIP_MASTER_ENABLE(inst)) {
1379                 utmip_phy_disable_pmc_bus_ctrl(phy);
1380         }
1381
1382         utmi_phy_disable_obs_bus(phy);
1383
1384         return 0;
1385 }
1386
1387 static int phy_post_suspend(struct tegra_usb_phy *phy)
1388 {
1389
1390         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1391         /* Need a 4ms delay for controller to suspend */
1392         mdelay(4);
1393
1394         return 0;
1395
1396 }
1397
1398 static int utmi_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1399 {
1400         unsigned long val;
1401         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1402         void __iomem *base = phy->regs;
1403         unsigned  int inst = phy->inst;
1404
1405         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1406         phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
1407                         HOSTPC1_DEVLC_PSPD_MASK;
1408
1409         if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH) {
1410                 /* Disable interrupts */
1411                 writel(0, base + USB_USBINTR);
1412                 /* Clear the run bit to stop SOFs - 2LS WAR */
1413                 val = readl(base + USB_USBCMD);
1414                 val &= ~USB_USBCMD_RS;
1415                 writel(val, base + USB_USBCMD);
1416                 if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
1417                                                          USB_USBSTS_HCH, 2000)) {
1418                         pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
1419                 }
1420         }
1421
1422         val = readl(pmc_base + PMC_SLEEP_CFG);
1423         if (val & UTMIP_MASTER_ENABLE(inst)) {
1424                 if (!remote_wakeup)
1425                         utmip_phy_disable_pmc_bus_ctrl(phy);
1426         } else {
1427                 utmi_phy_enable_obs_bus(phy);
1428         }
1429
1430         return 0;
1431 }
1432
1433 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
1434 {
1435         unsigned long val;
1436         void __iomem *base = phy->regs;
1437
1438         PHY_DBG("%s(%d) inst:[%d] BEGIN\n", __func__, __LINE__, phy->inst);
1439         if (!phy->phy_clk_on) {
1440                 PHY_DBG("%s(%d) inst:[%d] phy clk is already off\n",
1441                                         __func__, __LINE__, phy->inst);
1442                 return 0;
1443         }
1444
1445         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1446                 utmip_powerdown_pmc_wake_detect(phy);
1447
1448                 val = readl(base + USB_SUSP_CTRL);
1449                 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
1450                 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
1451                 writel(val, base + USB_SUSP_CTRL);
1452
1453                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1454                 val |= UTMIP_PD_CHRG;
1455                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1456         } else {
1457                 phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
1458                                 HOSTPC1_DEVLC_PSPD_MASK;
1459
1460                 /* Disable interrupts */
1461                 writel(0, base + USB_USBINTR);
1462
1463                 /* Clear the run bit to stop SOFs - 2LS WAR */
1464                 val = readl(base + USB_USBCMD);
1465                 val &= ~USB_USBCMD_RS;
1466                 writel(val, base + USB_USBCMD);
1467
1468                 if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
1469                                                          USB_USBSTS_HCH, 2000)) {
1470                         pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
1471                 }
1472                 utmip_setup_pmc_wake_detect(phy);
1473         }
1474
1475         if (!phy->pdata->u_data.host.hot_plug) {
1476                 val = readl(base + UTMIP_XCVR_CFG0);
1477                 val |= (UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
1478                          UTMIP_FORCE_PDZI_POWERDOWN);
1479                 writel(val, base + UTMIP_XCVR_CFG0);
1480         }
1481
1482         val = readl(base + UTMIP_XCVR_CFG1);
1483         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1484                    UTMIP_FORCE_PDDR_POWERDOWN;
1485         writel(val, base + UTMIP_XCVR_CFG1);
1486
1487         val = readl(base + UTMIP_BIAS_CFG1);
1488         val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
1489         writel(val, base + UTMIP_BIAS_CFG1);
1490
1491         utmi_phy_pad_power_off(phy);
1492
1493         if (phy->pdata->u_data.host.hot_plug) {
1494                 bool enable_hotplug = true;
1495                 /* if it is OTG port then make sure to enable hot-plug feature
1496                    only if host adaptor is connected, i.e id is low */
1497                 if (phy->pdata->port_otg) {
1498                         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1499                         enable_hotplug = (val & USB_ID_STATUS) ? false : true;
1500                 }
1501                 if (enable_hotplug) {
1502                         /* Enable wakeup event of device plug-in/plug-out */
1503                         val = readl(base + USB_PORTSC);
1504                         if (val & USB_PORTSC_CCS)
1505                                 val |= USB_PORTSC_WKDS;
1506                         else
1507                                 val |= USB_PORTSC_WKCN;
1508                         writel(val, base + USB_PORTSC);
1509
1510                         val = readl(base + USB_SUSP_CTRL);
1511                         val |= USB_PHY_CLK_VALID_INT_ENB;
1512                         writel(val, base + USB_SUSP_CTRL);
1513                 } else {
1514                         /* Disable PHY clock valid interrupts while going into suspend*/
1515                         val = readl(base + USB_SUSP_CTRL);
1516                         val &= ~USB_PHY_CLK_VALID_INT_ENB;
1517                         writel(val, base + USB_SUSP_CTRL);
1518                 }
1519         }
1520
1521         /* Disable PHY clock */
1522         val = readl(base + HOSTPC1_DEVLC);
1523         val |= HOSTPC1_DEVLC_PHCD;
1524         writel(val, base + HOSTPC1_DEVLC);
1525
1526         if (!phy->pdata->u_data.host.hot_plug) {
1527                 val = readl(base + USB_SUSP_CTRL);
1528                 val |= UTMIP_RESET;
1529                 writel(val, base + USB_SUSP_CTRL);
1530         }
1531
1532         phy->phy_clk_on = false;
1533         phy->hw_accessible = false;
1534
1535         PHY_DBG("%s(%d) inst:[%d] END\n", __func__, __LINE__, phy->inst);
1536
1537         return 0;
1538 }
1539
1540
1541 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
1542 {
1543         unsigned long val;
1544         void __iomem *base = phy->regs;
1545         struct tegra_utmi_config *config = &phy->pdata->u_cfg.utmi;
1546
1547         PHY_DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1548         if (phy->phy_clk_on) {
1549                 PHY_DBG("%s(%d) inst:[%d] phy clk is already On\n",
1550                                         __func__, __LINE__, phy->inst);
1551                 return 0;
1552         }
1553         val = readl(base + USB_SUSP_CTRL);
1554         val |= UTMIP_RESET;
1555         writel(val, base + USB_SUSP_CTRL);
1556
1557         val = readl(base + UTMIP_TX_CFG0);
1558         val |= UTMIP_FS_PREABMLE_J;
1559         writel(val, base + UTMIP_TX_CFG0);
1560
1561         val = readl(base + UTMIP_HSRX_CFG0);
1562         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
1563         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
1564         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
1565         writel(val, base + UTMIP_HSRX_CFG0);
1566
1567         val = readl(base + UTMIP_HSRX_CFG1);
1568         val &= ~UTMIP_HS_SYNC_START_DLY(~0);
1569         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
1570         writel(val, base + UTMIP_HSRX_CFG1);
1571
1572         val = readl(base + UTMIP_DEBOUNCE_CFG0);
1573         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
1574         val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
1575         writel(val, base + UTMIP_DEBOUNCE_CFG0);
1576
1577         val = readl(base + UTMIP_MISC_CFG0);
1578         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
1579         writel(val, base + UTMIP_MISC_CFG0);
1580
1581         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1582                 val = readl(base + USB_SUSP_CTRL);
1583                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
1584                 writel(val, base + USB_SUSP_CTRL);
1585
1586                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1587                 val &= ~UTMIP_PD_CHRG;
1588                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1589         } else {
1590                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1591                 val |= UTMIP_PD_CHRG;
1592                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1593         }
1594
1595         utmi_phy_pad_power_on(phy);
1596
1597         val = readl(base + UTMIP_XCVR_CFG0);
1598         val &= ~(UTMIP_XCVR_LSBIAS_SEL | UTMIP_FORCE_PD_POWERDOWN |
1599                  UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN |
1600                  UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_LSFSLEW(~0) |
1601                  UTMIP_XCVR_LSRSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
1602         val |= UTMIP_XCVR_SETUP(phy->utmi_xcvr_setup);
1603         val |= UTMIP_XCVR_SETUP_MSB(XCVR_SETUP_MSB_CALIB(phy->utmi_xcvr_setup));
1604         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
1605         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
1606         if (!config->xcvr_use_lsb)
1607                 val |= UTMIP_XCVR_HSSLEW_MSB(0x8);
1608         writel(val, base + UTMIP_XCVR_CFG0);
1609
1610         val = readl(base + UTMIP_XCVR_CFG1);
1611         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1612                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
1613         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
1614         writel(val, base + UTMIP_XCVR_CFG1);
1615
1616         val = readl(base + UTMIP_BIAS_CFG1);
1617         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
1618         val |= UTMIP_BIAS_PDTRK_COUNT(phy->freq->pdtrk_count);
1619         writel(val, base + UTMIP_BIAS_CFG1);
1620
1621         val = readl(base + UTMIP_SPARE_CFG0);
1622         val &= ~FUSE_SETUP_SEL;
1623         val |= FUSE_ATERM_SEL;
1624         writel(val, base + UTMIP_SPARE_CFG0);
1625
1626         val = readl(base + USB_SUSP_CTRL);
1627         val |= UTMIP_PHY_ENABLE;
1628         writel(val, base + USB_SUSP_CTRL);
1629
1630         val = readl(base + USB_SUSP_CTRL);
1631         val &= ~UTMIP_RESET;
1632         writel(val, base + USB_SUSP_CTRL);
1633
1634         val = readl(base + HOSTPC1_DEVLC);
1635         val &= ~HOSTPC1_DEVLC_PHCD;
1636         writel(val, base + HOSTPC1_DEVLC);
1637
1638         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1639                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500))
1640                 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
1641
1642         utmi_phy_enable_trking_data(phy);
1643
1644         if (phy->inst == 2)
1645                 writel(0, base + ICUSB_CTRL);
1646
1647         val = readl(base + USB_USBMODE);
1648         val &= ~USB_USBMODE_MASK;
1649         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST)
1650                 val |= USB_USBMODE_HOST;
1651         else
1652                 val |= USB_USBMODE_DEVICE;
1653         writel(val, base + USB_USBMODE);
1654
1655         val = readl(base + HOSTPC1_DEVLC);
1656         val &= ~HOSTPC1_DEVLC_PTS(~0);
1657         val |= HOSTPC1_DEVLC_STS;
1658         writel(val, base + HOSTPC1_DEVLC);
1659
1660         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE)
1661                 utmip_powerup_pmc_wake_detect(phy);
1662         phy->phy_clk_on = true;
1663         phy->hw_accessible = true;
1664         PHY_DBG("%s(%d) End inst:[%d]\n", __func__, __LINE__, phy->inst);
1665         return 0;
1666 }
1667
1668 static void utmi_phy_restore_start(struct tegra_usb_phy *phy)
1669 {
1670         unsigned long val;
1671         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1672         int inst = phy->inst;
1673
1674         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1675         val = readl(pmc_base + UTMIP_UHSIC_STATUS);
1676         /* Check whether we wake up from the remote resume.
1677            For lp1 case, pmc is not responsible for waking the
1678            system, it's the flow controller and hence
1679            UTMIP_WALK_PTR_VAL(inst) will return 0.
1680            Also, for lp1 case phy->remote_wakeup will already be set
1681            to true by utmi_phy_irq() when the remote wakeup happens.
1682            Hence change the logic in the else part to enter only
1683            if phy->remote_wakeup is not set to true by the
1684            utmi_phy_irq(). */
1685         if (UTMIP_WALK_PTR_VAL(inst) & val) {
1686                 phy->remote_wakeup = true;
1687         } else if(!phy->remote_wakeup) {
1688                 val = readl(pmc_base + PMC_SLEEP_CFG);
1689                 if (val & UTMIP_MASTER_ENABLE(inst))
1690                         utmip_phy_disable_pmc_bus_ctrl(phy);
1691         }
1692
1693         utmi_phy_enable_obs_bus(phy);
1694 }
1695
1696 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
1697 {
1698         unsigned long val;
1699         void __iomem *base = phy->regs;
1700         int wait_time_us = 25000; /* FPR should be set by this time */
1701
1702         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1703         /* check whether we wake up from the remote resume */
1704         if (phy->remote_wakeup) {
1705                 /* wait until SUSPEND and RESUME bit is cleared on remote resume */
1706                 do {
1707                         val = readl(base + USB_PORTSC);
1708                         udelay(1);
1709                         if (wait_time_us == 0) {
1710                                 PHY_DBG("%s PMC FPR timeout val = 0x%lx ",
1711                                                         __func__, val);
1712                                 utmip_phy_disable_pmc_bus_ctrl(phy);
1713                                 utmi_phy_post_resume(phy);
1714                                 return;
1715                         }
1716                         wait_time_us--;
1717                 } while (val & (USB_PORTSC_RESUME | USB_PORTSC_SUSP));
1718
1719                 /* wait for 25 ms to port resume complete */
1720                 msleep(25);
1721                 /* disable PMC master control */
1722                 utmip_phy_disable_pmc_bus_ctrl(phy);
1723
1724                 /* Clear PCI and SRI bits to avoid an interrupt upon resume */
1725                 val = readl(base + USB_USBSTS);
1726                 writel(val, base + USB_USBSTS);
1727                 /* wait to avoid SOF if there is any */
1728                 if (usb_phy_reg_status_wait(base + USB_USBSTS,
1729                         USB_USBSTS_SRI, USB_USBSTS_SRI, 2500) < 0) {
1730                         pr_err("%s: timeout waiting for SOF\n", __func__);
1731                 }
1732                 utmi_phy_post_resume(phy);
1733         }
1734 }
1735
1736 static int utmi_phy_resume(struct tegra_usb_phy *phy)
1737 {
1738         int status = 0;
1739         unsigned long val;
1740         void __iomem *base = phy->regs;
1741
1742         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1743         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) {
1744                 if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
1745                         utmi_phy_restore_start(phy);
1746                         usb_phy_bringup_host_controller(phy);
1747                         utmi_phy_restore_end(phy);
1748                 } else {
1749                         /* device is plugged in when system is in LP0 */
1750                         /* bring up the controller from LP0*/
1751                         val = readl(base + USB_USBCMD);
1752                         val |= USB_CMD_RESET;
1753                         writel(val, base + USB_USBCMD);
1754
1755                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1756                                 USB_CMD_RESET, 0, 2500) < 0) {
1757                                 pr_err("%s: timeout waiting for reset\n", __func__);
1758                         }
1759
1760                         val = readl(base + USB_USBMODE);
1761                         val &= ~USB_USBMODE_MASK;
1762                         val |= USB_USBMODE_HOST;
1763                         writel(val, base + USB_USBMODE);
1764
1765                         val = readl(base + HOSTPC1_DEVLC);
1766                         val &= ~HOSTPC1_DEVLC_PTS(~0);
1767                         val |= HOSTPC1_DEVLC_STS;
1768                         writel(val, base + HOSTPC1_DEVLC);
1769
1770                         writel(USB_USBCMD_RS, base + USB_USBCMD);
1771
1772                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1773                                 USB_USBCMD_RS, USB_USBCMD_RS, 2500) < 0) {
1774                                 pr_err("%s: timeout waiting for run bit\n", __func__);
1775                         }
1776
1777                         /* Enable Port Power */
1778                         val = readl(base + USB_PORTSC);
1779                         val |= USB_PORTSC_PP;
1780                         writel(val, base + USB_PORTSC);
1781                         udelay(10);
1782
1783                         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1784                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1785                 }
1786         }
1787
1788         return status;
1789 }
1790
1791 static bool utmi_phy_charger_detect(struct tegra_usb_phy *phy)
1792 {
1793         unsigned long val;
1794         void __iomem *base = phy->regs;
1795         bool status;
1796
1797         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1798         if (phy->pdata->op_mode != TEGRA_USB_OPMODE_DEVICE) {
1799                 /* Charger detection is not there for ULPI
1800                  * return Charger not available */
1801                 return false;
1802         }
1803
1804         /* Enable charger detection logic */
1805         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1806         val |= UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN;
1807         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1808
1809         /* Source should be on for 100 ms as per USB charging spec */
1810         msleep(TDP_SRC_ON_MS);
1811
1812         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1813         /* If charger is not connected disable the interrupt */
1814         val &= ~VDAT_DET_INT_EN;
1815         val |= VDAT_DET_CHG_DET;
1816         writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
1817
1818         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1819         if (val & VDAT_DET_STS)
1820                 status = true;
1821         else
1822                 status = false;
1823
1824         /* Disable charger detection logic */
1825         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1826         val &= ~(UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN);
1827         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1828
1829         /* Delay of 40 ms before we pull the D+ as per battery charger spec */
1830         msleep(TDPSRC_CON_MS);
1831
1832         return status;
1833 }
1834
1835 static void uhsic_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
1836 {
1837         unsigned long val;
1838         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1839
1840         /* turn on pad detectors for HSIC*/
1841         val = readl(pmc_base + PMC_USB_AO);
1842         val &= ~(HSIC_RESERVED_P0 | STROBE_VAL_PD_P0 | DATA_VAL_PD_P0);
1843         writel(val, pmc_base + PMC_USB_AO);
1844
1845         /* Disable PMC master mode by clearing MASTER_EN */
1846         val = readl(pmc_base + PMC_SLEEP_CFG);
1847         val &= ~(UHSIC_MASTER_ENABLE_P0);
1848         writel(val, pmc_base + PMC_SLEEP_CFG);
1849         mdelay(1);
1850 }
1851
1852 static void uhsic_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy)
1853 {
1854         unsigned long val;
1855         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1856
1857         DBG("%s:%d\n", __func__, __LINE__);
1858
1859         /* turn off pad detectors for HSIC*/
1860         val = readl(pmc_base + PMC_USB_AO);
1861         val |= (HSIC_RESERVED_P0 | STROBE_VAL_PD_P0 | DATA_VAL_PD_P0);
1862         writel(val, pmc_base + PMC_USB_AO);
1863
1864         /* enable pull downs on HSIC PMC */
1865         val = UHSIC_STROBE_RPD_A | UHSIC_DATA_RPD_A | UHSIC_STROBE_RPD_B |
1866                 UHSIC_DATA_RPD_B | UHSIC_STROBE_RPD_C | UHSIC_DATA_RPD_C |
1867                 UHSIC_STROBE_RPD_D | UHSIC_DATA_RPD_D;
1868         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1869
1870         /* Turn over pad configuration to PMC */
1871         val = readl(pmc_base + PMC_SLEEP_CFG);
1872         val &= ~UHSIC_WAKE_VAL_P0(~0);
1873         val |= UHSIC_WAKE_VAL_P0(WAKE_VAL_NONE) | UHSIC_MASTER_ENABLE_P0;
1874         writel(val, pmc_base + PMC_SLEEP_CFG);
1875 }
1876
1877 static void uhsic_setup_pmc_wake_detect(struct tegra_usb_phy *phy)
1878 {
1879         unsigned long val;
1880         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1881         void __iomem *base = phy->regs;
1882         bool port_connected;
1883
1884         DBG("%s:%d\n", __func__, __LINE__);
1885
1886         /* check for port connect status */
1887         val = readl(base + USB_PORTSC);
1888         port_connected = val & USB_PORTSC_CCS;
1889
1890         if (!port_connected)
1891                 return;
1892
1893         /*Set PMC MASTER bits to do the following
1894         * a. Take over the hsic drivers
1895         * b. set up such that it will take over resume
1896         *        if remote wakeup is detected
1897         * Prepare PMC to take over suspend-wake detect-drive resume until USB
1898         * controller ready
1899         */
1900
1901         /* disable master enable in PMC */
1902         val = readl(pmc_base + PMC_SLEEP_CFG);
1903         val &= ~UHSIC_MASTER_ENABLE_P0;
1904         writel(val, pmc_base + PMC_SLEEP_CFG);
1905
1906         /* UTMIP_PWR_PX=1 for power savings mode */
1907         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
1908         val |= UHSIC_PWR;
1909         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
1910
1911         /* Make sure nothing is happening on the line with respect to PMC */
1912         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
1913         val &= ~UHSIC_STROBE_VAL;
1914         val &= ~UHSIC_DATA_VAL;
1915         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
1916
1917         /* Clear walk enable */
1918         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
1919         val &= ~UHSIC_LINEVAL_WALK_EN;
1920         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
1921
1922         /* Make sure wake value for line is none */
1923         val = readl(pmc_base + PMC_SLEEP_CFG);
1924         val &= ~UHSIC_WAKE_VAL(WAKE_VAL_ANY);
1925         val |= UHSIC_WAKE_VAL(WAKE_VAL_NONE);
1926         writel(val, pmc_base + PMC_SLEEP_CFG);
1927
1928         /* turn on pad detectors */
1929         val = readl(pmc_base + PMC_USB_AO);
1930         val &= ~(STROBE_VAL_PD_P0 | DATA_VAL_PD_P0);
1931         writel(val, pmc_base + PMC_USB_AO);
1932
1933         /* Add small delay before usb detectors provide stable line values */
1934         udelay(1);
1935
1936         /* Enable which type of event can trigger a walk,
1937         * in this case usb_line_wake */
1938         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
1939         val |= UHSIC_LINEVAL_WALK_EN;
1940         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
1941
1942         /* program walk sequence, maintain a J, followed by a driven K
1943         * to signal a resume once an wake event is detected */
1944
1945         val = readl(pmc_base + PMC_SLEEPWALK_UHSIC);
1946
1947         val &= ~UHSIC_DATA_RPU_A;
1948         val |=  UHSIC_DATA_RPD_A;
1949         val &= ~UHSIC_STROBE_RPD_A;
1950         val |=  UHSIC_STROBE_RPU_A;
1951
1952         val &= ~UHSIC_DATA_RPD_B;
1953         val |=  UHSIC_DATA_RPU_B;
1954         val &= ~UHSIC_STROBE_RPU_B;
1955         val |=  UHSIC_STROBE_RPD_B;
1956
1957         val &= ~UHSIC_DATA_RPD_C;
1958         val |=  UHSIC_DATA_RPU_C;
1959         val &= ~UHSIC_STROBE_RPU_C;
1960         val |=  UHSIC_STROBE_RPD_C;
1961
1962         val &= ~UHSIC_DATA_RPD_D;
1963         val |=  UHSIC_DATA_RPU_D;
1964         val &= ~UHSIC_STROBE_RPU_D;
1965         val |=  UHSIC_STROBE_RPD_D;
1966         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1967
1968         phy->remote_wakeup = false;
1969
1970         /* Setting Wake event*/
1971         val = readl(pmc_base + PMC_SLEEP_CFG);
1972         val &= ~UHSIC_WAKE_VAL(WAKE_VAL_ANY);
1973         val |= UHSIC_WAKE_VAL(WAKE_VAL_SD10);
1974         writel(val, pmc_base + PMC_SLEEP_CFG);
1975
1976         /* Clear the walk pointers and wake alarm */
1977         val = readl(pmc_base + PMC_TRIGGERS);
1978         val |= UHSIC_CLR_WAKE_ALARM_P0 | UHSIC_CLR_WALK_PTR_P0;
1979         writel(val, pmc_base + PMC_TRIGGERS);
1980
1981         /* Turn over pad configuration to PMC  for line wake events*/
1982         val = readl(pmc_base + PMC_SLEEP_CFG);
1983         val |= UHSIC_MASTER_ENABLE;
1984         writel(val, pmc_base + PMC_SLEEP_CFG);
1985
1986         val = readl(base + UHSIC_PMC_WAKEUP0);
1987         val |= EVENT_INT_ENB;
1988         writel(val, base + UHSIC_PMC_WAKEUP0);
1989
1990         DBG("%s:PMC enabled for HSIC remote wakeup\n", __func__);
1991 }
1992
1993 static void uhsic_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy)
1994 {
1995         unsigned long val;
1996         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1997         void __iomem *base = phy->regs;
1998
1999         DBG("%s (%d)\n", __func__, __LINE__);
2000         val = readl(pmc_base + PMC_SLEEP_CFG);
2001         val &= ~UHSIC_WAKE_VAL(WAKE_VAL_ANY);
2002         val |= UHSIC_WAKE_VAL(WAKE_VAL_NONE);
2003         writel(val, pmc_base + PMC_SLEEP_CFG);
2004
2005         val = readl(base + UHSIC_PMC_WAKEUP0);
2006         val &= ~EVENT_INT_ENB;
2007         writel(val, base + UHSIC_PMC_WAKEUP0);
2008
2009         /* Disable PMC master mode by clearing MASTER_EN */
2010         val = readl(pmc_base + PMC_SLEEP_CFG);
2011         val &= ~(UHSIC_MASTER_ENABLE);
2012         writel(val, pmc_base + PMC_SLEEP_CFG);
2013
2014         /* turn off pad detectors */
2015         val = readl(pmc_base + PMC_USB_AO);
2016         val |= (STROBE_VAL_PD_P0 | DATA_VAL_PD_P0);
2017         writel(val, pmc_base + PMC_USB_AO);
2018
2019         val = readl(pmc_base + PMC_TRIGGERS);
2020         val |= (UHSIC_CLR_WALK_PTR_P0 | UHSIC_CLR_WAKE_ALARM_P0);
2021         writel(val, pmc_base + PMC_TRIGGERS);
2022
2023         phy->remote_wakeup = false;
2024 }
2025
2026 static bool uhsic_phy_remotewake_detected(struct tegra_usb_phy *phy)
2027 {
2028         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
2029         void __iomem *base = phy->regs;
2030         u32 val;
2031
2032         val = readl(base + UHSIC_PMC_WAKEUP0);
2033         if (val & EVENT_INT_ENB) {
2034                 val = readl(pmc_base + UTMIP_UHSIC_STATUS);
2035                 if (UHSIC_WAKE_ALARM & val) {
2036                         val = readl(pmc_base + PMC_SLEEP_CFG);
2037                         val &= ~UHSIC_WAKE_VAL(WAKE_VAL_ANY);
2038                         val |= UHSIC_WAKE_VAL(WAKE_VAL_NONE);
2039                         writel(val, pmc_base + PMC_SLEEP_CFG);
2040
2041                         val = readl(pmc_base + PMC_TRIGGERS);
2042                         val |= UHSIC_CLR_WAKE_ALARM_P0;
2043                         writel(val, pmc_base + PMC_TRIGGERS);
2044
2045                         val = readl(base + UHSIC_PMC_WAKEUP0);
2046                         val &= ~EVENT_INT_ENB;
2047                         writel(val, base + UHSIC_PMC_WAKEUP0);
2048                         phy->remote_wakeup = true;
2049                         DBG("%s:PMC remote wakeup detected for HSIC\n", __func__);
2050                         return true;
2051                 }
2052         }
2053         return false;
2054 }
2055
2056 static int uhsic_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
2057 {
2058         DBG("%s(%d)\n", __func__, __LINE__);
2059
2060         if (!remote_wakeup)
2061                 usb_phy_wait_for_sof(phy);
2062
2063         return 0;
2064 }
2065
2066 static int uhsic_phy_post_resume(struct tegra_usb_phy *phy)
2067 {
2068         unsigned long val;
2069         void __iomem *base = phy->regs;
2070
2071         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2072         val = readl(base + USB_TXFILLTUNING);
2073         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
2074                 val = USB_FIFO_TXFILL_THRES(0x10);
2075                 writel(val, base + USB_TXFILLTUNING);
2076         }
2077
2078         return 0;
2079 }
2080
2081 static void uhsic_phy_restore_start(struct tegra_usb_phy *phy)
2082 {
2083         unsigned long val;
2084         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
2085         void __iomem *base = phy->regs;
2086
2087         val = readl(pmc_base + UTMIP_UHSIC_STATUS);
2088
2089         /* check whether we wake up from the remote resume */
2090         if (UHSIC_WALK_PTR_VAL & val) {
2091                 phy->remote_wakeup = true;
2092         } else {
2093                 DBG("%s(%d): setting pretend connect\n", __func__, __LINE__);
2094                 val = readl(base + UHSIC_CMD_CFG0);
2095                 val |= UHSIC_PRETEND_CONNECT_DETECT;
2096                 writel(val, base + UHSIC_CMD_CFG0);
2097         }
2098 }
2099
2100 static void uhsic_phy_restore_end(struct tegra_usb_phy *phy)
2101 {
2102
2103         unsigned long val;
2104         void __iomem *base = phy->regs;
2105         int wait_time_us = 25000; /* FPR should be set by this time */
2106
2107         DBG("%s(%d)\n", __func__, __LINE__);
2108
2109         /* check whether we wake up from the remote resume */
2110         if (phy->remote_wakeup) {
2111                 /* wait until FPR bit is set automatically on remote resume */
2112                 do {
2113                         val = readl(base + USB_PORTSC);
2114                         udelay(1);
2115                         if (wait_time_us == 0) {
2116                                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2117                                 uhsic_phy_post_resume(phy);
2118                                 return;
2119                         }
2120                         wait_time_us--;
2121                 } while (val & (USB_PORTSC_RESUME | USB_PORTSC_SUSP));
2122
2123                 /* disable PMC master control */
2124                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2125
2126                 /* Clear PCI and SRI bits to avoid an interrupt upon resume */
2127                 val = readl(base + USB_USBSTS);
2128                 writel(val, base + USB_USBSTS);
2129                 /* wait to avoid SOF if there is any */
2130                 if (usb_phy_reg_status_wait(base + USB_USBSTS,
2131                         USB_USBSTS_SRI, USB_USBSTS_SRI, 2500)) {
2132                         pr_warn("%s: timeout waiting for SOF\n", __func__);
2133                 }
2134                 uhsic_phy_post_resume(phy);
2135
2136                 /* Set RUN bit */
2137                 val = readl(base + USB_USBCMD);
2138                 val |= USB_USBCMD_RS;
2139                 writel(val, base + USB_USBCMD);
2140                 if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2141                                                          USB_USBCMD_RS, 2000)) {
2142                         pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2143                         return;
2144                 }
2145         } else {
2146                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2147         }
2148 }
2149
2150 static int hsic_rail_enable(struct tegra_usb_phy *phy)
2151 {
2152         int ret;
2153
2154         if (phy->hsic_reg == NULL) {
2155                 phy->hsic_reg = regulator_get(NULL, "avdd_hsic");
2156                 if (IS_ERR_OR_NULL(phy->hsic_reg)) {
2157                         pr_err("HSIC: Could not get regulator avdd_hsic\n");
2158                         phy->hsic_reg = NULL;
2159                         return PTR_ERR(phy->hsic_reg);
2160                 }
2161         }
2162
2163         ret = regulator_enable(phy->hsic_reg);
2164         if (ret < 0) {
2165                 pr_err("%s avdd_hsic could not be enabled\n", __func__);
2166                 return ret;
2167         }
2168
2169         return 0;
2170 }
2171
2172 static int hsic_rail_disable(struct tegra_usb_phy *phy)
2173 {
2174         int ret;
2175
2176         if (phy->hsic_reg == NULL) {
2177                 pr_warn("%s: unbalanced disable\n", __func__);
2178                 return -EIO;
2179         }
2180
2181         ret = regulator_disable(phy->hsic_reg);
2182         if (ret < 0) {
2183                 pr_err("HSIC regulator avdd_hsic cannot be disabled\n");
2184                 return ret;
2185         }
2186
2187         return 0;
2188 }
2189
2190 static int uhsic_phy_open(struct tegra_usb_phy *phy)
2191 {
2192         unsigned long parent_rate;
2193         int i;
2194         int ret;
2195
2196         phy->hsic_reg = NULL;
2197         ret = hsic_rail_enable(phy);
2198         if (ret < 0) {
2199                 pr_err("%s avdd_hsic could not be enabled\n", __func__);
2200                 return ret;
2201         }
2202
2203         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2204         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
2205         for (i = 0; i < ARRAY_SIZE(uhsic_freq_table); i++) {
2206                 if (uhsic_freq_table[i].freq == parent_rate) {
2207                         phy->freq = &uhsic_freq_table[i];
2208                         break;
2209                 }
2210         }
2211         if (!phy->freq) {
2212                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
2213                 return -EINVAL;
2214         }
2215
2216         uhsic_powerup_pmc_wake_detect(phy);
2217
2218         return 0;
2219 }
2220
2221 static void uhsic_phy_close(struct tegra_usb_phy *phy)
2222 {
2223         int ret;
2224
2225         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2226         uhsic_powerdown_pmc_wake_detect(phy);
2227
2228         ret = hsic_rail_disable(phy);
2229         if (ret < 0)
2230                 pr_err("%s avdd_hsic could not be disabled\n", __func__);
2231 }
2232
2233 static int uhsic_phy_irq(struct tegra_usb_phy *phy)
2234 {
2235         usb_phy_fence_read(phy);
2236         /* check if there is any remote wake event */
2237         if (uhsic_phy_remotewake_detected(phy))
2238                 pr_info("%s: uhsic remote wake detected\n", __func__);
2239         return IRQ_HANDLED;
2240 }
2241
2242 static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
2243 {
2244         unsigned long val;
2245         void __iomem *base = phy->regs;
2246
2247         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2248
2249         if (phy->phy_clk_on) {
2250                 DBG("%s(%d) inst:[%d] phy clk is already On\n",
2251                                         __func__, __LINE__, phy->inst);
2252                 return 0;
2253         }
2254
2255         val = readl(base + UHSIC_PADS_CFG1);
2256         val &= ~(UHSIC_PD_BG | UHSIC_PD_TRK | UHSIC_PD_RX |
2257                         UHSIC_PD_ZI | UHSIC_RPD_DATA | UHSIC_RPD_STROBE);
2258         val |= (UHSIC_RX_SEL | UHSIC_PD_TX);
2259         writel(val, base + UHSIC_PADS_CFG1);
2260
2261         val = readl(base + USB_SUSP_CTRL);
2262         val |= UHSIC_RESET;
2263         writel(val, base + USB_SUSP_CTRL);
2264         udelay(1);
2265
2266         val = readl(base + USB_SUSP_CTRL);
2267         val |= UHSIC_PHY_ENABLE;
2268         writel(val, base + USB_SUSP_CTRL);
2269
2270         val = readl(base + UHSIC_HSRX_CFG0);
2271         val |= UHSIC_IDLE_WAIT(HSIC_IDLE_WAIT_DELAY);
2272         val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(HSIC_ELASTIC_UNDERRUN_LIMIT);
2273         val |= UHSIC_ELASTIC_OVERRUN_LIMIT(HSIC_ELASTIC_OVERRUN_LIMIT);
2274         writel(val, base + UHSIC_HSRX_CFG0);
2275
2276         val = readl(base + UHSIC_HSRX_CFG1);
2277         val |= UHSIC_HS_SYNC_START_DLY(HSIC_SYNC_START_DELAY);
2278         writel(val, base + UHSIC_HSRX_CFG1);
2279
2280         /* WAR HSIC TX */
2281         val = readl(base + UHSIC_TX_CFG0);
2282         val &= ~UHSIC_HS_READY_WAIT_FOR_VALID;
2283         writel(val, base + UHSIC_TX_CFG0);
2284
2285         val = readl(base + UHSIC_MISC_CFG0);
2286         val |= UHSIC_SUSPEND_EXIT_ON_EDGE;
2287         /* Disable generic bus reset, to allow AP30 specific bus reset*/
2288         val |= UHSIC_DISABLE_BUSRESET;
2289         writel(val, base + UHSIC_MISC_CFG0);
2290
2291         val = readl(base + UHSIC_MISC_CFG1);
2292         val |= UHSIC_PLLU_STABLE_COUNT(phy->freq->stable_count);
2293         writel(val, base + UHSIC_MISC_CFG1);
2294
2295         val = readl(base + UHSIC_PLL_CFG1);
2296         val |= UHSIC_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
2297         val |= UHSIC_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count);
2298         writel(val, base + UHSIC_PLL_CFG1);
2299
2300         val = readl(base + USB_SUSP_CTRL);
2301         val &= ~(UHSIC_RESET);
2302         writel(val, base + USB_SUSP_CTRL);
2303         udelay(1);
2304
2305         val = readl(base + UHSIC_PADS_CFG1);
2306         val &= ~(UHSIC_PD_TX);
2307         writel(val, base + UHSIC_PADS_CFG1);
2308
2309         val = readl(base + USB_USBMODE);
2310         val |= USB_USBMODE_HOST;
2311         writel(val, base + USB_USBMODE);
2312
2313         /* Change the USB controller PHY type to HSIC */
2314         val = readl(base + HOSTPC1_DEVLC);
2315         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
2316         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2317         val &= ~HOSTPC1_DEVLC_STS;
2318         writel(val, base + HOSTPC1_DEVLC);
2319
2320         val = readl(base + USB_TXFILLTUNING);
2321         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
2322                 val = USB_FIFO_TXFILL_THRES(0x10);
2323                 writel(val, base + USB_TXFILLTUNING);
2324         }
2325
2326         val = readl(base + USB_PORTSC);
2327         val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN);
2328         writel(val, base + USB_PORTSC);
2329
2330         val = readl(base + UHSIC_PADS_CFG0);
2331         val &= ~(UHSIC_TX_RTUNEN);
2332         /* set Rtune impedance to 50 ohm */
2333         val |= UHSIC_TX_RTUNE(8);
2334         writel(val, base + UHSIC_PADS_CFG0);
2335
2336         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
2337                                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500)) {
2338                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2339                 return -ETIMEDOUT;
2340         }
2341
2342         phy->phy_clk_on = true;
2343         phy->hw_accessible = true;
2344
2345         if (phy->pmc_sleepwalk) {
2346                 DBG("%s(%d) inst:[%d] restore phy\n", __func__, __LINE__,
2347                                         phy->inst);
2348                 uhsic_phy_restore_start(phy);
2349                 usb_phy_bringup_host_controller(phy);
2350                 uhsic_phy_restore_end(phy);
2351                 phy->pmc_sleepwalk = false;
2352         }
2353
2354         return 0;
2355 }
2356
2357 static int uhsic_phy_power_off(struct tegra_usb_phy *phy)
2358 {
2359         unsigned long val;
2360         void __iomem *base = phy->regs;
2361
2362         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2363         if (!phy->phy_clk_on) {
2364                 DBG("%s(%d) inst:[%d] phy clk is already off\n",
2365                                         __func__, __LINE__, phy->inst);
2366                 return 0;
2367         }
2368
2369         phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
2370                         HOSTPC1_DEVLC_PSPD_MASK;
2371
2372         /* Disable interrupts */
2373         writel(0, base + USB_USBINTR);
2374
2375         if (phy->pmc_sleepwalk == false) {
2376                 uhsic_setup_pmc_wake_detect(phy);
2377                 phy->pmc_sleepwalk = true;
2378         }
2379
2380         val = readl(base + HOSTPC1_DEVLC);
2381         val |= HOSTPC1_DEVLC_PHCD;
2382         writel(val, base + HOSTPC1_DEVLC);
2383
2384         /* Remove power downs for HSIC from PADS CFG1 register */
2385         val = readl(base + UHSIC_PADS_CFG1);
2386         val |= (UHSIC_PD_BG |UHSIC_PD_TRK | UHSIC_PD_RX |
2387                         UHSIC_PD_ZI | UHSIC_PD_TX);
2388         writel(val, base + UHSIC_PADS_CFG1);
2389         phy->phy_clk_on = false;
2390         phy->hw_accessible = false;
2391
2392         return 0;
2393 }
2394
2395 static int uhsic_phy_bus_port_power(struct tegra_usb_phy *phy)
2396 {
2397         unsigned long val;
2398         void __iomem *base = phy->regs;
2399
2400         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2401
2402         val = readl(base + USB_USBMODE);
2403         val |= USB_USBMODE_HOST;
2404         writel(val, base + USB_USBMODE);
2405
2406         /* Change the USB controller PHY type to HSIC */
2407         val = readl(base + HOSTPC1_DEVLC);
2408         val &= ~(HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK));
2409         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2410         writel(val, base + HOSTPC1_DEVLC);
2411
2412         val = readl(base + UHSIC_MISC_CFG0);
2413         val |= UHSIC_DETECT_SHORT_CONNECT;
2414         writel(val, base + UHSIC_MISC_CFG0);
2415         udelay(1);
2416
2417         val = readl(base + UHSIC_MISC_CFG0);
2418         val |= UHSIC_FORCE_XCVR_MODE;
2419         writel(val, base + UHSIC_MISC_CFG0);
2420
2421         val = readl(base + UHSIC_PADS_CFG1);
2422         val &= ~UHSIC_RPD_STROBE;
2423         writel(val, base + UHSIC_PADS_CFG1);
2424
2425         if (phy->pdata->ops && phy->pdata->ops->port_power)
2426                 phy->pdata->ops->port_power();
2427
2428         if (usb_phy_reg_status_wait(base + UHSIC_STAT_CFG0,
2429                         UHSIC_CONNECT_DETECT, UHSIC_CONNECT_DETECT, 25000)) {
2430                 pr_err("%s: timeout waiting for UHSIC_CONNECT_DETECT\n",
2431                                                                 __func__);
2432                 return -ETIMEDOUT;
2433         }
2434
2435         return 0;
2436 }
2437
2438 static int uhsic_phy_bus_reset(struct tegra_usb_phy *phy)
2439 {
2440         unsigned long val;
2441         void __iomem *base = phy->regs;
2442
2443         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2444
2445         /* Change the USB controller PHY type to HSIC */
2446         val = readl(base + HOSTPC1_DEVLC);
2447         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
2448         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2449         val &= ~HOSTPC1_DEVLC_STS;
2450         writel(val, base + HOSTPC1_DEVLC);
2451         /* wait here, otherwise HOSTPC1_DEVLC_PSPD will timeout */
2452         mdelay(5);
2453
2454         val = readl(base + USB_PORTSC);
2455         val |= USB_PORTSC_PTC(5);
2456         writel(val, base + USB_PORTSC);
2457         udelay(2);
2458
2459         val = readl(base + USB_PORTSC);
2460         val &= ~(USB_PORTSC_PTC(~0));
2461         writel(val, base + USB_PORTSC);
2462         udelay(2);
2463
2464         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_LS(0),
2465                                                  0, 2000)) {
2466                 pr_err("%s: timeout waiting for USB_PORTSC_LS\n", __func__);
2467                 return -ETIMEDOUT;
2468         }
2469
2470         /* Poll until CCS is enabled */
2471         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
2472                                                  USB_PORTSC_CCS, 2000)) {
2473                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
2474                 return -ETIMEDOUT;
2475         }
2476
2477         if (usb_phy_reg_status_wait(base + HOSTPC1_DEVLC,
2478                         HOSTPC1_DEVLC_PSPD(2),
2479                         HOSTPC1_DEVLC_PSPD(2), 2000) < 0) {
2480                 pr_err("%s: timeout waiting hsic high speed configuration\n",
2481                                                 __func__);
2482                         return -ETIMEDOUT;
2483         }
2484
2485         val = readl(base + USB_USBCMD);
2486         val &= ~USB_USBCMD_RS;
2487         writel(val, base + USB_USBCMD);
2488
2489         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
2490                                                  USB_USBSTS_HCH, 2000)) {
2491                 pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
2492                 return -ETIMEDOUT;
2493         }
2494
2495         val = readl(base + UHSIC_PADS_CFG1);
2496         val &= ~UHSIC_RPU_STROBE;
2497         val |= UHSIC_RPD_STROBE;
2498         writel(val, base + UHSIC_PADS_CFG1);
2499
2500         mdelay(50);
2501
2502         val = readl(base + UHSIC_PADS_CFG1);
2503         val &= ~UHSIC_RPD_STROBE;
2504         val |= UHSIC_RPU_STROBE;
2505         writel(val, base + UHSIC_PADS_CFG1);
2506
2507         val = readl(base + USB_USBCMD);
2508         val |= USB_USBCMD_RS;
2509         writel(val, base + USB_USBCMD);
2510
2511         val = readl(base + UHSIC_PADS_CFG1);
2512         val &= ~UHSIC_RPU_STROBE;
2513         writel(val, base + UHSIC_PADS_CFG1);
2514
2515         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2516                                                  USB_USBCMD_RS, 2000)) {
2517                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2518                 return -ETIMEDOUT;
2519         }
2520
2521         return 0;
2522 }
2523
2524 int uhsic_phy_resume(struct tegra_usb_phy *phy)
2525 {
2526         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2527
2528         return 0;
2529 }
2530
2531 static void ulpi_set_trimmer(struct tegra_usb_phy *phy)
2532 {
2533         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2534         void __iomem *base = phy->regs;
2535         unsigned long val;
2536
2537         val = ULPI_DATA_TRIMMER_SEL(config->data_trimmer);
2538         val |= ULPI_STPDIRNXT_TRIMMER_SEL(config->stpdirnxt_trimmer);
2539         val |= ULPI_DIR_TRIMMER_SEL(config->dir_trimmer);
2540         writel(val, base + ULPI_TIMING_CTRL_1);
2541         udelay(10);
2542
2543         val |= ULPI_DATA_TRIMMER_LOAD;
2544         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
2545         val |= ULPI_DIR_TRIMMER_LOAD;
2546         writel(val, base + ULPI_TIMING_CTRL_1);
2547 }
2548
2549 static void reset_utmip_uhsic(void __iomem *base)
2550 {
2551         unsigned long val;
2552
2553         val = readl(base + USB_SUSP_CTRL);
2554         val |= UHSIC_RESET;
2555         writel(val, base + USB_SUSP_CTRL);
2556
2557         val = readl(base + USB_SUSP_CTRL);
2558         val |= UTMIP_RESET;
2559         writel(val, base + USB_SUSP_CTRL);
2560 }
2561
2562 static void ulpi_set_host(void __iomem *base)
2563 {
2564         unsigned long val;
2565
2566         val = readl(base + USB_USBMODE);
2567         val &= ~USB_USBMODE_MASK;
2568         val |= USB_USBMODE_HOST;
2569         writel(val, base + USB_USBMODE);
2570
2571         val = readl(base + HOSTPC1_DEVLC);
2572         val |= HOSTPC1_DEVLC_PTS(2);
2573         writel(val, base + HOSTPC1_DEVLC);
2574 }
2575
2576 static inline void ulpi_pinmux_bypass(struct tegra_usb_phy *phy, bool enable)
2577 {
2578         unsigned long val;
2579         void __iomem *base = phy->regs;
2580
2581         val = readl(base + ULPI_TIMING_CTRL_0);
2582
2583         if (enable)
2584                 val |= ULPI_OUTPUT_PINMUX_BYP;
2585         else
2586                 val &= ~ULPI_OUTPUT_PINMUX_BYP;
2587
2588         writel(val, base + ULPI_TIMING_CTRL_0);
2589 }
2590
2591 static inline void ulpi_null_phy_set_tristate(bool enable)
2592 {
2593 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2594         int tristate = (enable) ? TEGRA_TRI_TRISTATE : TEGRA_TRI_NORMAL;
2595
2596         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA0, tristate);
2597         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA1, tristate);
2598         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA2, tristate);
2599         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA3, tristate);
2600         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA4, tristate);
2601         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA5, tristate);
2602         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA6, tristate);
2603         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA7, tristate);
2604         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_NXT, tristate);
2605
2606         if (enable)
2607                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR, tristate);
2608 #endif
2609 }
2610
2611 static void ulpi_null_phy_obs_read(void)
2612 {
2613         static void __iomem *apb_misc;
2614         unsigned slv0_obs, s2s_obs;
2615
2616         if (!apb_misc)
2617                 apb_misc = ioremap(TEGRA_APB_MISC_BASE, TEGRA_APB_MISC_SIZE);
2618
2619         writel(0x80d1003c, apb_misc + APB_MISC_GP_OBSCTRL_0);
2620         slv0_obs = readl(apb_misc + APB_MISC_GP_OBSDATA_0);
2621
2622         writel(0x80d10040, apb_misc + APB_MISC_GP_OBSCTRL_0);
2623         s2s_obs = readl(apb_misc + APB_MISC_GP_OBSDATA_0);
2624
2625         pr_debug("slv0 obs: %08x\ns2s obs: %08x\n", slv0_obs, s2s_obs);
2626 }
2627
2628 static const struct gpio ulpi_gpios[] = {
2629         {ULPI_STP, GPIOF_IN, "ULPI_STP"},
2630         {ULPI_DIR, GPIOF_OUT_INIT_LOW, "ULPI_DIR"},
2631         {ULPI_D0, GPIOF_OUT_INIT_LOW, "ULPI_D0"},
2632         {ULPI_D1, GPIOF_OUT_INIT_LOW, "ULPI_D1"},
2633 };
2634
2635 static int ulpi_null_phy_open(struct tegra_usb_phy *phy)
2636 {
2637         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2638         int ret;
2639
2640         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2641
2642         ret = gpio_request_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
2643         if (ret)
2644                 return ret;
2645
2646         if (gpio_is_valid(config->phy_restore_gpio)) {
2647                 ret = gpio_request(config->phy_restore_gpio, "phy_restore");
2648                 if (ret)
2649                         goto err_gpio_free;
2650
2651                 gpio_direction_input(config->phy_restore_gpio);
2652         }
2653
2654         tegra_periph_reset_assert(phy->ctrlr_clk);
2655         udelay(10);
2656         tegra_periph_reset_deassert(phy->ctrlr_clk);
2657
2658         return 0;
2659
2660 err_gpio_free:
2661         gpio_free_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
2662         return ret;
2663 }
2664
2665 static void ulpi_null_phy_close(struct tegra_usb_phy *phy)
2666 {
2667         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2668
2669         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2670
2671         if (gpio_is_valid(config->phy_restore_gpio))
2672                 gpio_free(config->phy_restore_gpio);
2673
2674         gpio_free_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
2675 }
2676
2677 static int ulpi_null_phy_power_off(struct tegra_usb_phy *phy)
2678 {
2679         unsigned int val;
2680         void __iomem *base = phy->regs;
2681
2682         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2683
2684         if (!phy->phy_clk_on) {
2685                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
2686                                                         __LINE__, phy->inst);
2687                 return 0;
2688         }
2689
2690         phy->phy_clk_on = false;
2691         phy->hw_accessible = false;
2692         ulpi_null_phy_set_tristate(true);
2693         val = readl(base + ULPIS2S_CTRL);
2694         val &= ~ULPIS2S_PLLU_MASTER_BLASTER60;
2695         writel(val, base + ULPIS2S_CTRL);
2696         return 0;
2697 }
2698
2699 /* NOTE: this function must be called before ehci reset */
2700 static int ulpi_null_phy_init(struct tegra_usb_phy *phy)
2701 {
2702         unsigned long val;
2703         void __iomem *base = phy->regs;
2704
2705         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2706         val = readl(base + ULPIS2S_CTRL);
2707         val |=  ULPIS2S_SLV0_CLAMP_XMIT;
2708         writel(val, base + ULPIS2S_CTRL);
2709
2710         val = readl(base + USB_SUSP_CTRL);
2711         val |= ULPIS2S_SLV0_RESET;
2712         writel(val, base + USB_SUSP_CTRL);
2713         udelay(10);
2714
2715         return 0;
2716 }
2717
2718 static int ulpi_null_phy_irq(struct tegra_usb_phy *phy)
2719 {
2720         unsigned long val;
2721         void __iomem *base = phy->regs;
2722
2723         usb_phy_fence_read(phy);
2724         if (phy->bus_reseting){
2725                 val = readl(base + USB_USBCMD);
2726                 val |= USB_USBCMD_RS;
2727                 writel(val, base + USB_USBCMD);
2728                 phy->bus_reseting = false;
2729         }
2730         return IRQ_HANDLED;
2731 }
2732
2733 /* NOTE: this function must be called after ehci reset */
2734 static int ulpi_null_phy_cmd_reset(struct tegra_usb_phy *phy)
2735 {
2736         unsigned long val;
2737         void __iomem *base = phy->regs;
2738
2739         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2740         ulpi_set_host(base);
2741
2742         /* remove slave0 reset */
2743         val = readl(base + USB_SUSP_CTRL);
2744         val &= ~ULPIS2S_SLV0_RESET;
2745         writel(val, base + USB_SUSP_CTRL);
2746
2747         val = readl(base + ULPIS2S_CTRL);
2748         val &=  ~ULPIS2S_SLV0_CLAMP_XMIT;
2749         writel(val, base + ULPIS2S_CTRL);
2750         udelay(10);
2751
2752         return 0;
2753 }
2754
2755 static int ulpi_phy_bus_reset(struct tegra_usb_phy *phy)
2756 {
2757         unsigned long val;
2758         void __iomem *base = phy->regs;
2759
2760         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2761
2762         /*DISABLE RUN BIT */
2763
2764         val = readl(base + USB_USBCMD);
2765         val &= ~USB_USBCMD_RS;
2766         writel(val, base + USB_USBCMD);
2767         phy->bus_reseting = true;
2768
2769         return 0;
2770 }
2771
2772 static int ulpi_null_phy_restore(struct tegra_usb_phy *phy)
2773 {
2774         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2775         unsigned long timeout;
2776         int ulpi_stp = ULPI_STP;
2777
2778         if (gpio_is_valid(config->phy_restore_gpio))
2779                 ulpi_stp = config->phy_restore_gpio;
2780
2781         /* disable ULPI pinmux bypass */
2782         ulpi_pinmux_bypass(phy, false);
2783
2784         /* driving linstate by GPIO */
2785         gpio_set_value(ULPI_D0, 0);
2786         gpio_set_value(ULPI_D1, 0);
2787
2788         /* driving DIR high */
2789         gpio_set_value(ULPI_DIR, 1);
2790
2791         /* remove ULPI tristate */
2792         ulpi_null_phy_set_tristate(false);
2793
2794         /* wait for STP high */
2795         timeout = jiffies + msecs_to_jiffies(25);
2796
2797         while (!gpio_get_value(ulpi_stp)) {
2798                 if (time_after(jiffies, timeout)) {
2799                         pr_warn("phy restore timeout\n");
2800                         return 1;
2801                 }
2802         }
2803
2804         return 0;
2805 }
2806
2807 static int ulpi_null_phy_lp0_resume(struct tegra_usb_phy *phy)
2808 {
2809         unsigned long val;
2810         void __iomem *base = phy->regs;
2811
2812         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2813         ulpi_null_phy_init(phy);
2814
2815         val = readl(base + USB_USBCMD);
2816         val |= USB_CMD_RESET;
2817         writel(val, base + USB_USBCMD);
2818
2819         if (usb_phy_reg_status_wait(base + USB_USBCMD,
2820                 USB_CMD_RESET, 0, 2500) < 0) {
2821                 pr_err("%s: timeout waiting for reset\n", __func__);
2822         }
2823
2824         ulpi_null_phy_cmd_reset(phy);
2825
2826         val = readl(base + USB_USBCMD);
2827         val |= USB_USBCMD_RS;
2828         writel(val, base + USB_USBCMD);
2829         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2830                                                  USB_USBCMD_RS, 2000)) {
2831                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2832                 return -ETIMEDOUT;
2833         }
2834
2835         /* Enable Port Power */
2836         val = readl(base + USB_PORTSC);
2837         val |= USB_PORTSC_PP;
2838         writel(val, base + USB_PORTSC);
2839         udelay(10);
2840
2841         ulpi_null_phy_restore(phy);
2842
2843         return 0;
2844 }
2845
2846 static int ulpi_null_phy_power_on(struct tegra_usb_phy *phy)
2847 {
2848         unsigned long val;
2849         void __iomem *base = phy->regs;
2850         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2851
2852         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2853         if (phy->phy_clk_on) {
2854                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
2855                                                         __LINE__, phy->inst);
2856                 return 0;
2857         }
2858         reset_utmip_uhsic(base);
2859
2860         /* remove ULPI PADS CLKEN reset */
2861         val = readl(base + USB_SUSP_CTRL);
2862         val &= ~ULPI_PADS_CLKEN_RESET;
2863         writel(val, base + USB_SUSP_CTRL);
2864         udelay(10);
2865
2866         val = readl(base + ULPI_TIMING_CTRL_0);
2867         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
2868         writel(val, base + ULPI_TIMING_CTRL_0);
2869
2870         val = readl(base + USB_SUSP_CTRL);
2871         val |= ULPI_PHY_ENABLE;
2872         writel(val, base + USB_SUSP_CTRL);
2873         udelay(10);
2874
2875         /* set timming parameters */
2876         val = readl(base + ULPI_TIMING_CTRL_0);
2877         val |= ULPI_SHADOW_CLK_LOOPBACK_EN;
2878         val &= ~ULPI_SHADOW_CLK_SEL;
2879         val &= ~ULPI_LBK_PAD_EN;
2880         val |= ULPI_SHADOW_CLK_DELAY(config->shadow_clk_delay);
2881         val |= ULPI_CLOCK_OUT_DELAY(config->clock_out_delay);
2882         val |= ULPI_LBK_PAD_E_INPUT_OR;
2883         writel(val, base + ULPI_TIMING_CTRL_0);
2884
2885         writel(0, base + ULPI_TIMING_CTRL_1);
2886         udelay(10);
2887
2888         /* start internal 60MHz clock */
2889         val = readl(base + ULPIS2S_CTRL);
2890         val |= ULPIS2S_ENA;
2891         val |= ULPIS2S_SUPPORT_DISCONNECT;
2892         val |= ULPIS2S_SPARE((phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) ? 3 : 1);
2893         val |= ULPIS2S_PLLU_MASTER_BLASTER60;
2894         writel(val, base + ULPIS2S_CTRL);
2895
2896         /* select ULPI_CORE_CLK_SEL to SHADOW_CLK */
2897         val = readl(base + ULPI_TIMING_CTRL_0);
2898         val |= ULPI_CORE_CLK_SEL;
2899         writel(val, base + ULPI_TIMING_CTRL_0);
2900         udelay(10);
2901
2902         /* enable ULPI null phy clock - can't set the trimmers before this */
2903         val = readl(base + ULPI_TIMING_CTRL_0);
2904         val |= ULPI_CLK_OUT_ENA;
2905         writel(val, base + ULPI_TIMING_CTRL_0);
2906         udelay(10);
2907
2908         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
2909                                                  USB_PHY_CLK_VALID, 2500)) {
2910                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2911                 return -ETIMEDOUT;
2912         }
2913
2914         /* set ULPI trimmers */
2915         ulpi_set_trimmer(phy);
2916
2917         ulpi_set_host(base);
2918
2919         /* remove slave0 reset */
2920         val = readl(base + USB_SUSP_CTRL);
2921         val &= ~ULPIS2S_SLV0_RESET;
2922         writel(val, base + USB_SUSP_CTRL);
2923
2924         /* remove slave1 and line reset */
2925         val = readl(base + USB_SUSP_CTRL);
2926         val &= ~ULPIS2S_SLV1_RESET;
2927         val &= ~ULPIS2S_LINE_RESET;
2928
2929         /* remove ULPI PADS reset */
2930         val &= ~ULPI_PADS_RESET;
2931         writel(val, base + USB_SUSP_CTRL);
2932
2933         if (!phy->ulpi_clk_padout_ena) {
2934                 val = readl(base + ULPI_TIMING_CTRL_0);
2935                 val |= ULPI_CLK_PADOUT_ENA;
2936                 writel(val, base + ULPI_TIMING_CTRL_0);
2937                 phy->ulpi_clk_padout_ena = true;
2938         } else {
2939                 if (!readl(base + USB_ASYNCLISTADDR))
2940                         ulpi_null_phy_lp0_resume(phy);
2941         }
2942         udelay(10);
2943
2944         phy->bus_reseting = false;
2945         phy->phy_clk_on = true;
2946         phy->hw_accessible = true;
2947
2948         return 0;
2949 }
2950
2951 static int ulpi_null_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
2952 {
2953         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2954         ulpi_null_phy_obs_read();
2955         usb_phy_wait_for_sof(phy);
2956         ulpi_null_phy_obs_read();
2957         return 0;
2958 }
2959
2960 static int ulpi_null_phy_post_resume(struct tegra_usb_phy *phy)
2961 {
2962         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2963         ulpi_null_phy_obs_read();
2964         return 0;
2965 }
2966
2967 static int ulpi_null_phy_resume(struct tegra_usb_phy *phy)
2968 {
2969         unsigned long val;
2970         void __iomem *base = phy->regs;
2971
2972         if (!readl(base + USB_ASYNCLISTADDR)) {
2973                 /* enable ULPI CLK output pad */
2974                 val = readl(base + ULPI_TIMING_CTRL_0);
2975                 val |= ULPI_CLK_PADOUT_ENA;
2976                 writel(val, base + ULPI_TIMING_CTRL_0);
2977
2978                 /* enable ULPI pinmux bypass */
2979                 ulpi_pinmux_bypass(phy, true);
2980                 udelay(5);
2981 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2982                 /* remove DIR tristate */
2983                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR,
2984                                           TEGRA_TRI_NORMAL);
2985 #endif
2986         }
2987         return 0;
2988 }
2989
2990
2991
2992 static struct tegra_usb_phy_ops utmi_phy_ops = {
2993         .open           = utmi_phy_open,
2994         .close          = utmi_phy_close,
2995         .irq            = utmi_phy_irq,
2996         .power_on       = utmi_phy_power_on,
2997         .power_off      = utmi_phy_power_off,
2998         .pre_resume = utmi_phy_pre_resume,
2999         .resume = utmi_phy_resume,
3000         .post_resume    = utmi_phy_post_resume,
3001         .charger_detect = utmi_phy_charger_detect,
3002         .post_suspend   = phy_post_suspend,
3003 };
3004
3005 static struct tegra_usb_phy_ops uhsic_phy_ops = {
3006         .open           = uhsic_phy_open,
3007         .close          = uhsic_phy_close,
3008         .irq            = uhsic_phy_irq,
3009         .power_on       = uhsic_phy_power_on,
3010         .power_off      = uhsic_phy_power_off,
3011         .pre_resume = uhsic_phy_pre_resume,
3012         .resume = uhsic_phy_resume,
3013         .post_resume = uhsic_phy_post_resume,
3014         .port_power = uhsic_phy_bus_port_power,
3015         .bus_reset      = uhsic_phy_bus_reset,
3016         .post_suspend   = phy_post_suspend,
3017 };
3018
3019 static struct tegra_usb_phy_ops ulpi_null_phy_ops = {
3020         .open           = ulpi_null_phy_open,
3021         .close          = ulpi_null_phy_close,
3022         .init           = ulpi_null_phy_init,
3023         .irq            = ulpi_null_phy_irq,
3024         .power_on       = ulpi_null_phy_power_on,
3025         .power_off      = ulpi_null_phy_power_off,
3026         .pre_resume = ulpi_null_phy_pre_resume,
3027         .resume = ulpi_null_phy_resume,
3028         .post_resume = ulpi_null_phy_post_resume,
3029         .reset          = ulpi_null_phy_cmd_reset,
3030         .post_suspend   = phy_post_suspend,
3031         .bus_reset      = ulpi_phy_bus_reset,
3032 };
3033
3034 static struct tegra_usb_phy_ops ulpi_link_phy_ops;
3035 static struct tegra_usb_phy_ops icusb_phy_ops;
3036
3037 static struct tegra_usb_phy_ops *phy_ops[] = {
3038         [TEGRA_USB_PHY_INTF_UTMI] = &utmi_phy_ops,
3039         [TEGRA_USB_PHY_INTF_ULPI_LINK] = &ulpi_link_phy_ops,
3040         [TEGRA_USB_PHY_INTF_ULPI_NULL] = &ulpi_null_phy_ops,
3041         [TEGRA_USB_PHY_INTF_HSIC] = &uhsic_phy_ops,
3042         [TEGRA_USB_PHY_INTF_ICUSB] = &icusb_phy_ops,
3043 };
3044
3045 int tegra3_usb_phy_init_ops(struct tegra_usb_phy *phy)
3046 {
3047         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
3048
3049         phy->ops = phy_ops[phy->pdata->phy_intf];
3050
3051         /* FIXME: uncommenting below line to make USB host mode fail*/
3052         /* usb_phy_power_down_pmc(); */
3053
3054         return 0;
3055 }