Arm: p1852: dvfs: Added ASIC SKUs as per updated POR
[linux-2.6.git] / arch / arm / mach-tegra / tegra3_speedo.c
1 /*
2  * arch/arm/mach-tegra/tegra3_speedo.c
3  *
4  * Copyright (c) 2011, NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/io.h>
23 #include <linux/err.h>
24 #include <linux/bug.h>                  /* For BUG_ON.  */
25
26 #include <mach/iomap.h>
27 #include <mach/tegra_fuse.h>
28 #include <mach/hardware.h>
29
30 #include "fuse.h"
31
32 #define CORE_PROCESS_CORNERS_NUM        1
33 #define CPU_PROCESS_CORNERS_NUM 7
34
35 #define FUSE_SPEEDO_CALIB_0     0x114
36 #define FUSE_PACKAGE_INFO       0X1FC
37 #define FUSE_TEST_PROG_VER      0X128
38 #define FUSE_SPARE_BIT_58       0x32c
39 #define FUSE_SPARE_BIT_59       0x330
40 #define FUSE_SPARE_BIT_60       0x334
41 #define FUSE_SPARE_BIT_61       0x338
42 #define FUSE_SPARE_BIT_62       0x33c
43 #define FUSE_SPARE_BIT_63       0x340
44 #define FUSE_SPARE_BIT_64       0x344
45 #define FUSE_SPARE_BIT_65       0x348
46
47 #define G_SPEEDO_BIT_MINUS1     FUSE_SPARE_BIT_58
48 #define G_SPEEDO_BIT_MINUS1_R   FUSE_SPARE_BIT_59
49 #define G_SPEEDO_BIT_MINUS2     FUSE_SPARE_BIT_60
50 #define G_SPEEDO_BIT_MINUS2_R   FUSE_SPARE_BIT_61
51 #define LP_SPEEDO_BIT_MINUS1    FUSE_SPARE_BIT_62
52 #define LP_SPEEDO_BIT_MINUS1_R  FUSE_SPARE_BIT_63
53 #define LP_SPEEDO_BIT_MINUS2    FUSE_SPARE_BIT_64
54 #define LP_SPEEDO_BIT_MINUS2_R  FUSE_SPARE_BIT_65
55
56 /* Maximum speedo levels for each core process corner */
57 static const u32 core_process_speedos[][CORE_PROCESS_CORNERS_NUM] = {
58 /* proc_id 0 */
59         {180}, /* [0]: soc_speedo_id 0: any A01 */
60
61 /* T30 family */
62         {170}, /* [1]: soc_speedo_id 1: AP30 */
63         {195}, /* [2]: soc_speedo_id 2: T30  */
64         {180}, /* [3]: soc_speedo_id 2: T30S */
65
66 /* Characterization SKUs */
67         {168}, /* [4]: soc_speedo_id 1: AP30 char */
68         {192}, /* [5]: soc_speedo_id 2: T30  char */
69         {180}, /* [6]: soc_speedo_id 2: T30S char */
70
71 /* T33 family */
72         {170}, /* [7]: soc_speedo_id = 1 - AP33 */
73         {195}, /* [8]: soc_speedo_id = 2 - T33  */
74         {180}, /* [9]: soc_speedo_id = 2 - T33S/AP37 */
75
76 /* T30 'L' family */
77         {180}, /* [10]: soc_speedo_id 1: T30L */
78         {180}, /* [11]: soc_speedo_id 1: T30SL */
79
80 /* T30 Automotives */
81         {185}, /* [12]: soc_speedo_id = 3 - Automotives */
82         {185}, /* [13]: soc_speedo_id = 3 - Automotives */
83
84 /* T37 Family*/
85         {210}, /* [14]: soc_speedo_id 2: T37 */
86 };
87
88 /* Maximum speedo levels for each CPU process corner */
89 static const u32 cpu_process_speedos[][CPU_PROCESS_CORNERS_NUM] = {
90 /* proc_id 0    1    2    3    4*/
91         {306, 338, 360, 376, UINT_MAX}, /* [0]: cpu_speedo_id 0: any A01 */
92
93 /* T30 family */
94         {295, 336, 358, 375, UINT_MAX}, /* [1]: cpu_speedo_id 1: AP30 */
95         {325, 325, 358, 375, UINT_MAX}, /* [2]: cpu_speedo_id 2: T30  */
96         {325, 325, 358, 375, UINT_MAX}, /* [3]: cpu_speedo_id 3: T30S */
97
98 /* Characterization SKUs */
99         {292, 324, 348, 364, UINT_MAX}, /* [4]: cpu_speedo_id 1: AP30char */
100         {324, 324, 348, 364, UINT_MAX}, /* [5]: cpu_speedo_id 2: T30char  */
101         {324, 324, 348, 364, UINT_MAX}, /* [6]: cpu_speedo_id 3: T30Schar */
102
103 /* T33 family */
104         {295, 336, 358, 375, UINT_MAX},      /* [7]: cpu_speedo_id: 4: AP33 */
105         {358, 358, 358, 358, 397, UINT_MAX}, /* [8]: cpu_speedo_id: 5: T33  */
106         {364, 364, 364, 364, 397, UINT_MAX}, /* [9]: cpu_speedo_id: 6/12: T33S/AP37 */
107
108 /* T30 'L' family */
109         {295, 336, 358, 375, 391, UINT_MAX}, /* [10]: cpu_speedo_id 7: T30L  */
110         {295, 336, 358, 375, 391, UINT_MAX}, /* [11]: cpu_speedo_id 8: T30SL */
111
112 /* T30 Automotives */
113         /* threshold_index 12: cpu_speedo_id 9 & 10
114          * 0,1,2 values correspond to speedo_id  9/14
115          * 3,4,5 values correspond to speedo_id 10/15*/
116         {300, 311, 360, 371, 381, 415, 431},
117         {300, 311, 410, 431, UINT_MAX}, /* [13]: cpu_speedo_id 11: T30 auto */
118
119 /* T37 family */
120         {358, 358, 358, 358, 397, UINT_MAX}, /* [14]: cpu_speedo_id 13: T37 */
121 };
122
123 /*
124  * Common speedo_value array threshold index for both core_process_speedos and
125  * cpu_process_speedos arrays. Make sure these two arrays are always in synch.
126  */
127 static int threshold_index;
128
129 static int cpu_process_id;
130 static int core_process_id;
131 static int cpu_speedo_id;
132 static int soc_speedo_id;
133 static int package_id;
134
135 static void fuse_speedo_calib(u32 *speedo_g, u32 *speedo_lp)
136 {
137         u32 reg;
138         int ate_ver, bit_minus1, bit_minus2;
139
140         BUG_ON(!speedo_g || !speedo_lp);
141         reg = tegra_fuse_readl(FUSE_SPEEDO_CALIB_0);
142
143         /* Speedo LP = Lower 16-bits Multiplied by 4 */
144         *speedo_lp = (reg & 0xFFFF) * 4;
145
146         /* Speedo G = Upper 16-bits Multiplied by 4 */
147         *speedo_g = ((reg >> 16) & 0xFFFF) * 4;
148
149         if (tegra_fuse_get_revision(&ate_ver))
150                 return;
151         pr_info("%s: ATE prog ver %d.%d\n", __func__, ate_ver/10, ate_ver%10);
152
153         pr_debug("CPU speedo base value %u (0x%3x)\n", *speedo_g, *speedo_g);
154         pr_debug("Core speedo base value %u (0x%3x)\n", *speedo_lp, *speedo_lp);
155
156         if (ate_ver >= 26) {
157                 /* read lower 2 bits of LP speedo from spare fuses */
158                 bit_minus1 = tegra_fuse_readl(LP_SPEEDO_BIT_MINUS1) & 0x1;
159                 bit_minus1 |= tegra_fuse_readl(LP_SPEEDO_BIT_MINUS1_R) & 0x1;
160                 bit_minus2 = tegra_fuse_readl(LP_SPEEDO_BIT_MINUS2) & 0x1;
161                 bit_minus2 |= tegra_fuse_readl(LP_SPEEDO_BIT_MINUS2_R) & 0x1;
162                 *speedo_lp |= (bit_minus1 << 1) | bit_minus2;
163
164                 /* read lower 2 bits of G speedo from spare fuses */
165                 bit_minus1 = tegra_fuse_readl(G_SPEEDO_BIT_MINUS1) & 0x1;
166                 bit_minus1 |= tegra_fuse_readl(G_SPEEDO_BIT_MINUS1_R) & 0x1;
167                 bit_minus2 = tegra_fuse_readl(G_SPEEDO_BIT_MINUS2) & 0x1;
168                 bit_minus2 |= tegra_fuse_readl(G_SPEEDO_BIT_MINUS2_R) & 0x1;
169                 *speedo_g |= (bit_minus1 << 1) | bit_minus2;
170         } else {
171                 /* set lower 2 bits for speedo ate-ver independent comparison */
172                 *speedo_lp |= 0x3;
173                 *speedo_g |= 0x3;
174         }
175 }
176
177 static void rev_sku_to_speedo_ids(int rev, int sku)
178 {
179         switch (rev) {
180         case TEGRA_REVISION_A01: /* any A01 */
181                 cpu_speedo_id = 0;
182                 soc_speedo_id = 0;
183                 threshold_index = 0;
184                 break;
185
186         case TEGRA_REVISION_A02:
187         case TEGRA_REVISION_A03:
188                 switch (sku) {
189                 case 0x87: /* AP30 */
190                 case 0x82: /* T30V */
191                         cpu_speedo_id = 1;
192                         soc_speedo_id = 1;
193                         threshold_index = 1;
194                         break;
195
196                 case 0x81: /* T30 */
197                         switch (package_id) {
198                         case 1: /* MID => T30 */
199                                 cpu_speedo_id = 2;
200                                 soc_speedo_id = 2;
201                                 threshold_index = 2;
202                                 break;
203                         case 2: /* DSC => AP33 */
204                                 cpu_speedo_id = 4;
205                                 soc_speedo_id = 1;
206                                 threshold_index = 7;
207                                 break;
208                         default:
209                                 pr_err("Tegra3 Rev-A02: Reserved pkg: %d\n",
210                                        package_id);
211                                 BUG();
212                                 break;
213                         }
214                         break;
215
216                 case 0x80: /* T33 or T33S */
217                         switch (package_id) {
218                         case 1: /* MID => T33 */
219                                 cpu_speedo_id = 5;
220                                 soc_speedo_id = 2;
221                                 threshold_index = 8;
222                                 break;
223                         case 2: /* DSC => T33S */
224                                 cpu_speedo_id = 6;
225                                 soc_speedo_id = 2;
226                                 threshold_index = 9;
227                                 break;
228                         default:
229                                 pr_err("Tegra3 Rev-A02: Reserved pkg: %d\n",
230                                        package_id);
231                                 BUG();
232                                 break;
233                         }
234                         break;
235
236                 case 0x83: /* T30L or T30S */
237                         switch (package_id) {
238                         case 1: /* MID => T30L */
239                                 cpu_speedo_id = 7;
240                                 soc_speedo_id = 1;
241                                 threshold_index = 10;
242                                 break;
243                         case 2: /* DSC => T30S */
244                                 cpu_speedo_id = 3;
245                                 soc_speedo_id = 2;
246                                 threshold_index = 3;
247                                 break;
248                         default:
249                                 pr_err("Tegra3 Rev-A02: Reserved pkg: %d\n",
250                                        package_id);
251                                 BUG();
252                                 break;
253                         }
254                         break;
255
256                 case 0x8F: /* T30SL */
257                         cpu_speedo_id = 8;
258                         soc_speedo_id = 1;
259                         threshold_index = 11;
260                         break;
261
262                 case 0xA0: /* T37 or A37 */
263                         switch (package_id) {
264                         case 1: /* MID => T37 */
265                                 cpu_speedo_id = 13;
266                                 soc_speedo_id = 2;
267                                 threshold_index = 14;
268                                 break;
269                         case 2: /* DSC => AP37 */
270                                 cpu_speedo_id = 12;
271                                 soc_speedo_id = 2;
272                                 threshold_index = 9;
273                                 break;
274                         default:
275                                 pr_err("Tegra3 Rev-A02: Reserved pkg: %d\n",
276                                                 package_id);
277                                 BUG();
278                                 break;
279                         }
280                         break;
281
282 /* Characterization SKUs */
283                 case 0x08: /* AP30 char */
284                         cpu_speedo_id = 1;
285                         soc_speedo_id = 1;
286                         threshold_index = 4;
287                         break;
288                 case 0x02: /* T30 char */
289                         cpu_speedo_id = 2;
290                         soc_speedo_id = 2;
291                         threshold_index = 5;
292                         break;
293                 case 0x04: /* T30S char */
294                         cpu_speedo_id = 3;
295                         soc_speedo_id = 2;
296                         threshold_index = 6;
297                         break;
298
299                 case 0x91: /* T30AGS-Ax */
300                 case 0xb0: /* T30IQS-Ax */
301                 case 0xb1: /* T30MQS-Ax */
302                 case 0x90: /* T30AQS-Ax */
303                         soc_speedo_id = 3;
304                         threshold_index = 12;
305                         break;
306                 case 0x93: /* T30AG-Ax */
307                         cpu_speedo_id = 11;
308                         soc_speedo_id = 3;
309                         threshold_index = 13;
310                         break;
311                 case 0:    /* ENG - check package_id */
312                         pr_info("Tegra3 ENG SKU: Checking package_id\n");
313                         switch (package_id) {
314                         case 1: /* MID => assume T30 */
315                                 cpu_speedo_id = 2;
316                                 soc_speedo_id = 2;
317                                 threshold_index = 2;
318                                 break;
319                         case 2: /* DSC => assume T30S */
320                                 cpu_speedo_id = 3;
321                                 soc_speedo_id = 2;
322                                 threshold_index = 3;
323                                 break;
324                         default:
325                                 pr_err("Tegra3 Rev-A02: Reserved pkg: %d\n",
326                                        package_id);
327                                 BUG();
328                                 break;
329                         }
330                         break;
331
332                 default:
333                         /* FIXME: replace with BUG() when all SKU's valid */
334                         pr_err("Tegra3 Rev-A02: Unknown SKU %d\n", sku);
335                         cpu_speedo_id = 0;
336                         soc_speedo_id = 0;
337                         threshold_index = 0;
338                         break;
339                 }
340                 break;
341         default:
342                 BUG();
343                 break;
344         }
345 }
346
347 void tegra_init_speedo_data(void)
348 {
349         u32 cpu_speedo_val, core_speedo_val;
350         int iv;
351         int fuse_sku = tegra_sku_id;
352         int sku_override = tegra_get_sku_override();
353         int new_sku = fuse_sku;
354
355         /* Package info: 4 bits - 0,3:reserved 1:MID 2:DSC */
356         package_id = tegra_fuse_readl(FUSE_PACKAGE_INFO) & 0x0F;
357
358         /* Arrays must be of equal size - each index corresponds to a SKU */
359         BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
360                ARRAY_SIZE(core_process_speedos));
361
362         /* SKU Overrides
363         * T33   => T30, T30L
364         * T33S  => T30S, T30SL
365         * T30   => T30L
366         * T30S  => T30SL
367         * AP33  => AP30
368         */
369         switch (sku_override) {
370         case 1:
371                 /* Base sku override */
372                 if (fuse_sku == 0x80) {
373                         if (package_id == 1) {
374                                 /* T33 to T30 */
375                                 pr_info("%s: SKU OR: T33->T30\n", __func__);
376                                 new_sku = 0x81;
377                         } else if (package_id == 2) {
378                                 /* T33S->T30S */
379                                 pr_info("%s: SKU OR: T33S->T30S\n", __func__);
380                                 new_sku = 0x83;
381                         }
382                 } else if (fuse_sku == 0x81) {
383                         if (package_id == 2) {
384                                 /* AP33->AP30 */
385                                 pr_info("%s: SKU OR: AP33->AP30\n", __func__);
386                                 new_sku = 0x87;
387                         }
388                 }
389                 break;
390         case 2:
391                 /* L sku override */
392                 if (fuse_sku == 0x80) {
393                         if (package_id == 1) {
394                                 /* T33->T30L */
395                                 pr_info("%s: SKU OR: T33->T30L\n", __func__);
396                                 new_sku = 0x83;
397                         } else if (package_id == 2) {
398                                 /* T33S->T33SL */
399                                 pr_info("%s: SKU OR: T33S->T30SL\n", __func__);
400                                 new_sku = 0x8f;
401                         }
402                 } else if (fuse_sku == 0x81) {
403                         if (package_id == 1) {
404                                 pr_info("%s: SKU OR: T30->T30L\n", __func__);
405                                 /* T30->T30L */
406                                 new_sku = 0x83;
407                         }
408                 } else if (fuse_sku == 0x83) {
409                         if (package_id == 2) {
410                                 pr_info("%s: SKU OR: T30S->T30SL\n", __func__);
411                                 /* T30S to T30SL */
412                                 new_sku = 0x8f;
413                         }
414                 }
415                 break;
416         default:
417                 /* no override */
418                 break;
419         }
420
421         rev_sku_to_speedo_ids(tegra_revision, new_sku);
422         BUG_ON(threshold_index >= ARRAY_SIZE(cpu_process_speedos));
423
424         fuse_speedo_calib(&cpu_speedo_val, &core_speedo_val);
425         pr_debug("%s CPU speedo value %u\n", __func__, cpu_speedo_val);
426         pr_debug("%s Core speedo value %u\n", __func__, core_speedo_val);
427
428         for (iv = 0; iv < CPU_PROCESS_CORNERS_NUM; iv++) {
429                 if (cpu_speedo_val <
430                     cpu_process_speedos[threshold_index][iv]) {
431                         break;
432                 }
433         }
434         cpu_process_id = iv -1;
435
436         if (cpu_process_id == -1) {
437                 pr_err("****************************************************");
438                 pr_err("****************************************************");
439                 pr_err("* tegra3_speedo: CPU speedo value %3d out of range *",
440                        cpu_speedo_val);
441                 pr_err("****************************************************");
442                 pr_err("****************************************************");
443
444                 cpu_process_id = INVALID_PROCESS_ID;
445                 cpu_speedo_id = 1;
446         }
447
448         for (iv = 0; iv < CORE_PROCESS_CORNERS_NUM; iv++) {
449                 if (core_speedo_val <
450                     core_process_speedos[threshold_index][iv]) {
451                         break;
452                 }
453         }
454         core_process_id = iv -1;
455
456         if (core_process_id == -1) {
457                 pr_err("****************************************************");
458                 pr_err("****************************************************");
459                 pr_err("* tegra3_speedo: CORE speedo value %3d out of range *",
460                        core_speedo_val);
461                 pr_err("****************************************************");
462                 pr_err("****************************************************");
463
464                 core_process_id = INVALID_PROCESS_ID;
465                 soc_speedo_id = 1;
466         }
467         if (threshold_index == 12 && cpu_process_id != INVALID_PROCESS_ID) {
468                 if (cpu_process_id <= 2) {
469                         switch(fuse_sku) {
470                         case 0xb0:
471                         case 0xb1:
472                                 cpu_speedo_id = 9;
473                                 break;
474                         case 0x90:
475                         case 0x91:
476                                 cpu_speedo_id = 14;
477                         default:
478                                 break;
479                         }
480                 } else if (cpu_process_id >= 3 && cpu_process_id < 6) {
481                         switch(fuse_sku) {
482                         case 0xb0:
483                         case 0xb1:
484                                 cpu_speedo_id = 10;
485                                 break;
486                         case 0x90:
487                         case 0x91:
488                                 cpu_speedo_id = 15;
489                         default:
490                                 break;
491                         }
492                 }
493         }
494         pr_info("Tegra3: CPU Speedo ID %d, Soc Speedo ID %d",
495                  cpu_speedo_id, soc_speedo_id);
496 }
497
498 int tegra_cpu_process_id(void)
499 {
500         /* FIXME: remove when ready to deprecate invalid process-id boards */
501         if (cpu_process_id == INVALID_PROCESS_ID)
502                 return 0;
503         else
504                 return cpu_process_id;
505 }
506
507 int tegra_core_process_id(void)
508 {
509         /* FIXME: remove when ready to deprecate invalid process-id boards */
510         if (core_process_id == INVALID_PROCESS_ID)
511                 return 0;
512         else
513                 return core_process_id;
514 }
515
516 int tegra_cpu_speedo_id(void)
517 {
518         return cpu_speedo_id;
519 }
520
521 int tegra_soc_speedo_id(void)
522 {
523         return soc_speedo_id;
524 }
525
526 int tegra_package_id(void)
527 {
528         return package_id;
529 }
530
531 /*
532  * CPU and core nominal voltage levels as determined by chip SKU and speedo
533  * (not final - can be lowered by dvfs tables and rail dependencies; the
534  * latter is resolved by the dvfs code)
535  */
536 static const int cpu_speedo_nominal_millivolts[] =
537 /* speedo_id 0,    1,    2,    3,    4,    5,    6,    7,    8,   9,  10,  11,   12,    13,  14,  15 */
538         { 1125, 1150, 1150, 1150, 1237, 1237, 1237, 1150, 1150, 1007, 916, 850, 1237, 1237, 950, 900};
539
540 int tegra_cpu_speedo_mv(void)
541 {
542         return cpu_speedo_nominal_millivolts[cpu_speedo_id];
543 }
544
545 int tegra_core_speedo_mv(void)
546 {
547         switch (soc_speedo_id) {
548         case 0:
549                 return 1200;
550         case 1:
551                 if ((cpu_speedo_id != 7) && (cpu_speedo_id != 8))
552                         return 1200;
553                 /* fall thru for T30L or T30SL */
554         case 2:
555                 if (cpu_speedo_id != 13)
556                         return 1300;
557                 /* T37 */
558                 return 1350;
559         case 3:
560                 return 1250;
561         default:
562                 BUG();
563         }
564 }