Ventana: KBC: Removing the KBC usage on ventana
[linux-2.6.git] / arch / arm / mach-tegra / tegra3_emc.h
1 /*
2  * arch/arm/mach-tegra/tegra3_emc.h
3  *
4  * Copyright (C) 2011 NVIDIA Corporation
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  *
20  */
21
22 #ifndef _MACH_TEGRA_TEGRA3_EMC_H
23 #define _MACH_TEGRA_TEGRA3_EMC_H
24
25 #define TEGRA_EMC_NUM_REGS      110
26
27 #define TEGRA_EMC_BRIDGE_RATE_MIN       300000000
28 #define TEGRA_EMC_BRIDGE_MVOLTS_MIN     1200
29
30 struct tegra_emc_table {
31         u8 rev;
32         unsigned long rate;
33
34         /* unconditionally updated in one burst shot */
35         u32 burst_regs[TEGRA_EMC_NUM_REGS];
36
37         /* updated separately under some conditions */
38         u32 emc_zcal_cnt_long;
39         u32 emc_acal_interval;
40         u32 emc_periodic_qrst;
41         u32 emc_mode_reset;
42         u32 emc_mode_1;
43         u32 emc_mode_2;
44 };
45
46 void tegra_init_emc(const struct tegra_emc_table *table, int table_size);
47
48 int tegra_emc_get_dram_type(void);
49
50 #define EMC_INTSTATUS                           0x0
51 #define EMC_INTSTATUS_CLKCHANGE_COMPLETE        (0x1 << 4)
52
53 #define EMC_DBG                                 0x8
54 #define EMC_DBG_WRITE_MUX_ACTIVE                (0x1 << 1)
55
56 #define EMC_CFG                                 0xc
57 #define EMC_CFG_PERIODIC_QRST                   (0x1 << 21)
58 #define EMC_CFG_DYN_SREF_ENABLE                 (0x1 << 28)
59 #define EMC_CFG_PWR_MASK                        (0xF << 28)
60
61 #define EMC_REFCTRL                             0x20
62 #define EMC_REFCTRL_DEV_SEL_SHIFT               0
63 #define EMC_REFCTRL_DEV_SEL_MASK                (0x3 << EMC_REFCTRL_DEV_SEL_SHIFT)
64 #define EMC_REFCTRL_ENABLE                      (0x1 << 31)
65 #define EMC_REFCTRL_ENABLE_ALL(num)             \
66         ((((num > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT) \
67          | EMC_REFCTRL_ENABLE)
68 #define EMC_REFCTRL_DISABLE_ALL(num)            \
69         (((num > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT)
70
71 #define EMC_TIMING_CONTROL                      0x28
72 #define EMC_RC                                  0x2c
73 #define EMC_RFC                                 0x30
74 #define EMC_RAS                                 0x34
75 #define EMC_RP                                  0x38
76 #define EMC_R2W                                 0x3c
77 #define EMC_W2R                                 0x40
78 #define EMC_R2P                                 0x44
79 #define EMC_W2P                                 0x48
80 #define EMC_RD_RCD                              0x4c
81 #define EMC_WR_RCD                              0x50
82 #define EMC_RRD                                 0x54
83 #define EMC_REXT                                0x58
84 #define EMC_WDV                                 0x5c
85 #define EMC_QUSE                                0x60
86 #define EMC_QRST                                0x64
87 #define EMC_QSAFE                               0x68
88 #define EMC_RDV                                 0x6c
89 #define EMC_REFRESH                             0x70
90 #define EMC_BURST_REFRESH_NUM                   0x74
91 #define EMC_PDEX2WR                             0x78
92 #define EMC_PDEX2RD                             0x7c
93 #define EMC_PCHG2PDEN                           0x80
94 #define EMC_ACT2PDEN                            0x84
95 #define EMC_AR2PDEN                             0x88
96 #define EMC_RW2PDEN                             0x8c
97 #define EMC_TXSR                                0x90
98 #define EMC_TCKE                                0x94
99 #define EMC_TFAW                                0x98
100 #define EMC_TRPAB                               0x9c
101 #define EMC_TCLKSTABLE                          0xa0
102 #define EMC_TCLKSTOP                            0xa4
103 #define EMC_TREFBW                              0xa8
104 #define EMC_QUSE_EXTRA                          0xac
105 #define EMC_ODT_WRITE                           0xb0
106 #define EMC_ODT_READ                            0xb4
107 #define EMC_WEXT                                0xb8
108 #define EMC_CTT                                 0xbc
109
110 #define EMC_MRS_WAIT_CNT                        0xc8
111 #define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT       0
112 #define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK        \
113         (0x3FF << EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT)
114 #define EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT        16
115 #define EMC_MRS_WAIT_CNT_LONG_WAIT_MASK         \
116         (0x3FF << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT)
117
118 #define EMC_MRS                                 0xcc
119 #define EMC_MODE_SET_DLL_RESET                  (0x1 << 8)
120 #define EMC_MODE_SET_LONG_CNT                   (0x1 << 26)
121 #define EMC_EMRS                                0xd0
122
123 #define EMC_SELF_REF                            0xe0
124 #define EMC_SELF_REF_CMD_ENABLED                (0x1 << 0)
125 #define EMC_SELF_REF_DEV_SEL_SHIFT              30
126 #define EMC_SELF_REF_DEV_SEL_MASK               (0x3 << EMC_SELF_REF_DEV_SEL_SHIFT)
127 enum {
128         DRAM_DEV_SEL_ALL = 0,
129         DRAM_DEV_SEL_0   = (2 << EMC_SELF_REF_DEV_SEL_SHIFT),
130         DRAM_DEV_SEL_1   = (1 << EMC_SELF_REF_DEV_SEL_SHIFT),
131 };
132 #define DRAM_BROADCAST(num)                     \
133         (((num) > 1) ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0)
134
135 #define EMC_MRW                                 0xe8
136 #define EMC_MRR                                 0xec
137 #define EMC_XM2DQSPADCTRL3                      0xf8
138 #define EMC_XM2DQSPADCTRL3_VREF_ENABLE          (0x1 << 5)
139 #define EMC_FBIO_SPARE                          0x100
140
141 #define EMC_FBIO_CFG5                           0x104
142 #define EMC_CFG5_TYPE_SHIFT                     0x0
143 #define EMC_CFG5_TYPE_MASK                      (0x3 << EMC_CFG5_TYPE_SHIFT)
144 enum {
145         DRAM_TYPE_DDR3   = 0,
146         DRAM_TYPE_LPDDR2 = 2,
147 };
148 #define EMC_CFG5_QUSE_MODE_SHIFT                13
149 #define EMC_CFG5_QUSE_MODE_MASK                 (0x7 << EMC_CFG5_QUSE_MODE_SHIFT)
150 enum {
151         EMC_CFG5_QUSE_MODE_NORMAL = 0,
152         EMC_CFG5_QUSE_MODE_ALWAYS_ON,
153         EMC_CFG5_QUSE_MODE_INTERNAL_LPBK,
154         EMC_CFG5_QUSE_MODE_PULSE_INTERN,
155         EMC_CFG5_QUSE_MODE_PULSE_EXTERN,
156 };
157
158 #define EMC_FBIO_CFG6                           0x114
159 #define EMC_CFG_RSV                             0x120
160 #define EMC_AUTO_CAL_CONFIG                     0x2a4
161 #define EMC_AUTO_CAL_INTERVAL                   0x2a8
162 #define EMC_AUTO_CAL_STATUS                     0x2ac
163 #define EMC_AUTO_CAL_STATUS_ACTIVE              (0x1 << 31)
164 #define EMC_STATUS                              0x2b4
165 #define EMC_STATUS_TIMING_UPDATE_STALLED        (0x1 << 23)
166
167 #define EMC_CFG_2                               0x2b8
168 #define EMC_CFG_2_MODE_SHIFT                    0
169 #define EMC_CFG_2_MODE_MASK                     (0x7 << EMC_CFG_2_MODE_SHIFT)
170 #define EMC_CFG_2_SREF_MODE                     0x1
171 #define EMC_CFG_2_PD_MODE                       0x3
172
173 #define EMC_CFG_DIG_DLL                         0x2bc
174 #define EMC_CFG_DIG_DLL_PERIOD                  0x2c0
175 #define EMC_CTT_DURATION                        0x2d8
176 #define EMC_CTT_TERM_CTRL                       0x2dc
177 #define EMC_ZCAL_INTERVAL                       0x2e0
178 #define EMC_ZCAL_WAIT_CNT                       0x2e4
179
180 #define EMC_ZQ_CAL                              0x2ec
181 #define EMC_ZQ_CAL_CMD                          (0x1 << 0)
182 #define EMC_ZQ_CAL_LONG                         (0x1 << 4)
183 #define EMC_ZQ_CAL_LONG_CMD_DEV0                \
184         (DRAM_DEV_SEL_0 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
185 #define EMC_ZQ_CAL_LONG_CMD_DEV1                \
186         (DRAM_DEV_SEL_1 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
187
188 #define EMC_XM2CMDPADCTRL                       0x2f0
189 #define EMC_XM2DQSPADCTRL2                      0x2fc
190 #define EMC_XM2DQSPADCTRL2_VREF_ENABLE          (0x1 << 5)
191 #define EMC_XM2DQPADCTRL2                       0x304
192 #define EMC_XM2CLKPADCTRL                       0x308
193 #define EMC_XM2COMPPADCTRL                      0x30c
194 #define EMC_XM2COMPPADCTRL_VREF_CAL_ENABLE      (0x1 << 10)
195 #define EMC_XM2VTTGENPADCTRL                    0x310
196 #define EMC_XM2VTTGENPADCTRL2                   0x314
197 #define EMC_XM2QUSEPADCTRL                      0x318
198 #define EMC_XM2QUSEPADCTRL_IVREF_ENABLE         (0x1 << 4)
199 #define EMC_DLL_XFORM_DQS0                      0x328
200 #define EMC_DLL_XFORM_DQS1                      0x32c
201 #define EMC_DLL_XFORM_DQS2                      0x330
202 #define EMC_DLL_XFORM_DQS3                      0x334
203 #define EMC_DLL_XFORM_DQS4                      0x338
204 #define EMC_DLL_XFORM_DQS5                      0x33c
205 #define EMC_DLL_XFORM_DQS6                      0x340
206 #define EMC_DLL_XFORM_DQS7                      0x344
207 #define EMC_DLL_XFORM_QUSE0                     0x348
208 #define EMC_DLL_XFORM_QUSE1                     0x34c
209 #define EMC_DLL_XFORM_QUSE2                     0x350
210 #define EMC_DLL_XFORM_QUSE3                     0x354
211 #define EMC_DLL_XFORM_QUSE4                     0x358
212 #define EMC_DLL_XFORM_QUSE5                     0x35c
213 #define EMC_DLL_XFORM_QUSE6                     0x360
214 #define EMC_DLL_XFORM_QUSE7                     0x364
215 #define EMC_DLL_XFORM_DQ0                       0x368
216 #define EMC_DLL_XFORM_DQ1                       0x36c
217 #define EMC_DLL_XFORM_DQ2                       0x370
218 #define EMC_DLL_XFORM_DQ3                       0x374
219 #define EMC_DLI_TRIM_TXDQS0                     0x3a8
220 #define EMC_DLI_TRIM_TXDQS1                     0x3ac
221 #define EMC_DLI_TRIM_TXDQS2                     0x3b0
222 #define EMC_DLI_TRIM_TXDQS3                     0x3b4
223 #define EMC_DLI_TRIM_TXDQS4                     0x3b8
224 #define EMC_DLI_TRIM_TXDQS5                     0x3bc
225 #define EMC_DLI_TRIM_TXDQS6                     0x3c0
226 #define EMC_DLI_TRIM_TXDQS7                     0x3c4
227 #define EMC_STALL_BEFORE_CLKCHANGE              0x3c8
228 #define EMC_STALL_AFTER_CLKCHANGE               0x3cc
229 #define EMC_UNSTALL_RW_AFTER_CLKCHANGE          0x3d0
230 #define EMC_SEL_DPD_CTRL                        0x3d8
231 #define EMC_SEL_DPD_CTRL_QUSE_DPD_ENABLE        (0x1 << 9)
232 #define EMC_PRE_REFRESH_REQ_CNT                 0x3dc
233 #define EMC_DYN_SELF_REF_CONTROL                0x3e0
234 #define EMC_TXSRDLL                             0x3e4
235
236 #define MC_EMEM_ADR_CFG                         0x54
237 #define MC_EMEM_ARB_CFG                         0x90
238 #define MC_EMEM_ARB_OUTSTANDING_REQ             0x94
239 #define MC_EMEM_ARB_TIMING_RCD                  0x98
240 #define MC_EMEM_ARB_TIMING_RP                   0x9c
241 #define MC_EMEM_ARB_TIMING_RC                   0xa0
242 #define MC_EMEM_ARB_TIMING_RAS                  0xa4
243 #define MC_EMEM_ARB_TIMING_FAW                  0xa8
244 #define MC_EMEM_ARB_TIMING_RRD                  0xac
245 #define MC_EMEM_ARB_TIMING_RAP2PRE              0xb0
246 #define MC_EMEM_ARB_TIMING_WAP2PRE              0xb4
247 #define MC_EMEM_ARB_TIMING_R2R                  0xb8
248 #define MC_EMEM_ARB_TIMING_W2W                  0xbc
249 #define MC_EMEM_ARB_TIMING_R2W                  0xc0
250 #define MC_EMEM_ARB_TIMING_W2R                  0xc4
251 #define MC_EMEM_ARB_DA_TURNS                    0xd0
252 #define MC_EMEM_ARB_DA_COVERS                   0xd4
253 #define MC_EMEM_ARB_MISC0                       0xd8
254 #define MC_EMEM_ARB_MISC0_EMC_SAME_FREQ         (0x1 << 27)
255 #define MC_EMEM_ARB_RING1_THROTTLE              0xe0
256 #define MC_EMEM_ARB_OVERRIDE                    0xe8
257 #define MC_RESERVED_RSV                         0x3fc
258
259 #endif