rtc: tps80031: register as mfd sub device
[linux-2.6.git] / arch / arm / mach-tegra / tegra3_emc.h
1 /*
2  * arch/arm/mach-tegra/tegra3_emc.h
3  *
4  * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  *
20  */
21
22 #ifndef _MACH_TEGRA_TEGRA3_EMC_H
23 #define _MACH_TEGRA_TEGRA3_EMC_H
24
25 #define TEGRA_EMC_NUM_REGS      110
26
27 #define TEGRA_EMC_BRIDGE_RATE_MIN       300000000
28 #define TEGRA_EMC_BRIDGE_MVOLTS_MIN     1200
29
30 extern u8 tegra_emc_bw_efficiency;
31 extern u8 tegra_emc_bw_efficiency_boost;
32
33 struct tegra_emc_table {
34         u8 rev;
35         unsigned long rate;
36
37         /* unconditionally updated in one burst shot */
38         u32 burst_regs[TEGRA_EMC_NUM_REGS];
39
40         /* updated separately under some conditions */
41         u32 emc_zcal_cnt_long;
42         u32 emc_acal_interval;
43         u32 emc_periodic_qrst;
44         u32 emc_mode_reset;
45         u32 emc_mode_1;
46         u32 emc_mode_2;
47         u32 emc_dsr;
48         int emc_min_mv;
49 };
50
51 enum {
52         DRAM_OVER_TEMP_NONE = 0,
53         DRAM_OVER_TEMP_REFRESH,
54 };
55
56 struct clk;
57
58 void tegra_init_emc(const struct tegra_emc_table *table, int table_size);
59
60 void tegra_init_dram_bit_map(const u32 *bit_map, int map_size);
61 void tegra_emc_dram_type_init(struct clk *c);
62 int tegra_emc_get_dram_type(void);
63 int tegra_emc_get_dram_temperature(void);
64 int tegra_emc_set_over_temp_state(unsigned long state);
65
66 #ifdef CONFIG_PM_SLEEP
67 void tegra_mc_timing_restore(void);
68 #else
69 static inline void tegra_mc_timing_restore(void)
70 { }
71 #endif
72
73 #define EMC_INTSTATUS                           0x0
74 #define EMC_INTSTATUS_CLKCHANGE_COMPLETE        (0x1 << 4)
75
76 #define EMC_DBG                                 0x8
77 #define EMC_DBG_WRITE_MUX_ACTIVE                (0x1 << 1)
78
79 #define EMC_CFG                                 0xc
80 #define EMC_CFG_PERIODIC_QRST                   (0x1 << 21)
81 #define EMC_CFG_DYN_SREF_ENABLE                 (0x1 << 28)
82 #define EMC_CFG_PWR_MASK                        (0xF << 28)
83
84 #define EMC_REFCTRL                             0x20
85 #define EMC_REFCTRL_DEV_SEL_SHIFT               0
86 #define EMC_REFCTRL_DEV_SEL_MASK                (0x3 << EMC_REFCTRL_DEV_SEL_SHIFT)
87 #define EMC_REFCTRL_ENABLE                      (0x1 << 31)
88 #define EMC_REFCTRL_ENABLE_ALL(num)             \
89         ((((num > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT) \
90          | EMC_REFCTRL_ENABLE)
91 #define EMC_REFCTRL_DISABLE_ALL(num)            \
92         (((num > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT)
93
94 #define EMC_TIMING_CONTROL                      0x28
95 #define EMC_RC                                  0x2c
96 #define EMC_RFC                                 0x30
97 #define EMC_RAS                                 0x34
98 #define EMC_RP                                  0x38
99 #define EMC_R2W                                 0x3c
100 #define EMC_W2R                                 0x40
101 #define EMC_R2P                                 0x44
102 #define EMC_W2P                                 0x48
103 #define EMC_RD_RCD                              0x4c
104 #define EMC_WR_RCD                              0x50
105 #define EMC_RRD                                 0x54
106 #define EMC_REXT                                0x58
107 #define EMC_WDV                                 0x5c
108 #define EMC_QUSE                                0x60
109 #define EMC_QRST                                0x64
110 #define EMC_QSAFE                               0x68
111 #define EMC_RDV                                 0x6c
112 #define EMC_REFRESH                             0x70
113 #define EMC_BURST_REFRESH_NUM                   0x74
114 #define EMC_PDEX2WR                             0x78
115 #define EMC_PDEX2RD                             0x7c
116 #define EMC_PCHG2PDEN                           0x80
117 #define EMC_ACT2PDEN                            0x84
118 #define EMC_AR2PDEN                             0x88
119 #define EMC_RW2PDEN                             0x8c
120 #define EMC_TXSR                                0x90
121 #define EMC_TCKE                                0x94
122 #define EMC_TFAW                                0x98
123 #define EMC_TRPAB                               0x9c
124 #define EMC_TCLKSTABLE                          0xa0
125 #define EMC_TCLKSTOP                            0xa4
126 #define EMC_TREFBW                              0xa8
127 #define EMC_QUSE_EXTRA                          0xac
128 #define EMC_ODT_WRITE                           0xb0
129 #define EMC_ODT_READ                            0xb4
130 #define EMC_WEXT                                0xb8
131 #define EMC_CTT                                 0xbc
132
133 #define EMC_MRS_WAIT_CNT                        0xc8
134 #define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT       0
135 #define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK        \
136         (0x3FF << EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT)
137 #define EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT        16
138 #define EMC_MRS_WAIT_CNT_LONG_WAIT_MASK         \
139         (0x3FF << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT)
140
141 #define EMC_MRS                                 0xcc
142 #define EMC_MODE_SET_DLL_RESET                  (0x1 << 8)
143 #define EMC_MODE_SET_LONG_CNT                   (0x1 << 26)
144 #define EMC_EMRS                                0xd0
145 #define EMC_REF                                 0xd4
146 #define EMC_REF_FORCE_CMD                       1
147
148 #define EMC_SELF_REF                            0xe0
149 #define EMC_SELF_REF_CMD_ENABLED                (0x1 << 0)
150 #define EMC_SELF_REF_DEV_SEL_SHIFT              30
151 #define EMC_SELF_REF_DEV_SEL_MASK               (0x3 << EMC_SELF_REF_DEV_SEL_SHIFT)
152 enum {
153         DRAM_DEV_SEL_ALL = 0,
154         DRAM_DEV_SEL_0   = (2 << EMC_SELF_REF_DEV_SEL_SHIFT),
155         DRAM_DEV_SEL_1   = (1 << EMC_SELF_REF_DEV_SEL_SHIFT),
156 };
157 #define DRAM_BROADCAST(num)                     \
158         (((num) > 1) ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0)
159
160 #define EMC_MRW                                 0xe8
161 #define EMC_MRR                                 0xec
162 #define EMC_MRR_MA_SHIFT                        16
163 #define EMC_MRR_MA_MASK                         (0xFF << EMC_MRR_MA_SHIFT)
164 #define EMC_MRR_DATA_MASK                       ((0x1 << EMC_MRR_MA_SHIFT) - 1)
165 #define LPDDR2_MR4_TEMP_SHIFT                   0
166 #define LPDDR2_MR4_TEMP_MASK                    (0x7 << LPDDR2_MR4_TEMP_SHIFT)
167
168 #define EMC_XM2DQSPADCTRL3                      0xf8
169 #define EMC_XM2DQSPADCTRL3_VREF_ENABLE          (0x1 << 5)
170 #define EMC_FBIO_SPARE                          0x100
171
172 #define EMC_FBIO_CFG5                           0x104
173 #define EMC_CFG5_TYPE_SHIFT                     0x0
174 #define EMC_CFG5_TYPE_MASK                      (0x3 << EMC_CFG5_TYPE_SHIFT)
175 enum {
176         DRAM_TYPE_DDR3   = 0,
177         DRAM_TYPE_LPDDR2 = 2,
178 };
179 #define EMC_CFG5_QUSE_MODE_SHIFT                13
180 #define EMC_CFG5_QUSE_MODE_MASK                 (0x7 << EMC_CFG5_QUSE_MODE_SHIFT)
181 enum {
182         EMC_CFG5_QUSE_MODE_NORMAL = 0,
183         EMC_CFG5_QUSE_MODE_ALWAYS_ON,
184         EMC_CFG5_QUSE_MODE_INTERNAL_LPBK,
185         EMC_CFG5_QUSE_MODE_PULSE_INTERN,
186         EMC_CFG5_QUSE_MODE_PULSE_EXTERN,
187 };
188
189 #define EMC_FBIO_CFG6                           0x114
190 #define EMC_CFG_RSV                             0x120
191 #define EMC_AUTO_CAL_CONFIG                     0x2a4
192 #define EMC_AUTO_CAL_INTERVAL                   0x2a8
193 #define EMC_AUTO_CAL_STATUS                     0x2ac
194 #define EMC_AUTO_CAL_STATUS_ACTIVE              (0x1 << 31)
195 #define EMC_STATUS                              0x2b4
196 #define EMC_STATUS_TIMING_UPDATE_STALLED        (0x1 << 23)
197 #define EMC_STATUS_MRR_DIVLD                    (0x1 << 20)
198
199 #define EMC_CFG_2                               0x2b8
200 #define EMC_CFG_2_MODE_SHIFT                    0
201 #define EMC_CFG_2_MODE_MASK                     (0x7 << EMC_CFG_2_MODE_SHIFT)
202 #define EMC_CFG_2_SREF_MODE                     0x1
203 #define EMC_CFG_2_PD_MODE                       0x3
204
205 #define EMC_CFG_DIG_DLL                         0x2bc
206 #define EMC_CFG_DIG_DLL_PERIOD                  0x2c0
207 #define EMC_CTT_DURATION                        0x2d8
208 #define EMC_CTT_TERM_CTRL                       0x2dc
209 #define EMC_ZCAL_INTERVAL                       0x2e0
210 #define EMC_ZCAL_WAIT_CNT                       0x2e4
211
212 #define EMC_ZQ_CAL                              0x2ec
213 #define EMC_ZQ_CAL_CMD                          (0x1 << 0)
214 #define EMC_ZQ_CAL_LONG                         (0x1 << 4)
215 #define EMC_ZQ_CAL_LONG_CMD_DEV0                \
216         (DRAM_DEV_SEL_0 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
217 #define EMC_ZQ_CAL_LONG_CMD_DEV1                \
218         (DRAM_DEV_SEL_1 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
219
220 #define EMC_XM2CMDPADCTRL                       0x2f0
221 #define EMC_XM2DQSPADCTRL2                      0x2fc
222 #define EMC_XM2DQSPADCTRL2_VREF_ENABLE          (0x1 << 5)
223 #define EMC_XM2DQPADCTRL2                       0x304
224 #define EMC_XM2CLKPADCTRL                       0x308
225 #define EMC_XM2COMPPADCTRL                      0x30c
226 #define EMC_XM2COMPPADCTRL_VREF_CAL_ENABLE      (0x1 << 10)
227 #define EMC_XM2VTTGENPADCTRL                    0x310
228 #define EMC_XM2VTTGENPADCTRL2                   0x314
229 #define EMC_XM2QUSEPADCTRL                      0x318
230 #define EMC_XM2QUSEPADCTRL_IVREF_ENABLE         (0x1 << 4)
231 #define EMC_DLL_XFORM_DQS0                      0x328
232 #define EMC_DLL_XFORM_DQS1                      0x32c
233 #define EMC_DLL_XFORM_DQS2                      0x330
234 #define EMC_DLL_XFORM_DQS3                      0x334
235 #define EMC_DLL_XFORM_DQS4                      0x338
236 #define EMC_DLL_XFORM_DQS5                      0x33c
237 #define EMC_DLL_XFORM_DQS6                      0x340
238 #define EMC_DLL_XFORM_DQS7                      0x344
239 #define EMC_DLL_XFORM_QUSE0                     0x348
240 #define EMC_DLL_XFORM_QUSE1                     0x34c
241 #define EMC_DLL_XFORM_QUSE2                     0x350
242 #define EMC_DLL_XFORM_QUSE3                     0x354
243 #define EMC_DLL_XFORM_QUSE4                     0x358
244 #define EMC_DLL_XFORM_QUSE5                     0x35c
245 #define EMC_DLL_XFORM_QUSE6                     0x360
246 #define EMC_DLL_XFORM_QUSE7                     0x364
247 #define EMC_DLL_XFORM_DQ0                       0x368
248 #define EMC_DLL_XFORM_DQ1                       0x36c
249 #define EMC_DLL_XFORM_DQ2                       0x370
250 #define EMC_DLL_XFORM_DQ3                       0x374
251 #define EMC_DLI_TRIM_TXDQS0                     0x3a8
252 #define EMC_DLI_TRIM_TXDQS1                     0x3ac
253 #define EMC_DLI_TRIM_TXDQS2                     0x3b0
254 #define EMC_DLI_TRIM_TXDQS3                     0x3b4
255 #define EMC_DLI_TRIM_TXDQS4                     0x3b8
256 #define EMC_DLI_TRIM_TXDQS5                     0x3bc
257 #define EMC_DLI_TRIM_TXDQS6                     0x3c0
258 #define EMC_DLI_TRIM_TXDQS7                     0x3c4
259 #define EMC_STALL_BEFORE_CLKCHANGE              0x3c8
260 #define EMC_STALL_AFTER_CLKCHANGE               0x3cc
261 #define EMC_UNSTALL_RW_AFTER_CLKCHANGE          0x3d0
262 #define EMC_SEL_DPD_CTRL                        0x3d8
263 #define EMC_SEL_DPD_CTRL_QUSE_DPD_ENABLE        (0x1 << 9)
264 #define EMC_PRE_REFRESH_REQ_CNT                 0x3dc
265 #define EMC_DYN_SELF_REF_CONTROL                0x3e0
266 #define EMC_TXSRDLL                             0x3e4
267
268 #define MC_EMEM_ADR_CFG                         0x54
269 #define MC_EMEM_ARB_CFG                         0x90
270 #define MC_EMEM_ARB_OUTSTANDING_REQ             0x94
271 #define MC_EMEM_ARB_OUTSTANDING_REQ_MAX_SHIFT   0
272 #define MC_EMEM_ARB_OUTSTANDING_REQ_MAX_MASK    \
273         (0x1FF << MC_EMEM_ARB_OUTSTANDING_REQ_MAX_SHIFT)
274 #define MC_EMEM_ARB_OUTSTANDING_REQ_HOLDOFF_OVERRIDE    (0x1 << 30)
275 #define MC_EMEM_ARB_OUTSTANDING_REQ_LIMIT_ENABLE        (0x1 << 31)
276 #define MC_EMEM_ARB_TIMING_RCD                  0x98
277 #define MC_EMEM_ARB_TIMING_RP                   0x9c
278 #define MC_EMEM_ARB_TIMING_RC                   0xa0
279 #define MC_EMEM_ARB_TIMING_RAS                  0xa4
280 #define MC_EMEM_ARB_TIMING_FAW                  0xa8
281 #define MC_EMEM_ARB_TIMING_RRD                  0xac
282 #define MC_EMEM_ARB_TIMING_RAP2PRE              0xb0
283 #define MC_EMEM_ARB_TIMING_WAP2PRE              0xb4
284 #define MC_EMEM_ARB_TIMING_R2R                  0xb8
285 #define MC_EMEM_ARB_TIMING_W2W                  0xbc
286 #define MC_EMEM_ARB_TIMING_R2W                  0xc0
287 #define MC_EMEM_ARB_TIMING_W2R                  0xc4
288 #define MC_EMEM_ARB_DA_TURNS                    0xd0
289 #define MC_EMEM_ARB_DA_COVERS                   0xd4
290 #define MC_EMEM_ARB_MISC0                       0xd8
291 #define MC_EMEM_ARB_MISC0_EMC_SAME_FREQ         (0x1 << 27)
292 #define MC_EMEM_ARB_MISC1                       0xdc
293 #define MC_EMEM_ARB_RING1_THROTTLE              0xe0
294 #define MC_EMEM_ARB_RING3_THROTTLE              0xe4
295 #define MC_EMEM_ARB_OVERRIDE                    0xe8
296 #define MC_EMEM_ARB_OVERRIDE_EACK_MASK          (0x3 << 0)
297 #define MC_TIMING_CONTROL                       0xfc
298 #define MC_RESERVED_RSV                         0x3fc
299
300 #endif