ARM: tegra: usb_phy: Fixing HSIC port power code
[linux-2.6.git] / arch / arm / mach-tegra / tegra2_usb_phy.c
1 /*
2  * arch/arm/mach-tegra/tegra2_usb_phy.c
3  *
4  * Copyright (C) 2011 NVIDIA Corporation
5  *
6  *
7  * This software is licensed under the terms of the GNU General Public
8  * License version 2, as published by the Free Software Foundation, and
9  * may be copied, distributed, and modified under those terms.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17 #include <linux/resource.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/slab.h>
21 #include <linux/err.h>
22 #include <linux/platform_device.h>
23 #include <linux/io.h>
24 #include <linux/gpio.h>
25 #include <linux/usb/otg.h>
26 #include <linux/usb/ulpi.h>
27 #include <linux/interrupt.h>
28 #include <linux/clk.h>
29 #include <linux/regulator/consumer.h>
30 #include <linux/platform_data/tegra_usb.h>
31 #include <mach/iomap.h>
32 #include <mach/pinmux.h>
33 #include <asm/mach-types.h>
34 #include <mach/usb_phy.h>
35 #include "tegra_usb_phy.h"
36 #include "fuse.h"
37
38
39 #define USB_USBCMD              0x140
40 #define   USB_USBCMD_RS         (1 << 0)
41 #define   USB_USBCMD_RESET      (1 << 1)
42
43 #define USB_USBSTS              0x144
44 #define   USB_USBSTS_PCI        (1 << 2)
45 #define   USB_USBSTS_SRI        (1 << 7)
46 #define   USB_USBSTS_HCH        (1 << 12)
47
48 #define USB_ASYNCLISTADDR       0x158
49
50 #define USB_TXFILLTUNING                0x164
51 #define USB_FIFO_TXFILL_THRES(x)   (((x) & 0x1f) << 16)
52 #define USB_FIFO_TXFILL_MASK    0x1f0000
53
54 #define ULPI_VIEWPORT           0x170
55 #define   ULPI_WAKEUP           (1 << 31)
56 #define   ULPI_RUN              (1 << 30)
57 #define   ULPI_RD_WR            (1 << 29)
58
59 #define USB_PORTSC              0x184
60 #define   USB_PORTSC_PTS(x)     (((x) & 0x3) << 30)
61 #define   USB_PORTSC_PSPD(x)    (((x) & 0x3) << 26)
62 #define   USB_PORTSC_PHCD       (1 << 23)
63 #define   USB_PORTSC_WKOC       (1 << 22)
64 #define   USB_PORTSC_WKDS       (1 << 21)
65 #define   USB_PORTSC_WKCN       (1 << 20)
66 #define   USB_PORTSC_PTC(x)     (((x) & 0xf) << 16)
67 #define   USB_PORTSC_PP (1 << 12)
68 #define   USB_PORTSC_LS(x) (((x) & 0x3) << 10)
69 #define   USB_PORTSC_SUSP       (1 << 7)
70 #define   USB_PORTSC_OCC        (1 << 5)
71 #define   USB_PORTSC_PEC        (1 << 3)
72 #define   USB_PORTSC_PE         (1 << 2)
73 #define   USB_PORTSC_CSC        (1 << 1)
74 #define   USB_PORTSC_CCS        (1 << 0)
75 #define   USB_PORTSC_RWC_BITS (USB_PORTSC_CSC | USB_PORTSC_PEC | USB_PORTSC_OCC)
76 #define   USB_PORTSC_PSPD_MASK  3
77
78 #define USB_USBMODE_REG_OFFSET  0x1a8
79 #define   USB_USBMODE_MASK              (3 << 0)
80 #define   USB_USBMODE_HOST              (3 << 0)
81 #define   USB_USBMODE_DEVICE    (2 << 0)
82
83 #define USB_SUSP_CTRL           0x400
84 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
85 #define   USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
86 #define   USB_SUSP_CLR          (1 << 5)
87 #define   USB_CLKEN             (1 << 6)
88 #define   USB_PHY_CLK_VALID (1 << 7)
89 #define   USB_PHY_CLK_VALID_INT_ENB    (1 << 9)
90 #define   UTMIP_RESET           (1 << 11)
91 #define   UHSIC_RESET           (1 << 11)
92 #define   UTMIP_PHY_ENABLE      (1 << 12)
93 #define   UHSIC_PHY_ENABLE      (1 << 12)
94 #define   ULPI_PHY_ENABLE       (1 << 13)
95 #define   USB_SUSP_SET          (1 << 14)
96 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
97 #define   USB_PHY_CLK_VALID_INT_STS     (1 << 8)
98
99 #define USB_PHY_VBUS_WAKEUP_ID  0x408
100 #define   VDAT_DET_INT_EN       (1 << 16)
101 #define   VDAT_DET_CHG_DET      (1 << 17)
102 #define   VDAT_DET_STS          (1 << 18)
103 #define   USB_ID_STATUS         (1 << 2)
104
105 #define USB1_LEGACY_CTRL        0x410
106 #define   USB1_NO_LEGACY_MODE                   (1 << 0)
107 #define   USB1_VBUS_SENSE_CTL_MASK              (3 << 1)
108 #define   USB1_VBUS_SENSE_CTL_VBUS_WAKEUP       (0 << 1)
109 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
110                                                 (1 << 1)
111 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD       (2 << 1)
112 #define   USB1_VBUS_SENSE_CTL_A_SESS_VLD        (3 << 1)
113
114 #define ULPIS2S_CTRL            0x418
115 #define   ULPIS2S_ENA                   (1 << 0)
116 #define   ULPIS2S_SUPPORT_DISCONNECT    (1 << 2)
117 #define   ULPIS2S_PLLU_MASTER_BLASTER60 (1 << 3)
118 #define   ULPIS2S_SPARE(x)              (((x) & 0xF) << 8)
119 #define   ULPIS2S_FORCE_ULPI_CLK_OUT    (1 << 12)
120 #define   ULPIS2S_DISCON_DONT_CHECK_SE0 (1 << 13)
121 #define   ULPIS2S_SUPPORT_HS_KEEP_ALIVE (1 << 14)
122 #define   ULPIS2S_DISABLE_STP_PU        (1 << 15)
123 #define   ULPIS2S_SLV0_CLAMP_XMIT       (1 << 16)
124
125 #define ULPI_TIMING_CTRL_0      0x424
126 #define   ULPI_CLOCK_OUT_DELAY(x)       ((x) & 0x1F)
127 #define   ULPI_OUTPUT_PINMUX_BYP        (1 << 10)
128 #define   ULPI_CLKOUT_PINMUX_BYP        (1 << 11)
129 #define   ULPI_SHADOW_CLK_LOOPBACK_EN   (1 << 12)
130 #define   ULPI_SHADOW_CLK_SEL           (1 << 13)
131 #define   ULPI_CORE_CLK_SEL             (1 << 14)
132 #define   ULPI_SHADOW_CLK_DELAY(x)      (((x) & 0x1F) << 16)
133 #define   ULPI_LBK_PAD_EN               (1 << 26)
134 #define   ULPI_LBK_PAD_E_INPUT_OR       (1 << 27)
135 #define   ULPI_CLK_OUT_ENA              (1 << 28)
136 #define   ULPI_CLK_PADOUT_ENA           (1 << 29)
137
138 #define ULPI_TIMING_CTRL_1      0x428
139 #define   ULPI_DATA_TRIMMER_LOAD        (1 << 0)
140 #define   ULPI_DATA_TRIMMER_SEL(x)      (((x) & 0x7) << 1)
141 #define   ULPI_STPDIRNXT_TRIMMER_LOAD   (1 << 16)
142 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
143 #define   ULPI_DIR_TRIMMER_LOAD         (1 << 24)
144 #define   ULPI_DIR_TRIMMER_SEL(x)       (((x) & 0x7) << 25)
145
146 #define UTMIP_PLL_CFG1          0x804
147 #define UHSIC_PLL_CFG1                          0x804
148 #define   UTMIP_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
149 #define   UTMIP_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 27)
150 #define   UHSIC_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
151 #define   UHSIC_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 14)
152
153 #define UTMIP_XCVR_UHSIC_HSRX_CFG0              0x808
154 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
155 #define   UHSIC_ELASTIC_UNDERRUN_LIMIT(x)       (((x) & 0x1f) << 2)
156 #define   UHSIC_ELASTIC_OVERRUN_LIMIT(x)        (((x) & 0x1f) << 8)
157 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
158 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
159 #define   UHSIC_IDLE_WAIT(x)                    (((x) & 0x1f) << 13)
160 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
161 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
162 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
163 #define   UTMIP_XCVR_LSBIAS_SEL                 (1 << 21)
164 #define   UTMIP_XCVR_SETUP_MSB(x)               (((x) & 0x7) << 22)
165 #define   UTMIP_XCVR_HSSLEW_MSB(x)              (((x) & 0x7f) << 25)
166 #define   UTMIP_XCVR_MAX_OFFSET         2
167 #define   UTMIP_XCVR_SETUP_MAX_VALUE    0x7f
168 #define   UTMIP_XCVR_SETUP_MIN_VALUE    0
169 #define   XCVR_SETUP_MSB_CALIB(x) ((x) >> 4)
170
171 #define UTMIP_BIAS_CFG0                 0x80c
172 #define   UTMIP_OTGPD                   (1 << 11)
173 #define   UTMIP_BIASPD                  (1 << 10)
174
175 #define UHSIC_HSRX_CFG1                         0x80c
176 #define   UHSIC_HS_SYNC_START_DLY(x)            (((x) & 0x1f) << 1)
177
178 #define UTMIP_HSRX_CFG0                 0x810
179 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
180 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
181
182 #define UTMIP_HSRX_CFG1                 0x814
183 #define UHSIC_MISC_CFG0                 0x814
184 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
185 #define   UHSIC_SUSPEND_EXIT_ON_EDGE            (1 << 7)
186 #define   UHSIC_DETECT_SHORT_CONNECT            (1 << 8)
187 #define   UHSIC_FORCE_XCVR_MODE                 (1 << 15)
188
189 #define UHSIC_MISC_CFG1                         0x818
190 #define   UHSIC_PLLU_STABLE_COUNT(x)            (((x) & 0xfff) << 2)
191
192 #define UHSIC_PADS_CFG0                         0x81c
193 #define   UHSIC_TX_RTUNEN                       0xf000
194 #define   UHSIC_TX_RTUNE(x)                     (((x) & 0xf) << 12)
195
196 #define UTMIP_TX_CFG0                           0x820
197 #define UHSIC_PADS_CFG1                         0x820
198 #define   UHSIC_PD_BG                           (1 << 2)
199 #define   UHSIC_PD_TX                           (1 << 3)
200 #define   UHSIC_PD_TRK                          (1 << 4)
201 #define   UHSIC_PD_RX                           (1 << 5)
202 #define   UHSIC_PD_ZI                           (1 << 6)
203 #define   UHSIC_RX_SEL                          (1 << 7)
204 #define   UHSIC_RPD_DATA                        (1 << 9)
205 #define   UHSIC_RPD_STROBE                      (1 << 10)
206 #define   UHSIC_RPU_DATA                        (1 << 11)
207 #define   UHSIC_RPU_STROBE                      (1 << 12)
208 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
209 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
210
211 #define UTMIP_MISC_CFG0         0x824
212 #define   UTMIP_DPDM_OBSERVE            (1 << 26)
213 #define   UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
214 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J   UTMIP_DPDM_OBSERVE_SEL(0xf)
215 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K   UTMIP_DPDM_OBSERVE_SEL(0xe)
216 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
217 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
218 #define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
219 #define   FORCE_PULLDN_DM       (1 << 8)
220 #define   FORCE_PULLDN_DP       (1 << 9)
221 #define   COMB_TERMS            (1 << 0)
222 #define   ALWAYS_FREE_RUNNING_TERMS (1 << 1)
223
224 #define USB1_PREFETCH_ID               6
225 #define USB2_PREFETCH_ID               18
226 #define USB3_PREFETCH_ID               17
227
228 #define UTMIP_MISC_CFG1         0x828
229 #define   UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18)
230 #define   UTMIP_PLLU_STABLE_COUNT(x)    (((x) & 0xfff) << 6)
231
232 #define UHSIC_STAT_CFG0         0x828
233 #define   UHSIC_CONNECT_DETECT          (1 << 0)
234
235 #define UTMIP_DEBOUNCE_CFG0 0x82c
236 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
237
238 #define UTMIP_BAT_CHRG_CFG0     0x830
239 #define   UTMIP_PD_CHRG                 (1 << 0)
240 #define   UTMIP_ON_SINK_EN              (1 << 2)
241 #define   UTMIP_OP_SRC_EN               (1 << 3)
242
243 #define UTMIP_SPARE_CFG0        0x834
244 #define   FUSE_SETUP_SEL                (1 << 3)
245 #define   FUSE_ATERM_SEL                (1 << 4)
246
247 #define UTMIP_XCVR_CFG1         0x838
248 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
249 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
250 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
251 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
252
253 #define UTMIP_BIAS_CFG1         0x83c
254 #define   UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
255
256 #define FUSE_USB_CALIB_0                0x1F0
257 #define FUSE_USB_CALIB_XCVR_SETUP(x)    (((x) & 0x7F) << 0)
258
259 /* These values (in milli second) are taken from the battery charging spec */
260 #define TDP_SRC_ON_MS    100
261 #define TDPSRC_CON_MS    40
262
263 #ifdef DEBUG
264 #define DBG(stuff...)   pr_info("tegra2_usb_phy: " stuff)
265 #else
266 #define DBG(stuff...)   do {} while (0)
267 #endif
268
269 static DEFINE_SPINLOCK(utmip_pad_lock);
270 static int utmip_pad_count;
271 static int utmip_pad_state_on;
272
273 static struct tegra_xtal_freq utmip_freq_table[] = {
274         {
275                 .freq = 12000000,
276                 .enable_delay = 0x02,
277                 .stable_count = 0x2F,
278                 .active_delay = 0x04,
279                 .xtal_freq_count = 0x76,
280                 .debounce = 0x7530,
281                 .pdtrk_count = 5,
282         },
283         {
284                 .freq = 13000000,
285                 .enable_delay = 0x02,
286                 .stable_count = 0x33,
287                 .active_delay = 0x05,
288                 .xtal_freq_count = 0x7F,
289                 .debounce = 0x7EF4,
290                 .pdtrk_count = 5,
291         },
292         {
293                 .freq = 19200000,
294                 .enable_delay = 0x03,
295                 .stable_count = 0x4B,
296                 .active_delay = 0x06,
297                 .xtal_freq_count = 0xBB,
298                 .debounce = 0xBB80,
299                 .pdtrk_count = 7,
300         },
301         {
302                 .freq = 26000000,
303                 .enable_delay = 0x04,
304                 .stable_count = 0x66,
305                 .active_delay = 0x09,
306                 .xtal_freq_count = 0xFE,
307                 .debounce = 0xFDE8,
308                 .pdtrk_count = 9,
309         },
310 };
311
312 static struct tegra_xtal_freq uhsic_freq_table[] = {
313         {
314                 .freq = 12000000,
315                 .enable_delay = 0x02,
316                 .stable_count = 0x2F,
317                 .active_delay = 0x0,
318                 .xtal_freq_count = 0x1CA,
319         },
320         {
321                 .freq = 13000000,
322                 .enable_delay = 0x02,
323                 .stable_count = 0x33,
324                 .active_delay = 0x0,
325                 .xtal_freq_count = 0x1F0,
326         },
327         {
328                 .freq = 19200000,
329                 .enable_delay = 0x03,
330                 .stable_count = 0x4B,
331                 .active_delay = 0x0,
332                 .xtal_freq_count = 0x2DD,
333         },
334         {
335                 .freq = 26000000,
336                 .enable_delay = 0x04,
337                 .stable_count = 0x66,
338                 .active_delay = 0x0,
339                 .xtal_freq_count = 0x3E0,
340         },
341 };
342
343 static void usb_phy_fence_read(struct tegra_usb_phy *phy)
344 {
345         /* Fence read for coherency of AHB master intiated writes */
346         if (phy->inst == 0)
347                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB1_PREFETCH_ID));
348         else if (phy->inst == 1)
349                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB2_PREFETCH_ID));
350         else if (phy->inst == 2)
351                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB3_PREFETCH_ID));
352
353         return;
354 }
355
356 static int usb_phy_bringup_host_controller(struct tegra_usb_phy *phy)
357 {
358         unsigned long val;
359         void __iomem *base = phy->regs;
360
361         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
362         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d] - 0\n",
363                         readl(base + USB_USBSTS), readl(base + USB_PORTSC),
364                                                         phy->port_speed);
365
366         /* enable host mode */
367         val = readl(base + USB_USBMODE_REG_OFFSET);
368         val |= USB_USBMODE_HOST;
369         writel(val, base + USB_USBMODE_REG_OFFSET);
370
371         /* Enable Port Power */
372         val = readl(base + USB_PORTSC);
373         val |= USB_PORTSC_PP;
374         writel(val, base + USB_PORTSC);
375         udelay(10);
376
377         /* Check if the phy resume from LP0. When the phy resume from LP0
378          * USB register will be reset.to zero */
379         if (!readl(base + USB_ASYNCLISTADDR)) {
380                 val = readl(base + USB_USBCMD);
381                 val |= USB_USBCMD_RS;
382                 writel(val, base + USB_USBCMD);
383
384                 /* Program the field PTC based on the saved speed mode */
385                 val = readl(base + USB_PORTSC);
386                 val &= ~(USB_PORTSC_PTC(~0));
387                 if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH)
388                         val |= USB_PORTSC_PTC(5);
389                 else if (phy->port_speed == USB_PHY_PORT_SPEED_FULL)
390                         val |= USB_PORTSC_PTC(6);
391                 else if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
392                         val |= USB_PORTSC_PTC(7);
393                 writel(val, base + USB_PORTSC);
394                 udelay(10);
395
396                 /* Disable test mode by setting PTC field to NORMAL_OP */
397                 val = readl(base + USB_PORTSC);
398                 val &= ~(USB_PORTSC_PTC(~0));
399                 writel(val, base + USB_PORTSC);
400                 udelay(10);
401         }
402
403         /* Poll until CCS is enabled */
404         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
405                                                  USB_PORTSC_CCS, 2000)) {
406                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
407         }
408
409         /* Poll until PE is enabled */
410         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_PE,
411                                                  USB_PORTSC_PE, 2000)) {
412                 pr_err("%s: timeout waiting for USB_PORTSC_PE\n", __func__);
413         }
414
415         /* Clear the PCI status, to avoid an interrupt taken upon resume */
416         val = readl(base + USB_USBSTS);
417         val |= USB_USBSTS_PCI;
418         writel(val, base + USB_USBSTS);
419
420         /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
421         val = readl(base + USB_PORTSC);
422         if ((val & USB_PORTSC_PP) && (val & USB_PORTSC_PE)) {
423                 val |= USB_PORTSC_SUSP;
424                 writel(val, base + USB_PORTSC);
425                 /* Need a 4ms delay before the controller goes to suspend */
426                 mdelay(4);
427
428                 /* Wait until port suspend completes */
429                 if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_SUSP,
430                                                  USB_PORTSC_SUSP, 1000)) {
431                         pr_err("%s: timeout waiting for PORT_SUSPEND\n",
432                                                                 __func__);
433                 }
434         }
435
436         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
437                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
438
439         return 0;
440 }
441
442 static void usb_phy_wait_for_sof(struct tegra_usb_phy *phy)
443 {
444         unsigned long val;
445         void __iomem *base = phy->regs;
446
447         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
448         val = readl(base + USB_USBSTS);
449         writel(val, base + USB_USBSTS);
450         udelay(20);
451         /* wait for two SOFs */
452         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
453                 USB_USBSTS_SRI, 2500))
454                 pr_err("%s: timeout waiting for SOF\n", __func__);
455
456         val = readl(base + USB_USBSTS);
457         writel(val, base + USB_USBSTS);
458         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI, 0, 2500))
459                 pr_err("%s: timeout waiting for SOF\n", __func__);
460
461         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
462                         USB_USBSTS_SRI, 2500))
463                 pr_err("%s: timeout waiting for SOF\n", __func__);
464
465         udelay(20);
466 }
467
468 static unsigned int utmi_phy_xcvr_setup_value(struct tegra_usb_phy *phy)
469 {
470         struct tegra_utmi_config *cfg = &phy->pdata->u_cfg.utmi;
471         signed long val;
472
473         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
474         if (cfg->xcvr_use_fuses) {
475                 val = FUSE_USB_CALIB_XCVR_SETUP(
476                                 tegra_fuse_readl(FUSE_USB_CALIB_0));
477                 if (cfg->xcvr_setup_offset <= UTMIP_XCVR_MAX_OFFSET)
478                         val = val + cfg->xcvr_setup_offset;
479
480                 if (val > UTMIP_XCVR_SETUP_MAX_VALUE) {
481                         val = UTMIP_XCVR_SETUP_MAX_VALUE;
482                         pr_info("%s: reset XCVR_SETUP to max value\n",
483                                  __func__);
484                 } else if (val < UTMIP_XCVR_SETUP_MIN_VALUE) {
485                         val = UTMIP_XCVR_SETUP_MIN_VALUE;
486                         pr_info("%s: reset XCVR_SETUP to min value\n",
487                                  __func__);
488                 }
489         } else {
490                 val = cfg->xcvr_setup;
491         }
492
493         return (unsigned int) val;
494 }
495
496
497 static int utmi_phy_open(struct tegra_usb_phy *phy)
498 {
499         unsigned long parent_rate;
500         int i;
501
502         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
503         phy->utmi_pad_clk = clk_get_sys("utmip-pad", NULL);
504         if (IS_ERR(phy->utmi_pad_clk)) {
505                 pr_err("%s: can't get utmip pad clock\n", __func__);
506                 return PTR_ERR(phy->utmi_pad_clk);
507         }
508
509         phy->utmi_xcvr_setup = utmi_phy_xcvr_setup_value(phy);
510
511         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
512         for (i = 0; i < ARRAY_SIZE(utmip_freq_table); i++) {
513                 if (utmip_freq_table[i].freq == parent_rate) {
514                         phy->freq = &utmip_freq_table[i];
515                         break;
516                 }
517         }
518         if (!phy->freq) {
519                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
520                 return -EINVAL;
521         }
522
523         return 0;
524 }
525
526 static void utmi_phy_close(struct tegra_usb_phy *phy)
527 {
528         DBG("%s inst:[%d]\n", __func__, phy->inst);
529
530         clk_put(phy->utmi_pad_clk);
531 }
532
533 static int utmi_phy_pad_power_on(struct tegra_usb_phy *phy)
534 {
535         unsigned long val, flags;
536         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
537
538         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
539         clk_enable(phy->utmi_pad_clk);
540
541         spin_lock_irqsave(&utmip_pad_lock, flags);
542
543         utmip_pad_count++;
544         val = readl(pad_base + UTMIP_BIAS_CFG0);
545         val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
546         writel(val, pad_base + UTMIP_BIAS_CFG0);
547         utmip_pad_state_on = true;
548
549         spin_unlock_irqrestore(&utmip_pad_lock, flags);
550
551         clk_disable(phy->utmi_pad_clk);
552
553         return 0;
554 }
555
556 static int utmi_phy_pad_power_off(struct tegra_usb_phy *phy)
557 {
558         unsigned long val, flags;
559         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
560
561         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
562         clk_enable(phy->utmi_pad_clk);
563         spin_lock_irqsave(&utmip_pad_lock, flags);
564
565         if (!utmip_pad_count) {
566                 pr_err("%s: utmip pad already powered off\n", __func__);
567                 goto out;
568         }
569         if (--utmip_pad_count == 0) {
570                 val = readl(pad_base + UTMIP_BIAS_CFG0);
571                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
572                 writel(val, pad_base + UTMIP_BIAS_CFG0);
573                 utmip_pad_state_on = false;
574         }
575 out:
576         spin_unlock_irqrestore(&utmip_pad_lock, flags);
577         clk_disable(phy->utmi_pad_clk);
578
579         return 0;
580 }
581
582 static int utmi_phy_irq(struct tegra_usb_phy *phy)
583 {
584         void __iomem *base = phy->regs;
585         unsigned long val = 0;
586
587         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
588
589         usb_phy_fence_read(phy);
590         if (phy->pdata->u_data.host.hot_plug) {
591                 val = readl(base + USB_SUSP_CTRL);
592                 if ((val  & USB_PHY_CLK_VALID_INT_STS)) {
593                         val &= ~USB_PHY_CLK_VALID_INT_ENB |
594                                         USB_PHY_CLK_VALID_INT_STS;
595                         writel(val , (base + USB_SUSP_CTRL));
596                         pr_info("%s: usb device plugged-in\n", __func__);
597                         val = readl(base + USB_USBSTS);
598                         if (!(val  & USB_USBSTS_PCI))
599                                 return IRQ_NONE;
600                         val = readl(base + USB_PORTSC);
601                         val &= ~(USB_PORTSC_WKCN | USB_PORTSC_RWC_BITS);
602                         writel(val , (base + USB_PORTSC));
603                 }
604         }
605
606         return IRQ_HANDLED;
607 }
608
609
610 static int utmi_phy_post_resume(struct tegra_usb_phy *phy)
611 {
612         unsigned long val;
613         void __iomem *base = phy->regs;
614
615         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
616
617         val = readl(base + UTMIP_TX_CFG0);
618         val &= ~UTMIP_HS_DISCON_DISABLE;
619         writel(val, base + UTMIP_TX_CFG0);
620         return 0;
621 }
622
623 static int utmi_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
624 {
625         unsigned long val;
626         void __iomem *base = phy->regs;
627
628         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
629         val = readl(base + UTMIP_TX_CFG0);
630         val |= UTMIP_HS_DISCON_DISABLE;
631         writel(val, base + UTMIP_TX_CFG0);
632
633         usb_phy_wait_for_sof(phy);
634
635         return 0;
636 }
637
638 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
639 {
640         unsigned long val;
641         void __iomem *base = phy->regs;
642
643         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
644         if (!phy->phy_clk_on) {
645                 DBG("%s(%d) inst:[%d] phy clk is already off\n",
646                                         __func__, __LINE__, phy->inst);
647                 return 0;
648         }
649
650         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
651                 val = readl(base + USB_SUSP_CTRL);
652                 val &= ~(USB_WAKEUP_DEBOUNCE_COUNT(~0));
653                 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
654                 writel(val, base + USB_SUSP_CTRL);
655
656                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
657                 val |= UTMIP_PD_CHRG;
658                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
659         }
660
661         if (!phy->pdata->u_data.host.hot_plug) {
662                 val = readl(base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
663                 val |= (UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
664                          UTMIP_FORCE_PDZI_POWERDOWN);
665                 writel(val, base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
666         }
667
668         val = readl(base + UTMIP_XCVR_CFG1);
669         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
670                    UTMIP_FORCE_PDDR_POWERDOWN;
671         writel(val, base + UTMIP_XCVR_CFG1);
672
673         if (phy->inst != 0) {
674                 val = readl(base + UTMIP_BIAS_CFG0);
675                 val |= UTMIP_OTGPD;
676                 writel(val, base + UTMIP_BIAS_CFG0);
677         }
678
679         phy->port_speed = (readl(base + USB_PORTSC) >> 26) &
680                         USB_PORTSC_PSPD_MASK;
681
682         if (phy->pdata->u_data.host.hot_plug) {
683                 bool enable_hotplug = true;
684                 /* if it is OTG port then make sure to enable hot-plug feature
685                    only if host adaptor is connected, i.e id is low */
686                 if (phy->pdata->port_otg) {
687                         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
688                         enable_hotplug = (val & USB_ID_STATUS) ? false : true;
689                 }
690                 if (enable_hotplug) {
691                         val = readl(base + USB_PORTSC);
692                         val |= USB_PORTSC_WKCN;
693                         writel(val, base + USB_PORTSC);
694
695                         val = readl(base + USB_SUSP_CTRL);
696                         val |= USB_PHY_CLK_VALID_INT_ENB;
697                         writel(val, base + USB_SUSP_CTRL);
698                 } else {
699                         /* Disable PHY clock valid interrupts while going into suspend*/
700                         val = readl(base + USB_SUSP_CTRL);
701                         val &= ~USB_PHY_CLK_VALID_INT_ENB;
702                         writel(val, base + USB_SUSP_CTRL);
703                 }
704         }
705
706         if (phy->inst == 2) {
707                 val = readl(base + USB_PORTSC);
708                 val |= USB_PORTSC_PHCD;
709                 writel(val, base + USB_PORTSC);
710         } else {
711                 val = readl(base + USB_SUSP_CTRL);
712                 val |= USB_SUSP_SET;
713                 writel(val, base + USB_SUSP_CTRL);
714                 udelay(10);
715                 val = readl(base + USB_SUSP_CTRL);
716                 val &= ~USB_SUSP_SET;
717                 writel(val, base + USB_SUSP_CTRL);
718         }
719
720         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
721                                                                 0, 2500))
722                 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
723
724         utmi_phy_pad_power_off(phy);
725
726         phy->phy_clk_on = false;
727         phy->hw_accessible = false;
728
729         DBG("%s(%d) inst:[%d]END\n", __func__, __LINE__, phy->inst);
730
731         return 0;
732 }
733
734 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
735 {
736         unsigned long val;
737         void __iomem *base = phy->regs;
738         struct tegra_utmi_config *config = &phy->pdata->u_cfg.utmi;
739         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
740         if (phy->phy_clk_on) {
741                 DBG("%s(%d) inst:[%d] phy clk is already on\n",
742                                         __func__, __LINE__, phy->inst);
743                 return 0;
744         }
745
746         val = readl(base + USB_SUSP_CTRL);
747         val |= UTMIP_RESET;
748         writel(val, base + USB_SUSP_CTRL);
749
750         val = readl(base + UTMIP_TX_CFG0);
751         val |= UTMIP_FS_PREABMLE_J;
752         writel(val, base + UTMIP_TX_CFG0);
753
754         val = readl(base + UTMIP_HSRX_CFG0);
755         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
756         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
757         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
758         writel(val, base + UTMIP_HSRX_CFG0);
759
760         val = readl(base + UTMIP_HSRX_CFG1);
761         val &= ~(UTMIP_HS_SYNC_START_DLY(~0));
762         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
763         writel(val, base + UTMIP_HSRX_CFG1);
764
765         val = readl(base + UTMIP_DEBOUNCE_CFG0);
766         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
767         val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
768         writel(val, base + UTMIP_DEBOUNCE_CFG0);
769
770         val = readl(base + UTMIP_MISC_CFG0);
771         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
772         writel(val, base + UTMIP_MISC_CFG0);
773
774         val = readl(base + UTMIP_MISC_CFG1);
775         val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) | UTMIP_PLLU_STABLE_COUNT(~0));
776         val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |
777                 UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count);
778         writel(val, base + UTMIP_MISC_CFG1);
779
780         val = readl(base + UTMIP_PLL_CFG1);
781         val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) | UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
782         val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |
783                 UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
784         writel(val, base + UTMIP_PLL_CFG1);
785
786         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
787                 val = readl(base + USB_SUSP_CTRL);
788                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
789                 writel(val, base + USB_SUSP_CTRL);
790
791                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
792                 val &= ~UTMIP_PD_CHRG;
793                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
794         } else {
795                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
796                 val |= UTMIP_PD_CHRG;
797                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
798         }
799
800         utmi_phy_pad_power_on(phy);
801
802         val = readl(base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
803         val &= ~(UTMIP_XCVR_LSBIAS_SEL | UTMIP_FORCE_PD_POWERDOWN |
804                  UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN |
805                  UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_LSFSLEW(~0) |
806                  UTMIP_XCVR_LSRSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
807         val |= UTMIP_XCVR_SETUP(phy->utmi_xcvr_setup);
808         val |= UTMIP_XCVR_SETUP_MSB(XCVR_SETUP_MSB_CALIB(phy->utmi_xcvr_setup));
809         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
810         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
811
812         writel(val, base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
813
814         val = readl(base + UTMIP_XCVR_CFG1);
815         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
816                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
817         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
818         writel(val, base + UTMIP_XCVR_CFG1);
819
820
821         val = readl(base + UTMIP_BIAS_CFG1);
822         val &= ~(UTMIP_BIAS_PDTRK_COUNT(~0));
823         val |= UTMIP_BIAS_PDTRK_COUNT(phy->freq->pdtrk_count);
824         writel(val, base + UTMIP_BIAS_CFG1);
825
826         val = readl(base + UTMIP_SPARE_CFG0);
827         val &= ~FUSE_SETUP_SEL;
828         writel(val, base + UTMIP_SPARE_CFG0);
829
830         val = readl(base + USB_SUSP_CTRL);
831         val |= UTMIP_PHY_ENABLE;
832         writel(val, base + USB_SUSP_CTRL);
833
834         val = readl(base + USB_SUSP_CTRL);
835         val &= ~UTMIP_RESET;
836         writel(val, base + USB_SUSP_CTRL);
837
838         if (phy->inst == 0) {
839                 val = readl(base + USB_SUSP_CTRL);
840                 val &= ~USB_SUSP_SET;
841                 writel(val, base + USB_SUSP_CTRL);
842         } else {
843                 val = readl(base + USB_PORTSC);
844                 val &= ~USB_PORTSC_PHCD;
845                 writel(val, base + USB_PORTSC);
846         }
847
848         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
849                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500))
850                 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
851
852         if (phy->inst == 2) {
853                 val = readl(base + USB_PORTSC);
854                 val &= ~(USB_PORTSC_PTS(~0));
855                 writel(val, base + USB_PORTSC);
856         }
857
858         phy->phy_clk_on = true;
859         phy->hw_accessible = true;
860
861         return 0;
862 }
863
864 static void utmi_phy_restore_start(struct tegra_usb_phy *phy)
865 {
866         unsigned long val;
867         void __iomem *base = phy->regs;
868
869         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
870         val = readl(base + UTMIP_MISC_CFG0);
871         val &= ~(UTMIP_DPDM_OBSERVE_SEL(~0));
872
873         if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
874                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
875         else
876                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
877         writel(val, base + UTMIP_MISC_CFG0);
878         udelay(1);
879
880         val = readl(base + UTMIP_MISC_CFG0);
881         val |= UTMIP_DPDM_OBSERVE;
882         writel(val, base + UTMIP_MISC_CFG0);
883         udelay(10);
884 }
885
886 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
887 {
888         unsigned long val;
889         void __iomem *base = phy->regs;
890
891         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
892         val = readl(base + UTMIP_MISC_CFG0);
893         val &= ~UTMIP_DPDM_OBSERVE;
894         writel(val, base + UTMIP_MISC_CFG0);
895         udelay(10);
896 }
897
898
899 static int utmi_phy_resume(struct tegra_usb_phy *phy)
900 {
901         int status = 0;
902         unsigned long val, flags;
903         void __iomem *base = phy->regs;
904         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
905
906         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
907         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) {
908                 if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
909                         utmi_phy_restore_start(phy);
910                         usb_phy_bringup_host_controller(phy);
911                         utmi_phy_restore_end(phy);
912                 } else {
913                         /* device is plugged in when system is in LP0 */
914                         /* bring up the controller from LP0*/
915                         val = readl(base + USB_USBCMD);
916                         val |= USB_USBCMD_RESET;
917                         writel(val, base + USB_USBCMD);
918
919                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
920                                 USB_USBCMD_RESET, 0, 2500) < 0) {
921                                 pr_err("%s: timeout waiting for reset\n", __func__);
922                         }
923
924                         val = readl(base + USB_USBMODE_REG_OFFSET);
925                         val &= ~USB_USBMODE_MASK;
926                         val |= USB_USBMODE_HOST;
927                         writel(val, base + USB_USBMODE_REG_OFFSET);
928
929                         if (phy->inst == 2) {
930                                 val = readl(base + USB_PORTSC);
931                                 val &= ~USB_PORTSC_PTS(~0);
932                                 writel(val, base + USB_PORTSC);
933                         }
934                         writel(USB_USBCMD_RS, base + USB_USBCMD);
935
936                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
937                                 USB_USBCMD_RS, USB_USBCMD_RS, 2500) < 0) {
938                                 pr_err("%s: timeout waiting for run bit\n", __func__);
939                         }
940
941                         /* Enable Port Power */
942                         val = readl(base + USB_PORTSC);
943                         val |= USB_PORTSC_PP;
944                         writel(val, base + USB_PORTSC);
945                         udelay(10);
946
947                         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
948                                 readl(base + USB_USBSTS), readl(base + USB_PORTSC));
949                 }
950         } else {
951                 /* Restoring the pad powers */
952                 clk_enable(phy->utmi_pad_clk);
953
954                 spin_lock_irqsave(&utmip_pad_lock, flags);
955
956                 val = readl(pad_base + UTMIP_BIAS_CFG0);
957                 if (utmip_pad_state_on)
958                         val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
959                 else
960                         val |= (UTMIP_OTGPD | UTMIP_BIASPD);
961                 writel(val, pad_base + UTMIP_BIAS_CFG0);
962
963                 spin_unlock_irqrestore(&utmip_pad_lock, flags);
964                 clk_disable(phy->utmi_pad_clk);
965         }
966
967         return status;
968 }
969
970 static bool utmi_phy_charger_detect(struct tegra_usb_phy *phy)
971 {
972         unsigned long val;
973         void __iomem *base = phy->regs;
974         bool status;
975
976         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
977         /* Enable charger detection logic */
978         val = readl(base + UTMIP_BAT_CHRG_CFG0);
979         val |= UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN;
980         writel(val, base + UTMIP_BAT_CHRG_CFG0);
981
982         /* Source should be on for 100 ms as per USB charging spec */
983         msleep(TDP_SRC_ON_MS);
984
985         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
986         /* If charger is not connected disable the interrupt */
987         val &= ~VDAT_DET_INT_EN;
988         val |= VDAT_DET_CHG_DET;
989         writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
990
991         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
992         if (val & VDAT_DET_STS)
993                 status = true;
994         else
995                 status = false;
996
997         /* Disable charger detection logic */
998         val = readl(base + UTMIP_BAT_CHRG_CFG0);
999         val &= ~(UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN);
1000         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1001
1002         /* Delay of 40 ms before we pull the D+ as per battery charger spec */
1003         msleep(TDPSRC_CON_MS);
1004
1005         return status;
1006 }
1007
1008
1009 static int uhsic_phy_open(struct tegra_usb_phy *phy)
1010 {
1011         unsigned long parent_rate;
1012         int i;
1013
1014         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1015         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
1016         for (i = 0; i < ARRAY_SIZE(uhsic_freq_table); i++) {
1017                 if (uhsic_freq_table[i].freq == parent_rate) {
1018                         phy->freq = &uhsic_freq_table[i];
1019                         break;
1020                 }
1021         }
1022         if (!phy->freq) {
1023                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
1024                 return -EINVAL;
1025         }
1026
1027         return 0;
1028 }
1029
1030 static int uhsic_phy_irq(struct tegra_usb_phy *phy)
1031 {
1032         usb_phy_fence_read(phy);
1033         return IRQ_HANDLED;
1034 }
1035
1036 static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
1037 {
1038         unsigned long val;
1039         void __iomem *base = phy->regs;
1040         struct tegra_hsic_config *config = &phy->pdata->u_cfg.hsic;
1041
1042         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1043         if (phy->phy_clk_on) {
1044                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
1045                                                         __LINE__, phy->inst);
1046                 return 0;
1047         }
1048
1049         val = readl(base + UHSIC_PADS_CFG1);
1050         val &= ~(UHSIC_PD_BG | UHSIC_PD_TX | UHSIC_PD_TRK | UHSIC_PD_RX |
1051                         UHSIC_PD_ZI | UHSIC_RPD_DATA | UHSIC_RPD_STROBE);
1052         val |= UHSIC_RX_SEL;
1053         writel(val, base + UHSIC_PADS_CFG1);
1054         udelay(2);
1055
1056         val = readl(base + USB_SUSP_CTRL);
1057         val |= UHSIC_RESET;
1058         writel(val, base + USB_SUSP_CTRL);
1059         udelay(30);
1060
1061         val = readl(base + USB_SUSP_CTRL);
1062         val |= UHSIC_PHY_ENABLE;
1063         writel(val, base + USB_SUSP_CTRL);
1064
1065         val = readl(base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
1066         val |= UHSIC_IDLE_WAIT(config->idle_wait_delay);
1067         val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(config->elastic_underrun_limit);
1068         val |= UHSIC_ELASTIC_OVERRUN_LIMIT(config->elastic_overrun_limit);
1069         writel(val, base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
1070
1071         val = readl(base + UHSIC_HSRX_CFG1);
1072         val |= UHSIC_HS_SYNC_START_DLY(config->sync_start_delay);
1073         writel(val, base + UHSIC_HSRX_CFG1);
1074
1075         val = readl(base + UHSIC_MISC_CFG0);
1076         val |= UHSIC_SUSPEND_EXIT_ON_EDGE;
1077         writel(val, base + UHSIC_MISC_CFG0);
1078
1079         val = readl(base + UHSIC_MISC_CFG1);
1080         val |= UHSIC_PLLU_STABLE_COUNT(phy->freq->stable_count);
1081         writel(val, base + UHSIC_MISC_CFG1);
1082
1083         val = readl(base + UHSIC_PLL_CFG1);
1084         val |= UHSIC_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
1085         val |= UHSIC_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count);
1086         writel(val, base + UHSIC_PLL_CFG1);
1087
1088         val = readl(base + USB_SUSP_CTRL);
1089         val &= ~(UHSIC_RESET);
1090         writel(val, base + USB_SUSP_CTRL);
1091         udelay(2);
1092
1093         val = readl(base + USB_PORTSC);
1094         val &= ~(USB_PORTSC_PTS(~0));
1095         writel(val, base + USB_PORTSC);
1096
1097         val = readl(base + USB_TXFILLTUNING);
1098         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
1099                 val = USB_FIFO_TXFILL_THRES(0x10);
1100                 writel(val, base + USB_TXFILLTUNING);
1101         }
1102
1103         val = readl(base + USB_PORTSC);
1104         val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN);
1105         writel(val, base + USB_PORTSC);
1106
1107         val = readl(base + UHSIC_PADS_CFG0);
1108         val &= ~(UHSIC_TX_RTUNEN);
1109         /* set Rtune impedance to 40 ohm */
1110         val |= UHSIC_TX_RTUNE(0);
1111         writel(val, base + UHSIC_PADS_CFG0);
1112
1113         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
1114                                                 USB_PHY_CLK_VALID, 2500)) {
1115                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
1116                 return -ETIMEDOUT;
1117         }
1118
1119         phy->phy_clk_on = true;
1120         phy->hw_accessible = true;
1121
1122         return 0;
1123 }
1124
1125 static int uhsic_phy_power_off(struct tegra_usb_phy *phy)
1126 {
1127         unsigned long val;
1128         void __iomem *base = phy->regs;
1129
1130         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1131         if (!phy->phy_clk_on) {
1132                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
1133                                                         __LINE__, phy->inst);
1134                 return 0;
1135         }
1136
1137         val = readl(base + UHSIC_PADS_CFG1);
1138         val &= ~UHSIC_RPU_STROBE;
1139         val |= UHSIC_RPD_STROBE;
1140         writel(val, base + UHSIC_PADS_CFG1);
1141
1142         val = readl(base + USB_SUSP_CTRL);
1143         val |= UHSIC_RESET;
1144         writel(val, base + USB_SUSP_CTRL);
1145         udelay(30);
1146
1147         val = readl(base + USB_SUSP_CTRL);
1148         val &= ~UHSIC_PHY_ENABLE;
1149         writel(val, base + USB_SUSP_CTRL);
1150
1151         phy->phy_clk_on = false;
1152         phy->hw_accessible = false;
1153
1154         return 0;
1155 }
1156
1157 static int uhsic_phy_bus_port_power(struct tegra_usb_phy *phy)
1158 {
1159         unsigned long val;
1160         void __iomem *base = phy->regs;
1161
1162         val = readl(base + UHSIC_MISC_CFG0);
1163         val |= UHSIC_DETECT_SHORT_CONNECT;
1164         writel(val, base + UHSIC_MISC_CFG0);
1165         udelay(1);
1166
1167         val = readl(base + UHSIC_MISC_CFG0);
1168         val |= UHSIC_FORCE_XCVR_MODE;
1169         writel(val, base + UHSIC_MISC_CFG0);
1170
1171         val = readl(base + UHSIC_PADS_CFG1);
1172         val &= ~UHSIC_RPD_STROBE;
1173         val |= UHSIC_RPU_STROBE;
1174         writel(val, base + UHSIC_PADS_CFG1);
1175
1176         val = readl(base + USB_USBCMD);
1177         val &= ~USB_USBCMD_RS;
1178         writel(val, base + USB_USBCMD);
1179
1180         if (phy->pdata->ops && phy->pdata->ops->port_power)
1181                 phy->pdata->ops->port_power();
1182
1183         if (usb_phy_reg_status_wait(base + UHSIC_STAT_CFG0,
1184                         UHSIC_CONNECT_DETECT, UHSIC_CONNECT_DETECT, 2000)) {
1185                 pr_err("%s: timeout waiting for UHSIC_CONNECT_DETECT\n",
1186                                                                 __func__);
1187                 return -ETIMEDOUT;
1188         }
1189
1190 /* FIXME : need to check whether this piece is required or not
1191         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_LS(2),
1192                                                 USB_PORTSC_LS(2), 2000)) {
1193                 pr_err("%s: timeout waiting for dplus state\n", __func__);
1194                 return -ETIMEDOUT;
1195         }
1196 */
1197         return 0;
1198 }
1199
1200
1201 static int uhsic_phy_bus_reset(struct tegra_usb_phy *phy)
1202 {
1203         unsigned long val;
1204         void __iomem *base = phy->regs;
1205
1206         val = readl(base + USB_PORTSC);
1207         val |= USB_PORTSC_PTC(5);
1208         writel(val, base + USB_PORTSC);
1209         udelay(2);
1210
1211         val = readl(base + USB_PORTSC);
1212         val &= ~(USB_PORTSC_PTC(~0));
1213         writel(val, base + USB_PORTSC);
1214         udelay(2);
1215
1216         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_LS(0),
1217                                                  0, 2000)) {
1218                 pr_err("%s: timeout waiting for USB_PORTSC_LS\n", __func__);
1219                 return -ETIMEDOUT;
1220         }
1221
1222         /* Poll until CCS is enabled */
1223         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
1224                                                  USB_PORTSC_CCS, 2000)) {
1225                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
1226                 return -ETIMEDOUT;
1227         }
1228
1229         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_PSPD(2),
1230                                                  USB_PORTSC_PSPD(2), 2000)) {
1231                 pr_err("%s: timeout waiting for USB_PORTSC_PSPD\n", __func__);
1232                 return -ETIMEDOUT;
1233         }
1234
1235         val = readl(base + USB_USBCMD);
1236         val &= ~USB_USBCMD_RS;
1237         writel(val, base + USB_USBCMD);
1238
1239         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
1240                                                  USB_USBSTS_HCH, 2000)) {
1241                 pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
1242                 return -ETIMEDOUT;
1243         }
1244
1245         val = readl(base + UHSIC_PADS_CFG1);
1246         val &= ~UHSIC_RPU_STROBE;
1247         val |= UHSIC_RPD_STROBE;
1248         writel(val, base + UHSIC_PADS_CFG1);
1249
1250         mdelay(50);
1251
1252         val = readl(base + UHSIC_PADS_CFG1);
1253         val &= ~UHSIC_RPD_STROBE;
1254         val |= UHSIC_RPU_STROBE;
1255         writel(val, base + UHSIC_PADS_CFG1);
1256
1257         val = readl(base + USB_USBCMD);
1258         val |= USB_USBCMD_RS;
1259         writel(val, base + USB_USBCMD);
1260
1261         val = readl(base + UHSIC_PADS_CFG1);
1262         val &= ~UHSIC_RPU_STROBE;
1263         writel(val, base + UHSIC_PADS_CFG1);
1264
1265         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
1266                                                  USB_USBCMD_RS, 2000)) {
1267                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
1268                 return -ETIMEDOUT;
1269         }
1270
1271         return 0;
1272 }
1273
1274
1275 static int uhsic_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1276 {
1277         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1278         usb_phy_wait_for_sof(phy);
1279
1280         return 0;
1281 }
1282
1283 static int uhsic_phy_resume(struct tegra_usb_phy *phy)
1284 {
1285         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1286         uhsic_phy_bus_port_power(phy);
1287
1288         return 0;
1289 }
1290
1291
1292 static int uhsic_phy_post_resume(struct tegra_usb_phy *phy)
1293 {
1294         unsigned long val;
1295         void __iomem *base = phy->regs;
1296
1297         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1298         val = readl(base + USB_TXFILLTUNING);
1299         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
1300                 val = USB_FIFO_TXFILL_THRES(0x10);
1301                 writel(val, base + USB_TXFILLTUNING);
1302         }
1303
1304         return 0;
1305 }
1306
1307 static void ulpi_set_trimmer(struct tegra_usb_phy *phy)
1308 {
1309         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
1310         void __iomem *base = phy->regs;
1311         unsigned long val;
1312
1313         val = ULPI_DATA_TRIMMER_SEL(config->data_trimmer);
1314         val |= ULPI_STPDIRNXT_TRIMMER_SEL(config->stpdirnxt_trimmer);
1315         val |= ULPI_DIR_TRIMMER_SEL(config->dir_trimmer);
1316         writel(val, base + ULPI_TIMING_CTRL_1);
1317         udelay(10);
1318
1319         val |= ULPI_DATA_TRIMMER_LOAD;
1320         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
1321         val |= ULPI_DIR_TRIMMER_LOAD;
1322         writel(val, base + ULPI_TIMING_CTRL_1);
1323 }
1324
1325
1326 static int ulpi_link_phy_open(struct tegra_usb_phy *phy)
1327 {
1328         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
1329         int err = 0;
1330
1331         phy->ulpi_clk = NULL;
1332
1333         if (config->clk) {
1334                 phy->ulpi_clk = clk_get_sys(NULL, config->clk);
1335                 if (IS_ERR(phy->ulpi_clk)) {
1336                         pr_err("%s: can't get ulpi clock\n", __func__);
1337                         err = -ENXIO;
1338                 }
1339         }
1340
1341         phy->ulpi_vp = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
1342         phy->ulpi_vp->io_priv = phy->regs + ULPI_VIEWPORT;
1343
1344         return err;
1345 }
1346
1347 static void ulpi_link_phy_close(struct tegra_usb_phy *phy)
1348 {
1349         DBG("%s inst:[%d]\n", __func__, phy->inst);
1350         if (phy->ulpi_clk)
1351                 clk_put(phy->ulpi_clk);
1352 }
1353
1354 static int ulpi_link_phy_irq(struct tegra_usb_phy *phy)
1355 {
1356         usb_phy_fence_read(phy);
1357         return IRQ_HANDLED;
1358 }
1359
1360 static int ulpi_link_phy_power_off(struct tegra_usb_phy *phy)
1361 {
1362         unsigned long val;
1363         void __iomem *base = phy->regs;
1364         int ret;
1365
1366         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1367         if (!phy->phy_clk_on) {
1368                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
1369                                                         __LINE__, phy->inst);
1370                 return 0;
1371         }
1372
1373         /* Disable VbusValid, SessEnd comparators */
1374         ret = otg_io_write(phy->ulpi_vp, 0x00, 0x0D);
1375         if (ret)
1376                 pr_err("%s: ulpi write 0x0D failed\n", __func__);
1377
1378         ret = otg_io_write(phy->ulpi_vp, 0x00, 0x10);
1379         if (ret)
1380                 pr_err("%s: ulpi write 0x10 failed\n", __func__);
1381
1382         /* Disable IdFloat comparator */
1383         ret = otg_io_write(phy->ulpi_vp, 0x00, 0x19);
1384         if (ret)
1385                 pr_err("%s: ulpi write 0x19 failed\n", __func__);
1386
1387         ret = otg_io_write(phy->ulpi_vp, 0x00, 0x1D);
1388         if (ret)
1389                 pr_err("%s: ulpi write 0x1D failed\n", __func__);
1390
1391         phy->port_speed = (readl(base + USB_PORTSC) >> 26) &
1392                         USB_PORTSC_PSPD_MASK;
1393
1394         /* Clear WKCN/WKDS/WKOC wake-on events that can cause the USB
1395          * Controller to immediately bring the ULPI PHY out of low power
1396          */
1397         val = readl(base + USB_PORTSC);
1398         val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN);
1399         writel(val, base + USB_PORTSC);
1400
1401         /* Put the PHY in the low power mode */
1402         val = readl(base + USB_PORTSC);
1403         val |= USB_PORTSC_PHCD;
1404         writel(val, base + USB_PORTSC);
1405
1406         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
1407                                                          0, 2500)) {
1408                 pr_err("%s: timeout waiting for phy to stop\n", __func__);
1409         }
1410
1411         if (phy->ulpi_clk)
1412                 clk_disable(phy->ulpi_clk);
1413
1414         phy->phy_clk_on = false;
1415         phy->hw_accessible = false;
1416
1417         return 0;
1418 }
1419
1420 static int ulpi_link_phy_power_on(struct tegra_usb_phy *phy)
1421 {
1422         int ret;
1423         unsigned long val;
1424         void __iomem *base = phy->regs;
1425
1426         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1427         if (phy->phy_clk_on) {
1428                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
1429                                                         __LINE__, phy->inst);
1430                 return 0;
1431         }
1432
1433         if (phy->ulpi_clk) {
1434                 clk_enable(phy->ulpi_clk);
1435                 mdelay(1);
1436         }
1437
1438         val = readl(base + USB_SUSP_CTRL);
1439         val |= UHSIC_RESET;
1440         writel(val, base + USB_SUSP_CTRL);
1441
1442         val = readl(base + ULPI_TIMING_CTRL_0);
1443         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
1444         writel(val, base + ULPI_TIMING_CTRL_0);
1445
1446         val = readl(base + USB_SUSP_CTRL);
1447         val |= ULPI_PHY_ENABLE;
1448         writel(val, base + USB_SUSP_CTRL);
1449
1450         val = readl(base + USB_SUSP_CTRL);
1451         val |= USB_SUSP_CLR;
1452         writel(val, base + USB_SUSP_CTRL);
1453
1454         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
1455                                                 USB_PHY_CLK_VALID, 2500))
1456                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
1457
1458         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_CLKEN,
1459                                                 USB_CLKEN, 2500))
1460                 pr_err("%s: timeout waiting for AHB clock\n", __func__);
1461
1462         val = readl(base + USB_SUSP_CTRL);
1463         val &= ~USB_SUSP_CLR;
1464         writel(val, base + USB_SUSP_CTRL);
1465
1466         val = 0;
1467         writel(val, base + ULPI_TIMING_CTRL_1);
1468
1469         ulpi_set_trimmer(phy);
1470
1471         /* Fix VbusInvalid due to floating VBUS */
1472         ret = otg_io_write(phy->ulpi_vp, 0x40, 0x08);
1473         if (ret) {
1474                 pr_err("%s: ulpi write failed\n", __func__);
1475                 return ret;
1476         }
1477
1478         ret = otg_io_write(phy->ulpi_vp, 0x80, 0x0B);
1479         if (ret) {
1480                 pr_err("%s: ulpi write failed\n", __func__);
1481                 return ret;
1482         }
1483
1484         val = readl(base + USB_PORTSC);
1485         val |= USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN;
1486         writel(val, base + USB_PORTSC);
1487
1488         phy->phy_clk_on = true;
1489         phy->hw_accessible = true;
1490
1491         return 0;
1492 }
1493
1494 static inline void ulpi_link_phy_set_tristate(bool enable)
1495 {
1496 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1497         int tristate = (enable) ? TEGRA_TRI_TRISTATE : TEGRA_TRI_NORMAL;
1498
1499         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAA, tristate);
1500         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAB, tristate);
1501         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UDA, tristate);
1502 #endif
1503 }
1504
1505 static void ulpi_link_phy_restore_start(struct tegra_usb_phy *phy)
1506 {
1507         unsigned long val;
1508         void __iomem *base = phy->regs;
1509
1510         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1511
1512         /*Tristate ulpi interface before USB controller resume*/
1513         ulpi_link_phy_set_tristate(true);
1514
1515         val = readl(base + ULPI_TIMING_CTRL_0);
1516         val &= ~ULPI_OUTPUT_PINMUX_BYP;
1517         writel(val, base + ULPI_TIMING_CTRL_0);
1518 }
1519
1520 static void ulpi_link_phy_restore_end(struct tegra_usb_phy *phy)
1521 {
1522         unsigned long val;
1523         void __iomem *base = phy->regs;
1524
1525         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1526
1527         val = readl(base + ULPI_TIMING_CTRL_0);
1528         val |= ULPI_OUTPUT_PINMUX_BYP;
1529         writel(val, base + ULPI_TIMING_CTRL_0);
1530
1531         ulpi_link_phy_set_tristate(false);
1532 }
1533
1534 static int ulpi_link_phy_resume(struct tegra_usb_phy *phy)
1535 {
1536         int status = 0;
1537
1538         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1539         if (phy->pdata->u_data.host.power_off_on_suspend) {
1540                 status = ulpi_link_phy_power_on(phy);
1541                 if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
1542                         ulpi_link_phy_restore_start(phy);
1543                         usb_phy_bringup_host_controller(phy);
1544                         ulpi_link_phy_restore_end(phy);
1545                 }
1546         }
1547
1548         return status;
1549 }
1550
1551
1552 static int ulpi_null_phy_power_off(struct tegra_usb_phy *phy)
1553 {
1554         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1555
1556         if (!phy->phy_clk_on) {
1557                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
1558                                                         __LINE__, phy->inst);
1559                 return 0;
1560         }
1561
1562         phy->phy_clk_on = false;
1563         phy->hw_accessible = false;
1564
1565         return 0;
1566 }
1567
1568 static int ulpi_null_phy_irq(struct tegra_usb_phy *phy)
1569 {
1570         usb_phy_fence_read(phy);
1571         return IRQ_HANDLED;
1572 }
1573
1574 static int ulpi_null_phy_lp0_resume(struct tegra_usb_phy *phy)
1575 {
1576         unsigned long val;
1577         void __iomem *base = phy->regs;
1578
1579         val = readl(base + USB_USBCMD);
1580         val |= USB_USBCMD_RESET;
1581         writel(val, base + USB_USBCMD);
1582
1583         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1584                 USB_USBCMD_RESET, 0, 2500) < 0) {
1585                 pr_err("%s: timeout waiting for reset\n", __func__);
1586         }
1587
1588         val = readl(base + USB_USBMODE_REG_OFFSET);
1589         val &= ~USB_USBMODE_MASK;
1590         val |= USB_USBMODE_HOST;
1591         writel(val, base + USB_USBMODE_REG_OFFSET);
1592
1593         val = readl(base + USB_USBCMD);
1594         val |= USB_USBCMD_RS;
1595         writel(val, base + USB_USBCMD);
1596         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
1597                                                  USB_USBCMD_RS, 2000)) {
1598                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
1599                 return -ETIMEDOUT;
1600         }
1601
1602         /* Enable Port Power */
1603         val = readl(base + USB_PORTSC);
1604         val |= USB_PORTSC_PP;
1605         writel(val, base + USB_PORTSC);
1606         udelay(10);
1607
1608         /* disable ULPI pinmux bypass */
1609         val = readl(base + ULPI_TIMING_CTRL_0);
1610         val &= ~ULPI_OUTPUT_PINMUX_BYP;
1611         writel(val, base + ULPI_TIMING_CTRL_0);
1612
1613         return 0;
1614 }
1615
1616 static int ulpi_null_phy_power_on(struct tegra_usb_phy *phy)
1617 {
1618         unsigned long val;
1619         void __iomem *base = phy->regs;
1620         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
1621         static bool cold_boot = true;
1622
1623         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1624         if (phy->phy_clk_on) {
1625                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
1626                                                         __LINE__, phy->inst);
1627                 return 0;
1628         }
1629
1630         val = readl(base + USB_SUSP_CTRL);
1631         val |= UHSIC_RESET;
1632         writel(val, base + USB_SUSP_CTRL);
1633
1634         val = readl(base + ULPI_TIMING_CTRL_0);
1635         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
1636         writel(val, base + ULPI_TIMING_CTRL_0);
1637
1638         val = readl(base + USB_SUSP_CTRL);
1639         val |= ULPI_PHY_ENABLE;
1640         writel(val, base + USB_SUSP_CTRL);
1641         udelay(10);
1642
1643         /* set timming parameters */
1644         val = readl(base + ULPI_TIMING_CTRL_0);
1645         val |= ULPI_SHADOW_CLK_LOOPBACK_EN;
1646         val |= ULPI_SHADOW_CLK_SEL;
1647         val |= ULPI_LBK_PAD_EN;
1648         val |= ULPI_SHADOW_CLK_DELAY(config->shadow_clk_delay);
1649         val |= ULPI_CLOCK_OUT_DELAY(config->clock_out_delay);
1650         val |= ULPI_LBK_PAD_E_INPUT_OR;
1651         writel(val, base + ULPI_TIMING_CTRL_0);
1652
1653         writel(0, base + ULPI_TIMING_CTRL_1);
1654         udelay(10);
1655
1656         /* start internal 60MHz clock */
1657         val = readl(base + ULPIS2S_CTRL);
1658         val |= ULPIS2S_ENA;
1659         val |= ULPIS2S_SUPPORT_DISCONNECT;
1660         val |= ULPIS2S_SPARE((phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) ? 3 : 1);
1661         val |= ULPIS2S_PLLU_MASTER_BLASTER60;
1662         writel(val, base + ULPIS2S_CTRL);
1663
1664         /* select ULPI_CORE_CLK_SEL to SHADOW_CLK */
1665         val = readl(base + ULPI_TIMING_CTRL_0);
1666         val |= ULPI_CORE_CLK_SEL;
1667         writel(val, base + ULPI_TIMING_CTRL_0);
1668         udelay(10);
1669
1670         /* enable ULPI null phy clock - can't set the trimmers before this */
1671         val = readl(base + ULPI_TIMING_CTRL_0);
1672         val |= ULPI_CLK_OUT_ENA;
1673         writel(val, base + ULPI_TIMING_CTRL_0);
1674         udelay(10);
1675
1676         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
1677                                                  USB_PHY_CLK_VALID, 2500)) {
1678                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
1679                 return -ETIMEDOUT;
1680         }
1681
1682         /* set ULPI trimmers */
1683         ulpi_set_trimmer(phy);
1684
1685         if (cold_boot) {
1686                 val = readl(base + ULPI_TIMING_CTRL_0);
1687                 val |= ULPI_CLK_PADOUT_ENA;
1688                 writel(val, base + ULPI_TIMING_CTRL_0);
1689                 cold_boot = false;
1690         } else {
1691                 if (!readl(base + USB_ASYNCLISTADDR))
1692                         ulpi_null_phy_lp0_resume(phy);
1693         }
1694         udelay(10);
1695
1696         phy->phy_clk_on = true;
1697         phy->hw_accessible = true;
1698
1699         return 0;
1700 }
1701
1702
1703 static int ulpi_null_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1704 {
1705         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1706
1707         usb_phy_wait_for_sof(phy);
1708         return 0;
1709 }
1710
1711 static int ulpi_null_phy_resume(struct tegra_usb_phy *phy)
1712 {
1713         unsigned long val;
1714         void __iomem *base = phy->regs;
1715
1716         if (!readl(base + USB_ASYNCLISTADDR)) {
1717                 /* enable ULPI CLK output pad */
1718                 val = readl(base + ULPI_TIMING_CTRL_0);
1719                 val |= ULPI_CLK_PADOUT_ENA;
1720                 writel(val, base + ULPI_TIMING_CTRL_0);
1721
1722                 /* enable ULPI pinmux bypass */
1723                 val = readl(base + ULPI_TIMING_CTRL_0);
1724                 val |= ULPI_OUTPUT_PINMUX_BYP;
1725                 writel(val, base + ULPI_TIMING_CTRL_0);
1726                 udelay(5);
1727         }
1728
1729         return 0;
1730 }
1731
1732
1733
1734 static struct tegra_usb_phy_ops utmi_phy_ops = {
1735         .open           = utmi_phy_open,
1736         .close          = utmi_phy_close,
1737         .irq            = utmi_phy_irq,
1738         .power_on       = utmi_phy_power_on,
1739         .power_off      = utmi_phy_power_off,
1740         .pre_resume = utmi_phy_pre_resume,
1741         .resume = utmi_phy_resume,
1742         .post_resume    = utmi_phy_post_resume,
1743         .charger_detect = utmi_phy_charger_detect,
1744 };
1745
1746 static struct tegra_usb_phy_ops uhsic_phy_ops = {
1747         .open           = uhsic_phy_open,
1748         .irq            = uhsic_phy_irq,
1749         .power_on       = uhsic_phy_power_on,
1750         .power_off      = uhsic_phy_power_off,
1751         .pre_resume     = uhsic_phy_pre_resume,
1752         .resume         = uhsic_phy_resume,
1753         .post_resume    = uhsic_phy_post_resume,
1754         .port_power     = uhsic_phy_bus_port_power,
1755         .bus_reset      = uhsic_phy_bus_reset,
1756 };
1757
1758 static struct tegra_usb_phy_ops ulpi_link_phy_ops = {
1759         .open           = ulpi_link_phy_open,
1760         .close  = ulpi_link_phy_close,
1761         .irq            = ulpi_link_phy_irq,
1762         .power_on       = ulpi_link_phy_power_on,
1763         .power_off      = ulpi_link_phy_power_off,
1764         .resume         = ulpi_link_phy_resume,
1765 };
1766
1767 static struct tegra_usb_phy_ops ulpi_null_phy_ops = {
1768         .irq            = ulpi_null_phy_irq,
1769         .power_on       = ulpi_null_phy_power_on,
1770         .power_off      = ulpi_null_phy_power_off,
1771         .pre_resume = ulpi_null_phy_pre_resume,
1772         .resume = ulpi_null_phy_resume,
1773 };
1774
1775 static struct tegra_usb_phy_ops icusb_phy_ops;
1776
1777
1778 static struct tegra_usb_phy_ops *phy_ops[] = {
1779         [TEGRA_USB_PHY_INTF_UTMI] = &utmi_phy_ops,
1780         [TEGRA_USB_PHY_INTF_ULPI_LINK] = &ulpi_link_phy_ops,
1781         [TEGRA_USB_PHY_INTF_ULPI_NULL] = &ulpi_null_phy_ops,
1782         [TEGRA_USB_PHY_INTF_HSIC] = &uhsic_phy_ops,
1783         [TEGRA_USB_PHY_INTF_ICUSB] = &icusb_phy_ops,
1784 };
1785
1786 int tegra2_usb_phy_init_ops(struct tegra_usb_phy *phy)
1787 {
1788         phy->ops = phy_ops[phy->pdata->phy_intf];
1789
1790         return 0;
1791 }