Merge commit 'main-jb-2012.08.03-B4' into t114-0806
[linux-2.6.git] / arch / arm / mach-tegra / tegra2_usb_phy.c
1 /*
2  * arch/arm/mach-tegra/tegra2_usb_phy.c
3  *
4  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
5  *
6  *
7  * This software is licensed under the terms of the GNU General Public
8  * License version 2, as published by the Free Software Foundation, and
9  * may be copied, distributed, and modified under those terms.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17 #include <linux/resource.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/slab.h>
21 #include <linux/err.h>
22 #include <linux/platform_device.h>
23 #include <linux/io.h>
24 #include <linux/gpio.h>
25 #include <linux/usb/otg.h>
26 #include <linux/usb/ulpi.h>
27 #include <linux/interrupt.h>
28 #include <linux/clk.h>
29 #include <linux/regulator/consumer.h>
30 #include <linux/platform_data/tegra_usb.h>
31
32 #include <asm/mach-types.h>
33
34 #include <mach/clk.h>
35 #include <mach/iomap.h>
36 #include <mach/pinmux.h>
37 #include <mach/pinmux-tegra20.h>
38 #include <mach/usb_phy.h>
39
40 #include "tegra_usb_phy.h"
41 #include "gpio-names.h"
42 #include "fuse.h"
43
44 #define USB_USBCMD              0x140
45 #define   USB_USBCMD_RS         (1 << 0)
46 #define   USB_USBCMD_RESET      (1 << 1)
47
48 #define USB_USBSTS              0x144
49 #define   USB_USBSTS_PCI        (1 << 2)
50 #define   USB_USBSTS_SRI        (1 << 7)
51 #define   USB_USBSTS_HCH        (1 << 12)
52
53 #define USB_USBINTR             0x148
54
55 #define USB_ASYNCLISTADDR       0x158
56
57 #define USB_TXFILLTUNING                0x164
58 #define USB_FIFO_TXFILL_THRES(x)   (((x) & 0x1f) << 16)
59 #define USB_FIFO_TXFILL_MASK    0x3f0000
60
61 #define ULPI_VIEWPORT           0x170
62 #define   ULPI_WAKEUP           (1 << 31)
63 #define   ULPI_RUN              (1 << 30)
64 #define   ULPI_RD_WR            (1 << 29)
65
66 #define USB_PORTSC              0x184
67 #define   USB_PORTSC_PTS(x)     (((x) & 0x3) << 30)
68 #define   USB_PORTSC_PSPD(x)    (((x) & 0x3) << 26)
69 #define   USB_PORTSC_PHCD       (1 << 23)
70 #define   USB_PORTSC_WKOC       (1 << 22)
71 #define   USB_PORTSC_WKDS       (1 << 21)
72 #define   USB_PORTSC_WKCN       (1 << 20)
73 #define   USB_PORTSC_PTC(x)     (((x) & 0xf) << 16)
74 #define   USB_PORTSC_PP (1 << 12)
75 #define   USB_PORTSC_LS(x) (((x) & 0x3) << 10)
76 #define   USB_PORTSC_SUSP       (1 << 7)
77 #define   USB_PORTSC_RESUME     (1 << 6)
78 #define   USB_PORTSC_OCC        (1 << 5)
79 #define   USB_PORTSC_PEC        (1 << 3)
80 #define   USB_PORTSC_PE         (1 << 2)
81 #define   USB_PORTSC_CSC        (1 << 1)
82 #define   USB_PORTSC_CCS        (1 << 0)
83 #define   USB_PORTSC_RWC_BITS (USB_PORTSC_CSC | USB_PORTSC_PEC | USB_PORTSC_OCC)
84 #define   USB_PORTSC_PSPD_MASK  3
85
86 #define USB_USBMODE_REG_OFFSET  0x1a8
87 #define   USB_USBMODE_MASK              (3 << 0)
88 #define   USB_USBMODE_HOST              (3 << 0)
89 #define   USB_USBMODE_DEVICE    (2 << 0)
90
91 #define USB_SUSP_CTRL           0x400
92 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
93 #define   USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
94 #define   USB_SUSP_CLR          (1 << 5)
95 #define   USB_CLKEN             (1 << 6)
96 #define   USB_PHY_CLK_VALID (1 << 7)
97 #define   USB_PHY_CLK_VALID_INT_ENB    (1 << 9)
98 #define   UTMIP_RESET           (1 << 11)
99 #define   UHSIC_RESET           (1 << 11)
100 #define   UTMIP_PHY_ENABLE      (1 << 12)
101 #define   UHSIC_PHY_ENABLE      (1 << 12)
102 #define   ULPI_PHY_ENABLE       (1 << 13)
103 #define   USB_SUSP_SET          (1 << 14)
104 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
105 #define   USB_PHY_CLK_VALID_INT_STS     (1 << 8)
106
107 #define USB_PHY_VBUS_WAKEUP_ID  0x408
108 #define   VDAT_DET_INT_EN       (1 << 16)
109 #define   VDAT_DET_CHG_DET      (1 << 17)
110 #define   VDAT_DET_STS          (1 << 18)
111 #define   USB_ID_STATUS         (1 << 2)
112
113 #define USB1_LEGACY_CTRL        0x410
114 #define   USB1_NO_LEGACY_MODE                   (1 << 0)
115 #define   USB1_VBUS_SENSE_CTL_MASK              (3 << 1)
116 #define   USB1_VBUS_SENSE_CTL_VBUS_WAKEUP       (0 << 1)
117 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
118                                                 (1 << 1)
119 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD       (2 << 1)
120 #define   USB1_VBUS_SENSE_CTL_A_SESS_VLD        (3 << 1)
121
122 #define ULPIS2S_CTRL            0x418
123 #define   ULPIS2S_ENA                   (1 << 0)
124 #define   ULPIS2S_SUPPORT_DISCONNECT    (1 << 2)
125 #define   ULPIS2S_PLLU_MASTER_BLASTER60 (1 << 3)
126 #define   ULPIS2S_SPARE(x)              (((x) & 0xF) << 8)
127 #define   ULPIS2S_FORCE_ULPI_CLK_OUT    (1 << 12)
128 #define   ULPIS2S_DISCON_DONT_CHECK_SE0 (1 << 13)
129 #define   ULPIS2S_SUPPORT_HS_KEEP_ALIVE (1 << 14)
130 #define   ULPIS2S_DISABLE_STP_PU        (1 << 15)
131 #define   ULPIS2S_SLV0_CLAMP_XMIT       (1 << 16)
132
133 #define ULPI_TIMING_CTRL_0      0x424
134 #define   ULPI_CLOCK_OUT_DELAY(x)       ((x) & 0x1F)
135 #define   ULPI_OUTPUT_PINMUX_BYP        (1 << 10)
136 #define   ULPI_CLKOUT_PINMUX_BYP        (1 << 11)
137 #define   ULPI_SHADOW_CLK_LOOPBACK_EN   (1 << 12)
138 #define   ULPI_SHADOW_CLK_SEL           (1 << 13)
139 #define   ULPI_CORE_CLK_SEL             (1 << 14)
140 #define   ULPI_SHADOW_CLK_DELAY(x)      (((x) & 0x1F) << 16)
141 #define   ULPI_LBK_PAD_EN               (1 << 26)
142 #define   ULPI_LBK_PAD_E_INPUT_OR       (1 << 27)
143 #define   ULPI_CLK_OUT_ENA              (1 << 28)
144 #define   ULPI_CLK_PADOUT_ENA           (1 << 29)
145
146 #define ULPI_TIMING_CTRL_1      0x428
147 #define   ULPI_DATA_TRIMMER_LOAD        (1 << 0)
148 #define   ULPI_DATA_TRIMMER_SEL(x)      (((x) & 0x7) << 1)
149 #define   ULPI_STPDIRNXT_TRIMMER_LOAD   (1 << 16)
150 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
151 #define   ULPI_DIR_TRIMMER_LOAD         (1 << 24)
152 #define   ULPI_DIR_TRIMMER_SEL(x)       (((x) & 0x7) << 25)
153
154 #define UTMIP_PLL_CFG1          0x804
155 #define UHSIC_PLL_CFG1                          0x804
156 #define   UTMIP_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
157 #define   UTMIP_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 27)
158 #define   UHSIC_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
159 #define   UHSIC_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 14)
160
161 #define UTMIP_XCVR_UHSIC_HSRX_CFG0              0x808
162 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
163 #define   UHSIC_ELASTIC_UNDERRUN_LIMIT(x)       (((x) & 0x1f) << 2)
164 #define   UHSIC_ELASTIC_OVERRUN_LIMIT(x)        (((x) & 0x1f) << 8)
165 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
166 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
167 #define   UHSIC_IDLE_WAIT(x)                    (((x) & 0x1f) << 13)
168 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
169 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
170 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
171 #define   UTMIP_XCVR_LSBIAS_SEL                 (1 << 21)
172 #define   UTMIP_XCVR_SETUP_MSB(x)               (((x) & 0x7) << 22)
173 #define   UTMIP_XCVR_HSSLEW_MSB(x)              (((x) & 0x7f) << 25)
174 #define   UTMIP_XCVR_MAX_OFFSET         2
175 #define   UTMIP_XCVR_SETUP_MAX_VALUE    0x7f
176 #define   UTMIP_XCVR_SETUP_MIN_VALUE    0
177 #define   XCVR_SETUP_MSB_CALIB(x) ((x) >> 4)
178
179 #define UTMIP_BIAS_CFG0                 0x80c
180 #define   UTMIP_OTGPD                   (1 << 11)
181 #define   UTMIP_BIASPD                  (1 << 10)
182
183 #define UHSIC_HSRX_CFG1                         0x80c
184 #define   UHSIC_HS_SYNC_START_DLY(x)            (((x) & 0x1f) << 1)
185
186 #define UTMIP_HSRX_CFG0                 0x810
187 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
188 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
189
190 #define UTMIP_HSRX_CFG1                 0x814
191 #define UHSIC_MISC_CFG0                 0x814
192 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
193 #define   UHSIC_SUSPEND_EXIT_ON_EDGE            (1 << 7)
194 #define   UHSIC_DETECT_SHORT_CONNECT            (1 << 8)
195 #define   UHSIC_FORCE_XCVR_MODE                 (1 << 15)
196
197 #define UHSIC_MISC_CFG1                         0x818
198 #define   UHSIC_PLLU_STABLE_COUNT(x)            (((x) & 0xfff) << 2)
199
200 #define UHSIC_PADS_CFG0                         0x81c
201 #define   UHSIC_TX_RTUNEN                       0xf000
202 #define   UHSIC_TX_RTUNE(x)                     (((x) & 0xf) << 12)
203
204 #define UTMIP_TX_CFG0                           0x820
205 #define UHSIC_PADS_CFG1                         0x820
206 #define   UHSIC_PD_BG                           (1 << 2)
207 #define   UHSIC_PD_TX                           (1 << 3)
208 #define   UHSIC_PD_TRK                          (1 << 4)
209 #define   UHSIC_PD_RX                           (1 << 5)
210 #define   UHSIC_PD_ZI                           (1 << 6)
211 #define   UHSIC_RX_SEL                          (1 << 7)
212 #define   UHSIC_RPD_DATA                        (1 << 9)
213 #define   UHSIC_RPD_STROBE                      (1 << 10)
214 #define   UHSIC_RPU_DATA                        (1 << 11)
215 #define   UHSIC_RPU_STROBE                      (1 << 12)
216 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
217 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
218
219 #define UTMIP_MISC_CFG0         0x824
220 #define   UTMIP_DPDM_OBSERVE            (1 << 26)
221 #define   UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
222 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J   UTMIP_DPDM_OBSERVE_SEL(0xf)
223 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K   UTMIP_DPDM_OBSERVE_SEL(0xe)
224 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
225 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
226 #define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
227 #define   FORCE_PULLDN_DM       (1 << 8)
228 #define   FORCE_PULLDN_DP       (1 << 9)
229 #define   COMB_TERMS            (1 << 0)
230 #define   ALWAYS_FREE_RUNNING_TERMS (1 << 1)
231
232 #define USB1_PREFETCH_ID               6
233 #define USB2_PREFETCH_ID               18
234 #define USB3_PREFETCH_ID               17
235
236 #define UTMIP_MISC_CFG1         0x828
237 #define   UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18)
238 #define   UTMIP_PLLU_STABLE_COUNT(x)    (((x) & 0xfff) << 6)
239
240 #define UHSIC_STAT_CFG0         0x828
241 #define   UHSIC_CONNECT_DETECT          (1 << 0)
242
243 #define UTMIP_DEBOUNCE_CFG0 0x82c
244 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
245
246 #define UTMIP_BAT_CHRG_CFG0     0x830
247 #define   UTMIP_PD_CHRG                 (1 << 0)
248 #define   UTMIP_ON_SINK_EN              (1 << 2)
249 #define   UTMIP_OP_SRC_EN               (1 << 3)
250
251 #define UTMIP_SPARE_CFG0        0x834
252 #define   FUSE_SETUP_SEL                (1 << 3)
253 #define   FUSE_ATERM_SEL                (1 << 4)
254
255 #define UTMIP_XCVR_CFG1         0x838
256 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
257 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
258 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
259 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
260
261 #define UTMIP_BIAS_CFG1         0x83c
262 #define   UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
263
264 #define FUSE_USB_CALIB_0                0x1F0
265 #define FUSE_USB_CALIB_XCVR_SETUP(x)    (((x) & 0x7F) << 0)
266
267 #define APB_MISC_GP_OBSCTRL_0   0x818
268 #define APB_MISC_GP_OBSDATA_0   0x81c
269
270 /* ULPI GPIO */
271 #define ULPI_STP        TEGRA_GPIO_PY3
272 #define ULPI_DIR        TEGRA_GPIO_PY1
273 #define ULPI_D0         TEGRA_GPIO_PO1
274 #define ULPI_D1         TEGRA_GPIO_PO2
275
276 /* These values (in milli second) are taken from the battery charging spec */
277 #define TDP_SRC_ON_MS    100
278 #define TDPSRC_CON_MS    40
279
280 #ifdef DEBUG
281 #define DBG(stuff...)   pr_info("tegra2_usb_phy: " stuff)
282 #else
283 #define DBG(stuff...)   do {} while (0)
284 #endif
285
286 /* define HSIC phy params */
287 #define HSIC_SYNC_START_DELAY           9
288 #define HSIC_IDLE_WAIT_DELAY            17
289 #define HSIC_ELASTIC_UNDERRUN_LIMIT     16
290 #define HSIC_ELASTIC_OVERRUN_LIMIT      16
291
292 static DEFINE_SPINLOCK(utmip_pad_lock);
293 static int utmip_pad_count;
294 static int utmip_pad_state_on;
295
296 static struct tegra_xtal_freq utmip_freq_table[] = {
297         {
298                 .freq = 12000000,
299                 .enable_delay = 0x02,
300                 .stable_count = 0x2F,
301                 .active_delay = 0x04,
302                 .xtal_freq_count = 0x76,
303                 .debounce = 0x7530,
304                 .pdtrk_count = 5,
305         },
306         {
307                 .freq = 13000000,
308                 .enable_delay = 0x02,
309                 .stable_count = 0x33,
310                 .active_delay = 0x05,
311                 .xtal_freq_count = 0x7F,
312                 .debounce = 0x7EF4,
313                 .pdtrk_count = 5,
314         },
315         {
316                 .freq = 19200000,
317                 .enable_delay = 0x03,
318                 .stable_count = 0x4B,
319                 .active_delay = 0x06,
320                 .xtal_freq_count = 0xBB,
321                 .debounce = 0xBB80,
322                 .pdtrk_count = 7,
323         },
324         {
325                 .freq = 26000000,
326                 .enable_delay = 0x04,
327                 .stable_count = 0x66,
328                 .active_delay = 0x09,
329                 .xtal_freq_count = 0xFE,
330                 .debounce = 0xFDE8,
331                 .pdtrk_count = 9,
332         },
333 };
334
335 static struct tegra_xtal_freq uhsic_freq_table[] = {
336         {
337                 .freq = 12000000,
338                 .enable_delay = 0x02,
339                 .stable_count = 0x2F,
340                 .active_delay = 0x0,
341                 .xtal_freq_count = 0x1CA,
342         },
343         {
344                 .freq = 13000000,
345                 .enable_delay = 0x02,
346                 .stable_count = 0x33,
347                 .active_delay = 0x0,
348                 .xtal_freq_count = 0x1F0,
349         },
350         {
351                 .freq = 19200000,
352                 .enable_delay = 0x03,
353                 .stable_count = 0x4B,
354                 .active_delay = 0x0,
355                 .xtal_freq_count = 0x2DD,
356         },
357         {
358                 .freq = 26000000,
359                 .enable_delay = 0x04,
360                 .stable_count = 0x66,
361                 .active_delay = 0x0,
362                 .xtal_freq_count = 0x3E0,
363         },
364 };
365
366 static void usb_phy_fence_read(struct tegra_usb_phy *phy)
367 {
368         /* Fence read for coherency of AHB master intiated writes */
369         if (phy->inst == 0)
370                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB1_PREFETCH_ID));
371         else if (phy->inst == 1)
372                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB2_PREFETCH_ID));
373         else if (phy->inst == 2)
374                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB3_PREFETCH_ID));
375
376         return;
377 }
378
379 static int usb_phy_bringup_host_controller(struct tegra_usb_phy *phy)
380 {
381         unsigned long val;
382         void __iomem *base = phy->regs;
383
384         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
385         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d] - 0\n",
386                         readl(base + USB_USBSTS), readl(base + USB_PORTSC),
387                                                         phy->port_speed);
388
389         /* enable host mode */
390         val = readl(base + USB_USBMODE_REG_OFFSET);
391         val |= USB_USBMODE_HOST;
392         writel(val, base + USB_USBMODE_REG_OFFSET);
393
394         /* Enable Port Power */
395         val = readl(base + USB_PORTSC);
396         val |= USB_PORTSC_PP;
397         writel(val, base + USB_PORTSC);
398         udelay(10);
399
400         /* Check if the phy resume from LP0. When the phy resume from LP0
401          * USB register will be reset.to zero */
402         if (!readl(base + USB_ASYNCLISTADDR)) {
403                 val = readl(base + USB_USBCMD);
404                 val |= USB_USBCMD_RS;
405                 writel(val, base + USB_USBCMD);
406
407                 /* Program the field PTC based on the saved speed mode */
408                 val = readl(base + USB_PORTSC);
409                 val &= ~(USB_PORTSC_PTC(~0));
410                 if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH)
411                         val |= USB_PORTSC_PTC(5);
412                 else if (phy->port_speed == USB_PHY_PORT_SPEED_FULL)
413                         val |= USB_PORTSC_PTC(6);
414                 else if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
415                         val |= USB_PORTSC_PTC(7);
416                 writel(val, base + USB_PORTSC);
417                 udelay(10);
418
419                 /* Disable test mode by setting PTC field to NORMAL_OP */
420                 val = readl(base + USB_PORTSC);
421                 val &= ~(USB_PORTSC_PTC(~0));
422                 writel(val, base + USB_PORTSC);
423                 udelay(10);
424         }
425
426         /* Poll until CCS is enabled */
427         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
428                                                  USB_PORTSC_CCS, 2000)) {
429                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
430         }
431
432         /* Poll until PE is enabled */
433         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_PE,
434                                                  USB_PORTSC_PE, 2000)) {
435                 pr_err("%s: timeout waiting for USB_PORTSC_PE\n", __func__);
436         }
437
438         /* Clear the PCI status, to avoid an interrupt taken upon resume */
439         val = readl(base + USB_USBSTS);
440         val |= USB_USBSTS_PCI;
441         writel(val, base + USB_USBSTS);
442
443         /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
444         val = readl(base + USB_PORTSC);
445         if ((val & USB_PORTSC_PP) && (val & USB_PORTSC_PE)) {
446                 val |= USB_PORTSC_SUSP;
447                 writel(val, base + USB_PORTSC);
448                 /* Need a 4ms delay before the controller goes to suspend */
449                 mdelay(4);
450
451                 /* Wait until port suspend completes */
452                 if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_SUSP,
453                                                  USB_PORTSC_SUSP, 1000)) {
454                         pr_err("%s: timeout waiting for PORT_SUSPEND\n",
455                                                                 __func__);
456                 }
457         }
458
459         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
460                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
461
462         return 0;
463 }
464
465 static void usb_phy_wait_for_sof(struct tegra_usb_phy *phy)
466 {
467         unsigned long val;
468         void __iomem *base = phy->regs;
469
470         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
471         val = readl(base + USB_USBSTS);
472         writel(val, base + USB_USBSTS);
473         udelay(20);
474         /* wait for two SOFs */
475         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
476                 USB_USBSTS_SRI, 2500))
477                 pr_err("%s: timeout waiting for SOF\n", __func__);
478
479         val = readl(base + USB_USBSTS);
480         writel(val, base + USB_USBSTS);
481         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI, 0, 2500))
482                 pr_err("%s: timeout waiting for SOF\n", __func__);
483
484         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
485                         USB_USBSTS_SRI, 2500))
486                 pr_err("%s: timeout waiting for SOF\n", __func__);
487
488         udelay(20);
489 }
490
491 static unsigned int utmi_phy_xcvr_setup_value(struct tegra_usb_phy *phy)
492 {
493         struct tegra_utmi_config *cfg = &phy->pdata->u_cfg.utmi;
494         signed long val;
495
496         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
497         if (cfg->xcvr_use_fuses) {
498                 val = FUSE_USB_CALIB_XCVR_SETUP(
499                                 tegra_fuse_readl(FUSE_USB_CALIB_0));
500                 if (cfg->xcvr_setup_offset <= UTMIP_XCVR_MAX_OFFSET)
501                         val = val + cfg->xcvr_setup_offset;
502
503                 if (val > UTMIP_XCVR_SETUP_MAX_VALUE) {
504                         val = UTMIP_XCVR_SETUP_MAX_VALUE;
505                         pr_info("%s: reset XCVR_SETUP to max value\n",
506                                  __func__);
507                 } else if (val < UTMIP_XCVR_SETUP_MIN_VALUE) {
508                         val = UTMIP_XCVR_SETUP_MIN_VALUE;
509                         pr_info("%s: reset XCVR_SETUP to min value\n",
510                                  __func__);
511                 }
512         } else {
513                 val = cfg->xcvr_setup;
514         }
515
516         return (unsigned int) val;
517 }
518
519
520 static int utmi_phy_open(struct tegra_usb_phy *phy)
521 {
522         unsigned long parent_rate;
523         int i;
524
525         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
526         phy->utmi_pad_clk = clk_get_sys("utmip-pad", NULL);
527         if (IS_ERR(phy->utmi_pad_clk)) {
528                 pr_err("%s: can't get utmip pad clock\n", __func__);
529                 return PTR_ERR(phy->utmi_pad_clk);
530         }
531
532         phy->utmi_xcvr_setup = utmi_phy_xcvr_setup_value(phy);
533
534         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
535         for (i = 0; i < ARRAY_SIZE(utmip_freq_table); i++) {
536                 if (utmip_freq_table[i].freq == parent_rate) {
537                         phy->freq = &utmip_freq_table[i];
538                         break;
539                 }
540         }
541         if (!phy->freq) {
542                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
543                 return -EINVAL;
544         }
545
546         return 0;
547 }
548
549 static void utmi_phy_close(struct tegra_usb_phy *phy)
550 {
551         DBG("%s inst:[%d]\n", __func__, phy->inst);
552
553         clk_put(phy->utmi_pad_clk);
554 }
555
556 static int utmi_phy_pad_power_on(struct tegra_usb_phy *phy)
557 {
558         unsigned long val, flags;
559         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
560
561         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
562         clk_enable(phy->utmi_pad_clk);
563
564         spin_lock_irqsave(&utmip_pad_lock, flags);
565
566         utmip_pad_count++;
567         val = readl(pad_base + UTMIP_BIAS_CFG0);
568         val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
569         writel(val, pad_base + UTMIP_BIAS_CFG0);
570         utmip_pad_state_on = true;
571
572         spin_unlock_irqrestore(&utmip_pad_lock, flags);
573
574         clk_disable(phy->utmi_pad_clk);
575
576         return 0;
577 }
578
579 static int utmi_phy_pad_power_off(struct tegra_usb_phy *phy)
580 {
581         unsigned long val, flags;
582         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
583
584         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
585         clk_enable(phy->utmi_pad_clk);
586         spin_lock_irqsave(&utmip_pad_lock, flags);
587
588         if (!utmip_pad_count) {
589                 pr_err("%s: utmip pad already powered off\n", __func__);
590                 goto out;
591         }
592         if (--utmip_pad_count == 0) {
593                 val = readl(pad_base + UTMIP_BIAS_CFG0);
594                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
595                 writel(val, pad_base + UTMIP_BIAS_CFG0);
596                 utmip_pad_state_on = false;
597         }
598 out:
599         spin_unlock_irqrestore(&utmip_pad_lock, flags);
600         clk_disable(phy->utmi_pad_clk);
601
602         return 0;
603 }
604
605 static int utmi_phy_irq(struct tegra_usb_phy *phy)
606 {
607         void __iomem *base = phy->regs;
608         unsigned long val = 0;
609
610         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
611
612         usb_phy_fence_read(phy);
613         if (phy->pdata->u_data.host.hot_plug) {
614                 val = readl(base + USB_SUSP_CTRL);
615                 if ((val  & USB_PHY_CLK_VALID_INT_STS)) {
616                         val &= ~USB_PHY_CLK_VALID_INT_ENB |
617                                         USB_PHY_CLK_VALID_INT_STS;
618                         writel(val , (base + USB_SUSP_CTRL));
619                         pr_info("%s: usb device plugged-in\n", __func__);
620                         val = readl(base + USB_USBSTS);
621                         if (!(val  & USB_USBSTS_PCI))
622                                 return IRQ_NONE;
623                         val = readl(base + USB_PORTSC);
624                         val &= ~(USB_PORTSC_WKCN | USB_PORTSC_RWC_BITS);
625                         writel(val , (base + USB_PORTSC));
626                 } else if (!phy->phy_clk_on) {
627                         return IRQ_NONE;
628                 }
629         }
630
631         return IRQ_HANDLED;
632 }
633
634 static int phy_post_suspend(struct tegra_usb_phy *phy)
635 {
636
637         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
638         /* Need a 4ms delay for controller to suspend */
639         mdelay(4);
640         return 0;
641 }
642
643 static int utmi_phy_post_resume(struct tegra_usb_phy *phy)
644 {
645         unsigned long val;
646         void __iomem *base = phy->regs;
647
648         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
649
650         val = readl(base + UTMIP_TX_CFG0);
651         val &= ~UTMIP_HS_DISCON_DISABLE;
652         writel(val, base + UTMIP_TX_CFG0);
653         return 0;
654 }
655
656 static int utmi_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
657 {
658         unsigned long val;
659         void __iomem *base = phy->regs;
660
661         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
662         val = readl(base + UTMIP_TX_CFG0);
663         val |= UTMIP_HS_DISCON_DISABLE;
664         writel(val, base + UTMIP_TX_CFG0);
665
666         usb_phy_wait_for_sof(phy);
667
668         return 0;
669 }
670
671 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
672 {
673         unsigned long val;
674         void __iomem *base = phy->regs;
675
676         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
677         if (!phy->phy_clk_on) {
678                 DBG("%s(%d) inst:[%d] phy clk is already off\n",
679                                         __func__, __LINE__, phy->inst);
680                 return 0;
681         }
682
683         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
684                 val = readl(base + USB_SUSP_CTRL);
685                 val &= ~(USB_WAKEUP_DEBOUNCE_COUNT(~0));
686                 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
687                 writel(val, base + USB_SUSP_CTRL);
688
689                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
690                 val |= UTMIP_PD_CHRG;
691                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
692         }
693
694         if (!phy->pdata->u_data.host.hot_plug) {
695                 val = readl(base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
696                 val |= (UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
697                          UTMIP_FORCE_PDZI_POWERDOWN);
698                 writel(val, base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
699         }
700
701         val = readl(base + UTMIP_XCVR_CFG1);
702         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
703                    UTMIP_FORCE_PDDR_POWERDOWN;
704         writel(val, base + UTMIP_XCVR_CFG1);
705
706         if (phy->inst != 0) {
707                 val = readl(base + UTMIP_BIAS_CFG0);
708                 val |= UTMIP_OTGPD;
709                 writel(val, base + UTMIP_BIAS_CFG0);
710         }
711
712         phy->port_speed = (readl(base + USB_PORTSC) >> 26) &
713                         USB_PORTSC_PSPD_MASK;
714
715         if (phy->pdata->u_data.host.hot_plug) {
716                 bool enable_hotplug = true;
717                 /* if it is OTG port then make sure to enable hot-plug feature
718                    only if host adaptor is connected, i.e id is low */
719                 if (phy->pdata->port_otg) {
720                         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
721                         enable_hotplug = (val & USB_ID_STATUS) ? false : true;
722                 }
723                 if (enable_hotplug) {
724                         val = readl(base + USB_PORTSC);
725                         val |= USB_PORTSC_WKCN;
726                         writel(val, base + USB_PORTSC);
727
728                         val = readl(base + USB_SUSP_CTRL);
729                         val |= USB_PHY_CLK_VALID_INT_ENB;
730                         writel(val, base + USB_SUSP_CTRL);
731                 } else {
732                         /* Disable PHY clock valid interrupts
733                                 while going into suspend*/
734                         val = readl(base + USB_SUSP_CTRL);
735                         val &= ~USB_PHY_CLK_VALID_INT_ENB;
736                         writel(val, base + USB_SUSP_CTRL);
737                 }
738         }
739
740         if (phy->inst == 2) {
741                 val = readl(base + USB_PORTSC);
742                 val |= USB_PORTSC_PHCD;
743                 writel(val, base + USB_PORTSC);
744         } else {
745                 val = readl(base + USB_SUSP_CTRL);
746                 val |= USB_SUSP_SET;
747                 writel(val, base + USB_SUSP_CTRL);
748                 udelay(10);
749                 val = readl(base + USB_SUSP_CTRL);
750                 val &= ~USB_SUSP_SET;
751                 writel(val, base + USB_SUSP_CTRL);
752         }
753
754         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
755                                                                 0, 2500))
756                 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
757
758         utmi_phy_pad_power_off(phy);
759
760         phy->phy_clk_on = false;
761         phy->hw_accessible = false;
762
763         DBG("%s(%d) inst:[%d]END\n", __func__, __LINE__, phy->inst);
764
765         return 0;
766 }
767
768 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
769 {
770         unsigned long val;
771         void __iomem *base = phy->regs;
772         struct tegra_utmi_config *config = &phy->pdata->u_cfg.utmi;
773         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
774         if (phy->phy_clk_on) {
775                 DBG("%s(%d) inst:[%d] phy clk is already on\n",
776                                         __func__, __LINE__, phy->inst);
777                 return 0;
778         }
779
780         val = readl(base + USB_SUSP_CTRL);
781         val |= UTMIP_RESET;
782         writel(val, base + USB_SUSP_CTRL);
783
784         val = readl(base + UTMIP_TX_CFG0);
785         val |= UTMIP_FS_PREABMLE_J;
786         writel(val, base + UTMIP_TX_CFG0);
787
788         val = readl(base + UTMIP_HSRX_CFG0);
789         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
790         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
791         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
792         writel(val, base + UTMIP_HSRX_CFG0);
793
794         val = readl(base + UTMIP_HSRX_CFG1);
795         val &= ~(UTMIP_HS_SYNC_START_DLY(~0));
796         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
797         writel(val, base + UTMIP_HSRX_CFG1);
798
799         val = readl(base + UTMIP_DEBOUNCE_CFG0);
800         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
801         val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
802         writel(val, base + UTMIP_DEBOUNCE_CFG0);
803
804         val = readl(base + UTMIP_MISC_CFG0);
805         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
806         writel(val, base + UTMIP_MISC_CFG0);
807
808         val = readl(base + UTMIP_MISC_CFG1);
809         val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) | UTMIP_PLLU_STABLE_COUNT(~0));
810         val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |
811                 UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count);
812         writel(val, base + UTMIP_MISC_CFG1);
813
814         val = readl(base + UTMIP_PLL_CFG1);
815         val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) | UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
816         val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |
817                 UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
818         writel(val, base + UTMIP_PLL_CFG1);
819
820         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
821                 val = readl(base + USB_SUSP_CTRL);
822                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
823                 writel(val, base + USB_SUSP_CTRL);
824
825                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
826                 val &= ~UTMIP_PD_CHRG;
827                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
828         } else {
829                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
830                 val |= UTMIP_PD_CHRG;
831                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
832         }
833
834         utmi_phy_pad_power_on(phy);
835
836         val = readl(base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
837         val &= ~(UTMIP_XCVR_LSBIAS_SEL | UTMIP_FORCE_PD_POWERDOWN |
838                  UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN |
839                  UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_LSFSLEW(~0) |
840                  UTMIP_XCVR_LSRSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
841         val |= UTMIP_XCVR_SETUP(phy->utmi_xcvr_setup);
842         val |= UTMIP_XCVR_SETUP_MSB(XCVR_SETUP_MSB_CALIB(phy->utmi_xcvr_setup));
843         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
844         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
845
846         writel(val, base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
847
848         val = readl(base + UTMIP_XCVR_CFG1);
849         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
850                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
851         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
852         writel(val, base + UTMIP_XCVR_CFG1);
853
854
855         val = readl(base + UTMIP_BIAS_CFG1);
856         val &= ~(UTMIP_BIAS_PDTRK_COUNT(~0));
857         val |= UTMIP_BIAS_PDTRK_COUNT(phy->freq->pdtrk_count);
858         writel(val, base + UTMIP_BIAS_CFG1);
859
860         val = readl(base + UTMIP_SPARE_CFG0);
861         val &= ~FUSE_SETUP_SEL;
862         writel(val, base + UTMIP_SPARE_CFG0);
863
864         val = readl(base + USB_SUSP_CTRL);
865         val |= UTMIP_PHY_ENABLE;
866         writel(val, base + USB_SUSP_CTRL);
867
868         val = readl(base + USB_SUSP_CTRL);
869         val &= ~UTMIP_RESET;
870         writel(val, base + USB_SUSP_CTRL);
871
872         if (phy->inst == 0) {
873                 val = readl(base + USB_SUSP_CTRL);
874                 val &= ~USB_SUSP_SET;
875                 writel(val, base + USB_SUSP_CTRL);
876         } else {
877                 val = readl(base + USB_PORTSC);
878                 val &= ~USB_PORTSC_PHCD;
879                 writel(val, base + USB_PORTSC);
880         }
881
882         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
883                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500))
884                 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
885
886         if (phy->inst == 2) {
887                 val = readl(base + USB_PORTSC);
888                 val &= ~(USB_PORTSC_PTS(~0));
889                 writel(val, base + USB_PORTSC);
890         }
891
892         phy->phy_clk_on = true;
893         phy->hw_accessible = true;
894
895         return 0;
896 }
897
898 static void utmi_phy_restore_start(struct tegra_usb_phy *phy)
899 {
900         unsigned long val;
901         void __iomem *base = phy->regs;
902
903         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
904         val = readl(base + UTMIP_MISC_CFG0);
905         val &= ~(UTMIP_DPDM_OBSERVE_SEL(~0));
906
907         if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
908                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
909         else
910                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
911         writel(val, base + UTMIP_MISC_CFG0);
912         udelay(1);
913
914         val = readl(base + UTMIP_MISC_CFG0);
915         val |= UTMIP_DPDM_OBSERVE;
916         writel(val, base + UTMIP_MISC_CFG0);
917         udelay(10);
918 }
919
920 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
921 {
922         unsigned long val;
923         void __iomem *base = phy->regs;
924
925         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
926         val = readl(base + UTMIP_MISC_CFG0);
927         val &= ~UTMIP_DPDM_OBSERVE;
928         writel(val, base + UTMIP_MISC_CFG0);
929         udelay(10);
930 }
931
932
933 static int utmi_phy_resume(struct tegra_usb_phy *phy)
934 {
935         int status = 0;
936         unsigned long val, flags;
937         void __iomem *base = phy->regs;
938         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
939
940         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
941         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) {
942                 if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
943                         utmi_phy_restore_start(phy);
944                         usb_phy_bringup_host_controller(phy);
945                         utmi_phy_restore_end(phy);
946                 } else {
947                         /* device is plugged in when system is in LP0 */
948                         /* bring up the controller from LP0*/
949                         val = readl(base + USB_USBCMD);
950                         val |= USB_USBCMD_RESET;
951                         writel(val, base + USB_USBCMD);
952
953                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
954                                 USB_USBCMD_RESET, 0, 2500) < 0) {
955                                 pr_err("%s: timeout waiting for reset\n",
956                                         __func__);
957                         }
958
959                         val = readl(base + USB_USBMODE_REG_OFFSET);
960                         val &= ~USB_USBMODE_MASK;
961                         val |= USB_USBMODE_HOST;
962                         writel(val, base + USB_USBMODE_REG_OFFSET);
963
964                         if (phy->inst == 2) {
965                                 val = readl(base + USB_PORTSC);
966                                 val &= ~USB_PORTSC_PTS(~0);
967                                 writel(val, base + USB_PORTSC);
968                         }
969                         writel(USB_USBCMD_RS, base + USB_USBCMD);
970
971                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
972                                 USB_USBCMD_RS, USB_USBCMD_RS, 2500) < 0) {
973                                 pr_err("%s: timeout waiting for run bit\n",
974                                         __func__);
975                         }
976
977                         /* Enable Port Power */
978                         val = readl(base + USB_PORTSC);
979                         val |= USB_PORTSC_PP;
980                         writel(val, base + USB_PORTSC);
981                         udelay(10);
982
983                         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
984                                 readl(base + USB_USBSTS),
985                                 readl(base + USB_PORTSC));
986                 }
987         } else {
988                 /* Restoring the pad powers */
989                 clk_enable(phy->utmi_pad_clk);
990
991                 spin_lock_irqsave(&utmip_pad_lock, flags);
992
993                 val = readl(pad_base + UTMIP_BIAS_CFG0);
994                 if (utmip_pad_state_on)
995                         val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
996                 else
997                         val |= (UTMIP_OTGPD | UTMIP_BIASPD);
998                 writel(val, pad_base + UTMIP_BIAS_CFG0);
999
1000                 spin_unlock_irqrestore(&utmip_pad_lock, flags);
1001                 clk_disable(phy->utmi_pad_clk);
1002         }
1003
1004         return status;
1005 }
1006
1007 static bool utmi_phy_charger_detect(struct tegra_usb_phy *phy)
1008 {
1009         unsigned long val;
1010         void __iomem *base = phy->regs;
1011         bool status;
1012
1013         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1014         /* Enable charger detection logic */
1015         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1016         val |= UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN;
1017         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1018
1019         /* Source should be on for 100 ms as per USB charging spec */
1020         msleep(TDP_SRC_ON_MS);
1021
1022         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1023         /* If charger is not connected disable the interrupt */
1024         val &= ~VDAT_DET_INT_EN;
1025         val |= VDAT_DET_CHG_DET;
1026         writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
1027
1028         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1029         if (val & VDAT_DET_STS)
1030                 status = true;
1031         else
1032                 status = false;
1033
1034         /* Disable charger detection logic */
1035         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1036         val &= ~(UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN);
1037         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1038
1039         /* Delay of 40 ms before we pull the D+ as per battery charger spec */
1040         msleep(TDPSRC_CON_MS);
1041
1042         return status;
1043 }
1044
1045
1046 static int uhsic_phy_open(struct tegra_usb_phy *phy)
1047 {
1048         unsigned long parent_rate;
1049         int i;
1050
1051         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1052         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
1053         for (i = 0; i < ARRAY_SIZE(uhsic_freq_table); i++) {
1054                 if (uhsic_freq_table[i].freq == parent_rate) {
1055                         phy->freq = &uhsic_freq_table[i];
1056                         break;
1057                 }
1058         }
1059         if (!phy->freq) {
1060                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
1061                 return -EINVAL;
1062         }
1063
1064         return 0;
1065 }
1066
1067 static int uhsic_phy_irq(struct tegra_usb_phy *phy)
1068 {
1069         usb_phy_fence_read(phy);
1070         return IRQ_HANDLED;
1071 }
1072
1073 static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
1074 {
1075         unsigned long val;
1076         void __iomem *base = phy->regs;
1077
1078         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1079         if (phy->phy_clk_on) {
1080                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
1081                                                         __LINE__, phy->inst);
1082                 return 0;
1083         }
1084
1085         val = readl(base + UHSIC_PADS_CFG1);
1086         val &= ~(UHSIC_PD_BG | UHSIC_PD_TX | UHSIC_PD_TRK | UHSIC_PD_RX |
1087                         UHSIC_PD_ZI | UHSIC_RPD_DATA | UHSIC_RPD_STROBE);
1088         val |= UHSIC_RX_SEL;
1089         writel(val, base + UHSIC_PADS_CFG1);
1090         udelay(2);
1091
1092         val = readl(base + USB_SUSP_CTRL);
1093         val |= UHSIC_RESET;
1094         writel(val, base + USB_SUSP_CTRL);
1095         udelay(30);
1096
1097         val = readl(base + USB_SUSP_CTRL);
1098         val |= UHSIC_PHY_ENABLE;
1099         writel(val, base + USB_SUSP_CTRL);
1100
1101         val = readl(base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
1102         val |= UHSIC_IDLE_WAIT(HSIC_IDLE_WAIT_DELAY);
1103         val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(HSIC_ELASTIC_UNDERRUN_LIMIT);
1104         val |= UHSIC_ELASTIC_OVERRUN_LIMIT(HSIC_ELASTIC_OVERRUN_LIMIT);
1105         writel(val, base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
1106
1107         val = readl(base + UHSIC_HSRX_CFG1);
1108         val |= UHSIC_HS_SYNC_START_DLY(HSIC_SYNC_START_DELAY);
1109         writel(val, base + UHSIC_HSRX_CFG1);
1110
1111         val = readl(base + UHSIC_MISC_CFG0);
1112         val |= UHSIC_SUSPEND_EXIT_ON_EDGE;
1113         writel(val, base + UHSIC_MISC_CFG0);
1114
1115         val = readl(base + UHSIC_MISC_CFG1);
1116         val |= UHSIC_PLLU_STABLE_COUNT(phy->freq->stable_count);
1117         writel(val, base + UHSIC_MISC_CFG1);
1118
1119         val = readl(base + UHSIC_PLL_CFG1);
1120         val |= UHSIC_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
1121         val |= UHSIC_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count);
1122         writel(val, base + UHSIC_PLL_CFG1);
1123
1124         val = readl(base + USB_SUSP_CTRL);
1125         val &= ~(UHSIC_RESET);
1126         writel(val, base + USB_SUSP_CTRL);
1127         udelay(2);
1128
1129         val = readl(base + USB_PORTSC);
1130         val &= ~(USB_PORTSC_PTS(~0));
1131         writel(val, base + USB_PORTSC);
1132
1133         val = readl(base + USB_TXFILLTUNING);
1134         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
1135                 val = USB_FIFO_TXFILL_THRES(0x10);
1136                 writel(val, base + USB_TXFILLTUNING);
1137         }
1138
1139         val = readl(base + USB_PORTSC);
1140         val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN);
1141         writel(val, base + USB_PORTSC);
1142
1143         val = readl(base + UHSIC_PADS_CFG0);
1144         val &= ~(UHSIC_TX_RTUNEN);
1145         /* set Rtune impedance to 40 ohm */
1146         val |= UHSIC_TX_RTUNE(0);
1147         writel(val, base + UHSIC_PADS_CFG0);
1148
1149         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
1150                                                 USB_PHY_CLK_VALID, 2500)) {
1151                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
1152                 return -ETIMEDOUT;
1153         }
1154
1155         phy->phy_clk_on = true;
1156         phy->hw_accessible = true;
1157
1158         return 0;
1159 }
1160
1161 static int uhsic_phy_power_off(struct tegra_usb_phy *phy)
1162 {
1163         unsigned long val;
1164         void __iomem *base = phy->regs;
1165
1166         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1167         if (!phy->phy_clk_on) {
1168                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
1169                                                         __LINE__, phy->inst);
1170                 return 0;
1171         }
1172
1173         val = readl(base + UHSIC_PADS_CFG1);
1174         val &= ~UHSIC_RPU_STROBE;
1175         val |= UHSIC_RPD_STROBE;
1176         writel(val, base + UHSIC_PADS_CFG1);
1177
1178         val = readl(base + USB_SUSP_CTRL);
1179         val |= UHSIC_RESET;
1180         writel(val, base + USB_SUSP_CTRL);
1181         udelay(30);
1182
1183         val = readl(base + USB_SUSP_CTRL);
1184         val &= ~UHSIC_PHY_ENABLE;
1185         writel(val, base + USB_SUSP_CTRL);
1186
1187         phy->phy_clk_on = false;
1188         phy->hw_accessible = false;
1189
1190         return 0;
1191 }
1192
1193 static int uhsic_phy_bus_port_power(struct tegra_usb_phy *phy)
1194 {
1195         unsigned long val;
1196         void __iomem *base = phy->regs;
1197
1198         val = readl(base + UHSIC_MISC_CFG0);
1199         val |= UHSIC_DETECT_SHORT_CONNECT;
1200         writel(val, base + UHSIC_MISC_CFG0);
1201         udelay(1);
1202
1203         val = readl(base + UHSIC_MISC_CFG0);
1204         val |= UHSIC_FORCE_XCVR_MODE;
1205         writel(val, base + UHSIC_MISC_CFG0);
1206
1207         val = readl(base + UHSIC_PADS_CFG1);
1208         val &= ~UHSIC_RPD_STROBE;
1209         val |= UHSIC_RPU_STROBE;
1210         writel(val, base + UHSIC_PADS_CFG1);
1211
1212         val = readl(base + USB_USBCMD);
1213         val &= ~USB_USBCMD_RS;
1214         writel(val, base + USB_USBCMD);
1215
1216         if (phy->pdata->ops && phy->pdata->ops->port_power)
1217                 phy->pdata->ops->port_power();
1218
1219         if (usb_phy_reg_status_wait(base + UHSIC_STAT_CFG0,
1220                         UHSIC_CONNECT_DETECT, UHSIC_CONNECT_DETECT, 2000)) {
1221                 pr_err("%s: timeout waiting for UHSIC_CONNECT_DETECT\n",
1222                                                                 __func__);
1223                 return -ETIMEDOUT;
1224         }
1225
1226 /* FIXME : need to check whether this piece is required or not
1227         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_LS(2),
1228                                                 USB_PORTSC_LS(2), 2000)) {
1229                 pr_err("%s: timeout waiting for dplus state\n", __func__);
1230                 return -ETIMEDOUT;
1231         }
1232 */
1233         return 0;
1234 }
1235
1236
1237 static int uhsic_phy_bus_reset(struct tegra_usb_phy *phy)
1238 {
1239         unsigned long val;
1240         void __iomem *base = phy->regs;
1241
1242         val = readl(base + USB_PORTSC);
1243         val |= USB_PORTSC_PTC(5);
1244         writel(val, base + USB_PORTSC);
1245         udelay(2);
1246
1247         val = readl(base + USB_PORTSC);
1248         val &= ~(USB_PORTSC_PTC(~0));
1249         writel(val, base + USB_PORTSC);
1250         udelay(2);
1251
1252         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_LS(0),
1253                                                  0, 2000)) {
1254                 pr_err("%s: timeout waiting for USB_PORTSC_LS\n", __func__);
1255                 return -ETIMEDOUT;
1256         }
1257
1258         /* Poll until CCS is enabled */
1259         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
1260                                                  USB_PORTSC_CCS, 2000)) {
1261                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
1262                 return -ETIMEDOUT;
1263         }
1264
1265         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_PSPD(2),
1266                                                  USB_PORTSC_PSPD(2), 2000)) {
1267                 pr_err("%s: timeout waiting for USB_PORTSC_PSPD\n", __func__);
1268                 return -ETIMEDOUT;
1269         }
1270
1271         val = readl(base + USB_USBCMD);
1272         val &= ~USB_USBCMD_RS;
1273         writel(val, base + USB_USBCMD);
1274
1275         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
1276                                                  USB_USBSTS_HCH, 2000)) {
1277                 pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
1278                 return -ETIMEDOUT;
1279         }
1280
1281         val = readl(base + UHSIC_PADS_CFG1);
1282         val &= ~UHSIC_RPU_STROBE;
1283         val |= UHSIC_RPD_STROBE;
1284         writel(val, base + UHSIC_PADS_CFG1);
1285
1286         mdelay(50);
1287
1288         val = readl(base + UHSIC_PADS_CFG1);
1289         val &= ~UHSIC_RPD_STROBE;
1290         val |= UHSIC_RPU_STROBE;
1291         writel(val, base + UHSIC_PADS_CFG1);
1292
1293         val = readl(base + USB_USBCMD);
1294         val |= USB_USBCMD_RS;
1295         writel(val, base + USB_USBCMD);
1296
1297         val = readl(base + UHSIC_PADS_CFG1);
1298         val &= ~UHSIC_RPU_STROBE;
1299         writel(val, base + UHSIC_PADS_CFG1);
1300
1301         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
1302                                                  USB_USBCMD_RS, 2000)) {
1303                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
1304                 return -ETIMEDOUT;
1305         }
1306
1307         return 0;
1308 }
1309
1310
1311 static int uhsic_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1312 {
1313         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1314         usb_phy_wait_for_sof(phy);
1315
1316         return 0;
1317 }
1318
1319 static int uhsic_phy_resume(struct tegra_usb_phy *phy)
1320 {
1321         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1322         uhsic_phy_bus_port_power(phy);
1323
1324         return 0;
1325 }
1326
1327
1328 static int uhsic_phy_post_resume(struct tegra_usb_phy *phy)
1329 {
1330         unsigned long val;
1331         void __iomem *base = phy->regs;
1332
1333         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1334         val = readl(base + USB_TXFILLTUNING);
1335         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
1336                 val = USB_FIFO_TXFILL_THRES(0x10);
1337                 writel(val, base + USB_TXFILLTUNING);
1338         }
1339
1340         return 0;
1341 }
1342
1343 static void ulpi_set_trimmer(struct tegra_usb_phy *phy)
1344 {
1345         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
1346         void __iomem *base = phy->regs;
1347         unsigned long val;
1348
1349         val = ULPI_DATA_TRIMMER_SEL(config->data_trimmer);
1350         val |= ULPI_STPDIRNXT_TRIMMER_SEL(config->stpdirnxt_trimmer);
1351         val |= ULPI_DIR_TRIMMER_SEL(config->dir_trimmer);
1352         writel(val, base + ULPI_TIMING_CTRL_1);
1353         udelay(10);
1354
1355         val |= ULPI_DATA_TRIMMER_LOAD;
1356         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
1357         val |= ULPI_DIR_TRIMMER_LOAD;
1358         writel(val, base + ULPI_TIMING_CTRL_1);
1359 }
1360
1361
1362 static int ulpi_link_phy_open(struct tegra_usb_phy *phy)
1363 {
1364         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
1365         int err = 0;
1366
1367         phy->ulpi_clk = NULL;
1368
1369         if (config->clk) {
1370                 phy->ulpi_clk = clk_get_sys(NULL, config->clk);
1371                 if (IS_ERR(phy->ulpi_clk)) {
1372                         pr_err("%s: can't get ulpi clock\n", __func__);
1373                         err = -ENXIO;
1374                 }
1375         }
1376
1377         phy->ulpi_vp = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
1378         phy->ulpi_vp->io_priv = phy->regs + ULPI_VIEWPORT;
1379         phy->linkphy_init = true;
1380         return err;
1381 }
1382
1383 static void ulpi_link_phy_close(struct tegra_usb_phy *phy)
1384 {
1385         DBG("%s inst:[%d]\n", __func__, phy->inst);
1386         if (phy->ulpi_clk)
1387                 clk_put(phy->ulpi_clk);
1388 }
1389
1390 static int ulpi_link_phy_irq(struct tegra_usb_phy *phy)
1391 {
1392         usb_phy_fence_read(phy);
1393         return IRQ_HANDLED;
1394 }
1395
1396 static int ulpi_link_phy_power_off(struct tegra_usb_phy *phy)
1397 {
1398         unsigned long val;
1399         void __iomem *base = phy->regs;
1400         int ret;
1401
1402         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1403         if (!phy->phy_clk_on) {
1404                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
1405                                                         __LINE__, phy->inst);
1406                 return 0;
1407         }
1408
1409         /* Disable VbusValid, SessEnd comparators */
1410         ret = usb_phy_io_write(phy->ulpi_vp, 0x00, 0x0D);
1411         if (ret)
1412                 pr_err("%s: ulpi write 0x0D failed\n", __func__);
1413
1414         ret = usb_phy_io_write(phy->ulpi_vp, 0x00, 0x10);
1415         if (ret)
1416                 pr_err("%s: ulpi write 0x10 failed\n", __func__);
1417
1418         /* Disable IdFloat comparator */
1419         ret = usb_phy_io_write(phy->ulpi_vp, 0x00, 0x19);
1420         if (ret)
1421                 pr_err("%s: ulpi write 0x19 failed\n", __func__);
1422
1423         ret = usb_phy_io_write(phy->ulpi_vp, 0x00, 0x1D);
1424         if (ret)
1425                 pr_err("%s: ulpi write 0x1D failed\n", __func__);
1426
1427         phy->port_speed = (readl(base + USB_PORTSC) >> 26) &
1428                         USB_PORTSC_PSPD_MASK;
1429
1430         /* Clear WKCN/WKDS/WKOC wake-on events that can cause the USB
1431          * Controller to immediately bring the ULPI PHY out of low power
1432          */
1433         val = readl(base + USB_PORTSC);
1434         val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN);
1435         writel(val, base + USB_PORTSC);
1436
1437         /* Put the PHY in the low power mode */
1438         val = readl(base + USB_PORTSC);
1439         val |= USB_PORTSC_PHCD;
1440         writel(val, base + USB_PORTSC);
1441
1442         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
1443                                                          0, 2500)) {
1444                 pr_err("%s: timeout waiting for phy to stop\n", __func__);
1445         }
1446
1447         if (phy->ulpi_clk)
1448                 clk_disable(phy->ulpi_clk);
1449
1450         phy->phy_clk_on = false;
1451         phy->hw_accessible = false;
1452
1453         return 0;
1454 }
1455
1456 static int ulpi_link_phy_power_on(struct tegra_usb_phy *phy)
1457 {
1458         int ret;
1459         unsigned long val;
1460         void __iomem *base = phy->regs;
1461
1462         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1463         if (phy->phy_clk_on) {
1464                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
1465                                                         __LINE__, phy->inst);
1466                 return 0;
1467         }
1468
1469         if (phy->ulpi_clk) {
1470                 clk_enable(phy->ulpi_clk);
1471                 mdelay(1);
1472         }
1473
1474         val = readl(base + USB_SUSP_CTRL);
1475
1476         /* Case for lp0 */
1477         if (!(val & UHSIC_RESET)) {
1478                 val |= UHSIC_RESET;
1479                 writel(val, base + USB_SUSP_CTRL);
1480
1481                 val = 0;
1482                 writel(val, base + ULPI_TIMING_CTRL_1);
1483
1484                 ulpi_set_trimmer(phy);
1485
1486                 val = readl(base + ULPI_TIMING_CTRL_0);
1487                 val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
1488                 writel(val, base + ULPI_TIMING_CTRL_0);
1489 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1490                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAA, TEGRA_TRI_NORMAL);
1491                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAB, TEGRA_TRI_NORMAL);
1492                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_UDA, TEGRA_TRI_NORMAL);
1493 #endif
1494                 val = readl(base + USB_SUSP_CTRL);
1495                 val |= ULPI_PHY_ENABLE;
1496                 writel(val, base + USB_SUSP_CTRL);
1497
1498                 if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1499                         USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500) < 0)
1500                         pr_err("%s: timeout waiting for phy" \
1501                         "to stabilize\n", __func__);
1502
1503                 val = readl(base + USB_TXFILLTUNING);
1504                 if ((val & USB_FIFO_TXFILL_MASK) !=
1505                                 USB_FIFO_TXFILL_THRES(0x10)) {
1506                         val = USB_FIFO_TXFILL_THRES(0x10);
1507                         writel(val, base + USB_TXFILLTUNING);
1508                 }
1509         } else {
1510         /* Case for auto resume*/
1511                 val = readl(base + USB_SUSP_CTRL);
1512                 val |= USB_SUSP_CLR;
1513                 writel(val, base + USB_SUSP_CTRL);
1514
1515                 if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1516                         USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500) < 0)
1517                         pr_err("%s: timeout waiting for phy" \
1518                                         "to stabilize\n", __func__);
1519
1520                 if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1521                         USB_CLKEN, USB_CLKEN, 2500) < 0)
1522                         pr_err("%s: timeout waiting for AHB clock\n", __func__);
1523
1524                 val = readl(base + USB_SUSP_CTRL);
1525                 val &= ~USB_SUSP_CLR;
1526                 writel(val, base + USB_SUSP_CTRL);
1527         }
1528         if (phy->linkphy_init) {
1529                 /* To be done only incase of coldboot*/
1530                 /* Fix VbusInvalid due to floating VBUS */
1531                 ret = usb_phy_io_write(phy->ulpi_vp, 0x40, 0x08);
1532                 if (ret) {
1533                         pr_err("%s: ulpi write failed\n", __func__);
1534                         return ret;
1535                 }
1536
1537                 ret = usb_phy_io_write(phy->ulpi_vp, 0x80, 0x0B);
1538                 if (ret) {
1539                         pr_err("%s: ulpi write failed\n", __func__);
1540                         return ret;
1541                 }
1542                 phy->linkphy_init = false;
1543         }
1544
1545         val = readl(base + USB_PORTSC);
1546         val |= USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN;
1547         writel(val, base + USB_PORTSC);
1548
1549         phy->phy_clk_on = true;
1550         phy->hw_accessible = true;
1551
1552         return 0;
1553 }
1554
1555 static inline void ulpi_link_phy_set_tristate(bool enable)
1556 {
1557 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1558         int tristate = (enable) ? TEGRA_TRI_TRISTATE : TEGRA_TRI_NORMAL;
1559
1560         tegra_pinmux_set_tristate(TEGRA_PINGROUP_CDEV2, tristate);
1561         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAA, tristate);
1562         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAB, tristate);
1563         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UDA, tristate);
1564 #endif
1565 }
1566
1567 static void ulpi_link_phy_restore_start(struct tegra_usb_phy *phy)
1568 {
1569         unsigned long val;
1570         void __iomem *base = phy->regs;
1571
1572         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1573
1574         /*Tristate ulpi interface before USB controller resume*/
1575         ulpi_link_phy_set_tristate(true);
1576
1577         val = readl(base + ULPI_TIMING_CTRL_0);
1578         val &= ~ULPI_OUTPUT_PINMUX_BYP;
1579         writel(val, base + ULPI_TIMING_CTRL_0);
1580 }
1581
1582 static void ulpi_link_phy_restore_end(struct tegra_usb_phy *phy)
1583 {
1584         unsigned long val;
1585         void __iomem *base = phy->regs;
1586         int ret;
1587
1588         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1589
1590         val = readl(base + ULPI_TIMING_CTRL_0);
1591         val |= ULPI_OUTPUT_PINMUX_BYP;
1592         writel(val, base + ULPI_TIMING_CTRL_0);
1593
1594         ulpi_link_phy_set_tristate(false);
1595
1596         udelay(10);
1597         ret = usb_phy_io_write(phy->ulpi_vp, 0x55, 0x04);
1598         if (ret) {
1599                 pr_err("%s: ulpi write failed\n", __func__);
1600                 return;
1601         }
1602 }
1603
1604 static int ulpi_link_phy_resume(struct tegra_usb_phy *phy)
1605 {
1606         int status = 0;
1607
1608         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1609         if (phy->pdata->u_data.host.power_off_on_suspend) {
1610                 status = ulpi_link_phy_power_on(phy);
1611                 if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
1612                         ulpi_link_phy_restore_start(phy);
1613                         usb_phy_bringup_host_controller(phy);
1614                         ulpi_link_phy_restore_end(phy);
1615                 }
1616         }
1617
1618         return status;
1619 }
1620
1621 static int ulpi_link_phy_pre_resume(struct tegra_usb_phy *phy,
1622                         bool remote_wakeup)
1623 {
1624         int status = 0;
1625         unsigned long val;
1626         void __iomem *base = phy->regs;
1627         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1628
1629         val = readl(base + USB_PORTSC);
1630         if (val & USB_PORTSC_RESUME) {
1631
1632                 val = readl(base + USB_USBCMD);
1633                 val &= ~USB_USBCMD_RS;
1634                 writel(val, base + USB_USBCMD);
1635
1636                 /* detect remote wakeup */
1637                 msleep(20);
1638
1639                 val = readl(base + USB_PORTSC);
1640
1641                 /* Poll until the controller clears RESUME and SUSPEND */
1642                 if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1643                         USB_PORTSC_RESUME, 0, 2500))
1644                         pr_err("%s: timeout waiting for RESUME\n", __func__);
1645                 if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1646                         USB_PORTSC_SUSP, 0, 2500))
1647                         pr_err("%s: timeout waiting for SUSPEND\n", __func__);
1648
1649                 /* Since we skip remote wakeup event,
1650                 put controller in suspend again and
1651                 resume port later */
1652                 val = readl(base + USB_PORTSC);
1653                 val |= USB_PORTSC_SUSP;
1654                 writel(val, base + USB_PORTSC);
1655                 mdelay(4);
1656                 /* Wait until port suspend completes */
1657                 if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1658                         USB_PORTSC_SUSP, USB_PORTSC_SUSP, 2500))
1659                         pr_err("%s: timeout waiting for" \
1660                                 "PORT_SUSPEND\n", __func__);
1661
1662                 /* Disable interrupts */
1663                 writel(0, base + USB_USBINTR);
1664                 /* Clear the run bit to stop SOFs - 2LS WAR */
1665                 val = readl(base + USB_USBCMD);
1666                 val &= ~USB_USBCMD_RS;
1667                 writel(val, base + USB_USBCMD);
1668                 if (usb_phy_reg_status_wait(base + USB_USBSTS,
1669                         USB_USBSTS_HCH, USB_USBSTS_HCH, 2000)) {
1670                         pr_err("%s: timeout waiting for" \
1671                                 "USB_USBSTS_HCH\n", __func__);
1672                 }
1673                 usb_phy_wait_for_sof(phy);
1674
1675                 val = readl(base + USB_USBCMD);
1676                 val |= USB_USBCMD_RS;
1677                 writel(val, base + USB_USBCMD);
1678         }
1679         return status;
1680 }
1681
1682
1683 static inline void ulpi_pinmux_bypass(struct tegra_usb_phy *phy,
1684         bool enable)
1685 {
1686         unsigned long val;
1687         void __iomem *base = phy->regs;
1688
1689         val = readl(base + ULPI_TIMING_CTRL_0);
1690
1691         if (enable)
1692                 val |= ULPI_OUTPUT_PINMUX_BYP;
1693         else
1694                 val &= ~ULPI_OUTPUT_PINMUX_BYP;
1695
1696         writel(val, base + ULPI_TIMING_CTRL_0);
1697 }
1698
1699 static inline void ulpi_null_phy_set_tristate(bool enable)
1700 {
1701 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1702         int tristate = (enable) ? TEGRA_TRI_TRISTATE : TEGRA_TRI_NORMAL;
1703
1704         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UDA, tristate);
1705         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAA, tristate);
1706         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAB, tristate);
1707 #endif
1708 }
1709
1710 static void ulpi_null_phy_obs_read(void)
1711 {
1712         static void __iomem *apb_misc;
1713         unsigned slv0_obs, s2s_obs;
1714
1715         if (!apb_misc)
1716                 apb_misc = ioremap(TEGRA_APB_MISC_BASE, TEGRA_APB_MISC_SIZE);
1717
1718         writel(0x80b10034, apb_misc + APB_MISC_GP_OBSCTRL_0);
1719         slv0_obs = readl(apb_misc + APB_MISC_GP_OBSDATA_0);
1720
1721         writel(0x80b10038, apb_misc + APB_MISC_GP_OBSCTRL_0);
1722         s2s_obs = readl(apb_misc + APB_MISC_GP_OBSDATA_0);
1723
1724         pr_debug("slv0 obs: %08x\ns2s obs: %08x\n", slv0_obs, s2s_obs);
1725 }
1726
1727 static const struct gpio ulpi_gpios[] = {
1728         {ULPI_STP, GPIOF_IN, "ULPI_STP"},
1729         {ULPI_DIR, GPIOF_OUT_INIT_LOW, "ULPI_DIR"},
1730         {ULPI_D0, GPIOF_OUT_INIT_LOW, "ULPI_D0"},
1731         {ULPI_D1, GPIOF_OUT_INIT_LOW, "ULPI_D1"},
1732 };
1733
1734 static int ulpi_null_phy_open(struct tegra_usb_phy *phy)
1735 {
1736         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
1737         int ret;
1738
1739         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1740
1741         ret = gpio_request_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
1742         if (ret)
1743                 return ret;
1744
1745         if (gpio_is_valid(config->phy_restore_gpio)) {
1746                 ret = gpio_request(config->phy_restore_gpio, "phy_restore");
1747                 if (ret)
1748                         goto err_gpio_free;
1749
1750                 gpio_direction_input(config->phy_restore_gpio);
1751         }
1752
1753         tegra_periph_reset_assert(phy->ctrlr_clk);
1754         udelay(10);
1755         tegra_periph_reset_deassert(phy->ctrlr_clk);
1756
1757         return 0;
1758
1759 err_gpio_free:
1760         gpio_free_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
1761         return ret;
1762 }
1763
1764 static void ulpi_null_phy_close(struct tegra_usb_phy *phy)
1765 {
1766         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
1767
1768         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1769
1770         if (gpio_is_valid(config->phy_restore_gpio))
1771                 gpio_free(config->phy_restore_gpio);
1772
1773         gpio_free_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
1774 }
1775
1776 static int ulpi_null_phy_power_off(struct tegra_usb_phy *phy)
1777 {
1778         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1779
1780         if (!phy->phy_clk_on) {
1781                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
1782                                                         __LINE__, phy->inst);
1783                 return 0;
1784         }
1785
1786         phy->phy_clk_on = false;
1787         phy->hw_accessible = false;
1788         ulpi_null_phy_set_tristate(true);
1789         return 0;
1790 }
1791
1792 static int ulpi_null_phy_irq(struct tegra_usb_phy *phy)
1793 {
1794         usb_phy_fence_read(phy);
1795         return IRQ_HANDLED;
1796 }
1797
1798 static int ulpi_null_phy_restore(struct tegra_usb_phy *phy)
1799 {
1800         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
1801         unsigned long timeout;
1802         int ulpi_stp = ULPI_STP;
1803
1804         if (gpio_is_valid(config->phy_restore_gpio))
1805                 ulpi_stp = config->phy_restore_gpio;
1806
1807         /* disable ULPI pinmux bypass */
1808         ulpi_pinmux_bypass(phy, false);
1809
1810         /* driving linstate by GPIO */
1811         gpio_set_value(ULPI_D0, 0);
1812         gpio_set_value(ULPI_D1, 0);
1813
1814         /* driving DIR high */
1815         gpio_set_value(ULPI_DIR, 1);
1816
1817         /* remove ULPI tristate */
1818         ulpi_null_phy_set_tristate(false);
1819
1820         /* wait for STP high */
1821         timeout = jiffies + msecs_to_jiffies(25);
1822
1823         while (!gpio_get_value(ulpi_stp)) {
1824                 if (time_after(jiffies, timeout)) {
1825                         pr_warn("phy restore timeout\n");
1826                         return 1;
1827                 }
1828         }
1829
1830         return 0;
1831 }
1832
1833 static int ulpi_null_phy_lp0_resume(struct tegra_usb_phy *phy)
1834 {
1835         unsigned long val;
1836         void __iomem *base = phy->regs;
1837
1838         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1839
1840         val = readl(base + USB_USBCMD);
1841         val |= USB_USBCMD_RESET;
1842         writel(val, base + USB_USBCMD);
1843
1844         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1845                 USB_USBCMD_RESET, 0, 2500) < 0) {
1846                 pr_err("%s: timeout waiting for reset\n", __func__);
1847         }
1848
1849         val = readl(base + USB_USBMODE_REG_OFFSET);
1850         val &= ~USB_USBMODE_MASK;
1851         val |= USB_USBMODE_HOST;
1852         writel(val, base + USB_USBMODE_REG_OFFSET);
1853
1854         val = readl(base + USB_USBCMD);
1855         val |= USB_USBCMD_RS;
1856         writel(val, base + USB_USBCMD);
1857         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
1858                                                  USB_USBCMD_RS, 2000)) {
1859                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
1860                 return -ETIMEDOUT;
1861         }
1862
1863         /* Enable Port Power */
1864         val = readl(base + USB_PORTSC);
1865         val |= USB_PORTSC_PP;
1866         writel(val, base + USB_PORTSC);
1867         udelay(10);
1868
1869         ulpi_null_phy_restore(phy);
1870
1871         return 0;
1872 }
1873
1874 static int ulpi_null_phy_power_on(struct tegra_usb_phy *phy)
1875 {
1876         unsigned long val;
1877         void __iomem *base = phy->regs;
1878         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
1879
1880         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1881         if (phy->phy_clk_on) {
1882                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
1883                                                         __LINE__, phy->inst);
1884                 return 0;
1885         }
1886
1887         val = readl(base + USB_SUSP_CTRL);
1888         val |= UHSIC_RESET;
1889         writel(val, base + USB_SUSP_CTRL);
1890
1891         val = readl(base + ULPI_TIMING_CTRL_0);
1892         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
1893         writel(val, base + ULPI_TIMING_CTRL_0);
1894
1895         val = readl(base + USB_SUSP_CTRL);
1896         val |= ULPI_PHY_ENABLE;
1897         writel(val, base + USB_SUSP_CTRL);
1898         udelay(10);
1899
1900         /* set timming parameters */
1901         val = readl(base + ULPI_TIMING_CTRL_0);
1902         val |= ULPI_SHADOW_CLK_LOOPBACK_EN;
1903         val |= ULPI_SHADOW_CLK_SEL;
1904         val |= ULPI_LBK_PAD_EN;
1905         val |= ULPI_SHADOW_CLK_DELAY(config->shadow_clk_delay);
1906         val |= ULPI_CLOCK_OUT_DELAY(config->clock_out_delay);
1907         val |= ULPI_LBK_PAD_E_INPUT_OR;
1908         writel(val, base + ULPI_TIMING_CTRL_0);
1909
1910         writel(0, base + ULPI_TIMING_CTRL_1);
1911         udelay(10);
1912
1913         /* start internal 60MHz clock */
1914         val = readl(base + ULPIS2S_CTRL);
1915         val |= ULPIS2S_ENA;
1916         val |= ULPIS2S_SUPPORT_DISCONNECT;
1917         val |= ULPIS2S_SPARE((phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST)
1918                                 ? 3 : 1);
1919         val |= ULPIS2S_PLLU_MASTER_BLASTER60;
1920         writel(val, base + ULPIS2S_CTRL);
1921
1922         /* select ULPI_CORE_CLK_SEL to SHADOW_CLK */
1923         val = readl(base + ULPI_TIMING_CTRL_0);
1924         val |= ULPI_CORE_CLK_SEL;
1925         writel(val, base + ULPI_TIMING_CTRL_0);
1926         udelay(10);
1927
1928         /* enable ULPI null phy clock - can't set the trimmers before this */
1929         val = readl(base + ULPI_TIMING_CTRL_0);
1930         val |= ULPI_CLK_OUT_ENA;
1931         writel(val, base + ULPI_TIMING_CTRL_0);
1932         udelay(10);
1933
1934         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
1935                                                  USB_PHY_CLK_VALID, 2500)) {
1936                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
1937                 return -ETIMEDOUT;
1938         }
1939
1940         /* set ULPI trimmers */
1941         ulpi_set_trimmer(phy);
1942
1943         if (!phy->ulpi_clk_padout_ena) {
1944                 val = readl(base + ULPI_TIMING_CTRL_0);
1945                 val |= ULPI_CLK_PADOUT_ENA;
1946                 writel(val, base + ULPI_TIMING_CTRL_0);
1947                 phy->ulpi_clk_padout_ena = true;
1948         } else {
1949                 if (!readl(base + USB_ASYNCLISTADDR))
1950                         ulpi_null_phy_lp0_resume(phy);
1951         }
1952         udelay(10);
1953
1954         phy->phy_clk_on = true;
1955         phy->hw_accessible = true;
1956
1957         return 0;
1958 }
1959
1960 static int ulpi_null_phy_pre_resume(struct tegra_usb_phy *phy,
1961                                     bool remote_wakeup)
1962 {
1963         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1964         ulpi_null_phy_obs_read();
1965         usb_phy_wait_for_sof(phy);
1966         ulpi_null_phy_obs_read();
1967         return 0;
1968 }
1969
1970 static int ulpi_null_phy_post_resume(struct tegra_usb_phy *phy)
1971 {
1972         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1973         ulpi_null_phy_obs_read();
1974         return 0;
1975 }
1976
1977 static int ulpi_null_phy_resume(struct tegra_usb_phy *phy)
1978 {
1979         unsigned long val;
1980         void __iomem *base = phy->regs;
1981
1982         if (!readl(base + USB_ASYNCLISTADDR)) {
1983                 /* enable ULPI CLK output pad */
1984                 val = readl(base + ULPI_TIMING_CTRL_0);
1985                 val |= ULPI_CLK_PADOUT_ENA;
1986                 writel(val, base + ULPI_TIMING_CTRL_0);
1987
1988                 /* enable ULPI pinmux bypass */
1989                 ulpi_pinmux_bypass(phy, true);
1990                 udelay(5);
1991         }
1992
1993         return 0;
1994 }
1995
1996
1997
1998 static struct tegra_usb_phy_ops utmi_phy_ops = {
1999         .open           = utmi_phy_open,
2000         .close          = utmi_phy_close,
2001         .irq            = utmi_phy_irq,
2002         .power_on       = utmi_phy_power_on,
2003         .power_off      = utmi_phy_power_off,
2004         .pre_resume = utmi_phy_pre_resume,
2005         .resume = utmi_phy_resume,
2006         .post_resume    = utmi_phy_post_resume,
2007         .charger_detect = utmi_phy_charger_detect,
2008         .post_suspend   = phy_post_suspend,
2009 };
2010
2011 static struct tegra_usb_phy_ops uhsic_phy_ops = {
2012         .open           = uhsic_phy_open,
2013         .irq            = uhsic_phy_irq,
2014         .power_on       = uhsic_phy_power_on,
2015         .power_off      = uhsic_phy_power_off,
2016         .pre_resume     = uhsic_phy_pre_resume,
2017         .resume         = uhsic_phy_resume,
2018         .post_resume    = uhsic_phy_post_resume,
2019         .port_power     = uhsic_phy_bus_port_power,
2020         .bus_reset      = uhsic_phy_bus_reset,
2021         .post_suspend   = phy_post_suspend,
2022 };
2023
2024 static struct tegra_usb_phy_ops ulpi_link_phy_ops = {
2025         .open           = ulpi_link_phy_open,
2026         .close  = ulpi_link_phy_close,
2027         .irq            = ulpi_link_phy_irq,
2028         .power_on       = ulpi_link_phy_power_on,
2029         .power_off      = ulpi_link_phy_power_off,
2030         .resume         = ulpi_link_phy_resume,
2031         .post_suspend   = phy_post_suspend,
2032         .pre_resume     = ulpi_link_phy_pre_resume,
2033 };
2034
2035 static struct tegra_usb_phy_ops ulpi_null_phy_ops = {
2036         .open           = ulpi_null_phy_open,
2037         .close          = ulpi_null_phy_close,
2038         .irq            = ulpi_null_phy_irq,
2039         .power_on       = ulpi_null_phy_power_on,
2040         .power_off      = ulpi_null_phy_power_off,
2041         .pre_resume = ulpi_null_phy_pre_resume,
2042         .resume = ulpi_null_phy_resume,
2043         .post_suspend   = phy_post_suspend,
2044         .post_resume = ulpi_null_phy_post_resume,
2045 };
2046
2047 static struct tegra_usb_phy_ops icusb_phy_ops;
2048
2049
2050 static struct tegra_usb_phy_ops *phy_ops[] = {
2051         [TEGRA_USB_PHY_INTF_UTMI] = &utmi_phy_ops,
2052         [TEGRA_USB_PHY_INTF_ULPI_LINK] = &ulpi_link_phy_ops,
2053         [TEGRA_USB_PHY_INTF_ULPI_NULL] = &ulpi_null_phy_ops,
2054         [TEGRA_USB_PHY_INTF_HSIC] = &uhsic_phy_ops,
2055         [TEGRA_USB_PHY_INTF_ICUSB] = &icusb_phy_ops,
2056 };
2057
2058 int tegra2_usb_phy_init_ops(struct tegra_usb_phy *phy)
2059 {
2060         phy->ops = phy_ops[phy->pdata->phy_intf];
2061
2062         return 0;
2063 }