ARM: Tegra: fix compilation warnings
[linux-2.6.git] / arch / arm / mach-tegra / tegra2_usb_phy.c
1 /*
2  * arch/arm/mach-tegra/tegra2_usb_phy.c
3  *
4  * Copyright (C) 2011 NVIDIA Corporation
5  *
6  *
7  * This software is licensed under the terms of the GNU General Public
8  * License version 2, as published by the Free Software Foundation, and
9  * may be copied, distributed, and modified under those terms.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17 #include <linux/resource.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/slab.h>
21 #include <linux/err.h>
22 #include <linux/platform_device.h>
23 #include <linux/io.h>
24 #include <linux/gpio.h>
25 #include <linux/usb/otg.h>
26 #include <linux/usb/ulpi.h>
27 #include <linux/interrupt.h>
28 #include <linux/clk.h>
29 #include <linux/regulator/consumer.h>
30 #include <linux/platform_data/tegra_usb.h>
31
32 #include <asm/mach-types.h>
33
34 #include <mach/iomap.h>
35 #include <mach/pinmux.h>
36 #include <mach/pinmux-tegra20.h>
37 #include <mach/usb_phy.h>
38
39 #include "tegra_usb_phy.h"
40 #include "fuse.h"
41
42 #define USB_USBCMD              0x140
43 #define   USB_USBCMD_RS         (1 << 0)
44 #define   USB_USBCMD_RESET      (1 << 1)
45
46 #define USB_USBSTS              0x144
47 #define   USB_USBSTS_PCI        (1 << 2)
48 #define   USB_USBSTS_SRI        (1 << 7)
49 #define   USB_USBSTS_HCH        (1 << 12)
50
51 #define USB_ASYNCLISTADDR       0x158
52
53 #define USB_TXFILLTUNING                0x164
54 #define USB_FIFO_TXFILL_THRES(x)   (((x) & 0x1f) << 16)
55 #define USB_FIFO_TXFILL_MASK    0x1f0000
56
57 #define ULPI_VIEWPORT           0x170
58 #define   ULPI_WAKEUP           (1 << 31)
59 #define   ULPI_RUN              (1 << 30)
60 #define   ULPI_RD_WR            (1 << 29)
61
62 #define USB_PORTSC              0x184
63 #define   USB_PORTSC_PTS(x)     (((x) & 0x3) << 30)
64 #define   USB_PORTSC_PSPD(x)    (((x) & 0x3) << 26)
65 #define   USB_PORTSC_PHCD       (1 << 23)
66 #define   USB_PORTSC_WKOC       (1 << 22)
67 #define   USB_PORTSC_WKDS       (1 << 21)
68 #define   USB_PORTSC_WKCN       (1 << 20)
69 #define   USB_PORTSC_PTC(x)     (((x) & 0xf) << 16)
70 #define   USB_PORTSC_PP (1 << 12)
71 #define   USB_PORTSC_LS(x) (((x) & 0x3) << 10)
72 #define   USB_PORTSC_SUSP       (1 << 7)
73 #define   USB_PORTSC_OCC        (1 << 5)
74 #define   USB_PORTSC_PEC        (1 << 3)
75 #define   USB_PORTSC_PE         (1 << 2)
76 #define   USB_PORTSC_CSC        (1 << 1)
77 #define   USB_PORTSC_CCS        (1 << 0)
78 #define   USB_PORTSC_RWC_BITS (USB_PORTSC_CSC | USB_PORTSC_PEC | USB_PORTSC_OCC)
79 #define   USB_PORTSC_PSPD_MASK  3
80
81 #define USB_USBMODE_REG_OFFSET  0x1a8
82 #define   USB_USBMODE_MASK              (3 << 0)
83 #define   USB_USBMODE_HOST              (3 << 0)
84 #define   USB_USBMODE_DEVICE    (2 << 0)
85
86 #define USB_SUSP_CTRL           0x400
87 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
88 #define   USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
89 #define   USB_SUSP_CLR          (1 << 5)
90 #define   USB_CLKEN             (1 << 6)
91 #define   USB_PHY_CLK_VALID (1 << 7)
92 #define   USB_PHY_CLK_VALID_INT_ENB    (1 << 9)
93 #define   UTMIP_RESET           (1 << 11)
94 #define   UHSIC_RESET           (1 << 11)
95 #define   UTMIP_PHY_ENABLE      (1 << 12)
96 #define   UHSIC_PHY_ENABLE      (1 << 12)
97 #define   ULPI_PHY_ENABLE       (1 << 13)
98 #define   USB_SUSP_SET          (1 << 14)
99 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
100 #define   USB_PHY_CLK_VALID_INT_STS     (1 << 8)
101
102 #define USB_PHY_VBUS_WAKEUP_ID  0x408
103 #define   VDAT_DET_INT_EN       (1 << 16)
104 #define   VDAT_DET_CHG_DET      (1 << 17)
105 #define   VDAT_DET_STS          (1 << 18)
106 #define   USB_ID_STATUS         (1 << 2)
107
108 #define USB1_LEGACY_CTRL        0x410
109 #define   USB1_NO_LEGACY_MODE                   (1 << 0)
110 #define   USB1_VBUS_SENSE_CTL_MASK              (3 << 1)
111 #define   USB1_VBUS_SENSE_CTL_VBUS_WAKEUP       (0 << 1)
112 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
113                                                 (1 << 1)
114 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD       (2 << 1)
115 #define   USB1_VBUS_SENSE_CTL_A_SESS_VLD        (3 << 1)
116
117 #define ULPIS2S_CTRL            0x418
118 #define   ULPIS2S_ENA                   (1 << 0)
119 #define   ULPIS2S_SUPPORT_DISCONNECT    (1 << 2)
120 #define   ULPIS2S_PLLU_MASTER_BLASTER60 (1 << 3)
121 #define   ULPIS2S_SPARE(x)              (((x) & 0xF) << 8)
122 #define   ULPIS2S_FORCE_ULPI_CLK_OUT    (1 << 12)
123 #define   ULPIS2S_DISCON_DONT_CHECK_SE0 (1 << 13)
124 #define   ULPIS2S_SUPPORT_HS_KEEP_ALIVE (1 << 14)
125 #define   ULPIS2S_DISABLE_STP_PU        (1 << 15)
126 #define   ULPIS2S_SLV0_CLAMP_XMIT       (1 << 16)
127
128 #define ULPI_TIMING_CTRL_0      0x424
129 #define   ULPI_CLOCK_OUT_DELAY(x)       ((x) & 0x1F)
130 #define   ULPI_OUTPUT_PINMUX_BYP        (1 << 10)
131 #define   ULPI_CLKOUT_PINMUX_BYP        (1 << 11)
132 #define   ULPI_SHADOW_CLK_LOOPBACK_EN   (1 << 12)
133 #define   ULPI_SHADOW_CLK_SEL           (1 << 13)
134 #define   ULPI_CORE_CLK_SEL             (1 << 14)
135 #define   ULPI_SHADOW_CLK_DELAY(x)      (((x) & 0x1F) << 16)
136 #define   ULPI_LBK_PAD_EN               (1 << 26)
137 #define   ULPI_LBK_PAD_E_INPUT_OR       (1 << 27)
138 #define   ULPI_CLK_OUT_ENA              (1 << 28)
139 #define   ULPI_CLK_PADOUT_ENA           (1 << 29)
140
141 #define ULPI_TIMING_CTRL_1      0x428
142 #define   ULPI_DATA_TRIMMER_LOAD        (1 << 0)
143 #define   ULPI_DATA_TRIMMER_SEL(x)      (((x) & 0x7) << 1)
144 #define   ULPI_STPDIRNXT_TRIMMER_LOAD   (1 << 16)
145 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
146 #define   ULPI_DIR_TRIMMER_LOAD         (1 << 24)
147 #define   ULPI_DIR_TRIMMER_SEL(x)       (((x) & 0x7) << 25)
148
149 #define UTMIP_PLL_CFG1          0x804
150 #define UHSIC_PLL_CFG1                          0x804
151 #define   UTMIP_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
152 #define   UTMIP_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 27)
153 #define   UHSIC_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
154 #define   UHSIC_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 14)
155
156 #define UTMIP_XCVR_UHSIC_HSRX_CFG0              0x808
157 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
158 #define   UHSIC_ELASTIC_UNDERRUN_LIMIT(x)       (((x) & 0x1f) << 2)
159 #define   UHSIC_ELASTIC_OVERRUN_LIMIT(x)        (((x) & 0x1f) << 8)
160 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
161 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
162 #define   UHSIC_IDLE_WAIT(x)                    (((x) & 0x1f) << 13)
163 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
164 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
165 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
166 #define   UTMIP_XCVR_LSBIAS_SEL                 (1 << 21)
167 #define   UTMIP_XCVR_SETUP_MSB(x)               (((x) & 0x7) << 22)
168 #define   UTMIP_XCVR_HSSLEW_MSB(x)              (((x) & 0x7f) << 25)
169 #define   UTMIP_XCVR_MAX_OFFSET         2
170 #define   UTMIP_XCVR_SETUP_MAX_VALUE    0x7f
171 #define   UTMIP_XCVR_SETUP_MIN_VALUE    0
172 #define   XCVR_SETUP_MSB_CALIB(x) ((x) >> 4)
173
174 #define UTMIP_BIAS_CFG0                 0x80c
175 #define   UTMIP_OTGPD                   (1 << 11)
176 #define   UTMIP_BIASPD                  (1 << 10)
177
178 #define UHSIC_HSRX_CFG1                         0x80c
179 #define   UHSIC_HS_SYNC_START_DLY(x)            (((x) & 0x1f) << 1)
180
181 #define UTMIP_HSRX_CFG0                 0x810
182 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
183 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
184
185 #define UTMIP_HSRX_CFG1                 0x814
186 #define UHSIC_MISC_CFG0                 0x814
187 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
188 #define   UHSIC_SUSPEND_EXIT_ON_EDGE            (1 << 7)
189 #define   UHSIC_DETECT_SHORT_CONNECT            (1 << 8)
190 #define   UHSIC_FORCE_XCVR_MODE                 (1 << 15)
191
192 #define UHSIC_MISC_CFG1                         0x818
193 #define   UHSIC_PLLU_STABLE_COUNT(x)            (((x) & 0xfff) << 2)
194
195 #define UHSIC_PADS_CFG0                         0x81c
196 #define   UHSIC_TX_RTUNEN                       0xf000
197 #define   UHSIC_TX_RTUNE(x)                     (((x) & 0xf) << 12)
198
199 #define UTMIP_TX_CFG0                           0x820
200 #define UHSIC_PADS_CFG1                         0x820
201 #define   UHSIC_PD_BG                           (1 << 2)
202 #define   UHSIC_PD_TX                           (1 << 3)
203 #define   UHSIC_PD_TRK                          (1 << 4)
204 #define   UHSIC_PD_RX                           (1 << 5)
205 #define   UHSIC_PD_ZI                           (1 << 6)
206 #define   UHSIC_RX_SEL                          (1 << 7)
207 #define   UHSIC_RPD_DATA                        (1 << 9)
208 #define   UHSIC_RPD_STROBE                      (1 << 10)
209 #define   UHSIC_RPU_DATA                        (1 << 11)
210 #define   UHSIC_RPU_STROBE                      (1 << 12)
211 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
212 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
213
214 #define UTMIP_MISC_CFG0         0x824
215 #define   UTMIP_DPDM_OBSERVE            (1 << 26)
216 #define   UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
217 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J   UTMIP_DPDM_OBSERVE_SEL(0xf)
218 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K   UTMIP_DPDM_OBSERVE_SEL(0xe)
219 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
220 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
221 #define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
222 #define   FORCE_PULLDN_DM       (1 << 8)
223 #define   FORCE_PULLDN_DP       (1 << 9)
224 #define   COMB_TERMS            (1 << 0)
225 #define   ALWAYS_FREE_RUNNING_TERMS (1 << 1)
226
227 #define USB1_PREFETCH_ID               6
228 #define USB2_PREFETCH_ID               18
229 #define USB3_PREFETCH_ID               17
230
231 #define UTMIP_MISC_CFG1         0x828
232 #define   UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18)
233 #define   UTMIP_PLLU_STABLE_COUNT(x)    (((x) & 0xfff) << 6)
234
235 #define UHSIC_STAT_CFG0         0x828
236 #define   UHSIC_CONNECT_DETECT          (1 << 0)
237
238 #define UTMIP_DEBOUNCE_CFG0 0x82c
239 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
240
241 #define UTMIP_BAT_CHRG_CFG0     0x830
242 #define   UTMIP_PD_CHRG                 (1 << 0)
243 #define   UTMIP_ON_SINK_EN              (1 << 2)
244 #define   UTMIP_OP_SRC_EN               (1 << 3)
245
246 #define UTMIP_SPARE_CFG0        0x834
247 #define   FUSE_SETUP_SEL                (1 << 3)
248 #define   FUSE_ATERM_SEL                (1 << 4)
249
250 #define UTMIP_XCVR_CFG1         0x838
251 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
252 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
253 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
254 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
255
256 #define UTMIP_BIAS_CFG1         0x83c
257 #define   UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
258
259 #define FUSE_USB_CALIB_0                0x1F0
260 #define FUSE_USB_CALIB_XCVR_SETUP(x)    (((x) & 0x7F) << 0)
261
262 /* These values (in milli second) are taken from the battery charging spec */
263 #define TDP_SRC_ON_MS    100
264 #define TDPSRC_CON_MS    40
265
266 #ifdef DEBUG
267 #define DBG(stuff...)   pr_info("tegra2_usb_phy: " stuff)
268 #else
269 #define DBG(stuff...)   do {} while (0)
270 #endif
271
272 static DEFINE_SPINLOCK(utmip_pad_lock);
273 static int utmip_pad_count;
274 static int utmip_pad_state_on;
275
276 static struct tegra_xtal_freq utmip_freq_table[] = {
277         {
278                 .freq = 12000000,
279                 .enable_delay = 0x02,
280                 .stable_count = 0x2F,
281                 .active_delay = 0x04,
282                 .xtal_freq_count = 0x76,
283                 .debounce = 0x7530,
284                 .pdtrk_count = 5,
285         },
286         {
287                 .freq = 13000000,
288                 .enable_delay = 0x02,
289                 .stable_count = 0x33,
290                 .active_delay = 0x05,
291                 .xtal_freq_count = 0x7F,
292                 .debounce = 0x7EF4,
293                 .pdtrk_count = 5,
294         },
295         {
296                 .freq = 19200000,
297                 .enable_delay = 0x03,
298                 .stable_count = 0x4B,
299                 .active_delay = 0x06,
300                 .xtal_freq_count = 0xBB,
301                 .debounce = 0xBB80,
302                 .pdtrk_count = 7,
303         },
304         {
305                 .freq = 26000000,
306                 .enable_delay = 0x04,
307                 .stable_count = 0x66,
308                 .active_delay = 0x09,
309                 .xtal_freq_count = 0xFE,
310                 .debounce = 0xFDE8,
311                 .pdtrk_count = 9,
312         },
313 };
314
315 static struct tegra_xtal_freq uhsic_freq_table[] = {
316         {
317                 .freq = 12000000,
318                 .enable_delay = 0x02,
319                 .stable_count = 0x2F,
320                 .active_delay = 0x0,
321                 .xtal_freq_count = 0x1CA,
322         },
323         {
324                 .freq = 13000000,
325                 .enable_delay = 0x02,
326                 .stable_count = 0x33,
327                 .active_delay = 0x0,
328                 .xtal_freq_count = 0x1F0,
329         },
330         {
331                 .freq = 19200000,
332                 .enable_delay = 0x03,
333                 .stable_count = 0x4B,
334                 .active_delay = 0x0,
335                 .xtal_freq_count = 0x2DD,
336         },
337         {
338                 .freq = 26000000,
339                 .enable_delay = 0x04,
340                 .stable_count = 0x66,
341                 .active_delay = 0x0,
342                 .xtal_freq_count = 0x3E0,
343         },
344 };
345
346 static void usb_phy_fence_read(struct tegra_usb_phy *phy)
347 {
348         /* Fence read for coherency of AHB master intiated writes */
349         if (phy->inst == 0)
350                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB1_PREFETCH_ID));
351         else if (phy->inst == 1)
352                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB2_PREFETCH_ID));
353         else if (phy->inst == 2)
354                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB3_PREFETCH_ID));
355
356         return;
357 }
358
359 static int usb_phy_bringup_host_controller(struct tegra_usb_phy *phy)
360 {
361         unsigned long val;
362         void __iomem *base = phy->regs;
363
364         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
365         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d] - 0\n",
366                         readl(base + USB_USBSTS), readl(base + USB_PORTSC),
367                                                         phy->port_speed);
368
369         /* enable host mode */
370         val = readl(base + USB_USBMODE_REG_OFFSET);
371         val |= USB_USBMODE_HOST;
372         writel(val, base + USB_USBMODE_REG_OFFSET);
373
374         /* Enable Port Power */
375         val = readl(base + USB_PORTSC);
376         val |= USB_PORTSC_PP;
377         writel(val, base + USB_PORTSC);
378         udelay(10);
379
380         /* Check if the phy resume from LP0. When the phy resume from LP0
381          * USB register will be reset.to zero */
382         if (!readl(base + USB_ASYNCLISTADDR)) {
383                 val = readl(base + USB_USBCMD);
384                 val |= USB_USBCMD_RS;
385                 writel(val, base + USB_USBCMD);
386
387                 /* Program the field PTC based on the saved speed mode */
388                 val = readl(base + USB_PORTSC);
389                 val &= ~(USB_PORTSC_PTC(~0));
390                 if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH)
391                         val |= USB_PORTSC_PTC(5);
392                 else if (phy->port_speed == USB_PHY_PORT_SPEED_FULL)
393                         val |= USB_PORTSC_PTC(6);
394                 else if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
395                         val |= USB_PORTSC_PTC(7);
396                 writel(val, base + USB_PORTSC);
397                 udelay(10);
398
399                 /* Disable test mode by setting PTC field to NORMAL_OP */
400                 val = readl(base + USB_PORTSC);
401                 val &= ~(USB_PORTSC_PTC(~0));
402                 writel(val, base + USB_PORTSC);
403                 udelay(10);
404         }
405
406         /* Poll until CCS is enabled */
407         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
408                                                  USB_PORTSC_CCS, 2000)) {
409                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
410         }
411
412         /* Poll until PE is enabled */
413         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_PE,
414                                                  USB_PORTSC_PE, 2000)) {
415                 pr_err("%s: timeout waiting for USB_PORTSC_PE\n", __func__);
416         }
417
418         /* Clear the PCI status, to avoid an interrupt taken upon resume */
419         val = readl(base + USB_USBSTS);
420         val |= USB_USBSTS_PCI;
421         writel(val, base + USB_USBSTS);
422
423         /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
424         val = readl(base + USB_PORTSC);
425         if ((val & USB_PORTSC_PP) && (val & USB_PORTSC_PE)) {
426                 val |= USB_PORTSC_SUSP;
427                 writel(val, base + USB_PORTSC);
428                 /* Need a 4ms delay before the controller goes to suspend */
429                 mdelay(4);
430
431                 /* Wait until port suspend completes */
432                 if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_SUSP,
433                                                  USB_PORTSC_SUSP, 1000)) {
434                         pr_err("%s: timeout waiting for PORT_SUSPEND\n",
435                                                                 __func__);
436                 }
437         }
438
439         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
440                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
441
442         return 0;
443 }
444
445 static void usb_phy_wait_for_sof(struct tegra_usb_phy *phy)
446 {
447         unsigned long val;
448         void __iomem *base = phy->regs;
449
450         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
451         val = readl(base + USB_USBSTS);
452         writel(val, base + USB_USBSTS);
453         udelay(20);
454         /* wait for two SOFs */
455         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
456                 USB_USBSTS_SRI, 2500))
457                 pr_err("%s: timeout waiting for SOF\n", __func__);
458
459         val = readl(base + USB_USBSTS);
460         writel(val, base + USB_USBSTS);
461         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI, 0, 2500))
462                 pr_err("%s: timeout waiting for SOF\n", __func__);
463
464         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
465                         USB_USBSTS_SRI, 2500))
466                 pr_err("%s: timeout waiting for SOF\n", __func__);
467
468         udelay(20);
469 }
470
471 static unsigned int utmi_phy_xcvr_setup_value(struct tegra_usb_phy *phy)
472 {
473         struct tegra_utmi_config *cfg = &phy->pdata->u_cfg.utmi;
474         signed long val;
475
476         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
477         if (cfg->xcvr_use_fuses) {
478                 val = FUSE_USB_CALIB_XCVR_SETUP(
479                                 tegra_fuse_readl(FUSE_USB_CALIB_0));
480                 if (cfg->xcvr_setup_offset <= UTMIP_XCVR_MAX_OFFSET)
481                         val = val + cfg->xcvr_setup_offset;
482
483                 if (val > UTMIP_XCVR_SETUP_MAX_VALUE) {
484                         val = UTMIP_XCVR_SETUP_MAX_VALUE;
485                         pr_info("%s: reset XCVR_SETUP to max value\n",
486                                  __func__);
487                 } else if (val < UTMIP_XCVR_SETUP_MIN_VALUE) {
488                         val = UTMIP_XCVR_SETUP_MIN_VALUE;
489                         pr_info("%s: reset XCVR_SETUP to min value\n",
490                                  __func__);
491                 }
492         } else {
493                 val = cfg->xcvr_setup;
494         }
495
496         return (unsigned int) val;
497 }
498
499
500 static int utmi_phy_open(struct tegra_usb_phy *phy)
501 {
502         unsigned long parent_rate;
503         int i;
504
505         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
506         phy->utmi_pad_clk = clk_get_sys("utmip-pad", NULL);
507         if (IS_ERR(phy->utmi_pad_clk)) {
508                 pr_err("%s: can't get utmip pad clock\n", __func__);
509                 return PTR_ERR(phy->utmi_pad_clk);
510         }
511
512         phy->utmi_xcvr_setup = utmi_phy_xcvr_setup_value(phy);
513
514         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
515         for (i = 0; i < ARRAY_SIZE(utmip_freq_table); i++) {
516                 if (utmip_freq_table[i].freq == parent_rate) {
517                         phy->freq = &utmip_freq_table[i];
518                         break;
519                 }
520         }
521         if (!phy->freq) {
522                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
523                 return -EINVAL;
524         }
525
526         return 0;
527 }
528
529 static void utmi_phy_close(struct tegra_usb_phy *phy)
530 {
531         DBG("%s inst:[%d]\n", __func__, phy->inst);
532
533         clk_put(phy->utmi_pad_clk);
534 }
535
536 static int utmi_phy_pad_power_on(struct tegra_usb_phy *phy)
537 {
538         unsigned long val, flags;
539         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
540
541         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
542         clk_enable(phy->utmi_pad_clk);
543
544         spin_lock_irqsave(&utmip_pad_lock, flags);
545
546         utmip_pad_count++;
547         val = readl(pad_base + UTMIP_BIAS_CFG0);
548         val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
549         writel(val, pad_base + UTMIP_BIAS_CFG0);
550         utmip_pad_state_on = true;
551
552         spin_unlock_irqrestore(&utmip_pad_lock, flags);
553
554         clk_disable(phy->utmi_pad_clk);
555
556         return 0;
557 }
558
559 static int utmi_phy_pad_power_off(struct tegra_usb_phy *phy)
560 {
561         unsigned long val, flags;
562         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
563
564         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
565         clk_enable(phy->utmi_pad_clk);
566         spin_lock_irqsave(&utmip_pad_lock, flags);
567
568         if (!utmip_pad_count) {
569                 pr_err("%s: utmip pad already powered off\n", __func__);
570                 goto out;
571         }
572         if (--utmip_pad_count == 0) {
573                 val = readl(pad_base + UTMIP_BIAS_CFG0);
574                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
575                 writel(val, pad_base + UTMIP_BIAS_CFG0);
576                 utmip_pad_state_on = false;
577         }
578 out:
579         spin_unlock_irqrestore(&utmip_pad_lock, flags);
580         clk_disable(phy->utmi_pad_clk);
581
582         return 0;
583 }
584
585 static int utmi_phy_irq(struct tegra_usb_phy *phy)
586 {
587         void __iomem *base = phy->regs;
588         unsigned long val = 0;
589
590         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
591
592         usb_phy_fence_read(phy);
593         if (phy->pdata->u_data.host.hot_plug) {
594                 val = readl(base + USB_SUSP_CTRL);
595                 if ((val  & USB_PHY_CLK_VALID_INT_STS)) {
596                         val &= ~USB_PHY_CLK_VALID_INT_ENB |
597                                         USB_PHY_CLK_VALID_INT_STS;
598                         writel(val , (base + USB_SUSP_CTRL));
599                         pr_info("%s: usb device plugged-in\n", __func__);
600                         val = readl(base + USB_USBSTS);
601                         if (!(val  & USB_USBSTS_PCI))
602                                 return IRQ_NONE;
603                         val = readl(base + USB_PORTSC);
604                         val &= ~(USB_PORTSC_WKCN | USB_PORTSC_RWC_BITS);
605                         writel(val , (base + USB_PORTSC));
606                 }
607         }
608
609         return IRQ_HANDLED;
610 }
611
612 static int phy_post_suspend(struct tegra_usb_phy *phy)
613 {
614
615         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
616         /* Need a 4ms delay for controller to suspend */
617         mdelay(4);
618         return 0;
619 }
620
621 static int utmi_phy_post_resume(struct tegra_usb_phy *phy)
622 {
623         unsigned long val;
624         void __iomem *base = phy->regs;
625
626         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
627
628         val = readl(base + UTMIP_TX_CFG0);
629         val &= ~UTMIP_HS_DISCON_DISABLE;
630         writel(val, base + UTMIP_TX_CFG0);
631         return 0;
632 }
633
634 static int utmi_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
635 {
636         unsigned long val;
637         void __iomem *base = phy->regs;
638
639         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
640         val = readl(base + UTMIP_TX_CFG0);
641         val |= UTMIP_HS_DISCON_DISABLE;
642         writel(val, base + UTMIP_TX_CFG0);
643
644         usb_phy_wait_for_sof(phy);
645
646         return 0;
647 }
648
649 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
650 {
651         unsigned long val;
652         void __iomem *base = phy->regs;
653
654         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
655         if (!phy->phy_clk_on) {
656                 DBG("%s(%d) inst:[%d] phy clk is already off\n",
657                                         __func__, __LINE__, phy->inst);
658                 return 0;
659         }
660
661         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
662                 val = readl(base + USB_SUSP_CTRL);
663                 val &= ~(USB_WAKEUP_DEBOUNCE_COUNT(~0));
664                 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
665                 writel(val, base + USB_SUSP_CTRL);
666
667                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
668                 val |= UTMIP_PD_CHRG;
669                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
670         }
671
672         if (!phy->pdata->u_data.host.hot_plug) {
673                 val = readl(base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
674                 val |= (UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
675                          UTMIP_FORCE_PDZI_POWERDOWN);
676                 writel(val, base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
677         }
678
679         val = readl(base + UTMIP_XCVR_CFG1);
680         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
681                    UTMIP_FORCE_PDDR_POWERDOWN;
682         writel(val, base + UTMIP_XCVR_CFG1);
683
684         if (phy->inst != 0) {
685                 val = readl(base + UTMIP_BIAS_CFG0);
686                 val |= UTMIP_OTGPD;
687                 writel(val, base + UTMIP_BIAS_CFG0);
688         }
689
690         phy->port_speed = (readl(base + USB_PORTSC) >> 26) &
691                         USB_PORTSC_PSPD_MASK;
692
693         if (phy->pdata->u_data.host.hot_plug) {
694                 bool enable_hotplug = true;
695                 /* if it is OTG port then make sure to enable hot-plug feature
696                    only if host adaptor is connected, i.e id is low */
697                 if (phy->pdata->port_otg) {
698                         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
699                         enable_hotplug = (val & USB_ID_STATUS) ? false : true;
700                 }
701                 if (enable_hotplug) {
702                         val = readl(base + USB_PORTSC);
703                         val |= USB_PORTSC_WKCN;
704                         writel(val, base + USB_PORTSC);
705
706                         val = readl(base + USB_SUSP_CTRL);
707                         val |= USB_PHY_CLK_VALID_INT_ENB;
708                         writel(val, base + USB_SUSP_CTRL);
709                 } else {
710                         /* Disable PHY clock valid interrupts while going into suspend*/
711                         val = readl(base + USB_SUSP_CTRL);
712                         val &= ~USB_PHY_CLK_VALID_INT_ENB;
713                         writel(val, base + USB_SUSP_CTRL);
714                 }
715         }
716
717         if (phy->inst == 2) {
718                 val = readl(base + USB_PORTSC);
719                 val |= USB_PORTSC_PHCD;
720                 writel(val, base + USB_PORTSC);
721         } else {
722                 val = readl(base + USB_SUSP_CTRL);
723                 val |= USB_SUSP_SET;
724                 writel(val, base + USB_SUSP_CTRL);
725                 udelay(10);
726                 val = readl(base + USB_SUSP_CTRL);
727                 val &= ~USB_SUSP_SET;
728                 writel(val, base + USB_SUSP_CTRL);
729         }
730
731         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
732                                                                 0, 2500))
733                 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
734
735         utmi_phy_pad_power_off(phy);
736
737         phy->phy_clk_on = false;
738         phy->hw_accessible = false;
739
740         DBG("%s(%d) inst:[%d]END\n", __func__, __LINE__, phy->inst);
741
742         return 0;
743 }
744
745 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
746 {
747         unsigned long val;
748         void __iomem *base = phy->regs;
749         struct tegra_utmi_config *config = &phy->pdata->u_cfg.utmi;
750         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
751         if (phy->phy_clk_on) {
752                 DBG("%s(%d) inst:[%d] phy clk is already on\n",
753                                         __func__, __LINE__, phy->inst);
754                 return 0;
755         }
756
757         val = readl(base + USB_SUSP_CTRL);
758         val |= UTMIP_RESET;
759         writel(val, base + USB_SUSP_CTRL);
760
761         val = readl(base + UTMIP_TX_CFG0);
762         val |= UTMIP_FS_PREABMLE_J;
763         writel(val, base + UTMIP_TX_CFG0);
764
765         val = readl(base + UTMIP_HSRX_CFG0);
766         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
767         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
768         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
769         writel(val, base + UTMIP_HSRX_CFG0);
770
771         val = readl(base + UTMIP_HSRX_CFG1);
772         val &= ~(UTMIP_HS_SYNC_START_DLY(~0));
773         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
774         writel(val, base + UTMIP_HSRX_CFG1);
775
776         val = readl(base + UTMIP_DEBOUNCE_CFG0);
777         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
778         val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
779         writel(val, base + UTMIP_DEBOUNCE_CFG0);
780
781         val = readl(base + UTMIP_MISC_CFG0);
782         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
783         writel(val, base + UTMIP_MISC_CFG0);
784
785         val = readl(base + UTMIP_MISC_CFG1);
786         val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) | UTMIP_PLLU_STABLE_COUNT(~0));
787         val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |
788                 UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count);
789         writel(val, base + UTMIP_MISC_CFG1);
790
791         val = readl(base + UTMIP_PLL_CFG1);
792         val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) | UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
793         val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |
794                 UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
795         writel(val, base + UTMIP_PLL_CFG1);
796
797         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
798                 val = readl(base + USB_SUSP_CTRL);
799                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
800                 writel(val, base + USB_SUSP_CTRL);
801
802                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
803                 val &= ~UTMIP_PD_CHRG;
804                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
805         } else {
806                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
807                 val |= UTMIP_PD_CHRG;
808                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
809         }
810
811         utmi_phy_pad_power_on(phy);
812
813         val = readl(base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
814         val &= ~(UTMIP_XCVR_LSBIAS_SEL | UTMIP_FORCE_PD_POWERDOWN |
815                  UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN |
816                  UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_LSFSLEW(~0) |
817                  UTMIP_XCVR_LSRSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
818         val |= UTMIP_XCVR_SETUP(phy->utmi_xcvr_setup);
819         val |= UTMIP_XCVR_SETUP_MSB(XCVR_SETUP_MSB_CALIB(phy->utmi_xcvr_setup));
820         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
821         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
822
823         writel(val, base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
824
825         val = readl(base + UTMIP_XCVR_CFG1);
826         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
827                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
828         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
829         writel(val, base + UTMIP_XCVR_CFG1);
830
831
832         val = readl(base + UTMIP_BIAS_CFG1);
833         val &= ~(UTMIP_BIAS_PDTRK_COUNT(~0));
834         val |= UTMIP_BIAS_PDTRK_COUNT(phy->freq->pdtrk_count);
835         writel(val, base + UTMIP_BIAS_CFG1);
836
837         val = readl(base + UTMIP_SPARE_CFG0);
838         val &= ~FUSE_SETUP_SEL;
839         writel(val, base + UTMIP_SPARE_CFG0);
840
841         val = readl(base + USB_SUSP_CTRL);
842         val |= UTMIP_PHY_ENABLE;
843         writel(val, base + USB_SUSP_CTRL);
844
845         val = readl(base + USB_SUSP_CTRL);
846         val &= ~UTMIP_RESET;
847         writel(val, base + USB_SUSP_CTRL);
848
849         if (phy->inst == 0) {
850                 val = readl(base + USB_SUSP_CTRL);
851                 val &= ~USB_SUSP_SET;
852                 writel(val, base + USB_SUSP_CTRL);
853         } else {
854                 val = readl(base + USB_PORTSC);
855                 val &= ~USB_PORTSC_PHCD;
856                 writel(val, base + USB_PORTSC);
857         }
858
859         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
860                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500))
861                 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
862
863         if (phy->inst == 2) {
864                 val = readl(base + USB_PORTSC);
865                 val &= ~(USB_PORTSC_PTS(~0));
866                 writel(val, base + USB_PORTSC);
867         }
868
869         phy->phy_clk_on = true;
870         phy->hw_accessible = true;
871
872         return 0;
873 }
874
875 static void utmi_phy_restore_start(struct tegra_usb_phy *phy)
876 {
877         unsigned long val;
878         void __iomem *base = phy->regs;
879
880         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
881         val = readl(base + UTMIP_MISC_CFG0);
882         val &= ~(UTMIP_DPDM_OBSERVE_SEL(~0));
883
884         if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
885                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
886         else
887                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
888         writel(val, base + UTMIP_MISC_CFG0);
889         udelay(1);
890
891         val = readl(base + UTMIP_MISC_CFG0);
892         val |= UTMIP_DPDM_OBSERVE;
893         writel(val, base + UTMIP_MISC_CFG0);
894         udelay(10);
895 }
896
897 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
898 {
899         unsigned long val;
900         void __iomem *base = phy->regs;
901
902         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
903         val = readl(base + UTMIP_MISC_CFG0);
904         val &= ~UTMIP_DPDM_OBSERVE;
905         writel(val, base + UTMIP_MISC_CFG0);
906         udelay(10);
907 }
908
909
910 static int utmi_phy_resume(struct tegra_usb_phy *phy)
911 {
912         int status = 0;
913         unsigned long val, flags;
914         void __iomem *base = phy->regs;
915         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
916
917         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
918         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) {
919                 if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
920                         utmi_phy_restore_start(phy);
921                         usb_phy_bringup_host_controller(phy);
922                         utmi_phy_restore_end(phy);
923                 } else {
924                         /* device is plugged in when system is in LP0 */
925                         /* bring up the controller from LP0*/
926                         val = readl(base + USB_USBCMD);
927                         val |= USB_USBCMD_RESET;
928                         writel(val, base + USB_USBCMD);
929
930                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
931                                 USB_USBCMD_RESET, 0, 2500) < 0) {
932                                 pr_err("%s: timeout waiting for reset\n", __func__);
933                         }
934
935                         val = readl(base + USB_USBMODE_REG_OFFSET);
936                         val &= ~USB_USBMODE_MASK;
937                         val |= USB_USBMODE_HOST;
938                         writel(val, base + USB_USBMODE_REG_OFFSET);
939
940                         if (phy->inst == 2) {
941                                 val = readl(base + USB_PORTSC);
942                                 val &= ~USB_PORTSC_PTS(~0);
943                                 writel(val, base + USB_PORTSC);
944                         }
945                         writel(USB_USBCMD_RS, base + USB_USBCMD);
946
947                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
948                                 USB_USBCMD_RS, USB_USBCMD_RS, 2500) < 0) {
949                                 pr_err("%s: timeout waiting for run bit\n", __func__);
950                         }
951
952                         /* Enable Port Power */
953                         val = readl(base + USB_PORTSC);
954                         val |= USB_PORTSC_PP;
955                         writel(val, base + USB_PORTSC);
956                         udelay(10);
957
958                         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
959                                 readl(base + USB_USBSTS), readl(base + USB_PORTSC));
960                 }
961         } else {
962                 /* Restoring the pad powers */
963                 clk_enable(phy->utmi_pad_clk);
964
965                 spin_lock_irqsave(&utmip_pad_lock, flags);
966
967                 val = readl(pad_base + UTMIP_BIAS_CFG0);
968                 if (utmip_pad_state_on)
969                         val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
970                 else
971                         val |= (UTMIP_OTGPD | UTMIP_BIASPD);
972                 writel(val, pad_base + UTMIP_BIAS_CFG0);
973
974                 spin_unlock_irqrestore(&utmip_pad_lock, flags);
975                 clk_disable(phy->utmi_pad_clk);
976         }
977
978         return status;
979 }
980
981 static bool utmi_phy_charger_detect(struct tegra_usb_phy *phy)
982 {
983         unsigned long val;
984         void __iomem *base = phy->regs;
985         bool status;
986
987         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
988         /* Enable charger detection logic */
989         val = readl(base + UTMIP_BAT_CHRG_CFG0);
990         val |= UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN;
991         writel(val, base + UTMIP_BAT_CHRG_CFG0);
992
993         /* Source should be on for 100 ms as per USB charging spec */
994         msleep(TDP_SRC_ON_MS);
995
996         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
997         /* If charger is not connected disable the interrupt */
998         val &= ~VDAT_DET_INT_EN;
999         val |= VDAT_DET_CHG_DET;
1000         writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
1001
1002         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1003         if (val & VDAT_DET_STS)
1004                 status = true;
1005         else
1006                 status = false;
1007
1008         /* Disable charger detection logic */
1009         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1010         val &= ~(UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN);
1011         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1012
1013         /* Delay of 40 ms before we pull the D+ as per battery charger spec */
1014         msleep(TDPSRC_CON_MS);
1015
1016         return status;
1017 }
1018
1019
1020 static int uhsic_phy_open(struct tegra_usb_phy *phy)
1021 {
1022         unsigned long parent_rate;
1023         int i;
1024
1025         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1026         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
1027         for (i = 0; i < ARRAY_SIZE(uhsic_freq_table); i++) {
1028                 if (uhsic_freq_table[i].freq == parent_rate) {
1029                         phy->freq = &uhsic_freq_table[i];
1030                         break;
1031                 }
1032         }
1033         if (!phy->freq) {
1034                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
1035                 return -EINVAL;
1036         }
1037
1038         return 0;
1039 }
1040
1041 static int uhsic_phy_irq(struct tegra_usb_phy *phy)
1042 {
1043         usb_phy_fence_read(phy);
1044         return IRQ_HANDLED;
1045 }
1046
1047 static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
1048 {
1049         unsigned long val;
1050         void __iomem *base = phy->regs;
1051         struct tegra_hsic_config *config = &phy->pdata->u_cfg.hsic;
1052
1053         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1054         if (phy->phy_clk_on) {
1055                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
1056                                                         __LINE__, phy->inst);
1057                 return 0;
1058         }
1059
1060         val = readl(base + UHSIC_PADS_CFG1);
1061         val &= ~(UHSIC_PD_BG | UHSIC_PD_TX | UHSIC_PD_TRK | UHSIC_PD_RX |
1062                         UHSIC_PD_ZI | UHSIC_RPD_DATA | UHSIC_RPD_STROBE);
1063         val |= UHSIC_RX_SEL;
1064         writel(val, base + UHSIC_PADS_CFG1);
1065         udelay(2);
1066
1067         val = readl(base + USB_SUSP_CTRL);
1068         val |= UHSIC_RESET;
1069         writel(val, base + USB_SUSP_CTRL);
1070         udelay(30);
1071
1072         val = readl(base + USB_SUSP_CTRL);
1073         val |= UHSIC_PHY_ENABLE;
1074         writel(val, base + USB_SUSP_CTRL);
1075
1076         val = readl(base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
1077         val |= UHSIC_IDLE_WAIT(config->idle_wait_delay);
1078         val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(config->elastic_underrun_limit);
1079         val |= UHSIC_ELASTIC_OVERRUN_LIMIT(config->elastic_overrun_limit);
1080         writel(val, base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
1081
1082         val = readl(base + UHSIC_HSRX_CFG1);
1083         val |= UHSIC_HS_SYNC_START_DLY(config->sync_start_delay);
1084         writel(val, base + UHSIC_HSRX_CFG1);
1085
1086         val = readl(base + UHSIC_MISC_CFG0);
1087         val |= UHSIC_SUSPEND_EXIT_ON_EDGE;
1088         writel(val, base + UHSIC_MISC_CFG0);
1089
1090         val = readl(base + UHSIC_MISC_CFG1);
1091         val |= UHSIC_PLLU_STABLE_COUNT(phy->freq->stable_count);
1092         writel(val, base + UHSIC_MISC_CFG1);
1093
1094         val = readl(base + UHSIC_PLL_CFG1);
1095         val |= UHSIC_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
1096         val |= UHSIC_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count);
1097         writel(val, base + UHSIC_PLL_CFG1);
1098
1099         val = readl(base + USB_SUSP_CTRL);
1100         val &= ~(UHSIC_RESET);
1101         writel(val, base + USB_SUSP_CTRL);
1102         udelay(2);
1103
1104         val = readl(base + USB_PORTSC);
1105         val &= ~(USB_PORTSC_PTS(~0));
1106         writel(val, base + USB_PORTSC);
1107
1108         val = readl(base + USB_TXFILLTUNING);
1109         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
1110                 val = USB_FIFO_TXFILL_THRES(0x10);
1111                 writel(val, base + USB_TXFILLTUNING);
1112         }
1113
1114         val = readl(base + USB_PORTSC);
1115         val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN);
1116         writel(val, base + USB_PORTSC);
1117
1118         val = readl(base + UHSIC_PADS_CFG0);
1119         val &= ~(UHSIC_TX_RTUNEN);
1120         /* set Rtune impedance to 40 ohm */
1121         val |= UHSIC_TX_RTUNE(0);
1122         writel(val, base + UHSIC_PADS_CFG0);
1123
1124         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
1125                                                 USB_PHY_CLK_VALID, 2500)) {
1126                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
1127                 return -ETIMEDOUT;
1128         }
1129
1130         phy->phy_clk_on = true;
1131         phy->hw_accessible = true;
1132
1133         return 0;
1134 }
1135
1136 static int uhsic_phy_power_off(struct tegra_usb_phy *phy)
1137 {
1138         unsigned long val;
1139         void __iomem *base = phy->regs;
1140
1141         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1142         if (!phy->phy_clk_on) {
1143                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
1144                                                         __LINE__, phy->inst);
1145                 return 0;
1146         }
1147
1148         val = readl(base + UHSIC_PADS_CFG1);
1149         val &= ~UHSIC_RPU_STROBE;
1150         val |= UHSIC_RPD_STROBE;
1151         writel(val, base + UHSIC_PADS_CFG1);
1152
1153         val = readl(base + USB_SUSP_CTRL);
1154         val |= UHSIC_RESET;
1155         writel(val, base + USB_SUSP_CTRL);
1156         udelay(30);
1157
1158         val = readl(base + USB_SUSP_CTRL);
1159         val &= ~UHSIC_PHY_ENABLE;
1160         writel(val, base + USB_SUSP_CTRL);
1161
1162         phy->phy_clk_on = false;
1163         phy->hw_accessible = false;
1164
1165         return 0;
1166 }
1167
1168 static int uhsic_phy_bus_port_power(struct tegra_usb_phy *phy)
1169 {
1170         unsigned long val;
1171         void __iomem *base = phy->regs;
1172
1173         val = readl(base + UHSIC_MISC_CFG0);
1174         val |= UHSIC_DETECT_SHORT_CONNECT;
1175         writel(val, base + UHSIC_MISC_CFG0);
1176         udelay(1);
1177
1178         val = readl(base + UHSIC_MISC_CFG0);
1179         val |= UHSIC_FORCE_XCVR_MODE;
1180         writel(val, base + UHSIC_MISC_CFG0);
1181
1182         val = readl(base + UHSIC_PADS_CFG1);
1183         val &= ~UHSIC_RPD_STROBE;
1184         val |= UHSIC_RPU_STROBE;
1185         writel(val, base + UHSIC_PADS_CFG1);
1186
1187         val = readl(base + USB_USBCMD);
1188         val &= ~USB_USBCMD_RS;
1189         writel(val, base + USB_USBCMD);
1190
1191         if (phy->pdata->ops && phy->pdata->ops->port_power)
1192                 phy->pdata->ops->port_power();
1193
1194         if (usb_phy_reg_status_wait(base + UHSIC_STAT_CFG0,
1195                         UHSIC_CONNECT_DETECT, UHSIC_CONNECT_DETECT, 2000)) {
1196                 pr_err("%s: timeout waiting for UHSIC_CONNECT_DETECT\n",
1197                                                                 __func__);
1198                 return -ETIMEDOUT;
1199         }
1200
1201 /* FIXME : need to check whether this piece is required or not
1202         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_LS(2),
1203                                                 USB_PORTSC_LS(2), 2000)) {
1204                 pr_err("%s: timeout waiting for dplus state\n", __func__);
1205                 return -ETIMEDOUT;
1206         }
1207 */
1208         return 0;
1209 }
1210
1211
1212 static int uhsic_phy_bus_reset(struct tegra_usb_phy *phy)
1213 {
1214         unsigned long val;
1215         void __iomem *base = phy->regs;
1216
1217         val = readl(base + USB_PORTSC);
1218         val |= USB_PORTSC_PTC(5);
1219         writel(val, base + USB_PORTSC);
1220         udelay(2);
1221
1222         val = readl(base + USB_PORTSC);
1223         val &= ~(USB_PORTSC_PTC(~0));
1224         writel(val, base + USB_PORTSC);
1225         udelay(2);
1226
1227         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_LS(0),
1228                                                  0, 2000)) {
1229                 pr_err("%s: timeout waiting for USB_PORTSC_LS\n", __func__);
1230                 return -ETIMEDOUT;
1231         }
1232
1233         /* Poll until CCS is enabled */
1234         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
1235                                                  USB_PORTSC_CCS, 2000)) {
1236                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
1237                 return -ETIMEDOUT;
1238         }
1239
1240         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_PSPD(2),
1241                                                  USB_PORTSC_PSPD(2), 2000)) {
1242                 pr_err("%s: timeout waiting for USB_PORTSC_PSPD\n", __func__);
1243                 return -ETIMEDOUT;
1244         }
1245
1246         val = readl(base + USB_USBCMD);
1247         val &= ~USB_USBCMD_RS;
1248         writel(val, base + USB_USBCMD);
1249
1250         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
1251                                                  USB_USBSTS_HCH, 2000)) {
1252                 pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
1253                 return -ETIMEDOUT;
1254         }
1255
1256         val = readl(base + UHSIC_PADS_CFG1);
1257         val &= ~UHSIC_RPU_STROBE;
1258         val |= UHSIC_RPD_STROBE;
1259         writel(val, base + UHSIC_PADS_CFG1);
1260
1261         mdelay(50);
1262
1263         val = readl(base + UHSIC_PADS_CFG1);
1264         val &= ~UHSIC_RPD_STROBE;
1265         val |= UHSIC_RPU_STROBE;
1266         writel(val, base + UHSIC_PADS_CFG1);
1267
1268         val = readl(base + USB_USBCMD);
1269         val |= USB_USBCMD_RS;
1270         writel(val, base + USB_USBCMD);
1271
1272         val = readl(base + UHSIC_PADS_CFG1);
1273         val &= ~UHSIC_RPU_STROBE;
1274         writel(val, base + UHSIC_PADS_CFG1);
1275
1276         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
1277                                                  USB_USBCMD_RS, 2000)) {
1278                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
1279                 return -ETIMEDOUT;
1280         }
1281
1282         return 0;
1283 }
1284
1285
1286 static int uhsic_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1287 {
1288         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1289         usb_phy_wait_for_sof(phy);
1290
1291         return 0;
1292 }
1293
1294 static int uhsic_phy_resume(struct tegra_usb_phy *phy)
1295 {
1296         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1297         uhsic_phy_bus_port_power(phy);
1298
1299         return 0;
1300 }
1301
1302
1303 static int uhsic_phy_post_resume(struct tegra_usb_phy *phy)
1304 {
1305         unsigned long val;
1306         void __iomem *base = phy->regs;
1307
1308         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1309         val = readl(base + USB_TXFILLTUNING);
1310         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
1311                 val = USB_FIFO_TXFILL_THRES(0x10);
1312                 writel(val, base + USB_TXFILLTUNING);
1313         }
1314
1315         return 0;
1316 }
1317
1318 static void ulpi_set_trimmer(struct tegra_usb_phy *phy)
1319 {
1320         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
1321         void __iomem *base = phy->regs;
1322         unsigned long val;
1323
1324         val = ULPI_DATA_TRIMMER_SEL(config->data_trimmer);
1325         val |= ULPI_STPDIRNXT_TRIMMER_SEL(config->stpdirnxt_trimmer);
1326         val |= ULPI_DIR_TRIMMER_SEL(config->dir_trimmer);
1327         writel(val, base + ULPI_TIMING_CTRL_1);
1328         udelay(10);
1329
1330         val |= ULPI_DATA_TRIMMER_LOAD;
1331         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
1332         val |= ULPI_DIR_TRIMMER_LOAD;
1333         writel(val, base + ULPI_TIMING_CTRL_1);
1334 }
1335
1336
1337 static int ulpi_link_phy_open(struct tegra_usb_phy *phy)
1338 {
1339         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
1340         int err = 0;
1341
1342         phy->ulpi_clk = NULL;
1343
1344         if (config->clk) {
1345                 phy->ulpi_clk = clk_get_sys(NULL, config->clk);
1346                 if (IS_ERR(phy->ulpi_clk)) {
1347                         pr_err("%s: can't get ulpi clock\n", __func__);
1348                         err = -ENXIO;
1349                 }
1350         }
1351
1352         phy->ulpi_vp = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
1353         phy->ulpi_vp->io_priv = phy->regs + ULPI_VIEWPORT;
1354
1355         return err;
1356 }
1357
1358 static void ulpi_link_phy_close(struct tegra_usb_phy *phy)
1359 {
1360         DBG("%s inst:[%d]\n", __func__, phy->inst);
1361         if (phy->ulpi_clk)
1362                 clk_put(phy->ulpi_clk);
1363 }
1364
1365 static int ulpi_link_phy_irq(struct tegra_usb_phy *phy)
1366 {
1367         usb_phy_fence_read(phy);
1368         return IRQ_HANDLED;
1369 }
1370
1371 static int ulpi_link_phy_power_off(struct tegra_usb_phy *phy)
1372 {
1373         unsigned long val;
1374         void __iomem *base = phy->regs;
1375         int ret;
1376
1377         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1378         if (!phy->phy_clk_on) {
1379                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
1380                                                         __LINE__, phy->inst);
1381                 return 0;
1382         }
1383
1384         /* Disable VbusValid, SessEnd comparators */
1385         ret = usb_phy_io_write(phy->ulpi_vp, 0x00, 0x0D);
1386         if (ret)
1387                 pr_err("%s: ulpi write 0x0D failed\n", __func__);
1388
1389         ret = usb_phy_io_write(phy->ulpi_vp, 0x00, 0x10);
1390         if (ret)
1391                 pr_err("%s: ulpi write 0x10 failed\n", __func__);
1392
1393         /* Disable IdFloat comparator */
1394         ret = usb_phy_io_write(phy->ulpi_vp, 0x00, 0x19);
1395         if (ret)
1396                 pr_err("%s: ulpi write 0x19 failed\n", __func__);
1397
1398         ret = usb_phy_io_write(phy->ulpi_vp, 0x00, 0x1D);
1399         if (ret)
1400                 pr_err("%s: ulpi write 0x1D failed\n", __func__);
1401
1402         phy->port_speed = (readl(base + USB_PORTSC) >> 26) &
1403                         USB_PORTSC_PSPD_MASK;
1404
1405         /* Clear WKCN/WKDS/WKOC wake-on events that can cause the USB
1406          * Controller to immediately bring the ULPI PHY out of low power
1407          */
1408         val = readl(base + USB_PORTSC);
1409         val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN);
1410         writel(val, base + USB_PORTSC);
1411
1412         /* Put the PHY in the low power mode */
1413         val = readl(base + USB_PORTSC);
1414         val |= USB_PORTSC_PHCD;
1415         writel(val, base + USB_PORTSC);
1416
1417         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
1418                                                          0, 2500)) {
1419                 pr_err("%s: timeout waiting for phy to stop\n", __func__);
1420         }
1421
1422         if (phy->ulpi_clk)
1423                 clk_disable(phy->ulpi_clk);
1424
1425         phy->phy_clk_on = false;
1426         phy->hw_accessible = false;
1427
1428         return 0;
1429 }
1430
1431 static int ulpi_link_phy_power_on(struct tegra_usb_phy *phy)
1432 {
1433         int ret;
1434         unsigned long val;
1435         void __iomem *base = phy->regs;
1436
1437         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1438         if (phy->phy_clk_on) {
1439                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
1440                                                         __LINE__, phy->inst);
1441                 return 0;
1442         }
1443
1444         if (phy->ulpi_clk) {
1445                 clk_enable(phy->ulpi_clk);
1446                 mdelay(1);
1447         }
1448
1449         val = readl(base + USB_SUSP_CTRL);
1450         val |= UHSIC_RESET;
1451         writel(val, base + USB_SUSP_CTRL);
1452
1453         val = readl(base + ULPI_TIMING_CTRL_0);
1454         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
1455         writel(val, base + ULPI_TIMING_CTRL_0);
1456
1457         val = readl(base + USB_SUSP_CTRL);
1458         val |= ULPI_PHY_ENABLE;
1459         writel(val, base + USB_SUSP_CTRL);
1460
1461         val = readl(base + USB_SUSP_CTRL);
1462         val |= USB_SUSP_CLR;
1463         writel(val, base + USB_SUSP_CTRL);
1464
1465         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
1466                                                 USB_PHY_CLK_VALID, 2500))
1467                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
1468
1469         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_CLKEN,
1470                                                 USB_CLKEN, 2500))
1471                 pr_err("%s: timeout waiting for AHB clock\n", __func__);
1472
1473         val = readl(base + USB_SUSP_CTRL);
1474         val &= ~USB_SUSP_CLR;
1475         writel(val, base + USB_SUSP_CTRL);
1476
1477         val = 0;
1478         writel(val, base + ULPI_TIMING_CTRL_1);
1479
1480         ulpi_set_trimmer(phy);
1481
1482         /* Fix VbusInvalid due to floating VBUS */
1483         ret = usb_phy_io_write(phy->ulpi_vp, 0x40, 0x08);
1484         if (ret) {
1485                 pr_err("%s: ulpi write failed\n", __func__);
1486                 return ret;
1487         }
1488
1489         ret = usb_phy_io_write(phy->ulpi_vp, 0x80, 0x0B);
1490         if (ret) {
1491                 pr_err("%s: ulpi write failed\n", __func__);
1492                 return ret;
1493         }
1494
1495         val = readl(base + USB_PORTSC);
1496         val |= USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN;
1497         writel(val, base + USB_PORTSC);
1498
1499         phy->phy_clk_on = true;
1500         phy->hw_accessible = true;
1501
1502         return 0;
1503 }
1504
1505 static inline void ulpi_link_phy_set_tristate(bool enable)
1506 {
1507 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1508         int tristate = (enable) ? TEGRA_TRI_TRISTATE : TEGRA_TRI_NORMAL;
1509
1510         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAA, tristate);
1511         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAB, tristate);
1512         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UDA, tristate);
1513 #endif
1514 }
1515
1516 static void ulpi_link_phy_restore_start(struct tegra_usb_phy *phy)
1517 {
1518         unsigned long val;
1519         void __iomem *base = phy->regs;
1520
1521         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1522
1523         /*Tristate ulpi interface before USB controller resume*/
1524         ulpi_link_phy_set_tristate(true);
1525
1526         val = readl(base + ULPI_TIMING_CTRL_0);
1527         val &= ~ULPI_OUTPUT_PINMUX_BYP;
1528         writel(val, base + ULPI_TIMING_CTRL_0);
1529 }
1530
1531 static void ulpi_link_phy_restore_end(struct tegra_usb_phy *phy)
1532 {
1533         unsigned long val;
1534         void __iomem *base = phy->regs;
1535
1536         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1537
1538         val = readl(base + ULPI_TIMING_CTRL_0);
1539         val |= ULPI_OUTPUT_PINMUX_BYP;
1540         writel(val, base + ULPI_TIMING_CTRL_0);
1541
1542         ulpi_link_phy_set_tristate(false);
1543 }
1544
1545 static int ulpi_link_phy_resume(struct tegra_usb_phy *phy)
1546 {
1547         int status = 0;
1548
1549         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1550         if (phy->pdata->u_data.host.power_off_on_suspend) {
1551                 status = ulpi_link_phy_power_on(phy);
1552                 if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
1553                         ulpi_link_phy_restore_start(phy);
1554                         usb_phy_bringup_host_controller(phy);
1555                         ulpi_link_phy_restore_end(phy);
1556                 }
1557         }
1558
1559         return status;
1560 }
1561
1562
1563 static int ulpi_null_phy_power_off(struct tegra_usb_phy *phy)
1564 {
1565         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1566
1567         if (!phy->phy_clk_on) {
1568                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
1569                                                         __LINE__, phy->inst);
1570                 return 0;
1571         }
1572
1573         phy->phy_clk_on = false;
1574         phy->hw_accessible = false;
1575
1576         return 0;
1577 }
1578
1579 static int ulpi_null_phy_irq(struct tegra_usb_phy *phy)
1580 {
1581         usb_phy_fence_read(phy);
1582         return IRQ_HANDLED;
1583 }
1584
1585 static int ulpi_null_phy_lp0_resume(struct tegra_usb_phy *phy)
1586 {
1587         unsigned long val;
1588         void __iomem *base = phy->regs;
1589
1590         val = readl(base + USB_USBCMD);
1591         val |= USB_USBCMD_RESET;
1592         writel(val, base + USB_USBCMD);
1593
1594         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1595                 USB_USBCMD_RESET, 0, 2500) < 0) {
1596                 pr_err("%s: timeout waiting for reset\n", __func__);
1597         }
1598
1599         val = readl(base + USB_USBMODE_REG_OFFSET);
1600         val &= ~USB_USBMODE_MASK;
1601         val |= USB_USBMODE_HOST;
1602         writel(val, base + USB_USBMODE_REG_OFFSET);
1603
1604         val = readl(base + USB_USBCMD);
1605         val |= USB_USBCMD_RS;
1606         writel(val, base + USB_USBCMD);
1607         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
1608                                                  USB_USBCMD_RS, 2000)) {
1609                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
1610                 return -ETIMEDOUT;
1611         }
1612
1613         /* Enable Port Power */
1614         val = readl(base + USB_PORTSC);
1615         val |= USB_PORTSC_PP;
1616         writel(val, base + USB_PORTSC);
1617         udelay(10);
1618
1619         /* disable ULPI pinmux bypass */
1620         val = readl(base + ULPI_TIMING_CTRL_0);
1621         val &= ~ULPI_OUTPUT_PINMUX_BYP;
1622         writel(val, base + ULPI_TIMING_CTRL_0);
1623
1624         return 0;
1625 }
1626
1627 static int ulpi_null_phy_power_on(struct tegra_usb_phy *phy)
1628 {
1629         unsigned long val;
1630         void __iomem *base = phy->regs;
1631         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
1632         static bool cold_boot = true;
1633
1634         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1635         if (phy->phy_clk_on) {
1636                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
1637                                                         __LINE__, phy->inst);
1638                 return 0;
1639         }
1640
1641         val = readl(base + USB_SUSP_CTRL);
1642         val |= UHSIC_RESET;
1643         writel(val, base + USB_SUSP_CTRL);
1644
1645         val = readl(base + ULPI_TIMING_CTRL_0);
1646         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
1647         writel(val, base + ULPI_TIMING_CTRL_0);
1648
1649         val = readl(base + USB_SUSP_CTRL);
1650         val |= ULPI_PHY_ENABLE;
1651         writel(val, base + USB_SUSP_CTRL);
1652         udelay(10);
1653
1654         /* set timming parameters */
1655         val = readl(base + ULPI_TIMING_CTRL_0);
1656         val |= ULPI_SHADOW_CLK_LOOPBACK_EN;
1657         val |= ULPI_SHADOW_CLK_SEL;
1658         val |= ULPI_LBK_PAD_EN;
1659         val |= ULPI_SHADOW_CLK_DELAY(config->shadow_clk_delay);
1660         val |= ULPI_CLOCK_OUT_DELAY(config->clock_out_delay);
1661         val |= ULPI_LBK_PAD_E_INPUT_OR;
1662         writel(val, base + ULPI_TIMING_CTRL_0);
1663
1664         writel(0, base + ULPI_TIMING_CTRL_1);
1665         udelay(10);
1666
1667         /* start internal 60MHz clock */
1668         val = readl(base + ULPIS2S_CTRL);
1669         val |= ULPIS2S_ENA;
1670         val |= ULPIS2S_SUPPORT_DISCONNECT;
1671         val |= ULPIS2S_SPARE((phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) ? 3 : 1);
1672         val |= ULPIS2S_PLLU_MASTER_BLASTER60;
1673         writel(val, base + ULPIS2S_CTRL);
1674
1675         /* select ULPI_CORE_CLK_SEL to SHADOW_CLK */
1676         val = readl(base + ULPI_TIMING_CTRL_0);
1677         val |= ULPI_CORE_CLK_SEL;
1678         writel(val, base + ULPI_TIMING_CTRL_0);
1679         udelay(10);
1680
1681         /* enable ULPI null phy clock - can't set the trimmers before this */
1682         val = readl(base + ULPI_TIMING_CTRL_0);
1683         val |= ULPI_CLK_OUT_ENA;
1684         writel(val, base + ULPI_TIMING_CTRL_0);
1685         udelay(10);
1686
1687         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
1688                                                  USB_PHY_CLK_VALID, 2500)) {
1689                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
1690                 return -ETIMEDOUT;
1691         }
1692
1693         /* set ULPI trimmers */
1694         ulpi_set_trimmer(phy);
1695
1696         if (cold_boot) {
1697                 val = readl(base + ULPI_TIMING_CTRL_0);
1698                 val |= ULPI_CLK_PADOUT_ENA;
1699                 writel(val, base + ULPI_TIMING_CTRL_0);
1700                 cold_boot = false;
1701         } else {
1702                 if (!readl(base + USB_ASYNCLISTADDR))
1703                         ulpi_null_phy_lp0_resume(phy);
1704         }
1705         udelay(10);
1706
1707         phy->phy_clk_on = true;
1708         phy->hw_accessible = true;
1709
1710         return 0;
1711 }
1712
1713
1714 static int ulpi_null_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1715 {
1716         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1717
1718         usb_phy_wait_for_sof(phy);
1719         return 0;
1720 }
1721
1722 static int ulpi_null_phy_resume(struct tegra_usb_phy *phy)
1723 {
1724         unsigned long val;
1725         void __iomem *base = phy->regs;
1726
1727         if (!readl(base + USB_ASYNCLISTADDR)) {
1728                 /* enable ULPI CLK output pad */
1729                 val = readl(base + ULPI_TIMING_CTRL_0);
1730                 val |= ULPI_CLK_PADOUT_ENA;
1731                 writel(val, base + ULPI_TIMING_CTRL_0);
1732
1733                 /* enable ULPI pinmux bypass */
1734                 val = readl(base + ULPI_TIMING_CTRL_0);
1735                 val |= ULPI_OUTPUT_PINMUX_BYP;
1736                 writel(val, base + ULPI_TIMING_CTRL_0);
1737                 udelay(5);
1738         }
1739
1740         return 0;
1741 }
1742
1743
1744
1745 static struct tegra_usb_phy_ops utmi_phy_ops = {
1746         .open           = utmi_phy_open,
1747         .close          = utmi_phy_close,
1748         .irq            = utmi_phy_irq,
1749         .power_on       = utmi_phy_power_on,
1750         .power_off      = utmi_phy_power_off,
1751         .pre_resume = utmi_phy_pre_resume,
1752         .resume = utmi_phy_resume,
1753         .post_resume    = utmi_phy_post_resume,
1754         .charger_detect = utmi_phy_charger_detect,
1755         .post_suspend   = phy_post_suspend,
1756 };
1757
1758 static struct tegra_usb_phy_ops uhsic_phy_ops = {
1759         .open           = uhsic_phy_open,
1760         .irq            = uhsic_phy_irq,
1761         .power_on       = uhsic_phy_power_on,
1762         .power_off      = uhsic_phy_power_off,
1763         .pre_resume     = uhsic_phy_pre_resume,
1764         .resume         = uhsic_phy_resume,
1765         .post_resume    = uhsic_phy_post_resume,
1766         .port_power     = uhsic_phy_bus_port_power,
1767         .bus_reset      = uhsic_phy_bus_reset,
1768         .post_suspend   = phy_post_suspend,
1769 };
1770
1771 static struct tegra_usb_phy_ops ulpi_link_phy_ops = {
1772         .open           = ulpi_link_phy_open,
1773         .close  = ulpi_link_phy_close,
1774         .irq            = ulpi_link_phy_irq,
1775         .power_on       = ulpi_link_phy_power_on,
1776         .power_off      = ulpi_link_phy_power_off,
1777         .resume         = ulpi_link_phy_resume,
1778         .post_suspend   = phy_post_suspend,
1779 };
1780
1781 static struct tegra_usb_phy_ops ulpi_null_phy_ops = {
1782         .irq            = ulpi_null_phy_irq,
1783         .power_on       = ulpi_null_phy_power_on,
1784         .power_off      = ulpi_null_phy_power_off,
1785         .pre_resume = ulpi_null_phy_pre_resume,
1786         .resume = ulpi_null_phy_resume,
1787         .post_suspend   = phy_post_suspend,
1788 };
1789
1790 static struct tegra_usb_phy_ops icusb_phy_ops;
1791
1792
1793 static struct tegra_usb_phy_ops *phy_ops[] = {
1794         [TEGRA_USB_PHY_INTF_UTMI] = &utmi_phy_ops,
1795         [TEGRA_USB_PHY_INTF_ULPI_LINK] = &ulpi_link_phy_ops,
1796         [TEGRA_USB_PHY_INTF_ULPI_NULL] = &ulpi_null_phy_ops,
1797         [TEGRA_USB_PHY_INTF_HSIC] = &uhsic_phy_ops,
1798         [TEGRA_USB_PHY_INTF_ICUSB] = &icusb_phy_ops,
1799 };
1800
1801 int tegra2_usb_phy_init_ops(struct tegra_usb_phy *phy)
1802 {
1803         phy->ops = phy_ops[phy->pdata->phy_intf];
1804
1805         return 0;
1806 }