57fd166ce02b51d1790e1c0ec37a4e6002d953f2
[linux-2.6.git] / arch / arm / mach-tegra / tegra2_usb_phy.c
1 /*
2  * arch/arm/mach-tegra/tegra2_usb_phy.c
3  *
4  * Copyright (C) 2011 NVIDIA Corporation
5  *
6  *
7  * This software is licensed under the terms of the GNU General Public
8  * License version 2, as published by the Free Software Foundation, and
9  * may be copied, distributed, and modified under those terms.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17 #include <linux/resource.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/slab.h>
21 #include <linux/err.h>
22 #include <linux/platform_device.h>
23 #include <linux/io.h>
24 #include <linux/gpio.h>
25 #include <linux/usb/otg.h>
26 #include <linux/usb/ulpi.h>
27 #include <linux/interrupt.h>
28 #include <linux/clk.h>
29 #include <linux/regulator/consumer.h>
30 #include <linux/platform_data/tegra_usb.h>
31
32 #include <asm/mach-types.h>
33
34 #include <mach/iomap.h>
35 #include <mach/pinmux.h>
36 #include <mach/pinmux-tegra20.h>
37 #include <mach/usb_phy.h>
38
39 #include "tegra_usb_phy.h"
40 #include "fuse.h"
41
42 #define USB_USBCMD              0x140
43 #define   USB_USBCMD_RS         (1 << 0)
44 #define   USB_USBCMD_RESET      (1 << 1)
45
46 #define USB_USBSTS              0x144
47 #define   USB_USBSTS_PCI        (1 << 2)
48 #define   USB_USBSTS_SRI        (1 << 7)
49 #define   USB_USBSTS_HCH        (1 << 12)
50
51 #define USB_ASYNCLISTADDR       0x158
52
53 #define USB_TXFILLTUNING                0x164
54 #define USB_FIFO_TXFILL_THRES(x)   (((x) & 0x1f) << 16)
55 #define USB_FIFO_TXFILL_MASK    0x1f0000
56
57 #define ULPI_VIEWPORT           0x170
58 #define   ULPI_WAKEUP           (1 << 31)
59 #define   ULPI_RUN              (1 << 30)
60 #define   ULPI_RD_WR            (1 << 29)
61
62 #define USB_PORTSC              0x184
63 #define   USB_PORTSC_PTS(x)     (((x) & 0x3) << 30)
64 #define   USB_PORTSC_PSPD(x)    (((x) & 0x3) << 26)
65 #define   USB_PORTSC_PHCD       (1 << 23)
66 #define   USB_PORTSC_WKOC       (1 << 22)
67 #define   USB_PORTSC_WKDS       (1 << 21)
68 #define   USB_PORTSC_WKCN       (1 << 20)
69 #define   USB_PORTSC_PTC(x)     (((x) & 0xf) << 16)
70 #define   USB_PORTSC_PP (1 << 12)
71 #define   USB_PORTSC_LS(x) (((x) & 0x3) << 10)
72 #define   USB_PORTSC_SUSP       (1 << 7)
73 #define   USB_PORTSC_OCC        (1 << 5)
74 #define   USB_PORTSC_PEC        (1 << 3)
75 #define   USB_PORTSC_PE         (1 << 2)
76 #define   USB_PORTSC_CSC        (1 << 1)
77 #define   USB_PORTSC_CCS        (1 << 0)
78 #define   USB_PORTSC_RWC_BITS (USB_PORTSC_CSC | USB_PORTSC_PEC | USB_PORTSC_OCC)
79 #define   USB_PORTSC_PSPD_MASK  3
80
81 #define USB_USBMODE_REG_OFFSET  0x1a8
82 #define   USB_USBMODE_MASK              (3 << 0)
83 #define   USB_USBMODE_HOST              (3 << 0)
84 #define   USB_USBMODE_DEVICE    (2 << 0)
85
86 #define USB_SUSP_CTRL           0x400
87 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
88 #define   USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
89 #define   USB_SUSP_CLR          (1 << 5)
90 #define   USB_CLKEN             (1 << 6)
91 #define   USB_PHY_CLK_VALID (1 << 7)
92 #define   USB_PHY_CLK_VALID_INT_ENB    (1 << 9)
93 #define   UTMIP_RESET           (1 << 11)
94 #define   UHSIC_RESET           (1 << 11)
95 #define   UTMIP_PHY_ENABLE      (1 << 12)
96 #define   UHSIC_PHY_ENABLE      (1 << 12)
97 #define   ULPI_PHY_ENABLE       (1 << 13)
98 #define   USB_SUSP_SET          (1 << 14)
99 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
100 #define   USB_PHY_CLK_VALID_INT_STS     (1 << 8)
101
102 #define USB_PHY_VBUS_WAKEUP_ID  0x408
103 #define   VDAT_DET_INT_EN       (1 << 16)
104 #define   VDAT_DET_CHG_DET      (1 << 17)
105 #define   VDAT_DET_STS          (1 << 18)
106 #define   USB_ID_STATUS         (1 << 2)
107
108 #define USB1_LEGACY_CTRL        0x410
109 #define   USB1_NO_LEGACY_MODE                   (1 << 0)
110 #define   USB1_VBUS_SENSE_CTL_MASK              (3 << 1)
111 #define   USB1_VBUS_SENSE_CTL_VBUS_WAKEUP       (0 << 1)
112 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
113                                                 (1 << 1)
114 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD       (2 << 1)
115 #define   USB1_VBUS_SENSE_CTL_A_SESS_VLD        (3 << 1)
116
117 #define ULPIS2S_CTRL            0x418
118 #define   ULPIS2S_ENA                   (1 << 0)
119 #define   ULPIS2S_SUPPORT_DISCONNECT    (1 << 2)
120 #define   ULPIS2S_PLLU_MASTER_BLASTER60 (1 << 3)
121 #define   ULPIS2S_SPARE(x)              (((x) & 0xF) << 8)
122 #define   ULPIS2S_FORCE_ULPI_CLK_OUT    (1 << 12)
123 #define   ULPIS2S_DISCON_DONT_CHECK_SE0 (1 << 13)
124 #define   ULPIS2S_SUPPORT_HS_KEEP_ALIVE (1 << 14)
125 #define   ULPIS2S_DISABLE_STP_PU        (1 << 15)
126 #define   ULPIS2S_SLV0_CLAMP_XMIT       (1 << 16)
127
128 #define ULPI_TIMING_CTRL_0      0x424
129 #define   ULPI_CLOCK_OUT_DELAY(x)       ((x) & 0x1F)
130 #define   ULPI_OUTPUT_PINMUX_BYP        (1 << 10)
131 #define   ULPI_CLKOUT_PINMUX_BYP        (1 << 11)
132 #define   ULPI_SHADOW_CLK_LOOPBACK_EN   (1 << 12)
133 #define   ULPI_SHADOW_CLK_SEL           (1 << 13)
134 #define   ULPI_CORE_CLK_SEL             (1 << 14)
135 #define   ULPI_SHADOW_CLK_DELAY(x)      (((x) & 0x1F) << 16)
136 #define   ULPI_LBK_PAD_EN               (1 << 26)
137 #define   ULPI_LBK_PAD_E_INPUT_OR       (1 << 27)
138 #define   ULPI_CLK_OUT_ENA              (1 << 28)
139 #define   ULPI_CLK_PADOUT_ENA           (1 << 29)
140
141 #define ULPI_TIMING_CTRL_1      0x428
142 #define   ULPI_DATA_TRIMMER_LOAD        (1 << 0)
143 #define   ULPI_DATA_TRIMMER_SEL(x)      (((x) & 0x7) << 1)
144 #define   ULPI_STPDIRNXT_TRIMMER_LOAD   (1 << 16)
145 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
146 #define   ULPI_DIR_TRIMMER_LOAD         (1 << 24)
147 #define   ULPI_DIR_TRIMMER_SEL(x)       (((x) & 0x7) << 25)
148
149 #define UTMIP_PLL_CFG1          0x804
150 #define UHSIC_PLL_CFG1                          0x804
151 #define   UTMIP_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
152 #define   UTMIP_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 27)
153 #define   UHSIC_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
154 #define   UHSIC_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 14)
155
156 #define UTMIP_XCVR_UHSIC_HSRX_CFG0              0x808
157 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
158 #define   UHSIC_ELASTIC_UNDERRUN_LIMIT(x)       (((x) & 0x1f) << 2)
159 #define   UHSIC_ELASTIC_OVERRUN_LIMIT(x)        (((x) & 0x1f) << 8)
160 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
161 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
162 #define   UHSIC_IDLE_WAIT(x)                    (((x) & 0x1f) << 13)
163 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
164 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
165 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
166 #define   UTMIP_XCVR_LSBIAS_SEL                 (1 << 21)
167 #define   UTMIP_XCVR_SETUP_MSB(x)               (((x) & 0x7) << 22)
168 #define   UTMIP_XCVR_HSSLEW_MSB(x)              (((x) & 0x7f) << 25)
169 #define   UTMIP_XCVR_MAX_OFFSET         2
170 #define   UTMIP_XCVR_SETUP_MAX_VALUE    0x7f
171 #define   UTMIP_XCVR_SETUP_MIN_VALUE    0
172 #define   XCVR_SETUP_MSB_CALIB(x) ((x) >> 4)
173
174 #define UTMIP_BIAS_CFG0                 0x80c
175 #define   UTMIP_OTGPD                   (1 << 11)
176 #define   UTMIP_BIASPD                  (1 << 10)
177
178 #define UHSIC_HSRX_CFG1                         0x80c
179 #define   UHSIC_HS_SYNC_START_DLY(x)            (((x) & 0x1f) << 1)
180
181 #define UTMIP_HSRX_CFG0                 0x810
182 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
183 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
184
185 #define UTMIP_HSRX_CFG1                 0x814
186 #define UHSIC_MISC_CFG0                 0x814
187 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
188 #define   UHSIC_SUSPEND_EXIT_ON_EDGE            (1 << 7)
189 #define   UHSIC_DETECT_SHORT_CONNECT            (1 << 8)
190 #define   UHSIC_FORCE_XCVR_MODE                 (1 << 15)
191
192 #define UHSIC_MISC_CFG1                         0x818
193 #define   UHSIC_PLLU_STABLE_COUNT(x)            (((x) & 0xfff) << 2)
194
195 #define UHSIC_PADS_CFG0                         0x81c
196 #define   UHSIC_TX_RTUNEN                       0xf000
197 #define   UHSIC_TX_RTUNE(x)                     (((x) & 0xf) << 12)
198
199 #define UTMIP_TX_CFG0                           0x820
200 #define UHSIC_PADS_CFG1                         0x820
201 #define   UHSIC_PD_BG                           (1 << 2)
202 #define   UHSIC_PD_TX                           (1 << 3)
203 #define   UHSIC_PD_TRK                          (1 << 4)
204 #define   UHSIC_PD_RX                           (1 << 5)
205 #define   UHSIC_PD_ZI                           (1 << 6)
206 #define   UHSIC_RX_SEL                          (1 << 7)
207 #define   UHSIC_RPD_DATA                        (1 << 9)
208 #define   UHSIC_RPD_STROBE                      (1 << 10)
209 #define   UHSIC_RPU_DATA                        (1 << 11)
210 #define   UHSIC_RPU_STROBE                      (1 << 12)
211 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
212 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
213
214 #define UTMIP_MISC_CFG0         0x824
215 #define   UTMIP_DPDM_OBSERVE            (1 << 26)
216 #define   UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
217 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J   UTMIP_DPDM_OBSERVE_SEL(0xf)
218 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K   UTMIP_DPDM_OBSERVE_SEL(0xe)
219 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
220 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
221 #define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
222 #define   FORCE_PULLDN_DM       (1 << 8)
223 #define   FORCE_PULLDN_DP       (1 << 9)
224 #define   COMB_TERMS            (1 << 0)
225 #define   ALWAYS_FREE_RUNNING_TERMS (1 << 1)
226
227 #define USB1_PREFETCH_ID               6
228 #define USB2_PREFETCH_ID               18
229 #define USB3_PREFETCH_ID               17
230
231 #define UTMIP_MISC_CFG1         0x828
232 #define   UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18)
233 #define   UTMIP_PLLU_STABLE_COUNT(x)    (((x) & 0xfff) << 6)
234
235 #define UHSIC_STAT_CFG0         0x828
236 #define   UHSIC_CONNECT_DETECT          (1 << 0)
237
238 #define UTMIP_DEBOUNCE_CFG0 0x82c
239 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
240
241 #define UTMIP_BAT_CHRG_CFG0     0x830
242 #define   UTMIP_PD_CHRG                 (1 << 0)
243 #define   UTMIP_ON_SINK_EN              (1 << 2)
244 #define   UTMIP_OP_SRC_EN               (1 << 3)
245
246 #define UTMIP_SPARE_CFG0        0x834
247 #define   FUSE_SETUP_SEL                (1 << 3)
248 #define   FUSE_ATERM_SEL                (1 << 4)
249
250 #define UTMIP_XCVR_CFG1         0x838
251 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
252 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
253 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
254 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
255
256 #define UTMIP_BIAS_CFG1         0x83c
257 #define   UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
258
259 #define FUSE_USB_CALIB_0                0x1F0
260 #define FUSE_USB_CALIB_XCVR_SETUP(x)    (((x) & 0x7F) << 0)
261
262 /* These values (in milli second) are taken from the battery charging spec */
263 #define TDP_SRC_ON_MS    100
264 #define TDPSRC_CON_MS    40
265
266 #ifdef DEBUG
267 #define DBG(stuff...)   pr_info("tegra2_usb_phy: " stuff)
268 #else
269 #define DBG(stuff...)   do {} while (0)
270 #endif
271
272 static DEFINE_SPINLOCK(utmip_pad_lock);
273 static int utmip_pad_count;
274 static int utmip_pad_state_on;
275
276 static struct tegra_xtal_freq utmip_freq_table[] = {
277         {
278                 .freq = 12000000,
279                 .enable_delay = 0x02,
280                 .stable_count = 0x2F,
281                 .active_delay = 0x04,
282                 .xtal_freq_count = 0x76,
283                 .debounce = 0x7530,
284                 .pdtrk_count = 5,
285         },
286         {
287                 .freq = 13000000,
288                 .enable_delay = 0x02,
289                 .stable_count = 0x33,
290                 .active_delay = 0x05,
291                 .xtal_freq_count = 0x7F,
292                 .debounce = 0x7EF4,
293                 .pdtrk_count = 5,
294         },
295         {
296                 .freq = 19200000,
297                 .enable_delay = 0x03,
298                 .stable_count = 0x4B,
299                 .active_delay = 0x06,
300                 .xtal_freq_count = 0xBB,
301                 .debounce = 0xBB80,
302                 .pdtrk_count = 7,
303         },
304         {
305                 .freq = 26000000,
306                 .enable_delay = 0x04,
307                 .stable_count = 0x66,
308                 .active_delay = 0x09,
309                 .xtal_freq_count = 0xFE,
310                 .debounce = 0xFDE8,
311                 .pdtrk_count = 9,
312         },
313 };
314
315 static struct tegra_xtal_freq uhsic_freq_table[] = {
316         {
317                 .freq = 12000000,
318                 .enable_delay = 0x02,
319                 .stable_count = 0x2F,
320                 .active_delay = 0x0,
321                 .xtal_freq_count = 0x1CA,
322         },
323         {
324                 .freq = 13000000,
325                 .enable_delay = 0x02,
326                 .stable_count = 0x33,
327                 .active_delay = 0x0,
328                 .xtal_freq_count = 0x1F0,
329         },
330         {
331                 .freq = 19200000,
332                 .enable_delay = 0x03,
333                 .stable_count = 0x4B,
334                 .active_delay = 0x0,
335                 .xtal_freq_count = 0x2DD,
336         },
337         {
338                 .freq = 26000000,
339                 .enable_delay = 0x04,
340                 .stable_count = 0x66,
341                 .active_delay = 0x0,
342                 .xtal_freq_count = 0x3E0,
343         },
344 };
345
346 static void usb_phy_fence_read(struct tegra_usb_phy *phy)
347 {
348         /* Fence read for coherency of AHB master intiated writes */
349         if (phy->inst == 0)
350                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB1_PREFETCH_ID));
351         else if (phy->inst == 1)
352                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB2_PREFETCH_ID));
353         else if (phy->inst == 2)
354                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB3_PREFETCH_ID));
355
356         return;
357 }
358
359 static int usb_phy_bringup_host_controller(struct tegra_usb_phy *phy)
360 {
361         unsigned long val;
362         void __iomem *base = phy->regs;
363
364         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
365         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d] - 0\n",
366                         readl(base + USB_USBSTS), readl(base + USB_PORTSC),
367                                                         phy->port_speed);
368
369         /* enable host mode */
370         val = readl(base + USB_USBMODE_REG_OFFSET);
371         val |= USB_USBMODE_HOST;
372         writel(val, base + USB_USBMODE_REG_OFFSET);
373
374         /* Enable Port Power */
375         val = readl(base + USB_PORTSC);
376         val |= USB_PORTSC_PP;
377         writel(val, base + USB_PORTSC);
378         udelay(10);
379
380         /* Check if the phy resume from LP0. When the phy resume from LP0
381          * USB register will be reset.to zero */
382         if (!readl(base + USB_ASYNCLISTADDR)) {
383                 val = readl(base + USB_USBCMD);
384                 val |= USB_USBCMD_RS;
385                 writel(val, base + USB_USBCMD);
386
387                 /* Program the field PTC based on the saved speed mode */
388                 val = readl(base + USB_PORTSC);
389                 val &= ~(USB_PORTSC_PTC(~0));
390                 if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH)
391                         val |= USB_PORTSC_PTC(5);
392                 else if (phy->port_speed == USB_PHY_PORT_SPEED_FULL)
393                         val |= USB_PORTSC_PTC(6);
394                 else if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
395                         val |= USB_PORTSC_PTC(7);
396                 writel(val, base + USB_PORTSC);
397                 udelay(10);
398
399                 /* Disable test mode by setting PTC field to NORMAL_OP */
400                 val = readl(base + USB_PORTSC);
401                 val &= ~(USB_PORTSC_PTC(~0));
402                 writel(val, base + USB_PORTSC);
403                 udelay(10);
404         }
405
406         /* Poll until CCS is enabled */
407         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
408                                                  USB_PORTSC_CCS, 2000)) {
409                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
410         }
411
412         /* Poll until PE is enabled */
413         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_PE,
414                                                  USB_PORTSC_PE, 2000)) {
415                 pr_err("%s: timeout waiting for USB_PORTSC_PE\n", __func__);
416         }
417
418         /* Clear the PCI status, to avoid an interrupt taken upon resume */
419         val = readl(base + USB_USBSTS);
420         val |= USB_USBSTS_PCI;
421         writel(val, base + USB_USBSTS);
422
423         /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
424         val = readl(base + USB_PORTSC);
425         if ((val & USB_PORTSC_PP) && (val & USB_PORTSC_PE)) {
426                 val |= USB_PORTSC_SUSP;
427                 writel(val, base + USB_PORTSC);
428                 /* Need a 4ms delay before the controller goes to suspend */
429                 mdelay(4);
430
431                 /* Wait until port suspend completes */
432                 if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_SUSP,
433                                                  USB_PORTSC_SUSP, 1000)) {
434                         pr_err("%s: timeout waiting for PORT_SUSPEND\n",
435                                                                 __func__);
436                 }
437         }
438
439         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
440                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
441
442         return 0;
443 }
444
445 static void usb_phy_wait_for_sof(struct tegra_usb_phy *phy)
446 {
447         unsigned long val;
448         void __iomem *base = phy->regs;
449
450         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
451         val = readl(base + USB_USBSTS);
452         writel(val, base + USB_USBSTS);
453         udelay(20);
454         /* wait for two SOFs */
455         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
456                 USB_USBSTS_SRI, 2500))
457                 pr_err("%s: timeout waiting for SOF\n", __func__);
458
459         val = readl(base + USB_USBSTS);
460         writel(val, base + USB_USBSTS);
461         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI, 0, 2500))
462                 pr_err("%s: timeout waiting for SOF\n", __func__);
463
464         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
465                         USB_USBSTS_SRI, 2500))
466                 pr_err("%s: timeout waiting for SOF\n", __func__);
467
468         udelay(20);
469 }
470
471 static unsigned int utmi_phy_xcvr_setup_value(struct tegra_usb_phy *phy)
472 {
473         struct tegra_utmi_config *cfg = &phy->pdata->u_cfg.utmi;
474         signed long val;
475
476         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
477         if (cfg->xcvr_use_fuses) {
478                 val = FUSE_USB_CALIB_XCVR_SETUP(
479                                 tegra_fuse_readl(FUSE_USB_CALIB_0));
480                 if (cfg->xcvr_setup_offset <= UTMIP_XCVR_MAX_OFFSET)
481                         val = val + cfg->xcvr_setup_offset;
482
483                 if (val > UTMIP_XCVR_SETUP_MAX_VALUE) {
484                         val = UTMIP_XCVR_SETUP_MAX_VALUE;
485                         pr_info("%s: reset XCVR_SETUP to max value\n",
486                                  __func__);
487                 } else if (val < UTMIP_XCVR_SETUP_MIN_VALUE) {
488                         val = UTMIP_XCVR_SETUP_MIN_VALUE;
489                         pr_info("%s: reset XCVR_SETUP to min value\n",
490                                  __func__);
491                 }
492         } else {
493                 val = cfg->xcvr_setup;
494         }
495
496         return (unsigned int) val;
497 }
498
499
500 static int utmi_phy_open(struct tegra_usb_phy *phy)
501 {
502         unsigned long parent_rate;
503         int i;
504
505         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
506         phy->utmi_pad_clk = clk_get_sys("utmip-pad", NULL);
507         if (IS_ERR(phy->utmi_pad_clk)) {
508                 pr_err("%s: can't get utmip pad clock\n", __func__);
509                 return PTR_ERR(phy->utmi_pad_clk);
510         }
511
512         phy->utmi_xcvr_setup = utmi_phy_xcvr_setup_value(phy);
513
514         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
515         for (i = 0; i < ARRAY_SIZE(utmip_freq_table); i++) {
516                 if (utmip_freq_table[i].freq == parent_rate) {
517                         phy->freq = &utmip_freq_table[i];
518                         break;
519                 }
520         }
521         if (!phy->freq) {
522                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
523                 return -EINVAL;
524         }
525
526         return 0;
527 }
528
529 static void utmi_phy_close(struct tegra_usb_phy *phy)
530 {
531         DBG("%s inst:[%d]\n", __func__, phy->inst);
532
533         clk_put(phy->utmi_pad_clk);
534 }
535
536 static int utmi_phy_pad_power_on(struct tegra_usb_phy *phy)
537 {
538         unsigned long val, flags;
539         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
540
541         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
542         clk_enable(phy->utmi_pad_clk);
543
544         spin_lock_irqsave(&utmip_pad_lock, flags);
545
546         utmip_pad_count++;
547         val = readl(pad_base + UTMIP_BIAS_CFG0);
548         val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
549         writel(val, pad_base + UTMIP_BIAS_CFG0);
550         utmip_pad_state_on = true;
551
552         spin_unlock_irqrestore(&utmip_pad_lock, flags);
553
554         clk_disable(phy->utmi_pad_clk);
555
556         return 0;
557 }
558
559 static int utmi_phy_pad_power_off(struct tegra_usb_phy *phy)
560 {
561         unsigned long val, flags;
562         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
563
564         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
565         clk_enable(phy->utmi_pad_clk);
566         spin_lock_irqsave(&utmip_pad_lock, flags);
567
568         if (!utmip_pad_count) {
569                 pr_err("%s: utmip pad already powered off\n", __func__);
570                 goto out;
571         }
572         if (--utmip_pad_count == 0) {
573                 val = readl(pad_base + UTMIP_BIAS_CFG0);
574                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
575                 writel(val, pad_base + UTMIP_BIAS_CFG0);
576                 utmip_pad_state_on = false;
577         }
578 out:
579         spin_unlock_irqrestore(&utmip_pad_lock, flags);
580         clk_disable(phy->utmi_pad_clk);
581
582         return 0;
583 }
584
585 static int utmi_phy_irq(struct tegra_usb_phy *phy)
586 {
587         void __iomem *base = phy->regs;
588         unsigned long val = 0;
589
590         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
591
592         usb_phy_fence_read(phy);
593         if (phy->pdata->u_data.host.hot_plug) {
594                 val = readl(base + USB_SUSP_CTRL);
595                 if ((val  & USB_PHY_CLK_VALID_INT_STS)) {
596                         val &= ~USB_PHY_CLK_VALID_INT_ENB |
597                                         USB_PHY_CLK_VALID_INT_STS;
598                         writel(val , (base + USB_SUSP_CTRL));
599                         pr_info("%s: usb device plugged-in\n", __func__);
600                         val = readl(base + USB_USBSTS);
601                         if (!(val  & USB_USBSTS_PCI))
602                                 return IRQ_NONE;
603                         val = readl(base + USB_PORTSC);
604                         val &= ~(USB_PORTSC_WKCN | USB_PORTSC_RWC_BITS);
605                         writel(val , (base + USB_PORTSC));
606                 }
607         }
608
609         return IRQ_HANDLED;
610 }
611
612 static void phy_post_suspend(struct tegra_usb_phy *phy)
613 {
614
615         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
616         /* Need a 4ms delay for controller to suspend */
617         mdelay(4);
618 }
619
620 static int utmi_phy_post_resume(struct tegra_usb_phy *phy)
621 {
622         unsigned long val;
623         void __iomem *base = phy->regs;
624
625         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
626
627         val = readl(base + UTMIP_TX_CFG0);
628         val &= ~UTMIP_HS_DISCON_DISABLE;
629         writel(val, base + UTMIP_TX_CFG0);
630         return 0;
631 }
632
633 static int utmi_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
634 {
635         unsigned long val;
636         void __iomem *base = phy->regs;
637
638         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
639         val = readl(base + UTMIP_TX_CFG0);
640         val |= UTMIP_HS_DISCON_DISABLE;
641         writel(val, base + UTMIP_TX_CFG0);
642
643         usb_phy_wait_for_sof(phy);
644
645         return 0;
646 }
647
648 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
649 {
650         unsigned long val;
651         void __iomem *base = phy->regs;
652
653         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
654         if (!phy->phy_clk_on) {
655                 DBG("%s(%d) inst:[%d] phy clk is already off\n",
656                                         __func__, __LINE__, phy->inst);
657                 return 0;
658         }
659
660         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
661                 val = readl(base + USB_SUSP_CTRL);
662                 val &= ~(USB_WAKEUP_DEBOUNCE_COUNT(~0));
663                 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
664                 writel(val, base + USB_SUSP_CTRL);
665
666                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
667                 val |= UTMIP_PD_CHRG;
668                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
669         }
670
671         if (!phy->pdata->u_data.host.hot_plug) {
672                 val = readl(base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
673                 val |= (UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
674                          UTMIP_FORCE_PDZI_POWERDOWN);
675                 writel(val, base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
676         }
677
678         val = readl(base + UTMIP_XCVR_CFG1);
679         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
680                    UTMIP_FORCE_PDDR_POWERDOWN;
681         writel(val, base + UTMIP_XCVR_CFG1);
682
683         if (phy->inst != 0) {
684                 val = readl(base + UTMIP_BIAS_CFG0);
685                 val |= UTMIP_OTGPD;
686                 writel(val, base + UTMIP_BIAS_CFG0);
687         }
688
689         phy->port_speed = (readl(base + USB_PORTSC) >> 26) &
690                         USB_PORTSC_PSPD_MASK;
691
692         if (phy->pdata->u_data.host.hot_plug) {
693                 bool enable_hotplug = true;
694                 /* if it is OTG port then make sure to enable hot-plug feature
695                    only if host adaptor is connected, i.e id is low */
696                 if (phy->pdata->port_otg) {
697                         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
698                         enable_hotplug = (val & USB_ID_STATUS) ? false : true;
699                 }
700                 if (enable_hotplug) {
701                         val = readl(base + USB_PORTSC);
702                         val |= USB_PORTSC_WKCN;
703                         writel(val, base + USB_PORTSC);
704
705                         val = readl(base + USB_SUSP_CTRL);
706                         val |= USB_PHY_CLK_VALID_INT_ENB;
707                         writel(val, base + USB_SUSP_CTRL);
708                 } else {
709                         /* Disable PHY clock valid interrupts while going into suspend*/
710                         val = readl(base + USB_SUSP_CTRL);
711                         val &= ~USB_PHY_CLK_VALID_INT_ENB;
712                         writel(val, base + USB_SUSP_CTRL);
713                 }
714         }
715
716         if (phy->inst == 2) {
717                 val = readl(base + USB_PORTSC);
718                 val |= USB_PORTSC_PHCD;
719                 writel(val, base + USB_PORTSC);
720         } else {
721                 val = readl(base + USB_SUSP_CTRL);
722                 val |= USB_SUSP_SET;
723                 writel(val, base + USB_SUSP_CTRL);
724                 udelay(10);
725                 val = readl(base + USB_SUSP_CTRL);
726                 val &= ~USB_SUSP_SET;
727                 writel(val, base + USB_SUSP_CTRL);
728         }
729
730         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
731                                                                 0, 2500))
732                 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
733
734         utmi_phy_pad_power_off(phy);
735
736         phy->phy_clk_on = false;
737         phy->hw_accessible = false;
738
739         DBG("%s(%d) inst:[%d]END\n", __func__, __LINE__, phy->inst);
740
741         return 0;
742 }
743
744 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
745 {
746         unsigned long val;
747         void __iomem *base = phy->regs;
748         struct tegra_utmi_config *config = &phy->pdata->u_cfg.utmi;
749         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
750         if (phy->phy_clk_on) {
751                 DBG("%s(%d) inst:[%d] phy clk is already on\n",
752                                         __func__, __LINE__, phy->inst);
753                 return 0;
754         }
755
756         val = readl(base + USB_SUSP_CTRL);
757         val |= UTMIP_RESET;
758         writel(val, base + USB_SUSP_CTRL);
759
760         val = readl(base + UTMIP_TX_CFG0);
761         val |= UTMIP_FS_PREABMLE_J;
762         writel(val, base + UTMIP_TX_CFG0);
763
764         val = readl(base + UTMIP_HSRX_CFG0);
765         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
766         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
767         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
768         writel(val, base + UTMIP_HSRX_CFG0);
769
770         val = readl(base + UTMIP_HSRX_CFG1);
771         val &= ~(UTMIP_HS_SYNC_START_DLY(~0));
772         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
773         writel(val, base + UTMIP_HSRX_CFG1);
774
775         val = readl(base + UTMIP_DEBOUNCE_CFG0);
776         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
777         val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
778         writel(val, base + UTMIP_DEBOUNCE_CFG0);
779
780         val = readl(base + UTMIP_MISC_CFG0);
781         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
782         writel(val, base + UTMIP_MISC_CFG0);
783
784         val = readl(base + UTMIP_MISC_CFG1);
785         val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) | UTMIP_PLLU_STABLE_COUNT(~0));
786         val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |
787                 UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count);
788         writel(val, base + UTMIP_MISC_CFG1);
789
790         val = readl(base + UTMIP_PLL_CFG1);
791         val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) | UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
792         val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |
793                 UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
794         writel(val, base + UTMIP_PLL_CFG1);
795
796         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
797                 val = readl(base + USB_SUSP_CTRL);
798                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
799                 writel(val, base + USB_SUSP_CTRL);
800
801                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
802                 val &= ~UTMIP_PD_CHRG;
803                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
804         } else {
805                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
806                 val |= UTMIP_PD_CHRG;
807                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
808         }
809
810         utmi_phy_pad_power_on(phy);
811
812         val = readl(base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
813         val &= ~(UTMIP_XCVR_LSBIAS_SEL | UTMIP_FORCE_PD_POWERDOWN |
814                  UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN |
815                  UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_LSFSLEW(~0) |
816                  UTMIP_XCVR_LSRSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
817         val |= UTMIP_XCVR_SETUP(phy->utmi_xcvr_setup);
818         val |= UTMIP_XCVR_SETUP_MSB(XCVR_SETUP_MSB_CALIB(phy->utmi_xcvr_setup));
819         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
820         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
821
822         writel(val, base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
823
824         val = readl(base + UTMIP_XCVR_CFG1);
825         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
826                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
827         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
828         writel(val, base + UTMIP_XCVR_CFG1);
829
830
831         val = readl(base + UTMIP_BIAS_CFG1);
832         val &= ~(UTMIP_BIAS_PDTRK_COUNT(~0));
833         val |= UTMIP_BIAS_PDTRK_COUNT(phy->freq->pdtrk_count);
834         writel(val, base + UTMIP_BIAS_CFG1);
835
836         val = readl(base + UTMIP_SPARE_CFG0);
837         val &= ~FUSE_SETUP_SEL;
838         writel(val, base + UTMIP_SPARE_CFG0);
839
840         val = readl(base + USB_SUSP_CTRL);
841         val |= UTMIP_PHY_ENABLE;
842         writel(val, base + USB_SUSP_CTRL);
843
844         val = readl(base + USB_SUSP_CTRL);
845         val &= ~UTMIP_RESET;
846         writel(val, base + USB_SUSP_CTRL);
847
848         if (phy->inst == 0) {
849                 val = readl(base + USB_SUSP_CTRL);
850                 val &= ~USB_SUSP_SET;
851                 writel(val, base + USB_SUSP_CTRL);
852         } else {
853                 val = readl(base + USB_PORTSC);
854                 val &= ~USB_PORTSC_PHCD;
855                 writel(val, base + USB_PORTSC);
856         }
857
858         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
859                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500))
860                 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
861
862         if (phy->inst == 2) {
863                 val = readl(base + USB_PORTSC);
864                 val &= ~(USB_PORTSC_PTS(~0));
865                 writel(val, base + USB_PORTSC);
866         }
867
868         phy->phy_clk_on = true;
869         phy->hw_accessible = true;
870
871         return 0;
872 }
873
874 static void utmi_phy_restore_start(struct tegra_usb_phy *phy)
875 {
876         unsigned long val;
877         void __iomem *base = phy->regs;
878
879         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
880         val = readl(base + UTMIP_MISC_CFG0);
881         val &= ~(UTMIP_DPDM_OBSERVE_SEL(~0));
882
883         if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
884                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
885         else
886                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
887         writel(val, base + UTMIP_MISC_CFG0);
888         udelay(1);
889
890         val = readl(base + UTMIP_MISC_CFG0);
891         val |= UTMIP_DPDM_OBSERVE;
892         writel(val, base + UTMIP_MISC_CFG0);
893         udelay(10);
894 }
895
896 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
897 {
898         unsigned long val;
899         void __iomem *base = phy->regs;
900
901         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
902         val = readl(base + UTMIP_MISC_CFG0);
903         val &= ~UTMIP_DPDM_OBSERVE;
904         writel(val, base + UTMIP_MISC_CFG0);
905         udelay(10);
906 }
907
908
909 static int utmi_phy_resume(struct tegra_usb_phy *phy)
910 {
911         int status = 0;
912         unsigned long val, flags;
913         void __iomem *base = phy->regs;
914         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
915
916         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
917         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) {
918                 if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
919                         utmi_phy_restore_start(phy);
920                         usb_phy_bringup_host_controller(phy);
921                         utmi_phy_restore_end(phy);
922                 } else {
923                         /* device is plugged in when system is in LP0 */
924                         /* bring up the controller from LP0*/
925                         val = readl(base + USB_USBCMD);
926                         val |= USB_USBCMD_RESET;
927                         writel(val, base + USB_USBCMD);
928
929                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
930                                 USB_USBCMD_RESET, 0, 2500) < 0) {
931                                 pr_err("%s: timeout waiting for reset\n", __func__);
932                         }
933
934                         val = readl(base + USB_USBMODE_REG_OFFSET);
935                         val &= ~USB_USBMODE_MASK;
936                         val |= USB_USBMODE_HOST;
937                         writel(val, base + USB_USBMODE_REG_OFFSET);
938
939                         if (phy->inst == 2) {
940                                 val = readl(base + USB_PORTSC);
941                                 val &= ~USB_PORTSC_PTS(~0);
942                                 writel(val, base + USB_PORTSC);
943                         }
944                         writel(USB_USBCMD_RS, base + USB_USBCMD);
945
946                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
947                                 USB_USBCMD_RS, USB_USBCMD_RS, 2500) < 0) {
948                                 pr_err("%s: timeout waiting for run bit\n", __func__);
949                         }
950
951                         /* Enable Port Power */
952                         val = readl(base + USB_PORTSC);
953                         val |= USB_PORTSC_PP;
954                         writel(val, base + USB_PORTSC);
955                         udelay(10);
956
957                         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
958                                 readl(base + USB_USBSTS), readl(base + USB_PORTSC));
959                 }
960         } else {
961                 /* Restoring the pad powers */
962                 clk_enable(phy->utmi_pad_clk);
963
964                 spin_lock_irqsave(&utmip_pad_lock, flags);
965
966                 val = readl(pad_base + UTMIP_BIAS_CFG0);
967                 if (utmip_pad_state_on)
968                         val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
969                 else
970                         val |= (UTMIP_OTGPD | UTMIP_BIASPD);
971                 writel(val, pad_base + UTMIP_BIAS_CFG0);
972
973                 spin_unlock_irqrestore(&utmip_pad_lock, flags);
974                 clk_disable(phy->utmi_pad_clk);
975         }
976
977         return status;
978 }
979
980 static bool utmi_phy_charger_detect(struct tegra_usb_phy *phy)
981 {
982         unsigned long val;
983         void __iomem *base = phy->regs;
984         bool status;
985
986         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
987         /* Enable charger detection logic */
988         val = readl(base + UTMIP_BAT_CHRG_CFG0);
989         val |= UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN;
990         writel(val, base + UTMIP_BAT_CHRG_CFG0);
991
992         /* Source should be on for 100 ms as per USB charging spec */
993         msleep(TDP_SRC_ON_MS);
994
995         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
996         /* If charger is not connected disable the interrupt */
997         val &= ~VDAT_DET_INT_EN;
998         val |= VDAT_DET_CHG_DET;
999         writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
1000
1001         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1002         if (val & VDAT_DET_STS)
1003                 status = true;
1004         else
1005                 status = false;
1006
1007         /* Disable charger detection logic */
1008         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1009         val &= ~(UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN);
1010         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1011
1012         /* Delay of 40 ms before we pull the D+ as per battery charger spec */
1013         msleep(TDPSRC_CON_MS);
1014
1015         return status;
1016 }
1017
1018
1019 static int uhsic_phy_open(struct tegra_usb_phy *phy)
1020 {
1021         unsigned long parent_rate;
1022         int i;
1023
1024         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1025         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
1026         for (i = 0; i < ARRAY_SIZE(uhsic_freq_table); i++) {
1027                 if (uhsic_freq_table[i].freq == parent_rate) {
1028                         phy->freq = &uhsic_freq_table[i];
1029                         break;
1030                 }
1031         }
1032         if (!phy->freq) {
1033                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
1034                 return -EINVAL;
1035         }
1036
1037         return 0;
1038 }
1039
1040 static int uhsic_phy_irq(struct tegra_usb_phy *phy)
1041 {
1042         usb_phy_fence_read(phy);
1043         return IRQ_HANDLED;
1044 }
1045
1046 static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
1047 {
1048         unsigned long val;
1049         void __iomem *base = phy->regs;
1050         struct tegra_hsic_config *config = &phy->pdata->u_cfg.hsic;
1051
1052         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1053         if (phy->phy_clk_on) {
1054                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
1055                                                         __LINE__, phy->inst);
1056                 return 0;
1057         }
1058
1059         val = readl(base + UHSIC_PADS_CFG1);
1060         val &= ~(UHSIC_PD_BG | UHSIC_PD_TX | UHSIC_PD_TRK | UHSIC_PD_RX |
1061                         UHSIC_PD_ZI | UHSIC_RPD_DATA | UHSIC_RPD_STROBE);
1062         val |= UHSIC_RX_SEL;
1063         writel(val, base + UHSIC_PADS_CFG1);
1064         udelay(2);
1065
1066         val = readl(base + USB_SUSP_CTRL);
1067         val |= UHSIC_RESET;
1068         writel(val, base + USB_SUSP_CTRL);
1069         udelay(30);
1070
1071         val = readl(base + USB_SUSP_CTRL);
1072         val |= UHSIC_PHY_ENABLE;
1073         writel(val, base + USB_SUSP_CTRL);
1074
1075         val = readl(base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
1076         val |= UHSIC_IDLE_WAIT(config->idle_wait_delay);
1077         val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(config->elastic_underrun_limit);
1078         val |= UHSIC_ELASTIC_OVERRUN_LIMIT(config->elastic_overrun_limit);
1079         writel(val, base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
1080
1081         val = readl(base + UHSIC_HSRX_CFG1);
1082         val |= UHSIC_HS_SYNC_START_DLY(config->sync_start_delay);
1083         writel(val, base + UHSIC_HSRX_CFG1);
1084
1085         val = readl(base + UHSIC_MISC_CFG0);
1086         val |= UHSIC_SUSPEND_EXIT_ON_EDGE;
1087         writel(val, base + UHSIC_MISC_CFG0);
1088
1089         val = readl(base + UHSIC_MISC_CFG1);
1090         val |= UHSIC_PLLU_STABLE_COUNT(phy->freq->stable_count);
1091         writel(val, base + UHSIC_MISC_CFG1);
1092
1093         val = readl(base + UHSIC_PLL_CFG1);
1094         val |= UHSIC_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
1095         val |= UHSIC_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count);
1096         writel(val, base + UHSIC_PLL_CFG1);
1097
1098         val = readl(base + USB_SUSP_CTRL);
1099         val &= ~(UHSIC_RESET);
1100         writel(val, base + USB_SUSP_CTRL);
1101         udelay(2);
1102
1103         val = readl(base + USB_PORTSC);
1104         val &= ~(USB_PORTSC_PTS(~0));
1105         writel(val, base + USB_PORTSC);
1106
1107         val = readl(base + USB_TXFILLTUNING);
1108         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
1109                 val = USB_FIFO_TXFILL_THRES(0x10);
1110                 writel(val, base + USB_TXFILLTUNING);
1111         }
1112
1113         val = readl(base + USB_PORTSC);
1114         val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN);
1115         writel(val, base + USB_PORTSC);
1116
1117         val = readl(base + UHSIC_PADS_CFG0);
1118         val &= ~(UHSIC_TX_RTUNEN);
1119         /* set Rtune impedance to 40 ohm */
1120         val |= UHSIC_TX_RTUNE(0);
1121         writel(val, base + UHSIC_PADS_CFG0);
1122
1123         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
1124                                                 USB_PHY_CLK_VALID, 2500)) {
1125                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
1126                 return -ETIMEDOUT;
1127         }
1128
1129         phy->phy_clk_on = true;
1130         phy->hw_accessible = true;
1131
1132         return 0;
1133 }
1134
1135 static int uhsic_phy_power_off(struct tegra_usb_phy *phy)
1136 {
1137         unsigned long val;
1138         void __iomem *base = phy->regs;
1139
1140         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1141         if (!phy->phy_clk_on) {
1142                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
1143                                                         __LINE__, phy->inst);
1144                 return 0;
1145         }
1146
1147         val = readl(base + UHSIC_PADS_CFG1);
1148         val &= ~UHSIC_RPU_STROBE;
1149         val |= UHSIC_RPD_STROBE;
1150         writel(val, base + UHSIC_PADS_CFG1);
1151
1152         val = readl(base + USB_SUSP_CTRL);
1153         val |= UHSIC_RESET;
1154         writel(val, base + USB_SUSP_CTRL);
1155         udelay(30);
1156
1157         val = readl(base + USB_SUSP_CTRL);
1158         val &= ~UHSIC_PHY_ENABLE;
1159         writel(val, base + USB_SUSP_CTRL);
1160
1161         phy->phy_clk_on = false;
1162         phy->hw_accessible = false;
1163
1164         return 0;
1165 }
1166
1167 static int uhsic_phy_bus_port_power(struct tegra_usb_phy *phy)
1168 {
1169         unsigned long val;
1170         void __iomem *base = phy->regs;
1171
1172         val = readl(base + UHSIC_MISC_CFG0);
1173         val |= UHSIC_DETECT_SHORT_CONNECT;
1174         writel(val, base + UHSIC_MISC_CFG0);
1175         udelay(1);
1176
1177         val = readl(base + UHSIC_MISC_CFG0);
1178         val |= UHSIC_FORCE_XCVR_MODE;
1179         writel(val, base + UHSIC_MISC_CFG0);
1180
1181         val = readl(base + UHSIC_PADS_CFG1);
1182         val &= ~UHSIC_RPD_STROBE;
1183         val |= UHSIC_RPU_STROBE;
1184         writel(val, base + UHSIC_PADS_CFG1);
1185
1186         val = readl(base + USB_USBCMD);
1187         val &= ~USB_USBCMD_RS;
1188         writel(val, base + USB_USBCMD);
1189
1190         if (phy->pdata->ops && phy->pdata->ops->port_power)
1191                 phy->pdata->ops->port_power();
1192
1193         if (usb_phy_reg_status_wait(base + UHSIC_STAT_CFG0,
1194                         UHSIC_CONNECT_DETECT, UHSIC_CONNECT_DETECT, 2000)) {
1195                 pr_err("%s: timeout waiting for UHSIC_CONNECT_DETECT\n",
1196                                                                 __func__);
1197                 return -ETIMEDOUT;
1198         }
1199
1200 /* FIXME : need to check whether this piece is required or not
1201         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_LS(2),
1202                                                 USB_PORTSC_LS(2), 2000)) {
1203                 pr_err("%s: timeout waiting for dplus state\n", __func__);
1204                 return -ETIMEDOUT;
1205         }
1206 */
1207         return 0;
1208 }
1209
1210
1211 static int uhsic_phy_bus_reset(struct tegra_usb_phy *phy)
1212 {
1213         unsigned long val;
1214         void __iomem *base = phy->regs;
1215
1216         val = readl(base + USB_PORTSC);
1217         val |= USB_PORTSC_PTC(5);
1218         writel(val, base + USB_PORTSC);
1219         udelay(2);
1220
1221         val = readl(base + USB_PORTSC);
1222         val &= ~(USB_PORTSC_PTC(~0));
1223         writel(val, base + USB_PORTSC);
1224         udelay(2);
1225
1226         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_LS(0),
1227                                                  0, 2000)) {
1228                 pr_err("%s: timeout waiting for USB_PORTSC_LS\n", __func__);
1229                 return -ETIMEDOUT;
1230         }
1231
1232         /* Poll until CCS is enabled */
1233         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
1234                                                  USB_PORTSC_CCS, 2000)) {
1235                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
1236                 return -ETIMEDOUT;
1237         }
1238
1239         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_PSPD(2),
1240                                                  USB_PORTSC_PSPD(2), 2000)) {
1241                 pr_err("%s: timeout waiting for USB_PORTSC_PSPD\n", __func__);
1242                 return -ETIMEDOUT;
1243         }
1244
1245         val = readl(base + USB_USBCMD);
1246         val &= ~USB_USBCMD_RS;
1247         writel(val, base + USB_USBCMD);
1248
1249         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
1250                                                  USB_USBSTS_HCH, 2000)) {
1251                 pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
1252                 return -ETIMEDOUT;
1253         }
1254
1255         val = readl(base + UHSIC_PADS_CFG1);
1256         val &= ~UHSIC_RPU_STROBE;
1257         val |= UHSIC_RPD_STROBE;
1258         writel(val, base + UHSIC_PADS_CFG1);
1259
1260         mdelay(50);
1261
1262         val = readl(base + UHSIC_PADS_CFG1);
1263         val &= ~UHSIC_RPD_STROBE;
1264         val |= UHSIC_RPU_STROBE;
1265         writel(val, base + UHSIC_PADS_CFG1);
1266
1267         val = readl(base + USB_USBCMD);
1268         val |= USB_USBCMD_RS;
1269         writel(val, base + USB_USBCMD);
1270
1271         val = readl(base + UHSIC_PADS_CFG1);
1272         val &= ~UHSIC_RPU_STROBE;
1273         writel(val, base + UHSIC_PADS_CFG1);
1274
1275         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
1276                                                  USB_USBCMD_RS, 2000)) {
1277                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
1278                 return -ETIMEDOUT;
1279         }
1280
1281         return 0;
1282 }
1283
1284
1285 static int uhsic_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1286 {
1287         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1288         usb_phy_wait_for_sof(phy);
1289
1290         return 0;
1291 }
1292
1293 static int uhsic_phy_resume(struct tegra_usb_phy *phy)
1294 {
1295         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1296         uhsic_phy_bus_port_power(phy);
1297
1298         return 0;
1299 }
1300
1301
1302 static int uhsic_phy_post_resume(struct tegra_usb_phy *phy)
1303 {
1304         unsigned long val;
1305         void __iomem *base = phy->regs;
1306
1307         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1308         val = readl(base + USB_TXFILLTUNING);
1309         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
1310                 val = USB_FIFO_TXFILL_THRES(0x10);
1311                 writel(val, base + USB_TXFILLTUNING);
1312         }
1313
1314         return 0;
1315 }
1316
1317 static void ulpi_set_trimmer(struct tegra_usb_phy *phy)
1318 {
1319         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
1320         void __iomem *base = phy->regs;
1321         unsigned long val;
1322
1323         val = ULPI_DATA_TRIMMER_SEL(config->data_trimmer);
1324         val |= ULPI_STPDIRNXT_TRIMMER_SEL(config->stpdirnxt_trimmer);
1325         val |= ULPI_DIR_TRIMMER_SEL(config->dir_trimmer);
1326         writel(val, base + ULPI_TIMING_CTRL_1);
1327         udelay(10);
1328
1329         val |= ULPI_DATA_TRIMMER_LOAD;
1330         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
1331         val |= ULPI_DIR_TRIMMER_LOAD;
1332         writel(val, base + ULPI_TIMING_CTRL_1);
1333 }
1334
1335
1336 static int ulpi_link_phy_open(struct tegra_usb_phy *phy)
1337 {
1338         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
1339         int err = 0;
1340
1341         phy->ulpi_clk = NULL;
1342
1343         if (config->clk) {
1344                 phy->ulpi_clk = clk_get_sys(NULL, config->clk);
1345                 if (IS_ERR(phy->ulpi_clk)) {
1346                         pr_err("%s: can't get ulpi clock\n", __func__);
1347                         err = -ENXIO;
1348                 }
1349         }
1350
1351         phy->ulpi_vp = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
1352         phy->ulpi_vp->io_priv = phy->regs + ULPI_VIEWPORT;
1353
1354         return err;
1355 }
1356
1357 static void ulpi_link_phy_close(struct tegra_usb_phy *phy)
1358 {
1359         DBG("%s inst:[%d]\n", __func__, phy->inst);
1360         if (phy->ulpi_clk)
1361                 clk_put(phy->ulpi_clk);
1362 }
1363
1364 static int ulpi_link_phy_irq(struct tegra_usb_phy *phy)
1365 {
1366         usb_phy_fence_read(phy);
1367         return IRQ_HANDLED;
1368 }
1369
1370 static int ulpi_link_phy_power_off(struct tegra_usb_phy *phy)
1371 {
1372         unsigned long val;
1373         void __iomem *base = phy->regs;
1374         int ret;
1375
1376         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1377         if (!phy->phy_clk_on) {
1378                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
1379                                                         __LINE__, phy->inst);
1380                 return 0;
1381         }
1382
1383         /* Disable VbusValid, SessEnd comparators */
1384         ret = usb_phy_io_write(phy->ulpi_vp, 0x00, 0x0D);
1385         if (ret)
1386                 pr_err("%s: ulpi write 0x0D failed\n", __func__);
1387
1388         ret = usb_phy_io_write(phy->ulpi_vp, 0x00, 0x10);
1389         if (ret)
1390                 pr_err("%s: ulpi write 0x10 failed\n", __func__);
1391
1392         /* Disable IdFloat comparator */
1393         ret = usb_phy_io_write(phy->ulpi_vp, 0x00, 0x19);
1394         if (ret)
1395                 pr_err("%s: ulpi write 0x19 failed\n", __func__);
1396
1397         ret = usb_phy_io_write(phy->ulpi_vp, 0x00, 0x1D);
1398         if (ret)
1399                 pr_err("%s: ulpi write 0x1D failed\n", __func__);
1400
1401         phy->port_speed = (readl(base + USB_PORTSC) >> 26) &
1402                         USB_PORTSC_PSPD_MASK;
1403
1404         /* Clear WKCN/WKDS/WKOC wake-on events that can cause the USB
1405          * Controller to immediately bring the ULPI PHY out of low power
1406          */
1407         val = readl(base + USB_PORTSC);
1408         val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN);
1409         writel(val, base + USB_PORTSC);
1410
1411         /* Put the PHY in the low power mode */
1412         val = readl(base + USB_PORTSC);
1413         val |= USB_PORTSC_PHCD;
1414         writel(val, base + USB_PORTSC);
1415
1416         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
1417                                                          0, 2500)) {
1418                 pr_err("%s: timeout waiting for phy to stop\n", __func__);
1419         }
1420
1421         if (phy->ulpi_clk)
1422                 clk_disable(phy->ulpi_clk);
1423
1424         phy->phy_clk_on = false;
1425         phy->hw_accessible = false;
1426
1427         return 0;
1428 }
1429
1430 static int ulpi_link_phy_power_on(struct tegra_usb_phy *phy)
1431 {
1432         int ret;
1433         unsigned long val;
1434         void __iomem *base = phy->regs;
1435
1436         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1437         if (phy->phy_clk_on) {
1438                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
1439                                                         __LINE__, phy->inst);
1440                 return 0;
1441         }
1442
1443         if (phy->ulpi_clk) {
1444                 clk_enable(phy->ulpi_clk);
1445                 mdelay(1);
1446         }
1447
1448         val = readl(base + USB_SUSP_CTRL);
1449         val |= UHSIC_RESET;
1450         writel(val, base + USB_SUSP_CTRL);
1451
1452         val = readl(base + ULPI_TIMING_CTRL_0);
1453         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
1454         writel(val, base + ULPI_TIMING_CTRL_0);
1455
1456         val = readl(base + USB_SUSP_CTRL);
1457         val |= ULPI_PHY_ENABLE;
1458         writel(val, base + USB_SUSP_CTRL);
1459
1460         val = readl(base + USB_SUSP_CTRL);
1461         val |= USB_SUSP_CLR;
1462         writel(val, base + USB_SUSP_CTRL);
1463
1464         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
1465                                                 USB_PHY_CLK_VALID, 2500))
1466                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
1467
1468         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_CLKEN,
1469                                                 USB_CLKEN, 2500))
1470                 pr_err("%s: timeout waiting for AHB clock\n", __func__);
1471
1472         val = readl(base + USB_SUSP_CTRL);
1473         val &= ~USB_SUSP_CLR;
1474         writel(val, base + USB_SUSP_CTRL);
1475
1476         val = 0;
1477         writel(val, base + ULPI_TIMING_CTRL_1);
1478
1479         ulpi_set_trimmer(phy);
1480
1481         /* Fix VbusInvalid due to floating VBUS */
1482         ret = usb_phy_io_write(phy->ulpi_vp, 0x40, 0x08);
1483         if (ret) {
1484                 pr_err("%s: ulpi write failed\n", __func__);
1485                 return ret;
1486         }
1487
1488         ret = usb_phy_io_write(phy->ulpi_vp, 0x80, 0x0B);
1489         if (ret) {
1490                 pr_err("%s: ulpi write failed\n", __func__);
1491                 return ret;
1492         }
1493
1494         val = readl(base + USB_PORTSC);
1495         val |= USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN;
1496         writel(val, base + USB_PORTSC);
1497
1498         phy->phy_clk_on = true;
1499         phy->hw_accessible = true;
1500
1501         return 0;
1502 }
1503
1504 static inline void ulpi_link_phy_set_tristate(bool enable)
1505 {
1506 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1507         int tristate = (enable) ? TEGRA_TRI_TRISTATE : TEGRA_TRI_NORMAL;
1508
1509         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAA, tristate);
1510         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAB, tristate);
1511         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UDA, tristate);
1512 #endif
1513 }
1514
1515 static void ulpi_link_phy_restore_start(struct tegra_usb_phy *phy)
1516 {
1517         unsigned long val;
1518         void __iomem *base = phy->regs;
1519
1520         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1521
1522         /*Tristate ulpi interface before USB controller resume*/
1523         ulpi_link_phy_set_tristate(true);
1524
1525         val = readl(base + ULPI_TIMING_CTRL_0);
1526         val &= ~ULPI_OUTPUT_PINMUX_BYP;
1527         writel(val, base + ULPI_TIMING_CTRL_0);
1528 }
1529
1530 static void ulpi_link_phy_restore_end(struct tegra_usb_phy *phy)
1531 {
1532         unsigned long val;
1533         void __iomem *base = phy->regs;
1534
1535         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1536
1537         val = readl(base + ULPI_TIMING_CTRL_0);
1538         val |= ULPI_OUTPUT_PINMUX_BYP;
1539         writel(val, base + ULPI_TIMING_CTRL_0);
1540
1541         ulpi_link_phy_set_tristate(false);
1542 }
1543
1544 static int ulpi_link_phy_resume(struct tegra_usb_phy *phy)
1545 {
1546         int status = 0;
1547
1548         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1549         if (phy->pdata->u_data.host.power_off_on_suspend) {
1550                 status = ulpi_link_phy_power_on(phy);
1551                 if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
1552                         ulpi_link_phy_restore_start(phy);
1553                         usb_phy_bringup_host_controller(phy);
1554                         ulpi_link_phy_restore_end(phy);
1555                 }
1556         }
1557
1558         return status;
1559 }
1560
1561
1562 static int ulpi_null_phy_power_off(struct tegra_usb_phy *phy)
1563 {
1564         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1565
1566         if (!phy->phy_clk_on) {
1567                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
1568                                                         __LINE__, phy->inst);
1569                 return 0;
1570         }
1571
1572         phy->phy_clk_on = false;
1573         phy->hw_accessible = false;
1574
1575         return 0;
1576 }
1577
1578 static int ulpi_null_phy_irq(struct tegra_usb_phy *phy)
1579 {
1580         usb_phy_fence_read(phy);
1581         return IRQ_HANDLED;
1582 }
1583
1584 static int ulpi_null_phy_lp0_resume(struct tegra_usb_phy *phy)
1585 {
1586         unsigned long val;
1587         void __iomem *base = phy->regs;
1588
1589         val = readl(base + USB_USBCMD);
1590         val |= USB_USBCMD_RESET;
1591         writel(val, base + USB_USBCMD);
1592
1593         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1594                 USB_USBCMD_RESET, 0, 2500) < 0) {
1595                 pr_err("%s: timeout waiting for reset\n", __func__);
1596         }
1597
1598         val = readl(base + USB_USBMODE_REG_OFFSET);
1599         val &= ~USB_USBMODE_MASK;
1600         val |= USB_USBMODE_HOST;
1601         writel(val, base + USB_USBMODE_REG_OFFSET);
1602
1603         val = readl(base + USB_USBCMD);
1604         val |= USB_USBCMD_RS;
1605         writel(val, base + USB_USBCMD);
1606         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
1607                                                  USB_USBCMD_RS, 2000)) {
1608                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
1609                 return -ETIMEDOUT;
1610         }
1611
1612         /* Enable Port Power */
1613         val = readl(base + USB_PORTSC);
1614         val |= USB_PORTSC_PP;
1615         writel(val, base + USB_PORTSC);
1616         udelay(10);
1617
1618         /* disable ULPI pinmux bypass */
1619         val = readl(base + ULPI_TIMING_CTRL_0);
1620         val &= ~ULPI_OUTPUT_PINMUX_BYP;
1621         writel(val, base + ULPI_TIMING_CTRL_0);
1622
1623         return 0;
1624 }
1625
1626 static int ulpi_null_phy_power_on(struct tegra_usb_phy *phy)
1627 {
1628         unsigned long val;
1629         void __iomem *base = phy->regs;
1630         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
1631         static bool cold_boot = true;
1632
1633         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1634         if (phy->phy_clk_on) {
1635                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
1636                                                         __LINE__, phy->inst);
1637                 return 0;
1638         }
1639
1640         val = readl(base + USB_SUSP_CTRL);
1641         val |= UHSIC_RESET;
1642         writel(val, base + USB_SUSP_CTRL);
1643
1644         val = readl(base + ULPI_TIMING_CTRL_0);
1645         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
1646         writel(val, base + ULPI_TIMING_CTRL_0);
1647
1648         val = readl(base + USB_SUSP_CTRL);
1649         val |= ULPI_PHY_ENABLE;
1650         writel(val, base + USB_SUSP_CTRL);
1651         udelay(10);
1652
1653         /* set timming parameters */
1654         val = readl(base + ULPI_TIMING_CTRL_0);
1655         val |= ULPI_SHADOW_CLK_LOOPBACK_EN;
1656         val |= ULPI_SHADOW_CLK_SEL;
1657         val |= ULPI_LBK_PAD_EN;
1658         val |= ULPI_SHADOW_CLK_DELAY(config->shadow_clk_delay);
1659         val |= ULPI_CLOCK_OUT_DELAY(config->clock_out_delay);
1660         val |= ULPI_LBK_PAD_E_INPUT_OR;
1661         writel(val, base + ULPI_TIMING_CTRL_0);
1662
1663         writel(0, base + ULPI_TIMING_CTRL_1);
1664         udelay(10);
1665
1666         /* start internal 60MHz clock */
1667         val = readl(base + ULPIS2S_CTRL);
1668         val |= ULPIS2S_ENA;
1669         val |= ULPIS2S_SUPPORT_DISCONNECT;
1670         val |= ULPIS2S_SPARE((phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) ? 3 : 1);
1671         val |= ULPIS2S_PLLU_MASTER_BLASTER60;
1672         writel(val, base + ULPIS2S_CTRL);
1673
1674         /* select ULPI_CORE_CLK_SEL to SHADOW_CLK */
1675         val = readl(base + ULPI_TIMING_CTRL_0);
1676         val |= ULPI_CORE_CLK_SEL;
1677         writel(val, base + ULPI_TIMING_CTRL_0);
1678         udelay(10);
1679
1680         /* enable ULPI null phy clock - can't set the trimmers before this */
1681         val = readl(base + ULPI_TIMING_CTRL_0);
1682         val |= ULPI_CLK_OUT_ENA;
1683         writel(val, base + ULPI_TIMING_CTRL_0);
1684         udelay(10);
1685
1686         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
1687                                                  USB_PHY_CLK_VALID, 2500)) {
1688                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
1689                 return -ETIMEDOUT;
1690         }
1691
1692         /* set ULPI trimmers */
1693         ulpi_set_trimmer(phy);
1694
1695         if (cold_boot) {
1696                 val = readl(base + ULPI_TIMING_CTRL_0);
1697                 val |= ULPI_CLK_PADOUT_ENA;
1698                 writel(val, base + ULPI_TIMING_CTRL_0);
1699                 cold_boot = false;
1700         } else {
1701                 if (!readl(base + USB_ASYNCLISTADDR))
1702                         ulpi_null_phy_lp0_resume(phy);
1703         }
1704         udelay(10);
1705
1706         phy->phy_clk_on = true;
1707         phy->hw_accessible = true;
1708
1709         return 0;
1710 }
1711
1712
1713 static int ulpi_null_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1714 {
1715         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1716
1717         usb_phy_wait_for_sof(phy);
1718         return 0;
1719 }
1720
1721 static int ulpi_null_phy_resume(struct tegra_usb_phy *phy)
1722 {
1723         unsigned long val;
1724         void __iomem *base = phy->regs;
1725
1726         if (!readl(base + USB_ASYNCLISTADDR)) {
1727                 /* enable ULPI CLK output pad */
1728                 val = readl(base + ULPI_TIMING_CTRL_0);
1729                 val |= ULPI_CLK_PADOUT_ENA;
1730                 writel(val, base + ULPI_TIMING_CTRL_0);
1731
1732                 /* enable ULPI pinmux bypass */
1733                 val = readl(base + ULPI_TIMING_CTRL_0);
1734                 val |= ULPI_OUTPUT_PINMUX_BYP;
1735                 writel(val, base + ULPI_TIMING_CTRL_0);
1736                 udelay(5);
1737         }
1738
1739         return 0;
1740 }
1741
1742
1743
1744 static struct tegra_usb_phy_ops utmi_phy_ops = {
1745         .open           = utmi_phy_open,
1746         .close          = utmi_phy_close,
1747         .irq            = utmi_phy_irq,
1748         .power_on       = utmi_phy_power_on,
1749         .power_off      = utmi_phy_power_off,
1750         .pre_resume = utmi_phy_pre_resume,
1751         .resume = utmi_phy_resume,
1752         .post_resume    = utmi_phy_post_resume,
1753         .charger_detect = utmi_phy_charger_detect,
1754         .post_suspend   = phy_post_suspend,
1755 };
1756
1757 static struct tegra_usb_phy_ops uhsic_phy_ops = {
1758         .open           = uhsic_phy_open,
1759         .irq            = uhsic_phy_irq,
1760         .power_on       = uhsic_phy_power_on,
1761         .power_off      = uhsic_phy_power_off,
1762         .pre_resume     = uhsic_phy_pre_resume,
1763         .resume         = uhsic_phy_resume,
1764         .post_resume    = uhsic_phy_post_resume,
1765         .port_power     = uhsic_phy_bus_port_power,
1766         .bus_reset      = uhsic_phy_bus_reset,
1767         .post_suspend   = phy_post_suspend,
1768 };
1769
1770 static struct tegra_usb_phy_ops ulpi_link_phy_ops = {
1771         .open           = ulpi_link_phy_open,
1772         .close  = ulpi_link_phy_close,
1773         .irq            = ulpi_link_phy_irq,
1774         .power_on       = ulpi_link_phy_power_on,
1775         .power_off      = ulpi_link_phy_power_off,
1776         .resume         = ulpi_link_phy_resume,
1777         .post_suspend   = phy_post_suspend,
1778 };
1779
1780 static struct tegra_usb_phy_ops ulpi_null_phy_ops = {
1781         .irq            = ulpi_null_phy_irq,
1782         .power_on       = ulpi_null_phy_power_on,
1783         .power_off      = ulpi_null_phy_power_off,
1784         .pre_resume = ulpi_null_phy_pre_resume,
1785         .resume = ulpi_null_phy_resume,
1786         .post_suspend   = phy_post_suspend,
1787 };
1788
1789 static struct tegra_usb_phy_ops icusb_phy_ops;
1790
1791
1792 static struct tegra_usb_phy_ops *phy_ops[] = {
1793         [TEGRA_USB_PHY_INTF_UTMI] = &utmi_phy_ops,
1794         [TEGRA_USB_PHY_INTF_ULPI_LINK] = &ulpi_link_phy_ops,
1795         [TEGRA_USB_PHY_INTF_ULPI_NULL] = &ulpi_null_phy_ops,
1796         [TEGRA_USB_PHY_INTF_HSIC] = &uhsic_phy_ops,
1797         [TEGRA_USB_PHY_INTF_ICUSB] = &icusb_phy_ops,
1798 };
1799
1800 int tegra2_usb_phy_init_ops(struct tegra_usb_phy *phy)
1801 {
1802         phy->ops = phy_ops[phy->pdata->phy_intf];
1803
1804         return 0;
1805 }