39e2899f018c248ef431524771f090d2af94f322
[linux-2.6.git] / arch / arm / mach-tegra / tegra2_usb_phy.c
1 /*
2  * arch/arm/mach-tegra/tegra2_usb_phy.c
3  *
4  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
5  *
6  *
7  * This software is licensed under the terms of the GNU General Public
8  * License version 2, as published by the Free Software Foundation, and
9  * may be copied, distributed, and modified under those terms.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17 #include <linux/resource.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/slab.h>
21 #include <linux/err.h>
22 #include <linux/platform_device.h>
23 #include <linux/io.h>
24 #include <linux/gpio.h>
25 #include <linux/usb/otg.h>
26 #include <linux/usb/ulpi.h>
27 #include <linux/interrupt.h>
28 #include <linux/clk.h>
29 #include <linux/regulator/consumer.h>
30 #include <linux/platform_data/tegra_usb.h>
31
32 #include <asm/mach-types.h>
33
34 #include <mach/clk.h>
35 #include <mach/iomap.h>
36 #include <mach/pinmux.h>
37 #include <mach/pinmux-tegra20.h>
38 #include <mach/usb_phy.h>
39
40 #include "tegra_usb_phy.h"
41 #include "gpio-names.h"
42 #include "fuse.h"
43
44 #define USB_USBCMD              0x140
45 #define   USB_USBCMD_RS         (1 << 0)
46 #define   USB_USBCMD_RESET      (1 << 1)
47
48 #define USB_USBSTS              0x144
49 #define   USB_USBSTS_PCI        (1 << 2)
50 #define   USB_USBSTS_SRI        (1 << 7)
51 #define   USB_USBSTS_HCH        (1 << 12)
52
53 #define USB_ASYNCLISTADDR       0x158
54
55 #define USB_TXFILLTUNING                0x164
56 #define USB_FIFO_TXFILL_THRES(x)   (((x) & 0x1f) << 16)
57 #define USB_FIFO_TXFILL_MASK    0x1f0000
58
59 #define ULPI_VIEWPORT           0x170
60 #define   ULPI_WAKEUP           (1 << 31)
61 #define   ULPI_RUN              (1 << 30)
62 #define   ULPI_RD_WR            (1 << 29)
63
64 #define USB_PORTSC              0x184
65 #define   USB_PORTSC_PTS(x)     (((x) & 0x3) << 30)
66 #define   USB_PORTSC_PSPD(x)    (((x) & 0x3) << 26)
67 #define   USB_PORTSC_PHCD       (1 << 23)
68 #define   USB_PORTSC_WKOC       (1 << 22)
69 #define   USB_PORTSC_WKDS       (1 << 21)
70 #define   USB_PORTSC_WKCN       (1 << 20)
71 #define   USB_PORTSC_PTC(x)     (((x) & 0xf) << 16)
72 #define   USB_PORTSC_PP (1 << 12)
73 #define   USB_PORTSC_LS(x) (((x) & 0x3) << 10)
74 #define   USB_PORTSC_SUSP       (1 << 7)
75 #define   USB_PORTSC_OCC        (1 << 5)
76 #define   USB_PORTSC_PEC        (1 << 3)
77 #define   USB_PORTSC_PE         (1 << 2)
78 #define   USB_PORTSC_CSC        (1 << 1)
79 #define   USB_PORTSC_CCS        (1 << 0)
80 #define   USB_PORTSC_RWC_BITS (USB_PORTSC_CSC | USB_PORTSC_PEC | USB_PORTSC_OCC)
81 #define   USB_PORTSC_PSPD_MASK  3
82
83 #define USB_USBMODE_REG_OFFSET  0x1a8
84 #define   USB_USBMODE_MASK              (3 << 0)
85 #define   USB_USBMODE_HOST              (3 << 0)
86 #define   USB_USBMODE_DEVICE    (2 << 0)
87
88 #define USB_SUSP_CTRL           0x400
89 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
90 #define   USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
91 #define   USB_SUSP_CLR          (1 << 5)
92 #define   USB_CLKEN             (1 << 6)
93 #define   USB_PHY_CLK_VALID (1 << 7)
94 #define   USB_PHY_CLK_VALID_INT_ENB    (1 << 9)
95 #define   UTMIP_RESET           (1 << 11)
96 #define   UHSIC_RESET           (1 << 11)
97 #define   UTMIP_PHY_ENABLE      (1 << 12)
98 #define   UHSIC_PHY_ENABLE      (1 << 12)
99 #define   ULPI_PHY_ENABLE       (1 << 13)
100 #define   USB_SUSP_SET          (1 << 14)
101 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
102 #define   USB_PHY_CLK_VALID_INT_STS     (1 << 8)
103
104 #define USB_PHY_VBUS_WAKEUP_ID  0x408
105 #define   VDAT_DET_INT_EN       (1 << 16)
106 #define   VDAT_DET_CHG_DET      (1 << 17)
107 #define   VDAT_DET_STS          (1 << 18)
108 #define   USB_ID_STATUS         (1 << 2)
109
110 #define USB1_LEGACY_CTRL        0x410
111 #define   USB1_NO_LEGACY_MODE                   (1 << 0)
112 #define   USB1_VBUS_SENSE_CTL_MASK              (3 << 1)
113 #define   USB1_VBUS_SENSE_CTL_VBUS_WAKEUP       (0 << 1)
114 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
115                                                 (1 << 1)
116 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD       (2 << 1)
117 #define   USB1_VBUS_SENSE_CTL_A_SESS_VLD        (3 << 1)
118
119 #define ULPIS2S_CTRL            0x418
120 #define   ULPIS2S_ENA                   (1 << 0)
121 #define   ULPIS2S_SUPPORT_DISCONNECT    (1 << 2)
122 #define   ULPIS2S_PLLU_MASTER_BLASTER60 (1 << 3)
123 #define   ULPIS2S_SPARE(x)              (((x) & 0xF) << 8)
124 #define   ULPIS2S_FORCE_ULPI_CLK_OUT    (1 << 12)
125 #define   ULPIS2S_DISCON_DONT_CHECK_SE0 (1 << 13)
126 #define   ULPIS2S_SUPPORT_HS_KEEP_ALIVE (1 << 14)
127 #define   ULPIS2S_DISABLE_STP_PU        (1 << 15)
128 #define   ULPIS2S_SLV0_CLAMP_XMIT       (1 << 16)
129
130 #define ULPI_TIMING_CTRL_0      0x424
131 #define   ULPI_CLOCK_OUT_DELAY(x)       ((x) & 0x1F)
132 #define   ULPI_OUTPUT_PINMUX_BYP        (1 << 10)
133 #define   ULPI_CLKOUT_PINMUX_BYP        (1 << 11)
134 #define   ULPI_SHADOW_CLK_LOOPBACK_EN   (1 << 12)
135 #define   ULPI_SHADOW_CLK_SEL           (1 << 13)
136 #define   ULPI_CORE_CLK_SEL             (1 << 14)
137 #define   ULPI_SHADOW_CLK_DELAY(x)      (((x) & 0x1F) << 16)
138 #define   ULPI_LBK_PAD_EN               (1 << 26)
139 #define   ULPI_LBK_PAD_E_INPUT_OR       (1 << 27)
140 #define   ULPI_CLK_OUT_ENA              (1 << 28)
141 #define   ULPI_CLK_PADOUT_ENA           (1 << 29)
142
143 #define ULPI_TIMING_CTRL_1      0x428
144 #define   ULPI_DATA_TRIMMER_LOAD        (1 << 0)
145 #define   ULPI_DATA_TRIMMER_SEL(x)      (((x) & 0x7) << 1)
146 #define   ULPI_STPDIRNXT_TRIMMER_LOAD   (1 << 16)
147 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
148 #define   ULPI_DIR_TRIMMER_LOAD         (1 << 24)
149 #define   ULPI_DIR_TRIMMER_SEL(x)       (((x) & 0x7) << 25)
150
151 #define UTMIP_PLL_CFG1          0x804
152 #define UHSIC_PLL_CFG1                          0x804
153 #define   UTMIP_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
154 #define   UTMIP_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 27)
155 #define   UHSIC_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
156 #define   UHSIC_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 14)
157
158 #define UTMIP_XCVR_UHSIC_HSRX_CFG0              0x808
159 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
160 #define   UHSIC_ELASTIC_UNDERRUN_LIMIT(x)       (((x) & 0x1f) << 2)
161 #define   UHSIC_ELASTIC_OVERRUN_LIMIT(x)        (((x) & 0x1f) << 8)
162 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
163 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
164 #define   UHSIC_IDLE_WAIT(x)                    (((x) & 0x1f) << 13)
165 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
166 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
167 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
168 #define   UTMIP_XCVR_LSBIAS_SEL                 (1 << 21)
169 #define   UTMIP_XCVR_SETUP_MSB(x)               (((x) & 0x7) << 22)
170 #define   UTMIP_XCVR_HSSLEW_MSB(x)              (((x) & 0x7f) << 25)
171 #define   UTMIP_XCVR_MAX_OFFSET         2
172 #define   UTMIP_XCVR_SETUP_MAX_VALUE    0x7f
173 #define   UTMIP_XCVR_SETUP_MIN_VALUE    0
174 #define   XCVR_SETUP_MSB_CALIB(x) ((x) >> 4)
175
176 #define UTMIP_BIAS_CFG0                 0x80c
177 #define   UTMIP_OTGPD                   (1 << 11)
178 #define   UTMIP_BIASPD                  (1 << 10)
179
180 #define UHSIC_HSRX_CFG1                         0x80c
181 #define   UHSIC_HS_SYNC_START_DLY(x)            (((x) & 0x1f) << 1)
182
183 #define UTMIP_HSRX_CFG0                 0x810
184 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
185 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
186
187 #define UTMIP_HSRX_CFG1                 0x814
188 #define UHSIC_MISC_CFG0                 0x814
189 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
190 #define   UHSIC_SUSPEND_EXIT_ON_EDGE            (1 << 7)
191 #define   UHSIC_DETECT_SHORT_CONNECT            (1 << 8)
192 #define   UHSIC_FORCE_XCVR_MODE                 (1 << 15)
193
194 #define UHSIC_MISC_CFG1                         0x818
195 #define   UHSIC_PLLU_STABLE_COUNT(x)            (((x) & 0xfff) << 2)
196
197 #define UHSIC_PADS_CFG0                         0x81c
198 #define   UHSIC_TX_RTUNEN                       0xf000
199 #define   UHSIC_TX_RTUNE(x)                     (((x) & 0xf) << 12)
200
201 #define UTMIP_TX_CFG0                           0x820
202 #define UHSIC_PADS_CFG1                         0x820
203 #define   UHSIC_PD_BG                           (1 << 2)
204 #define   UHSIC_PD_TX                           (1 << 3)
205 #define   UHSIC_PD_TRK                          (1 << 4)
206 #define   UHSIC_PD_RX                           (1 << 5)
207 #define   UHSIC_PD_ZI                           (1 << 6)
208 #define   UHSIC_RX_SEL                          (1 << 7)
209 #define   UHSIC_RPD_DATA                        (1 << 9)
210 #define   UHSIC_RPD_STROBE                      (1 << 10)
211 #define   UHSIC_RPU_DATA                        (1 << 11)
212 #define   UHSIC_RPU_STROBE                      (1 << 12)
213 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
214 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
215
216 #define UTMIP_MISC_CFG0         0x824
217 #define   UTMIP_DPDM_OBSERVE            (1 << 26)
218 #define   UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
219 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J   UTMIP_DPDM_OBSERVE_SEL(0xf)
220 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K   UTMIP_DPDM_OBSERVE_SEL(0xe)
221 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
222 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
223 #define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
224 #define   FORCE_PULLDN_DM       (1 << 8)
225 #define   FORCE_PULLDN_DP       (1 << 9)
226 #define   COMB_TERMS            (1 << 0)
227 #define   ALWAYS_FREE_RUNNING_TERMS (1 << 1)
228
229 #define USB1_PREFETCH_ID               6
230 #define USB2_PREFETCH_ID               18
231 #define USB3_PREFETCH_ID               17
232
233 #define UTMIP_MISC_CFG1         0x828
234 #define   UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18)
235 #define   UTMIP_PLLU_STABLE_COUNT(x)    (((x) & 0xfff) << 6)
236
237 #define UHSIC_STAT_CFG0         0x828
238 #define   UHSIC_CONNECT_DETECT          (1 << 0)
239
240 #define UTMIP_DEBOUNCE_CFG0 0x82c
241 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
242
243 #define UTMIP_BAT_CHRG_CFG0     0x830
244 #define   UTMIP_PD_CHRG                 (1 << 0)
245 #define   UTMIP_ON_SINK_EN              (1 << 2)
246 #define   UTMIP_OP_SRC_EN               (1 << 3)
247
248 #define UTMIP_SPARE_CFG0        0x834
249 #define   FUSE_SETUP_SEL                (1 << 3)
250 #define   FUSE_ATERM_SEL                (1 << 4)
251
252 #define UTMIP_XCVR_CFG1         0x838
253 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
254 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
255 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
256 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
257
258 #define UTMIP_BIAS_CFG1         0x83c
259 #define   UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
260
261 #define FUSE_USB_CALIB_0                0x1F0
262 #define FUSE_USB_CALIB_XCVR_SETUP(x)    (((x) & 0x7F) << 0)
263
264 #define APB_MISC_GP_OBSCTRL_0   0x818
265 #define APB_MISC_GP_OBSDATA_0   0x81c
266
267 /* ULPI GPIO */
268 #define ULPI_STP        TEGRA_GPIO_PY3
269 #define ULPI_DIR        TEGRA_GPIO_PY1
270 #define ULPI_D0         TEGRA_GPIO_PO1
271 #define ULPI_D1         TEGRA_GPIO_PO2
272
273 /* These values (in milli second) are taken from the battery charging spec */
274 #define TDP_SRC_ON_MS    100
275 #define TDPSRC_CON_MS    40
276
277 #ifdef DEBUG
278 #define DBG(stuff...)   pr_info("tegra2_usb_phy: " stuff)
279 #else
280 #define DBG(stuff...)   do {} while (0)
281 #endif
282
283
284 static DEFINE_SPINLOCK(utmip_pad_lock);
285 static int utmip_pad_count;
286 static int utmip_pad_state_on;
287
288 static struct tegra_xtal_freq utmip_freq_table[] = {
289         {
290                 .freq = 12000000,
291                 .enable_delay = 0x02,
292                 .stable_count = 0x2F,
293                 .active_delay = 0x04,
294                 .xtal_freq_count = 0x76,
295                 .debounce = 0x7530,
296                 .pdtrk_count = 5,
297         },
298         {
299                 .freq = 13000000,
300                 .enable_delay = 0x02,
301                 .stable_count = 0x33,
302                 .active_delay = 0x05,
303                 .xtal_freq_count = 0x7F,
304                 .debounce = 0x7EF4,
305                 .pdtrk_count = 5,
306         },
307         {
308                 .freq = 19200000,
309                 .enable_delay = 0x03,
310                 .stable_count = 0x4B,
311                 .active_delay = 0x06,
312                 .xtal_freq_count = 0xBB,
313                 .debounce = 0xBB80,
314                 .pdtrk_count = 7,
315         },
316         {
317                 .freq = 26000000,
318                 .enable_delay = 0x04,
319                 .stable_count = 0x66,
320                 .active_delay = 0x09,
321                 .xtal_freq_count = 0xFE,
322                 .debounce = 0xFDE8,
323                 .pdtrk_count = 9,
324         },
325 };
326
327 static struct tegra_xtal_freq uhsic_freq_table[] = {
328         {
329                 .freq = 12000000,
330                 .enable_delay = 0x02,
331                 .stable_count = 0x2F,
332                 .active_delay = 0x0,
333                 .xtal_freq_count = 0x1CA,
334         },
335         {
336                 .freq = 13000000,
337                 .enable_delay = 0x02,
338                 .stable_count = 0x33,
339                 .active_delay = 0x0,
340                 .xtal_freq_count = 0x1F0,
341         },
342         {
343                 .freq = 19200000,
344                 .enable_delay = 0x03,
345                 .stable_count = 0x4B,
346                 .active_delay = 0x0,
347                 .xtal_freq_count = 0x2DD,
348         },
349         {
350                 .freq = 26000000,
351                 .enable_delay = 0x04,
352                 .stable_count = 0x66,
353                 .active_delay = 0x0,
354                 .xtal_freq_count = 0x3E0,
355         },
356 };
357
358 static void usb_phy_fence_read(struct tegra_usb_phy *phy)
359 {
360         /* Fence read for coherency of AHB master intiated writes */
361         if (phy->inst == 0)
362                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB1_PREFETCH_ID));
363         else if (phy->inst == 1)
364                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB2_PREFETCH_ID));
365         else if (phy->inst == 2)
366                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB3_PREFETCH_ID));
367
368         return;
369 }
370
371 static int usb_phy_bringup_host_controller(struct tegra_usb_phy *phy)
372 {
373         unsigned long val;
374         void __iomem *base = phy->regs;
375
376         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
377         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d] - 0\n",
378                         readl(base + USB_USBSTS), readl(base + USB_PORTSC),
379                                                         phy->port_speed);
380
381         /* enable host mode */
382         val = readl(base + USB_USBMODE_REG_OFFSET);
383         val |= USB_USBMODE_HOST;
384         writel(val, base + USB_USBMODE_REG_OFFSET);
385
386         /* Enable Port Power */
387         val = readl(base + USB_PORTSC);
388         val |= USB_PORTSC_PP;
389         writel(val, base + USB_PORTSC);
390         udelay(10);
391
392         /* Check if the phy resume from LP0. When the phy resume from LP0
393          * USB register will be reset.to zero */
394         if (!readl(base + USB_ASYNCLISTADDR)) {
395                 val = readl(base + USB_USBCMD);
396                 val |= USB_USBCMD_RS;
397                 writel(val, base + USB_USBCMD);
398
399                 /* Program the field PTC based on the saved speed mode */
400                 val = readl(base + USB_PORTSC);
401                 val &= ~(USB_PORTSC_PTC(~0));
402                 if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH)
403                         val |= USB_PORTSC_PTC(5);
404                 else if (phy->port_speed == USB_PHY_PORT_SPEED_FULL)
405                         val |= USB_PORTSC_PTC(6);
406                 else if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
407                         val |= USB_PORTSC_PTC(7);
408                 writel(val, base + USB_PORTSC);
409                 udelay(10);
410
411                 /* Disable test mode by setting PTC field to NORMAL_OP */
412                 val = readl(base + USB_PORTSC);
413                 val &= ~(USB_PORTSC_PTC(~0));
414                 writel(val, base + USB_PORTSC);
415                 udelay(10);
416         }
417
418         /* Poll until CCS is enabled */
419         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
420                                                  USB_PORTSC_CCS, 2000)) {
421                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
422         }
423
424         /* Poll until PE is enabled */
425         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_PE,
426                                                  USB_PORTSC_PE, 2000)) {
427                 pr_err("%s: timeout waiting for USB_PORTSC_PE\n", __func__);
428         }
429
430         /* Clear the PCI status, to avoid an interrupt taken upon resume */
431         val = readl(base + USB_USBSTS);
432         val |= USB_USBSTS_PCI;
433         writel(val, base + USB_USBSTS);
434
435         /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
436         val = readl(base + USB_PORTSC);
437         if ((val & USB_PORTSC_PP) && (val & USB_PORTSC_PE)) {
438                 val |= USB_PORTSC_SUSP;
439                 writel(val, base + USB_PORTSC);
440                 /* Need a 4ms delay before the controller goes to suspend */
441                 mdelay(4);
442
443                 /* Wait until port suspend completes */
444                 if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_SUSP,
445                                                  USB_PORTSC_SUSP, 1000)) {
446                         pr_err("%s: timeout waiting for PORT_SUSPEND\n",
447                                                                 __func__);
448                 }
449         }
450
451         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
452                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
453
454         return 0;
455 }
456
457 static void usb_phy_wait_for_sof(struct tegra_usb_phy *phy)
458 {
459         unsigned long val;
460         void __iomem *base = phy->regs;
461
462         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
463         val = readl(base + USB_USBSTS);
464         writel(val, base + USB_USBSTS);
465         udelay(20);
466         /* wait for two SOFs */
467         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
468                 USB_USBSTS_SRI, 2500))
469                 pr_err("%s: timeout waiting for SOF\n", __func__);
470
471         val = readl(base + USB_USBSTS);
472         writel(val, base + USB_USBSTS);
473         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI, 0, 2500))
474                 pr_err("%s: timeout waiting for SOF\n", __func__);
475
476         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
477                         USB_USBSTS_SRI, 2500))
478                 pr_err("%s: timeout waiting for SOF\n", __func__);
479
480         udelay(20);
481 }
482
483 static unsigned int utmi_phy_xcvr_setup_value(struct tegra_usb_phy *phy)
484 {
485         struct tegra_utmi_config *cfg = &phy->pdata->u_cfg.utmi;
486         signed long val;
487
488         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
489         if (cfg->xcvr_use_fuses) {
490                 val = FUSE_USB_CALIB_XCVR_SETUP(
491                                 tegra_fuse_readl(FUSE_USB_CALIB_0));
492                 if (cfg->xcvr_setup_offset <= UTMIP_XCVR_MAX_OFFSET)
493                         val = val + cfg->xcvr_setup_offset;
494
495                 if (val > UTMIP_XCVR_SETUP_MAX_VALUE) {
496                         val = UTMIP_XCVR_SETUP_MAX_VALUE;
497                         pr_info("%s: reset XCVR_SETUP to max value\n",
498                                  __func__);
499                 } else if (val < UTMIP_XCVR_SETUP_MIN_VALUE) {
500                         val = UTMIP_XCVR_SETUP_MIN_VALUE;
501                         pr_info("%s: reset XCVR_SETUP to min value\n",
502                                  __func__);
503                 }
504         } else {
505                 val = cfg->xcvr_setup;
506         }
507
508         return (unsigned int) val;
509 }
510
511
512 static int utmi_phy_open(struct tegra_usb_phy *phy)
513 {
514         unsigned long parent_rate;
515         int i;
516
517         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
518         phy->utmi_pad_clk = clk_get_sys("utmip-pad", NULL);
519         if (IS_ERR(phy->utmi_pad_clk)) {
520                 pr_err("%s: can't get utmip pad clock\n", __func__);
521                 return PTR_ERR(phy->utmi_pad_clk);
522         }
523
524         phy->utmi_xcvr_setup = utmi_phy_xcvr_setup_value(phy);
525
526         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
527         for (i = 0; i < ARRAY_SIZE(utmip_freq_table); i++) {
528                 if (utmip_freq_table[i].freq == parent_rate) {
529                         phy->freq = &utmip_freq_table[i];
530                         break;
531                 }
532         }
533         if (!phy->freq) {
534                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
535                 return -EINVAL;
536         }
537
538         return 0;
539 }
540
541 static void utmi_phy_close(struct tegra_usb_phy *phy)
542 {
543         DBG("%s inst:[%d]\n", __func__, phy->inst);
544
545         clk_put(phy->utmi_pad_clk);
546 }
547
548 static int utmi_phy_pad_power_on(struct tegra_usb_phy *phy)
549 {
550         unsigned long val, flags;
551         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
552
553         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
554         clk_enable(phy->utmi_pad_clk);
555
556         spin_lock_irqsave(&utmip_pad_lock, flags);
557
558         utmip_pad_count++;
559         val = readl(pad_base + UTMIP_BIAS_CFG0);
560         val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
561         writel(val, pad_base + UTMIP_BIAS_CFG0);
562         utmip_pad_state_on = true;
563
564         spin_unlock_irqrestore(&utmip_pad_lock, flags);
565
566         clk_disable(phy->utmi_pad_clk);
567
568         return 0;
569 }
570
571 static int utmi_phy_pad_power_off(struct tegra_usb_phy *phy)
572 {
573         unsigned long val, flags;
574         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
575
576         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
577         clk_enable(phy->utmi_pad_clk);
578         spin_lock_irqsave(&utmip_pad_lock, flags);
579
580         if (!utmip_pad_count) {
581                 pr_err("%s: utmip pad already powered off\n", __func__);
582                 goto out;
583         }
584         if (--utmip_pad_count == 0) {
585                 val = readl(pad_base + UTMIP_BIAS_CFG0);
586                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
587                 writel(val, pad_base + UTMIP_BIAS_CFG0);
588                 utmip_pad_state_on = false;
589         }
590 out:
591         spin_unlock_irqrestore(&utmip_pad_lock, flags);
592         clk_disable(phy->utmi_pad_clk);
593
594         return 0;
595 }
596
597 static int utmi_phy_irq(struct tegra_usb_phy *phy)
598 {
599         void __iomem *base = phy->regs;
600         unsigned long val = 0;
601
602         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
603
604         usb_phy_fence_read(phy);
605         if (phy->pdata->u_data.host.hot_plug) {
606                 val = readl(base + USB_SUSP_CTRL);
607                 if ((val  & USB_PHY_CLK_VALID_INT_STS)) {
608                         val &= ~USB_PHY_CLK_VALID_INT_ENB |
609                                         USB_PHY_CLK_VALID_INT_STS;
610                         writel(val , (base + USB_SUSP_CTRL));
611                         pr_info("%s: usb device plugged-in\n", __func__);
612                         val = readl(base + USB_USBSTS);
613                         if (!(val  & USB_USBSTS_PCI))
614                                 return IRQ_NONE;
615                         val = readl(base + USB_PORTSC);
616                         val &= ~(USB_PORTSC_WKCN | USB_PORTSC_RWC_BITS);
617                         writel(val , (base + USB_PORTSC));
618                 } else if (!phy->phy_clk_on) {
619                         return IRQ_NONE;
620                 }
621         }
622
623         return IRQ_HANDLED;
624 }
625
626 static int phy_post_suspend(struct tegra_usb_phy *phy)
627 {
628
629         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
630         /* Need a 4ms delay for controller to suspend */
631         mdelay(4);
632         return 0;
633 }
634
635 static int utmi_phy_post_resume(struct tegra_usb_phy *phy)
636 {
637         unsigned long val;
638         void __iomem *base = phy->regs;
639
640         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
641
642         val = readl(base + UTMIP_TX_CFG0);
643         val &= ~UTMIP_HS_DISCON_DISABLE;
644         writel(val, base + UTMIP_TX_CFG0);
645         return 0;
646 }
647
648 static int utmi_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
649 {
650         unsigned long val;
651         void __iomem *base = phy->regs;
652
653         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
654         val = readl(base + UTMIP_TX_CFG0);
655         val |= UTMIP_HS_DISCON_DISABLE;
656         writel(val, base + UTMIP_TX_CFG0);
657
658         usb_phy_wait_for_sof(phy);
659
660         return 0;
661 }
662
663 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
664 {
665         unsigned long val;
666         void __iomem *base = phy->regs;
667
668         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
669         if (!phy->phy_clk_on) {
670                 DBG("%s(%d) inst:[%d] phy clk is already off\n",
671                                         __func__, __LINE__, phy->inst);
672                 return 0;
673         }
674
675         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
676                 val = readl(base + USB_SUSP_CTRL);
677                 val &= ~(USB_WAKEUP_DEBOUNCE_COUNT(~0));
678                 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
679                 writel(val, base + USB_SUSP_CTRL);
680
681                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
682                 val |= UTMIP_PD_CHRG;
683                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
684         }
685
686         if (!phy->pdata->u_data.host.hot_plug) {
687                 val = readl(base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
688                 val |= (UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
689                          UTMIP_FORCE_PDZI_POWERDOWN);
690                 writel(val, base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
691         }
692
693         val = readl(base + UTMIP_XCVR_CFG1);
694         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
695                    UTMIP_FORCE_PDDR_POWERDOWN;
696         writel(val, base + UTMIP_XCVR_CFG1);
697
698         if (phy->inst != 0) {
699                 val = readl(base + UTMIP_BIAS_CFG0);
700                 val |= UTMIP_OTGPD;
701                 writel(val, base + UTMIP_BIAS_CFG0);
702         }
703
704         phy->port_speed = (readl(base + USB_PORTSC) >> 26) &
705                         USB_PORTSC_PSPD_MASK;
706
707         if (phy->pdata->u_data.host.hot_plug) {
708                 bool enable_hotplug = true;
709                 /* if it is OTG port then make sure to enable hot-plug feature
710                    only if host adaptor is connected, i.e id is low */
711                 if (phy->pdata->port_otg) {
712                         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
713                         enable_hotplug = (val & USB_ID_STATUS) ? false : true;
714                 }
715                 if (enable_hotplug) {
716                         val = readl(base + USB_PORTSC);
717                         val |= USB_PORTSC_WKCN;
718                         writel(val, base + USB_PORTSC);
719
720                         val = readl(base + USB_SUSP_CTRL);
721                         val |= USB_PHY_CLK_VALID_INT_ENB;
722                         writel(val, base + USB_SUSP_CTRL);
723                 } else {
724                         /* Disable PHY clock valid interrupts while going into suspend*/
725                         val = readl(base + USB_SUSP_CTRL);
726                         val &= ~USB_PHY_CLK_VALID_INT_ENB;
727                         writel(val, base + USB_SUSP_CTRL);
728                 }
729         }
730
731         if (phy->inst == 2) {
732                 val = readl(base + USB_PORTSC);
733                 val |= USB_PORTSC_PHCD;
734                 writel(val, base + USB_PORTSC);
735         } else {
736                 val = readl(base + USB_SUSP_CTRL);
737                 val |= USB_SUSP_SET;
738                 writel(val, base + USB_SUSP_CTRL);
739                 udelay(10);
740                 val = readl(base + USB_SUSP_CTRL);
741                 val &= ~USB_SUSP_SET;
742                 writel(val, base + USB_SUSP_CTRL);
743         }
744
745         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
746                                                                 0, 2500))
747                 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
748
749         utmi_phy_pad_power_off(phy);
750
751         phy->phy_clk_on = false;
752         phy->hw_accessible = false;
753
754         DBG("%s(%d) inst:[%d]END\n", __func__, __LINE__, phy->inst);
755
756         return 0;
757 }
758
759 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
760 {
761         unsigned long val;
762         void __iomem *base = phy->regs;
763         struct tegra_utmi_config *config = &phy->pdata->u_cfg.utmi;
764         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
765         if (phy->phy_clk_on) {
766                 DBG("%s(%d) inst:[%d] phy clk is already on\n",
767                                         __func__, __LINE__, phy->inst);
768                 return 0;
769         }
770
771         val = readl(base + USB_SUSP_CTRL);
772         val |= UTMIP_RESET;
773         writel(val, base + USB_SUSP_CTRL);
774
775         val = readl(base + UTMIP_TX_CFG0);
776         val |= UTMIP_FS_PREABMLE_J;
777         writel(val, base + UTMIP_TX_CFG0);
778
779         val = readl(base + UTMIP_HSRX_CFG0);
780         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
781         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
782         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
783         writel(val, base + UTMIP_HSRX_CFG0);
784
785         val = readl(base + UTMIP_HSRX_CFG1);
786         val &= ~(UTMIP_HS_SYNC_START_DLY(~0));
787         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
788         writel(val, base + UTMIP_HSRX_CFG1);
789
790         val = readl(base + UTMIP_DEBOUNCE_CFG0);
791         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
792         val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
793         writel(val, base + UTMIP_DEBOUNCE_CFG0);
794
795         val = readl(base + UTMIP_MISC_CFG0);
796         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
797         writel(val, base + UTMIP_MISC_CFG0);
798
799         val = readl(base + UTMIP_MISC_CFG1);
800         val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) | UTMIP_PLLU_STABLE_COUNT(~0));
801         val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |
802                 UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count);
803         writel(val, base + UTMIP_MISC_CFG1);
804
805         val = readl(base + UTMIP_PLL_CFG1);
806         val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) | UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
807         val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |
808                 UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
809         writel(val, base + UTMIP_PLL_CFG1);
810
811         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
812                 val = readl(base + USB_SUSP_CTRL);
813                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
814                 writel(val, base + USB_SUSP_CTRL);
815
816                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
817                 val &= ~UTMIP_PD_CHRG;
818                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
819         } else {
820                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
821                 val |= UTMIP_PD_CHRG;
822                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
823         }
824
825         utmi_phy_pad_power_on(phy);
826
827         val = readl(base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
828         val &= ~(UTMIP_XCVR_LSBIAS_SEL | UTMIP_FORCE_PD_POWERDOWN |
829                  UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN |
830                  UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_LSFSLEW(~0) |
831                  UTMIP_XCVR_LSRSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
832         val |= UTMIP_XCVR_SETUP(phy->utmi_xcvr_setup);
833         val |= UTMIP_XCVR_SETUP_MSB(XCVR_SETUP_MSB_CALIB(phy->utmi_xcvr_setup));
834         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
835         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
836
837         writel(val, base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
838
839         val = readl(base + UTMIP_XCVR_CFG1);
840         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
841                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
842         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
843         writel(val, base + UTMIP_XCVR_CFG1);
844
845
846         val = readl(base + UTMIP_BIAS_CFG1);
847         val &= ~(UTMIP_BIAS_PDTRK_COUNT(~0));
848         val |= UTMIP_BIAS_PDTRK_COUNT(phy->freq->pdtrk_count);
849         writel(val, base + UTMIP_BIAS_CFG1);
850
851         val = readl(base + UTMIP_SPARE_CFG0);
852         val &= ~FUSE_SETUP_SEL;
853         writel(val, base + UTMIP_SPARE_CFG0);
854
855         val = readl(base + USB_SUSP_CTRL);
856         val |= UTMIP_PHY_ENABLE;
857         writel(val, base + USB_SUSP_CTRL);
858
859         val = readl(base + USB_SUSP_CTRL);
860         val &= ~UTMIP_RESET;
861         writel(val, base + USB_SUSP_CTRL);
862
863         if (phy->inst == 0) {
864                 val = readl(base + USB_SUSP_CTRL);
865                 val &= ~USB_SUSP_SET;
866                 writel(val, base + USB_SUSP_CTRL);
867         } else {
868                 val = readl(base + USB_PORTSC);
869                 val &= ~USB_PORTSC_PHCD;
870                 writel(val, base + USB_PORTSC);
871         }
872
873         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
874                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500))
875                 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
876
877         if (phy->inst == 2) {
878                 val = readl(base + USB_PORTSC);
879                 val &= ~(USB_PORTSC_PTS(~0));
880                 writel(val, base + USB_PORTSC);
881         }
882
883         phy->phy_clk_on = true;
884         phy->hw_accessible = true;
885
886         return 0;
887 }
888
889 static void utmi_phy_restore_start(struct tegra_usb_phy *phy)
890 {
891         unsigned long val;
892         void __iomem *base = phy->regs;
893
894         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
895         val = readl(base + UTMIP_MISC_CFG0);
896         val &= ~(UTMIP_DPDM_OBSERVE_SEL(~0));
897
898         if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
899                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
900         else
901                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
902         writel(val, base + UTMIP_MISC_CFG0);
903         udelay(1);
904
905         val = readl(base + UTMIP_MISC_CFG0);
906         val |= UTMIP_DPDM_OBSERVE;
907         writel(val, base + UTMIP_MISC_CFG0);
908         udelay(10);
909 }
910
911 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
912 {
913         unsigned long val;
914         void __iomem *base = phy->regs;
915
916         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
917         val = readl(base + UTMIP_MISC_CFG0);
918         val &= ~UTMIP_DPDM_OBSERVE;
919         writel(val, base + UTMIP_MISC_CFG0);
920         udelay(10);
921 }
922
923
924 static int utmi_phy_resume(struct tegra_usb_phy *phy)
925 {
926         int status = 0;
927         unsigned long val, flags;
928         void __iomem *base = phy->regs;
929         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
930
931         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
932         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) {
933                 if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
934                         utmi_phy_restore_start(phy);
935                         usb_phy_bringup_host_controller(phy);
936                         utmi_phy_restore_end(phy);
937                 } else {
938                         /* device is plugged in when system is in LP0 */
939                         /* bring up the controller from LP0*/
940                         val = readl(base + USB_USBCMD);
941                         val |= USB_USBCMD_RESET;
942                         writel(val, base + USB_USBCMD);
943
944                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
945                                 USB_USBCMD_RESET, 0, 2500) < 0) {
946                                 pr_err("%s: timeout waiting for reset\n", __func__);
947                         }
948
949                         val = readl(base + USB_USBMODE_REG_OFFSET);
950                         val &= ~USB_USBMODE_MASK;
951                         val |= USB_USBMODE_HOST;
952                         writel(val, base + USB_USBMODE_REG_OFFSET);
953
954                         if (phy->inst == 2) {
955                                 val = readl(base + USB_PORTSC);
956                                 val &= ~USB_PORTSC_PTS(~0);
957                                 writel(val, base + USB_PORTSC);
958                         }
959                         writel(USB_USBCMD_RS, base + USB_USBCMD);
960
961                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
962                                 USB_USBCMD_RS, USB_USBCMD_RS, 2500) < 0) {
963                                 pr_err("%s: timeout waiting for run bit\n", __func__);
964                         }
965
966                         /* Enable Port Power */
967                         val = readl(base + USB_PORTSC);
968                         val |= USB_PORTSC_PP;
969                         writel(val, base + USB_PORTSC);
970                         udelay(10);
971
972                         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
973                                 readl(base + USB_USBSTS), readl(base + USB_PORTSC));
974                 }
975         } else {
976                 /* Restoring the pad powers */
977                 clk_enable(phy->utmi_pad_clk);
978
979                 spin_lock_irqsave(&utmip_pad_lock, flags);
980
981                 val = readl(pad_base + UTMIP_BIAS_CFG0);
982                 if (utmip_pad_state_on)
983                         val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
984                 else
985                         val |= (UTMIP_OTGPD | UTMIP_BIASPD);
986                 writel(val, pad_base + UTMIP_BIAS_CFG0);
987
988                 spin_unlock_irqrestore(&utmip_pad_lock, flags);
989                 clk_disable(phy->utmi_pad_clk);
990         }
991
992         return status;
993 }
994
995 static bool utmi_phy_charger_detect(struct tegra_usb_phy *phy)
996 {
997         unsigned long val;
998         void __iomem *base = phy->regs;
999         bool status;
1000
1001         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1002         /* Enable charger detection logic */
1003         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1004         val |= UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN;
1005         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1006
1007         /* Source should be on for 100 ms as per USB charging spec */
1008         msleep(TDP_SRC_ON_MS);
1009
1010         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1011         /* If charger is not connected disable the interrupt */
1012         val &= ~VDAT_DET_INT_EN;
1013         val |= VDAT_DET_CHG_DET;
1014         writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
1015
1016         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1017         if (val & VDAT_DET_STS)
1018                 status = true;
1019         else
1020                 status = false;
1021
1022         /* Disable charger detection logic */
1023         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1024         val &= ~(UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN);
1025         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1026
1027         /* Delay of 40 ms before we pull the D+ as per battery charger spec */
1028         msleep(TDPSRC_CON_MS);
1029
1030         return status;
1031 }
1032
1033
1034 static int uhsic_phy_open(struct tegra_usb_phy *phy)
1035 {
1036         unsigned long parent_rate;
1037         int i;
1038
1039         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1040         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
1041         for (i = 0; i < ARRAY_SIZE(uhsic_freq_table); i++) {
1042                 if (uhsic_freq_table[i].freq == parent_rate) {
1043                         phy->freq = &uhsic_freq_table[i];
1044                         break;
1045                 }
1046         }
1047         if (!phy->freq) {
1048                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
1049                 return -EINVAL;
1050         }
1051
1052         return 0;
1053 }
1054
1055 static int uhsic_phy_irq(struct tegra_usb_phy *phy)
1056 {
1057         usb_phy_fence_read(phy);
1058         return IRQ_HANDLED;
1059 }
1060
1061 static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
1062 {
1063         unsigned long val;
1064         void __iomem *base = phy->regs;
1065         struct tegra_hsic_config *config = &phy->pdata->u_cfg.hsic;
1066
1067         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1068         if (phy->phy_clk_on) {
1069                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
1070                                                         __LINE__, phy->inst);
1071                 return 0;
1072         }
1073
1074         val = readl(base + UHSIC_PADS_CFG1);
1075         val &= ~(UHSIC_PD_BG | UHSIC_PD_TX | UHSIC_PD_TRK | UHSIC_PD_RX |
1076                         UHSIC_PD_ZI | UHSIC_RPD_DATA | UHSIC_RPD_STROBE);
1077         val |= UHSIC_RX_SEL;
1078         writel(val, base + UHSIC_PADS_CFG1);
1079         udelay(2);
1080
1081         val = readl(base + USB_SUSP_CTRL);
1082         val |= UHSIC_RESET;
1083         writel(val, base + USB_SUSP_CTRL);
1084         udelay(30);
1085
1086         val = readl(base + USB_SUSP_CTRL);
1087         val |= UHSIC_PHY_ENABLE;
1088         writel(val, base + USB_SUSP_CTRL);
1089
1090         val = readl(base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
1091         val |= UHSIC_IDLE_WAIT(config->idle_wait_delay);
1092         val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(config->elastic_underrun_limit);
1093         val |= UHSIC_ELASTIC_OVERRUN_LIMIT(config->elastic_overrun_limit);
1094         writel(val, base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
1095
1096         val = readl(base + UHSIC_HSRX_CFG1);
1097         val |= UHSIC_HS_SYNC_START_DLY(config->sync_start_delay);
1098         writel(val, base + UHSIC_HSRX_CFG1);
1099
1100         val = readl(base + UHSIC_MISC_CFG0);
1101         val |= UHSIC_SUSPEND_EXIT_ON_EDGE;
1102         writel(val, base + UHSIC_MISC_CFG0);
1103
1104         val = readl(base + UHSIC_MISC_CFG1);
1105         val |= UHSIC_PLLU_STABLE_COUNT(phy->freq->stable_count);
1106         writel(val, base + UHSIC_MISC_CFG1);
1107
1108         val = readl(base + UHSIC_PLL_CFG1);
1109         val |= UHSIC_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
1110         val |= UHSIC_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count);
1111         writel(val, base + UHSIC_PLL_CFG1);
1112
1113         val = readl(base + USB_SUSP_CTRL);
1114         val &= ~(UHSIC_RESET);
1115         writel(val, base + USB_SUSP_CTRL);
1116         udelay(2);
1117
1118         val = readl(base + USB_PORTSC);
1119         val &= ~(USB_PORTSC_PTS(~0));
1120         writel(val, base + USB_PORTSC);
1121
1122         val = readl(base + USB_TXFILLTUNING);
1123         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
1124                 val = USB_FIFO_TXFILL_THRES(0x10);
1125                 writel(val, base + USB_TXFILLTUNING);
1126         }
1127
1128         val = readl(base + USB_PORTSC);
1129         val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN);
1130         writel(val, base + USB_PORTSC);
1131
1132         val = readl(base + UHSIC_PADS_CFG0);
1133         val &= ~(UHSIC_TX_RTUNEN);
1134         /* set Rtune impedance to 40 ohm */
1135         val |= UHSIC_TX_RTUNE(0);
1136         writel(val, base + UHSIC_PADS_CFG0);
1137
1138         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
1139                                                 USB_PHY_CLK_VALID, 2500)) {
1140                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
1141                 return -ETIMEDOUT;
1142         }
1143
1144         phy->phy_clk_on = true;
1145         phy->hw_accessible = true;
1146
1147         return 0;
1148 }
1149
1150 static int uhsic_phy_power_off(struct tegra_usb_phy *phy)
1151 {
1152         unsigned long val;
1153         void __iomem *base = phy->regs;
1154
1155         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1156         if (!phy->phy_clk_on) {
1157                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
1158                                                         __LINE__, phy->inst);
1159                 return 0;
1160         }
1161
1162         val = readl(base + UHSIC_PADS_CFG1);
1163         val &= ~UHSIC_RPU_STROBE;
1164         val |= UHSIC_RPD_STROBE;
1165         writel(val, base + UHSIC_PADS_CFG1);
1166
1167         val = readl(base + USB_SUSP_CTRL);
1168         val |= UHSIC_RESET;
1169         writel(val, base + USB_SUSP_CTRL);
1170         udelay(30);
1171
1172         val = readl(base + USB_SUSP_CTRL);
1173         val &= ~UHSIC_PHY_ENABLE;
1174         writel(val, base + USB_SUSP_CTRL);
1175
1176         phy->phy_clk_on = false;
1177         phy->hw_accessible = false;
1178
1179         return 0;
1180 }
1181
1182 static int uhsic_phy_bus_port_power(struct tegra_usb_phy *phy)
1183 {
1184         unsigned long val;
1185         void __iomem *base = phy->regs;
1186
1187         val = readl(base + UHSIC_MISC_CFG0);
1188         val |= UHSIC_DETECT_SHORT_CONNECT;
1189         writel(val, base + UHSIC_MISC_CFG0);
1190         udelay(1);
1191
1192         val = readl(base + UHSIC_MISC_CFG0);
1193         val |= UHSIC_FORCE_XCVR_MODE;
1194         writel(val, base + UHSIC_MISC_CFG0);
1195
1196         val = readl(base + UHSIC_PADS_CFG1);
1197         val &= ~UHSIC_RPD_STROBE;
1198         val |= UHSIC_RPU_STROBE;
1199         writel(val, base + UHSIC_PADS_CFG1);
1200
1201         val = readl(base + USB_USBCMD);
1202         val &= ~USB_USBCMD_RS;
1203         writel(val, base + USB_USBCMD);
1204
1205         if (phy->pdata->ops && phy->pdata->ops->port_power)
1206                 phy->pdata->ops->port_power();
1207
1208         if (usb_phy_reg_status_wait(base + UHSIC_STAT_CFG0,
1209                         UHSIC_CONNECT_DETECT, UHSIC_CONNECT_DETECT, 2000)) {
1210                 pr_err("%s: timeout waiting for UHSIC_CONNECT_DETECT\n",
1211                                                                 __func__);
1212                 return -ETIMEDOUT;
1213         }
1214
1215 /* FIXME : need to check whether this piece is required or not
1216         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_LS(2),
1217                                                 USB_PORTSC_LS(2), 2000)) {
1218                 pr_err("%s: timeout waiting for dplus state\n", __func__);
1219                 return -ETIMEDOUT;
1220         }
1221 */
1222         return 0;
1223 }
1224
1225
1226 static int uhsic_phy_bus_reset(struct tegra_usb_phy *phy)
1227 {
1228         unsigned long val;
1229         void __iomem *base = phy->regs;
1230
1231         val = readl(base + USB_PORTSC);
1232         val |= USB_PORTSC_PTC(5);
1233         writel(val, base + USB_PORTSC);
1234         udelay(2);
1235
1236         val = readl(base + USB_PORTSC);
1237         val &= ~(USB_PORTSC_PTC(~0));
1238         writel(val, base + USB_PORTSC);
1239         udelay(2);
1240
1241         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_LS(0),
1242                                                  0, 2000)) {
1243                 pr_err("%s: timeout waiting for USB_PORTSC_LS\n", __func__);
1244                 return -ETIMEDOUT;
1245         }
1246
1247         /* Poll until CCS is enabled */
1248         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
1249                                                  USB_PORTSC_CCS, 2000)) {
1250                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
1251                 return -ETIMEDOUT;
1252         }
1253
1254         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_PSPD(2),
1255                                                  USB_PORTSC_PSPD(2), 2000)) {
1256                 pr_err("%s: timeout waiting for USB_PORTSC_PSPD\n", __func__);
1257                 return -ETIMEDOUT;
1258         }
1259
1260         val = readl(base + USB_USBCMD);
1261         val &= ~USB_USBCMD_RS;
1262         writel(val, base + USB_USBCMD);
1263
1264         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
1265                                                  USB_USBSTS_HCH, 2000)) {
1266                 pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
1267                 return -ETIMEDOUT;
1268         }
1269
1270         val = readl(base + UHSIC_PADS_CFG1);
1271         val &= ~UHSIC_RPU_STROBE;
1272         val |= UHSIC_RPD_STROBE;
1273         writel(val, base + UHSIC_PADS_CFG1);
1274
1275         mdelay(50);
1276
1277         val = readl(base + UHSIC_PADS_CFG1);
1278         val &= ~UHSIC_RPD_STROBE;
1279         val |= UHSIC_RPU_STROBE;
1280         writel(val, base + UHSIC_PADS_CFG1);
1281
1282         val = readl(base + USB_USBCMD);
1283         val |= USB_USBCMD_RS;
1284         writel(val, base + USB_USBCMD);
1285
1286         val = readl(base + UHSIC_PADS_CFG1);
1287         val &= ~UHSIC_RPU_STROBE;
1288         writel(val, base + UHSIC_PADS_CFG1);
1289
1290         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
1291                                                  USB_USBCMD_RS, 2000)) {
1292                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
1293                 return -ETIMEDOUT;
1294         }
1295
1296         return 0;
1297 }
1298
1299
1300 static int uhsic_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1301 {
1302         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1303         usb_phy_wait_for_sof(phy);
1304
1305         return 0;
1306 }
1307
1308 static int uhsic_phy_resume(struct tegra_usb_phy *phy)
1309 {
1310         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1311         uhsic_phy_bus_port_power(phy);
1312
1313         return 0;
1314 }
1315
1316
1317 static int uhsic_phy_post_resume(struct tegra_usb_phy *phy)
1318 {
1319         unsigned long val;
1320         void __iomem *base = phy->regs;
1321
1322         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1323         val = readl(base + USB_TXFILLTUNING);
1324         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
1325                 val = USB_FIFO_TXFILL_THRES(0x10);
1326                 writel(val, base + USB_TXFILLTUNING);
1327         }
1328
1329         return 0;
1330 }
1331
1332 static void ulpi_set_trimmer(struct tegra_usb_phy *phy)
1333 {
1334         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
1335         void __iomem *base = phy->regs;
1336         unsigned long val;
1337
1338         val = ULPI_DATA_TRIMMER_SEL(config->data_trimmer);
1339         val |= ULPI_STPDIRNXT_TRIMMER_SEL(config->stpdirnxt_trimmer);
1340         val |= ULPI_DIR_TRIMMER_SEL(config->dir_trimmer);
1341         writel(val, base + ULPI_TIMING_CTRL_1);
1342         udelay(10);
1343
1344         val |= ULPI_DATA_TRIMMER_LOAD;
1345         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
1346         val |= ULPI_DIR_TRIMMER_LOAD;
1347         writel(val, base + ULPI_TIMING_CTRL_1);
1348 }
1349
1350
1351 static int ulpi_link_phy_open(struct tegra_usb_phy *phy)
1352 {
1353         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
1354         int err = 0;
1355
1356         phy->ulpi_clk = NULL;
1357
1358         if (config->clk) {
1359                 phy->ulpi_clk = clk_get_sys(NULL, config->clk);
1360                 if (IS_ERR(phy->ulpi_clk)) {
1361                         pr_err("%s: can't get ulpi clock\n", __func__);
1362                         err = -ENXIO;
1363                 }
1364         }
1365
1366         phy->ulpi_vp = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
1367         phy->ulpi_vp->io_priv = phy->regs + ULPI_VIEWPORT;
1368
1369         return err;
1370 }
1371
1372 static void ulpi_link_phy_close(struct tegra_usb_phy *phy)
1373 {
1374         DBG("%s inst:[%d]\n", __func__, phy->inst);
1375         if (phy->ulpi_clk)
1376                 clk_put(phy->ulpi_clk);
1377 }
1378
1379 static int ulpi_link_phy_irq(struct tegra_usb_phy *phy)
1380 {
1381         usb_phy_fence_read(phy);
1382         return IRQ_HANDLED;
1383 }
1384
1385 static int ulpi_link_phy_power_off(struct tegra_usb_phy *phy)
1386 {
1387         unsigned long val;
1388         void __iomem *base = phy->regs;
1389         int ret;
1390
1391         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1392         if (!phy->phy_clk_on) {
1393                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
1394                                                         __LINE__, phy->inst);
1395                 return 0;
1396         }
1397
1398         /* Disable VbusValid, SessEnd comparators */
1399         ret = usb_phy_io_write(phy->ulpi_vp, 0x00, 0x0D);
1400         if (ret)
1401                 pr_err("%s: ulpi write 0x0D failed\n", __func__);
1402
1403         ret = usb_phy_io_write(phy->ulpi_vp, 0x00, 0x10);
1404         if (ret)
1405                 pr_err("%s: ulpi write 0x10 failed\n", __func__);
1406
1407         /* Disable IdFloat comparator */
1408         ret = usb_phy_io_write(phy->ulpi_vp, 0x00, 0x19);
1409         if (ret)
1410                 pr_err("%s: ulpi write 0x19 failed\n", __func__);
1411
1412         ret = usb_phy_io_write(phy->ulpi_vp, 0x00, 0x1D);
1413         if (ret)
1414                 pr_err("%s: ulpi write 0x1D failed\n", __func__);
1415
1416         phy->port_speed = (readl(base + USB_PORTSC) >> 26) &
1417                         USB_PORTSC_PSPD_MASK;
1418
1419         /* Clear WKCN/WKDS/WKOC wake-on events that can cause the USB
1420          * Controller to immediately bring the ULPI PHY out of low power
1421          */
1422         val = readl(base + USB_PORTSC);
1423         val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN);
1424         writel(val, base + USB_PORTSC);
1425
1426         /* Put the PHY in the low power mode */
1427         val = readl(base + USB_PORTSC);
1428         val |= USB_PORTSC_PHCD;
1429         writel(val, base + USB_PORTSC);
1430
1431         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
1432                                                          0, 2500)) {
1433                 pr_err("%s: timeout waiting for phy to stop\n", __func__);
1434         }
1435
1436         if (phy->ulpi_clk)
1437                 clk_disable(phy->ulpi_clk);
1438
1439         phy->phy_clk_on = false;
1440         phy->hw_accessible = false;
1441
1442         return 0;
1443 }
1444
1445 static int ulpi_link_phy_power_on(struct tegra_usb_phy *phy)
1446 {
1447         int ret;
1448         unsigned long val;
1449         void __iomem *base = phy->regs;
1450
1451         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1452         if (phy->phy_clk_on) {
1453                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
1454                                                         __LINE__, phy->inst);
1455                 return 0;
1456         }
1457
1458         if (phy->ulpi_clk) {
1459                 clk_enable(phy->ulpi_clk);
1460                 mdelay(1);
1461         }
1462
1463         val = readl(base + USB_SUSP_CTRL);
1464         val |= UHSIC_RESET;
1465         writel(val, base + USB_SUSP_CTRL);
1466
1467         val = readl(base + ULPI_TIMING_CTRL_0);
1468         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
1469         writel(val, base + ULPI_TIMING_CTRL_0);
1470
1471         val = readl(base + USB_SUSP_CTRL);
1472         val |= ULPI_PHY_ENABLE;
1473         writel(val, base + USB_SUSP_CTRL);
1474
1475         val = readl(base + USB_SUSP_CTRL);
1476         val |= USB_SUSP_CLR;
1477         writel(val, base + USB_SUSP_CTRL);
1478
1479         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
1480                                                 USB_PHY_CLK_VALID, 2500))
1481                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
1482
1483         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_CLKEN,
1484                                                 USB_CLKEN, 2500))
1485                 pr_err("%s: timeout waiting for AHB clock\n", __func__);
1486
1487         val = readl(base + USB_SUSP_CTRL);
1488         val &= ~USB_SUSP_CLR;
1489         writel(val, base + USB_SUSP_CTRL);
1490
1491         val = 0;
1492         writel(val, base + ULPI_TIMING_CTRL_1);
1493
1494         ulpi_set_trimmer(phy);
1495
1496         /* Fix VbusInvalid due to floating VBUS */
1497         ret = usb_phy_io_write(phy->ulpi_vp, 0x40, 0x08);
1498         if (ret) {
1499                 pr_err("%s: ulpi write failed\n", __func__);
1500                 return ret;
1501         }
1502
1503         ret = usb_phy_io_write(phy->ulpi_vp, 0x80, 0x0B);
1504         if (ret) {
1505                 pr_err("%s: ulpi write failed\n", __func__);
1506                 return ret;
1507         }
1508
1509         val = readl(base + USB_PORTSC);
1510         val |= USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN;
1511         writel(val, base + USB_PORTSC);
1512
1513         phy->phy_clk_on = true;
1514         phy->hw_accessible = true;
1515
1516         return 0;
1517 }
1518
1519 static inline void ulpi_link_phy_set_tristate(bool enable)
1520 {
1521 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1522         int tristate = (enable) ? TEGRA_TRI_TRISTATE : TEGRA_TRI_NORMAL;
1523
1524         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAA, tristate);
1525         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAB, tristate);
1526         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UDA, tristate);
1527 #endif
1528 }
1529
1530 static void ulpi_link_phy_restore_start(struct tegra_usb_phy *phy)
1531 {
1532         unsigned long val;
1533         void __iomem *base = phy->regs;
1534
1535         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1536
1537         /*Tristate ulpi interface before USB controller resume*/
1538         ulpi_link_phy_set_tristate(true);
1539
1540         val = readl(base + ULPI_TIMING_CTRL_0);
1541         val &= ~ULPI_OUTPUT_PINMUX_BYP;
1542         writel(val, base + ULPI_TIMING_CTRL_0);
1543 }
1544
1545 static void ulpi_link_phy_restore_end(struct tegra_usb_phy *phy)
1546 {
1547         unsigned long val;
1548         void __iomem *base = phy->regs;
1549
1550         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1551
1552         val = readl(base + ULPI_TIMING_CTRL_0);
1553         val |= ULPI_OUTPUT_PINMUX_BYP;
1554         writel(val, base + ULPI_TIMING_CTRL_0);
1555
1556         ulpi_link_phy_set_tristate(false);
1557 }
1558
1559 static int ulpi_link_phy_resume(struct tegra_usb_phy *phy)
1560 {
1561         int status = 0;
1562
1563         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1564         if (phy->pdata->u_data.host.power_off_on_suspend) {
1565                 status = ulpi_link_phy_power_on(phy);
1566                 if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
1567                         ulpi_link_phy_restore_start(phy);
1568                         usb_phy_bringup_host_controller(phy);
1569                         ulpi_link_phy_restore_end(phy);
1570                 }
1571         }
1572
1573         return status;
1574 }
1575
1576 static inline void ulpi_pinmux_bypass(struct tegra_usb_phy *phy, bool enable)
1577 {
1578         unsigned long val;
1579         void __iomem *base = phy->regs;
1580
1581         val = readl(base + ULPI_TIMING_CTRL_0);
1582
1583         if (enable)
1584                 val |= ULPI_OUTPUT_PINMUX_BYP;
1585         else
1586                 val &= ~ULPI_OUTPUT_PINMUX_BYP;
1587
1588         writel(val, base + ULPI_TIMING_CTRL_0);
1589 }
1590
1591 static inline void ulpi_null_phy_set_tristate(bool enable)
1592 {
1593 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1594         int tristate = (enable) ? TEGRA_TRI_TRISTATE : TEGRA_TRI_NORMAL;
1595
1596         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UDA, tristate);
1597         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAA, tristate);
1598         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAB, tristate);
1599 #endif
1600 }
1601
1602 static void ulpi_null_phy_obs_read(void)
1603 {
1604         static void __iomem *apb_misc;
1605         unsigned slv0_obs, s2s_obs;
1606
1607         if (!apb_misc)
1608                 apb_misc = ioremap(TEGRA_APB_MISC_BASE, TEGRA_APB_MISC_SIZE);
1609
1610         writel(0x80b10034, apb_misc + APB_MISC_GP_OBSCTRL_0);
1611         slv0_obs = readl(apb_misc + APB_MISC_GP_OBSDATA_0);
1612
1613         writel(0x80b10038, apb_misc + APB_MISC_GP_OBSCTRL_0);
1614         s2s_obs = readl(apb_misc + APB_MISC_GP_OBSDATA_0);
1615
1616         pr_debug("slv0 obs: %08x\ns2s obs: %08x\n", slv0_obs, s2s_obs);
1617 }
1618
1619 static const struct gpio ulpi_gpios[] = {
1620         {ULPI_STP, GPIOF_IN, "ULPI_STP"},
1621         {ULPI_DIR, GPIOF_OUT_INIT_LOW, "ULPI_DIR"},
1622         {ULPI_D0, GPIOF_OUT_INIT_LOW, "ULPI_D0"},
1623         {ULPI_D1, GPIOF_OUT_INIT_LOW, "ULPI_D1"},
1624 };
1625
1626 static int ulpi_null_phy_open(struct tegra_usb_phy *phy)
1627 {
1628         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
1629         int ret;
1630
1631         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1632
1633         ret = gpio_request_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
1634         if (ret)
1635                 return ret;
1636
1637         if (gpio_is_valid(config->phy_restore_gpio)) {
1638                 ret = gpio_request(config->phy_restore_gpio, "phy_restore");
1639                 if (ret)
1640                         goto err_gpio_free;
1641
1642                 gpio_direction_input(config->phy_restore_gpio);
1643         }
1644
1645         tegra_periph_reset_assert(phy->ctrlr_clk);
1646         udelay(10);
1647         tegra_periph_reset_deassert(phy->ctrlr_clk);
1648
1649         return 0;
1650
1651 err_gpio_free:
1652         gpio_free_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
1653         return ret;
1654 }
1655
1656 static void ulpi_null_phy_close(struct tegra_usb_phy *phy)
1657 {
1658         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
1659
1660         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1661
1662         if (gpio_is_valid(config->phy_restore_gpio))
1663                 gpio_free(config->phy_restore_gpio);
1664
1665         gpio_free_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
1666 }
1667
1668 static int ulpi_null_phy_power_off(struct tegra_usb_phy *phy)
1669 {
1670         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1671
1672         if (!phy->phy_clk_on) {
1673                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
1674                                                         __LINE__, phy->inst);
1675                 return 0;
1676         }
1677
1678         phy->phy_clk_on = false;
1679         phy->hw_accessible = false;
1680         ulpi_null_phy_set_tristate(true);
1681         return 0;
1682 }
1683
1684 static int ulpi_null_phy_irq(struct tegra_usb_phy *phy)
1685 {
1686         usb_phy_fence_read(phy);
1687         return IRQ_HANDLED;
1688 }
1689
1690 static int ulpi_null_phy_restore(struct tegra_usb_phy *phy)
1691 {
1692         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
1693         unsigned long timeout;
1694         int ulpi_stp = ULPI_STP;
1695
1696         if (gpio_is_valid(config->phy_restore_gpio))
1697                 ulpi_stp = config->phy_restore_gpio;
1698
1699         /* disable ULPI pinmux bypass */
1700         ulpi_pinmux_bypass(phy, false);
1701
1702         /* driving linstate by GPIO */
1703         gpio_set_value(ULPI_D0, 0);
1704         gpio_set_value(ULPI_D1, 0);
1705
1706         /* driving DIR high */
1707         gpio_set_value(ULPI_DIR, 1);
1708
1709         /* remove ULPI tristate */
1710         ulpi_null_phy_set_tristate(false);
1711
1712         /* wait for STP high */
1713         timeout = jiffies + msecs_to_jiffies(25);
1714
1715         while (!gpio_get_value(ulpi_stp)) {
1716                 if (time_after(jiffies, timeout)) {
1717                         pr_warn("phy restore timeout\n");
1718                         return 1;
1719                 }
1720         }
1721
1722         return 0;
1723 }
1724
1725 static int ulpi_null_phy_lp0_resume(struct tegra_usb_phy *phy)
1726 {
1727         unsigned long val;
1728         void __iomem *base = phy->regs;
1729
1730         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1731
1732         val = readl(base + USB_USBCMD);
1733         val |= USB_USBCMD_RESET;
1734         writel(val, base + USB_USBCMD);
1735
1736         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1737                 USB_USBCMD_RESET, 0, 2500) < 0) {
1738                 pr_err("%s: timeout waiting for reset\n", __func__);
1739         }
1740
1741         val = readl(base + USB_USBMODE_REG_OFFSET);
1742         val &= ~USB_USBMODE_MASK;
1743         val |= USB_USBMODE_HOST;
1744         writel(val, base + USB_USBMODE_REG_OFFSET);
1745
1746         val = readl(base + USB_USBCMD);
1747         val |= USB_USBCMD_RS;
1748         writel(val, base + USB_USBCMD);
1749         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
1750                                                  USB_USBCMD_RS, 2000)) {
1751                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
1752                 return -ETIMEDOUT;
1753         }
1754
1755         /* Enable Port Power */
1756         val = readl(base + USB_PORTSC);
1757         val |= USB_PORTSC_PP;
1758         writel(val, base + USB_PORTSC);
1759         udelay(10);
1760
1761         ulpi_null_phy_restore(phy);
1762
1763         return 0;
1764 }
1765
1766 static int ulpi_null_phy_power_on(struct tegra_usb_phy *phy)
1767 {
1768         unsigned long val;
1769         void __iomem *base = phy->regs;
1770         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
1771
1772         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1773         if (phy->phy_clk_on) {
1774                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
1775                                                         __LINE__, phy->inst);
1776                 return 0;
1777         }
1778
1779         val = readl(base + USB_SUSP_CTRL);
1780         val |= UHSIC_RESET;
1781         writel(val, base + USB_SUSP_CTRL);
1782
1783         val = readl(base + ULPI_TIMING_CTRL_0);
1784         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
1785         writel(val, base + ULPI_TIMING_CTRL_0);
1786
1787         val = readl(base + USB_SUSP_CTRL);
1788         val |= ULPI_PHY_ENABLE;
1789         writel(val, base + USB_SUSP_CTRL);
1790         udelay(10);
1791
1792         /* set timming parameters */
1793         val = readl(base + ULPI_TIMING_CTRL_0);
1794         val |= ULPI_SHADOW_CLK_LOOPBACK_EN;
1795         val |= ULPI_SHADOW_CLK_SEL;
1796         val |= ULPI_LBK_PAD_EN;
1797         val |= ULPI_SHADOW_CLK_DELAY(config->shadow_clk_delay);
1798         val |= ULPI_CLOCK_OUT_DELAY(config->clock_out_delay);
1799         val |= ULPI_LBK_PAD_E_INPUT_OR;
1800         writel(val, base + ULPI_TIMING_CTRL_0);
1801
1802         writel(0, base + ULPI_TIMING_CTRL_1);
1803         udelay(10);
1804
1805         /* start internal 60MHz clock */
1806         val = readl(base + ULPIS2S_CTRL);
1807         val |= ULPIS2S_ENA;
1808         val |= ULPIS2S_SUPPORT_DISCONNECT;
1809         val |= ULPIS2S_SPARE((phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) ? 3 : 1);
1810         val |= ULPIS2S_PLLU_MASTER_BLASTER60;
1811         writel(val, base + ULPIS2S_CTRL);
1812
1813         /* select ULPI_CORE_CLK_SEL to SHADOW_CLK */
1814         val = readl(base + ULPI_TIMING_CTRL_0);
1815         val |= ULPI_CORE_CLK_SEL;
1816         writel(val, base + ULPI_TIMING_CTRL_0);
1817         udelay(10);
1818
1819         /* enable ULPI null phy clock - can't set the trimmers before this */
1820         val = readl(base + ULPI_TIMING_CTRL_0);
1821         val |= ULPI_CLK_OUT_ENA;
1822         writel(val, base + ULPI_TIMING_CTRL_0);
1823         udelay(10);
1824
1825         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
1826                                                  USB_PHY_CLK_VALID, 2500)) {
1827                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
1828                 return -ETIMEDOUT;
1829         }
1830
1831         /* set ULPI trimmers */
1832         ulpi_set_trimmer(phy);
1833
1834         if (!phy->ulpi_clk_padout_ena) {
1835                 val = readl(base + ULPI_TIMING_CTRL_0);
1836                 val |= ULPI_CLK_PADOUT_ENA;
1837                 writel(val, base + ULPI_TIMING_CTRL_0);
1838                 phy->ulpi_clk_padout_ena = true;
1839         } else {
1840                 if (!readl(base + USB_ASYNCLISTADDR))
1841                         ulpi_null_phy_lp0_resume(phy);
1842         }
1843         udelay(10);
1844
1845         phy->phy_clk_on = true;
1846         phy->hw_accessible = true;
1847
1848         return 0;
1849 }
1850
1851 static int ulpi_null_phy_pre_resume(struct tegra_usb_phy *phy,
1852                                     bool remote_wakeup)
1853 {
1854         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1855         ulpi_null_phy_obs_read();
1856         usb_phy_wait_for_sof(phy);
1857         ulpi_null_phy_obs_read();
1858         return 0;
1859 }
1860
1861 static int ulpi_null_phy_post_resume(struct tegra_usb_phy *phy)
1862 {
1863         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1864         ulpi_null_phy_obs_read();
1865         return 0;
1866 }
1867
1868 static int ulpi_null_phy_resume(struct tegra_usb_phy *phy)
1869 {
1870         unsigned long val;
1871         void __iomem *base = phy->regs;
1872
1873         if (!readl(base + USB_ASYNCLISTADDR)) {
1874                 /* enable ULPI CLK output pad */
1875                 val = readl(base + ULPI_TIMING_CTRL_0);
1876                 val |= ULPI_CLK_PADOUT_ENA;
1877                 writel(val, base + ULPI_TIMING_CTRL_0);
1878
1879                 /* enable ULPI pinmux bypass */
1880                 ulpi_pinmux_bypass(phy, true);
1881                 udelay(5);
1882         }
1883
1884         return 0;
1885 }
1886
1887
1888
1889 static struct tegra_usb_phy_ops utmi_phy_ops = {
1890         .open           = utmi_phy_open,
1891         .close          = utmi_phy_close,
1892         .irq            = utmi_phy_irq,
1893         .power_on       = utmi_phy_power_on,
1894         .power_off      = utmi_phy_power_off,
1895         .pre_resume = utmi_phy_pre_resume,
1896         .resume = utmi_phy_resume,
1897         .post_resume    = utmi_phy_post_resume,
1898         .charger_detect = utmi_phy_charger_detect,
1899         .post_suspend   = phy_post_suspend,
1900 };
1901
1902 static struct tegra_usb_phy_ops uhsic_phy_ops = {
1903         .open           = uhsic_phy_open,
1904         .irq            = uhsic_phy_irq,
1905         .power_on       = uhsic_phy_power_on,
1906         .power_off      = uhsic_phy_power_off,
1907         .pre_resume     = uhsic_phy_pre_resume,
1908         .resume         = uhsic_phy_resume,
1909         .post_resume    = uhsic_phy_post_resume,
1910         .port_power     = uhsic_phy_bus_port_power,
1911         .bus_reset      = uhsic_phy_bus_reset,
1912         .post_suspend   = phy_post_suspend,
1913 };
1914
1915 static struct tegra_usb_phy_ops ulpi_link_phy_ops = {
1916         .open           = ulpi_link_phy_open,
1917         .close  = ulpi_link_phy_close,
1918         .irq            = ulpi_link_phy_irq,
1919         .power_on       = ulpi_link_phy_power_on,
1920         .power_off      = ulpi_link_phy_power_off,
1921         .resume         = ulpi_link_phy_resume,
1922         .post_suspend   = phy_post_suspend,
1923 };
1924
1925 static struct tegra_usb_phy_ops ulpi_null_phy_ops = {
1926         .open           = ulpi_null_phy_open,
1927         .close          = ulpi_null_phy_close,
1928         .irq            = ulpi_null_phy_irq,
1929         .power_on       = ulpi_null_phy_power_on,
1930         .power_off      = ulpi_null_phy_power_off,
1931         .pre_resume = ulpi_null_phy_pre_resume,
1932         .resume = ulpi_null_phy_resume,
1933         .post_suspend   = phy_post_suspend,
1934         .post_resume = ulpi_null_phy_post_resume,
1935 };
1936
1937 static struct tegra_usb_phy_ops icusb_phy_ops;
1938
1939
1940 static struct tegra_usb_phy_ops *phy_ops[] = {
1941         [TEGRA_USB_PHY_INTF_UTMI] = &utmi_phy_ops,
1942         [TEGRA_USB_PHY_INTF_ULPI_LINK] = &ulpi_link_phy_ops,
1943         [TEGRA_USB_PHY_INTF_ULPI_NULL] = &ulpi_null_phy_ops,
1944         [TEGRA_USB_PHY_INTF_HSIC] = &uhsic_phy_ops,
1945         [TEGRA_USB_PHY_INTF_ICUSB] = &icusb_phy_ops,
1946 };
1947
1948 int tegra2_usb_phy_init_ops(struct tegra_usb_phy *phy)
1949 {
1950         phy->ops = phy_ops[phy->pdata->phy_intf];
1951
1952         return 0;
1953 }