arm: tegra: phy: enable wakeup event for usb phy
[linux-2.6.git] / arch / arm / mach-tegra / tegra2_usb_phy.c
1 /*
2  * arch/arm/mach-tegra/tegra2_usb_phy.c
3  *
4  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
5  *
6  *
7  * This software is licensed under the terms of the GNU General Public
8  * License version 2, as published by the Free Software Foundation, and
9  * may be copied, distributed, and modified under those terms.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17 #include <linux/resource.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/slab.h>
21 #include <linux/err.h>
22 #include <linux/platform_device.h>
23 #include <linux/io.h>
24 #include <linux/gpio.h>
25 #include <linux/usb/otg.h>
26 #include <linux/usb/ulpi.h>
27 #include <linux/interrupt.h>
28 #include <linux/clk.h>
29 #include <linux/regulator/consumer.h>
30 #include <linux/platform_data/tegra_usb.h>
31
32 #include <asm/mach-types.h>
33
34 #include <mach/clk.h>
35 #include <mach/iomap.h>
36 #include <mach/pinmux.h>
37 #include <mach/pinmux-tegra20.h>
38 #include <mach/usb_phy.h>
39
40 #include "tegra_usb_phy.h"
41 #include "gpio-names.h"
42 #include "fuse.h"
43
44 #define USB_USBCMD              0x140
45 #define   USB_USBCMD_RS         (1 << 0)
46 #define   USB_USBCMD_RESET      (1 << 1)
47
48 #define USB_USBSTS              0x144
49 #define   USB_USBSTS_PCI        (1 << 2)
50 #define   USB_USBSTS_SRI        (1 << 7)
51 #define   USB_USBSTS_HCH        (1 << 12)
52
53 #define USB_USBINTR             0x148
54
55 #define USB_ASYNCLISTADDR       0x158
56
57 #define USB_TXFILLTUNING                0x164
58 #define USB_FIFO_TXFILL_THRES(x)   (((x) & 0x1f) << 16)
59 #define USB_FIFO_TXFILL_MASK    0x3f0000
60
61 #define ULPI_VIEWPORT           0x170
62 #define   ULPI_WAKEUP           (1 << 31)
63 #define   ULPI_RUN              (1 << 30)
64 #define   ULPI_RD_WR            (1 << 29)
65
66 #define USB_PORTSC              0x184
67 #define   USB_PORTSC_PTS(x)     (((x) & 0x3) << 30)
68 #define   USB_PORTSC_PSPD(x)    (((x) & 0x3) << 26)
69 #define   USB_PORTSC_PHCD       (1 << 23)
70 #define   USB_PORTSC_WKOC       (1 << 22)
71 #define   USB_PORTSC_WKDS       (1 << 21)
72 #define   USB_PORTSC_WKCN       (1 << 20)
73 #define   USB_PORTSC_PTC(x)     (((x) & 0xf) << 16)
74 #define   USB_PORTSC_PP (1 << 12)
75 #define   USB_PORTSC_LS(x) (((x) & 0x3) << 10)
76 #define   USB_PORTSC_SUSP       (1 << 7)
77 #define   USB_PORTSC_RESUME     (1 << 6)
78 #define   USB_PORTSC_OCC        (1 << 5)
79 #define   USB_PORTSC_PEC        (1 << 3)
80 #define   USB_PORTSC_PE         (1 << 2)
81 #define   USB_PORTSC_CSC        (1 << 1)
82 #define   USB_PORTSC_CCS        (1 << 0)
83 #define   USB_PORTSC_RWC_BITS (USB_PORTSC_CSC | USB_PORTSC_PEC | USB_PORTSC_OCC)
84 #define   USB_PORTSC_PSPD_MASK  3
85
86 #define USB_USBMODE_REG_OFFSET  0x1a8
87 #define   USB_USBMODE_MASK              (3 << 0)
88 #define   USB_USBMODE_HOST              (3 << 0)
89 #define   USB_USBMODE_DEVICE    (2 << 0)
90
91 #define USB_SUSP_CTRL           0x400
92 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
93 #define   USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
94 #define   USB_SUSP_CLR          (1 << 5)
95 #define   USB_CLKEN             (1 << 6)
96 #define   USB_PHY_CLK_VALID (1 << 7)
97 #define   USB_PHY_CLK_VALID_INT_ENB    (1 << 9)
98 #define   UTMIP_RESET           (1 << 11)
99 #define   UHSIC_RESET           (1 << 11)
100 #define   UTMIP_PHY_ENABLE      (1 << 12)
101 #define   UHSIC_PHY_ENABLE      (1 << 12)
102 #define   ULPI_PHY_ENABLE       (1 << 13)
103 #define   USB_SUSP_SET          (1 << 14)
104 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
105 #define   USB_PHY_CLK_VALID_INT_STS     (1 << 8)
106
107 #define USB_PHY_VBUS_WAKEUP_ID  0x408
108 #define   VDAT_DET_INT_EN       (1 << 16)
109 #define   VDAT_DET_CHG_DET      (1 << 17)
110 #define   VDAT_DET_STS          (1 << 18)
111 #define   USB_ID_STATUS         (1 << 2)
112
113 #define USB1_LEGACY_CTRL        0x410
114 #define   USB1_NO_LEGACY_MODE                   (1 << 0)
115 #define   USB1_VBUS_SENSE_CTL_MASK              (3 << 1)
116 #define   USB1_VBUS_SENSE_CTL_VBUS_WAKEUP       (0 << 1)
117 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
118                                                 (1 << 1)
119 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD       (2 << 1)
120 #define   USB1_VBUS_SENSE_CTL_A_SESS_VLD        (3 << 1)
121
122 #define ULPIS2S_CTRL            0x418
123 #define   ULPIS2S_ENA                   (1 << 0)
124 #define   ULPIS2S_SUPPORT_DISCONNECT    (1 << 2)
125 #define   ULPIS2S_PLLU_MASTER_BLASTER60 (1 << 3)
126 #define   ULPIS2S_SPARE(x)              (((x) & 0xF) << 8)
127 #define   ULPIS2S_FORCE_ULPI_CLK_OUT    (1 << 12)
128 #define   ULPIS2S_DISCON_DONT_CHECK_SE0 (1 << 13)
129 #define   ULPIS2S_SUPPORT_HS_KEEP_ALIVE (1 << 14)
130 #define   ULPIS2S_DISABLE_STP_PU        (1 << 15)
131 #define   ULPIS2S_SLV0_CLAMP_XMIT       (1 << 16)
132
133 #define ULPI_TIMING_CTRL_0      0x424
134 #define   ULPI_CLOCK_OUT_DELAY(x)       ((x) & 0x1F)
135 #define   ULPI_OUTPUT_PINMUX_BYP        (1 << 10)
136 #define   ULPI_CLKOUT_PINMUX_BYP        (1 << 11)
137 #define   ULPI_SHADOW_CLK_LOOPBACK_EN   (1 << 12)
138 #define   ULPI_SHADOW_CLK_SEL           (1 << 13)
139 #define   ULPI_CORE_CLK_SEL             (1 << 14)
140 #define   ULPI_SHADOW_CLK_DELAY(x)      (((x) & 0x1F) << 16)
141 #define   ULPI_LBK_PAD_EN               (1 << 26)
142 #define   ULPI_LBK_PAD_E_INPUT_OR       (1 << 27)
143 #define   ULPI_CLK_OUT_ENA              (1 << 28)
144 #define   ULPI_CLK_PADOUT_ENA           (1 << 29)
145
146 #define ULPI_TIMING_CTRL_1      0x428
147 #define   ULPI_DATA_TRIMMER_LOAD        (1 << 0)
148 #define   ULPI_DATA_TRIMMER_SEL(x)      (((x) & 0x7) << 1)
149 #define   ULPI_STPDIRNXT_TRIMMER_LOAD   (1 << 16)
150 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
151 #define   ULPI_DIR_TRIMMER_LOAD         (1 << 24)
152 #define   ULPI_DIR_TRIMMER_SEL(x)       (((x) & 0x7) << 25)
153
154 #define UTMIP_PLL_CFG1          0x804
155 #define UHSIC_PLL_CFG1                          0x804
156 #define   UTMIP_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
157 #define   UTMIP_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 27)
158 #define   UHSIC_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
159 #define   UHSIC_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 14)
160
161 #define UTMIP_XCVR_UHSIC_HSRX_CFG0              0x808
162 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
163 #define   UHSIC_ELASTIC_UNDERRUN_LIMIT(x)       (((x) & 0x1f) << 2)
164 #define   UHSIC_ELASTIC_OVERRUN_LIMIT(x)        (((x) & 0x1f) << 8)
165 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
166 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
167 #define   UHSIC_IDLE_WAIT(x)                    (((x) & 0x1f) << 13)
168 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
169 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
170 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
171 #define   UTMIP_XCVR_LSBIAS_SEL                 (1 << 21)
172 #define   UTMIP_XCVR_SETUP_MSB(x)               (((x) & 0x7) << 22)
173 #define   UTMIP_XCVR_HSSLEW_MSB(x)              (((x) & 0x7f) << 25)
174 #define   UTMIP_XCVR_MAX_OFFSET         2
175 #define   UTMIP_XCVR_SETUP_MAX_VALUE    0x7f
176 #define   UTMIP_XCVR_SETUP_MIN_VALUE    0
177 #define   XCVR_SETUP_MSB_CALIB(x) ((x) >> 4)
178
179 #define UTMIP_BIAS_CFG0                 0x80c
180 #define   UTMIP_OTGPD                   (1 << 11)
181 #define   UTMIP_BIASPD                  (1 << 10)
182
183 #define UHSIC_HSRX_CFG1                         0x80c
184 #define   UHSIC_HS_SYNC_START_DLY(x)            (((x) & 0x1f) << 1)
185
186 #define UTMIP_HSRX_CFG0                 0x810
187 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
188 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
189
190 #define UTMIP_HSRX_CFG1                 0x814
191 #define UHSIC_MISC_CFG0                 0x814
192 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
193 #define   UHSIC_SUSPEND_EXIT_ON_EDGE            (1 << 7)
194 #define   UHSIC_DETECT_SHORT_CONNECT            (1 << 8)
195 #define   UHSIC_FORCE_XCVR_MODE                 (1 << 15)
196
197 #define UHSIC_MISC_CFG1                         0x818
198 #define   UHSIC_PLLU_STABLE_COUNT(x)            (((x) & 0xfff) << 2)
199
200 #define UHSIC_PADS_CFG0                         0x81c
201 #define   UHSIC_TX_RTUNEN                       0xf000
202 #define   UHSIC_TX_RTUNE(x)                     (((x) & 0xf) << 12)
203
204 #define UTMIP_TX_CFG0                           0x820
205 #define UHSIC_PADS_CFG1                         0x820
206 #define   UHSIC_PD_BG                           (1 << 2)
207 #define   UHSIC_PD_TX                           (1 << 3)
208 #define   UHSIC_PD_TRK                          (1 << 4)
209 #define   UHSIC_PD_RX                           (1 << 5)
210 #define   UHSIC_PD_ZI                           (1 << 6)
211 #define   UHSIC_RX_SEL                          (1 << 7)
212 #define   UHSIC_RPD_DATA                        (1 << 9)
213 #define   UHSIC_RPD_STROBE                      (1 << 10)
214 #define   UHSIC_RPU_DATA                        (1 << 11)
215 #define   UHSIC_RPU_STROBE                      (1 << 12)
216 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
217 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
218
219 #define UTMIP_MISC_CFG0         0x824
220 #define   UTMIP_DPDM_OBSERVE            (1 << 26)
221 #define   UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
222 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J   UTMIP_DPDM_OBSERVE_SEL(0xf)
223 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K   UTMIP_DPDM_OBSERVE_SEL(0xe)
224 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
225 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
226 #define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
227 #define   FORCE_PULLDN_DM       (1 << 8)
228 #define   FORCE_PULLDN_DP       (1 << 9)
229 #define   COMB_TERMS            (1 << 0)
230 #define   ALWAYS_FREE_RUNNING_TERMS (1 << 1)
231
232 #define USB1_PREFETCH_ID               6
233 #define USB2_PREFETCH_ID               18
234 #define USB3_PREFETCH_ID               17
235
236 #define UTMIP_MISC_CFG1         0x828
237 #define   UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18)
238 #define   UTMIP_PLLU_STABLE_COUNT(x)    (((x) & 0xfff) << 6)
239
240 #define UHSIC_STAT_CFG0         0x828
241 #define   UHSIC_CONNECT_DETECT          (1 << 0)
242
243 #define UTMIP_DEBOUNCE_CFG0 0x82c
244 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
245
246 #define UTMIP_BAT_CHRG_CFG0     0x830
247 #define   UTMIP_PD_CHRG                 (1 << 0)
248 #define   UTMIP_ON_SINK_EN              (1 << 2)
249 #define   UTMIP_OP_SRC_EN               (1 << 3)
250
251 #define UTMIP_SPARE_CFG0        0x834
252 #define   FUSE_SETUP_SEL                (1 << 3)
253 #define   FUSE_ATERM_SEL                (1 << 4)
254
255 #define UTMIP_XCVR_CFG1         0x838
256 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
257 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
258 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
259 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
260
261 #define UTMIP_BIAS_CFG1         0x83c
262 #define   UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
263
264 #define FUSE_USB_CALIB_0                0x1F0
265 #define FUSE_USB_CALIB_XCVR_SETUP(x)    (((x) & 0x7F) << 0)
266
267 #define APB_MISC_GP_OBSCTRL_0   0x818
268 #define APB_MISC_GP_OBSDATA_0   0x81c
269
270 /* ULPI GPIO */
271 #define ULPI_STP        TEGRA_GPIO_PY3
272 #define ULPI_DIR        TEGRA_GPIO_PY1
273 #define ULPI_D0         TEGRA_GPIO_PO1
274 #define ULPI_D1         TEGRA_GPIO_PO2
275
276 /* These values (in milli second) are taken from the battery charging spec */
277 #define TDP_SRC_ON_MS    100
278 #define TDPSRC_CON_MS    40
279
280 #ifdef DEBUG
281 #define DBG(stuff...)   pr_info("tegra2_usb_phy: " stuff)
282 #else
283 #define DBG(stuff...)   do {} while (0)
284 #endif
285
286 /* define HSIC phy params */
287 #define HSIC_SYNC_START_DELAY           9
288 #define HSIC_IDLE_WAIT_DELAY            17
289 #define HSIC_ELASTIC_UNDERRUN_LIMIT     16
290 #define HSIC_ELASTIC_OVERRUN_LIMIT      16
291
292 static DEFINE_SPINLOCK(utmip_pad_lock);
293 static int utmip_pad_count;
294 static int utmip_pad_state_on;
295
296 static struct tegra_xtal_freq utmip_freq_table[] = {
297         {
298                 .freq = 12000000,
299                 .enable_delay = 0x02,
300                 .stable_count = 0x2F,
301                 .active_delay = 0x04,
302                 .xtal_freq_count = 0x76,
303                 .debounce = 0x7530,
304                 .pdtrk_count = 5,
305         },
306         {
307                 .freq = 13000000,
308                 .enable_delay = 0x02,
309                 .stable_count = 0x33,
310                 .active_delay = 0x05,
311                 .xtal_freq_count = 0x7F,
312                 .debounce = 0x7EF4,
313                 .pdtrk_count = 5,
314         },
315         {
316                 .freq = 19200000,
317                 .enable_delay = 0x03,
318                 .stable_count = 0x4B,
319                 .active_delay = 0x06,
320                 .xtal_freq_count = 0xBB,
321                 .debounce = 0xBB80,
322                 .pdtrk_count = 7,
323         },
324         {
325                 .freq = 26000000,
326                 .enable_delay = 0x04,
327                 .stable_count = 0x66,
328                 .active_delay = 0x09,
329                 .xtal_freq_count = 0xFE,
330                 .debounce = 0xFDE8,
331                 .pdtrk_count = 9,
332         },
333 };
334
335 static struct tegra_xtal_freq uhsic_freq_table[] = {
336         {
337                 .freq = 12000000,
338                 .enable_delay = 0x02,
339                 .stable_count = 0x2F,
340                 .active_delay = 0x0,
341                 .xtal_freq_count = 0x1CA,
342         },
343         {
344                 .freq = 13000000,
345                 .enable_delay = 0x02,
346                 .stable_count = 0x33,
347                 .active_delay = 0x0,
348                 .xtal_freq_count = 0x1F0,
349         },
350         {
351                 .freq = 19200000,
352                 .enable_delay = 0x03,
353                 .stable_count = 0x4B,
354                 .active_delay = 0x0,
355                 .xtal_freq_count = 0x2DD,
356         },
357         {
358                 .freq = 26000000,
359                 .enable_delay = 0x04,
360                 .stable_count = 0x66,
361                 .active_delay = 0x0,
362                 .xtal_freq_count = 0x3E0,
363         },
364 };
365
366 static void usb_phy_fence_read(struct tegra_usb_phy *phy)
367 {
368         /* Fence read for coherency of AHB master intiated writes */
369         if (phy->inst == 0)
370                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB1_PREFETCH_ID));
371         else if (phy->inst == 1)
372                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB2_PREFETCH_ID));
373         else if (phy->inst == 2)
374                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB3_PREFETCH_ID));
375
376         return;
377 }
378
379 static int usb_phy_bringup_host_controller(struct tegra_usb_phy *phy)
380 {
381         unsigned long val;
382         void __iomem *base = phy->regs;
383
384         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
385         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d] - 0\n",
386                         readl(base + USB_USBSTS), readl(base + USB_PORTSC),
387                                                         phy->port_speed);
388
389         /* enable host mode */
390         val = readl(base + USB_USBMODE_REG_OFFSET);
391         val |= USB_USBMODE_HOST;
392         writel(val, base + USB_USBMODE_REG_OFFSET);
393
394         /* Enable Port Power */
395         val = readl(base + USB_PORTSC);
396         val |= USB_PORTSC_PP;
397         writel(val, base + USB_PORTSC);
398         udelay(10);
399
400         /* Check if the phy resume from LP0. When the phy resume from LP0
401          * USB register will be reset.to zero */
402         if (!readl(base + USB_ASYNCLISTADDR)) {
403                 val = readl(base + USB_USBCMD);
404                 val |= USB_USBCMD_RS;
405                 writel(val, base + USB_USBCMD);
406
407                 /* Program the field PTC based on the saved speed mode */
408                 val = readl(base + USB_PORTSC);
409                 val &= ~(USB_PORTSC_PTC(~0));
410                 if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH)
411                         val |= USB_PORTSC_PTC(5);
412                 else if (phy->port_speed == USB_PHY_PORT_SPEED_FULL)
413                         val |= USB_PORTSC_PTC(6);
414                 else if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
415                         val |= USB_PORTSC_PTC(7);
416                 writel(val, base + USB_PORTSC);
417                 udelay(10);
418
419                 /* Disable test mode by setting PTC field to NORMAL_OP */
420                 val = readl(base + USB_PORTSC);
421                 val &= ~(USB_PORTSC_PTC(~0));
422                 writel(val, base + USB_PORTSC);
423                 udelay(10);
424         }
425
426         /* Poll until CCS is enabled */
427         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
428                                                  USB_PORTSC_CCS, 2000)) {
429                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
430         }
431
432         /* Poll until PE is enabled */
433         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_PE,
434                                                  USB_PORTSC_PE, 2000)) {
435                 pr_err("%s: timeout waiting for USB_PORTSC_PE\n", __func__);
436         }
437
438         /* Clear the PCI status, to avoid an interrupt taken upon resume */
439         val = readl(base + USB_USBSTS);
440         val |= USB_USBSTS_PCI;
441         writel(val, base + USB_USBSTS);
442
443         /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
444         val = readl(base + USB_PORTSC);
445         if ((val & USB_PORTSC_PP) && (val & USB_PORTSC_PE)) {
446                 val |= USB_PORTSC_SUSP;
447                 writel(val, base + USB_PORTSC);
448                 /* Need a 4ms delay before the controller goes to suspend */
449                 mdelay(4);
450
451                 /* Wait until port suspend completes */
452                 if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_SUSP,
453                                                  USB_PORTSC_SUSP, 1000)) {
454                         pr_err("%s: timeout waiting for PORT_SUSPEND\n",
455                                                                 __func__);
456                 }
457         }
458
459         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
460                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
461
462         return 0;
463 }
464
465 static void usb_phy_wait_for_sof(struct tegra_usb_phy *phy)
466 {
467         unsigned long val;
468         void __iomem *base = phy->regs;
469
470         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
471         val = readl(base + USB_USBSTS);
472         writel(val, base + USB_USBSTS);
473         udelay(20);
474         /* wait for two SOFs */
475         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
476                 USB_USBSTS_SRI, 2500))
477                 pr_err("%s: timeout waiting for SOF\n", __func__);
478
479         val = readl(base + USB_USBSTS);
480         writel(val, base + USB_USBSTS);
481         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI, 0, 2500))
482                 pr_err("%s: timeout waiting for SOF\n", __func__);
483
484         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
485                         USB_USBSTS_SRI, 2500))
486                 pr_err("%s: timeout waiting for SOF\n", __func__);
487
488         udelay(20);
489 }
490
491 static unsigned int utmi_phy_xcvr_setup_value(struct tegra_usb_phy *phy)
492 {
493         struct tegra_utmi_config *cfg = &phy->pdata->u_cfg.utmi;
494         signed long val;
495
496         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
497         if (cfg->xcvr_use_fuses) {
498                 val = FUSE_USB_CALIB_XCVR_SETUP(
499                                 tegra_fuse_readl(FUSE_USB_CALIB_0));
500                 if (cfg->xcvr_setup_offset <= UTMIP_XCVR_MAX_OFFSET)
501                         val = val + cfg->xcvr_setup_offset;
502
503                 if (val > UTMIP_XCVR_SETUP_MAX_VALUE) {
504                         val = UTMIP_XCVR_SETUP_MAX_VALUE;
505                         pr_info("%s: reset XCVR_SETUP to max value\n",
506                                  __func__);
507                 } else if (val < UTMIP_XCVR_SETUP_MIN_VALUE) {
508                         val = UTMIP_XCVR_SETUP_MIN_VALUE;
509                         pr_info("%s: reset XCVR_SETUP to min value\n",
510                                  __func__);
511                 }
512         } else {
513                 val = cfg->xcvr_setup;
514         }
515
516         return (unsigned int) val;
517 }
518
519
520 static int utmi_phy_open(struct tegra_usb_phy *phy)
521 {
522         unsigned long parent_rate;
523         int i;
524
525         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
526         phy->utmi_pad_clk = clk_get_sys("utmip-pad", NULL);
527         if (IS_ERR(phy->utmi_pad_clk)) {
528                 pr_err("%s: can't get utmip pad clock\n", __func__);
529                 return PTR_ERR(phy->utmi_pad_clk);
530         }
531
532         phy->utmi_xcvr_setup = utmi_phy_xcvr_setup_value(phy);
533
534         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
535         for (i = 0; i < ARRAY_SIZE(utmip_freq_table); i++) {
536                 if (utmip_freq_table[i].freq == parent_rate) {
537                         phy->freq = &utmip_freq_table[i];
538                         break;
539                 }
540         }
541         if (!phy->freq) {
542                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
543                 return -EINVAL;
544         }
545
546         return 0;
547 }
548
549 static void utmi_phy_close(struct tegra_usb_phy *phy)
550 {
551         DBG("%s inst:[%d]\n", __func__, phy->inst);
552
553         clk_put(phy->utmi_pad_clk);
554 }
555
556 static int utmi_phy_pad_power_on(struct tegra_usb_phy *phy)
557 {
558         unsigned long val, flags;
559         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
560
561         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
562         clk_enable(phy->utmi_pad_clk);
563
564         spin_lock_irqsave(&utmip_pad_lock, flags);
565
566         utmip_pad_count++;
567         val = readl(pad_base + UTMIP_BIAS_CFG0);
568         val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
569         writel(val, pad_base + UTMIP_BIAS_CFG0);
570         utmip_pad_state_on = true;
571
572         spin_unlock_irqrestore(&utmip_pad_lock, flags);
573
574         clk_disable(phy->utmi_pad_clk);
575
576         return 0;
577 }
578
579 static int utmi_phy_pad_power_off(struct tegra_usb_phy *phy)
580 {
581         unsigned long val, flags;
582         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
583
584         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
585         clk_enable(phy->utmi_pad_clk);
586         spin_lock_irqsave(&utmip_pad_lock, flags);
587
588         if (!utmip_pad_count) {
589                 pr_err("%s: utmip pad already powered off\n", __func__);
590                 goto out;
591         }
592         if (--utmip_pad_count == 0) {
593                 val = readl(pad_base + UTMIP_BIAS_CFG0);
594                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
595                 writel(val, pad_base + UTMIP_BIAS_CFG0);
596                 utmip_pad_state_on = false;
597         }
598 out:
599         spin_unlock_irqrestore(&utmip_pad_lock, flags);
600         clk_disable(phy->utmi_pad_clk);
601
602         return 0;
603 }
604
605 static int utmi_phy_irq(struct tegra_usb_phy *phy)
606 {
607         void __iomem *base = phy->regs;
608         unsigned long val = 0;
609
610         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
611
612         usb_phy_fence_read(phy);
613         if (phy->pdata->u_data.host.hot_plug) {
614                 val = readl(base + USB_SUSP_CTRL);
615                 if ((val  & USB_PHY_CLK_VALID_INT_STS)) {
616                         val &= ~USB_PHY_CLK_VALID_INT_ENB |
617                                         USB_PHY_CLK_VALID_INT_STS;
618                         writel(val , (base + USB_SUSP_CTRL));
619
620                         val = readl(base + USB_USBSTS);
621                         if (!(val  & USB_USBSTS_PCI))
622                                 return IRQ_NONE;
623
624                         val = readl(base + USB_PORTSC);
625                         if (val & USB_PORTSC_CCS)
626                                 val &= ~USB_PORTSC_WKCN;
627                         else
628                                 val &= ~USB_PORTSC_WKDS;
629                         val &= ~USB_PORTSC_RWC_BITS;
630                         writel(val , (base + USB_PORTSC));
631
632                 } else if (!phy->phy_clk_on) {
633                         return IRQ_NONE;
634                 }
635         }
636
637         return IRQ_HANDLED;
638 }
639
640 static int phy_post_suspend(struct tegra_usb_phy *phy)
641 {
642
643         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
644         /* Need a 4ms delay for controller to suspend */
645         mdelay(4);
646         return 0;
647 }
648
649 static int utmi_phy_post_resume(struct tegra_usb_phy *phy)
650 {
651         unsigned long val;
652         void __iomem *base = phy->regs;
653
654         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
655
656         val = readl(base + UTMIP_TX_CFG0);
657         val &= ~UTMIP_HS_DISCON_DISABLE;
658         writel(val, base + UTMIP_TX_CFG0);
659         return 0;
660 }
661
662 static int utmi_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
663 {
664         unsigned long val;
665         void __iomem *base = phy->regs;
666
667         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
668         val = readl(base + UTMIP_TX_CFG0);
669         val |= UTMIP_HS_DISCON_DISABLE;
670         writel(val, base + UTMIP_TX_CFG0);
671
672         usb_phy_wait_for_sof(phy);
673
674         return 0;
675 }
676
677 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
678 {
679         unsigned long val;
680         void __iomem *base = phy->regs;
681
682         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
683         if (!phy->phy_clk_on) {
684                 DBG("%s(%d) inst:[%d] phy clk is already off\n",
685                                         __func__, __LINE__, phy->inst);
686                 return 0;
687         }
688
689         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
690                 val = readl(base + USB_SUSP_CTRL);
691                 val &= ~(USB_WAKEUP_DEBOUNCE_COUNT(~0));
692                 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
693                 writel(val, base + USB_SUSP_CTRL);
694
695                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
696                 val |= UTMIP_PD_CHRG;
697                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
698         }
699
700         if (!phy->pdata->u_data.host.hot_plug) {
701                 val = readl(base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
702                 val |= (UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
703                          UTMIP_FORCE_PDZI_POWERDOWN);
704                 writel(val, base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
705         }
706
707         val = readl(base + UTMIP_XCVR_CFG1);
708         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
709                    UTMIP_FORCE_PDDR_POWERDOWN;
710         writel(val, base + UTMIP_XCVR_CFG1);
711
712         if (phy->inst != 0) {
713                 val = readl(base + UTMIP_BIAS_CFG0);
714                 val |= UTMIP_OTGPD;
715                 writel(val, base + UTMIP_BIAS_CFG0);
716         }
717
718         phy->port_speed = (readl(base + USB_PORTSC) >> 26) &
719                         USB_PORTSC_PSPD_MASK;
720
721         if (phy->pdata->u_data.host.hot_plug) {
722                 bool enable_hotplug = true;
723                 /* if it is OTG port then make sure to enable hot-plug feature
724                    only if host adaptor is connected, i.e id is low */
725                 if (phy->pdata->port_otg) {
726                         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
727                         enable_hotplug = (val & USB_ID_STATUS) ? false : true;
728                 }
729                 if (enable_hotplug) {
730                         /* Enable wakeup event of device plug-in/plug-out */
731                         val = readl(base + USB_PORTSC);
732                         if (val & USB_PORTSC_CCS)
733                                 val |= USB_PORTSC_WKDS;
734                         else
735                                 val |= USB_PORTSC_WKCN;
736                         writel(val, base + USB_PORTSC);
737
738                         val = readl(base + USB_SUSP_CTRL);
739                         val |= USB_PHY_CLK_VALID_INT_ENB;
740                         writel(val, base + USB_SUSP_CTRL);
741                 } else {
742                         /* Disable PHY clock valid interrupts
743                                 while going into suspend*/
744                         val = readl(base + USB_SUSP_CTRL);
745                         val &= ~USB_PHY_CLK_VALID_INT_ENB;
746                         writel(val, base + USB_SUSP_CTRL);
747                 }
748         }
749
750         /* Disable PHY clock */
751         if (phy->inst == 2) {
752                 val = readl(base + USB_PORTSC);
753                 val |= USB_PORTSC_PHCD;
754                 writel(val, base + USB_PORTSC);
755         } else {
756                 val = readl(base + USB_SUSP_CTRL);
757                 val |= USB_SUSP_SET;
758                 writel(val, base + USB_SUSP_CTRL);
759                 udelay(10);
760                 val = readl(base + USB_SUSP_CTRL);
761                 val &= ~USB_SUSP_SET;
762                 writel(val, base + USB_SUSP_CTRL);
763         }
764
765         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
766                                                                 0, 2500))
767                 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
768
769         utmi_phy_pad_power_off(phy);
770
771         phy->phy_clk_on = false;
772         phy->hw_accessible = false;
773
774         DBG("%s(%d) inst:[%d]END\n", __func__, __LINE__, phy->inst);
775
776         return 0;
777 }
778
779 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
780 {
781         unsigned long val;
782         void __iomem *base = phy->regs;
783         struct tegra_utmi_config *config = &phy->pdata->u_cfg.utmi;
784         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
785         if (phy->phy_clk_on) {
786                 DBG("%s(%d) inst:[%d] phy clk is already on\n",
787                                         __func__, __LINE__, phy->inst);
788                 return 0;
789         }
790
791         val = readl(base + USB_SUSP_CTRL);
792         val |= UTMIP_RESET;
793         writel(val, base + USB_SUSP_CTRL);
794
795         val = readl(base + UTMIP_TX_CFG0);
796         val |= UTMIP_FS_PREABMLE_J;
797         writel(val, base + UTMIP_TX_CFG0);
798
799         val = readl(base + UTMIP_HSRX_CFG0);
800         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
801         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
802         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
803         writel(val, base + UTMIP_HSRX_CFG0);
804
805         val = readl(base + UTMIP_HSRX_CFG1);
806         val &= ~(UTMIP_HS_SYNC_START_DLY(~0));
807         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
808         writel(val, base + UTMIP_HSRX_CFG1);
809
810         val = readl(base + UTMIP_DEBOUNCE_CFG0);
811         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
812         val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
813         writel(val, base + UTMIP_DEBOUNCE_CFG0);
814
815         val = readl(base + UTMIP_MISC_CFG0);
816         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
817         writel(val, base + UTMIP_MISC_CFG0);
818
819         val = readl(base + UTMIP_MISC_CFG1);
820         val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) | UTMIP_PLLU_STABLE_COUNT(~0));
821         val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |
822                 UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count);
823         writel(val, base + UTMIP_MISC_CFG1);
824
825         val = readl(base + UTMIP_PLL_CFG1);
826         val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) | UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
827         val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |
828                 UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
829         writel(val, base + UTMIP_PLL_CFG1);
830
831         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
832                 val = readl(base + USB_SUSP_CTRL);
833                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
834                 writel(val, base + USB_SUSP_CTRL);
835
836                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
837                 val &= ~UTMIP_PD_CHRG;
838                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
839         } else {
840                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
841                 val |= UTMIP_PD_CHRG;
842                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
843         }
844
845         utmi_phy_pad_power_on(phy);
846
847         val = readl(base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
848         val &= ~(UTMIP_XCVR_LSBIAS_SEL | UTMIP_FORCE_PD_POWERDOWN |
849                  UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN |
850                  UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_LSFSLEW(~0) |
851                  UTMIP_XCVR_LSRSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
852         val |= UTMIP_XCVR_SETUP(phy->utmi_xcvr_setup);
853         val |= UTMIP_XCVR_SETUP_MSB(XCVR_SETUP_MSB_CALIB(phy->utmi_xcvr_setup));
854         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
855         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
856
857         writel(val, base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
858
859         val = readl(base + UTMIP_XCVR_CFG1);
860         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
861                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
862         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
863         writel(val, base + UTMIP_XCVR_CFG1);
864
865
866         val = readl(base + UTMIP_BIAS_CFG1);
867         val &= ~(UTMIP_BIAS_PDTRK_COUNT(~0));
868         val |= UTMIP_BIAS_PDTRK_COUNT(phy->freq->pdtrk_count);
869         writel(val, base + UTMIP_BIAS_CFG1);
870
871         val = readl(base + UTMIP_SPARE_CFG0);
872         val &= ~FUSE_SETUP_SEL;
873         writel(val, base + UTMIP_SPARE_CFG0);
874
875         val = readl(base + USB_SUSP_CTRL);
876         val |= UTMIP_PHY_ENABLE;
877         writel(val, base + USB_SUSP_CTRL);
878
879         val = readl(base + USB_SUSP_CTRL);
880         val &= ~UTMIP_RESET;
881         writel(val, base + USB_SUSP_CTRL);
882
883         if (phy->inst == 0) {
884                 val = readl(base + USB_SUSP_CTRL);
885                 val &= ~USB_SUSP_SET;
886                 writel(val, base + USB_SUSP_CTRL);
887         } else {
888                 val = readl(base + USB_PORTSC);
889                 val &= ~USB_PORTSC_PHCD;
890                 writel(val, base + USB_PORTSC);
891         }
892
893         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
894                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500))
895                 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
896
897         if (phy->inst == 2) {
898                 val = readl(base + USB_PORTSC);
899                 val &= ~(USB_PORTSC_PTS(~0));
900                 writel(val, base + USB_PORTSC);
901         }
902
903         phy->phy_clk_on = true;
904         phy->hw_accessible = true;
905
906         return 0;
907 }
908
909 static void utmi_phy_restore_start(struct tegra_usb_phy *phy)
910 {
911         unsigned long val;
912         void __iomem *base = phy->regs;
913
914         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
915         val = readl(base + UTMIP_MISC_CFG0);
916         val &= ~(UTMIP_DPDM_OBSERVE_SEL(~0));
917
918         if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
919                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
920         else
921                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
922         writel(val, base + UTMIP_MISC_CFG0);
923         udelay(1);
924
925         val = readl(base + UTMIP_MISC_CFG0);
926         val |= UTMIP_DPDM_OBSERVE;
927         writel(val, base + UTMIP_MISC_CFG0);
928         udelay(10);
929 }
930
931 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
932 {
933         unsigned long val;
934         void __iomem *base = phy->regs;
935
936         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
937         val = readl(base + UTMIP_MISC_CFG0);
938         val &= ~UTMIP_DPDM_OBSERVE;
939         writel(val, base + UTMIP_MISC_CFG0);
940         udelay(10);
941 }
942
943
944 static int utmi_phy_resume(struct tegra_usb_phy *phy)
945 {
946         int status = 0;
947         unsigned long val, flags;
948         void __iomem *base = phy->regs;
949         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
950
951         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
952         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) {
953                 if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
954                         utmi_phy_restore_start(phy);
955                         usb_phy_bringup_host_controller(phy);
956                         utmi_phy_restore_end(phy);
957                 } else {
958                         /* device is plugged in when system is in LP0 */
959                         /* bring up the controller from LP0*/
960                         val = readl(base + USB_USBCMD);
961                         val |= USB_USBCMD_RESET;
962                         writel(val, base + USB_USBCMD);
963
964                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
965                                 USB_USBCMD_RESET, 0, 2500) < 0) {
966                                 pr_err("%s: timeout waiting for reset\n",
967                                         __func__);
968                         }
969
970                         val = readl(base + USB_USBMODE_REG_OFFSET);
971                         val &= ~USB_USBMODE_MASK;
972                         val |= USB_USBMODE_HOST;
973                         writel(val, base + USB_USBMODE_REG_OFFSET);
974
975                         if (phy->inst == 2) {
976                                 val = readl(base + USB_PORTSC);
977                                 val &= ~USB_PORTSC_PTS(~0);
978                                 writel(val, base + USB_PORTSC);
979                         }
980                         writel(USB_USBCMD_RS, base + USB_USBCMD);
981
982                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
983                                 USB_USBCMD_RS, USB_USBCMD_RS, 2500) < 0) {
984                                 pr_err("%s: timeout waiting for run bit\n",
985                                         __func__);
986                         }
987
988                         /* Enable Port Power */
989                         val = readl(base + USB_PORTSC);
990                         val |= USB_PORTSC_PP;
991                         writel(val, base + USB_PORTSC);
992                         udelay(10);
993
994                         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
995                                 readl(base + USB_USBSTS),
996                                 readl(base + USB_PORTSC));
997                 }
998         } else {
999                 /* Restoring the pad powers */
1000                 clk_enable(phy->utmi_pad_clk);
1001
1002                 spin_lock_irqsave(&utmip_pad_lock, flags);
1003
1004                 val = readl(pad_base + UTMIP_BIAS_CFG0);
1005                 if (utmip_pad_state_on)
1006                         val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
1007                 else
1008                         val |= (UTMIP_OTGPD | UTMIP_BIASPD);
1009                 writel(val, pad_base + UTMIP_BIAS_CFG0);
1010
1011                 spin_unlock_irqrestore(&utmip_pad_lock, flags);
1012                 clk_disable(phy->utmi_pad_clk);
1013         }
1014
1015         return status;
1016 }
1017
1018 static bool utmi_phy_charger_detect(struct tegra_usb_phy *phy)
1019 {
1020         unsigned long val;
1021         void __iomem *base = phy->regs;
1022         bool status;
1023
1024         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1025         /* Enable charger detection logic */
1026         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1027         val |= UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN;
1028         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1029
1030         /* Source should be on for 100 ms as per USB charging spec */
1031         msleep(TDP_SRC_ON_MS);
1032
1033         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1034         /* If charger is not connected disable the interrupt */
1035         val &= ~VDAT_DET_INT_EN;
1036         val |= VDAT_DET_CHG_DET;
1037         writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
1038
1039         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1040         if (val & VDAT_DET_STS)
1041                 status = true;
1042         else
1043                 status = false;
1044
1045         /* Disable charger detection logic */
1046         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1047         val &= ~(UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN);
1048         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1049
1050         /* Delay of 40 ms before we pull the D+ as per battery charger spec */
1051         msleep(TDPSRC_CON_MS);
1052
1053         return status;
1054 }
1055
1056
1057 static int uhsic_phy_open(struct tegra_usb_phy *phy)
1058 {
1059         unsigned long parent_rate;
1060         int i;
1061
1062         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1063         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
1064         for (i = 0; i < ARRAY_SIZE(uhsic_freq_table); i++) {
1065                 if (uhsic_freq_table[i].freq == parent_rate) {
1066                         phy->freq = &uhsic_freq_table[i];
1067                         break;
1068                 }
1069         }
1070         if (!phy->freq) {
1071                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
1072                 return -EINVAL;
1073         }
1074
1075         return 0;
1076 }
1077
1078 static int uhsic_phy_irq(struct tegra_usb_phy *phy)
1079 {
1080         usb_phy_fence_read(phy);
1081         return IRQ_HANDLED;
1082 }
1083
1084 static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
1085 {
1086         unsigned long val;
1087         void __iomem *base = phy->regs;
1088
1089         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1090         if (phy->phy_clk_on) {
1091                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
1092                                                         __LINE__, phy->inst);
1093                 return 0;
1094         }
1095
1096         val = readl(base + UHSIC_PADS_CFG1);
1097         val &= ~(UHSIC_PD_BG | UHSIC_PD_TX | UHSIC_PD_TRK | UHSIC_PD_RX |
1098                         UHSIC_PD_ZI | UHSIC_RPD_DATA | UHSIC_RPD_STROBE);
1099         val |= UHSIC_RX_SEL;
1100         writel(val, base + UHSIC_PADS_CFG1);
1101         udelay(2);
1102
1103         val = readl(base + USB_SUSP_CTRL);
1104         val |= UHSIC_RESET;
1105         writel(val, base + USB_SUSP_CTRL);
1106         udelay(30);
1107
1108         val = readl(base + USB_SUSP_CTRL);
1109         val |= UHSIC_PHY_ENABLE;
1110         writel(val, base + USB_SUSP_CTRL);
1111
1112         val = readl(base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
1113         val |= UHSIC_IDLE_WAIT(HSIC_IDLE_WAIT_DELAY);
1114         val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(HSIC_ELASTIC_UNDERRUN_LIMIT);
1115         val |= UHSIC_ELASTIC_OVERRUN_LIMIT(HSIC_ELASTIC_OVERRUN_LIMIT);
1116         writel(val, base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
1117
1118         val = readl(base + UHSIC_HSRX_CFG1);
1119         val |= UHSIC_HS_SYNC_START_DLY(HSIC_SYNC_START_DELAY);
1120         writel(val, base + UHSIC_HSRX_CFG1);
1121
1122         val = readl(base + UHSIC_MISC_CFG0);
1123         val |= UHSIC_SUSPEND_EXIT_ON_EDGE;
1124         writel(val, base + UHSIC_MISC_CFG0);
1125
1126         val = readl(base + UHSIC_MISC_CFG1);
1127         val |= UHSIC_PLLU_STABLE_COUNT(phy->freq->stable_count);
1128         writel(val, base + UHSIC_MISC_CFG1);
1129
1130         val = readl(base + UHSIC_PLL_CFG1);
1131         val |= UHSIC_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
1132         val |= UHSIC_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count);
1133         writel(val, base + UHSIC_PLL_CFG1);
1134
1135         val = readl(base + USB_SUSP_CTRL);
1136         val &= ~(UHSIC_RESET);
1137         writel(val, base + USB_SUSP_CTRL);
1138         udelay(2);
1139
1140         val = readl(base + USB_PORTSC);
1141         val &= ~(USB_PORTSC_PTS(~0));
1142         writel(val, base + USB_PORTSC);
1143
1144         val = readl(base + USB_TXFILLTUNING);
1145         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
1146                 val = USB_FIFO_TXFILL_THRES(0x10);
1147                 writel(val, base + USB_TXFILLTUNING);
1148         }
1149
1150         val = readl(base + USB_PORTSC);
1151         val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN);
1152         writel(val, base + USB_PORTSC);
1153
1154         val = readl(base + UHSIC_PADS_CFG0);
1155         val &= ~(UHSIC_TX_RTUNEN);
1156         /* set Rtune impedance to 40 ohm */
1157         val |= UHSIC_TX_RTUNE(0);
1158         writel(val, base + UHSIC_PADS_CFG0);
1159
1160         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
1161                                                 USB_PHY_CLK_VALID, 2500)) {
1162                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
1163                 return -ETIMEDOUT;
1164         }
1165
1166         phy->phy_clk_on = true;
1167         phy->hw_accessible = true;
1168
1169         return 0;
1170 }
1171
1172 static int uhsic_phy_power_off(struct tegra_usb_phy *phy)
1173 {
1174         unsigned long val;
1175         void __iomem *base = phy->regs;
1176
1177         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1178         if (!phy->phy_clk_on) {
1179                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
1180                                                         __LINE__, phy->inst);
1181                 return 0;
1182         }
1183
1184         val = readl(base + UHSIC_PADS_CFG1);
1185         val &= ~UHSIC_RPU_STROBE;
1186         val |= UHSIC_RPD_STROBE;
1187         writel(val, base + UHSIC_PADS_CFG1);
1188
1189         val = readl(base + USB_SUSP_CTRL);
1190         val |= UHSIC_RESET;
1191         writel(val, base + USB_SUSP_CTRL);
1192         udelay(30);
1193
1194         val = readl(base + USB_SUSP_CTRL);
1195         val &= ~UHSIC_PHY_ENABLE;
1196         writel(val, base + USB_SUSP_CTRL);
1197
1198         phy->phy_clk_on = false;
1199         phy->hw_accessible = false;
1200
1201         return 0;
1202 }
1203
1204 static int uhsic_phy_bus_port_power(struct tegra_usb_phy *phy)
1205 {
1206         unsigned long val;
1207         void __iomem *base = phy->regs;
1208
1209         val = readl(base + UHSIC_MISC_CFG0);
1210         val |= UHSIC_DETECT_SHORT_CONNECT;
1211         writel(val, base + UHSIC_MISC_CFG0);
1212         udelay(1);
1213
1214         val = readl(base + UHSIC_MISC_CFG0);
1215         val |= UHSIC_FORCE_XCVR_MODE;
1216         writel(val, base + UHSIC_MISC_CFG0);
1217
1218         val = readl(base + UHSIC_PADS_CFG1);
1219         val &= ~UHSIC_RPD_STROBE;
1220         val |= UHSIC_RPU_STROBE;
1221         writel(val, base + UHSIC_PADS_CFG1);
1222
1223         val = readl(base + USB_USBCMD);
1224         val &= ~USB_USBCMD_RS;
1225         writel(val, base + USB_USBCMD);
1226
1227         if (phy->pdata->ops && phy->pdata->ops->port_power)
1228                 phy->pdata->ops->port_power();
1229
1230         if (usb_phy_reg_status_wait(base + UHSIC_STAT_CFG0,
1231                         UHSIC_CONNECT_DETECT, UHSIC_CONNECT_DETECT, 2000)) {
1232                 pr_err("%s: timeout waiting for UHSIC_CONNECT_DETECT\n",
1233                                                                 __func__);
1234                 return -ETIMEDOUT;
1235         }
1236
1237 /* FIXME : need to check whether this piece is required or not
1238         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_LS(2),
1239                                                 USB_PORTSC_LS(2), 2000)) {
1240                 pr_err("%s: timeout waiting for dplus state\n", __func__);
1241                 return -ETIMEDOUT;
1242         }
1243 */
1244         return 0;
1245 }
1246
1247
1248 static int uhsic_phy_bus_reset(struct tegra_usb_phy *phy)
1249 {
1250         unsigned long val;
1251         void __iomem *base = phy->regs;
1252
1253         val = readl(base + USB_PORTSC);
1254         val |= USB_PORTSC_PTC(5);
1255         writel(val, base + USB_PORTSC);
1256         udelay(2);
1257
1258         val = readl(base + USB_PORTSC);
1259         val &= ~(USB_PORTSC_PTC(~0));
1260         writel(val, base + USB_PORTSC);
1261         udelay(2);
1262
1263         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_LS(0),
1264                                                  0, 2000)) {
1265                 pr_err("%s: timeout waiting for USB_PORTSC_LS\n", __func__);
1266                 return -ETIMEDOUT;
1267         }
1268
1269         /* Poll until CCS is enabled */
1270         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
1271                                                  USB_PORTSC_CCS, 2000)) {
1272                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
1273                 return -ETIMEDOUT;
1274         }
1275
1276         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_PSPD(2),
1277                                                  USB_PORTSC_PSPD(2), 2000)) {
1278                 pr_err("%s: timeout waiting for USB_PORTSC_PSPD\n", __func__);
1279                 return -ETIMEDOUT;
1280         }
1281
1282         val = readl(base + USB_USBCMD);
1283         val &= ~USB_USBCMD_RS;
1284         writel(val, base + USB_USBCMD);
1285
1286         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
1287                                                  USB_USBSTS_HCH, 2000)) {
1288                 pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
1289                 return -ETIMEDOUT;
1290         }
1291
1292         val = readl(base + UHSIC_PADS_CFG1);
1293         val &= ~UHSIC_RPU_STROBE;
1294         val |= UHSIC_RPD_STROBE;
1295         writel(val, base + UHSIC_PADS_CFG1);
1296
1297         mdelay(50);
1298
1299         val = readl(base + UHSIC_PADS_CFG1);
1300         val &= ~UHSIC_RPD_STROBE;
1301         val |= UHSIC_RPU_STROBE;
1302         writel(val, base + UHSIC_PADS_CFG1);
1303
1304         val = readl(base + USB_USBCMD);
1305         val |= USB_USBCMD_RS;
1306         writel(val, base + USB_USBCMD);
1307
1308         val = readl(base + UHSIC_PADS_CFG1);
1309         val &= ~UHSIC_RPU_STROBE;
1310         writel(val, base + UHSIC_PADS_CFG1);
1311
1312         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
1313                                                  USB_USBCMD_RS, 2000)) {
1314                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
1315                 return -ETIMEDOUT;
1316         }
1317
1318         return 0;
1319 }
1320
1321
1322 static int uhsic_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1323 {
1324         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1325         usb_phy_wait_for_sof(phy);
1326
1327         return 0;
1328 }
1329
1330 static int uhsic_phy_resume(struct tegra_usb_phy *phy)
1331 {
1332         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1333         uhsic_phy_bus_port_power(phy);
1334
1335         return 0;
1336 }
1337
1338
1339 static int uhsic_phy_post_resume(struct tegra_usb_phy *phy)
1340 {
1341         unsigned long val;
1342         void __iomem *base = phy->regs;
1343
1344         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1345         val = readl(base + USB_TXFILLTUNING);
1346         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
1347                 val = USB_FIFO_TXFILL_THRES(0x10);
1348                 writel(val, base + USB_TXFILLTUNING);
1349         }
1350
1351         return 0;
1352 }
1353
1354 static void ulpi_set_trimmer(struct tegra_usb_phy *phy)
1355 {
1356         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
1357         void __iomem *base = phy->regs;
1358         unsigned long val;
1359
1360         val = ULPI_DATA_TRIMMER_SEL(config->data_trimmer);
1361         val |= ULPI_STPDIRNXT_TRIMMER_SEL(config->stpdirnxt_trimmer);
1362         val |= ULPI_DIR_TRIMMER_SEL(config->dir_trimmer);
1363         writel(val, base + ULPI_TIMING_CTRL_1);
1364         udelay(10);
1365
1366         val |= ULPI_DATA_TRIMMER_LOAD;
1367         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
1368         val |= ULPI_DIR_TRIMMER_LOAD;
1369         writel(val, base + ULPI_TIMING_CTRL_1);
1370 }
1371
1372
1373 static int ulpi_link_phy_open(struct tegra_usb_phy *phy)
1374 {
1375         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
1376         int err = 0;
1377
1378         phy->ulpi_clk = NULL;
1379
1380         if (config->clk) {
1381                 phy->ulpi_clk = clk_get_sys(NULL, config->clk);
1382                 if (IS_ERR(phy->ulpi_clk)) {
1383                         pr_err("%s: can't get ulpi clock\n", __func__);
1384                         err = -ENXIO;
1385                 }
1386         }
1387
1388         phy->ulpi_vp = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
1389         phy->ulpi_vp->io_priv = phy->regs + ULPI_VIEWPORT;
1390         phy->linkphy_init = true;
1391         return err;
1392 }
1393
1394 static void ulpi_link_phy_close(struct tegra_usb_phy *phy)
1395 {
1396         DBG("%s inst:[%d]\n", __func__, phy->inst);
1397         if (phy->ulpi_clk)
1398                 clk_put(phy->ulpi_clk);
1399 }
1400
1401 static int ulpi_link_phy_irq(struct tegra_usb_phy *phy)
1402 {
1403         usb_phy_fence_read(phy);
1404         return IRQ_HANDLED;
1405 }
1406
1407 static int ulpi_link_phy_power_off(struct tegra_usb_phy *phy)
1408 {
1409         unsigned long val;
1410         void __iomem *base = phy->regs;
1411         int ret;
1412
1413         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1414         if (!phy->phy_clk_on) {
1415                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
1416                                                         __LINE__, phy->inst);
1417                 return 0;
1418         }
1419
1420         /* Disable VbusValid, SessEnd comparators */
1421         ret = usb_phy_io_write(phy->ulpi_vp, 0x00, 0x0D);
1422         if (ret)
1423                 pr_err("%s: ulpi write 0x0D failed\n", __func__);
1424
1425         ret = usb_phy_io_write(phy->ulpi_vp, 0x00, 0x10);
1426         if (ret)
1427                 pr_err("%s: ulpi write 0x10 failed\n", __func__);
1428
1429         /* Disable IdFloat comparator */
1430         ret = usb_phy_io_write(phy->ulpi_vp, 0x00, 0x19);
1431         if (ret)
1432                 pr_err("%s: ulpi write 0x19 failed\n", __func__);
1433
1434         ret = usb_phy_io_write(phy->ulpi_vp, 0x00, 0x1D);
1435         if (ret)
1436                 pr_err("%s: ulpi write 0x1D failed\n", __func__);
1437
1438         phy->port_speed = (readl(base + USB_PORTSC) >> 26) &
1439                         USB_PORTSC_PSPD_MASK;
1440
1441         /* Clear WKCN/WKDS/WKOC wake-on events that can cause the USB
1442          * Controller to immediately bring the ULPI PHY out of low power
1443          */
1444         val = readl(base + USB_PORTSC);
1445         val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN);
1446         writel(val, base + USB_PORTSC);
1447
1448         /* Put the PHY in the low power mode */
1449         val = readl(base + USB_PORTSC);
1450         val |= USB_PORTSC_PHCD;
1451         writel(val, base + USB_PORTSC);
1452
1453         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
1454                                                          0, 2500)) {
1455                 pr_err("%s: timeout waiting for phy to stop\n", __func__);
1456         }
1457
1458         if (phy->ulpi_clk)
1459                 clk_disable(phy->ulpi_clk);
1460
1461         phy->phy_clk_on = false;
1462         phy->hw_accessible = false;
1463
1464         return 0;
1465 }
1466
1467 static int ulpi_link_phy_power_on(struct tegra_usb_phy *phy)
1468 {
1469         int ret;
1470         unsigned long val;
1471         void __iomem *base = phy->regs;
1472
1473         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1474         if (phy->phy_clk_on) {
1475                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
1476                                                         __LINE__, phy->inst);
1477                 return 0;
1478         }
1479
1480         if (phy->ulpi_clk) {
1481                 clk_enable(phy->ulpi_clk);
1482                 mdelay(1);
1483         }
1484
1485         val = readl(base + USB_SUSP_CTRL);
1486
1487         /* Case for lp0 */
1488         if (!(val & UHSIC_RESET)) {
1489                 val |= UHSIC_RESET;
1490                 writel(val, base + USB_SUSP_CTRL);
1491
1492                 val = 0;
1493                 writel(val, base + ULPI_TIMING_CTRL_1);
1494
1495                 ulpi_set_trimmer(phy);
1496
1497                 val = readl(base + ULPI_TIMING_CTRL_0);
1498                 val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
1499                 writel(val, base + ULPI_TIMING_CTRL_0);
1500 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1501                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAA, TEGRA_TRI_NORMAL);
1502                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAB, TEGRA_TRI_NORMAL);
1503                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_UDA, TEGRA_TRI_NORMAL);
1504 #endif
1505                 val = readl(base + USB_SUSP_CTRL);
1506                 val |= ULPI_PHY_ENABLE;
1507                 writel(val, base + USB_SUSP_CTRL);
1508
1509                 if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1510                         USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500) < 0)
1511                         pr_err("%s: timeout waiting for phy" \
1512                         "to stabilize\n", __func__);
1513
1514                 val = readl(base + USB_TXFILLTUNING);
1515                 if ((val & USB_FIFO_TXFILL_MASK) !=
1516                                 USB_FIFO_TXFILL_THRES(0x10)) {
1517                         val = USB_FIFO_TXFILL_THRES(0x10);
1518                         writel(val, base + USB_TXFILLTUNING);
1519                 }
1520         } else {
1521         /* Case for auto resume*/
1522                 val = readl(base + USB_SUSP_CTRL);
1523                 val |= USB_SUSP_CLR;
1524                 writel(val, base + USB_SUSP_CTRL);
1525
1526                 if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1527                         USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500) < 0)
1528                         pr_err("%s: timeout waiting for phy" \
1529                                         "to stabilize\n", __func__);
1530
1531                 if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1532                         USB_CLKEN, USB_CLKEN, 2500) < 0)
1533                         pr_err("%s: timeout waiting for AHB clock\n", __func__);
1534
1535                 val = readl(base + USB_SUSP_CTRL);
1536                 val &= ~USB_SUSP_CLR;
1537                 writel(val, base + USB_SUSP_CTRL);
1538         }
1539         if (phy->linkphy_init) {
1540                 /* To be done only incase of coldboot*/
1541                 /* Fix VbusInvalid due to floating VBUS */
1542                 ret = usb_phy_io_write(phy->ulpi_vp, 0x40, 0x08);
1543                 if (ret) {
1544                         pr_err("%s: ulpi write failed\n", __func__);
1545                         return ret;
1546                 }
1547
1548                 ret = usb_phy_io_write(phy->ulpi_vp, 0x80, 0x0B);
1549                 if (ret) {
1550                         pr_err("%s: ulpi write failed\n", __func__);
1551                         return ret;
1552                 }
1553                 phy->linkphy_init = false;
1554         }
1555
1556         val = readl(base + USB_PORTSC);
1557         val |= USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN;
1558         writel(val, base + USB_PORTSC);
1559
1560         phy->phy_clk_on = true;
1561         phy->hw_accessible = true;
1562
1563         return 0;
1564 }
1565
1566 static inline void ulpi_link_phy_set_tristate(bool enable)
1567 {
1568 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1569         int tristate = (enable) ? TEGRA_TRI_TRISTATE : TEGRA_TRI_NORMAL;
1570
1571         tegra_pinmux_set_tristate(TEGRA_PINGROUP_CDEV2, tristate);
1572         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAA, tristate);
1573         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAB, tristate);
1574         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UDA, tristate);
1575 #endif
1576 }
1577
1578 static void ulpi_link_phy_restore_start(struct tegra_usb_phy *phy)
1579 {
1580         unsigned long val;
1581         void __iomem *base = phy->regs;
1582
1583         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1584
1585         /*Tristate ulpi interface before USB controller resume*/
1586         ulpi_link_phy_set_tristate(true);
1587
1588         val = readl(base + ULPI_TIMING_CTRL_0);
1589         val &= ~ULPI_OUTPUT_PINMUX_BYP;
1590         writel(val, base + ULPI_TIMING_CTRL_0);
1591 }
1592
1593 static void ulpi_link_phy_restore_end(struct tegra_usb_phy *phy)
1594 {
1595         unsigned long val;
1596         void __iomem *base = phy->regs;
1597         int ret;
1598
1599         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1600
1601         val = readl(base + ULPI_TIMING_CTRL_0);
1602         val |= ULPI_OUTPUT_PINMUX_BYP;
1603         writel(val, base + ULPI_TIMING_CTRL_0);
1604
1605         ulpi_link_phy_set_tristate(false);
1606
1607         udelay(10);
1608         ret = usb_phy_io_write(phy->ulpi_vp, 0x55, 0x04);
1609         if (ret) {
1610                 pr_err("%s: ulpi write failed\n", __func__);
1611                 return;
1612         }
1613 }
1614
1615 static int ulpi_link_phy_resume(struct tegra_usb_phy *phy)
1616 {
1617         int status = 0;
1618
1619         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1620         if (phy->pdata->u_data.host.power_off_on_suspend) {
1621                 status = ulpi_link_phy_power_on(phy);
1622                 if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
1623                         ulpi_link_phy_restore_start(phy);
1624                         usb_phy_bringup_host_controller(phy);
1625                         ulpi_link_phy_restore_end(phy);
1626                 }
1627         }
1628
1629         return status;
1630 }
1631
1632 static int ulpi_link_phy_pre_resume(struct tegra_usb_phy *phy,
1633                         bool remote_wakeup)
1634 {
1635         int status = 0;
1636         unsigned long val;
1637         void __iomem *base = phy->regs;
1638         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1639
1640         val = readl(base + USB_PORTSC);
1641         if (val & USB_PORTSC_RESUME) {
1642
1643                 val = readl(base + USB_USBCMD);
1644                 val &= ~USB_USBCMD_RS;
1645                 writel(val, base + USB_USBCMD);
1646
1647                 /* detect remote wakeup */
1648                 msleep(20);
1649
1650                 val = readl(base + USB_PORTSC);
1651
1652                 /* Poll until the controller clears RESUME and SUSPEND */
1653                 if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1654                         USB_PORTSC_RESUME, 0, 2500))
1655                         pr_err("%s: timeout waiting for RESUME\n", __func__);
1656                 if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1657                         USB_PORTSC_SUSP, 0, 2500))
1658                         pr_err("%s: timeout waiting for SUSPEND\n", __func__);
1659
1660                 /* Since we skip remote wakeup event,
1661                 put controller in suspend again and
1662                 resume port later */
1663                 val = readl(base + USB_PORTSC);
1664                 val |= USB_PORTSC_SUSP;
1665                 writel(val, base + USB_PORTSC);
1666                 mdelay(4);
1667                 /* Wait until port suspend completes */
1668                 if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1669                         USB_PORTSC_SUSP, USB_PORTSC_SUSP, 2500))
1670                         pr_err("%s: timeout waiting for" \
1671                                 "PORT_SUSPEND\n", __func__);
1672
1673                 /* Disable interrupts */
1674                 writel(0, base + USB_USBINTR);
1675                 /* Clear the run bit to stop SOFs - 2LS WAR */
1676                 val = readl(base + USB_USBCMD);
1677                 val &= ~USB_USBCMD_RS;
1678                 writel(val, base + USB_USBCMD);
1679                 if (usb_phy_reg_status_wait(base + USB_USBSTS,
1680                         USB_USBSTS_HCH, USB_USBSTS_HCH, 2000)) {
1681                         pr_err("%s: timeout waiting for" \
1682                                 "USB_USBSTS_HCH\n", __func__);
1683                 }
1684                 usb_phy_wait_for_sof(phy);
1685
1686                 val = readl(base + USB_USBCMD);
1687                 val |= USB_USBCMD_RS;
1688                 writel(val, base + USB_USBCMD);
1689         }
1690         return status;
1691 }
1692
1693
1694 static inline void ulpi_pinmux_bypass(struct tegra_usb_phy *phy,
1695         bool enable)
1696 {
1697         unsigned long val;
1698         void __iomem *base = phy->regs;
1699
1700         val = readl(base + ULPI_TIMING_CTRL_0);
1701
1702         if (enable)
1703                 val |= ULPI_OUTPUT_PINMUX_BYP;
1704         else
1705                 val &= ~ULPI_OUTPUT_PINMUX_BYP;
1706
1707         writel(val, base + ULPI_TIMING_CTRL_0);
1708 }
1709
1710 static inline void ulpi_null_phy_set_tristate(bool enable)
1711 {
1712 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1713         int tristate = (enable) ? TEGRA_TRI_TRISTATE : TEGRA_TRI_NORMAL;
1714
1715         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UDA, tristate);
1716         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAA, tristate);
1717         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAB, tristate);
1718 #endif
1719 }
1720
1721 static void ulpi_null_phy_obs_read(void)
1722 {
1723         static void __iomem *apb_misc;
1724         unsigned slv0_obs, s2s_obs;
1725
1726         if (!apb_misc)
1727                 apb_misc = ioremap(TEGRA_APB_MISC_BASE, TEGRA_APB_MISC_SIZE);
1728
1729         writel(0x80b10034, apb_misc + APB_MISC_GP_OBSCTRL_0);
1730         slv0_obs = readl(apb_misc + APB_MISC_GP_OBSDATA_0);
1731
1732         writel(0x80b10038, apb_misc + APB_MISC_GP_OBSCTRL_0);
1733         s2s_obs = readl(apb_misc + APB_MISC_GP_OBSDATA_0);
1734
1735         pr_debug("slv0 obs: %08x\ns2s obs: %08x\n", slv0_obs, s2s_obs);
1736 }
1737
1738 static const struct gpio ulpi_gpios[] = {
1739         {ULPI_STP, GPIOF_IN, "ULPI_STP"},
1740         {ULPI_DIR, GPIOF_OUT_INIT_LOW, "ULPI_DIR"},
1741         {ULPI_D0, GPIOF_OUT_INIT_LOW, "ULPI_D0"},
1742         {ULPI_D1, GPIOF_OUT_INIT_LOW, "ULPI_D1"},
1743 };
1744
1745 static int ulpi_null_phy_open(struct tegra_usb_phy *phy)
1746 {
1747         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
1748         int ret;
1749
1750         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1751
1752         ret = gpio_request_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
1753         if (ret)
1754                 return ret;
1755
1756         if (gpio_is_valid(config->phy_restore_gpio)) {
1757                 ret = gpio_request(config->phy_restore_gpio, "phy_restore");
1758                 if (ret)
1759                         goto err_gpio_free;
1760
1761                 gpio_direction_input(config->phy_restore_gpio);
1762         }
1763
1764         tegra_periph_reset_assert(phy->ctrlr_clk);
1765         udelay(10);
1766         tegra_periph_reset_deassert(phy->ctrlr_clk);
1767
1768         return 0;
1769
1770 err_gpio_free:
1771         gpio_free_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
1772         return ret;
1773 }
1774
1775 static void ulpi_null_phy_close(struct tegra_usb_phy *phy)
1776 {
1777         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
1778
1779         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1780
1781         if (gpio_is_valid(config->phy_restore_gpio))
1782                 gpio_free(config->phy_restore_gpio);
1783
1784         gpio_free_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
1785 }
1786
1787 static int ulpi_null_phy_power_off(struct tegra_usb_phy *phy)
1788 {
1789         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1790
1791         if (!phy->phy_clk_on) {
1792                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
1793                                                         __LINE__, phy->inst);
1794                 return 0;
1795         }
1796
1797         phy->phy_clk_on = false;
1798         phy->hw_accessible = false;
1799         ulpi_null_phy_set_tristate(true);
1800         return 0;
1801 }
1802
1803 static int ulpi_null_phy_irq(struct tegra_usb_phy *phy)
1804 {
1805         usb_phy_fence_read(phy);
1806         return IRQ_HANDLED;
1807 }
1808
1809 static int ulpi_null_phy_restore(struct tegra_usb_phy *phy)
1810 {
1811         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
1812         unsigned long timeout;
1813         int ulpi_stp = ULPI_STP;
1814
1815         if (gpio_is_valid(config->phy_restore_gpio))
1816                 ulpi_stp = config->phy_restore_gpio;
1817
1818         /* disable ULPI pinmux bypass */
1819         ulpi_pinmux_bypass(phy, false);
1820
1821         /* driving linstate by GPIO */
1822         gpio_set_value(ULPI_D0, 0);
1823         gpio_set_value(ULPI_D1, 0);
1824
1825         /* driving DIR high */
1826         gpio_set_value(ULPI_DIR, 1);
1827
1828         /* remove ULPI tristate */
1829         ulpi_null_phy_set_tristate(false);
1830
1831         /* wait for STP high */
1832         timeout = jiffies + msecs_to_jiffies(25);
1833
1834         while (!gpio_get_value(ulpi_stp)) {
1835                 if (time_after(jiffies, timeout)) {
1836                         pr_warn("phy restore timeout\n");
1837                         return 1;
1838                 }
1839         }
1840
1841         return 0;
1842 }
1843
1844 static int ulpi_null_phy_lp0_resume(struct tegra_usb_phy *phy)
1845 {
1846         unsigned long val;
1847         void __iomem *base = phy->regs;
1848
1849         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1850
1851         val = readl(base + USB_USBCMD);
1852         val |= USB_USBCMD_RESET;
1853         writel(val, base + USB_USBCMD);
1854
1855         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1856                 USB_USBCMD_RESET, 0, 2500) < 0) {
1857                 pr_err("%s: timeout waiting for reset\n", __func__);
1858         }
1859
1860         val = readl(base + USB_USBMODE_REG_OFFSET);
1861         val &= ~USB_USBMODE_MASK;
1862         val |= USB_USBMODE_HOST;
1863         writel(val, base + USB_USBMODE_REG_OFFSET);
1864
1865         val = readl(base + USB_USBCMD);
1866         val |= USB_USBCMD_RS;
1867         writel(val, base + USB_USBCMD);
1868         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
1869                                                  USB_USBCMD_RS, 2000)) {
1870                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
1871                 return -ETIMEDOUT;
1872         }
1873
1874         /* Enable Port Power */
1875         val = readl(base + USB_PORTSC);
1876         val |= USB_PORTSC_PP;
1877         writel(val, base + USB_PORTSC);
1878         udelay(10);
1879
1880         ulpi_null_phy_restore(phy);
1881
1882         return 0;
1883 }
1884
1885 static int ulpi_null_phy_power_on(struct tegra_usb_phy *phy)
1886 {
1887         unsigned long val;
1888         void __iomem *base = phy->regs;
1889         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
1890
1891         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1892         if (phy->phy_clk_on) {
1893                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
1894                                                         __LINE__, phy->inst);
1895                 return 0;
1896         }
1897
1898         val = readl(base + USB_SUSP_CTRL);
1899         val |= UHSIC_RESET;
1900         writel(val, base + USB_SUSP_CTRL);
1901
1902         val = readl(base + ULPI_TIMING_CTRL_0);
1903         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
1904         writel(val, base + ULPI_TIMING_CTRL_0);
1905
1906         val = readl(base + USB_SUSP_CTRL);
1907         val |= ULPI_PHY_ENABLE;
1908         writel(val, base + USB_SUSP_CTRL);
1909         udelay(10);
1910
1911         /* set timming parameters */
1912         val = readl(base + ULPI_TIMING_CTRL_0);
1913         val |= ULPI_SHADOW_CLK_LOOPBACK_EN;
1914         val |= ULPI_SHADOW_CLK_SEL;
1915         val |= ULPI_LBK_PAD_EN;
1916         val |= ULPI_SHADOW_CLK_DELAY(config->shadow_clk_delay);
1917         val |= ULPI_CLOCK_OUT_DELAY(config->clock_out_delay);
1918         val |= ULPI_LBK_PAD_E_INPUT_OR;
1919         writel(val, base + ULPI_TIMING_CTRL_0);
1920
1921         writel(0, base + ULPI_TIMING_CTRL_1);
1922         udelay(10);
1923
1924         /* start internal 60MHz clock */
1925         val = readl(base + ULPIS2S_CTRL);
1926         val |= ULPIS2S_ENA;
1927         val |= ULPIS2S_SUPPORT_DISCONNECT;
1928         val |= ULPIS2S_SPARE((phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST)
1929                                 ? 3 : 1);
1930         val |= ULPIS2S_PLLU_MASTER_BLASTER60;
1931         writel(val, base + ULPIS2S_CTRL);
1932
1933         /* select ULPI_CORE_CLK_SEL to SHADOW_CLK */
1934         val = readl(base + ULPI_TIMING_CTRL_0);
1935         val |= ULPI_CORE_CLK_SEL;
1936         writel(val, base + ULPI_TIMING_CTRL_0);
1937         udelay(10);
1938
1939         /* enable ULPI null phy clock - can't set the trimmers before this */
1940         val = readl(base + ULPI_TIMING_CTRL_0);
1941         val |= ULPI_CLK_OUT_ENA;
1942         writel(val, base + ULPI_TIMING_CTRL_0);
1943         udelay(10);
1944
1945         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
1946                                                  USB_PHY_CLK_VALID, 2500)) {
1947                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
1948                 return -ETIMEDOUT;
1949         }
1950
1951         /* set ULPI trimmers */
1952         ulpi_set_trimmer(phy);
1953
1954         if (!phy->ulpi_clk_padout_ena) {
1955                 val = readl(base + ULPI_TIMING_CTRL_0);
1956                 val |= ULPI_CLK_PADOUT_ENA;
1957                 writel(val, base + ULPI_TIMING_CTRL_0);
1958                 phy->ulpi_clk_padout_ena = true;
1959         } else {
1960                 if (!readl(base + USB_ASYNCLISTADDR))
1961                         ulpi_null_phy_lp0_resume(phy);
1962         }
1963         udelay(10);
1964
1965         phy->phy_clk_on = true;
1966         phy->hw_accessible = true;
1967
1968         return 0;
1969 }
1970
1971 static int ulpi_null_phy_pre_resume(struct tegra_usb_phy *phy,
1972                                     bool remote_wakeup)
1973 {
1974         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1975         ulpi_null_phy_obs_read();
1976         usb_phy_wait_for_sof(phy);
1977         ulpi_null_phy_obs_read();
1978         return 0;
1979 }
1980
1981 static int ulpi_null_phy_post_resume(struct tegra_usb_phy *phy)
1982 {
1983         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1984         ulpi_null_phy_obs_read();
1985         return 0;
1986 }
1987
1988 static int ulpi_null_phy_resume(struct tegra_usb_phy *phy)
1989 {
1990         unsigned long val;
1991         void __iomem *base = phy->regs;
1992
1993         if (!readl(base + USB_ASYNCLISTADDR)) {
1994                 /* enable ULPI CLK output pad */
1995                 val = readl(base + ULPI_TIMING_CTRL_0);
1996                 val |= ULPI_CLK_PADOUT_ENA;
1997                 writel(val, base + ULPI_TIMING_CTRL_0);
1998
1999                 /* enable ULPI pinmux bypass */
2000                 ulpi_pinmux_bypass(phy, true);
2001                 udelay(5);
2002         }
2003
2004         return 0;
2005 }
2006
2007
2008
2009 static struct tegra_usb_phy_ops utmi_phy_ops = {
2010         .open           = utmi_phy_open,
2011         .close          = utmi_phy_close,
2012         .irq            = utmi_phy_irq,
2013         .power_on       = utmi_phy_power_on,
2014         .power_off      = utmi_phy_power_off,
2015         .pre_resume = utmi_phy_pre_resume,
2016         .resume = utmi_phy_resume,
2017         .post_resume    = utmi_phy_post_resume,
2018         .charger_detect = utmi_phy_charger_detect,
2019         .post_suspend   = phy_post_suspend,
2020 };
2021
2022 static struct tegra_usb_phy_ops uhsic_phy_ops = {
2023         .open           = uhsic_phy_open,
2024         .irq            = uhsic_phy_irq,
2025         .power_on       = uhsic_phy_power_on,
2026         .power_off      = uhsic_phy_power_off,
2027         .pre_resume     = uhsic_phy_pre_resume,
2028         .resume         = uhsic_phy_resume,
2029         .post_resume    = uhsic_phy_post_resume,
2030         .port_power     = uhsic_phy_bus_port_power,
2031         .bus_reset      = uhsic_phy_bus_reset,
2032         .post_suspend   = phy_post_suspend,
2033 };
2034
2035 static struct tegra_usb_phy_ops ulpi_link_phy_ops = {
2036         .open           = ulpi_link_phy_open,
2037         .close  = ulpi_link_phy_close,
2038         .irq            = ulpi_link_phy_irq,
2039         .power_on       = ulpi_link_phy_power_on,
2040         .power_off      = ulpi_link_phy_power_off,
2041         .resume         = ulpi_link_phy_resume,
2042         .post_suspend   = phy_post_suspend,
2043         .pre_resume     = ulpi_link_phy_pre_resume,
2044 };
2045
2046 static struct tegra_usb_phy_ops ulpi_null_phy_ops = {
2047         .open           = ulpi_null_phy_open,
2048         .close          = ulpi_null_phy_close,
2049         .irq            = ulpi_null_phy_irq,
2050         .power_on       = ulpi_null_phy_power_on,
2051         .power_off      = ulpi_null_phy_power_off,
2052         .pre_resume = ulpi_null_phy_pre_resume,
2053         .resume = ulpi_null_phy_resume,
2054         .post_suspend   = phy_post_suspend,
2055         .post_resume = ulpi_null_phy_post_resume,
2056 };
2057
2058 static struct tegra_usb_phy_ops icusb_phy_ops;
2059
2060
2061 static struct tegra_usb_phy_ops *phy_ops[] = {
2062         [TEGRA_USB_PHY_INTF_UTMI] = &utmi_phy_ops,
2063         [TEGRA_USB_PHY_INTF_ULPI_LINK] = &ulpi_link_phy_ops,
2064         [TEGRA_USB_PHY_INTF_ULPI_NULL] = &ulpi_null_phy_ops,
2065         [TEGRA_USB_PHY_INTF_HSIC] = &uhsic_phy_ops,
2066         [TEGRA_USB_PHY_INTF_ICUSB] = &icusb_phy_ops,
2067 };
2068
2069 int tegra2_usb_phy_init_ops(struct tegra_usb_phy *phy)
2070 {
2071         phy->ops = phy_ops[phy->pdata->phy_intf];
2072
2073         return 0;
2074 }