rtc: tps80031: register as mfd sub device
[linux-2.6.git] / arch / arm / mach-tegra / tegra2_mc.h
1 /*
2  * arch/arm/mach-tegra/tegra2_mc.c
3  *
4  * Memory controller bandwidth profiling interface
5  *
6  * Copyright (c) 2009-2011, NVIDIA Corporation.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful, but WITHOUT
14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
16  * more details.
17  *
18  * You should have received a copy of the GNU General Public License along
19  * with this program; if not, write to the Free Software Foundation, Inc.,
20  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
21  */
22
23 #ifndef _INCLUDE_TEGRA2_MC_H_
24 #define _INCLUDE_TEGRA2_MC_H_
25
26 #define SAMPLE_ENABLE_DEFAULT           0
27 #define SAMPLE_LOG_SIZE                 1024 /* need to be DWORD aligned */
28 #define SAMPLE_QUANTUM_DEFAULT          1 /* in milliseconds */
29 #define CLIENT_ENABLED_DEFAULT          false
30 #define CLIENT_ON_SCHEDULE_LENGTH       256
31 #define SHIFT_4K                        12
32
33 typedef enum {
34         FILTER_NONE,
35         FILTER_ADDR,
36         FILTER_CLIENT,
37 } FILTER_MODE;
38
39 #define MC_COUNTER_CLIENT_SIZE                                  256
40
41 #define MC_STAT_CONTROL_0                                       0x90
42 #define MC_STAT_CONTROL_0_EMC_GATHER_SHIFT                      8
43 #define MC_STAT_CONTROL_0_EMC_GATHER_CLEAR                      1
44 #define MC_STAT_CONTROL_0_EMC_GATHER_DISABLE                    2
45 #define MC_STAT_CONTROL_0_EMC_GATHER_ENABLE                     3
46
47 #define MC_STAT_EMC_ADDR_LOW_0                                  0x98
48 #define MC_STAT_EMC_ADDR_HIGH_0                                 0x9c
49 #define MC_STAT_EMC_CLOCK_LIMIT_0                               0xa0
50 #define MC_STAT_EMC_CLOCKS_0                                    0xa4
51 #define MC_STAT_EMC_CONTROL_0_0                                 0xa8
52 #define MC_STAT_EMC_COUNT_0_0                                   0xb8
53 #define MC_STAT_EMC_COUNT_1_0                                   0xbc
54
55 #define ARMC_STAT_CONTROL_FILTER_ADDR_SHIFT                     27
56 #define ARMC_STAT_CONTROL_FILTER_ADDR_DISABLE                   0
57 #define ARMC_STAT_CONTROL_FILTER_ADDR_ENABLE                    1
58 #define ARMC_STAT_CONTROL_FILTER_CLIENT_SHIFT                   26
59 #define ARMC_STAT_CONTROL_FILTER_CLIENT_DISABLE                 0
60 #define ARMC_STAT_CONTROL_FILTER_CLIENT_ENABLE                  1
61 #define ARMC_STAT_CONTROL_FILTER_PRI_SHIFT                      28
62 #define ARMC_STAT_CONTROL_FILTER_PRI_DISABLE                    0
63 #define ARMC_STAT_CONTROL_FILTER_COALESCED_SHIFT                30
64 #define ARMC_STAT_CONTROL_FILTER_COALESCED_DISABLE              0
65 #define ARMC_STAT_CONTROL_CLIENT_ID_SHIFT                       8
66 #define ARMC_STAT_CONTROL_MODE_SHIFT                            0
67 #define ARMC_STAT_CONTROL_MODE_BANDWIDTH                        0
68 #define ARMC_STAT_CONTROL_EVENT_SHIFT                           16
69 #define ARMC_STAT_CONTROL_EVENT_QUALIFIED                       0
70
71 #define EMC_STAT_CONTROL_0                                      0x160
72 #define EMC_STAT_CONTROL_0_LLMC_GATHER_SHIFT                    0
73 #define EMC_STAT_CONTROL_0_LLMC_GATHER_CLEAR                    1
74 #define EMC_STAT_CONTROL_0_LLMC_GATHER_DISABLE                  2
75 #define EMC_STAT_CONTROL_0_LLMC_GATHER_ENABLE                   3
76 #define EMC_STAT_CONTROL_0_DRAM_GATHER_SHIFT                    16
77 #define EMC_STAT_CONTROL_0_DRAM_GATHER_CLEAR                    1
78 #define EMC_STAT_CONTROL_0_DRAM_GATHER_DISABLE                  2
79 #define EMC_STAT_CONTROL_0_DRAM_GATHER_ENABLE                   3
80
81 #define AREMC_STAT_CONTROL_MODE_SHIFT                           0
82 #define AREMC_STAT_CONTROL_MODE_BANDWIDTH                       0
83 #define AREMC_STAT_CONTROL_FILTER_ADDR_SHIFT                    27
84 #define AREMC_STAT_CONTROL_FILTER_ADDR_ENABLE                   1
85 #define AREMC_STAT_CONTROL_CLIENT_TYPE_SHIFT                    8
86 #define AREMC_STAT_CONTROL_CLIENT_TYPE_MPCORER                  0
87 #define AREMC_STAT_CONTROL_FILTER_CLIENT_SHIFT                  26
88 #define AREMC_STAT_CONTROL_FILTER_CLIENT_DISABLE                0
89 #define AREMC_STAT_CONTROL_FILTER_ADDR_DISABLE                  0
90 #define AREMC_STAT_CONTROL_EVENT_SHIFT                          16
91 #define AREMC_STAT_CONTROL_EVENT_QUALIFIED                      0
92
93 #define EMC_STAT_LLMC_ADDR_LOW_0                                0x168
94 #define EMC_STAT_LLMC_ADDR_HIGH_0                               0x16c
95 #define EMC_STAT_LLMC_CLOCK_LIMIT_0                             0x170
96 #define EMC_STAT_LLMC_CONTROL_0_0                               0x178
97 #define EMC_STAT_LLMC_COUNT_0_0                                 0x188
98
99 #define EMC_STAT_DRAM_CLOCK_LIMIT_LO_0                          0x1a4
100 #define EMC_STAT_DRAM_CLOCK_LIMIT_HI_0                          0x1a8
101 #define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO_0                    0x1b4
102 #define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI_0                    0x1b8
103 #define EMC_STAT_DRAM_DEV0_READ_CNT_LO_0                        0x1bc
104 #define EMC_STAT_DRAM_DEV0_READ_CNT_HI_0                        0x1c0
105 #define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO_0                       0x1c4
106 #define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI_0                       0x1c8
107 #define EMC_STAT_DRAM_DEV0_REF_CNT_LO_0                         0x1cc
108 #define EMC_STAT_DRAM_DEV0_REF_CNT_HI_0                         0x1d0
109 #define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0       0x1d4
110 #define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0       0x1d8
111 #define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0       0x1dc
112 #define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0       0x1e0
113 #define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_LO_0                    0x1e4
114 #define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_HI_0                    0x1e8
115 #define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_LO_0                 0x1ec
116 #define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_HI_0                 0x1f0
117 #define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_LO_0                 0x1f4
118 #define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_HI_0                 0x1f8
119 #define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO_0                    0x1fc
120 #define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI_0                    0x200
121 #define EMC_STAT_DRAM_DEV1_READ_CNT_LO_0                        0x204
122 #define EMC_STAT_DRAM_DEV1_READ_CNT_HI_0                        0x208
123 #define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO_0                       0x20c
124 #define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI_0                       0x210
125 #define EMC_STAT_DRAM_DEV1_REF_CNT_LO_0                         0x214
126 #define EMC_STAT_DRAM_DEV1_REF_CNT_HI_0                         0x218
127 #define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0       0x21c
128 #define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0       0x220
129 #define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0       0x224
130 #define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0       0x228
131 #define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_LO_0                    0x22c
132 #define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_HI_0                    0x230
133 #define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_LO_0                 0x234
134 #define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_HI_0                 0x238
135 #define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_LO_0                 0x23c
136 #define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_HI_0                 0x240
137 #define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_0         0x244
138 #define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_0         0x248
139 #define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_0         0x24c
140 #define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_0         0x250
141 #define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_0         0x254
142 #define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_0         0x258
143 #define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_0         0x25c
144 #define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0         0x260
145
146 #pragma pack(push)
147 #pragma pack(1)
148
149 typedef struct {
150         u32     signature;
151         u32     client_number;
152         u32     client_counts;
153         u32     total_counts;
154         u32     emc_clock_rate;
155 } sample_data_t;
156
157 #pragma pack(pop)
158
159 typedef struct tegra_mc_counter {
160         bool            enabled;
161         u32             period;
162         FILTER_MODE     mode;
163         u32             address_low;
164         u32             address_length;
165         u32             current_client_index;
166         u32             total_clients;
167         u8              clients[MC_COUNTER_CLIENT_SIZE];
168         sample_data_t   sample_data;
169 } tegra_mc_counter_t;
170
171 typedef struct tegra_emc_dram_counter {
172         bool    enabled;
173         u8      device_mask;
174
175         sample_data_t   sample_data;
176 } tegra_emc_dram_counter_t;
177
178 /* client ids of mc/emc */
179 typedef enum {
180         MC_STAT_BEGIN = 0,
181         CBR_DISPLAY0A = 0,
182         CBR_DISPLAY0AB,
183         CBR_DISPLAY0B,
184         CBR_DISPLAY0BB,
185         CBR_DISPLAY0C,
186         CBR_DISPLAY0CB,
187         CBR_DISPLAY1B,
188         CBR_DISPLAY1BB,
189         CBR_EPPUP,
190         CBR_G2PR,
191         CBR_G2SR,
192         CBR_MPEUNIFBR,
193         CBR_VIRUV,
194         CSR_AVPCARM7R,
195         CSR_DISPLAYHC,
196         CSR_DISPLAYHCB,
197         CSR_FDCDRD,
198         CSR_G2DR,
199         CSR_HOST1XDMAR,
200         CSR_HOST1XR,
201         CSR_IDXSRD,
202         CSR_MPCORER,
203         CSR_MPE_IPRED,
204         CSR_MPEAMEMRD,
205         CSR_MPECSRD,
206         CSR_PPCSAHBDMAR,
207         CSR_PPCSAHBSLVR,
208         CSR_TEXSRD,
209         CSR_VDEBSEVR,
210         CSR_VDEMBER,
211         CSR_VDEMCER,
212         CSR_VDETPER,
213         CBW_EPPU,
214         CBW_EPPV,
215         CBW_EPPY,
216         CBW_MPEUNIFBW,
217         CBW_VIWSB,
218         CBW_VIWU,
219         CBW_VIWV,
220         CBW_VIWY,
221         CCW_G2DW,
222         CSW_AVPCARM7W,
223         CSW_FDCDWR,
224         CSW_HOST1XW,
225         CSW_ISPW,
226         CSW_MPCOREW,
227         CSW_MPECSWR,
228         CSW_PPCSAHBDMAW,
229         CSW_PPCSAHBSLVW,
230         CSW_VDEBSEVW,
231         CSW_VDEMBEW,
232         CSW_VDETPMW,
233         MC_STAT_END,
234         EMC_DRAM_STAT_BEGIN = 128,
235         ACTIVATE_CNT = 128,
236         READ_CNT,
237         WRITE_CNT,
238         REF_CNT,
239         CUMM_BANKS_ACTIVE_CKE_EQ1,
240         CUMM_BANKS_ACTIVE_CKE_EQ0,
241         CKE_EQ1_CLKS,
242         EXTCLKS_CKE_EQ1,
243         EXTCLKS_CKE_EQ0,
244         NO_BANKS_ACTIVE_CKE_EQ1,
245         NO_BANKS_ACTIVE_CKE_EQ0,
246         EMC_DRAM_STAT_END,
247         MC_STAT_AGGREGATE = 255,
248 } device_id;
249
250 #endif