ad2814c5fff986b8e97373beb0e44b662eba0239
[linux-2.6.git] / arch / arm / mach-tegra / tegra11x_usb_phy.c
1 /*
2  * arch/arm/mach-tegra/tegra11x_usb_phy.c
3  *
4  * Copyright (C) 2012 NVIDIA Corporation
5  *
6  *
7  * This software is licensed under the terms of the GNU General Public
8  * License version 2, as published by the Free Software Foundation, and
9  * may be copied, distributed, and modified under those terms.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17 #include <linux/resource.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/slab.h>
21 #include <linux/err.h>
22 #include <linux/platform_device.h>
23 #include <linux/io.h>
24 #include <linux/gpio.h>
25 #include <linux/usb/ulpi.h>
26 #include <linux/interrupt.h>
27 #include <linux/clk.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/platform_data/tegra_usb.h>
30 #include <mach/clk.h>
31 #include <mach/iomap.h>
32 #include <mach/pinmux.h>
33 #include <mach/pinmux-t11.h>
34 #include <asm/mach-types.h>
35 #include "tegra_usb_phy.h"
36 #include "gpio-names.h"
37 #include "fuse.h"
38
39 #define USB_USBCMD              0x130
40 #define   USB_USBCMD_RS         (1 << 0)
41 #define   USB_CMD_RESET (1<<1)
42
43 #define USB_USBSTS              0x134
44 #define   USB_USBSTS_PCI        (1 << 2)
45 #define   USB_USBSTS_SRI        (1 << 7)
46 #define   USB_USBSTS_HCH        (1 << 12)
47
48 #define USB_TXFILLTUNING        0x154
49 #define USB_FIFO_TXFILL_THRES(x)   (((x) & 0x1f) << 16)
50 #define USB_FIFO_TXFILL_MASK    0x1f0000
51
52 #define ULPI_VIEWPORT           0x170
53 #define   ULPI_WAKEUP           (1 << 31)
54 #define   ULPI_RUN              (1 << 30)
55 #define   ULPI_RD_WR            (1 << 29)
56
57 #define USB_ASYNCLISTADDR       0x148
58
59 #define ICUSB_CTRL              0x15c
60
61 #define USB_PORTSC              0x174
62 #define   USB_PORTSC_PHCD       (1 << 23)
63 #define   USB_PORTSC_WKOC       (1 << 22)
64 #define   USB_PORTSC_WKDS       (1 << 21)
65 #define   USB_PORTSC_WKCN       (1 << 20)
66 #define   USB_PORTSC_PTC(x)     (((x) & 0xf) << 16)
67 #define   USB_PORTSC_PP (1 << 12)
68 #define   USB_PORTSC_LS(x) (((x) & 0x3) << 10)
69 #define   USB_PORTSC_SUSP       (1 << 7)
70 #define   USB_PORTSC_RESUME     (1 << 6)
71 #define   USB_PORTSC_OCC        (1 << 5)
72 #define   USB_PORTSC_PEC        (1 << 3)
73 #define   USB_PORTSC_PE         (1 << 2)
74 #define   USB_PORTSC_CSC        (1 << 1)
75 #define   USB_PORTSC_CCS        (1 << 0)
76 #define   USB_PORTSC_RWC_BITS (USB_PORTSC_CSC | USB_PORTSC_PEC | USB_PORTSC_OCC)
77 #define   USB_PORTSC_PSPD_MASK  3
78
79 #define HOSTPC1_DEVLC           0x1b4
80 #define   HOSTPC1_DEVLC_PHCD            (1 << 22)
81 #define   HOSTPC1_DEVLC_PTS(x)          (((x) & 0x7) << 29)
82 #define   HOSTPC1_DEVLC_PTS_MASK        7
83 #define   HOSTPC1_DEVLC_PTS_HSIC        4
84 #define   HOSTPC1_DEVLC_STS             (1 << 28)
85 #define   HOSTPC1_DEVLC_PSPD(x)         (((x) & 0x3) << 25)
86 #define   HOSTPC1_DEVLC_PSPD_MASK       3
87 #define   HOSTPC1_DEVLC_PSPD_HIGH_SPEED 2
88 #define   HOSTPC1_DEVLC_NYT_ASUS        1
89
90 #define USB_USBMODE             0x1f8
91 #define   USB_USBMODE_MASK              (3 << 0)
92 #define   USB_USBMODE_HOST              (3 << 0)
93 #define   USB_USBMODE_DEVICE            (2 << 0)
94
95 #define USB_SUSP_CTRL           0x400
96 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
97 #define   USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
98 #define   USB_SUSP_CLR                  (1 << 5)
99 #define   USB_CLKEN             (1 << 6)
100 #define   USB_PHY_CLK_VALID             (1 << 7)
101 #define   USB_PHY_CLK_VALID_INT_ENB     (1 << 9)
102 #define   USB_PHY_CLK_VALID_INT_STS     (1 << 8)
103 #define   UTMIP_RESET                   (1 << 11)
104 #define   UTMIP_PHY_ENABLE              (1 << 12)
105 #define   ULPI_PHY_ENABLE               (1 << 13)
106 #define   UHSIC_RESET                   (1 << 14)
107 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
108 #define   UHSIC_PHY_ENABLE              (1 << 19)
109 #define   ULPIS2S_SLV0_RESET            (1 << 20)
110 #define   ULPIS2S_SLV1_RESET            (1 << 21)
111 #define   ULPIS2S_LINE_RESET            (1 << 22)
112 #define   ULPI_PADS_RESET               (1 << 23)
113 #define   ULPI_PADS_CLKEN_RESET         (1 << 24)
114
115 #define USB_PHY_VBUS_WAKEUP_ID  0x408
116 #define   VDAT_DET_INT_EN       (1 << 16)
117 #define   VDAT_DET_CHG_DET      (1 << 17)
118 #define   VDAT_DET_STS          (1 << 18)
119 #define   USB_ID_STATUS         (1 << 2)
120
121 #define ULPIS2S_CTRL            0x418
122 #define   ULPIS2S_ENA                   (1 << 0)
123 #define   ULPIS2S_SUPPORT_DISCONNECT    (1 << 2)
124 #define   ULPIS2S_PLLU_MASTER_BLASTER60 (1 << 3)
125 #define   ULPIS2S_SPARE(x)              (((x) & 0xF) << 8)
126 #define   ULPIS2S_FORCE_ULPI_CLK_OUT    (1 << 12)
127 #define   ULPIS2S_DISCON_DONT_CHECK_SE0 (1 << 13)
128 #define   ULPIS2S_SUPPORT_HS_KEEP_ALIVE (1 << 14)
129 #define   ULPIS2S_DISABLE_STP_PU        (1 << 15)
130 #define   ULPIS2S_SLV0_CLAMP_XMIT       (1 << 16)
131
132 #define ULPI_TIMING_CTRL_0      0x424
133 #define   ULPI_CLOCK_OUT_DELAY(x)       ((x) & 0x1F)
134 #define   ULPI_OUTPUT_PINMUX_BYP        (1 << 10)
135 #define   ULPI_CLKOUT_PINMUX_BYP        (1 << 11)
136 #define   ULPI_SHADOW_CLK_LOOPBACK_EN   (1 << 12)
137 #define   ULPI_SHADOW_CLK_SEL           (1 << 13)
138 #define   ULPI_CORE_CLK_SEL             (1 << 14)
139 #define   ULPI_SHADOW_CLK_DELAY(x)      (((x) & 0x1F) << 16)
140 #define   ULPI_LBK_PAD_EN               (1 << 26)
141 #define   ULPI_LBK_PAD_E_INPUT_OR       (1 << 27)
142 #define   ULPI_CLK_OUT_ENA              (1 << 28)
143 #define   ULPI_CLK_PADOUT_ENA           (1 << 29)
144
145 #define ULPI_TIMING_CTRL_1      0x428
146 #define   ULPI_DATA_TRIMMER_LOAD        (1 << 0)
147 #define   ULPI_DATA_TRIMMER_SEL(x)      (((x) & 0x7) << 1)
148 #define   ULPI_STPDIRNXT_TRIMMER_LOAD   (1 << 16)
149 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
150 #define   ULPI_DIR_TRIMMER_LOAD         (1 << 24)
151 #define   ULPI_DIR_TRIMMER_SEL(x)       (((x) & 0x7) << 25)
152
153 #define USB_IF_SPARE    0x498
154 #define   USB_HS_RSM_EOP_EN         (1 << 4)
155 #define   USB_PORT_SUSPEND_EN       (1 << 5)
156
157 #define USB_NEW_CONTROL  0x4c0
158 #define   USB_COHRENCY_EN           (1 << 0)
159 #define   USB_MEM_ALLIGNMENT_MUX_EN (1 << 1)
160
161 #define UTMIP_XCVR_CFG0         0x808
162 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
163 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
164 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
165 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
166 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
167 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
168 #define   UTMIP_XCVR_LSBIAS_SEL                 (1 << 21)
169 #define   UTMIP_XCVR_SETUP_MSB(x)               (((x) & 0x7) << 22)
170 #define   UTMIP_XCVR_HSSLEW_MSB(x)              (((x) & 0x7f) << 25)
171 #define   UTMIP_XCVR_MAX_OFFSET         2
172 #define   UTMIP_XCVR_SETUP_MAX_VALUE    0x7f
173 #define   UTMIP_XCVR_SETUP_MIN_VALUE    0
174 #define   XCVR_SETUP_MSB_CALIB(x) ((x) >> 4)
175
176 #define UTMIP_BIAS_CFG0         0x80c
177 #define   UTMIP_OTGPD                   (1 << 11)
178 #define   UTMIP_BIASPD                  (1 << 10)
179 #define   UTMIP_HSSQUELCH_LEVEL(x)      (((x) & 0x3) << 0)
180 #define   UTMIP_HSDISCON_LEVEL(x)       (((x) & 0x3) << 2)
181 #define   UTMIP_HSDISCON_LEVEL_MSB      (1 << 24)
182
183 #define UTMIP_HSRX_CFG0         0x810
184 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
185 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
186
187 #define UTMIP_HSRX_CFG1         0x814
188 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
189
190 #define UTMIP_TX_CFG0           0x820
191 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
192 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
193
194 #define UTMIP_DEBOUNCE_CFG0 0x82c
195 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
196
197 #define UTMIP_BAT_CHRG_CFG0 0x830
198 #define   UTMIP_PD_CHRG                 (1 << 0)
199 #define   UTMIP_ON_SINK_EN              (1 << 2)
200 #define   UTMIP_OP_SRC_EN               (1 << 3)
201
202 #define UTMIP_XCVR_CFG1         0x838
203 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
204 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
205 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
206 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
207
208 #define UTMIP_BIAS_CFG1         0x83c
209 #define   UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
210 #define   UTMIP_BIAS_PDTRK_POWERDOWN    (1 << 0)
211 #define   UTMIP_BIAS_PDTRK_POWERUP      (1 << 1)
212
213 #define UTMIP_MISC_CFG0         0x824
214 #define   UTMIP_DPDM_OBSERVE            (1 << 26)
215 #define   UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
216 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J   UTMIP_DPDM_OBSERVE_SEL(0xf)
217 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K   UTMIP_DPDM_OBSERVE_SEL(0xe)
218 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
219 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
220 #define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
221 #define   FORCE_PULLDN_DM       (1 << 8)
222 #define   FORCE_PULLDN_DP       (1 << 9)
223 #define   COMB_TERMS            (1 << 0)
224 #define   ALWAYS_FREE_RUNNING_TERMS (1 << 1)
225
226 #define UTMIP_SPARE_CFG0        0x834
227 #define   FUSE_SETUP_SEL                (1 << 3)
228 #define   FUSE_ATERM_SEL                (1 << 4)
229
230 #define UTMIP_PMC_WAKEUP0               0x84c
231 #define   EVENT_INT_ENB                 (1 << 0)
232
233 #define UTMIP_BIAS_STS0                 0x840
234 #define   UTMIP_RCTRL_VAL(x)            (((x) & 0xffff) << 0)
235 #define   UTMIP_TCTRL_VAL(x)            (((x) & (0xffff << 16)) >> 16)
236
237 #define UHSIC_PLL_CFG1                          0xc04
238 #define   UHSIC_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
239 #define   UHSIC_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 14)
240
241 #define UHSIC_HSRX_CFG0                         0xc08
242 #define   UHSIC_ELASTIC_UNDERRUN_LIMIT(x)       (((x) & 0x1f) << 2)
243 #define   UHSIC_ELASTIC_OVERRUN_LIMIT(x)        (((x) & 0x1f) << 8)
244 #define   UHSIC_IDLE_WAIT(x)                    (((x) & 0x1f) << 13)
245
246 #define UHSIC_HSRX_CFG1                         0xc0c
247 #define   UHSIC_HS_SYNC_START_DLY(x)            (((x) & 0x1f) << 1)
248
249 #define UHSIC_TX_CFG0                           0xc10
250 #define UHSIC_HS_READY_WAIT_FOR_VALID   (1 << 9)
251 #define UHSIC_MISC_CFG0                         0xc14
252 #define   UHSIC_SUSPEND_EXIT_ON_EDGE            (1 << 7)
253 #define   UHSIC_DETECT_SHORT_CONNECT            (1 << 8)
254 #define   UHSIC_FORCE_XCVR_MODE                 (1 << 15)
255 #define   UHSIC_DISABLE_BUSRESET                (1 << 20)
256 #define UHSIC_MISC_CFG1                         0xc18
257 #define   UHSIC_PLLU_STABLE_COUNT(x)            (((x) & 0xfff) << 2)
258
259 #define UHSIC_PADS_CFG0                         0xc1c
260 #define   UHSIC_TX_RTUNEN                       0xf000
261 #define   UHSIC_TX_RTUNE(x)                     (((x) & 0xf) << 12)
262 #define   UHSIC_TX_SLEWP                        (0xf << 16)
263 #define   UHSIC_TX_SLEWN                        (0xf << 20)
264
265 #define UHSIC_PADS_CFG1                         0xc20
266 #define   UHSIC_PD_BG                           (1 << 2)
267 #define   UHSIC_PD_TX                           (1 << 3)
268 #define   UHSIC_PD_TRK                          (1 << 4)
269 #define   UHSIC_PD_RX                           (1 << 5)
270 #define   UHSIC_PD_ZI                           (1 << 6)
271 #define   UHSIC_RX_SEL                          (1 << 7)
272 #define   UHSIC_RPD_DATA                        (1 << 9)
273 #define   UHSIC_RPD_STROBE                      (1 << 10)
274 #define   UHSIC_RPU_DATA                        (1 << 11)
275 #define   UHSIC_RPU_STROBE                      (1 << 12)
276
277 #define UHSIC_STAT_CFG0                 0xc28
278 #define   UHSIC_CONNECT_DETECT                  (1 << 0)
279
280 #define PMC_USB_DEBOUNCE                        0xec
281 #define   UTMIP_LINE_DEB_CNT(x)                 (((x) & 0xf) << 16)
282
283 #define PMC_USB_AO                              0xf0
284 #define PMC_POWER_DOWN_MASK                     0xffff
285 #define HSIC_RESERVED_P0                        (3 << 14)
286 #define HSIC_STOBE_VAL_PD_P0                    (1 << 13)
287 #define HSIC_DATA_VAL_PD_P0                     (1 << 12)
288 #define USB_ID_PD(inst)                         (1 << ((4*(inst))+3))
289 #define VBUS_WAKEUP_PD(inst)                    (1 << ((4*(inst))+2))
290 #define   USBON_VAL_PD(inst)                    (1 << ((4*(inst))+1))
291 #define   USBON_VAL_PD_P2                       (1 << 9)
292 #define   USBON_VAL_PD_P1                       (1 << 5)
293 #define   USBON_VAL_PD_P0                       (1 << 1)
294 #define   USBOP_VAL_PD(inst)                    (1 << (4*(inst)))
295 #define   USBOP_VAL_PD_P2                       (1 << 8)
296 #define   USBOP_VAL_PD_P1                       (1 << 4)
297 #define   USBOP_VAL_PD_P0                       (1 << 0)
298 #define   PMC_USB_AO_PD_P2                      (0xf << 8)
299 #define   PMC_USB_AO_ID_PD_P0                   (1 << 3)
300 #define   PMC_USB_AO_VBUS_WAKEUP_PD_P0  (1 << 2)
301
302 #define PMC_TRIGGERS                    0x1ec
303 #define   UTMIP_CLR_WALK_PTR(inst)      (1 << (inst))
304 #define   UTMIP_CLR_WALK_PTR_P2         (1 << 2)
305 #define   UTMIP_CLR_WALK_PTR_P1         (1 << 1)
306 #define   UTMIP_CLR_WALK_PTR_P0         (1 << 0)
307 #define   UTMIP_CAP_CFG(inst)   (1 << ((inst)+4))
308 #define   UTMIP_CAP_CFG_P2              (1 << 6)
309 #define   UTMIP_CAP_CFG_P1              (1 << 5)
310 #define   UTMIP_CAP_CFG_P0              (1 << 4)
311 #define   UTMIP_CLR_WAKE_ALARM(inst)            (1 << ((inst)+12))
312 #define   UTMIP_CLR_WAKE_ALARM_P2       (1 << 14)
313
314 #define PMC_PAD_CFG             (0x1f4)
315
316 #define PMC_UTMIP_TERM_PAD_CFG  0x1f8
317 #define   PMC_TCTRL_VAL(x)      (((x) & 0x1f) << 5)
318 #define   PMC_RCTRL_VAL(x)      (((x) & 0x1f) << 0)
319
320 #define UHSIC_SLEEPWALK_REG             0x210
321 #define UHSIC_DATA_RPD_D                (1 << 25)
322 #define UHSIC_STRB_RPD_D                (1 << 24)
323 #define UHSIC_DATA_RPD_C                (1 << 17)
324 #define UHSIC_STRB_RPD_C                (1 << 16)
325 #define UHSIC_DATA_RPD_B                (1 << 9)
326 #define UHSIC_STRB_RPD_B                (1 << 8)
327 #define UHSIC_DATA_RPD_A                (1 << 1)
328 #define UHSIC_STRB_RPD_A                (1 << 0)
329
330 #define PMC_SLEEP_CFG                   0x1fc
331 #define   UTMIP_TCTRL_USE_PMC(inst) (1 << ((8*(inst))+3))
332 #define   UTMIP_TCTRL_USE_PMC_P2                (1 << 19)
333 #define   UTMIP_TCTRL_USE_PMC_P1                (1 << 11)
334 #define   UTMIP_TCTRL_USE_PMC_P0                (1 << 3)
335 #define   UTMIP_RCTRL_USE_PMC(inst) (1 << ((8*(inst))+2))
336 #define   UTMIP_RCTRL_USE_PMC_P2                (1 << 18)
337 #define   UTMIP_RCTRL_USE_PMC_P1                (1 << 10)
338 #define   UTMIP_RCTRL_USE_PMC_P0                (1 << 2)
339 #define   UTMIP_FSLS_USE_PMC(inst)      (1 << ((8*(inst))+1))
340 #define   UTMIP_FSLS_USE_PMC_P2         (1 << 17)
341 #define   UTMIP_FSLS_USE_PMC_P1         (1 << 9)
342 #define   UTMIP_FSLS_USE_PMC_P0         (1 << 1)
343 #define   UTMIP_MASTER_ENABLE(inst) (1 << (8*(inst)))
344 #define   UTMIP_MASTER_ENABLE_P2                (1 << 16)
345 #define   UTMIP_MASTER_ENABLE_P1                (1 << 8)
346 #define   UTMIP_MASTER_ENABLE_P0                (1 << 0)
347 #define UHSIC_MASTER_ENABLE_P0          (1 << 24)
348 #define UHSIC_WAKE_VAL_P0(x)            (((x) & 0xf) << 28)
349
350 #define PMC_SLEEPWALK_CFG               0x200
351 #define   UTMIP_LINEVAL_WALK_EN(inst) (1 << ((8*(inst))+7))
352 #define   UTMIP_LINEVAL_WALK_EN_P2      (1 << 23)
353 #define   UTMIP_LINEVAL_WALK_EN_P1      (1 << 15)
354 #define   UTMIP_LINEVAL_WALK_EN_P0      (1 << 7)
355 #define   UTMIP_WAKE_VAL(inst, x) (((x) & 0xf) << ((8*(inst))+4))
356 #define   UTMIP_WAKE_VAL_P2(x)          (((x) & 0xf) << 20)
357 #define   UTMIP_WAKE_VAL_P1(x)          (((x) & 0xf) << 12)
358 #define   UTMIP_WAKE_VAL_P0(x)          (((x) & 0xf) << 4)
359 #define   WAKE_VAL_NONE         0xc
360 #define   WAKE_VAL_ANY                  0xF
361 #define   WAKE_VAL_FSJ                  0x2
362 #define   WAKE_VAL_FSK                  0x1
363 #define   WAKE_VAL_SE0                  0x0
364
365 #define PMC_SLEEPWALK_REG(inst)         (0x204 + (4*(inst)))
366 #define   UTMIP_USBOP_RPD_A     (1 << 0)
367 #define   UTMIP_USBON_RPD_A     (1 << 1)
368 #define   UTMIP_AP_A                    (1 << 4)
369 #define   UTMIP_AN_A                    (1 << 5)
370 #define   UTMIP_HIGHZ_A         (1 << 6)
371 #define   UTMIP_USBOP_RPD_B     (1 << 8)
372 #define   UTMIP_USBON_RPD_B     (1 << 9)
373 #define   UTMIP_AP_B                    (1 << 12)
374 #define   UTMIP_AN_B                    (1 << 13)
375 #define   UTMIP_HIGHZ_B         (1 << 14)
376 #define   UTMIP_USBOP_RPD_C     (1 << 16)
377 #define   UTMIP_USBON_RPD_C     (1 << 17)
378 #define   UTMIP_AP_C            (1 << 20)
379 #define   UTMIP_AN_C            (1 << 21)
380 #define   UTMIP_HIGHZ_C         (1 << 22)
381 #define   UTMIP_USBOP_RPD_D     (1 << 24)
382 #define   UTMIP_USBON_RPD_D     (1 << 25)
383 #define   UTMIP_AP_D            (1 << 28)
384 #define   UTMIP_AN_D            (1 << 29)
385 #define   UTMIP_HIGHZ_D         (1 << 30)
386
387 #define UTMIP_UHSIC_STATUS              0x214
388 #define   UTMIP_WALK_PTR_VAL(inst)      (0x3 << ((inst)*2))
389 #define   UTMIP_USBOP_VAL(inst)         (1 << ((2*(inst)) + 8))
390 #define   UTMIP_USBOP_VAL_P2            (1 << 12)
391 #define   UTMIP_USBOP_VAL_P1            (1 << 10)
392 #define   UTMIP_USBOP_VAL_P0            (1 << 8)
393 #define   UTMIP_USBON_VAL(inst)         (1 << ((2*(inst)) + 9))
394 #define   UTMIP_USBON_VAL_P2            (1 << 13)
395 #define   UTMIP_USBON_VAL_P1            (1 << 11)
396 #define   UTMIP_USBON_VAL_P0            (1 << 9)
397 #define   UTMIP_WAKE_ALARM(inst)                (1 << ((inst) + 16))
398 #define   UTMIP_WAKE_ALARM_P2   (1 << 18)
399 #define   UTMIP_WAKE_ALARM_P1   (1 << 17)
400 #define   UTMIP_WAKE_ALARM_P0   (1 << 16)
401 #define   UTMIP_WALK_PTR(inst)  (1 << ((inst)*2))
402 #define   UTMIP_WALK_PTR_P2     (1 << 4)
403 #define   UTMIP_WALK_PTR_P1     (1 << 2)
404 #define   UTMIP_WALK_PTR_P0     (1 << 0)
405
406 #define USB1_PREFETCH_ID               6
407 #define USB2_PREFETCH_ID               18
408 #define USB3_PREFETCH_ID               17
409
410 #define PMC_UTMIP_UHSIC_FAKE            0x218
411 #define   USBON_VAL(inst)       (1 << ((4*(inst))+1))
412 #define   USBON_VAL_P2                  (1 << 9)
413 #define   USBON_VAL_P1                  (1 << 5)
414 #define   USBON_VAL_P0                  (1 << 1)
415 #define   USBOP_VAL(inst)       (1 << (4*(inst)))
416 #define   USBOP_VAL_P2                  (1 << 8)
417 #define   USBOP_VAL_P1                  (1 << 4)
418 #define   USBOP_VAL_P0                  (1 << 0)
419
420 #define PMC_UTMIP_BIAS_MASTER_CNTRL 0x30c
421 #define   BIAS_MASTER_PROG_VAL          (1 << 1)
422
423 #define PMC_UTMIP_MASTER_CONFIG         0x310
424 #define   UTMIP_PWR(inst)               (1 << (inst))
425
426 #define FUSE_USB_CALIB_0                0x1F0
427 #define   FUSE_USB_CALIB_XCVR_SETUP(x)  (((x) & 0x7F) << 0)
428
429 #define APB_MISC_GP_OBSCTRL_0   0x818
430 #define APB_MISC_GP_OBSDATA_0   0x81c
431
432 /* ULPI GPIO */
433 #define ULPI_STP        TEGRA_GPIO_PY3
434 #define ULPI_DIR        TEGRA_GPIO_PY1
435 #define ULPI_D0         TEGRA_GPIO_PO1
436 #define ULPI_D1         TEGRA_GPIO_PO2
437
438 #define TEGRA_STREAM_DISABLE    0x1f8
439 #define TEGRA_STREAM_DISABLE_OFFSET     (1 << 4)
440
441 /* These values (in milli second) are taken from the battery charging spec */
442 #define TDP_SRC_ON_MS    100
443 #define TDPSRC_CON_MS    40
444
445 #ifdef DEBUG
446 #define DBG(stuff...)   pr_info("tegra11x_usb_phy: " stuff)
447 #else
448 #define DBG(stuff...)   do {} while (0)
449 #endif
450
451 static u32 utmip_rctrl_val, utmip_tctrl_val;
452 static DEFINE_SPINLOCK(utmip_pad_lock);
453 static int utmip_pad_count;
454
455 static struct tegra_xtal_freq utmip_freq_table[] = {
456         {
457                 .freq = 12000000,
458                 .enable_delay = 0x02,
459                 .stable_count = 0x2F,
460                 .active_delay = 0x04,
461                 .xtal_freq_count = 0x76,
462                 .debounce = 0x7530,
463                 .pdtrk_count = 5,
464         },
465         {
466                 .freq = 13000000,
467                 .enable_delay = 0x02,
468                 .stable_count = 0x33,
469                 .active_delay = 0x05,
470                 .xtal_freq_count = 0x7F,
471                 .debounce = 0x7EF4,
472                 .pdtrk_count = 5,
473         },
474         {
475                 .freq = 19200000,
476                 .enable_delay = 0x03,
477                 .stable_count = 0x4B,
478                 .active_delay = 0x06,
479                 .xtal_freq_count = 0xBB,
480                 .debounce = 0xBB80,
481                 .pdtrk_count = 7,
482         },
483         {
484                 .freq = 26000000,
485                 .enable_delay = 0x04,
486                 .stable_count = 0x66,
487                 .active_delay = 0x09,
488                 .xtal_freq_count = 0xFE,
489                 .debounce = 0xFDE8,
490                 .pdtrk_count = 9,
491         },
492 };
493
494 static struct tegra_xtal_freq uhsic_freq_table[] = {
495         {
496                 .freq = 12000000,
497                 .enable_delay = 0x02,
498                 .stable_count = 0x2F,
499                 .active_delay = 0x0,
500                 .xtal_freq_count = 0x1CA,
501         },
502         {
503                 .freq = 13000000,
504                 .enable_delay = 0x02,
505                 .stable_count = 0x33,
506                 .active_delay = 0x0,
507                 .xtal_freq_count = 0x1F0,
508         },
509         {
510                 .freq = 19200000,
511                 .enable_delay = 0x03,
512                 .stable_count = 0x4B,
513                 .active_delay = 0x0,
514                 .xtal_freq_count = 0x2DD,
515         },
516         {
517                 .freq = 26000000,
518                 .enable_delay = 0x04,
519                 .stable_count = 0x66,
520                 .active_delay = 0x0,
521                 .xtal_freq_count = 0x3E0,
522         },
523 };
524
525 static int _usb_phy_init(struct tegra_usb_phy *phy)
526 {
527         unsigned long val;
528         void __iomem *base = phy->regs;
529
530         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
531
532         val = readl(base + HOSTPC1_DEVLC);
533         val &= ~HOSTPC1_DEVLC_STS;
534         writel(val, base + HOSTPC1_DEVLC);
535
536         val = readl(base + USB_IF_SPARE);
537         val |= USB_HS_RSM_EOP_EN;
538         val |= USB_PORT_SUSPEND_EN;
539         writel(val, base + USB_IF_SPARE);
540
541         val = readl(base + USB_NEW_CONTROL);
542         val |= USB_COHRENCY_EN;
543         val |= USB_MEM_ALLIGNMENT_MUX_EN;
544         writel(val, base + USB_NEW_CONTROL);
545
546 #if !defined(CONFIG_TEGRA_SILICON_PLATFORM)
547         val =  readl(base + TEGRA_STREAM_DISABLE);
548         val |= TEGRA_STREAM_DISABLE_OFFSET;
549         writel(val , base + TEGRA_STREAM_DISABLE);
550 #endif
551
552         return 0;
553 }
554 static int usb_phy_reset(struct tegra_usb_phy *phy)
555 {
556         unsigned long val;
557         void __iomem *base = phy->regs;
558
559         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
560
561 #if !defined(CONFIG_TEGRA_SILICON_PLATFORM)
562         val =  readl(base + TEGRA_STREAM_DISABLE);
563         val |= TEGRA_STREAM_DISABLE_OFFSET;
564         writel(val , base + TEGRA_STREAM_DISABLE);
565 #endif
566         val = readl(base + USB_TXFILLTUNING);
567         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
568                 val = USB_FIFO_TXFILL_THRES(0x10);
569                 writel(val, base + USB_TXFILLTUNING);
570         }
571
572 return 0;
573 }
574
575 static void utmip_setup_pmc_wake_detect(struct tegra_usb_phy *phy)
576 {
577         unsigned long val, pmc_pad_cfg_val;
578         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
579         unsigned  int inst = phy->inst;
580         void __iomem *base = phy->regs;
581         bool port_connected;
582         enum usb_phy_port_speed port_speed;
583
584         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
585
586         /* check for port connect status */
587         val = readl(base + USB_PORTSC);
588         port_connected = val & USB_PORTSC_CCS;
589
590         if (!port_connected)
591                 return;
592
593         port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
594                 HOSTPC1_DEVLC_PSPD_MASK;
595         /*Set PMC MASTER bits to do the following
596         * a. Take over the UTMI drivers
597         * b. set up such that it will take over resume
598         *        if remote wakeup is detected
599         * Prepare PMC to take over suspend-wake detect-drive resume until USB
600         * controller ready
601         */
602
603         /* disable master enable in PMC */
604         val = readl(pmc_base + PMC_SLEEP_CFG);
605         val &= ~UTMIP_MASTER_ENABLE(inst);
606         writel(val, pmc_base + PMC_SLEEP_CFG);
607
608         /* UTMIP_PWR_PX=1 for power savings mode */
609         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
610         val |= UTMIP_PWR(inst);
611         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
612
613         /* config debouncer */
614         val = readl(pmc_base + PMC_USB_DEBOUNCE);
615         val &= ~UTMIP_LINE_DEB_CNT(~0);
616         val |= UTMIP_LINE_DEB_CNT(4);
617         writel(val, pmc_base + PMC_USB_DEBOUNCE);
618
619         /* Make sure nothing is happening on the line with respect to PMC */
620         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
621         val &= ~USBOP_VAL(inst);
622         val &= ~USBON_VAL(inst);
623         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
624
625         /* Make sure wake value for line is none */
626         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
627         val &= ~UTMIP_LINEVAL_WALK_EN(inst);
628         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
629         val = readl(pmc_base + PMC_SLEEP_CFG);
630         val &= ~UTMIP_WAKE_VAL(inst, ~0);
631         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
632         writel(val, pmc_base + PMC_SLEEP_CFG);
633
634         /* turn off pad detectors */
635         val = readl(pmc_base + PMC_USB_AO);
636         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
637         writel(val, pmc_base + PMC_USB_AO);
638
639         /* Remove fake values and make synchronizers work a bit */
640         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
641         val &= ~USBOP_VAL(inst);
642         val &= ~USBON_VAL(inst);
643         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
644
645         /* Enable which type of event can trigger a walk,
646         in this case usb_line_wake */
647         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
648         val |= UTMIP_LINEVAL_WALK_EN(inst);
649         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
650
651         /* Enable which type of event can trigger a walk,
652         * in this case usb_line_wake */
653         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
654         val |= UTMIP_LINEVAL_WALK_EN(inst);
655         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
656
657         /* Clear the walk pointers and wake alarm */
658         val = readl(pmc_base + PMC_TRIGGERS);
659         val |= UTMIP_CLR_WAKE_ALARM(inst) | UTMIP_CLR_WALK_PTR(inst);
660         writel(val, pmc_base + PMC_TRIGGERS);
661
662
663         /* Capture FS/LS pad configurations */
664         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
665         val = readl(pmc_base + PMC_TRIGGERS);
666         val |= UTMIP_CAP_CFG(inst);
667         writel(val, pmc_base + PMC_TRIGGERS);
668         udelay(1);
669         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
670
671         /* BIAS MASTER_ENABLE=0 */
672         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
673         val &= ~BIAS_MASTER_PROG_VAL;
674         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
675
676         /* program walk sequence, maintain a J, followed by a driven K
677         * to signal a resume once an wake event is detected */
678         val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
679         val &= ~UTMIP_AP_A;
680         val |= UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_AN_A |UTMIP_HIGHZ_A |
681                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_AP_B | UTMIP_AN_B |
682                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_AP_C | UTMIP_AN_C |
683                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_AP_D | UTMIP_AN_D;
684         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
685
686         if (port_speed == USB_PHY_PORT_SPEED_LOW) {
687                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
688                 val &= ~(UTMIP_AN_B | UTMIP_HIGHZ_B | UTMIP_AN_C |
689                         UTMIP_HIGHZ_C | UTMIP_AN_D | UTMIP_HIGHZ_D);
690                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
691         } else {
692                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
693                 val &= ~(UTMIP_AP_B | UTMIP_HIGHZ_B | UTMIP_AP_C |
694                         UTMIP_HIGHZ_C | UTMIP_AP_D | UTMIP_HIGHZ_D);
695                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
696         }
697
698         /* turn on pad detectors */
699         val = readl(pmc_base + PMC_USB_AO);
700         val &= ~(USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
701         writel(val, pmc_base + PMC_USB_AO);
702
703         /* Add small delay before usb detectors provide stable line values */
704         mdelay(1);
705
706         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
707         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
708         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
709         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
710
711         phy->remote_wakeup = false;
712
713         /* Turn over pad configuration to PMC  for line wake events*/
714         val = readl(pmc_base + PMC_SLEEP_CFG);
715         val &= ~UTMIP_WAKE_VAL(inst, ~0);
716         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_ANY);
717         val |= UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst);
718         val |= UTMIP_MASTER_ENABLE(inst) | UTMIP_FSLS_USE_PMC(inst);
719         writel(val, pmc_base + PMC_SLEEP_CFG);
720
721         val = readl(base + UTMIP_PMC_WAKEUP0);
722         val |= EVENT_INT_ENB;
723         writel(val, base + UTMIP_PMC_WAKEUP0);
724 }
725
726 static void utmip_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy)
727 {
728         unsigned long val;
729         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
730         unsigned  int inst = phy->inst;
731         void __iomem *base = phy->regs;
732
733         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
734
735         val = readl(pmc_base + PMC_SLEEP_CFG);
736         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
737         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
738         writel(val, pmc_base + PMC_SLEEP_CFG);
739
740         val = readl(pmc_base + PMC_TRIGGERS);
741         val |= UTMIP_CLR_WAKE_ALARM(inst) | UTMIP_CLR_WALK_PTR(inst);
742         writel(val, pmc_base + PMC_TRIGGERS);
743
744         val = readl(base + UTMIP_PMC_WAKEUP0);
745         val &= ~EVENT_INT_ENB;
746         writel(val, base + UTMIP_PMC_WAKEUP0);
747
748         /* Disable PMC master mode by clearing MASTER_EN */
749         val = readl(pmc_base + PMC_SLEEP_CFG);
750         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
751                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
752         writel(val, pmc_base + PMC_SLEEP_CFG);
753
754         val = readl(pmc_base + PMC_TRIGGERS);
755         val &= ~UTMIP_CAP_CFG(inst);
756         writel(val, pmc_base + PMC_TRIGGERS);
757
758         /* turn off pad detectors */
759         val = readl(pmc_base + PMC_USB_AO);
760         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
761         writel(val, pmc_base + PMC_USB_AO);
762
763         phy->remote_wakeup = false;
764 }
765
766 static bool utmi_phy_remotewake_detected(struct tegra_usb_phy *phy)
767 {
768         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
769         void __iomem *base = phy->regs;
770         unsigned  int inst = phy->inst;
771         u32 val;
772
773         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
774         val = readl(base + UTMIP_PMC_WAKEUP0);
775         if (val & EVENT_INT_ENB) {
776                 val = readl(pmc_base + UTMIP_UHSIC_STATUS);
777                 if (UTMIP_WAKE_ALARM(inst) & val) {
778                         val = readl(pmc_base + PMC_SLEEP_CFG);
779                         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
780                         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
781                         writel(val, pmc_base + PMC_SLEEP_CFG);
782
783                         val = readl(pmc_base + PMC_TRIGGERS);
784                         val |= UTMIP_CLR_WAKE_ALARM(inst) |
785                                 UTMIP_CLR_WALK_PTR(inst);
786                         writel(val, pmc_base + PMC_TRIGGERS);
787
788                         val = readl(base + UTMIP_PMC_WAKEUP0);
789                         val &= ~EVENT_INT_ENB;
790                         writel(val, base + UTMIP_PMC_WAKEUP0);
791                         phy->remote_wakeup = true;
792                         return true;
793                 }
794         }
795         return false;
796 }
797
798 static void utmi_phy_enable_trking_data(struct tegra_usb_phy *phy)
799 {
800         void __iomem *base = IO_ADDRESS(TEGRA_USB_BASE);
801         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
802         static bool init_done = false;
803         u32 val;
804
805         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
806
807         /* Should be done only once after system boot */
808         if (init_done)
809                 return;
810
811         clk_enable(phy->utmi_pad_clk);
812         /* Bias pad MASTER_ENABLE=1 */
813         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
814         val |= BIAS_MASTER_PROG_VAL;
815         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
816
817         /* Setting the tracking length time */
818         val = readl(base + UTMIP_BIAS_CFG1);
819         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
820         val |= UTMIP_BIAS_PDTRK_COUNT(5);
821         writel(val, base + UTMIP_BIAS_CFG1);
822
823         /* Bias PDTRK is Shared and MUST be done from USB1 ONLY, PD_TRK=0 */
824         val = readl(base + UTMIP_BIAS_CFG1);
825         val &= ~UTMIP_BIAS_PDTRK_POWERDOWN;
826         writel(val, base + UTMIP_BIAS_CFG1);
827
828         val = readl(base + UTMIP_BIAS_CFG1);
829         val |= UTMIP_BIAS_PDTRK_POWERUP;
830         writel(val, base + UTMIP_BIAS_CFG1);
831
832         /* Wait for 25usec */
833         udelay(25);
834
835         /* Bias pad MASTER_ENABLE=0 */
836         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
837         val &= ~BIAS_MASTER_PROG_VAL;
838         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
839
840         /* Wait for 1usec */
841         udelay(1);
842
843         /* Bias pad MASTER_ENABLE=1 */
844         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
845         val |= BIAS_MASTER_PROG_VAL;
846         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
847
848         /* Read RCTRL and TCTRL from UTMIP space */
849         val = readl(base + UTMIP_BIAS_STS0);
850         utmip_rctrl_val = ffz(UTMIP_RCTRL_VAL(val));
851         utmip_tctrl_val = ffz(UTMIP_TCTRL_VAL(val));
852
853         /* PD_TRK=1 */
854         val = readl(base + UTMIP_BIAS_CFG1);
855         val |= UTMIP_BIAS_PDTRK_POWERDOWN;
856         writel(val, base + UTMIP_BIAS_CFG1);
857
858         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
859         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
860         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
861         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
862         clk_disable(phy->utmi_pad_clk);
863         init_done = true;
864 }
865
866 static void utmip_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy)
867 {
868         unsigned long val;
869         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
870         unsigned  int inst = phy->inst;
871
872         /* power down UTMIP interfaces */
873         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
874         val |= UTMIP_PWR(inst);
875         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
876
877         /* setup sleep walk usb controller */
878         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
879                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
880                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
881                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
882         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
883
884         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
885         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
886         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
887         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
888
889         /* Turn over pad configuration to PMC */
890         val = readl(pmc_base + PMC_SLEEP_CFG);
891         val &= ~UTMIP_WAKE_VAL(inst, ~0);
892         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE) |
893                 UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
894                 UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst);
895         writel(val, pmc_base + PMC_SLEEP_CFG);
896 }
897
898 static void utmip_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
899 {
900         unsigned long val;
901         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
902         unsigned  int inst = phy->inst;
903
904         /* Disable PMC master mode by clearing MASTER_EN */
905         val = readl(pmc_base + PMC_SLEEP_CFG);
906         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
907                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
908         writel(val, pmc_base + PMC_SLEEP_CFG);
909         mdelay(1);
910 }
911
912 #if 0
913 static int uhsic_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy)
914 {
915         unsigned long val;
916         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
917
918         /* turn on pad detectors for HSIC*/
919         val = readl(pmc_base + PMC_USB_AO);
920         val |= (HSIC_RESERVED_P0 | HSIC_STOBE_VAL_PD_P0 | HSIC_DATA_VAL_PD_P0);
921         writel(val, pmc_base + PMC_USB_AO);
922
923         /* enable pull downs on HSIC PMC */
924         val = UHSIC_STRB_RPD_A | UHSIC_DATA_RPD_A | UHSIC_STRB_RPD_B |
925                 UHSIC_DATA_RPD_B | UHSIC_STRB_RPD_C | UHSIC_DATA_RPD_C |
926                 UHSIC_STRB_RPD_D | UHSIC_DATA_RPD_D;
927         writel(val, pmc_base + UHSIC_SLEEPWALK_REG);
928
929         /* Turn over pad configuration to PMC */
930         val = readl(pmc_base + PMC_SLEEP_CFG);
931         val &= ~UHSIC_WAKE_VAL_P0(~0);
932         val |= UHSIC_WAKE_VAL_P0(WAKE_VAL_NONE) | UHSIC_MASTER_ENABLE_P0;
933         writel(val, pmc_base + PMC_SLEEP_CFG);
934
935         return 0;
936 }
937
938 static void usb_phy_power_down_pmc(void)
939 {
940         unsigned long val;
941         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
942
943         /* power down all 3 UTMIP interfaces */
944         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
945         val |= UTMIP_PWR(0) | UTMIP_PWR(1) | UTMIP_PWR(2);
946         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
947
948         /* turn on pad detectors */
949         writel(PMC_POWER_DOWN_MASK, pmc_base + PMC_USB_AO);
950
951         /* setup sleep walk fl all 3 usb controllers */
952         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
953                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
954                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
955                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
956         writel(val, pmc_base + PMC_SLEEPWALK_REG(0));
957         writel(val, pmc_base + PMC_SLEEPWALK_REG(1));
958         writel(val, pmc_base + PMC_SLEEPWALK_REG(2));
959
960         /* enable pull downs on HSIC PMC */
961         val = UHSIC_STRB_RPD_A | UHSIC_DATA_RPD_A | UHSIC_STRB_RPD_B |
962                 UHSIC_DATA_RPD_B | UHSIC_STRB_RPD_C | UHSIC_DATA_RPD_C |
963                 UHSIC_STRB_RPD_D | UHSIC_DATA_RPD_D;
964         writel(val, pmc_base + UHSIC_SLEEPWALK_REG);
965
966         /* Turn over pad configuration to PMC */
967         val = readl(pmc_base + PMC_SLEEP_CFG);
968         val &= ~UTMIP_WAKE_VAL(0, ~0);
969         val &= ~UTMIP_WAKE_VAL(1, ~0);
970         val &= ~UTMIP_WAKE_VAL(2, ~0);
971         val &= ~UHSIC_WAKE_VAL_P0(~0);
972         val |= UTMIP_WAKE_VAL(0, WAKE_VAL_NONE) | UHSIC_WAKE_VAL_P0(WAKE_VAL_NONE) |
973         UTMIP_WAKE_VAL(1, WAKE_VAL_NONE) | UTMIP_WAKE_VAL(2, WAKE_VAL_NONE) |
974         UTMIP_RCTRL_USE_PMC(0) | UTMIP_RCTRL_USE_PMC(1) | UTMIP_RCTRL_USE_PMC(2) |
975         UTMIP_TCTRL_USE_PMC(0) | UTMIP_TCTRL_USE_PMC(1) | UTMIP_TCTRL_USE_PMC(2) |
976         UTMIP_FSLS_USE_PMC(0) | UTMIP_FSLS_USE_PMC(1) | UTMIP_FSLS_USE_PMC(2) |
977         UTMIP_MASTER_ENABLE(0) | UTMIP_MASTER_ENABLE(1) | UTMIP_MASTER_ENABLE(2) |
978         UHSIC_MASTER_ENABLE_P0;
979         writel(val, pmc_base + PMC_SLEEP_CFG);
980 }
981 #endif
982
983 static void uhsic_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
984 {
985         unsigned long val;
986         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
987
988         /* turn on pad detectors for HSIC*/
989         val = readl(pmc_base + PMC_USB_AO);
990         val &= ~(HSIC_RESERVED_P0 | HSIC_STOBE_VAL_PD_P0 | HSIC_DATA_VAL_PD_P0);
991         writel(val, pmc_base + PMC_USB_AO);
992
993         /* Disable PMC master mode by clearing MASTER_EN */
994         val = readl(pmc_base + PMC_SLEEP_CFG);
995         val &= ~(UHSIC_MASTER_ENABLE_P0);
996         writel(val, pmc_base + PMC_SLEEP_CFG);
997         mdelay(1);
998 }
999
1000 static int usb_phy_bringup_host_controller(struct tegra_usb_phy *phy)
1001 {
1002         unsigned long val;
1003         void __iomem *base = phy->regs;
1004
1005         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1006         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n",
1007                 readl(base + USB_USBSTS), readl(base + USB_PORTSC),
1008                                                         phy->port_speed);
1009
1010         /* Enable Port Power */
1011         val = readl(base + USB_PORTSC);
1012         val |= USB_PORTSC_PP;
1013         writel(val, base + USB_PORTSC);
1014         udelay(10);
1015
1016         /* Check if the phy resume from LP0. When the phy resume from LP0
1017          * USB register will be reset.to zero */
1018         if (!readl(base + USB_ASYNCLISTADDR)) {
1019                 /* Program the field PTC based on the saved speed mode */
1020                 val = readl(base + USB_PORTSC);
1021                 val &= ~USB_PORTSC_PTC(~0);
1022                 if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH)
1023                         val |= USB_PORTSC_PTC(5);
1024                 else if (phy->port_speed == USB_PHY_PORT_SPEED_FULL)
1025                         val |= USB_PORTSC_PTC(6);
1026                 else if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
1027                         val |= USB_PORTSC_PTC(7);
1028                 writel(val, base + USB_PORTSC);
1029                 udelay(10);
1030
1031                 /* Disable test mode by setting PTC field to NORMAL_OP */
1032                 val = readl(base + USB_PORTSC);
1033                 val &= ~USB_PORTSC_PTC(~0);
1034                 writel(val, base + USB_PORTSC);
1035                 udelay(10);
1036         }
1037
1038         /* Poll until CCS is enabled */
1039         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
1040                                                  USB_PORTSC_CCS, 2000)) {
1041                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
1042         }
1043
1044         /* Poll until PE is enabled */
1045         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_PE,
1046                                                  USB_PORTSC_PE, 2000)) {
1047                 pr_err("%s: timeout waiting for USB_PORTSC_PE\n", __func__);
1048         }
1049
1050         /* Clear the PCI status, to avoid an interrupt taken upon resume */
1051         val = readl(base + USB_USBSTS);
1052         val |= USB_USBSTS_PCI;
1053         writel(val, base + USB_USBSTS);
1054
1055         /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
1056         val = readl(base + USB_PORTSC);
1057         if ((val & USB_PORTSC_PP) && (val & USB_PORTSC_PE)) {
1058                 val |= USB_PORTSC_SUSP;
1059                 writel(val, base + USB_PORTSC);
1060                 /* Need a 4ms delay before the controller goes to suspend */
1061                 mdelay(4);
1062
1063                 /* Wait until port suspend completes */
1064                 if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_SUSP,
1065                                                  USB_PORTSC_SUSP, 1000)) {
1066                         pr_err("%s: timeout waiting for PORT_SUSPEND\n",
1067                                                                 __func__);
1068                 }
1069         }
1070
1071         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1072                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1073         return 0;
1074 }
1075
1076 static void usb_phy_wait_for_sof(struct tegra_usb_phy *phy)
1077 {
1078         unsigned long val;
1079         void __iomem *base = phy->regs;
1080
1081         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1082
1083         val = readl(base + USB_USBSTS);
1084         writel(val, base + USB_USBSTS);
1085         udelay(20);
1086         /* wait for two SOFs */
1087         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1088                 USB_USBSTS_SRI, 2500))
1089                 pr_err("%s: timeout waiting for SOF\n", __func__);
1090
1091         val = readl(base + USB_USBSTS);
1092         writel(val, base + USB_USBSTS);
1093         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI, 0, 2500))
1094                 pr_err("%s: timeout waiting for SOF\n", __func__);
1095
1096         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1097                         USB_USBSTS_SRI, 2500))
1098                 pr_err("%s: timeout waiting for SOF\n", __func__);
1099
1100         udelay(20);
1101 }
1102
1103 static unsigned int utmi_phy_xcvr_setup_value(struct tegra_usb_phy *phy)
1104 {
1105         struct tegra_utmi_config *cfg = &phy->pdata->u_cfg.utmi;
1106         signed long val;
1107
1108         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1109
1110         if (cfg->xcvr_use_fuses) {
1111                 val = FUSE_USB_CALIB_XCVR_SETUP(
1112                                 tegra_fuse_readl(FUSE_USB_CALIB_0));
1113                 if (cfg->xcvr_setup_offset <= UTMIP_XCVR_MAX_OFFSET)
1114                         val = val + cfg->xcvr_setup_offset;
1115
1116                 if (val > UTMIP_XCVR_SETUP_MAX_VALUE) {
1117                         val = UTMIP_XCVR_SETUP_MAX_VALUE;
1118                         pr_info("%s: reset XCVR_SETUP to max value\n",
1119                                  __func__);
1120                 } else if (val < UTMIP_XCVR_SETUP_MIN_VALUE) {
1121                         val = UTMIP_XCVR_SETUP_MIN_VALUE;
1122                         pr_info("%s: reset XCVR_SETUP to min value\n",
1123                                  __func__);
1124                 }
1125         } else {
1126                 val = cfg->xcvr_setup;
1127         }
1128
1129         return (unsigned int) val;
1130 }
1131
1132 static int utmi_phy_open(struct tegra_usb_phy *phy)
1133 {
1134         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1135         unsigned long parent_rate, val;
1136         int i;
1137
1138         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1139
1140         phy->utmi_pad_clk = clk_get_sys("utmip-pad", NULL);
1141         if (IS_ERR(phy->utmi_pad_clk)) {
1142                 pr_err("%s: can't get utmip pad clock\n", __func__);
1143                 return PTR_ERR(phy->utmi_pad_clk);
1144         }
1145
1146         phy->utmi_xcvr_setup = utmi_phy_xcvr_setup_value(phy);
1147
1148         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
1149         for (i = 0; i < ARRAY_SIZE(utmip_freq_table); i++) {
1150                 if (utmip_freq_table[i].freq == parent_rate) {
1151                         phy->freq = &utmip_freq_table[i];
1152                         break;
1153                 }
1154         }
1155         if (!phy->freq) {
1156                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
1157                 return -EINVAL;
1158         }
1159
1160         /* Power-up the VBUS detector for UTMIP PHY */
1161         val = readl(pmc_base + PMC_USB_AO);
1162         val &= ~(PMC_USB_AO_VBUS_WAKEUP_PD_P0 | PMC_USB_AO_ID_PD_P0);
1163         writel((val | PMC_USB_AO_PD_P2), (pmc_base + PMC_USB_AO));
1164
1165         utmip_powerup_pmc_wake_detect(phy);
1166
1167         return 0;
1168 }
1169
1170 static void utmi_phy_close(struct tegra_usb_phy *phy)
1171 {
1172         unsigned long val;
1173         void __iomem *base = phy->regs;
1174
1175         DBG("%s inst:[%d]\n", __func__, phy->inst);
1176
1177         /* Disable PHY clock valid interrupts while going into suspend*/
1178         if (phy->pdata->u_data.host.hot_plug) {
1179                 val = readl(base + USB_SUSP_CTRL);
1180                 val &= ~USB_PHY_CLK_VALID_INT_ENB;
1181                 writel(val, base + USB_SUSP_CTRL);
1182         }
1183
1184         val = readl(base + USB_PORTSC);
1185         val |= USB_PORTSC_WKCN;
1186         writel(val, base + USB_PORTSC);
1187
1188         clk_put(phy->utmi_pad_clk);
1189 }
1190
1191 static int utmi_phy_pad_power_on(struct tegra_usb_phy *phy)
1192 {
1193         unsigned long val, flags;
1194         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1195
1196         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1197
1198         clk_enable(phy->utmi_pad_clk);
1199
1200         spin_lock_irqsave(&utmip_pad_lock, flags);
1201         utmip_pad_count++;
1202
1203         val = readl(pad_base + UTMIP_BIAS_CFG0);
1204         val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
1205         val |= UTMIP_HSSQUELCH_LEVEL(0x2) | UTMIP_HSDISCON_LEVEL(0x1) |
1206                 UTMIP_HSDISCON_LEVEL_MSB;
1207         writel(val, pad_base + UTMIP_BIAS_CFG0);
1208
1209         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1210
1211         clk_disable(phy->utmi_pad_clk);
1212
1213         return 0;
1214 }
1215
1216 static int utmi_phy_pad_power_off(struct tegra_usb_phy *phy)
1217 {
1218         unsigned long val, flags;
1219         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1220
1221         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1222
1223         clk_enable(phy->utmi_pad_clk);
1224         spin_lock_irqsave(&utmip_pad_lock, flags);
1225
1226         if (!utmip_pad_count) {
1227                 pr_err("%s: utmip pad already powered off\n", __func__);
1228                 goto out;
1229         }
1230         if (--utmip_pad_count == 0) {
1231                 val = readl(pad_base + UTMIP_BIAS_CFG0);
1232                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
1233                 val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) | UTMIP_HSDISCON_LEVEL(~0) |
1234                         UTMIP_HSDISCON_LEVEL_MSB);
1235                 writel(val, pad_base + UTMIP_BIAS_CFG0);
1236         }
1237 out:
1238         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1239         clk_disable(phy->utmi_pad_clk);
1240
1241         return 0;
1242 }
1243
1244 static int utmi_phy_irq(struct tegra_usb_phy *phy)
1245 {
1246         void __iomem *base = phy->regs;
1247         unsigned long val = 0;
1248
1249         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1250         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1251                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1252         DBG("USB_USBMODE[0x%x] USB_USBCMD[0x%x]\n",
1253                         readl(base + USB_USBMODE), readl(base + USB_USBCMD));
1254
1255         /* check if there is any remote wake event */
1256         if (utmi_phy_remotewake_detected(phy))
1257                 pr_info("%s: utmip remote wake detected\n", __func__);
1258
1259         if (phy->pdata->u_data.host.hot_plug) {
1260                 val = readl(base + USB_SUSP_CTRL);
1261                 if ((val  & USB_PHY_CLK_VALID_INT_STS)) {
1262                         val &= ~USB_PHY_CLK_VALID_INT_ENB |
1263                                         USB_PHY_CLK_VALID_INT_STS;
1264                         writel(val , (base + USB_SUSP_CTRL));
1265                         pr_info("%s: usb device plugged-in\n", __func__);
1266                         val = readl(base + USB_USBSTS);
1267                         if (!(val  & USB_USBSTS_PCI))
1268                                 return IRQ_NONE;
1269                         val = readl(base + USB_PORTSC);
1270                         val &= ~(USB_PORTSC_WKCN | USB_PORTSC_RWC_BITS);
1271                         writel(val , (base + USB_PORTSC));
1272                 }
1273         }
1274
1275         return IRQ_HANDLED;
1276 }
1277
1278 static int utmi_phy_post_resume(struct tegra_usb_phy *phy)
1279 {
1280         unsigned long val;
1281         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1282         unsigned  int inst = phy->inst;
1283
1284         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1285         val = readl(pmc_base + PMC_SLEEP_CFG);
1286         /* if PMC is not disabled by now then disable it */
1287         if (val & UTMIP_MASTER_ENABLE(inst)) {
1288                 utmip_phy_disable_pmc_bus_ctrl(phy);
1289         }
1290
1291         return 0;
1292 }
1293
1294 static int utmi_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1295 {
1296         unsigned long val;
1297         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1298         unsigned  int inst = phy->inst;
1299
1300         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1301         val = readl(pmc_base + PMC_SLEEP_CFG);
1302         if (val & UTMIP_MASTER_ENABLE(inst)) {
1303                 if (!remote_wakeup)
1304                         utmip_phy_disable_pmc_bus_ctrl(phy);
1305         }
1306
1307         return 0;
1308 }
1309
1310 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
1311 {
1312         unsigned long val;
1313         void __iomem *base = phy->regs;
1314
1315         DBG("%s(%d) inst:[%d] BEGIN\n", __func__, __LINE__, phy->inst);
1316         if (!phy->phy_clk_on) {
1317                 DBG("%s(%d) inst:[%d] phy clk is already off\n",
1318                                         __func__, __LINE__, phy->inst);
1319                 return 0;
1320         }
1321
1322         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1323                 utmip_powerdown_pmc_wake_detect(phy);
1324
1325                 val = readl(base + USB_SUSP_CTRL);
1326                 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
1327                 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
1328                 writel(val, base + USB_SUSP_CTRL);
1329
1330                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1331                 val |= UTMIP_PD_CHRG;
1332                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1333         } else {
1334                 utmip_setup_pmc_wake_detect(phy);
1335         }
1336
1337         if (!phy->pdata->u_data.host.hot_plug) {
1338                 val = readl(base + UTMIP_XCVR_CFG0);
1339                 val |= (UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
1340                          UTMIP_FORCE_PDZI_POWERDOWN);
1341                 writel(val, base + UTMIP_XCVR_CFG0);
1342         }
1343
1344         val = readl(base + UTMIP_XCVR_CFG1);
1345         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1346                    UTMIP_FORCE_PDDR_POWERDOWN;
1347         writel(val, base + UTMIP_XCVR_CFG1);
1348
1349         val = readl(base + UTMIP_BIAS_CFG1);
1350         val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
1351         writel(val, base + UTMIP_BIAS_CFG1);
1352
1353         utmi_phy_pad_power_off(phy);
1354
1355         phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
1356                         HOSTPC1_DEVLC_PSPD_MASK;
1357
1358         if (phy->pdata->u_data.host.hot_plug) {
1359                 bool enable_hotplug = true;
1360                 /* if it is OTG port then make sure to enable hot-plug feature
1361                    only if host adaptor is connected, i.e id is low */
1362                 if (phy->pdata->port_otg) {
1363                         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1364                         enable_hotplug = (val & USB_ID_STATUS) ? false : true;
1365                 }
1366                 if (enable_hotplug) {
1367                         val = readl(base + USB_PORTSC);
1368                         val |= USB_PORTSC_WKCN;
1369                         writel(val, base + USB_PORTSC);
1370
1371                         val = readl(base + USB_SUSP_CTRL);
1372                         val |= USB_PHY_CLK_VALID_INT_ENB;
1373                         writel(val, base + USB_SUSP_CTRL);
1374                 } else {
1375                         /* Disable PHY clock valid interrupts while going into suspend*/
1376                         val = readl(base + USB_SUSP_CTRL);
1377                         val &= ~USB_PHY_CLK_VALID_INT_ENB;
1378                         writel(val, base + USB_SUSP_CTRL);
1379                 }
1380         }
1381
1382         if (phy->inst == 0) {
1383                         val = readl(base + USB_SUSP_CTRL);
1384                         val |= UTMIP_RESET;
1385                         writel(val, base + USB_SUSP_CTRL);
1386         }
1387
1388         val = readl(base + HOSTPC1_DEVLC);
1389         val |= HOSTPC1_DEVLC_PHCD;
1390         writel(val, base + HOSTPC1_DEVLC);
1391
1392         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
1393                                                                 0, 2500))
1394                 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
1395
1396         phy->phy_clk_on = false;
1397         phy->hw_accessible = false;
1398
1399         DBG("%s(%d) inst:[%d] END\n", __func__, __LINE__, phy->inst);
1400
1401         return 0;
1402 }
1403
1404
1405 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
1406 {
1407         unsigned long val;
1408         void __iomem *base = phy->regs;
1409         struct tegra_utmi_config *config = &phy->pdata->u_cfg.utmi;
1410
1411         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1412         if (phy->phy_clk_on) {
1413                 DBG("%s(%d) inst:[%d] phy clk is already On\n",
1414                                         __func__, __LINE__, phy->inst);
1415                 return 0;
1416         }
1417         val = readl(base + USB_SUSP_CTRL);
1418         val |= UTMIP_RESET;
1419         writel(val, base + USB_SUSP_CTRL);
1420
1421         val = readl(base + UTMIP_TX_CFG0);
1422         val |= UTMIP_FS_PREABMLE_J;
1423         writel(val, base + UTMIP_TX_CFG0);
1424
1425         val = readl(base + UTMIP_HSRX_CFG0);
1426         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
1427         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
1428         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
1429         writel(val, base + UTMIP_HSRX_CFG0);
1430
1431         val = readl(base + UTMIP_HSRX_CFG1);
1432         val &= ~UTMIP_HS_SYNC_START_DLY(~0);
1433         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
1434         writel(val, base + UTMIP_HSRX_CFG1);
1435
1436         val = readl(base + UTMIP_DEBOUNCE_CFG0);
1437         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
1438         val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
1439         writel(val, base + UTMIP_DEBOUNCE_CFG0);
1440
1441         val = readl(base + UTMIP_MISC_CFG0);
1442         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
1443         writel(val, base + UTMIP_MISC_CFG0);
1444
1445         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1446                 val = readl(base + USB_SUSP_CTRL);
1447                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
1448                 writel(val, base + USB_SUSP_CTRL);
1449
1450                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1451                 val &= ~UTMIP_PD_CHRG;
1452                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1453         } else {
1454                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1455                 val |= UTMIP_PD_CHRG;
1456                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1457         }
1458
1459         utmi_phy_pad_power_on(phy);
1460
1461         val = readl(base + UTMIP_XCVR_CFG0);
1462         val &= ~(UTMIP_XCVR_LSBIAS_SEL | UTMIP_FORCE_PD_POWERDOWN |
1463                  UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN |
1464                  UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_LSFSLEW(~0) |
1465                  UTMIP_XCVR_LSRSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
1466         val |= UTMIP_XCVR_SETUP(phy->utmi_xcvr_setup);
1467         val |= UTMIP_XCVR_SETUP_MSB(XCVR_SETUP_MSB_CALIB(phy->utmi_xcvr_setup));
1468         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
1469         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
1470         val |= UTMIP_XCVR_HSSLEW_MSB(0x8);
1471         writel(val, base + UTMIP_XCVR_CFG0);
1472
1473         val = readl(base + UTMIP_XCVR_CFG1);
1474         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1475                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
1476         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
1477         writel(val, base + UTMIP_XCVR_CFG1);
1478
1479         val = readl(base + UTMIP_BIAS_CFG1);
1480         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
1481         val |= UTMIP_BIAS_PDTRK_COUNT(phy->freq->pdtrk_count);
1482         writel(val, base + UTMIP_BIAS_CFG1);
1483
1484         val = readl(base + UTMIP_SPARE_CFG0);
1485         val &= ~FUSE_SETUP_SEL;
1486         val |= FUSE_ATERM_SEL;
1487         writel(val, base + UTMIP_SPARE_CFG0);
1488
1489         val = readl(base + USB_SUSP_CTRL);
1490         val |= UTMIP_PHY_ENABLE;
1491         writel(val, base + USB_SUSP_CTRL);
1492
1493         val = readl(base + USB_SUSP_CTRL);
1494         val &= ~UTMIP_RESET;
1495         writel(val, base + USB_SUSP_CTRL);
1496
1497         val = readl(base + HOSTPC1_DEVLC);
1498         val &= ~HOSTPC1_DEVLC_PHCD;
1499         writel(val, base + HOSTPC1_DEVLC);
1500
1501         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1502                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500))
1503                 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
1504
1505         utmi_phy_enable_trking_data(phy);
1506
1507         if (phy->inst == 2)
1508                 writel(0, base + ICUSB_CTRL);
1509
1510         val = readl(base + USB_USBMODE);
1511         val &= ~USB_USBMODE_MASK;
1512         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST)
1513                 val |= USB_USBMODE_HOST;
1514         else
1515                 val |= USB_USBMODE_DEVICE;
1516         writel(val, base + USB_USBMODE);
1517
1518         val = readl(base + HOSTPC1_DEVLC);
1519         val &= ~HOSTPC1_DEVLC_PTS(~0);
1520         val |= HOSTPC1_DEVLC_STS;
1521         writel(val, base + HOSTPC1_DEVLC);
1522
1523         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE)
1524                 utmip_powerup_pmc_wake_detect(phy);
1525         phy->phy_clk_on = true;
1526         phy->hw_accessible = true;
1527         DBG("%s(%d) End\n", __func__, __LINE__);
1528
1529         return 0;
1530 }
1531
1532 static void utmi_phy_restore_start(struct tegra_usb_phy *phy)
1533 {
1534         unsigned long val;
1535         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1536         int inst = phy->inst;
1537
1538         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1539         val = readl(pmc_base + UTMIP_UHSIC_STATUS);
1540         /* check whether we wake up from the remote resume */
1541         if (UTMIP_WALK_PTR_VAL(inst) & val) {
1542                 phy->remote_wakeup = true;
1543         } else {
1544                 if (!((UTMIP_USBON_VAL(phy->inst) |
1545                         UTMIP_USBOP_VAL(phy->inst)) & val)) {
1546                                 utmip_phy_disable_pmc_bus_ctrl(phy);
1547                 }
1548         }
1549 }
1550
1551 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
1552 {
1553         unsigned long val;
1554         void __iomem *base = phy->regs;
1555         int wait_time_us = 3000; /* FPR should be set by this time */
1556
1557         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1558         /* check whether we wake up from the remote resume */
1559         if (phy->remote_wakeup) {
1560                 /* wait until FPR bit is set automatically on remote resume */
1561                 do {
1562                         val = readl(base + USB_PORTSC);
1563                         udelay(1);
1564                         if (wait_time_us == 0)
1565                                 return;
1566                         wait_time_us--;
1567                 } while (!(val & USB_PORTSC_RESUME));
1568                 /* wait for 25 ms to port resume complete */
1569                 msleep(25);
1570                 /* disable PMC master control */
1571                 utmip_phy_disable_pmc_bus_ctrl(phy);
1572
1573                 /* Clear PCI and SRI bits to avoid an interrupt upon resume */
1574                 val = readl(base + USB_USBSTS);
1575                 writel(val, base + USB_USBSTS);
1576                 /* wait to avoid SOF if there is any */
1577                 if (usb_phy_reg_status_wait(base + USB_USBSTS,
1578                         USB_USBSTS_SRI, USB_USBSTS_SRI, 2500) < 0) {
1579                         pr_err("%s: timeout waiting for SOF\n", __func__);
1580                 }
1581                 utmi_phy_post_resume(phy);
1582         }
1583 }
1584
1585 static int utmi_phy_resume(struct tegra_usb_phy *phy)
1586 {
1587         int status = 0;
1588         unsigned long val;
1589         void __iomem *base = phy->regs;
1590
1591         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1592         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) {
1593                 if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
1594                         utmi_phy_restore_start(phy);
1595                         usb_phy_bringup_host_controller(phy);
1596                         utmi_phy_restore_end(phy);
1597                 } else {
1598                         /* device is plugged in when system is in LP0 */
1599                         /* bring up the controller from LP0*/
1600                         val = readl(base + USB_USBCMD);
1601                         val |= USB_CMD_RESET;
1602                         writel(val, base + USB_USBCMD);
1603
1604                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1605                                 USB_CMD_RESET, 0, 2500) < 0) {
1606                                 pr_err("%s: timeout waiting for reset\n", __func__);
1607                         }
1608
1609                         val = readl(base + USB_USBMODE);
1610                         val &= ~USB_USBMODE_MASK;
1611                         val |= USB_USBMODE_HOST;
1612                         writel(val, base + USB_USBMODE);
1613
1614                         val = readl(base + HOSTPC1_DEVLC);
1615                         val &= ~HOSTPC1_DEVLC_PTS(~0);
1616                         val |= HOSTPC1_DEVLC_STS;
1617                         writel(val, base + HOSTPC1_DEVLC);
1618
1619                         writel(USB_USBCMD_RS, base + USB_USBCMD);
1620
1621                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1622                                 USB_USBCMD_RS, USB_USBCMD_RS, 2500) < 0) {
1623                                 pr_err("%s: timeout waiting for run bit\n", __func__);
1624                         }
1625
1626                         /* Enable Port Power */
1627                         val = readl(base + USB_PORTSC);
1628                         val |= USB_PORTSC_PP;
1629                         writel(val, base + USB_PORTSC);
1630                         udelay(10);
1631
1632                         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1633                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1634                 }
1635         }
1636
1637         return status;
1638 }
1639
1640 static bool utmi_phy_charger_detect(struct tegra_usb_phy *phy)
1641 {
1642         unsigned long val;
1643         void __iomem *base = phy->regs;
1644         bool status;
1645
1646         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1647         if (phy->pdata->op_mode != TEGRA_USB_OPMODE_DEVICE) {
1648                 /* Charger detection is not there for ULPI
1649                  * return Charger not available */
1650                 return false;
1651         }
1652
1653         /* Enable charger detection logic */
1654         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1655         val |= UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN;
1656         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1657
1658         /* Source should be on for 100 ms as per USB charging spec */
1659         msleep(TDP_SRC_ON_MS);
1660
1661         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1662         /* If charger is not connected disable the interrupt */
1663         val &= ~VDAT_DET_INT_EN;
1664         val |= VDAT_DET_CHG_DET;
1665         writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
1666
1667         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1668         if (val & VDAT_DET_STS)
1669                 status = true;
1670         else
1671                 status = false;
1672
1673         /* Disable charger detection logic */
1674         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1675         val &= ~(UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN);
1676         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1677
1678         /* Delay of 40 ms before we pull the D+ as per battery charger spec */
1679         msleep(TDPSRC_CON_MS);
1680
1681         return status;
1682 }
1683
1684 static int uhsic_phy_open(struct tegra_usb_phy *phy)
1685 {
1686         unsigned long parent_rate;
1687         int i;
1688
1689         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1690         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
1691         for (i = 0; i < ARRAY_SIZE(uhsic_freq_table); i++) {
1692                 if (uhsic_freq_table[i].freq == parent_rate) {
1693                         phy->freq = &uhsic_freq_table[i];
1694                         break;
1695                 }
1696         }
1697         if (!phy->freq) {
1698                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
1699                 return -EINVAL;
1700         }
1701
1702         uhsic_powerup_pmc_wake_detect(phy);
1703
1704         return 0;
1705 }
1706
1707 static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
1708 {
1709         unsigned long val;
1710         void __iomem *base = phy->regs;
1711         struct tegra_hsic_config *config = &phy->pdata->u_cfg.hsic;
1712
1713         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1714
1715         utmip_powerup_pmc_wake_detect(phy);
1716
1717         if (phy->phy_clk_on) {
1718                 DBG("%s(%d) inst:[%d] phy clk is already On\n",
1719                                         __func__, __LINE__, phy->inst);
1720                 return 0;
1721         }
1722
1723         val = readl(base + UHSIC_PADS_CFG1);
1724         val &= ~(UHSIC_PD_BG | UHSIC_PD_TX | UHSIC_PD_TRK | UHSIC_PD_RX |
1725                         UHSIC_PD_ZI | UHSIC_RPD_DATA | UHSIC_RPD_STROBE);
1726         val |= UHSIC_RX_SEL;
1727         writel(val, base + UHSIC_PADS_CFG1);
1728         udelay(2);
1729
1730         val = readl(base + USB_SUSP_CTRL);
1731         val |= UHSIC_RESET;
1732         writel(val, base + USB_SUSP_CTRL);
1733         udelay(30);
1734
1735         val = readl(base + USB_SUSP_CTRL);
1736         val |= UHSIC_PHY_ENABLE;
1737         writel(val, base + USB_SUSP_CTRL);
1738
1739         val = readl(base + UHSIC_HSRX_CFG0);
1740         val |= UHSIC_IDLE_WAIT(config->idle_wait_delay);
1741         val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(config->elastic_underrun_limit);
1742         val |= UHSIC_ELASTIC_OVERRUN_LIMIT(config->elastic_overrun_limit);
1743         writel(val, base + UHSIC_HSRX_CFG0);
1744
1745         val = readl(base + UHSIC_HSRX_CFG1);
1746         val |= UHSIC_HS_SYNC_START_DLY(config->sync_start_delay);
1747         writel(val, base + UHSIC_HSRX_CFG1);
1748
1749         /* WAR HSIC TX */
1750         val = readl(base + UHSIC_TX_CFG0);
1751         val &= ~UHSIC_HS_READY_WAIT_FOR_VALID;
1752         writel(val, base + UHSIC_TX_CFG0);
1753
1754         val = readl(base + UHSIC_MISC_CFG0);
1755         val |= UHSIC_SUSPEND_EXIT_ON_EDGE;
1756         /* Disable generic bus reset, to allow AP30 specific bus reset*/
1757         val |= UHSIC_DISABLE_BUSRESET;
1758         writel(val, base + UHSIC_MISC_CFG0);
1759
1760         val = readl(base + UHSIC_MISC_CFG1);
1761         val |= UHSIC_PLLU_STABLE_COUNT(phy->freq->stable_count);
1762         writel(val, base + UHSIC_MISC_CFG1);
1763
1764         val = readl(base + UHSIC_PLL_CFG1);
1765         val |= UHSIC_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
1766         val |= UHSIC_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count);
1767         writel(val, base + UHSIC_PLL_CFG1);
1768
1769         val = readl(base + USB_SUSP_CTRL);
1770         val &= ~(UHSIC_RESET);
1771         writel(val, base + USB_SUSP_CTRL);
1772         udelay(2);
1773
1774         val = readl(base + USB_USBMODE);
1775         val |= USB_USBMODE_HOST;
1776         writel(val, base + USB_USBMODE);
1777
1778         /* Change the USB controller PHY type to HSIC */
1779         val = readl(base + HOSTPC1_DEVLC);
1780         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
1781         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
1782         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
1783         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
1784         writel(val, base + HOSTPC1_DEVLC);
1785
1786         val = readl(base + USB_TXFILLTUNING);
1787         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
1788                 val = USB_FIFO_TXFILL_THRES(0x10);
1789                 writel(val, base + USB_TXFILLTUNING);
1790         }
1791
1792         val = readl(base + USB_PORTSC);
1793         val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN);
1794         writel(val, base + USB_PORTSC);
1795
1796         val = readl(base + UHSIC_PADS_CFG0);
1797         /* Clear RTUNEN, SLEWP & SLEWN bit fields */
1798         val &= ~(UHSIC_TX_RTUNEN | UHSIC_TX_SLEWP | UHSIC_TX_SLEWN);
1799         /* set Rtune impedance to 50 ohm */
1800         val |= UHSIC_TX_RTUNE(8);
1801         writel(val, base + UHSIC_PADS_CFG0);
1802
1803         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1804                                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500)) {
1805                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
1806                 return -ETIMEDOUT;
1807         }
1808
1809         phy->phy_clk_on = true;
1810         phy->hw_accessible = true;
1811
1812         return 0;
1813 }
1814
1815 static int uhsic_phy_power_off(struct tegra_usb_phy *phy)
1816 {
1817         unsigned long val;
1818         void __iomem *base = phy->regs;
1819
1820         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1821         if (!phy->phy_clk_on) {
1822                 DBG("%s(%d) inst:[%d] phy clk is already off\n",
1823                                         __func__, __LINE__, phy->inst);
1824                 return 0;
1825         }
1826
1827         val = readl(base + UHSIC_PADS_CFG1);
1828         val &= ~UHSIC_RPU_STROBE;
1829         val |= UHSIC_RPD_STROBE;
1830         writel(val, base + UHSIC_PADS_CFG1);
1831
1832         val = readl(base + USB_SUSP_CTRL);
1833         val |= UHSIC_RESET;
1834         writel(val, base + USB_SUSP_CTRL);
1835         udelay(30);
1836
1837         utmip_powerdown_pmc_wake_detect(phy);
1838
1839         phy->phy_clk_on = false;
1840         phy->hw_accessible = false;
1841
1842         return 0;
1843 }
1844
1845 static int uhsic_phy_bus_port_power(struct tegra_usb_phy *phy)
1846 {
1847         unsigned long val;
1848         void __iomem *base = phy->regs;
1849
1850         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1851         val = readl(base + UHSIC_STAT_CFG0);
1852         val &= ~UHSIC_CONNECT_DETECT;
1853         writel(val, base + UHSIC_STAT_CFG0);
1854
1855         val = readl(base + USB_USBMODE);
1856         val |= USB_USBMODE_HOST;
1857         writel(val, base + USB_USBMODE);
1858
1859         /* Change the USB controller PHY type to HSIC */
1860         val = readl(base + HOSTPC1_DEVLC);
1861         val &= ~(HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK));
1862         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
1863         val &= ~(HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK));
1864         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
1865         writel(val, base + HOSTPC1_DEVLC);
1866
1867         val = readl(base + UHSIC_MISC_CFG0);
1868         val |= UHSIC_DETECT_SHORT_CONNECT;
1869         writel(val, base + UHSIC_MISC_CFG0);
1870         udelay(1);
1871
1872         val = readl(base + UHSIC_MISC_CFG0);
1873         val |= UHSIC_FORCE_XCVR_MODE;
1874         writel(val, base + UHSIC_MISC_CFG0);
1875
1876         val = readl(base + UHSIC_PADS_CFG1);
1877         val &= ~UHSIC_RPD_STROBE;
1878         /* safe to enable RPU on STROBE at all times during idle */
1879         val |= UHSIC_RPU_STROBE;
1880         writel(val, base + UHSIC_PADS_CFG1);
1881
1882         val = readl(base + USB_USBCMD);
1883         val &= ~USB_USBCMD_RS;
1884         writel(val, base + USB_USBCMD);
1885
1886         if (usb_phy_reg_status_wait(base + UHSIC_STAT_CFG0,
1887                         UHSIC_CONNECT_DETECT, UHSIC_CONNECT_DETECT, 25000)) {
1888                 pr_err("%s: timeout waiting for UHSIC_CONNECT_DETECT\n",
1889                                                                 __func__);
1890                 return -ETIMEDOUT;
1891         }
1892
1893         return 0;
1894 }
1895
1896 static int uhsic_phy_bus_reset(struct tegra_usb_phy *phy)
1897 {
1898         unsigned long val;
1899         void __iomem *base = phy->regs;
1900
1901         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1902
1903         /* Change the USB controller PHY type to HSIC */
1904         val = readl(base + HOSTPC1_DEVLC);
1905         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
1906         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
1907         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
1908         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
1909         writel(val, base + HOSTPC1_DEVLC);
1910         /* wait here, otherwise HOSTPC1_DEVLC_PSPD will timeout */
1911         mdelay(5);
1912
1913         val = readl(base + USB_PORTSC);
1914         val |= USB_PORTSC_PTC(5);
1915         writel(val, base + USB_PORTSC);
1916         udelay(2);
1917
1918         val = readl(base + USB_PORTSC);
1919         val &= ~(USB_PORTSC_PTC(~0));
1920         writel(val, base + USB_PORTSC);
1921         udelay(2);
1922
1923         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_LS(0),
1924                                                  0, 2000)) {
1925                 pr_err("%s: timeout waiting for USB_PORTSC_LS\n", __func__);
1926                 return -ETIMEDOUT;
1927         }
1928
1929         /* Poll until CCS is enabled */
1930         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
1931                                                  USB_PORTSC_CCS, 2000)) {
1932                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
1933                 return -ETIMEDOUT;
1934         }
1935
1936         if (usb_phy_reg_status_wait(base + HOSTPC1_DEVLC,
1937                         HOSTPC1_DEVLC_PSPD(2),
1938                         HOSTPC1_DEVLC_PSPD(2), 2000) < 0) {
1939                 pr_err("%s: timeout waiting hsic high speed configuration\n",
1940                                                 __func__);
1941                         return -ETIMEDOUT;
1942         }
1943
1944         val = readl(base + USB_USBCMD);
1945         val &= ~USB_USBCMD_RS;
1946         writel(val, base + USB_USBCMD);
1947
1948         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
1949                                                  USB_USBSTS_HCH, 2000)) {
1950                 pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
1951                 return -ETIMEDOUT;
1952         }
1953
1954         val = readl(base + UHSIC_PADS_CFG1);
1955         val &= ~UHSIC_RPU_STROBE;
1956         val |= UHSIC_RPD_STROBE;
1957         writel(val, base + UHSIC_PADS_CFG1);
1958
1959         mdelay(50);
1960
1961         val = readl(base + UHSIC_PADS_CFG1);
1962         val &= ~UHSIC_RPD_STROBE;
1963         val |= UHSIC_RPU_STROBE;
1964         writel(val, base + UHSIC_PADS_CFG1);
1965
1966         val = readl(base + USB_USBCMD);
1967         val |= USB_USBCMD_RS;
1968         writel(val, base + USB_USBCMD);
1969
1970         val = readl(base + UHSIC_PADS_CFG1);
1971         val &= ~UHSIC_RPU_STROBE;
1972         writel(val, base + UHSIC_PADS_CFG1);
1973
1974         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
1975                                                  USB_USBCMD_RS, 2000)) {
1976                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
1977                 return -ETIMEDOUT;
1978         }
1979
1980         return 0;
1981 }
1982
1983
1984 static int uhsic_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1985 {
1986         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1987
1988         usb_phy_wait_for_sof(phy);
1989
1990         return 0;
1991 }
1992
1993 static int uhsic_phy_resume(struct tegra_usb_phy *phy)
1994 {
1995         void __iomem *base = phy->regs;
1996         unsigned long val;
1997
1998         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1999
2000         /* Check if the phy resume from LP0. When the phy resume from LP0
2001          * USB register will be reset.to zero */
2002         if (!readl(base + USB_ASYNCLISTADDR)) {
2003
2004                 val = readl(base + USB_USBCMD);
2005                 val |= USB_CMD_RESET;
2006                 writel(val, base + USB_USBCMD);
2007
2008                 if (usb_phy_reg_status_wait(base + USB_USBCMD,
2009                         USB_CMD_RESET, 0, 2500) < 0) {
2010                         pr_err("%s: timeout waiting for reset\n", __func__);
2011                 }
2012
2013                 val = readl(base + USB_USBMODE);
2014                 val &= ~USB_USBMODE_MASK;
2015                 val |= USB_USBMODE_HOST;
2016                 writel(val, base + USB_USBMODE);
2017
2018                 /* Enable Port Power */
2019                 val = readl(base + USB_PORTSC);
2020                 val |= USB_PORTSC_PP;
2021                 writel(val, base + USB_PORTSC);
2022                 udelay(10);
2023
2024                 DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
2025                 readl(base + USB_USBSTS), readl(base + USB_PORTSC));
2026
2027                 uhsic_phy_bus_port_power(phy);
2028         }
2029
2030         return 0;
2031 }
2032
2033 static int uhsic_phy_post_resume(struct tegra_usb_phy *phy)
2034 {
2035         unsigned long val;
2036         void __iomem *base = phy->regs;
2037
2038         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2039         val = readl(base + USB_TXFILLTUNING);
2040         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
2041                 val = USB_FIFO_TXFILL_THRES(0x10);
2042                 writel(val, base + USB_TXFILLTUNING);
2043         }
2044
2045         return 0;
2046 }
2047
2048 static void ulpi_set_trimmer(struct tegra_usb_phy *phy)
2049 {
2050         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2051         void __iomem *base = phy->regs;
2052         unsigned long val;
2053
2054         val = ULPI_DATA_TRIMMER_SEL(config->data_trimmer);
2055         val |= ULPI_STPDIRNXT_TRIMMER_SEL(config->stpdirnxt_trimmer);
2056         val |= ULPI_DIR_TRIMMER_SEL(config->dir_trimmer);
2057         writel(val, base + ULPI_TIMING_CTRL_1);
2058         udelay(10);
2059
2060         val |= ULPI_DATA_TRIMMER_LOAD;
2061         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
2062         val |= ULPI_DIR_TRIMMER_LOAD;
2063         writel(val, base + ULPI_TIMING_CTRL_1);
2064 }
2065
2066 static int ulpi_link_phy_open(struct tegra_usb_phy *phy)
2067 {
2068 #if defined(CONFIG_TEGRA_SILICON_PLATFORM)
2069         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2070 #endif
2071         int err = 0;
2072
2073         phy->ulpi_clk = NULL;
2074         DBG("%s inst:[%d]\n", __func__, phy->inst);
2075
2076 #if defined(CONFIG_TEGRA_SILICON_PLATFORM)
2077         if (config->clk) {
2078                 phy->ulpi_clk = clk_get_sys(NULL, config->clk);
2079                 if (IS_ERR(phy->ulpi_clk)) {
2080                         pr_err("%s: can't get ulpi clock\n", __func__);
2081                         err = -ENXIO;
2082                 }
2083         }
2084 #endif
2085         phy->ulpi_vp = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
2086         phy->ulpi_vp->io_priv = phy->regs + ULPI_VIEWPORT;
2087
2088         return err;
2089 }
2090
2091 static void ulpi_link_phy_close(struct tegra_usb_phy *phy)
2092 {
2093         DBG("%s inst:[%d]\n", __func__, phy->inst);
2094         if (phy->ulpi_clk)
2095                 clk_put(phy->ulpi_clk);
2096 }
2097
2098 static int ulpi_link_phy_irq(struct tegra_usb_phy *phy)
2099 {
2100         DBG("%s inst:[%d]\n", __func__, phy->inst);
2101         return IRQ_HANDLED;
2102 }
2103
2104 static int ulpi_link_phy_power_off(struct tegra_usb_phy *phy)
2105 {
2106         unsigned long val;
2107         void __iomem *base = phy->regs;
2108         int ret;
2109
2110         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2111         if (!phy->phy_clk_on) {
2112                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
2113                                                         __LINE__, phy->inst);
2114                 return 0;
2115         }
2116
2117         /* Disable VbusValid, SessEnd comparators */
2118         ret = usb_phy_io_write(phy->ulpi_vp, 0x00, 0x0D);
2119         if (ret)
2120                 pr_err("%s: ulpi write 0x0D failed\n", __func__);
2121
2122         ret = usb_phy_io_write(phy->ulpi_vp, 0x00, 0x10);
2123         if (ret)
2124                 pr_err("%s: ulpi write 0x10 failed\n", __func__);
2125
2126         /* Disable IdFloat comparator */
2127         ret = usb_phy_io_write(phy->ulpi_vp, 0x00, 0x19);
2128         if (ret)
2129                 pr_err("%s: ulpi write 0x19 failed\n", __func__);
2130
2131         ret = usb_phy_io_write(phy->ulpi_vp, 0x00, 0x1D);
2132         if (ret)
2133                 pr_err("%s: ulpi write 0x1D failed\n", __func__);
2134
2135         phy->port_speed = (readl(base + USB_PORTSC) >> 26) &
2136                         USB_PORTSC_PSPD_MASK;
2137
2138         /* Clear WKCN/WKDS/WKOC wake-on events that can cause the USB
2139          * Controller to immediately bring the ULPI PHY out of low power
2140          */
2141         val = readl(base + USB_PORTSC);
2142         val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN);
2143         writel(val, base + USB_PORTSC);
2144
2145         /* Put the PHY in the low power mode */
2146         val = readl(base + USB_PORTSC);
2147         val |= USB_PORTSC_PHCD;
2148         writel(val, base + USB_PORTSC);
2149
2150         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
2151                                                          0, 2500)) {
2152                 pr_err("%s: timeout waiting for phy to stop\n", __func__);
2153         }
2154
2155         if (phy->ulpi_clk)
2156                 clk_disable(phy->ulpi_clk);
2157
2158         phy->phy_clk_on = false;
2159         phy->hw_accessible = false;
2160
2161         return 0;
2162 }
2163
2164 static int ulpi_link_phy_power_on(struct tegra_usb_phy *phy)
2165 {
2166         int ret;
2167         unsigned long val;
2168         void __iomem *base = phy->regs;
2169
2170         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2171         if (phy->phy_clk_on) {
2172                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
2173                                                         __LINE__, phy->inst);
2174                 return 0;
2175         }
2176
2177         if (phy->ulpi_clk) {
2178                 clk_enable(phy->ulpi_clk);
2179                 mdelay(1);
2180         }
2181
2182         val = readl(base + USB_SUSP_CTRL);
2183         val |= UHSIC_RESET;
2184         writel(val, base + USB_SUSP_CTRL);
2185
2186         val = readl(base + ULPI_TIMING_CTRL_0);
2187         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
2188         writel(val, base + ULPI_TIMING_CTRL_0);
2189
2190         val = readl(base + USB_SUSP_CTRL);
2191         val |= ULPI_PHY_ENABLE;
2192         writel(val, base + USB_SUSP_CTRL);
2193
2194         val = readl(base + USB_SUSP_CTRL);
2195         val |= USB_SUSP_CLR;
2196         writel(val, base + USB_SUSP_CTRL);
2197
2198         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
2199                                                 USB_PHY_CLK_VALID, 2500))
2200                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2201
2202         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_CLKEN,
2203                                                 USB_CLKEN, 2500))
2204                 pr_err("%s: timeout waiting for AHB clock\n", __func__);
2205
2206         val = readl(base + USB_SUSP_CTRL);
2207         val &= ~USB_SUSP_CLR;
2208         writel(val, base + USB_SUSP_CTRL);
2209
2210         val = 0;
2211         writel(val, base + ULPI_TIMING_CTRL_1);
2212
2213         ulpi_set_trimmer(phy);
2214
2215         /* Fix VbusInvalid due to floating VBUS */
2216         ret = usb_phy_io_write(phy->ulpi_vp, 0x40, 0x08);
2217         if (ret) {
2218                 pr_err("%s: ulpi write failed\n", __func__);
2219                 return ret;
2220         }
2221
2222         ret = usb_phy_io_write(phy->ulpi_vp, 0x80, 0x0B);
2223         if (ret) {
2224                 pr_err("%s: ulpi write failed\n", __func__);
2225                 return ret;
2226         }
2227
2228         val = readl(base + USB_PORTSC);
2229         val |= USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN;
2230         writel(val, base + USB_PORTSC);
2231
2232         phy->phy_clk_on = true;
2233         phy->hw_accessible = true;
2234
2235         return 0;
2236 }
2237
2238 static inline void ulpi_link_phy_set_tristate(bool enable)
2239 {
2240 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2241         int tristate = (enable) ? TEGRA_TRI_TRISTATE : TEGRA_TRI_NORMAL;
2242
2243         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAA, tristate);
2244         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAB, tristate);
2245         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UDA, tristate);
2246 #endif
2247 }
2248
2249 static void ulpi_link_phy_restore_start(struct tegra_usb_phy *phy)
2250 {
2251         unsigned long val;
2252         void __iomem *base = phy->regs;
2253
2254         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2255
2256         /*Tristate ulpi interface before USB controller resume*/
2257         ulpi_link_phy_set_tristate(true);
2258
2259         val = readl(base + ULPI_TIMING_CTRL_0);
2260         val &= ~ULPI_OUTPUT_PINMUX_BYP;
2261         writel(val, base + ULPI_TIMING_CTRL_0);
2262 }
2263
2264 static void ulpi_link_phy_restore_end(struct tegra_usb_phy *phy)
2265 {
2266         unsigned long val;
2267         void __iomem *base = phy->regs;
2268
2269         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2270
2271         val = readl(base + ULPI_TIMING_CTRL_0);
2272         val |= ULPI_OUTPUT_PINMUX_BYP;
2273         writel(val, base + ULPI_TIMING_CTRL_0);
2274
2275         ulpi_link_phy_set_tristate(false);
2276 }
2277
2278 static int ulpi_link_phy_resume(struct tegra_usb_phy *phy)
2279 {
2280         int status = 0;
2281
2282         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2283         if (phy->pdata->u_data.host.power_off_on_suspend) {
2284                 status = ulpi_link_phy_power_on(phy);
2285                 if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
2286                         ulpi_link_phy_restore_start(phy);
2287                         usb_phy_bringup_host_controller(phy);
2288                         ulpi_link_phy_restore_end(phy);
2289                 }
2290         }
2291
2292         return status;
2293 }
2294
2295 static void reset_utmip_uhsic(void __iomem *base)
2296 {
2297         unsigned long val;
2298
2299         val = readl(base + USB_SUSP_CTRL);
2300         val |= UHSIC_RESET;
2301         writel(val, base + USB_SUSP_CTRL);
2302
2303         val = readl(base + USB_SUSP_CTRL);
2304         val |= UTMIP_RESET;
2305         writel(val, base + USB_SUSP_CTRL);
2306 }
2307
2308 static void ulpi_set_host(void __iomem *base)
2309 {
2310         unsigned long val;
2311
2312         val = readl(base + USB_USBMODE);
2313         val &= ~USB_USBMODE_MASK;
2314         val |= USB_USBMODE_HOST;
2315         writel(val, base + USB_USBMODE);
2316
2317         val = readl(base + HOSTPC1_DEVLC);
2318         val |= HOSTPC1_DEVLC_PTS(2);
2319         writel(val, base + HOSTPC1_DEVLC);
2320 }
2321
2322 static inline void ulpi_pinmux_bypass(struct tegra_usb_phy *phy, bool enable)
2323 {
2324         unsigned long val;
2325         void __iomem *base = phy->regs;
2326
2327         val = readl(base + ULPI_TIMING_CTRL_0);
2328
2329         if (enable)
2330                 val |= ULPI_OUTPUT_PINMUX_BYP;
2331         else
2332                 val &= ~ULPI_OUTPUT_PINMUX_BYP;
2333
2334         writel(val, base + ULPI_TIMING_CTRL_0);
2335 }
2336
2337 static inline void ulpi_null_phy_set_tristate(bool enable)
2338 {
2339 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2340         int tristate = (enable) ? TEGRA_TRI_TRISTATE : TEGRA_TRI_NORMAL;
2341         DBG("%s(%d) inst:[%s] FIXME enable pin group +++\n", __func__,
2342                                 __LINE__, enable ? "TRISTATE" : "NORMAL");
2343
2344         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA0, tristate);
2345         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA1, tristate);
2346         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA2, tristate);
2347         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA3, tristate);
2348         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA4, tristate);
2349         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA5, tristate);
2350         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA6, tristate);
2351         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA7, tristate);
2352         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_NXT, tristate);
2353
2354         if (enable)
2355                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR, tristate);
2356 #endif
2357 }
2358
2359 static void ulpi_null_phy_obs_read(void)
2360 {
2361         static void __iomem *apb_misc;
2362         unsigned slv0_obs, s2s_obs;
2363
2364         if (!apb_misc)
2365                 apb_misc = ioremap(TEGRA_APB_MISC_BASE, TEGRA_APB_MISC_SIZE);
2366
2367         writel(0x80d1003c, apb_misc + APB_MISC_GP_OBSCTRL_0);
2368         slv0_obs = readl(apb_misc + APB_MISC_GP_OBSDATA_0);
2369
2370         writel(0x80d10040, apb_misc + APB_MISC_GP_OBSCTRL_0);
2371         s2s_obs = readl(apb_misc + APB_MISC_GP_OBSDATA_0);
2372
2373         pr_debug("slv0 obs: %08x\ns2s obs: %08x\n", slv0_obs, s2s_obs);
2374 }
2375
2376 static const struct gpio ulpi_gpios[] = {
2377         {ULPI_STP, GPIOF_IN, "ULPI_STP"},
2378         {ULPI_DIR, GPIOF_OUT_INIT_LOW, "ULPI_DIR"},
2379         {ULPI_D0, GPIOF_OUT_INIT_LOW, "ULPI_D0"},
2380         {ULPI_D1, GPIOF_OUT_INIT_LOW, "ULPI_D1"},
2381 };
2382
2383 static int ulpi_null_phy_open(struct tegra_usb_phy *phy)
2384 {
2385         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2386         int ret;
2387
2388         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2389
2390         ret = gpio_request_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
2391         if (ret)
2392                 return ret;
2393
2394         if (gpio_is_valid(config->phy_restore_gpio)) {
2395                 ret = gpio_request(config->phy_restore_gpio, "phy_restore");
2396                 if (ret)
2397                         goto err_gpio_free;
2398
2399                 gpio_direction_input(config->phy_restore_gpio);
2400         }
2401
2402         tegra_periph_reset_assert(phy->ctrlr_clk);
2403         udelay(10);
2404         tegra_periph_reset_deassert(phy->ctrlr_clk);
2405
2406         return 0;
2407
2408 err_gpio_free:
2409         gpio_free_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
2410         return ret;
2411 }
2412
2413 static void ulpi_null_phy_close(struct tegra_usb_phy *phy)
2414 {
2415         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2416
2417         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2418
2419         if (gpio_is_valid(config->phy_restore_gpio))
2420                 gpio_free(config->phy_restore_gpio);
2421
2422         gpio_free_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
2423 }
2424
2425 static int ulpi_null_phy_power_off(struct tegra_usb_phy *phy)
2426 {
2427         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2428
2429         if (!phy->phy_clk_on) {
2430                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
2431                                                         __LINE__, phy->inst);
2432                 return 0;
2433         }
2434
2435         phy->phy_clk_on = false;
2436         phy->hw_accessible = false;
2437         ulpi_null_phy_set_tristate(true);
2438         return 0;
2439 }
2440
2441 /* NOTE: this function must be called before ehci reset */
2442 static int ulpi_null_phy_init(struct tegra_usb_phy *phy)
2443 {
2444         unsigned long val;
2445         void __iomem *base = phy->regs;
2446
2447         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2448         _usb_phy_init(phy);
2449         val = readl(base + ULPIS2S_CTRL);
2450         val |=  ULPIS2S_SLV0_CLAMP_XMIT;
2451         writel(val, base + ULPIS2S_CTRL);
2452
2453         val = readl(base + USB_SUSP_CTRL);
2454         val |= ULPIS2S_SLV0_RESET;
2455         writel(val, base + USB_SUSP_CTRL);
2456         udelay(10);
2457
2458         return 0;
2459 }
2460
2461 static int ulpi_null_phy_irq(struct tegra_usb_phy *phy)
2462 {
2463         return IRQ_HANDLED;
2464 }
2465
2466 /* NOTE: this function must be called after ehci reset */
2467 static int ulpi_null_phy_cmd_reset(struct tegra_usb_phy *phy)
2468 {
2469         unsigned long val;
2470         void __iomem *base = phy->regs;
2471
2472         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2473         ulpi_set_host(base);
2474
2475         /* remove slave0 reset */
2476         val = readl(base + USB_SUSP_CTRL);
2477         val &= ~ULPIS2S_SLV0_RESET;
2478         writel(val, base + USB_SUSP_CTRL);
2479
2480         val = readl(base + ULPIS2S_CTRL);
2481         val &=  ~ULPIS2S_SLV0_CLAMP_XMIT;
2482         writel(val, base + ULPIS2S_CTRL);
2483         udelay(10);
2484
2485         return 0;
2486 }
2487
2488 static int ulpi_null_phy_restore(struct tegra_usb_phy *phy)
2489 {
2490         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2491         unsigned long timeout;
2492         int ulpi_stp = ULPI_STP;
2493
2494         if (gpio_is_valid(config->phy_restore_gpio))
2495                 ulpi_stp = config->phy_restore_gpio;
2496
2497         /* disable ULPI pinmux bypass */
2498         ulpi_pinmux_bypass(phy, false);
2499
2500         /* driving linstate by GPIO */
2501         gpio_set_value(ULPI_D0, 0);
2502         gpio_set_value(ULPI_D1, 0);
2503
2504         /* driving DIR high */
2505         gpio_set_value(ULPI_DIR, 1);
2506
2507         /* remove ULPI tristate */
2508         ulpi_null_phy_set_tristate(false);
2509
2510         /* wait for STP high */
2511         timeout = jiffies + msecs_to_jiffies(25);
2512
2513         while (!gpio_get_value(ulpi_stp)) {
2514                 if (time_after(jiffies, timeout)) {
2515                         pr_warn("phy restore timeout\n");
2516                         return 1;
2517                 }
2518         }
2519
2520         return 0;
2521 }
2522
2523 static int ulpi_null_phy_lp0_resume(struct tegra_usb_phy *phy)
2524 {
2525         unsigned long val;
2526         void __iomem *base = phy->regs;
2527
2528         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2529         ulpi_null_phy_init(phy);
2530
2531         val = readl(base + USB_USBCMD);
2532         val |= USB_CMD_RESET;
2533         writel(val, base + USB_USBCMD);
2534
2535         if (usb_phy_reg_status_wait(base + USB_USBCMD,
2536                 USB_CMD_RESET, 0, 2500) < 0) {
2537                 pr_err("%s: timeout waiting for reset\n", __func__);
2538         }
2539
2540         ulpi_null_phy_cmd_reset(phy);
2541
2542         val = readl(base + USB_USBCMD);
2543         val |= USB_USBCMD_RS;
2544         writel(val, base + USB_USBCMD);
2545         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2546                                                  USB_USBCMD_RS, 2000)) {
2547                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2548                 return -ETIMEDOUT;
2549         }
2550
2551         /* Enable Port Power */
2552         val = readl(base + USB_PORTSC);
2553         val |= USB_PORTSC_PP;
2554         writel(val, base + USB_PORTSC);
2555         udelay(10);
2556
2557         ulpi_null_phy_restore(phy);
2558
2559         return 0;
2560 }
2561
2562 static int ulpi_null_phy_power_on(struct tegra_usb_phy *phy)
2563 {
2564         unsigned long val;
2565         void __iomem *base = phy->regs;
2566         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2567
2568         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2569         if (phy->phy_clk_on) {
2570                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
2571                                                         __LINE__, phy->inst);
2572                 return 0;
2573         }
2574         reset_utmip_uhsic(base);
2575
2576         /* remove ULPI PADS CLKEN reset */
2577         val = readl(base + USB_SUSP_CTRL);
2578         val &= ~ULPI_PADS_CLKEN_RESET;
2579         writel(val, base + USB_SUSP_CTRL);
2580         udelay(10);
2581
2582         val = readl(base + ULPI_TIMING_CTRL_0);
2583         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
2584         writel(val, base + ULPI_TIMING_CTRL_0);
2585
2586         val = readl(base + USB_SUSP_CTRL);
2587         val |= ULPI_PHY_ENABLE;
2588         writel(val, base + USB_SUSP_CTRL);
2589         udelay(10);
2590
2591         /* set timming parameters */
2592         val = readl(base + ULPI_TIMING_CTRL_0);
2593         val |= ULPI_SHADOW_CLK_LOOPBACK_EN;
2594         val &= ~ULPI_SHADOW_CLK_SEL;
2595         val &= ~ULPI_LBK_PAD_EN;
2596         val |= ULPI_SHADOW_CLK_DELAY(config->shadow_clk_delay);
2597         val |= ULPI_CLOCK_OUT_DELAY(config->clock_out_delay);
2598         val |= ULPI_LBK_PAD_E_INPUT_OR;
2599         writel(val, base + ULPI_TIMING_CTRL_0);
2600
2601         writel(0, base + ULPI_TIMING_CTRL_1);
2602         udelay(10);
2603
2604         /* start internal 60MHz clock */
2605         val = readl(base + ULPIS2S_CTRL);
2606         val |= ULPIS2S_ENA;
2607         val |= ULPIS2S_SUPPORT_DISCONNECT;
2608         val |= ULPIS2S_SPARE((phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) ? 3 : 1);
2609         val |= ULPIS2S_PLLU_MASTER_BLASTER60;
2610         writel(val, base + ULPIS2S_CTRL);
2611
2612         /* select ULPI_CORE_CLK_SEL to SHADOW_CLK */
2613         val = readl(base + ULPI_TIMING_CTRL_0);
2614         val |= ULPI_CORE_CLK_SEL;
2615         writel(val, base + ULPI_TIMING_CTRL_0);
2616         udelay(10);
2617
2618         /* enable ULPI null phy clock - can't set the trimmers before this */
2619         val = readl(base + ULPI_TIMING_CTRL_0);
2620         val |= ULPI_CLK_OUT_ENA;
2621         writel(val, base + ULPI_TIMING_CTRL_0);
2622         udelay(10);
2623
2624         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
2625                                                  USB_PHY_CLK_VALID, 2500)) {
2626                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2627                 return -ETIMEDOUT;
2628         }
2629
2630         /* set ULPI trimmers */
2631         ulpi_set_trimmer(phy);
2632
2633         ulpi_set_host(base);
2634
2635         /* remove slave0 reset */
2636         val = readl(base + USB_SUSP_CTRL);
2637         val &= ~ULPIS2S_SLV0_RESET;
2638         writel(val, base + USB_SUSP_CTRL);
2639
2640         /* remove slave1 and line reset */
2641         val = readl(base + USB_SUSP_CTRL);
2642         val &= ~ULPIS2S_SLV1_RESET;
2643         val &= ~ULPIS2S_LINE_RESET;
2644
2645         /* remove ULPI PADS reset */
2646         val &= ~ULPI_PADS_RESET;
2647         writel(val, base + USB_SUSP_CTRL);
2648
2649         if (!phy->ulpi_clk_padout_ena) {
2650                 val = readl(base + ULPI_TIMING_CTRL_0);
2651                 val |= ULPI_CLK_PADOUT_ENA;
2652                 writel(val, base + ULPI_TIMING_CTRL_0);
2653                 phy->ulpi_clk_padout_ena = true;
2654         } else {
2655                 if (!readl(base + USB_ASYNCLISTADDR))
2656                         ulpi_null_phy_lp0_resume(phy);
2657         }
2658         udelay(10);
2659
2660         phy->phy_clk_on = true;
2661         phy->hw_accessible = true;
2662
2663         return 0;
2664 }
2665
2666 static int ulpi_null_phy_pre_resume(struct tegra_usb_phy *phy,
2667                                     bool remote_wakeup)
2668 {
2669         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2670         ulpi_null_phy_obs_read();
2671         return 0;
2672 }
2673
2674 static int ulpi_null_phy_post_resume(struct tegra_usb_phy *phy)
2675 {
2676         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2677         ulpi_null_phy_obs_read();
2678         return 0;
2679 }
2680
2681 static int ulpi_null_phy_resume(struct tegra_usb_phy *phy)
2682 {
2683         unsigned long val;
2684         void __iomem *base = phy->regs;
2685
2686         if (!readl(base + USB_ASYNCLISTADDR)) {
2687                 /* enable ULPI CLK output pad */
2688                 val = readl(base + ULPI_TIMING_CTRL_0);
2689                 val |= ULPI_CLK_PADOUT_ENA;
2690                 writel(val, base + ULPI_TIMING_CTRL_0);
2691
2692                 /* enable ULPI pinmux bypass */
2693                 ulpi_pinmux_bypass(phy, true);
2694                 udelay(5);
2695 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2696                 /* remove DIR tristate */
2697                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR,
2698                                           TEGRA_TRI_NORMAL);
2699 #endif
2700         }
2701         return 0;
2702 }
2703
2704 static struct tegra_usb_phy_ops utmi_phy_ops = {
2705         .init           = _usb_phy_init,
2706         .reset          = usb_phy_reset,
2707         .open           = utmi_phy_open,
2708         .close          = utmi_phy_close,
2709         .irq            = utmi_phy_irq,
2710         .power_on       = utmi_phy_power_on,
2711         .power_off      = utmi_phy_power_off,
2712         .pre_resume = utmi_phy_pre_resume,
2713         .resume = utmi_phy_resume,
2714         .post_resume    = utmi_phy_post_resume,
2715         .charger_detect = utmi_phy_charger_detect,
2716 };
2717
2718 static struct tegra_usb_phy_ops uhsic_phy_ops = {
2719         .init           = _usb_phy_init,
2720         .open           = uhsic_phy_open,
2721         .power_on       = uhsic_phy_power_on,
2722         .power_off      = uhsic_phy_power_off,
2723         .pre_resume = uhsic_phy_pre_resume,
2724         .resume = uhsic_phy_resume,
2725         .post_resume = uhsic_phy_post_resume,
2726         .port_power = uhsic_phy_bus_port_power,
2727         .bus_reset      = uhsic_phy_bus_reset,
2728 };
2729
2730 static struct tegra_usb_phy_ops ulpi_link_phy_ops = {
2731         .init           = _usb_phy_init,
2732         .reset          = usb_phy_reset,
2733         .open           = ulpi_link_phy_open,
2734         .close          = ulpi_link_phy_close,
2735         .irq            = ulpi_link_phy_irq,
2736         .power_on       = ulpi_link_phy_power_on,
2737         .power_off      = ulpi_link_phy_power_off,
2738         .resume         = ulpi_link_phy_resume,
2739 };
2740
2741 static struct tegra_usb_phy_ops ulpi_null_phy_ops = {
2742         .open           = ulpi_null_phy_open,
2743         .close          = ulpi_null_phy_close,
2744         .init           = ulpi_null_phy_init,
2745         .irq            = ulpi_null_phy_irq,
2746         .power_on       = ulpi_null_phy_power_on,
2747         .power_off      = ulpi_null_phy_power_off,
2748         .pre_resume = ulpi_null_phy_pre_resume,
2749         .resume = ulpi_null_phy_resume,
2750         .post_resume = ulpi_null_phy_post_resume,
2751         .reset          = ulpi_null_phy_cmd_reset,
2752 };
2753
2754 static struct tegra_usb_phy_ops icusb_phy_ops;
2755
2756 static struct tegra_usb_phy_ops *phy_ops[] = {
2757         [TEGRA_USB_PHY_INTF_UTMI] = &utmi_phy_ops,
2758         [TEGRA_USB_PHY_INTF_ULPI_LINK] = &ulpi_link_phy_ops,
2759         [TEGRA_USB_PHY_INTF_ULPI_NULL] = &ulpi_null_phy_ops,
2760         [TEGRA_USB_PHY_INTF_HSIC] = &uhsic_phy_ops,
2761         [TEGRA_USB_PHY_INTF_ICUSB] = &icusb_phy_ops,
2762 };
2763
2764 int tegra11x_usb_phy_init_ops(struct tegra_usb_phy *phy)
2765 {
2766         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2767
2768         phy->ops = phy_ops[phy->pdata->phy_intf];
2769
2770         /* FIXME: uncommenting below line to make USB host mode fail*/
2771         /* usb_phy_power_down_pmc(); */
2772
2773         return 0;
2774 }