ARM: Tegra: fix compilation warnings
[linux-2.6.git] / arch / arm / mach-tegra / tegra11x_usb_phy.c
1 /*
2  * arch/arm/mach-tegra/tegra11x_usb_phy.c
3  *
4  * Copyright (C) 2012 NVIDIA Corporation
5  *
6  *
7  * This software is licensed under the terms of the GNU General Public
8  * License version 2, as published by the Free Software Foundation, and
9  * may be copied, distributed, and modified under those terms.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17 #include <linux/resource.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/slab.h>
21 #include <linux/err.h>
22 #include <linux/platform_device.h>
23 #include <linux/io.h>
24 #include <linux/gpio.h>
25 #include <linux/interrupt.h>
26 #include <linux/clk.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <mach/iomap.h>
30 #include <mach/pinmux.h>
31 #include <mach/pinmux-t11.h>
32 #include "tegra_usb_phy.h"
33 #include "fuse.h"
34
35 #define USB_USBCMD              0x130
36 #define   USB_USBCMD_RS         (1 << 0)
37 #define   USB_CMD_RESET (1<<1)
38
39 #define USB_USBSTS              0x134
40 #define   USB_USBSTS_PCI        (1 << 2)
41 #define   USB_USBSTS_SRI        (1 << 7)
42 #define   USB_USBSTS_HCH        (1 << 12)
43
44 #define USB_TXFILLTUNING        0x154
45 #define USB_FIFO_TXFILL_THRES(x)   (((x) & 0x1f) << 16)
46 #define USB_FIFO_TXFILL_MASK    0x1f0000
47
48 #define USB_ASYNCLISTADDR       0x148
49
50 #define ICUSB_CTRL              0x15c
51
52 #define USB_PORTSC              0x174
53 #define   USB_PORTSC_WKOC       (1 << 22)
54 #define   USB_PORTSC_WKDS       (1 << 21)
55 #define   USB_PORTSC_WKCN       (1 << 20)
56 #define   USB_PORTSC_PTC(x)     (((x) & 0xf) << 16)
57 #define   USB_PORTSC_PP (1 << 12)
58 #define   USB_PORTSC_LS(x) (((x) & 0x3) << 10)
59 #define   USB_PORTSC_SUSP       (1 << 7)
60 #define   USB_PORTSC_RESUME     (1 << 6)
61 #define   USB_PORTSC_OCC        (1 << 5)
62 #define   USB_PORTSC_PEC        (1 << 3)
63 #define   USB_PORTSC_PE         (1 << 2)
64 #define   USB_PORTSC_CSC        (1 << 1)
65 #define   USB_PORTSC_CCS        (1 << 0)
66 #define   USB_PORTSC_RWC_BITS (USB_PORTSC_CSC | USB_PORTSC_PEC | USB_PORTSC_OCC)
67
68 #define HOSTPC1_DEVLC           0x1b4
69 #define   HOSTPC1_DEVLC_PHCD            (1 << 22)
70 #define   HOSTPC1_DEVLC_PTS(x)          (((x) & 0x7) << 29)
71 #define   HOSTPC1_DEVLC_PTS_MASK        7
72 #define   HOSTPC1_DEVLC_PTS_HSIC        4
73 #define   HOSTPC1_DEVLC_STS             (1 << 28)
74 #define   HOSTPC1_DEVLC_PSPD(x)         (((x) & 0x3) << 25)
75 #define   HOSTPC1_DEVLC_PSPD_MASK       3
76 #define   HOSTPC1_DEVLC_PSPD_HIGH_SPEED 2
77 #define   HOSTPC1_DEVLC_NYT_ASUS        1
78
79 #define USB_USBMODE             0x1f8
80 #define   USB_USBMODE_MASK              (3 << 0)
81 #define   USB_USBMODE_HOST              (3 << 0)
82 #define   USB_USBMODE_DEVICE            (2 << 0)
83
84 #define USB_SUSP_CTRL           0x400
85 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
86 #define   USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
87 #define   USB_SUSP_CLR                  (1 << 5)
88 #define   USB_PHY_CLK_VALID             (1 << 7)
89 #define   USB_PHY_CLK_VALID_INT_ENB     (1 << 9)
90 #define   USB_PHY_CLK_VALID_INT_STS     (1 << 8)
91 #define   UTMIP_RESET                   (1 << 11)
92 #define   UTMIP_PHY_ENABLE              (1 << 12)
93 #define   ULPI_PHY_ENABLE               (1 << 13)
94 #define   UHSIC_RESET                   (1 << 14)
95 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
96 #define   UHSIC_PHY_ENABLE              (1 << 19)
97 #define   ULPIS2S_SLV0_RESET            (1 << 20)
98 #define   ULPIS2S_SLV1_RESET            (1 << 21)
99 #define   ULPIS2S_LINE_RESET            (1 << 22)
100 #define   ULPI_PADS_RESET               (1 << 23)
101 #define   ULPI_PADS_CLKEN_RESET         (1 << 24)
102
103 #define USB_PHY_VBUS_WAKEUP_ID  0x408
104 #define   VDAT_DET_INT_EN       (1 << 16)
105 #define   VDAT_DET_CHG_DET      (1 << 17)
106 #define   VDAT_DET_STS          (1 << 18)
107 #define   USB_ID_STATUS         (1 << 2)
108
109 #define ULPIS2S_CTRL            0x418
110 #define   ULPIS2S_ENA                   (1 << 0)
111 #define   ULPIS2S_SUPPORT_DISCONNECT    (1 << 2)
112 #define   ULPIS2S_PLLU_MASTER_BLASTER60 (1 << 3)
113 #define   ULPIS2S_SPARE(x)              (((x) & 0xF) << 8)
114 #define   ULPIS2S_FORCE_ULPI_CLK_OUT    (1 << 12)
115 #define   ULPIS2S_DISCON_DONT_CHECK_SE0 (1 << 13)
116 #define   ULPIS2S_SUPPORT_HS_KEEP_ALIVE (1 << 14)
117 #define   ULPIS2S_DISABLE_STP_PU        (1 << 15)
118 #define   ULPIS2S_SLV0_CLAMP_XMIT       (1 << 16)
119
120 #define ULPI_TIMING_CTRL_0      0x424
121 #define   ULPI_CLOCK_OUT_DELAY(x)       ((x) & 0x1F)
122 #define   ULPI_OUTPUT_PINMUX_BYP        (1 << 10)
123 #define   ULPI_CLKOUT_PINMUX_BYP        (1 << 11)
124 #define   ULPI_SHADOW_CLK_LOOPBACK_EN   (1 << 12)
125 #define   ULPI_SHADOW_CLK_SEL           (1 << 13)
126 #define   ULPI_CORE_CLK_SEL             (1 << 14)
127 #define   ULPI_SHADOW_CLK_DELAY(x)      (((x) & 0x1F) << 16)
128 #define   ULPI_LBK_PAD_EN               (1 << 26)
129 #define   ULPI_LBK_PAD_E_INPUT_OR       (1 << 27)
130 #define   ULPI_CLK_OUT_ENA              (1 << 28)
131 #define   ULPI_CLK_PADOUT_ENA           (1 << 29)
132
133 #define ULPI_TIMING_CTRL_1      0x428
134 #define   ULPI_DATA_TRIMMER_LOAD        (1 << 0)
135 #define   ULPI_DATA_TRIMMER_SEL(x)      (((x) & 0x7) << 1)
136 #define   ULPI_STPDIRNXT_TRIMMER_LOAD   (1 << 16)
137 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
138 #define   ULPI_DIR_TRIMMER_LOAD         (1 << 24)
139 #define   ULPI_DIR_TRIMMER_SEL(x)       (((x) & 0x7) << 25)
140
141 #define USB_IF_SPARE    0x498
142 #define   USB_HS_RSM_EOP_EN         (1 << 4)
143 #define   USB_PORT_SUSPEND_EN       (1 << 5)
144
145 #define USB_NEW_CONTROL  0x4c0
146 #define   USB_COHRENCY_EN           (1 << 0)
147 #define   USB_MEM_ALLIGNMENT_MUX_EN (1 << 1)
148
149 #define UTMIP_XCVR_CFG0         0x808
150 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
151 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
152 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
153 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
154 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
155 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
156 #define   UTMIP_XCVR_LSBIAS_SEL                 (1 << 21)
157 #define   UTMIP_XCVR_SETUP_MSB(x)               (((x) & 0x7) << 22)
158 #define   UTMIP_XCVR_HSSLEW_MSB(x)              (((x) & 0x7f) << 25)
159 #define   UTMIP_XCVR_MAX_OFFSET         2
160 #define   UTMIP_XCVR_SETUP_MAX_VALUE    0x7f
161 #define   UTMIP_XCVR_SETUP_MIN_VALUE    0
162 #define   XCVR_SETUP_MSB_CALIB(x) ((x) >> 4)
163
164 #define UTMIP_BIAS_CFG0         0x80c
165 #define   UTMIP_OTGPD                   (1 << 11)
166 #define   UTMIP_BIASPD                  (1 << 10)
167 #define   UTMIP_HSSQUELCH_LEVEL(x)      (((x) & 0x3) << 0)
168 #define   UTMIP_HSDISCON_LEVEL(x)       (((x) & 0x3) << 2)
169 #define   UTMIP_HSDISCON_LEVEL_MSB      (1 << 24)
170
171 #define UTMIP_HSRX_CFG0         0x810
172 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
173 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
174
175 #define UTMIP_HSRX_CFG1         0x814
176 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
177
178 #define UTMIP_TX_CFG0           0x820
179 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
180 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
181
182 #define UTMIP_DEBOUNCE_CFG0 0x82c
183 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
184
185 #define UTMIP_BAT_CHRG_CFG0 0x830
186 #define   UTMIP_PD_CHRG                 (1 << 0)
187 #define   UTMIP_ON_SINK_EN              (1 << 2)
188 #define   UTMIP_OP_SRC_EN               (1 << 3)
189
190 #define UTMIP_XCVR_CFG1         0x838
191 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
192 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
193 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
194 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
195
196 #define UTMIP_BIAS_CFG1         0x83c
197 #define   UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
198 #define   UTMIP_BIAS_PDTRK_POWERDOWN    (1 << 0)
199 #define   UTMIP_BIAS_PDTRK_POWERUP      (1 << 1)
200
201 #define UTMIP_MISC_CFG0         0x824
202 #define   UTMIP_DPDM_OBSERVE            (1 << 26)
203 #define   UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
204 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J   UTMIP_DPDM_OBSERVE_SEL(0xf)
205 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K   UTMIP_DPDM_OBSERVE_SEL(0xe)
206 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
207 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
208 #define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
209 #define   FORCE_PULLDN_DM       (1 << 8)
210 #define   FORCE_PULLDN_DP       (1 << 9)
211 #define   COMB_TERMS            (1 << 0)
212 #define   ALWAYS_FREE_RUNNING_TERMS (1 << 1)
213
214 #define UTMIP_SPARE_CFG0        0x834
215 #define   FUSE_SETUP_SEL                (1 << 3)
216 #define   FUSE_ATERM_SEL                (1 << 4)
217
218 #define UTMIP_PMC_WAKEUP0               0x84c
219 #define   EVENT_INT_ENB                 (1 << 0)
220
221 #define UTMIP_BIAS_STS0                 0x840
222 #define   UTMIP_RCTRL_VAL(x)            (((x) & 0xffff) << 0)
223 #define   UTMIP_TCTRL_VAL(x)            (((x) & (0xffff << 16)) >> 16)
224
225 #define UHSIC_PLL_CFG1                          0xc04
226 #define   UHSIC_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
227 #define   UHSIC_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 14)
228
229 #define UHSIC_HSRX_CFG0                         0xc08
230 #define   UHSIC_ELASTIC_UNDERRUN_LIMIT(x)       (((x) & 0x1f) << 2)
231 #define   UHSIC_ELASTIC_OVERRUN_LIMIT(x)        (((x) & 0x1f) << 8)
232 #define   UHSIC_IDLE_WAIT(x)                    (((x) & 0x1f) << 13)
233
234 #define UHSIC_HSRX_CFG1                         0xc0c
235 #define   UHSIC_HS_SYNC_START_DLY(x)            (((x) & 0x1f) << 1)
236
237 #define UHSIC_TX_CFG0                           0xc10
238 #define UHSIC_HS_READY_WAIT_FOR_VALID   (1 << 9)
239 #define UHSIC_MISC_CFG0                         0xc14
240 #define   UHSIC_SUSPEND_EXIT_ON_EDGE            (1 << 7)
241 #define   UHSIC_DETECT_SHORT_CONNECT            (1 << 8)
242 #define   UHSIC_FORCE_XCVR_MODE                 (1 << 15)
243 #define   UHSIC_DISABLE_BUSRESET                (1 << 20)
244 #define UHSIC_MISC_CFG1                         0xc18
245 #define   UHSIC_PLLU_STABLE_COUNT(x)            (((x) & 0xfff) << 2)
246
247 #define UHSIC_PADS_CFG0                         0xc1c
248 #define   UHSIC_TX_RTUNEN                       0xf000
249 #define   UHSIC_TX_RTUNE(x)                     (((x) & 0xf) << 12)
250
251 #define UHSIC_PADS_CFG1                         0xc20
252 #define   UHSIC_PD_BG                           (1 << 2)
253 #define   UHSIC_PD_TX                           (1 << 3)
254 #define   UHSIC_PD_TRK                          (1 << 4)
255 #define   UHSIC_PD_RX                           (1 << 5)
256 #define   UHSIC_PD_ZI                           (1 << 6)
257 #define   UHSIC_RX_SEL                          (1 << 7)
258 #define   UHSIC_RPD_DATA                        (1 << 9)
259 #define   UHSIC_RPD_STROBE                      (1 << 10)
260 #define   UHSIC_RPU_DATA                        (1 << 11)
261 #define   UHSIC_RPU_STROBE                      (1 << 12)
262
263 #define UHSIC_STAT_CFG0                 0xc28
264 #define   UHSIC_CONNECT_DETECT                  (1 << 0)
265
266 #define PMC_USB_DEBOUNCE                        0xec
267 #define   UTMIP_LINE_DEB_CNT(x)                 (((x) & 0xf) << 16)
268
269 #define PMC_USB_AO                              0xf0
270 #define PMC_POWER_DOWN_MASK                     0xffff
271 #define HSIC_RESERVED_P0                        (3 << 14)
272 #define HSIC_STOBE_VAL_PD_P0                    (1 << 13)
273 #define HSIC_DATA_VAL_PD_P0                     (1 << 12)
274 #define USB_ID_PD(inst)                         (1 << ((4*(inst))+3))
275 #define VBUS_WAKEUP_PD(inst)                    (1 << ((4*(inst))+2))
276 #define   USBON_VAL_PD(inst)                    (1 << ((4*(inst))+1))
277 #define   USBON_VAL_PD_P2                       (1 << 9)
278 #define   USBON_VAL_PD_P1                       (1 << 5)
279 #define   USBON_VAL_PD_P0                       (1 << 1)
280 #define   USBOP_VAL_PD(inst)                    (1 << (4*(inst)))
281 #define   USBOP_VAL_PD_P2                       (1 << 8)
282 #define   USBOP_VAL_PD_P1                       (1 << 4)
283 #define   USBOP_VAL_PD_P0                       (1 << 0)
284 #define   PMC_USB_AO_PD_P2                      (0xf << 8)
285 #define   PMC_USB_AO_ID_PD_P0                   (1 << 3)
286 #define   PMC_USB_AO_VBUS_WAKEUP_PD_P0  (1 << 2)
287
288 #define PMC_TRIGGERS                    0x1ec
289 #define   UTMIP_CLR_WALK_PTR(inst)      (1 << (inst))
290 #define   UTMIP_CLR_WALK_PTR_P2         (1 << 2)
291 #define   UTMIP_CLR_WALK_PTR_P1         (1 << 1)
292 #define   UTMIP_CLR_WALK_PTR_P0         (1 << 0)
293 #define   UTMIP_CAP_CFG(inst)   (1 << ((inst)+4))
294 #define   UTMIP_CAP_CFG_P2              (1 << 6)
295 #define   UTMIP_CAP_CFG_P1              (1 << 5)
296 #define   UTMIP_CAP_CFG_P0              (1 << 4)
297 #define   UTMIP_CLR_WAKE_ALARM(inst)            (1 << ((inst)+12))
298 #define   UTMIP_CLR_WAKE_ALARM_P2       (1 << 14)
299
300 #define PMC_PAD_CFG             (0x1f4)
301
302 #define PMC_UTMIP_TERM_PAD_CFG  0x1f8
303 #define   PMC_TCTRL_VAL(x)      (((x) & 0x1f) << 5)
304 #define   PMC_RCTRL_VAL(x)      (((x) & 0x1f) << 0)
305
306 #define UHSIC_SLEEPWALK_REG             0x210
307 #define UHSIC_DATA_RPD_D                (1 << 25)
308 #define UHSIC_STRB_RPD_D                (1 << 24)
309 #define UHSIC_DATA_RPD_C                (1 << 17)
310 #define UHSIC_STRB_RPD_C                (1 << 16)
311 #define UHSIC_DATA_RPD_B                (1 << 9)
312 #define UHSIC_STRB_RPD_B                (1 << 8)
313 #define UHSIC_DATA_RPD_A                (1 << 1)
314 #define UHSIC_STRB_RPD_A                (1 << 0)
315
316 #define PMC_SLEEP_CFG                   0x1fc
317 #define   UTMIP_TCTRL_USE_PMC(inst) (1 << ((8*(inst))+3))
318 #define   UTMIP_TCTRL_USE_PMC_P2                (1 << 19)
319 #define   UTMIP_TCTRL_USE_PMC_P1                (1 << 11)
320 #define   UTMIP_TCTRL_USE_PMC_P0                (1 << 3)
321 #define   UTMIP_RCTRL_USE_PMC(inst) (1 << ((8*(inst))+2))
322 #define   UTMIP_RCTRL_USE_PMC_P2                (1 << 18)
323 #define   UTMIP_RCTRL_USE_PMC_P1                (1 << 10)
324 #define   UTMIP_RCTRL_USE_PMC_P0                (1 << 2)
325 #define   UTMIP_FSLS_USE_PMC(inst)      (1 << ((8*(inst))+1))
326 #define   UTMIP_FSLS_USE_PMC_P2         (1 << 17)
327 #define   UTMIP_FSLS_USE_PMC_P1         (1 << 9)
328 #define   UTMIP_FSLS_USE_PMC_P0         (1 << 1)
329 #define   UTMIP_MASTER_ENABLE(inst) (1 << (8*(inst)))
330 #define   UTMIP_MASTER_ENABLE_P2                (1 << 16)
331 #define   UTMIP_MASTER_ENABLE_P1                (1 << 8)
332 #define   UTMIP_MASTER_ENABLE_P0                (1 << 0)
333 #define UHSIC_MASTER_ENABLE_P0          (1 << 24)
334 #define UHSIC_WAKE_VAL_P0(x)            (((x) & 0xf) << 28)
335
336 #define PMC_SLEEPWALK_CFG               0x200
337 #define   UTMIP_LINEVAL_WALK_EN(inst) (1 << ((8*(inst))+7))
338 #define   UTMIP_LINEVAL_WALK_EN_P2      (1 << 23)
339 #define   UTMIP_LINEVAL_WALK_EN_P1      (1 << 15)
340 #define   UTMIP_LINEVAL_WALK_EN_P0      (1 << 7)
341 #define   UTMIP_WAKE_VAL(inst, x) (((x) & 0xf) << ((8*(inst))+4))
342 #define   UTMIP_WAKE_VAL_P2(x)          (((x) & 0xf) << 20)
343 #define   UTMIP_WAKE_VAL_P1(x)          (((x) & 0xf) << 12)
344 #define   UTMIP_WAKE_VAL_P0(x)          (((x) & 0xf) << 4)
345 #define   WAKE_VAL_NONE         0xc
346 #define   WAKE_VAL_ANY                  0xF
347 #define   WAKE_VAL_FSJ                  0x2
348 #define   WAKE_VAL_FSK                  0x1
349 #define   WAKE_VAL_SE0                  0x0
350
351 #define PMC_SLEEPWALK_REG(inst)         (0x204 + (4*(inst)))
352 #define   UTMIP_USBOP_RPD_A     (1 << 0)
353 #define   UTMIP_USBON_RPD_A     (1 << 1)
354 #define   UTMIP_AP_A                    (1 << 4)
355 #define   UTMIP_AN_A                    (1 << 5)
356 #define   UTMIP_HIGHZ_A         (1 << 6)
357 #define   UTMIP_USBOP_RPD_B     (1 << 8)
358 #define   UTMIP_USBON_RPD_B     (1 << 9)
359 #define   UTMIP_AP_B                    (1 << 12)
360 #define   UTMIP_AN_B                    (1 << 13)
361 #define   UTMIP_HIGHZ_B         (1 << 14)
362 #define   UTMIP_USBOP_RPD_C     (1 << 16)
363 #define   UTMIP_USBON_RPD_C     (1 << 17)
364 #define   UTMIP_AP_C            (1 << 20)
365 #define   UTMIP_AN_C            (1 << 21)
366 #define   UTMIP_HIGHZ_C         (1 << 22)
367 #define   UTMIP_USBOP_RPD_D     (1 << 24)
368 #define   UTMIP_USBON_RPD_D     (1 << 25)
369 #define   UTMIP_AP_D            (1 << 28)
370 #define   UTMIP_AN_D            (1 << 29)
371 #define   UTMIP_HIGHZ_D         (1 << 30)
372
373 #define UTMIP_UHSIC_STATUS              0x214
374 #define   UTMIP_WALK_PTR_VAL(inst)      (0x3 << ((inst)*2))
375 #define   UTMIP_USBOP_VAL(inst)         (1 << ((2*(inst)) + 8))
376 #define   UTMIP_USBOP_VAL_P2            (1 << 12)
377 #define   UTMIP_USBOP_VAL_P1            (1 << 10)
378 #define   UTMIP_USBOP_VAL_P0            (1 << 8)
379 #define   UTMIP_USBON_VAL(inst)         (1 << ((2*(inst)) + 9))
380 #define   UTMIP_USBON_VAL_P2            (1 << 13)
381 #define   UTMIP_USBON_VAL_P1            (1 << 11)
382 #define   UTMIP_USBON_VAL_P0            (1 << 9)
383 #define   UTMIP_WAKE_ALARM(inst)                (1 << ((inst) + 16))
384 #define   UTMIP_WAKE_ALARM_P2   (1 << 18)
385 #define   UTMIP_WAKE_ALARM_P1   (1 << 17)
386 #define   UTMIP_WAKE_ALARM_P0   (1 << 16)
387 #define   UTMIP_WALK_PTR(inst)  (1 << ((inst)*2))
388 #define   UTMIP_WALK_PTR_P2     (1 << 4)
389 #define   UTMIP_WALK_PTR_P1     (1 << 2)
390 #define   UTMIP_WALK_PTR_P0     (1 << 0)
391
392 #define USB1_PREFETCH_ID               6
393 #define USB2_PREFETCH_ID               18
394 #define USB3_PREFETCH_ID               17
395
396 #define PMC_UTMIP_UHSIC_FAKE            0x218
397 #define   USBON_VAL(inst)       (1 << ((4*(inst))+1))
398 #define   USBON_VAL_P2                  (1 << 9)
399 #define   USBON_VAL_P1                  (1 << 5)
400 #define   USBON_VAL_P0                  (1 << 1)
401 #define   USBOP_VAL(inst)       (1 << (4*(inst)))
402 #define   USBOP_VAL_P2                  (1 << 8)
403 #define   USBOP_VAL_P1                  (1 << 4)
404 #define   USBOP_VAL_P0                  (1 << 0)
405
406 #define PMC_UTMIP_BIAS_MASTER_CNTRL 0x30c
407 #define   BIAS_MASTER_PROG_VAL          (1 << 1)
408
409 #define PMC_UTMIP_MASTER_CONFIG         0x310
410 #define   UTMIP_PWR(inst)               (1 << (inst))
411
412 #define FUSE_USB_CALIB_0                0x1F0
413 #define   FUSE_USB_CALIB_XCVR_SETUP(x)  (((x) & 0x7F) << 0)
414
415 /* These values (in milli second) are taken from the battery charging spec */
416 #define TDP_SRC_ON_MS    100
417 #define TDPSRC_CON_MS    40
418
419 #ifdef DEBUG
420 #define DBG(stuff...)   pr_info("tegra11x_usb_phy: " stuff)
421 #else
422 #define DBG(stuff...)   do {} while (0)
423 #endif
424
425 static u32 utmip_rctrl_val, utmip_tctrl_val;
426 static DEFINE_SPINLOCK(utmip_pad_lock);
427 static int utmip_pad_count;
428
429 static struct tegra_xtal_freq utmip_freq_table[] = {
430         {
431                 .freq = 12000000,
432                 .enable_delay = 0x02,
433                 .stable_count = 0x2F,
434                 .active_delay = 0x04,
435                 .xtal_freq_count = 0x76,
436                 .debounce = 0x7530,
437                 .pdtrk_count = 5,
438         },
439         {
440                 .freq = 13000000,
441                 .enable_delay = 0x02,
442                 .stable_count = 0x33,
443                 .active_delay = 0x05,
444                 .xtal_freq_count = 0x7F,
445                 .debounce = 0x7EF4,
446                 .pdtrk_count = 5,
447         },
448         {
449                 .freq = 19200000,
450                 .enable_delay = 0x03,
451                 .stable_count = 0x4B,
452                 .active_delay = 0x06,
453                 .xtal_freq_count = 0xBB,
454                 .debounce = 0xBB80,
455                 .pdtrk_count = 7,
456         },
457         {
458                 .freq = 26000000,
459                 .enable_delay = 0x04,
460                 .stable_count = 0x66,
461                 .active_delay = 0x09,
462                 .xtal_freq_count = 0xFE,
463                 .debounce = 0xFDE8,
464                 .pdtrk_count = 9,
465         },
466 };
467
468 static struct tegra_xtal_freq uhsic_freq_table[] = {
469         {
470                 .freq = 12000000,
471                 .enable_delay = 0x02,
472                 .stable_count = 0x2F,
473                 .active_delay = 0x0,
474                 .xtal_freq_count = 0x1CA,
475         },
476         {
477                 .freq = 13000000,
478                 .enable_delay = 0x02,
479                 .stable_count = 0x33,
480                 .active_delay = 0x0,
481                 .xtal_freq_count = 0x1F0,
482         },
483         {
484                 .freq = 19200000,
485                 .enable_delay = 0x03,
486                 .stable_count = 0x4B,
487                 .active_delay = 0x0,
488                 .xtal_freq_count = 0x2DD,
489         },
490         {
491                 .freq = 26000000,
492                 .enable_delay = 0x04,
493                 .stable_count = 0x66,
494                 .active_delay = 0x0,
495                 .xtal_freq_count = 0x3E0,
496         },
497 };
498
499 static int usb_phy_init(struct tegra_usb_phy *phy)
500 {
501         unsigned long val;
502         void __iomem *base = phy->regs;
503
504         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
505
506         val = readl(base + HOSTPC1_DEVLC);
507         val &= ~HOSTPC1_DEVLC_STS;
508         writel(val, base + HOSTPC1_DEVLC);
509
510         val = readl(base + USB_IF_SPARE);
511         val |= USB_HS_RSM_EOP_EN;
512         val |= USB_PORT_SUSPEND_EN;
513         writel(val, base + USB_IF_SPARE);
514
515         val = readl(base + USB_NEW_CONTROL);
516         val |= USB_COHRENCY_EN;
517         writel(val, base + USB_NEW_CONTROL);
518
519         return 0;
520 }
521
522 static void utmip_setup_pmc_wake_detect(struct tegra_usb_phy *phy)
523 {
524         unsigned long val, pmc_pad_cfg_val;
525         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
526         unsigned  int inst = phy->inst;
527         void __iomem *base = phy->regs;
528         bool port_connected;
529         enum usb_phy_port_speed port_speed;
530
531         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
532
533         /* check for port connect status */
534         val = readl(base + USB_PORTSC);
535         port_connected = val & USB_PORTSC_CCS;
536
537         if (!port_connected)
538                 return;
539
540         port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
541                 HOSTPC1_DEVLC_PSPD_MASK;
542         /*Set PMC MASTER bits to do the following
543         * a. Take over the UTMI drivers
544         * b. set up such that it will take over resume
545         *        if remote wakeup is detected
546         * Prepare PMC to take over suspend-wake detect-drive resume until USB
547         * controller ready
548         */
549
550         /* disable master enable in PMC */
551         val = readl(pmc_base + PMC_SLEEP_CFG);
552         val &= ~UTMIP_MASTER_ENABLE(inst);
553         writel(val, pmc_base + PMC_SLEEP_CFG);
554
555         /* UTMIP_PWR_PX=1 for power savings mode */
556         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
557         val |= UTMIP_PWR(inst);
558         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
559
560         /* config debouncer */
561         val = readl(pmc_base + PMC_USB_DEBOUNCE);
562         val &= ~UTMIP_LINE_DEB_CNT(~0);
563         val |= UTMIP_LINE_DEB_CNT(4);
564         writel(val, pmc_base + PMC_USB_DEBOUNCE);
565
566         /* Make sure nothing is happening on the line with respect to PMC */
567         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
568         val &= ~USBOP_VAL(inst);
569         val &= ~USBON_VAL(inst);
570         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
571
572         /* Make sure wake value for line is none */
573         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
574         val &= ~UTMIP_LINEVAL_WALK_EN(inst);
575         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
576         val = readl(pmc_base + PMC_SLEEP_CFG);
577         val &= ~UTMIP_WAKE_VAL(inst, ~0);
578         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
579         writel(val, pmc_base + PMC_SLEEP_CFG);
580
581         /* turn off pad detectors */
582         val = readl(pmc_base + PMC_USB_AO);
583         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
584         writel(val, pmc_base + PMC_USB_AO);
585
586         /* Remove fake values and make synchronizers work a bit */
587         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
588         val &= ~USBOP_VAL(inst);
589         val &= ~USBON_VAL(inst);
590         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
591
592         /* Enable which type of event can trigger a walk,
593         in this case usb_line_wake */
594         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
595         val |= UTMIP_LINEVAL_WALK_EN(inst);
596         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
597
598         /* Enable which type of event can trigger a walk,
599         * in this case usb_line_wake */
600         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
601         val |= UTMIP_LINEVAL_WALK_EN(inst);
602         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
603
604         /* Clear the walk pointers and wake alarm */
605         val = readl(pmc_base + PMC_TRIGGERS);
606         val |= UTMIP_CLR_WAKE_ALARM(inst) | UTMIP_CLR_WALK_PTR(inst);
607         writel(val, pmc_base + PMC_TRIGGERS);
608
609
610         /* Capture FS/LS pad configurations */
611         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
612         val = readl(pmc_base + PMC_TRIGGERS);
613         val |= UTMIP_CAP_CFG(inst);
614         writel(val, pmc_base + PMC_TRIGGERS);
615         udelay(1);
616         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
617
618         /* BIAS MASTER_ENABLE=0 */
619         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
620         val &= ~BIAS_MASTER_PROG_VAL;
621         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
622
623         /* program walk sequence, maintain a J, followed by a driven K
624         * to signal a resume once an wake event is detected */
625         val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
626         val &= ~UTMIP_AP_A;
627         val |= UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_AN_A |UTMIP_HIGHZ_A |
628                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_AP_B | UTMIP_AN_B |
629                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_AP_C | UTMIP_AN_C |
630                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_AP_D | UTMIP_AN_D;
631         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
632
633         if (port_speed == USB_PHY_PORT_SPEED_LOW) {
634                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
635                 val &= ~(UTMIP_AN_B | UTMIP_HIGHZ_B | UTMIP_AN_C |
636                         UTMIP_HIGHZ_C | UTMIP_AN_D | UTMIP_HIGHZ_D);
637                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
638         } else {
639                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
640                 val &= ~(UTMIP_AP_B | UTMIP_HIGHZ_B | UTMIP_AP_C |
641                         UTMIP_HIGHZ_C | UTMIP_AP_D | UTMIP_HIGHZ_D);
642                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
643         }
644
645         /* turn on pad detectors */
646         val = readl(pmc_base + PMC_USB_AO);
647         val &= ~(USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
648         writel(val, pmc_base + PMC_USB_AO);
649
650         /* Add small delay before usb detectors provide stable line values */
651         mdelay(1);
652
653         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
654         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
655         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
656         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
657
658         phy->remote_wakeup = false;
659
660         /* Turn over pad configuration to PMC  for line wake events*/
661         val = readl(pmc_base + PMC_SLEEP_CFG);
662         val &= ~UTMIP_WAKE_VAL(inst, ~0);
663         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_ANY);
664         val |= UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst);
665         val |= UTMIP_MASTER_ENABLE(inst) | UTMIP_FSLS_USE_PMC(inst);
666         writel(val, pmc_base + PMC_SLEEP_CFG);
667
668         val = readl(base + UTMIP_PMC_WAKEUP0);
669         val |= EVENT_INT_ENB;
670         writel(val, base + UTMIP_PMC_WAKEUP0);
671 }
672
673 static void utmip_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy)
674 {
675         unsigned long val;
676         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
677         unsigned  int inst = phy->inst;
678         void __iomem *base = phy->regs;
679
680         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
681
682         val = readl(pmc_base + PMC_SLEEP_CFG);
683         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
684         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
685         writel(val, pmc_base + PMC_SLEEP_CFG);
686
687         val = readl(pmc_base + PMC_TRIGGERS);
688         val |= UTMIP_CLR_WAKE_ALARM(inst) | UTMIP_CLR_WALK_PTR(inst);
689         writel(val, pmc_base + PMC_TRIGGERS);
690
691         val = readl(base + UTMIP_PMC_WAKEUP0);
692         val &= ~EVENT_INT_ENB;
693         writel(val, base + UTMIP_PMC_WAKEUP0);
694
695         /* Disable PMC master mode by clearing MASTER_EN */
696         val = readl(pmc_base + PMC_SLEEP_CFG);
697         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
698                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
699         writel(val, pmc_base + PMC_SLEEP_CFG);
700
701         val = readl(pmc_base + PMC_TRIGGERS);
702         val &= ~UTMIP_CAP_CFG(inst);
703         writel(val, pmc_base + PMC_TRIGGERS);
704
705         /* turn off pad detectors */
706         val = readl(pmc_base + PMC_USB_AO);
707         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
708         writel(val, pmc_base + PMC_USB_AO);
709
710         phy->remote_wakeup = false;
711 }
712
713 static bool utmi_phy_remotewake_detected(struct tegra_usb_phy *phy)
714 {
715         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
716         void __iomem *base = phy->regs;
717         unsigned  int inst = phy->inst;
718         u32 val;
719
720         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
721         val = readl(base + UTMIP_PMC_WAKEUP0);
722         if (val & EVENT_INT_ENB) {
723                 val = readl(pmc_base + UTMIP_UHSIC_STATUS);
724                 if (UTMIP_WAKE_ALARM(inst) & val) {
725                         val = readl(pmc_base + PMC_SLEEP_CFG);
726                         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
727                         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
728                         writel(val, pmc_base + PMC_SLEEP_CFG);
729
730                         val = readl(pmc_base + PMC_TRIGGERS);
731                         val |= UTMIP_CLR_WAKE_ALARM(inst) |
732                                 UTMIP_CLR_WALK_PTR(inst);
733                         writel(val, pmc_base + PMC_TRIGGERS);
734
735                         val = readl(base + UTMIP_PMC_WAKEUP0);
736                         val &= ~EVENT_INT_ENB;
737                         writel(val, base + UTMIP_PMC_WAKEUP0);
738                         phy->remote_wakeup = true;
739                         return true;
740                 }
741         }
742         return false;
743 }
744
745 static void utmi_phy_enable_trking_data(struct tegra_usb_phy *phy)
746 {
747         void __iomem *base = IO_ADDRESS(TEGRA_USB_BASE);
748         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
749         static bool init_done = false;
750         u32 val;
751
752         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
753
754         /* Should be done only once after system boot */
755         if (init_done)
756                 return;
757
758         clk_enable(phy->utmi_pad_clk);
759         /* Bias pad MASTER_ENABLE=1 */
760         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
761         val |= BIAS_MASTER_PROG_VAL;
762         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
763
764         /* Setting the tracking length time */
765         val = readl(base + UTMIP_BIAS_CFG1);
766         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
767         val |= UTMIP_BIAS_PDTRK_COUNT(5);
768         writel(val, base + UTMIP_BIAS_CFG1);
769
770         /* Bias PDTRK is Shared and MUST be done from USB1 ONLY, PD_TRK=0 */
771         val = readl(base + UTMIP_BIAS_CFG1);
772         val &= ~UTMIP_BIAS_PDTRK_POWERDOWN;
773         writel(val, base + UTMIP_BIAS_CFG1);
774
775         val = readl(base + UTMIP_BIAS_CFG1);
776         val |= UTMIP_BIAS_PDTRK_POWERUP;
777         writel(val, base + UTMIP_BIAS_CFG1);
778
779         /* Wait for 25usec */
780         udelay(25);
781
782         /* Bias pad MASTER_ENABLE=0 */
783         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
784         val &= ~BIAS_MASTER_PROG_VAL;
785         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
786
787         /* Wait for 1usec */
788         udelay(1);
789
790         /* Bias pad MASTER_ENABLE=1 */
791         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
792         val |= BIAS_MASTER_PROG_VAL;
793         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
794
795         /* Read RCTRL and TCTRL from UTMIP space */
796         val = readl(base + UTMIP_BIAS_STS0);
797         utmip_rctrl_val = ffz(UTMIP_RCTRL_VAL(val));
798         utmip_tctrl_val = ffz(UTMIP_TCTRL_VAL(val));
799
800         /* PD_TRK=1 */
801         val = readl(base + UTMIP_BIAS_CFG1);
802         val |= UTMIP_BIAS_PDTRK_POWERDOWN;
803         writel(val, base + UTMIP_BIAS_CFG1);
804
805         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
806         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
807         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
808         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
809         clk_disable(phy->utmi_pad_clk);
810         init_done = true;
811 }
812
813 static void utmip_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy)
814 {
815         unsigned long val;
816         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
817         unsigned  int inst = phy->inst;
818
819         /* power down UTMIP interfaces */
820         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
821         val |= UTMIP_PWR(inst);
822         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
823
824         /* setup sleep walk usb controller */
825         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
826                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
827                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
828                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
829         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
830
831         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
832         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
833         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
834         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
835
836         /* Turn over pad configuration to PMC */
837         val = readl(pmc_base + PMC_SLEEP_CFG);
838         val &= ~UTMIP_WAKE_VAL(inst, ~0);
839         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE) |
840                 UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
841                 UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst);
842         writel(val, pmc_base + PMC_SLEEP_CFG);
843 }
844
845 static void utmip_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
846 {
847         unsigned long val;
848         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
849         unsigned  int inst = phy->inst;
850
851         /* Disable PMC master mode by clearing MASTER_EN */
852         val = readl(pmc_base + PMC_SLEEP_CFG);
853         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
854                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
855         writel(val, pmc_base + PMC_SLEEP_CFG);
856         mdelay(1);
857 }
858
859 #if 0
860 static int uhsic_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy)
861 {
862         unsigned long val;
863         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
864
865         /* turn on pad detectors for HSIC*/
866         val = readl(pmc_base + PMC_USB_AO);
867         val |= (HSIC_RESERVED_P0 | HSIC_STOBE_VAL_PD_P0 | HSIC_DATA_VAL_PD_P0);
868         writel(val, pmc_base + PMC_USB_AO);
869
870         /* enable pull downs on HSIC PMC */
871         val = UHSIC_STRB_RPD_A | UHSIC_DATA_RPD_A | UHSIC_STRB_RPD_B |
872                 UHSIC_DATA_RPD_B | UHSIC_STRB_RPD_C | UHSIC_DATA_RPD_C |
873                 UHSIC_STRB_RPD_D | UHSIC_DATA_RPD_D;
874         writel(val, pmc_base + UHSIC_SLEEPWALK_REG);
875
876         /* Turn over pad configuration to PMC */
877         val = readl(pmc_base + PMC_SLEEP_CFG);
878         val &= ~UHSIC_WAKE_VAL_P0(~0);
879         val |= UHSIC_WAKE_VAL_P0(WAKE_VAL_NONE) | UHSIC_MASTER_ENABLE_P0;
880         writel(val, pmc_base + PMC_SLEEP_CFG);
881
882         return 0;
883 }
884
885 static void usb_phy_power_down_pmc(void)
886 {
887         unsigned long val;
888         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
889
890         /* power down all 3 UTMIP interfaces */
891         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
892         val |= UTMIP_PWR(0) | UTMIP_PWR(1) | UTMIP_PWR(2);
893         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
894
895         /* turn on pad detectors */
896         writel(PMC_POWER_DOWN_MASK, pmc_base + PMC_USB_AO);
897
898         /* setup sleep walk fl all 3 usb controllers */
899         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
900                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
901                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
902                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
903         writel(val, pmc_base + PMC_SLEEPWALK_REG(0));
904         writel(val, pmc_base + PMC_SLEEPWALK_REG(1));
905         writel(val, pmc_base + PMC_SLEEPWALK_REG(2));
906
907         /* enable pull downs on HSIC PMC */
908         val = UHSIC_STRB_RPD_A | UHSIC_DATA_RPD_A | UHSIC_STRB_RPD_B |
909                 UHSIC_DATA_RPD_B | UHSIC_STRB_RPD_C | UHSIC_DATA_RPD_C |
910                 UHSIC_STRB_RPD_D | UHSIC_DATA_RPD_D;
911         writel(val, pmc_base + UHSIC_SLEEPWALK_REG);
912
913         /* Turn over pad configuration to PMC */
914         val = readl(pmc_base + PMC_SLEEP_CFG);
915         val &= ~UTMIP_WAKE_VAL(0, ~0);
916         val &= ~UTMIP_WAKE_VAL(1, ~0);
917         val &= ~UTMIP_WAKE_VAL(2, ~0);
918         val &= ~UHSIC_WAKE_VAL_P0(~0);
919         val |= UTMIP_WAKE_VAL(0, WAKE_VAL_NONE) | UHSIC_WAKE_VAL_P0(WAKE_VAL_NONE) |
920         UTMIP_WAKE_VAL(1, WAKE_VAL_NONE) | UTMIP_WAKE_VAL(2, WAKE_VAL_NONE) |
921         UTMIP_RCTRL_USE_PMC(0) | UTMIP_RCTRL_USE_PMC(1) | UTMIP_RCTRL_USE_PMC(2) |
922         UTMIP_TCTRL_USE_PMC(0) | UTMIP_TCTRL_USE_PMC(1) | UTMIP_TCTRL_USE_PMC(2) |
923         UTMIP_FSLS_USE_PMC(0) | UTMIP_FSLS_USE_PMC(1) | UTMIP_FSLS_USE_PMC(2) |
924         UTMIP_MASTER_ENABLE(0) | UTMIP_MASTER_ENABLE(1) | UTMIP_MASTER_ENABLE(2) |
925         UHSIC_MASTER_ENABLE_P0;
926         writel(val, pmc_base + PMC_SLEEP_CFG);
927 }
928 #endif
929
930 static void uhsic_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
931 {
932         unsigned long val;
933         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
934
935         /* turn on pad detectors for HSIC*/
936         val = readl(pmc_base + PMC_USB_AO);
937         val &= ~(HSIC_RESERVED_P0 | HSIC_STOBE_VAL_PD_P0 | HSIC_DATA_VAL_PD_P0);
938         writel(val, pmc_base + PMC_USB_AO);
939
940         /* Disable PMC master mode by clearing MASTER_EN */
941         val = readl(pmc_base + PMC_SLEEP_CFG);
942         val &= ~(UHSIC_MASTER_ENABLE_P0);
943         writel(val, pmc_base + PMC_SLEEP_CFG);
944         mdelay(1);
945 }
946
947 static int usb_phy_bringup_host_controller(struct tegra_usb_phy *phy)
948 {
949         unsigned long val;
950         void __iomem *base = phy->regs;
951
952         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
953         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n",
954                 readl(base + USB_USBSTS), readl(base + USB_PORTSC),
955                                                         phy->port_speed);
956
957         /* Enable Port Power */
958         val = readl(base + USB_PORTSC);
959         val |= USB_PORTSC_PP;
960         writel(val, base + USB_PORTSC);
961         udelay(10);
962
963         /* Check if the phy resume from LP0. When the phy resume from LP0
964          * USB register will be reset.to zero */
965         if (!readl(base + USB_ASYNCLISTADDR)) {
966                 /* Program the field PTC based on the saved speed mode */
967                 val = readl(base + USB_PORTSC);
968                 val &= ~USB_PORTSC_PTC(~0);
969                 if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH)
970                         val |= USB_PORTSC_PTC(5);
971                 else if (phy->port_speed == USB_PHY_PORT_SPEED_FULL)
972                         val |= USB_PORTSC_PTC(6);
973                 else if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
974                         val |= USB_PORTSC_PTC(7);
975                 writel(val, base + USB_PORTSC);
976                 udelay(10);
977
978                 /* Disable test mode by setting PTC field to NORMAL_OP */
979                 val = readl(base + USB_PORTSC);
980                 val &= ~USB_PORTSC_PTC(~0);
981                 writel(val, base + USB_PORTSC);
982                 udelay(10);
983         }
984
985         /* Poll until CCS is enabled */
986         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
987                                                  USB_PORTSC_CCS, 2000)) {
988                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
989         }
990
991         /* Poll until PE is enabled */
992         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_PE,
993                                                  USB_PORTSC_PE, 2000)) {
994                 pr_err("%s: timeout waiting for USB_PORTSC_PE\n", __func__);
995         }
996
997         /* Clear the PCI status, to avoid an interrupt taken upon resume */
998         val = readl(base + USB_USBSTS);
999         val |= USB_USBSTS_PCI;
1000         writel(val, base + USB_USBSTS);
1001
1002         /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
1003         val = readl(base + USB_PORTSC);
1004         if ((val & USB_PORTSC_PP) && (val & USB_PORTSC_PE)) {
1005                 val |= USB_PORTSC_SUSP;
1006                 writel(val, base + USB_PORTSC);
1007                 /* Need a 4ms delay before the controller goes to suspend */
1008                 mdelay(4);
1009
1010                 /* Wait until port suspend completes */
1011                 if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_SUSP,
1012                                                  USB_PORTSC_SUSP, 1000)) {
1013                         pr_err("%s: timeout waiting for PORT_SUSPEND\n",
1014                                                                 __func__);
1015                 }
1016         }
1017
1018         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1019                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1020         return 0;
1021 }
1022
1023 static void usb_phy_wait_for_sof(struct tegra_usb_phy *phy)
1024 {
1025         unsigned long val;
1026         void __iomem *base = phy->regs;
1027
1028         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1029
1030         val = readl(base + USB_USBSTS);
1031         writel(val, base + USB_USBSTS);
1032         udelay(20);
1033         /* wait for two SOFs */
1034         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1035                 USB_USBSTS_SRI, 2500))
1036                 pr_err("%s: timeout waiting for SOF\n", __func__);
1037
1038         val = readl(base + USB_USBSTS);
1039         writel(val, base + USB_USBSTS);
1040         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI, 0, 2500))
1041                 pr_err("%s: timeout waiting for SOF\n", __func__);
1042
1043         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1044                         USB_USBSTS_SRI, 2500))
1045                 pr_err("%s: timeout waiting for SOF\n", __func__);
1046
1047         udelay(20);
1048 }
1049
1050 static unsigned int utmi_phy_xcvr_setup_value(struct tegra_usb_phy *phy)
1051 {
1052         struct tegra_utmi_config *cfg = &phy->pdata->u_cfg.utmi;
1053         signed long val;
1054
1055         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1056
1057         if (cfg->xcvr_use_fuses) {
1058                 val = FUSE_USB_CALIB_XCVR_SETUP(
1059                                 tegra_fuse_readl(FUSE_USB_CALIB_0));
1060                 if (cfg->xcvr_setup_offset <= UTMIP_XCVR_MAX_OFFSET)
1061                         val = val + cfg->xcvr_setup_offset;
1062
1063                 if (val > UTMIP_XCVR_SETUP_MAX_VALUE) {
1064                         val = UTMIP_XCVR_SETUP_MAX_VALUE;
1065                         pr_info("%s: reset XCVR_SETUP to max value\n",
1066                                  __func__);
1067                 } else if (val < UTMIP_XCVR_SETUP_MIN_VALUE) {
1068                         val = UTMIP_XCVR_SETUP_MIN_VALUE;
1069                         pr_info("%s: reset XCVR_SETUP to min value\n",
1070                                  __func__);
1071                 }
1072         } else {
1073                 val = cfg->xcvr_setup;
1074         }
1075
1076         return (unsigned int) val;
1077 }
1078
1079 static int utmi_phy_open(struct tegra_usb_phy *phy)
1080 {
1081         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1082         unsigned long parent_rate, val;
1083         int i;
1084
1085         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1086
1087         phy->utmi_pad_clk = clk_get_sys("utmip-pad", NULL);
1088         if (IS_ERR(phy->utmi_pad_clk)) {
1089                 pr_err("%s: can't get utmip pad clock\n", __func__);
1090                 return PTR_ERR(phy->utmi_pad_clk);
1091         }
1092
1093         phy->utmi_xcvr_setup = utmi_phy_xcvr_setup_value(phy);
1094
1095         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
1096         for (i = 0; i < ARRAY_SIZE(utmip_freq_table); i++) {
1097                 if (utmip_freq_table[i].freq == parent_rate) {
1098                         phy->freq = &utmip_freq_table[i];
1099                         break;
1100                 }
1101         }
1102         if (!phy->freq) {
1103                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
1104                 return -EINVAL;
1105         }
1106
1107         /* Power-up the VBUS detector for UTMIP PHY */
1108         val = readl(pmc_base + PMC_USB_AO);
1109         val &= ~(PMC_USB_AO_VBUS_WAKEUP_PD_P0 | PMC_USB_AO_ID_PD_P0);
1110         writel((val | PMC_USB_AO_PD_P2), (pmc_base + PMC_USB_AO));
1111
1112         utmip_powerup_pmc_wake_detect(phy);
1113
1114         return 0;
1115 }
1116
1117 static void utmi_phy_close(struct tegra_usb_phy *phy)
1118 {
1119         unsigned long val;
1120         void __iomem *base = phy->regs;
1121
1122         DBG("%s inst:[%d]\n", __func__, phy->inst);
1123
1124         /* Disable PHY clock valid interrupts while going into suspend*/
1125         if (phy->pdata->u_data.host.hot_plug) {
1126                 val = readl(base + USB_SUSP_CTRL);
1127                 val &= ~USB_PHY_CLK_VALID_INT_ENB;
1128                 writel(val, base + USB_SUSP_CTRL);
1129         }
1130
1131         val = readl(base + USB_PORTSC);
1132         val |= USB_PORTSC_WKCN;
1133         writel(val, base + USB_PORTSC);
1134
1135         clk_put(phy->utmi_pad_clk);
1136 }
1137
1138 static int utmi_phy_pad_power_on(struct tegra_usb_phy *phy)
1139 {
1140         unsigned long val, flags;
1141         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1142
1143         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1144
1145         clk_enable(phy->utmi_pad_clk);
1146
1147         spin_lock_irqsave(&utmip_pad_lock, flags);
1148         utmip_pad_count++;
1149
1150         val = readl(pad_base + UTMIP_BIAS_CFG0);
1151         val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
1152         val |= UTMIP_HSSQUELCH_LEVEL(0x2) | UTMIP_HSDISCON_LEVEL(0x1) |
1153                 UTMIP_HSDISCON_LEVEL_MSB;
1154         writel(val, pad_base + UTMIP_BIAS_CFG0);
1155
1156         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1157
1158         clk_disable(phy->utmi_pad_clk);
1159
1160         return 0;
1161 }
1162
1163 static int utmi_phy_pad_power_off(struct tegra_usb_phy *phy)
1164 {
1165         unsigned long val, flags;
1166         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1167
1168         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1169
1170         clk_enable(phy->utmi_pad_clk);
1171         spin_lock_irqsave(&utmip_pad_lock, flags);
1172
1173         if (!utmip_pad_count) {
1174                 pr_err("%s: utmip pad already powered off\n", __func__);
1175                 goto out;
1176         }
1177         if (--utmip_pad_count == 0) {
1178                 val = readl(pad_base + UTMIP_BIAS_CFG0);
1179                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
1180                 val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) | UTMIP_HSDISCON_LEVEL(~0) |
1181                         UTMIP_HSDISCON_LEVEL_MSB);
1182                 writel(val, pad_base + UTMIP_BIAS_CFG0);
1183         }
1184 out:
1185         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1186         clk_disable(phy->utmi_pad_clk);
1187
1188         return 0;
1189 }
1190
1191 static int utmi_phy_irq(struct tegra_usb_phy *phy)
1192 {
1193         void __iomem *base = phy->regs;
1194         unsigned long val = 0;
1195
1196         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1197         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1198                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1199         DBG("USB_USBMODE[0x%x] USB_USBCMD[0x%x]\n",
1200                         readl(base + USB_USBMODE), readl(base + USB_USBCMD));
1201
1202         /* check if there is any remote wake event */
1203         if (utmi_phy_remotewake_detected(phy))
1204                 pr_info("%s: utmip remote wake detected\n", __func__);
1205
1206         if (phy->pdata->u_data.host.hot_plug) {
1207                 val = readl(base + USB_SUSP_CTRL);
1208                 if ((val  & USB_PHY_CLK_VALID_INT_STS)) {
1209                         val &= ~USB_PHY_CLK_VALID_INT_ENB |
1210                                         USB_PHY_CLK_VALID_INT_STS;
1211                         writel(val , (base + USB_SUSP_CTRL));
1212                         pr_info("%s: usb device plugged-in\n", __func__);
1213                         val = readl(base + USB_USBSTS);
1214                         if (!(val  & USB_USBSTS_PCI))
1215                                 return IRQ_NONE;
1216                         val = readl(base + USB_PORTSC);
1217                         val &= ~(USB_PORTSC_WKCN | USB_PORTSC_RWC_BITS);
1218                         writel(val , (base + USB_PORTSC));
1219                 }
1220         }
1221
1222         return IRQ_HANDLED;
1223 }
1224
1225 static int utmi_phy_post_resume(struct tegra_usb_phy *phy)
1226 {
1227         unsigned long val;
1228         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1229         unsigned  int inst = phy->inst;
1230
1231         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1232         val = readl(pmc_base + PMC_SLEEP_CFG);
1233         /* if PMC is not disabled by now then disable it */
1234         if (val & UTMIP_MASTER_ENABLE(inst)) {
1235                 utmip_phy_disable_pmc_bus_ctrl(phy);
1236         }
1237
1238         return 0;
1239 }
1240
1241 static int utmi_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1242 {
1243         unsigned long val;
1244         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1245         unsigned  int inst = phy->inst;
1246
1247         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1248         val = readl(pmc_base + PMC_SLEEP_CFG);
1249         if (val & UTMIP_MASTER_ENABLE(inst)) {
1250                 if (!remote_wakeup)
1251                         utmip_phy_disable_pmc_bus_ctrl(phy);
1252         }
1253
1254         return 0;
1255 }
1256
1257 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
1258 {
1259         unsigned long val;
1260         void __iomem *base = phy->regs;
1261
1262         DBG("%s(%d) inst:[%d] BEGIN\n", __func__, __LINE__, phy->inst);
1263         if (!phy->phy_clk_on) {
1264                 DBG("%s(%d) inst:[%d] phy clk is already off\n",
1265                                         __func__, __LINE__, phy->inst);
1266                 return 0;
1267         }
1268
1269         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1270                 utmip_powerdown_pmc_wake_detect(phy);
1271
1272                 val = readl(base + USB_SUSP_CTRL);
1273                 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
1274                 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
1275                 writel(val, base + USB_SUSP_CTRL);
1276
1277                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1278                 val |= UTMIP_PD_CHRG;
1279                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1280         } else {
1281                 utmip_setup_pmc_wake_detect(phy);
1282         }
1283
1284         if (!phy->pdata->u_data.host.hot_plug) {
1285                 val = readl(base + UTMIP_XCVR_CFG0);
1286                 val |= (UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
1287                          UTMIP_FORCE_PDZI_POWERDOWN);
1288                 writel(val, base + UTMIP_XCVR_CFG0);
1289         }
1290
1291         val = readl(base + UTMIP_XCVR_CFG1);
1292         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1293                    UTMIP_FORCE_PDDR_POWERDOWN;
1294         writel(val, base + UTMIP_XCVR_CFG1);
1295
1296         val = readl(base + UTMIP_BIAS_CFG1);
1297         val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
1298         writel(val, base + UTMIP_BIAS_CFG1);
1299
1300         utmi_phy_pad_power_off(phy);
1301
1302         phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
1303                         HOSTPC1_DEVLC_PSPD_MASK;
1304
1305         if (phy->pdata->u_data.host.hot_plug) {
1306                 bool enable_hotplug = true;
1307                 /* if it is OTG port then make sure to enable hot-plug feature
1308                    only if host adaptor is connected, i.e id is low */
1309                 if (phy->pdata->port_otg) {
1310                         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1311                         enable_hotplug = (val & USB_ID_STATUS) ? false : true;
1312                 }
1313                 if (enable_hotplug) {
1314                         val = readl(base + USB_PORTSC);
1315                         val |= USB_PORTSC_WKCN;
1316                         writel(val, base + USB_PORTSC);
1317
1318                         val = readl(base + USB_SUSP_CTRL);
1319                         val |= USB_PHY_CLK_VALID_INT_ENB;
1320                         writel(val, base + USB_SUSP_CTRL);
1321                 } else {
1322                         /* Disable PHY clock valid interrupts while going into suspend*/
1323                         val = readl(base + USB_SUSP_CTRL);
1324                         val &= ~USB_PHY_CLK_VALID_INT_ENB;
1325                         writel(val, base + USB_SUSP_CTRL);
1326                 }
1327         }
1328
1329         if (phy->inst == 0) {
1330                         val = readl(base + USB_SUSP_CTRL);
1331                         val |= UTMIP_RESET;
1332                         writel(val, base + USB_SUSP_CTRL);
1333         }
1334
1335         val = readl(base + HOSTPC1_DEVLC);
1336         val |= HOSTPC1_DEVLC_PHCD;
1337         writel(val, base + HOSTPC1_DEVLC);
1338
1339         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
1340                                                                 0, 2500))
1341                 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
1342
1343         phy->phy_clk_on = false;
1344         phy->hw_accessible = false;
1345
1346         DBG("%s(%d) inst:[%d] END\n", __func__, __LINE__, phy->inst);
1347
1348         return 0;
1349 }
1350
1351
1352 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
1353 {
1354         unsigned long val;
1355         void __iomem *base = phy->regs;
1356         struct tegra_utmi_config *config = &phy->pdata->u_cfg.utmi;
1357
1358         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1359         if (phy->phy_clk_on) {
1360                 DBG("%s(%d) inst:[%d] phy clk is already On\n",
1361                                         __func__, __LINE__, phy->inst);
1362                 return 0;
1363         }
1364         val = readl(base + USB_SUSP_CTRL);
1365         val |= UTMIP_RESET;
1366         writel(val, base + USB_SUSP_CTRL);
1367
1368         val = readl(base + UTMIP_TX_CFG0);
1369         val |= UTMIP_FS_PREABMLE_J;
1370         writel(val, base + UTMIP_TX_CFG0);
1371
1372         val = readl(base + UTMIP_HSRX_CFG0);
1373         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
1374         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
1375         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
1376         writel(val, base + UTMIP_HSRX_CFG0);
1377
1378         val = readl(base + UTMIP_HSRX_CFG1);
1379         val &= ~UTMIP_HS_SYNC_START_DLY(~0);
1380         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
1381         writel(val, base + UTMIP_HSRX_CFG1);
1382
1383         val = readl(base + UTMIP_DEBOUNCE_CFG0);
1384         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
1385         val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
1386         writel(val, base + UTMIP_DEBOUNCE_CFG0);
1387
1388         val = readl(base + UTMIP_MISC_CFG0);
1389         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
1390         writel(val, base + UTMIP_MISC_CFG0);
1391
1392         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1393                 val = readl(base + USB_SUSP_CTRL);
1394                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
1395                 writel(val, base + USB_SUSP_CTRL);
1396
1397                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1398                 val &= ~UTMIP_PD_CHRG;
1399                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1400         } else {
1401                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1402                 val |= UTMIP_PD_CHRG;
1403                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1404         }
1405
1406         utmi_phy_pad_power_on(phy);
1407
1408         val = readl(base + UTMIP_XCVR_CFG0);
1409         val &= ~(UTMIP_XCVR_LSBIAS_SEL | UTMIP_FORCE_PD_POWERDOWN |
1410                  UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN |
1411                  UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_LSFSLEW(~0) |
1412                  UTMIP_XCVR_LSRSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
1413         val |= UTMIP_XCVR_SETUP(phy->utmi_xcvr_setup);
1414         val |= UTMIP_XCVR_SETUP_MSB(XCVR_SETUP_MSB_CALIB(phy->utmi_xcvr_setup));
1415         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
1416         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
1417         val |= UTMIP_XCVR_HSSLEW_MSB(0x8);
1418         writel(val, base + UTMIP_XCVR_CFG0);
1419
1420         val = readl(base + UTMIP_XCVR_CFG1);
1421         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1422                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
1423         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
1424         writel(val, base + UTMIP_XCVR_CFG1);
1425
1426         val = readl(base + UTMIP_BIAS_CFG1);
1427         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
1428         val |= UTMIP_BIAS_PDTRK_COUNT(phy->freq->pdtrk_count);
1429         writel(val, base + UTMIP_BIAS_CFG1);
1430
1431         val = readl(base + UTMIP_SPARE_CFG0);
1432         val &= ~FUSE_SETUP_SEL;
1433         val |= FUSE_ATERM_SEL;
1434         writel(val, base + UTMIP_SPARE_CFG0);
1435
1436         val = readl(base + USB_SUSP_CTRL);
1437         val |= UTMIP_PHY_ENABLE;
1438         writel(val, base + USB_SUSP_CTRL);
1439
1440         val = readl(base + USB_SUSP_CTRL);
1441         val &= ~UTMIP_RESET;
1442         writel(val, base + USB_SUSP_CTRL);
1443
1444         val = readl(base + HOSTPC1_DEVLC);
1445         val &= ~HOSTPC1_DEVLC_PHCD;
1446         writel(val, base + HOSTPC1_DEVLC);
1447
1448         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1449                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500))
1450                 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
1451
1452         utmi_phy_enable_trking_data(phy);
1453
1454         if (phy->inst == 2)
1455                 writel(0, base + ICUSB_CTRL);
1456
1457         val = readl(base + USB_USBMODE);
1458         val &= ~USB_USBMODE_MASK;
1459         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST)
1460                 val |= USB_USBMODE_HOST;
1461         else
1462                 val |= USB_USBMODE_DEVICE;
1463         writel(val, base + USB_USBMODE);
1464
1465         val = readl(base + HOSTPC1_DEVLC);
1466         val &= ~HOSTPC1_DEVLC_PTS(~0);
1467         val |= HOSTPC1_DEVLC_STS;
1468         writel(val, base + HOSTPC1_DEVLC);
1469
1470         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE)
1471                 utmip_powerup_pmc_wake_detect(phy);
1472         phy->phy_clk_on = true;
1473         phy->hw_accessible = true;
1474         DBG("%s(%d) End\n", __func__, __LINE__);
1475
1476         return 0;
1477 }
1478
1479 static void utmi_phy_restore_start(struct tegra_usb_phy *phy)
1480 {
1481         unsigned long val;
1482         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1483         int inst = phy->inst;
1484
1485         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1486         val = readl(pmc_base + UTMIP_UHSIC_STATUS);
1487         /* check whether we wake up from the remote resume */
1488         if (UTMIP_WALK_PTR_VAL(inst) & val) {
1489                 phy->remote_wakeup = true;
1490         } else {
1491                 if (!((UTMIP_USBON_VAL(phy->inst) |
1492                         UTMIP_USBOP_VAL(phy->inst)) & val)) {
1493                                 utmip_phy_disable_pmc_bus_ctrl(phy);
1494                 }
1495         }
1496 }
1497
1498 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
1499 {
1500         unsigned long val;
1501         void __iomem *base = phy->regs;
1502         int wait_time_us = 3000; /* FPR should be set by this time */
1503
1504         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1505         /* check whether we wake up from the remote resume */
1506         if (phy->remote_wakeup) {
1507                 /* wait until FPR bit is set automatically on remote resume */
1508                 do {
1509                         val = readl(base + USB_PORTSC);
1510                         udelay(1);
1511                         if (wait_time_us == 0)
1512                                 return;
1513                         wait_time_us--;
1514                 } while (!(val & USB_PORTSC_RESUME));
1515                 /* wait for 25 ms to port resume complete */
1516                 msleep(25);
1517                 /* disable PMC master control */
1518                 utmip_phy_disable_pmc_bus_ctrl(phy);
1519
1520                 /* Clear PCI and SRI bits to avoid an interrupt upon resume */
1521                 val = readl(base + USB_USBSTS);
1522                 writel(val, base + USB_USBSTS);
1523                 /* wait to avoid SOF if there is any */
1524                 if (usb_phy_reg_status_wait(base + USB_USBSTS,
1525                         USB_USBSTS_SRI, USB_USBSTS_SRI, 2500) < 0) {
1526                         pr_err("%s: timeout waiting for SOF\n", __func__);
1527                 }
1528                 utmi_phy_post_resume(phy);
1529         }
1530 }
1531
1532 static int utmi_phy_resume(struct tegra_usb_phy *phy)
1533 {
1534         int status = 0;
1535         unsigned long val;
1536         void __iomem *base = phy->regs;
1537
1538         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1539         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) {
1540                 if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
1541                         utmi_phy_restore_start(phy);
1542                         usb_phy_bringup_host_controller(phy);
1543                         utmi_phy_restore_end(phy);
1544                 } else {
1545                         /* device is plugged in when system is in LP0 */
1546                         /* bring up the controller from LP0*/
1547                         val = readl(base + USB_USBCMD);
1548                         val |= USB_CMD_RESET;
1549                         writel(val, base + USB_USBCMD);
1550
1551                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1552                                 USB_CMD_RESET, 0, 2500) < 0) {
1553                                 pr_err("%s: timeout waiting for reset\n", __func__);
1554                         }
1555
1556                         val = readl(base + USB_USBMODE);
1557                         val &= ~USB_USBMODE_MASK;
1558                         val |= USB_USBMODE_HOST;
1559                         writel(val, base + USB_USBMODE);
1560
1561                         val = readl(base + HOSTPC1_DEVLC);
1562                         val &= ~HOSTPC1_DEVLC_PTS(~0);
1563                         val |= HOSTPC1_DEVLC_STS;
1564                         writel(val, base + HOSTPC1_DEVLC);
1565
1566                         writel(USB_USBCMD_RS, base + USB_USBCMD);
1567
1568                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1569                                 USB_USBCMD_RS, USB_USBCMD_RS, 2500) < 0) {
1570                                 pr_err("%s: timeout waiting for run bit\n", __func__);
1571                         }
1572
1573                         /* Enable Port Power */
1574                         val = readl(base + USB_PORTSC);
1575                         val |= USB_PORTSC_PP;
1576                         writel(val, base + USB_PORTSC);
1577                         udelay(10);
1578
1579                         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1580                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1581                 }
1582         }
1583
1584         return status;
1585 }
1586
1587 static bool utmi_phy_charger_detect(struct tegra_usb_phy *phy)
1588 {
1589         unsigned long val;
1590         void __iomem *base = phy->regs;
1591         bool status;
1592
1593         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1594         if (phy->pdata->op_mode != TEGRA_USB_OPMODE_DEVICE) {
1595                 /* Charger detection is not there for ULPI
1596                  * return Charger not available */
1597                 return false;
1598         }
1599
1600         /* Enable charger detection logic */
1601         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1602         val |= UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN;
1603         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1604
1605         /* Source should be on for 100 ms as per USB charging spec */
1606         msleep(TDP_SRC_ON_MS);
1607
1608         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1609         /* If charger is not connected disable the interrupt */
1610         val &= ~VDAT_DET_INT_EN;
1611         val |= VDAT_DET_CHG_DET;
1612         writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
1613
1614         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1615         if (val & VDAT_DET_STS)
1616                 status = true;
1617         else
1618                 status = false;
1619
1620         /* Disable charger detection logic */
1621         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1622         val &= ~(UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN);
1623         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1624
1625         /* Delay of 40 ms before we pull the D+ as per battery charger spec */
1626         msleep(TDPSRC_CON_MS);
1627
1628         return status;
1629 }
1630
1631 static int uhsic_phy_open(struct tegra_usb_phy *phy)
1632 {
1633         unsigned long parent_rate;
1634         int i;
1635
1636         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1637         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
1638         for (i = 0; i < ARRAY_SIZE(uhsic_freq_table); i++) {
1639                 if (uhsic_freq_table[i].freq == parent_rate) {
1640                         phy->freq = &uhsic_freq_table[i];
1641                         break;
1642                 }
1643         }
1644         if (!phy->freq) {
1645                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
1646                 return -EINVAL;
1647         }
1648
1649         uhsic_powerup_pmc_wake_detect(phy);
1650
1651         return 0;
1652 }
1653
1654 static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
1655 {
1656         unsigned long val;
1657         void __iomem *base = phy->regs;
1658         struct tegra_hsic_config *config = &phy->pdata->u_cfg.hsic;
1659
1660         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1661
1662         utmip_powerup_pmc_wake_detect(phy);
1663
1664         if (phy->phy_clk_on) {
1665                 DBG("%s(%d) inst:[%d] phy clk is already On\n",
1666                                         __func__, __LINE__, phy->inst);
1667                 return 0;
1668         }
1669
1670         val = readl(base + UHSIC_PADS_CFG1);
1671         val &= ~(UHSIC_PD_BG | UHSIC_PD_TX | UHSIC_PD_TRK | UHSIC_PD_RX |
1672                         UHSIC_PD_ZI | UHSIC_RPD_DATA | UHSIC_RPD_STROBE);
1673         val |= UHSIC_RX_SEL;
1674         writel(val, base + UHSIC_PADS_CFG1);
1675         udelay(2);
1676
1677         val = readl(base + USB_SUSP_CTRL);
1678         val |= UHSIC_RESET;
1679         writel(val, base + USB_SUSP_CTRL);
1680         udelay(30);
1681
1682         val = readl(base + USB_SUSP_CTRL);
1683         val |= UHSIC_PHY_ENABLE;
1684         writel(val, base + USB_SUSP_CTRL);
1685
1686         val = readl(base + UHSIC_HSRX_CFG0);
1687         val |= UHSIC_IDLE_WAIT(config->idle_wait_delay);
1688         val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(config->elastic_underrun_limit);
1689         val |= UHSIC_ELASTIC_OVERRUN_LIMIT(config->elastic_overrun_limit);
1690         writel(val, base + UHSIC_HSRX_CFG0);
1691
1692         val = readl(base + UHSIC_HSRX_CFG1);
1693         val |= UHSIC_HS_SYNC_START_DLY(config->sync_start_delay);
1694         writel(val, base + UHSIC_HSRX_CFG1);
1695
1696         /* WAR HSIC TX */
1697         val = readl(base + UHSIC_TX_CFG0);
1698         val &= ~UHSIC_HS_READY_WAIT_FOR_VALID;
1699         writel(val, base + UHSIC_TX_CFG0);
1700
1701         val = readl(base + UHSIC_MISC_CFG0);
1702         val |= UHSIC_SUSPEND_EXIT_ON_EDGE;
1703         /* Disable generic bus reset, to allow AP30 specific bus reset*/
1704         val |= UHSIC_DISABLE_BUSRESET;
1705         writel(val, base + UHSIC_MISC_CFG0);
1706
1707         val = readl(base + UHSIC_MISC_CFG1);
1708         val |= UHSIC_PLLU_STABLE_COUNT(phy->freq->stable_count);
1709         writel(val, base + UHSIC_MISC_CFG1);
1710
1711         val = readl(base + UHSIC_PLL_CFG1);
1712         val |= UHSIC_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
1713         val |= UHSIC_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count);
1714         writel(val, base + UHSIC_PLL_CFG1);
1715
1716         val = readl(base + USB_SUSP_CTRL);
1717         val &= ~(UHSIC_RESET);
1718         writel(val, base + USB_SUSP_CTRL);
1719         udelay(2);
1720
1721         val = readl(base + USB_USBMODE);
1722         val |= USB_USBMODE_HOST;
1723         writel(val, base + USB_USBMODE);
1724
1725         /* Change the USB controller PHY type to HSIC */
1726         val = readl(base + HOSTPC1_DEVLC);
1727         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
1728         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
1729         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
1730         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
1731         writel(val, base + HOSTPC1_DEVLC);
1732
1733         val = readl(base + USB_TXFILLTUNING);
1734         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
1735                 val = USB_FIFO_TXFILL_THRES(0x10);
1736                 writel(val, base + USB_TXFILLTUNING);
1737         }
1738
1739         val = readl(base + USB_PORTSC);
1740         val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN);
1741         writel(val, base + USB_PORTSC);
1742
1743         val = readl(base + UHSIC_PADS_CFG0);
1744         val &= ~(UHSIC_TX_RTUNEN);
1745         /* set Rtune impedance to 50 ohm */
1746         val |= UHSIC_TX_RTUNE(8);
1747         writel(val, base + UHSIC_PADS_CFG0);
1748
1749         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1750                                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500)) {
1751                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
1752                 return -ETIMEDOUT;
1753         }
1754
1755         phy->phy_clk_on = true;
1756         phy->hw_accessible = true;
1757
1758         return 0;
1759 }
1760
1761 static int uhsic_phy_power_off(struct tegra_usb_phy *phy)
1762 {
1763         unsigned long val;
1764         void __iomem *base = phy->regs;
1765
1766         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1767         if (!phy->phy_clk_on) {
1768                 DBG("%s(%d) inst:[%d] phy clk is already off\n",
1769                                         __func__, __LINE__, phy->inst);
1770                 return 0;
1771         }
1772
1773         val = readl(base + UHSIC_PADS_CFG1);
1774         val &= ~UHSIC_RPU_STROBE;
1775         val |= UHSIC_RPD_STROBE;
1776         writel(val, base + UHSIC_PADS_CFG1);
1777
1778         val = readl(base + USB_SUSP_CTRL);
1779         val |= UHSIC_RESET;
1780         writel(val, base + USB_SUSP_CTRL);
1781         udelay(30);
1782
1783         utmip_powerdown_pmc_wake_detect(phy);
1784
1785         phy->phy_clk_on = false;
1786         phy->hw_accessible = false;
1787
1788         return 0;
1789 }
1790
1791 static int uhsic_phy_bus_port_power(struct tegra_usb_phy *phy)
1792 {
1793         unsigned long val;
1794         void __iomem *base = phy->regs;
1795
1796         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1797         val = readl(base + UHSIC_STAT_CFG0);
1798         val &= ~UHSIC_CONNECT_DETECT;
1799         writel(val, base + UHSIC_STAT_CFG0);
1800
1801         val = readl(base + USB_USBMODE);
1802         val |= USB_USBMODE_HOST;
1803         writel(val, base + USB_USBMODE);
1804
1805         /* Change the USB controller PHY type to HSIC */
1806         val = readl(base + HOSTPC1_DEVLC);
1807         val &= ~(HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK));
1808         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
1809         val &= ~(HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK));
1810         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
1811         writel(val, base + HOSTPC1_DEVLC);
1812
1813         val = readl(base + UHSIC_MISC_CFG0);
1814         val |= UHSIC_DETECT_SHORT_CONNECT;
1815         writel(val, base + UHSIC_MISC_CFG0);
1816         udelay(1);
1817
1818         val = readl(base + UHSIC_MISC_CFG0);
1819         val |= UHSIC_FORCE_XCVR_MODE;
1820         writel(val, base + UHSIC_MISC_CFG0);
1821
1822         val = readl(base + UHSIC_PADS_CFG1);
1823         val &= ~UHSIC_RPD_STROBE;
1824         /* safe to enable RPU on STROBE at all times during idle */
1825         val |= UHSIC_RPU_STROBE;
1826         writel(val, base + UHSIC_PADS_CFG1);
1827
1828         val = readl(base + USB_USBCMD);
1829         val &= ~USB_USBCMD_RS;
1830         writel(val, base + USB_USBCMD);
1831
1832         if (usb_phy_reg_status_wait(base + UHSIC_STAT_CFG0,
1833                         UHSIC_CONNECT_DETECT, UHSIC_CONNECT_DETECT, 25000)) {
1834                 pr_err("%s: timeout waiting for UHSIC_CONNECT_DETECT\n",
1835                                                                 __func__);
1836                 return -ETIMEDOUT;
1837         }
1838
1839         return 0;
1840 }
1841
1842 static int uhsic_phy_bus_reset(struct tegra_usb_phy *phy)
1843 {
1844         unsigned long val;
1845         void __iomem *base = phy->regs;
1846
1847         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1848
1849         /* Change the USB controller PHY type to HSIC */
1850         val = readl(base + HOSTPC1_DEVLC);
1851         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
1852         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
1853         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
1854         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
1855         writel(val, base + HOSTPC1_DEVLC);
1856         /* wait here, otherwise HOSTPC1_DEVLC_PSPD will timeout */
1857         mdelay(5);
1858
1859         val = readl(base + USB_PORTSC);
1860         val |= USB_PORTSC_PTC(5);
1861         writel(val, base + USB_PORTSC);
1862         udelay(2);
1863
1864         val = readl(base + USB_PORTSC);
1865         val &= ~(USB_PORTSC_PTC(~0));
1866         writel(val, base + USB_PORTSC);
1867         udelay(2);
1868
1869         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_LS(0),
1870                                                  0, 2000)) {
1871                 pr_err("%s: timeout waiting for USB_PORTSC_LS\n", __func__);
1872                 return -ETIMEDOUT;
1873         }
1874
1875         /* Poll until CCS is enabled */
1876         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
1877                                                  USB_PORTSC_CCS, 2000)) {
1878                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
1879                 return -ETIMEDOUT;
1880         }
1881
1882         if (usb_phy_reg_status_wait(base + HOSTPC1_DEVLC,
1883                         HOSTPC1_DEVLC_PSPD(2),
1884                         HOSTPC1_DEVLC_PSPD(2), 2000) < 0) {
1885                 pr_err("%s: timeout waiting hsic high speed configuration\n",
1886                                                 __func__);
1887                         return -ETIMEDOUT;
1888         }
1889
1890         val = readl(base + USB_USBCMD);
1891         val &= ~USB_USBCMD_RS;
1892         writel(val, base + USB_USBCMD);
1893
1894         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
1895                                                  USB_USBSTS_HCH, 2000)) {
1896                 pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
1897                 return -ETIMEDOUT;
1898         }
1899
1900         val = readl(base + UHSIC_PADS_CFG1);
1901         val &= ~UHSIC_RPU_STROBE;
1902         val |= UHSIC_RPD_STROBE;
1903         writel(val, base + UHSIC_PADS_CFG1);
1904
1905         mdelay(50);
1906
1907         val = readl(base + UHSIC_PADS_CFG1);
1908         val &= ~UHSIC_RPD_STROBE;
1909         val |= UHSIC_RPU_STROBE;
1910         writel(val, base + UHSIC_PADS_CFG1);
1911
1912         val = readl(base + USB_USBCMD);
1913         val |= USB_USBCMD_RS;
1914         writel(val, base + USB_USBCMD);
1915
1916         val = readl(base + UHSIC_PADS_CFG1);
1917         val &= ~UHSIC_RPU_STROBE;
1918         writel(val, base + UHSIC_PADS_CFG1);
1919
1920         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
1921                                                  USB_USBCMD_RS, 2000)) {
1922                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
1923                 return -ETIMEDOUT;
1924         }
1925
1926         return 0;
1927 }
1928
1929
1930 static int uhsic_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1931 {
1932         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1933
1934         usb_phy_wait_for_sof(phy);
1935
1936         return 0;
1937 }
1938
1939 static int uhsic_phy_resume(struct tegra_usb_phy *phy)
1940 {
1941         void __iomem *base = phy->regs;
1942         unsigned long val;
1943
1944         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1945
1946         /* Check if the phy resume from LP0. When the phy resume from LP0
1947          * USB register will be reset.to zero */
1948         if (!readl(base + USB_ASYNCLISTADDR)) {
1949
1950                 val = readl(base + USB_USBCMD);
1951                 val |= USB_CMD_RESET;
1952                 writel(val, base + USB_USBCMD);
1953
1954                 if (usb_phy_reg_status_wait(base + USB_USBCMD,
1955                         USB_CMD_RESET, 0, 2500) < 0) {
1956                         pr_err("%s: timeout waiting for reset\n", __func__);
1957                 }
1958
1959                 val = readl(base + USB_USBMODE);
1960                 val &= ~USB_USBMODE_MASK;
1961                 val |= USB_USBMODE_HOST;
1962                 writel(val, base + USB_USBMODE);
1963
1964                 /* Enable Port Power */
1965                 val = readl(base + USB_PORTSC);
1966                 val |= USB_PORTSC_PP;
1967                 writel(val, base + USB_PORTSC);
1968                 udelay(10);
1969
1970                 DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1971                 readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1972
1973                 uhsic_phy_bus_port_power(phy);
1974         }
1975
1976         return 0;
1977 }
1978
1979 static int uhsic_phy_post_resume(struct tegra_usb_phy *phy)
1980 {
1981         unsigned long val;
1982         void __iomem *base = phy->regs;
1983
1984         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1985         val = readl(base + USB_TXFILLTUNING);
1986         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
1987                 val = USB_FIFO_TXFILL_THRES(0x10);
1988                 writel(val, base + USB_TXFILLTUNING);
1989         }
1990
1991         return 0;
1992 }
1993
1994 static void ulpi_set_trimmer(struct tegra_usb_phy *phy)
1995 {
1996         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
1997         void __iomem *base = phy->regs;
1998         unsigned long val;
1999
2000         val = ULPI_DATA_TRIMMER_SEL(config->data_trimmer);
2001         val |= ULPI_STPDIRNXT_TRIMMER_SEL(config->stpdirnxt_trimmer);
2002         val |= ULPI_DIR_TRIMMER_SEL(config->dir_trimmer);
2003         writel(val, base + ULPI_TIMING_CTRL_1);
2004         udelay(10);
2005
2006         val |= ULPI_DATA_TRIMMER_LOAD;
2007         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
2008         val |= ULPI_DIR_TRIMMER_LOAD;
2009         writel(val, base + ULPI_TIMING_CTRL_1);
2010 }
2011
2012 static void reset_utmip_uhsic(void __iomem *base)
2013 {
2014         unsigned long val;
2015
2016         val = readl(base + USB_SUSP_CTRL);
2017         val |= UHSIC_RESET;
2018         writel(val, base + USB_SUSP_CTRL);
2019
2020         val = readl(base + USB_SUSP_CTRL);
2021         val |= UTMIP_RESET;
2022         writel(val, base + USB_SUSP_CTRL);
2023 }
2024
2025 static void ulpi_set_host(void __iomem *base)
2026 {
2027         unsigned long val;
2028
2029         val = readl(base + USB_USBMODE);
2030         val |= USB_USBMODE_HOST;
2031         writel(val, base + USB_USBMODE);
2032
2033         val = readl(base + HOSTPC1_DEVLC);
2034         val |= HOSTPC1_DEVLC_PTS(2);
2035         writel(val, base + HOSTPC1_DEVLC);
2036 }
2037
2038
2039
2040 static inline void null_phy_set_tristate(bool enable)
2041 {
2042 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2043         int tristate = (enable) ? TEGRA_TRI_TRISTATE : TEGRA_TRI_NORMAL;
2044         DBG("%s(%d) inst:[%s] FIXME enable pin group +++\n", __func__,
2045                                 __LINE__, enable ? "TRISTATE" : "NORMAL");
2046
2047         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA0, tristate);
2048         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA1, tristate);
2049         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA2, tristate);
2050         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA3, tristate);
2051         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA4, tristate);
2052         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA5, tristate);
2053         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA6, tristate);
2054         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA7, tristate);
2055         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_NXT, tristate);
2056
2057         if (enable)
2058                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR, tristate);
2059 #endif
2060
2061 }
2062
2063
2064 static int ulpi_null_phy_power_off(struct tegra_usb_phy *phy)
2065 {
2066         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2067
2068         if (!phy->phy_clk_on) {
2069                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
2070                                                         __LINE__, phy->inst);
2071                 return 0;
2072         }
2073
2074         null_phy_set_tristate(true);
2075
2076         phy->phy_clk_on = false;
2077         phy->hw_accessible = false;
2078
2079         return 0;
2080 }
2081
2082 static int ulpi_null_phy_init(struct tegra_usb_phy *phy)
2083 {
2084         unsigned long val;
2085         void __iomem *base = phy->regs;
2086
2087         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2088         usb_phy_init(phy);
2089         val = readl(base + ULPIS2S_CTRL);
2090         val |=  ULPIS2S_SLV0_CLAMP_XMIT;
2091         writel(val, base + ULPIS2S_CTRL);
2092
2093         val = readl(base + USB_SUSP_CTRL);
2094         val |= ULPIS2S_SLV0_RESET;
2095         writel(val, base + USB_SUSP_CTRL);
2096         udelay(10);
2097
2098         return 0;
2099 }
2100
2101 static int ulpi_null_phy_cmd_reset(struct tegra_usb_phy *phy)
2102 {
2103         unsigned long val;
2104         void __iomem *base = phy->regs;
2105
2106         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2107         ulpi_set_host(base);
2108
2109         /* remove slave0 reset */
2110         val = readl(base + USB_SUSP_CTRL);
2111         val &= ~ULPIS2S_SLV0_RESET;
2112         writel(val, base + USB_SUSP_CTRL);
2113
2114         val = readl(base + ULPIS2S_CTRL);
2115         val &=  ~ULPIS2S_SLV0_CLAMP_XMIT;
2116         writel(val, base + ULPIS2S_CTRL);
2117         udelay(10);
2118
2119         return 0;
2120 }
2121
2122 static int ulpi_null_phy_power_on(struct tegra_usb_phy *phy)
2123 {
2124         unsigned long val;
2125         void __iomem *base = phy->regs;
2126         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2127         static bool cold_boot = true;
2128
2129         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2130         if (phy->phy_clk_on) {
2131                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
2132                                                         __LINE__, phy->inst);
2133                 return 0;
2134         }
2135         reset_utmip_uhsic(base);
2136
2137         /* remove ULPI PADS CLKEN reset */
2138         val = readl(base + USB_SUSP_CTRL);
2139         val &= ~ULPI_PADS_CLKEN_RESET;
2140         writel(val, base + USB_SUSP_CTRL);
2141         udelay(10);
2142
2143         val = readl(base + ULPI_TIMING_CTRL_0);
2144         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
2145         writel(val, base + ULPI_TIMING_CTRL_0);
2146
2147         val = readl(base + USB_SUSP_CTRL);
2148         val |= ULPI_PHY_ENABLE;
2149         writel(val, base + USB_SUSP_CTRL);
2150         udelay(10);
2151
2152         /* set timming parameters */
2153         val = readl(base + ULPI_TIMING_CTRL_0);
2154         val |= ULPI_SHADOW_CLK_LOOPBACK_EN;
2155         val &= ~ULPI_SHADOW_CLK_SEL;
2156         val &= ~ULPI_LBK_PAD_EN;
2157         val |= ULPI_SHADOW_CLK_DELAY(config->shadow_clk_delay);
2158         val |= ULPI_CLOCK_OUT_DELAY(config->clock_out_delay);
2159         val |= ULPI_LBK_PAD_E_INPUT_OR;
2160         writel(val, base + ULPI_TIMING_CTRL_0);
2161
2162         writel(0, base + ULPI_TIMING_CTRL_1);
2163         udelay(10);
2164
2165         /* start internal 60MHz clock */
2166         val = readl(base + ULPIS2S_CTRL);
2167         val |= ULPIS2S_ENA;
2168         val |= ULPIS2S_SUPPORT_DISCONNECT;
2169         val |= ULPIS2S_SPARE((phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) ? 3 : 1);
2170         val |= ULPIS2S_PLLU_MASTER_BLASTER60;
2171         writel(val, base + ULPIS2S_CTRL);
2172
2173         /* select ULPI_CORE_CLK_SEL to SHADOW_CLK */
2174         val = readl(base + ULPI_TIMING_CTRL_0);
2175         val |= ULPI_CORE_CLK_SEL;
2176         writel(val, base + ULPI_TIMING_CTRL_0);
2177         udelay(10);
2178
2179         /* enable ULPI null phy clock - can't set the trimmers before this */
2180         val = readl(base + ULPI_TIMING_CTRL_0);
2181         val |= ULPI_CLK_OUT_ENA;
2182         writel(val, base + ULPI_TIMING_CTRL_0);
2183         udelay(10);
2184
2185         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
2186                                                  USB_PHY_CLK_VALID, 2500)) {
2187                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2188                 return -ETIMEDOUT;
2189         }
2190
2191         /* set ULPI trimmers */
2192         ulpi_set_trimmer(phy);
2193
2194         ulpi_set_host(base);
2195
2196         /* remove slave0 reset */
2197         val = readl(base + USB_SUSP_CTRL);
2198         val &= ~ULPIS2S_SLV0_RESET;
2199         writel(val, base + USB_SUSP_CTRL);
2200
2201         /* remove slave1 and line reset */
2202         val = readl(base + USB_SUSP_CTRL);
2203         val &= ~ULPIS2S_SLV1_RESET;
2204         val &= ~ULPIS2S_LINE_RESET;
2205
2206         /* remove ULPI PADS reset */
2207         val &= ~ULPI_PADS_RESET;
2208         writel(val, base + USB_SUSP_CTRL);
2209
2210         if (cold_boot) {
2211                 val = readl(base + ULPI_TIMING_CTRL_0);
2212                 val |= ULPI_CLK_PADOUT_ENA;
2213                 writel(val, base + ULPI_TIMING_CTRL_0);
2214                 cold_boot = false;
2215         }
2216         udelay(10);
2217
2218         phy->phy_clk_on = true;
2219         phy->hw_accessible = true;
2220
2221         return 0;
2222 }
2223
2224
2225 static int ulpi_null_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
2226 {
2227         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2228
2229         usb_phy_wait_for_sof(phy);
2230         return 0;
2231 }
2232
2233 static struct tegra_usb_phy_ops utmi_phy_ops = {
2234         .init           = usb_phy_init,
2235         .open           = utmi_phy_open,
2236         .close          = utmi_phy_close,
2237         .irq            = utmi_phy_irq,
2238         .power_on       = utmi_phy_power_on,
2239         .power_off      = utmi_phy_power_off,
2240         .pre_resume = utmi_phy_pre_resume,
2241         .resume = utmi_phy_resume,
2242         .post_resume    = utmi_phy_post_resume,
2243         .charger_detect = utmi_phy_charger_detect,
2244 };
2245
2246 static struct tegra_usb_phy_ops uhsic_phy_ops = {
2247         .init           = usb_phy_init,
2248         .open           = uhsic_phy_open,
2249         .power_on       = uhsic_phy_power_on,
2250         .power_off      = uhsic_phy_power_off,
2251         .pre_resume = uhsic_phy_pre_resume,
2252         .resume = uhsic_phy_resume,
2253         .post_resume = uhsic_phy_post_resume,
2254         .port_power = uhsic_phy_bus_port_power,
2255         .bus_reset      = uhsic_phy_bus_reset,
2256 };
2257
2258 static struct tegra_usb_phy_ops ulpi_null_phy_ops = {
2259         .init           = ulpi_null_phy_init,
2260         .power_on       = ulpi_null_phy_power_on,
2261         .power_off      = ulpi_null_phy_power_off,
2262         .pre_resume = ulpi_null_phy_pre_resume,
2263         .reset          = ulpi_null_phy_cmd_reset,
2264 };
2265
2266 static struct tegra_usb_phy_ops ulpi_link_phy_ops;
2267 static struct tegra_usb_phy_ops icusb_phy_ops;
2268
2269 static struct tegra_usb_phy_ops *phy_ops[] = {
2270         [TEGRA_USB_PHY_INTF_UTMI] = &utmi_phy_ops,
2271         [TEGRA_USB_PHY_INTF_ULPI_LINK] = &ulpi_link_phy_ops,
2272         [TEGRA_USB_PHY_INTF_ULPI_NULL] = &ulpi_null_phy_ops,
2273         [TEGRA_USB_PHY_INTF_HSIC] = &uhsic_phy_ops,
2274         [TEGRA_USB_PHY_INTF_ICUSB] = &icusb_phy_ops,
2275 };
2276
2277 int tegra11x_usb_phy_init_ops(struct tegra_usb_phy *phy)
2278 {
2279         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2280
2281         phy->ops = phy_ops[phy->pdata->phy_intf];
2282
2283         /* FIXME: uncommenting below line to make USB host mode fail*/
2284         /* usb_phy_power_down_pmc(); */
2285
2286         return 0;
2287 }