a543d93ecbee8de5bcd9ffe830e8348993ac3e6e
[linux-2.6.git] / arch / arm / mach-tegra / tegra11x_usb_phy.c
1 /*
2  * arch/arm/mach-tegra/tegra11x_usb_phy.c
3  *
4  * Copyright (C) 2012 NVIDIA Corporation
5  *
6  *
7  * This software is licensed under the terms of the GNU General Public
8  * License version 2, as published by the Free Software Foundation, and
9  * may be copied, distributed, and modified under those terms.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17 #include <linux/resource.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/slab.h>
21 #include <linux/err.h>
22 #include <linux/platform_device.h>
23 #include <linux/io.h>
24 #include <linux/gpio.h>
25 #include <linux/interrupt.h>
26 #include <linux/clk.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <mach/iomap.h>
30 #include <mach/pinmux.h>
31 #include <mach/pinmux-t11.h>
32 #include "tegra_usb_phy.h"
33 #include "fuse.h"
34
35 #define USB_USBCMD              0x130
36 #define   USB_USBCMD_RS         (1 << 0)
37 #define   USB_CMD_RESET (1<<1)
38
39 #define USB_USBSTS              0x134
40 #define   USB_USBSTS_PCI        (1 << 2)
41 #define   USB_USBSTS_SRI        (1 << 7)
42 #define   USB_USBSTS_HCH        (1 << 12)
43
44 #define USB_TXFILLTUNING        0x154
45 #define USB_FIFO_TXFILL_THRES(x)   (((x) & 0x1f) << 16)
46 #define USB_FIFO_TXFILL_MASK    0x1f0000
47
48 #define USB_ASYNCLISTADDR       0x148
49
50 #define ICUSB_CTRL              0x15c
51
52 #define USB_PORTSC              0x174
53 #define   USB_PORTSC_WKOC       (1 << 22)
54 #define   USB_PORTSC_WKDS       (1 << 21)
55 #define   USB_PORTSC_WKCN       (1 << 20)
56 #define   USB_PORTSC_PTC(x)     (((x) & 0xf) << 16)
57 #define   USB_PORTSC_PP (1 << 12)
58 #define   USB_PORTSC_LS(x) (((x) & 0x3) << 10)
59 #define   USB_PORTSC_SUSP       (1 << 7)
60 #define   USB_PORTSC_RESUME     (1 << 6)
61 #define   USB_PORTSC_OCC        (1 << 5)
62 #define   USB_PORTSC_PEC        (1 << 3)
63 #define   USB_PORTSC_PE         (1 << 2)
64 #define   USB_PORTSC_CSC        (1 << 1)
65 #define   USB_PORTSC_CCS        (1 << 0)
66 #define   USB_PORTSC_RWC_BITS (USB_PORTSC_CSC | USB_PORTSC_PEC | USB_PORTSC_OCC)
67
68 #define HOSTPC1_DEVLC           0x1b4
69 #define   HOSTPC1_DEVLC_PHCD            (1 << 22)
70 #define   HOSTPC1_DEVLC_PTS(x)          (((x) & 0x7) << 29)
71 #define   HOSTPC1_DEVLC_PTS_MASK        7
72 #define   HOSTPC1_DEVLC_PTS_HSIC        4
73 #define   HOSTPC1_DEVLC_STS             (1 << 28)
74 #define   HOSTPC1_DEVLC_PSPD(x)         (((x) & 0x3) << 25)
75 #define   HOSTPC1_DEVLC_PSPD_MASK       3
76 #define   HOSTPC1_DEVLC_PSPD_HIGH_SPEED 2
77 #define   HOSTPC1_DEVLC_NYT_ASUS        1
78
79 #define USB_USBMODE             0x1f8
80 #define   USB_USBMODE_MASK              (3 << 0)
81 #define   USB_USBMODE_HOST              (3 << 0)
82 #define   USB_USBMODE_DEVICE            (2 << 0)
83
84 #define USB_SUSP_CTRL           0x400
85 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
86 #define   USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
87 #define   USB_SUSP_CLR                  (1 << 5)
88 #define   USB_PHY_CLK_VALID             (1 << 7)
89 #define   USB_PHY_CLK_VALID_INT_ENB     (1 << 9)
90 #define   USB_PHY_CLK_VALID_INT_STS     (1 << 8)
91 #define   UTMIP_RESET                   (1 << 11)
92 #define   UTMIP_PHY_ENABLE              (1 << 12)
93 #define   ULPI_PHY_ENABLE               (1 << 13)
94 #define   UHSIC_RESET                   (1 << 14)
95 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
96 #define   UHSIC_PHY_ENABLE              (1 << 19)
97 #define   ULPIS2S_SLV0_RESET            (1 << 20)
98 #define   ULPIS2S_SLV1_RESET            (1 << 21)
99 #define   ULPIS2S_LINE_RESET            (1 << 22)
100 #define   ULPI_PADS_RESET               (1 << 23)
101 #define   ULPI_PADS_CLKEN_RESET         (1 << 24)
102
103 #define USB_PHY_VBUS_WAKEUP_ID  0x408
104 #define   VDAT_DET_INT_EN       (1 << 16)
105 #define   VDAT_DET_CHG_DET      (1 << 17)
106 #define   VDAT_DET_STS          (1 << 18)
107 #define   USB_ID_STATUS         (1 << 2)
108
109 #define ULPIS2S_CTRL            0x418
110 #define   ULPIS2S_ENA                   (1 << 0)
111 #define   ULPIS2S_SUPPORT_DISCONNECT    (1 << 2)
112 #define   ULPIS2S_PLLU_MASTER_BLASTER60 (1 << 3)
113 #define   ULPIS2S_SPARE(x)              (((x) & 0xF) << 8)
114 #define   ULPIS2S_FORCE_ULPI_CLK_OUT    (1 << 12)
115 #define   ULPIS2S_DISCON_DONT_CHECK_SE0 (1 << 13)
116 #define   ULPIS2S_SUPPORT_HS_KEEP_ALIVE (1 << 14)
117 #define   ULPIS2S_DISABLE_STP_PU        (1 << 15)
118 #define   ULPIS2S_SLV0_CLAMP_XMIT       (1 << 16)
119
120 #define ULPI_TIMING_CTRL_0      0x424
121 #define   ULPI_CLOCK_OUT_DELAY(x)       ((x) & 0x1F)
122 #define   ULPI_OUTPUT_PINMUX_BYP        (1 << 10)
123 #define   ULPI_CLKOUT_PINMUX_BYP        (1 << 11)
124 #define   ULPI_SHADOW_CLK_LOOPBACK_EN   (1 << 12)
125 #define   ULPI_SHADOW_CLK_SEL           (1 << 13)
126 #define   ULPI_CORE_CLK_SEL             (1 << 14)
127 #define   ULPI_SHADOW_CLK_DELAY(x)      (((x) & 0x1F) << 16)
128 #define   ULPI_LBK_PAD_EN               (1 << 26)
129 #define   ULPI_LBK_PAD_E_INPUT_OR       (1 << 27)
130 #define   ULPI_CLK_OUT_ENA              (1 << 28)
131 #define   ULPI_CLK_PADOUT_ENA           (1 << 29)
132
133 #define ULPI_TIMING_CTRL_1      0x428
134 #define   ULPI_DATA_TRIMMER_LOAD        (1 << 0)
135 #define   ULPI_DATA_TRIMMER_SEL(x)      (((x) & 0x7) << 1)
136 #define   ULPI_STPDIRNXT_TRIMMER_LOAD   (1 << 16)
137 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
138 #define   ULPI_DIR_TRIMMER_LOAD         (1 << 24)
139 #define   ULPI_DIR_TRIMMER_SEL(x)       (((x) & 0x7) << 25)
140
141 #define USB_IF_SPARE    0x498
142 #define   USB_HS_RSM_EOP_EN         (1 << 4)
143 #define   USB_PORT_SUSPEND_EN       (1 << 5)
144
145 #define USB_NEW_CONTROL  0x4c0
146 #define   USB_COHRENCY_EN           (1 << 0)
147 #define   USB_MEM_ALLIGNMENT_MUX_EN (1 << 1)
148
149 #define UTMIP_XCVR_CFG0         0x808
150 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
151 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
152 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
153 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
154 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
155 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
156 #define   UTMIP_XCVR_LSBIAS_SEL                 (1 << 21)
157 #define   UTMIP_XCVR_SETUP_MSB(x)               (((x) & 0x7) << 22)
158 #define   UTMIP_XCVR_HSSLEW_MSB(x)              (((x) & 0x7f) << 25)
159 #define   UTMIP_XCVR_MAX_OFFSET         2
160 #define   UTMIP_XCVR_SETUP_MAX_VALUE    0x7f
161 #define   UTMIP_XCVR_SETUP_MIN_VALUE    0
162 #define   XCVR_SETUP_MSB_CALIB(x) ((x) >> 4)
163
164 #define UTMIP_BIAS_CFG0         0x80c
165 #define   UTMIP_OTGPD                   (1 << 11)
166 #define   UTMIP_BIASPD                  (1 << 10)
167 #define   UTMIP_HSSQUELCH_LEVEL(x)      (((x) & 0x3) << 0)
168 #define   UTMIP_HSDISCON_LEVEL(x)       (((x) & 0x3) << 2)
169 #define   UTMIP_HSDISCON_LEVEL_MSB      (1 << 24)
170
171 #define UTMIP_HSRX_CFG0         0x810
172 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
173 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
174
175 #define UTMIP_HSRX_CFG1         0x814
176 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
177
178 #define UTMIP_TX_CFG0           0x820
179 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
180 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
181
182 #define UTMIP_DEBOUNCE_CFG0 0x82c
183 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
184
185 #define UTMIP_BAT_CHRG_CFG0 0x830
186 #define   UTMIP_PD_CHRG                 (1 << 0)
187 #define   UTMIP_ON_SINK_EN              (1 << 2)
188 #define   UTMIP_OP_SRC_EN               (1 << 3)
189
190 #define UTMIP_XCVR_CFG1         0x838
191 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
192 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
193 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
194 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
195
196 #define UTMIP_BIAS_CFG1         0x83c
197 #define   UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
198 #define   UTMIP_BIAS_PDTRK_POWERDOWN    (1 << 0)
199 #define   UTMIP_BIAS_PDTRK_POWERUP      (1 << 1)
200
201 #define UTMIP_MISC_CFG0         0x824
202 #define   UTMIP_DPDM_OBSERVE            (1 << 26)
203 #define   UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
204 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J   UTMIP_DPDM_OBSERVE_SEL(0xf)
205 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K   UTMIP_DPDM_OBSERVE_SEL(0xe)
206 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
207 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
208 #define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
209 #define   FORCE_PULLDN_DM       (1 << 8)
210 #define   FORCE_PULLDN_DP       (1 << 9)
211 #define   COMB_TERMS            (1 << 0)
212 #define   ALWAYS_FREE_RUNNING_TERMS (1 << 1)
213
214 #define UTMIP_SPARE_CFG0        0x834
215 #define   FUSE_SETUP_SEL                (1 << 3)
216 #define   FUSE_ATERM_SEL                (1 << 4)
217
218 #define UTMIP_PMC_WAKEUP0               0x84c
219 #define   EVENT_INT_ENB                 (1 << 0)
220
221 #define UTMIP_BIAS_STS0                 0x840
222 #define   UTMIP_RCTRL_VAL(x)            (((x) & 0xffff) << 0)
223 #define   UTMIP_TCTRL_VAL(x)            (((x) & (0xffff << 16)) >> 16)
224
225 #define UHSIC_PLL_CFG1                          0xc04
226 #define   UHSIC_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
227 #define   UHSIC_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 14)
228
229 #define UHSIC_HSRX_CFG0                         0xc08
230 #define   UHSIC_ELASTIC_UNDERRUN_LIMIT(x)       (((x) & 0x1f) << 2)
231 #define   UHSIC_ELASTIC_OVERRUN_LIMIT(x)        (((x) & 0x1f) << 8)
232 #define   UHSIC_IDLE_WAIT(x)                    (((x) & 0x1f) << 13)
233
234 #define UHSIC_HSRX_CFG1                         0xc0c
235 #define   UHSIC_HS_SYNC_START_DLY(x)            (((x) & 0x1f) << 1)
236
237 #define UHSIC_TX_CFG0                           0xc10
238 #define UHSIC_HS_READY_WAIT_FOR_VALID   (1 << 9)
239 #define UHSIC_MISC_CFG0                         0xc14
240 #define   UHSIC_SUSPEND_EXIT_ON_EDGE            (1 << 7)
241 #define   UHSIC_DETECT_SHORT_CONNECT            (1 << 8)
242 #define   UHSIC_FORCE_XCVR_MODE                 (1 << 15)
243 #define   UHSIC_DISABLE_BUSRESET                (1 << 20)
244 #define UHSIC_MISC_CFG1                         0xc18
245 #define   UHSIC_PLLU_STABLE_COUNT(x)            (((x) & 0xfff) << 2)
246
247 #define UHSIC_PADS_CFG0                         0xc1c
248 #define   UHSIC_TX_RTUNEN                       0xf000
249 #define   UHSIC_TX_RTUNE(x)                     (((x) & 0xf) << 12)
250
251 #define UHSIC_PADS_CFG1                         0xc20
252 #define   UHSIC_PD_BG                           (1 << 2)
253 #define   UHSIC_PD_TX                           (1 << 3)
254 #define   UHSIC_PD_TRK                          (1 << 4)
255 #define   UHSIC_PD_RX                           (1 << 5)
256 #define   UHSIC_PD_ZI                           (1 << 6)
257 #define   UHSIC_RX_SEL                          (1 << 7)
258 #define   UHSIC_RPD_DATA                        (1 << 9)
259 #define   UHSIC_RPD_STROBE                      (1 << 10)
260 #define   UHSIC_RPU_DATA                        (1 << 11)
261 #define   UHSIC_RPU_STROBE                      (1 << 12)
262
263 #define UHSIC_STAT_CFG0                 0xc28
264 #define   UHSIC_CONNECT_DETECT                  (1 << 0)
265
266 #define PMC_USB_DEBOUNCE                        0xec
267 #define   UTMIP_LINE_DEB_CNT(x)                 (((x) & 0xf) << 16)
268
269 #define PMC_USB_AO                              0xf0
270 #define PMC_POWER_DOWN_MASK                     0xffff
271 #define HSIC_RESERVED_P0                        (3 << 14)
272 #define HSIC_STOBE_VAL_PD_P0                    (1 << 13)
273 #define HSIC_DATA_VAL_PD_P0                     (1 << 12)
274 #define USB_ID_PD(inst)                         (1 << ((4*(inst))+3))
275 #define VBUS_WAKEUP_PD(inst)                    (1 << ((4*(inst))+2))
276 #define   USBON_VAL_PD(inst)                    (1 << ((4*(inst))+1))
277 #define   USBON_VAL_PD_P2                       (1 << 9)
278 #define   USBON_VAL_PD_P1                       (1 << 5)
279 #define   USBON_VAL_PD_P0                       (1 << 1)
280 #define   USBOP_VAL_PD(inst)                    (1 << (4*(inst)))
281 #define   USBOP_VAL_PD_P2                       (1 << 8)
282 #define   USBOP_VAL_PD_P1                       (1 << 4)
283 #define   USBOP_VAL_PD_P0                       (1 << 0)
284 #define   PMC_USB_AO_PD_P2                      (0xf << 8)
285 #define   PMC_USB_AO_ID_PD_P0                   (1 << 3)
286 #define   PMC_USB_AO_VBUS_WAKEUP_PD_P0  (1 << 2)
287
288 #define PMC_TRIGGERS                    0x1ec
289 #define   UTMIP_CLR_WALK_PTR(inst)      (1 << (inst))
290 #define   UTMIP_CLR_WALK_PTR_P2         (1 << 2)
291 #define   UTMIP_CLR_WALK_PTR_P1         (1 << 1)
292 #define   UTMIP_CLR_WALK_PTR_P0         (1 << 0)
293 #define   UTMIP_CAP_CFG(inst)   (1 << ((inst)+4))
294 #define   UTMIP_CAP_CFG_P2              (1 << 6)
295 #define   UTMIP_CAP_CFG_P1              (1 << 5)
296 #define   UTMIP_CAP_CFG_P0              (1 << 4)
297 #define   UTMIP_CLR_WAKE_ALARM(inst)            (1 << ((inst)+12))
298 #define   UTMIP_CLR_WAKE_ALARM_P2       (1 << 14)
299
300 #define PMC_PAD_CFG             (0x1f4)
301
302 #define PMC_UTMIP_TERM_PAD_CFG  0x1f8
303 #define   PMC_TCTRL_VAL(x)      (((x) & 0x1f) << 5)
304 #define   PMC_RCTRL_VAL(x)      (((x) & 0x1f) << 0)
305
306 #define UHSIC_SLEEPWALK_REG             0x210
307 #define UHSIC_DATA_RPD_D                (1 << 25)
308 #define UHSIC_STRB_RPD_D                (1 << 24)
309 #define UHSIC_DATA_RPD_C                (1 << 17)
310 #define UHSIC_STRB_RPD_C                (1 << 16)
311 #define UHSIC_DATA_RPD_B                (1 << 9)
312 #define UHSIC_STRB_RPD_B                (1 << 8)
313 #define UHSIC_DATA_RPD_A                (1 << 1)
314 #define UHSIC_STRB_RPD_A                (1 << 0)
315
316 #define PMC_SLEEP_CFG                   0x1fc
317 #define   UTMIP_TCTRL_USE_PMC(inst) (1 << ((8*(inst))+3))
318 #define   UTMIP_TCTRL_USE_PMC_P2                (1 << 19)
319 #define   UTMIP_TCTRL_USE_PMC_P1                (1 << 11)
320 #define   UTMIP_TCTRL_USE_PMC_P0                (1 << 3)
321 #define   UTMIP_RCTRL_USE_PMC(inst) (1 << ((8*(inst))+2))
322 #define   UTMIP_RCTRL_USE_PMC_P2                (1 << 18)
323 #define   UTMIP_RCTRL_USE_PMC_P1                (1 << 10)
324 #define   UTMIP_RCTRL_USE_PMC_P0                (1 << 2)
325 #define   UTMIP_FSLS_USE_PMC(inst)      (1 << ((8*(inst))+1))
326 #define   UTMIP_FSLS_USE_PMC_P2         (1 << 17)
327 #define   UTMIP_FSLS_USE_PMC_P1         (1 << 9)
328 #define   UTMIP_FSLS_USE_PMC_P0         (1 << 1)
329 #define   UTMIP_MASTER_ENABLE(inst) (1 << (8*(inst)))
330 #define   UTMIP_MASTER_ENABLE_P2                (1 << 16)
331 #define   UTMIP_MASTER_ENABLE_P1                (1 << 8)
332 #define   UTMIP_MASTER_ENABLE_P0                (1 << 0)
333 #define UHSIC_MASTER_ENABLE_P0          (1 << 24)
334 #define UHSIC_WAKE_VAL_P0(x)            (((x) & 0xf) << 28)
335
336 #define PMC_SLEEPWALK_CFG               0x200
337 #define   UTMIP_LINEVAL_WALK_EN(inst) (1 << ((8*(inst))+7))
338 #define   UTMIP_LINEVAL_WALK_EN_P2      (1 << 23)
339 #define   UTMIP_LINEVAL_WALK_EN_P1      (1 << 15)
340 #define   UTMIP_LINEVAL_WALK_EN_P0      (1 << 7)
341 #define   UTMIP_WAKE_VAL(inst, x) (((x) & 0xf) << ((8*(inst))+4))
342 #define   UTMIP_WAKE_VAL_P2(x)          (((x) & 0xf) << 20)
343 #define   UTMIP_WAKE_VAL_P1(x)          (((x) & 0xf) << 12)
344 #define   UTMIP_WAKE_VAL_P0(x)          (((x) & 0xf) << 4)
345 #define   WAKE_VAL_NONE         0xc
346 #define   WAKE_VAL_ANY                  0xF
347 #define   WAKE_VAL_FSJ                  0x2
348 #define   WAKE_VAL_FSK                  0x1
349 #define   WAKE_VAL_SE0                  0x0
350
351 #define PMC_SLEEPWALK_REG(inst)         (0x204 + (4*(inst)))
352 #define   UTMIP_USBOP_RPD_A     (1 << 0)
353 #define   UTMIP_USBON_RPD_A     (1 << 1)
354 #define   UTMIP_AP_A                    (1 << 4)
355 #define   UTMIP_AN_A                    (1 << 5)
356 #define   UTMIP_HIGHZ_A         (1 << 6)
357 #define   UTMIP_USBOP_RPD_B     (1 << 8)
358 #define   UTMIP_USBON_RPD_B     (1 << 9)
359 #define   UTMIP_AP_B                    (1 << 12)
360 #define   UTMIP_AN_B                    (1 << 13)
361 #define   UTMIP_HIGHZ_B         (1 << 14)
362 #define   UTMIP_USBOP_RPD_C     (1 << 16)
363 #define   UTMIP_USBON_RPD_C     (1 << 17)
364 #define   UTMIP_AP_C            (1 << 20)
365 #define   UTMIP_AN_C            (1 << 21)
366 #define   UTMIP_HIGHZ_C         (1 << 22)
367 #define   UTMIP_USBOP_RPD_D     (1 << 24)
368 #define   UTMIP_USBON_RPD_D     (1 << 25)
369 #define   UTMIP_AP_D            (1 << 28)
370 #define   UTMIP_AN_D            (1 << 29)
371 #define   UTMIP_HIGHZ_D         (1 << 30)
372
373 #define UTMIP_UHSIC_STATUS              0x214
374 #define   UTMIP_WALK_PTR_VAL(inst)      (0x3 << ((inst)*2))
375 #define   UTMIP_USBOP_VAL(inst)         (1 << ((2*(inst)) + 8))
376 #define   UTMIP_USBOP_VAL_P2            (1 << 12)
377 #define   UTMIP_USBOP_VAL_P1            (1 << 10)
378 #define   UTMIP_USBOP_VAL_P0            (1 << 8)
379 #define   UTMIP_USBON_VAL(inst)         (1 << ((2*(inst)) + 9))
380 #define   UTMIP_USBON_VAL_P2            (1 << 13)
381 #define   UTMIP_USBON_VAL_P1            (1 << 11)
382 #define   UTMIP_USBON_VAL_P0            (1 << 9)
383 #define   UTMIP_WAKE_ALARM(inst)                (1 << ((inst) + 16))
384 #define   UTMIP_WAKE_ALARM_P2   (1 << 18)
385 #define   UTMIP_WAKE_ALARM_P1   (1 << 17)
386 #define   UTMIP_WAKE_ALARM_P0   (1 << 16)
387 #define   UTMIP_WALK_PTR(inst)  (1 << ((inst)*2))
388 #define   UTMIP_WALK_PTR_P2     (1 << 4)
389 #define   UTMIP_WALK_PTR_P1     (1 << 2)
390 #define   UTMIP_WALK_PTR_P0     (1 << 0)
391
392 #define USB1_PREFETCH_ID               6
393 #define USB2_PREFETCH_ID               18
394 #define USB3_PREFETCH_ID               17
395
396 #define PMC_UTMIP_UHSIC_FAKE            0x218
397 #define   USBON_VAL(inst)       (1 << ((4*(inst))+1))
398 #define   USBON_VAL_P2                  (1 << 9)
399 #define   USBON_VAL_P1                  (1 << 5)
400 #define   USBON_VAL_P0                  (1 << 1)
401 #define   USBOP_VAL(inst)       (1 << (4*(inst)))
402 #define   USBOP_VAL_P2                  (1 << 8)
403 #define   USBOP_VAL_P1                  (1 << 4)
404 #define   USBOP_VAL_P0                  (1 << 0)
405
406 #define PMC_UTMIP_BIAS_MASTER_CNTRL 0x30c
407 #define   BIAS_MASTER_PROG_VAL          (1 << 1)
408
409 #define PMC_UTMIP_MASTER_CONFIG         0x310
410 #define   UTMIP_PWR(inst)               (1 << (inst))
411
412 #define FUSE_USB_CALIB_0                0x1F0
413 #define   FUSE_USB_CALIB_XCVR_SETUP(x)  (((x) & 0x7F) << 0)
414
415 /* These values (in milli second) are taken from the battery charging spec */
416 #define TDP_SRC_ON_MS    100
417 #define TDPSRC_CON_MS    40
418
419 #ifdef DEBUG
420 #define DBG(stuff...)   pr_info("tegra11x_usb_phy: " stuff)
421 #else
422 #define DBG(stuff...)   do {} while (0)
423 #endif
424
425 static u32 utmip_rctrl_val, utmip_tctrl_val;
426 static DEFINE_SPINLOCK(utmip_pad_lock);
427 static int utmip_pad_count;
428
429 static struct tegra_xtal_freq utmip_freq_table[] = {
430         {
431                 .freq = 12000000,
432                 .enable_delay = 0x02,
433                 .stable_count = 0x2F,
434                 .active_delay = 0x04,
435                 .xtal_freq_count = 0x76,
436                 .debounce = 0x7530,
437                 .pdtrk_count = 5,
438         },
439         {
440                 .freq = 13000000,
441                 .enable_delay = 0x02,
442                 .stable_count = 0x33,
443                 .active_delay = 0x05,
444                 .xtal_freq_count = 0x7F,
445                 .debounce = 0x7EF4,
446                 .pdtrk_count = 5,
447         },
448         {
449                 .freq = 19200000,
450                 .enable_delay = 0x03,
451                 .stable_count = 0x4B,
452                 .active_delay = 0x06,
453                 .xtal_freq_count = 0xBB,
454                 .debounce = 0xBB80,
455                 .pdtrk_count = 7,
456         },
457         {
458                 .freq = 26000000,
459                 .enable_delay = 0x04,
460                 .stable_count = 0x66,
461                 .active_delay = 0x09,
462                 .xtal_freq_count = 0xFE,
463                 .debounce = 0xFDE8,
464                 .pdtrk_count = 9,
465         },
466 };
467
468 static struct tegra_xtal_freq uhsic_freq_table[] = {
469         {
470                 .freq = 12000000,
471                 .enable_delay = 0x02,
472                 .stable_count = 0x2F,
473                 .active_delay = 0x0,
474                 .xtal_freq_count = 0x1CA,
475         },
476         {
477                 .freq = 13000000,
478                 .enable_delay = 0x02,
479                 .stable_count = 0x33,
480                 .active_delay = 0x0,
481                 .xtal_freq_count = 0x1F0,
482         },
483         {
484                 .freq = 19200000,
485                 .enable_delay = 0x03,
486                 .stable_count = 0x4B,
487                 .active_delay = 0x0,
488                 .xtal_freq_count = 0x2DD,
489         },
490         {
491                 .freq = 26000000,
492                 .enable_delay = 0x04,
493                 .stable_count = 0x66,
494                 .active_delay = 0x0,
495                 .xtal_freq_count = 0x3E0,
496         },
497 };
498
499 static int usb_phy_init(struct tegra_usb_phy *phy)
500 {
501         unsigned long val;
502         void __iomem *base = phy->regs;
503
504         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
505
506         val = readl(base + HOSTPC1_DEVLC);
507         val &= ~HOSTPC1_DEVLC_STS;
508         writel(val, base + HOSTPC1_DEVLC);
509
510         val = readl(base + USB_IF_SPARE);
511         val |= USB_HS_RSM_EOP_EN;
512         val |= USB_PORT_SUSPEND_EN;
513         writel(val, base + USB_IF_SPARE);
514
515         val = readl(base + USB_NEW_CONTROL);
516         val |= USB_COHRENCY_EN;
517         writel(val, base + USB_NEW_CONTROL);
518
519         return 0;
520 }
521
522 static void utmip_setup_pmc_wake_detect(struct tegra_usb_phy *phy)
523 {
524         unsigned long val, pmc_pad_cfg_val;
525         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
526         unsigned  int inst = phy->inst;
527         void __iomem *base = phy->regs;
528         bool port_connected;
529         enum usb_phy_port_speed port_speed;
530
531         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
532
533         /* check for port connect status */
534         val = readl(base + USB_PORTSC);
535         port_connected = val & USB_PORTSC_CCS;
536
537         if (!port_connected)
538                 return;
539
540         port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
541                 HOSTPC1_DEVLC_PSPD_MASK;
542         /*Set PMC MASTER bits to do the following
543         * a. Take over the UTMI drivers
544         * b. set up such that it will take over resume
545         *        if remote wakeup is detected
546         * Prepare PMC to take over suspend-wake detect-drive resume until USB
547         * controller ready
548         */
549
550         /* disable master enable in PMC */
551         val = readl(pmc_base + PMC_SLEEP_CFG);
552         val &= ~UTMIP_MASTER_ENABLE(inst);
553         writel(val, pmc_base + PMC_SLEEP_CFG);
554
555         /* UTMIP_PWR_PX=1 for power savings mode */
556         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
557         val |= UTMIP_PWR(inst);
558         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
559
560         /* config debouncer */
561         val = readl(pmc_base + PMC_USB_DEBOUNCE);
562         val &= ~UTMIP_LINE_DEB_CNT(~0);
563         val |= UTMIP_LINE_DEB_CNT(4);
564         writel(val, pmc_base + PMC_USB_DEBOUNCE);
565
566         /* Make sure nothing is happening on the line with respect to PMC */
567         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
568         val &= ~USBOP_VAL(inst);
569         val &= ~USBON_VAL(inst);
570         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
571
572         /* Make sure wake value for line is none */
573         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
574         val &= ~UTMIP_LINEVAL_WALK_EN(inst);
575         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
576         val = readl(pmc_base + PMC_SLEEP_CFG);
577         val &= ~UTMIP_WAKE_VAL(inst, ~0);
578         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
579         writel(val, pmc_base + PMC_SLEEP_CFG);
580
581         /* turn off pad detectors */
582         val = readl(pmc_base + PMC_USB_AO);
583         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
584         writel(val, pmc_base + PMC_USB_AO);
585
586         /* Remove fake values and make synchronizers work a bit */
587         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
588         val &= ~USBOP_VAL(inst);
589         val &= ~USBON_VAL(inst);
590         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
591
592         /* Enable which type of event can trigger a walk,
593         in this case usb_line_wake */
594         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
595         val |= UTMIP_LINEVAL_WALK_EN(inst);
596         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
597
598         /* Enable which type of event can trigger a walk,
599         * in this case usb_line_wake */
600         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
601         val |= UTMIP_LINEVAL_WALK_EN(inst);
602         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
603
604         /* Clear the walk pointers and wake alarm */
605         val = readl(pmc_base + PMC_TRIGGERS);
606         val |= UTMIP_CLR_WAKE_ALARM(inst) | UTMIP_CLR_WALK_PTR(inst);
607         writel(val, pmc_base + PMC_TRIGGERS);
608
609
610         /* Capture FS/LS pad configurations */
611         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
612         val = readl(pmc_base + PMC_TRIGGERS);
613         val |= UTMIP_CAP_CFG(inst);
614         writel(val, pmc_base + PMC_TRIGGERS);
615         udelay(1);
616         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
617
618         /* BIAS MASTER_ENABLE=0 */
619         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
620         val &= ~BIAS_MASTER_PROG_VAL;
621         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
622
623         /* program walk sequence, maintain a J, followed by a driven K
624         * to signal a resume once an wake event is detected */
625         val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
626         val &= ~UTMIP_AP_A;
627         val |= UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_AN_A |UTMIP_HIGHZ_A |
628                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_AP_B | UTMIP_AN_B |
629                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_AP_C | UTMIP_AN_C |
630                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_AP_D | UTMIP_AN_D;
631         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
632
633         if (port_speed == USB_PHY_PORT_SPEED_LOW) {
634                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
635                 val &= ~(UTMIP_AN_B | UTMIP_HIGHZ_B | UTMIP_AN_C |
636                         UTMIP_HIGHZ_C | UTMIP_AN_D | UTMIP_HIGHZ_D);
637                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
638         } else {
639                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
640                 val &= ~(UTMIP_AP_B | UTMIP_HIGHZ_B | UTMIP_AP_C |
641                         UTMIP_HIGHZ_C | UTMIP_AP_D | UTMIP_HIGHZ_D);
642                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
643         }
644
645         /* turn on pad detectors */
646         val = readl(pmc_base + PMC_USB_AO);
647         val &= ~(USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
648         writel(val, pmc_base + PMC_USB_AO);
649
650         /* Add small delay before usb detectors provide stable line values */
651         mdelay(1);
652
653         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
654         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
655         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
656         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
657
658         phy->remote_wakeup = false;
659
660         /* Turn over pad configuration to PMC  for line wake events*/
661         val = readl(pmc_base + PMC_SLEEP_CFG);
662         val &= ~UTMIP_WAKE_VAL(inst, ~0);
663         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_ANY);
664         val |= UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst);
665         val |= UTMIP_MASTER_ENABLE(inst) | UTMIP_FSLS_USE_PMC(inst);
666         writel(val, pmc_base + PMC_SLEEP_CFG);
667
668         val = readl(base + UTMIP_PMC_WAKEUP0);
669         val |= EVENT_INT_ENB;
670         writel(val, base + UTMIP_PMC_WAKEUP0);
671 }
672
673 static void utmip_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy)
674 {
675         unsigned long val;
676         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
677         unsigned  int inst = phy->inst;
678         void __iomem *base = phy->regs;
679
680         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
681
682         val = readl(pmc_base + PMC_SLEEP_CFG);
683         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
684         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
685         writel(val, pmc_base + PMC_SLEEP_CFG);
686
687         val = readl(pmc_base + PMC_TRIGGERS);
688         val |= UTMIP_CLR_WAKE_ALARM(inst) | UTMIP_CLR_WALK_PTR(inst);
689         writel(val, pmc_base + PMC_TRIGGERS);
690
691         val = readl(base + UTMIP_PMC_WAKEUP0);
692         val &= ~EVENT_INT_ENB;
693         writel(val, base + UTMIP_PMC_WAKEUP0);
694
695         /* Disable PMC master mode by clearing MASTER_EN */
696         val = readl(pmc_base + PMC_SLEEP_CFG);
697         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
698                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
699         writel(val, pmc_base + PMC_SLEEP_CFG);
700
701         val = readl(pmc_base + PMC_TRIGGERS);
702         val &= ~UTMIP_CAP_CFG(inst);
703         writel(val, pmc_base + PMC_TRIGGERS);
704
705         /* turn off pad detectors */
706         val = readl(pmc_base + PMC_USB_AO);
707         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
708         writel(val, pmc_base + PMC_USB_AO);
709
710         phy->remote_wakeup = false;
711 }
712
713 static bool utmi_phy_remotewake_detected(struct tegra_usb_phy *phy)
714 {
715         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
716         void __iomem *base = phy->regs;
717         unsigned  int inst = phy->inst;
718         u32 val;
719
720         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
721         val = readl(base + UTMIP_PMC_WAKEUP0);
722         if (val & EVENT_INT_ENB) {
723                 val = readl(pmc_base + UTMIP_UHSIC_STATUS);
724                 if (UTMIP_WAKE_ALARM(inst) & val) {
725                         val = readl(pmc_base + PMC_SLEEP_CFG);
726                         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
727                         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
728                         writel(val, pmc_base + PMC_SLEEP_CFG);
729
730                         val = readl(pmc_base + PMC_TRIGGERS);
731                         val |= UTMIP_CLR_WAKE_ALARM(inst) |
732                                 UTMIP_CLR_WALK_PTR(inst);
733                         writel(val, pmc_base + PMC_TRIGGERS);
734
735                         val = readl(base + UTMIP_PMC_WAKEUP0);
736                         val &= ~EVENT_INT_ENB;
737                         writel(val, base + UTMIP_PMC_WAKEUP0);
738                         phy->remote_wakeup = true;
739                         return true;
740                 }
741         }
742         return false;
743 }
744
745 static void utmi_phy_enable_trking_data(struct tegra_usb_phy *phy)
746 {
747         void __iomem *base = IO_ADDRESS(TEGRA_USB_BASE);
748         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
749         static bool init_done = false;
750         u32 val;
751
752         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
753
754         /* Should be done only once after system boot */
755         if (init_done)
756                 return;
757
758         clk_enable(phy->utmi_pad_clk);
759         /* Bias pad MASTER_ENABLE=1 */
760         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
761         val |= BIAS_MASTER_PROG_VAL;
762         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
763
764         /* Setting the tracking length time */
765         val = readl(base + UTMIP_BIAS_CFG1);
766         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
767         val |= UTMIP_BIAS_PDTRK_COUNT(5);
768         writel(val, base + UTMIP_BIAS_CFG1);
769
770         /* Bias PDTRK is Shared and MUST be done from USB1 ONLY, PD_TRK=0 */
771         val = readl(base + UTMIP_BIAS_CFG1);
772         val &= ~UTMIP_BIAS_PDTRK_POWERDOWN;
773         writel(val, base + UTMIP_BIAS_CFG1);
774
775         val = readl(base + UTMIP_BIAS_CFG1);
776         val |= UTMIP_BIAS_PDTRK_POWERUP;
777         writel(val, base + UTMIP_BIAS_CFG1);
778
779         /* Wait for 25usec */
780         udelay(25);
781
782         /* Bias pad MASTER_ENABLE=0 */
783         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
784         val &= ~BIAS_MASTER_PROG_VAL;
785         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
786
787         /* Wait for 1usec */
788         udelay(1);
789
790         /* Bias pad MASTER_ENABLE=1 */
791         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
792         val |= BIAS_MASTER_PROG_VAL;
793         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
794
795         /* Read RCTRL and TCTRL from UTMIP space */
796         val = readl(base + UTMIP_BIAS_STS0);
797         utmip_rctrl_val = ffz(UTMIP_RCTRL_VAL(val));
798         utmip_tctrl_val = ffz(UTMIP_TCTRL_VAL(val));
799
800         /* PD_TRK=1 */
801         val = readl(base + UTMIP_BIAS_CFG1);
802         val |= UTMIP_BIAS_PDTRK_POWERDOWN;
803         writel(val, base + UTMIP_BIAS_CFG1);
804
805         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
806         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
807         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
808         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
809         clk_disable(phy->utmi_pad_clk);
810         init_done = true;
811 }
812
813 static void utmip_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy)
814 {
815         unsigned long val;
816         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
817         unsigned  int inst = phy->inst;
818
819         /* power down UTMIP interfaces */
820         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
821         val |= UTMIP_PWR(inst);
822         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
823
824         /* setup sleep walk usb controller */
825         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
826                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
827                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
828                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
829         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
830
831         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
832         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
833         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
834         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
835
836         /* Turn over pad configuration to PMC */
837         val = readl(pmc_base + PMC_SLEEP_CFG);
838         val &= ~UTMIP_WAKE_VAL(inst, ~0);
839         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE) |
840                 UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
841                 UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst);
842         writel(val, pmc_base + PMC_SLEEP_CFG);
843 }
844
845 static void utmip_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
846 {
847         unsigned long val;
848         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
849         unsigned  int inst = phy->inst;
850
851         /* Disable PMC master mode by clearing MASTER_EN */
852         val = readl(pmc_base + PMC_SLEEP_CFG);
853         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
854                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
855         writel(val, pmc_base + PMC_SLEEP_CFG);
856         mdelay(1);
857 }
858
859 static void uhsic_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy)
860 {
861         unsigned long val;
862         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
863
864         /* turn on pad detectors for HSIC*/
865         val = readl(pmc_base + PMC_USB_AO);
866         val |= (HSIC_RESERVED_P0 | HSIC_STOBE_VAL_PD_P0 | HSIC_DATA_VAL_PD_P0);
867         writel(val, pmc_base + PMC_USB_AO);
868
869         /* enable pull downs on HSIC PMC */
870         val = UHSIC_STRB_RPD_A | UHSIC_DATA_RPD_A | UHSIC_STRB_RPD_B |
871                 UHSIC_DATA_RPD_B | UHSIC_STRB_RPD_C | UHSIC_DATA_RPD_C |
872                 UHSIC_STRB_RPD_D | UHSIC_DATA_RPD_D;
873         writel(val, pmc_base + UHSIC_SLEEPWALK_REG);
874
875         /* Turn over pad configuration to PMC */
876         val = readl(pmc_base + PMC_SLEEP_CFG);
877         val &= ~UHSIC_WAKE_VAL_P0(~0);
878         val |= UHSIC_WAKE_VAL_P0(WAKE_VAL_NONE) | UHSIC_MASTER_ENABLE_P0;
879         writel(val, pmc_base + PMC_SLEEP_CFG);
880 }
881
882 static void uhsic_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
883 {
884         unsigned long val;
885         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
886
887         /* turn on pad detectors for HSIC*/
888         val = readl(pmc_base + PMC_USB_AO);
889         val &= ~(HSIC_RESERVED_P0 | HSIC_STOBE_VAL_PD_P0 | HSIC_DATA_VAL_PD_P0);
890         writel(val, pmc_base + PMC_USB_AO);
891
892         /* Disable PMC master mode by clearing MASTER_EN */
893         val = readl(pmc_base + PMC_SLEEP_CFG);
894         val &= ~(UHSIC_MASTER_ENABLE_P0);
895         writel(val, pmc_base + PMC_SLEEP_CFG);
896         mdelay(1);
897 }
898
899 static void usb_phy_power_down_pmc(void)
900 {
901         unsigned long val;
902         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
903
904         /* power down all 3 UTMIP interfaces */
905         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
906         val |= UTMIP_PWR(0) | UTMIP_PWR(1) | UTMIP_PWR(2);
907         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
908
909         /* turn on pad detectors */
910         writel(PMC_POWER_DOWN_MASK, pmc_base + PMC_USB_AO);
911
912         /* setup sleep walk fl all 3 usb controllers */
913         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
914                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
915                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
916                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
917         writel(val, pmc_base + PMC_SLEEPWALK_REG(0));
918         writel(val, pmc_base + PMC_SLEEPWALK_REG(1));
919         writel(val, pmc_base + PMC_SLEEPWALK_REG(2));
920
921         /* enable pull downs on HSIC PMC */
922         val = UHSIC_STRB_RPD_A | UHSIC_DATA_RPD_A | UHSIC_STRB_RPD_B |
923                 UHSIC_DATA_RPD_B | UHSIC_STRB_RPD_C | UHSIC_DATA_RPD_C |
924                 UHSIC_STRB_RPD_D | UHSIC_DATA_RPD_D;
925         writel(val, pmc_base + UHSIC_SLEEPWALK_REG);
926
927         /* Turn over pad configuration to PMC */
928         val = readl(pmc_base + PMC_SLEEP_CFG);
929         val &= ~UTMIP_WAKE_VAL(0, ~0);
930         val &= ~UTMIP_WAKE_VAL(1, ~0);
931         val &= ~UTMIP_WAKE_VAL(2, ~0);
932         val &= ~UHSIC_WAKE_VAL_P0(~0);
933         val |= UTMIP_WAKE_VAL(0, WAKE_VAL_NONE) | UHSIC_WAKE_VAL_P0(WAKE_VAL_NONE) |
934         UTMIP_WAKE_VAL(1, WAKE_VAL_NONE) | UTMIP_WAKE_VAL(2, WAKE_VAL_NONE) |
935         UTMIP_RCTRL_USE_PMC(0) | UTMIP_RCTRL_USE_PMC(1) | UTMIP_RCTRL_USE_PMC(2) |
936         UTMIP_TCTRL_USE_PMC(0) | UTMIP_TCTRL_USE_PMC(1) | UTMIP_TCTRL_USE_PMC(2) |
937         UTMIP_FSLS_USE_PMC(0) | UTMIP_FSLS_USE_PMC(1) | UTMIP_FSLS_USE_PMC(2) |
938         UTMIP_MASTER_ENABLE(0) | UTMIP_MASTER_ENABLE(1) | UTMIP_MASTER_ENABLE(2) |
939         UHSIC_MASTER_ENABLE_P0;
940         writel(val, pmc_base + PMC_SLEEP_CFG);
941 }
942
943 static int usb_phy_bringup_host_controller(struct tegra_usb_phy *phy)
944 {
945         unsigned long val;
946         void __iomem *base = phy->regs;
947
948         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
949         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n",
950                 readl(base + USB_USBSTS), readl(base + USB_PORTSC),
951                                                         phy->port_speed);
952
953         /* Enable Port Power */
954         val = readl(base + USB_PORTSC);
955         val |= USB_PORTSC_PP;
956         writel(val, base + USB_PORTSC);
957         udelay(10);
958
959         /* Check if the phy resume from LP0. When the phy resume from LP0
960          * USB register will be reset.to zero */
961         if (!readl(base + USB_ASYNCLISTADDR)) {
962                 /* Program the field PTC based on the saved speed mode */
963                 val = readl(base + USB_PORTSC);
964                 val &= ~USB_PORTSC_PTC(~0);
965                 if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH)
966                         val |= USB_PORTSC_PTC(5);
967                 else if (phy->port_speed == USB_PHY_PORT_SPEED_FULL)
968                         val |= USB_PORTSC_PTC(6);
969                 else if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
970                         val |= USB_PORTSC_PTC(7);
971                 writel(val, base + USB_PORTSC);
972                 udelay(10);
973
974                 /* Disable test mode by setting PTC field to NORMAL_OP */
975                 val = readl(base + USB_PORTSC);
976                 val &= ~USB_PORTSC_PTC(~0);
977                 writel(val, base + USB_PORTSC);
978                 udelay(10);
979         }
980
981         /* Poll until CCS is enabled */
982         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
983                                                  USB_PORTSC_CCS, 2000)) {
984                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
985         }
986
987         /* Poll until PE is enabled */
988         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_PE,
989                                                  USB_PORTSC_PE, 2000)) {
990                 pr_err("%s: timeout waiting for USB_PORTSC_PE\n", __func__);
991         }
992
993         /* Clear the PCI status, to avoid an interrupt taken upon resume */
994         val = readl(base + USB_USBSTS);
995         val |= USB_USBSTS_PCI;
996         writel(val, base + USB_USBSTS);
997
998         /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
999         val = readl(base + USB_PORTSC);
1000         if ((val & USB_PORTSC_PP) && (val & USB_PORTSC_PE)) {
1001                 val |= USB_PORTSC_SUSP;
1002                 writel(val, base + USB_PORTSC);
1003                 /* Need a 4ms delay before the controller goes to suspend */
1004                 mdelay(4);
1005
1006                 /* Wait until port suspend completes */
1007                 if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_SUSP,
1008                                                  USB_PORTSC_SUSP, 1000)) {
1009                         pr_err("%s: timeout waiting for PORT_SUSPEND\n",
1010                                                                 __func__);
1011                 }
1012         }
1013
1014         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1015                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1016         return 0;
1017 }
1018
1019 static void usb_phy_wait_for_sof(struct tegra_usb_phy *phy)
1020 {
1021         unsigned long val;
1022         void __iomem *base = phy->regs;
1023
1024         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1025
1026         val = readl(base + USB_USBSTS);
1027         writel(val, base + USB_USBSTS);
1028         udelay(20);
1029         /* wait for two SOFs */
1030         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1031                 USB_USBSTS_SRI, 2500))
1032                 pr_err("%s: timeout waiting for SOF\n", __func__);
1033
1034         val = readl(base + USB_USBSTS);
1035         writel(val, base + USB_USBSTS);
1036         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI, 0, 2500))
1037                 pr_err("%s: timeout waiting for SOF\n", __func__);
1038
1039         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1040                         USB_USBSTS_SRI, 2500))
1041                 pr_err("%s: timeout waiting for SOF\n", __func__);
1042
1043         udelay(20);
1044 }
1045
1046 static unsigned int utmi_phy_xcvr_setup_value(struct tegra_usb_phy *phy)
1047 {
1048         struct tegra_utmi_config *cfg = &phy->pdata->u_cfg.utmi;
1049         signed long val;
1050
1051         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1052
1053         if (cfg->xcvr_use_fuses) {
1054                 val = FUSE_USB_CALIB_XCVR_SETUP(
1055                                 tegra_fuse_readl(FUSE_USB_CALIB_0));
1056                 if (cfg->xcvr_setup_offset <= UTMIP_XCVR_MAX_OFFSET)
1057                         val = val + cfg->xcvr_setup_offset;
1058
1059                 if (val > UTMIP_XCVR_SETUP_MAX_VALUE) {
1060                         val = UTMIP_XCVR_SETUP_MAX_VALUE;
1061                         pr_info("%s: reset XCVR_SETUP to max value\n",
1062                                  __func__);
1063                 } else if (val < UTMIP_XCVR_SETUP_MIN_VALUE) {
1064                         val = UTMIP_XCVR_SETUP_MIN_VALUE;
1065                         pr_info("%s: reset XCVR_SETUP to min value\n",
1066                                  __func__);
1067                 }
1068         } else {
1069                 val = cfg->xcvr_setup;
1070         }
1071
1072         return (unsigned int) val;
1073 }
1074
1075 static int utmi_phy_open(struct tegra_usb_phy *phy)
1076 {
1077         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1078         unsigned long parent_rate, val;
1079         int i;
1080
1081         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1082
1083         phy->utmi_pad_clk = clk_get_sys("utmip-pad", NULL);
1084         if (IS_ERR(phy->utmi_pad_clk)) {
1085                 pr_err("%s: can't get utmip pad clock\n", __func__);
1086                 return PTR_ERR(phy->utmi_pad_clk);
1087         }
1088
1089         phy->utmi_xcvr_setup = utmi_phy_xcvr_setup_value(phy);
1090
1091         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
1092         for (i = 0; i < ARRAY_SIZE(utmip_freq_table); i++) {
1093                 if (utmip_freq_table[i].freq == parent_rate) {
1094                         phy->freq = &utmip_freq_table[i];
1095                         break;
1096                 }
1097         }
1098         if (!phy->freq) {
1099                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
1100                 return -EINVAL;
1101         }
1102
1103         /* Power-up the VBUS detector for UTMIP PHY */
1104         val = readl(pmc_base + PMC_USB_AO);
1105         val &= ~(PMC_USB_AO_VBUS_WAKEUP_PD_P0 | PMC_USB_AO_ID_PD_P0);
1106         writel((val | PMC_USB_AO_PD_P2), (pmc_base + PMC_USB_AO));
1107
1108         utmip_powerup_pmc_wake_detect(phy);
1109
1110         return 0;
1111 }
1112
1113 static void utmi_phy_close(struct tegra_usb_phy *phy)
1114 {
1115         unsigned long val;
1116         void __iomem *base = phy->regs;
1117
1118         DBG("%s inst:[%d]\n", __func__, phy->inst);
1119
1120         /* Disable PHY clock valid interrupts while going into suspend*/
1121         if (phy->pdata->u_data.host.hot_plug) {
1122                 val = readl(base + USB_SUSP_CTRL);
1123                 val &= ~USB_PHY_CLK_VALID_INT_ENB;
1124                 writel(val, base + USB_SUSP_CTRL);
1125         }
1126
1127         val = readl(base + USB_PORTSC);
1128         val |= USB_PORTSC_WKCN;
1129         writel(val, base + USB_PORTSC);
1130
1131         clk_put(phy->utmi_pad_clk);
1132 }
1133
1134 static int utmi_phy_pad_power_on(struct tegra_usb_phy *phy)
1135 {
1136         unsigned long val, flags;
1137         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1138
1139         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1140
1141         clk_enable(phy->utmi_pad_clk);
1142
1143         spin_lock_irqsave(&utmip_pad_lock, flags);
1144         utmip_pad_count++;
1145
1146         val = readl(pad_base + UTMIP_BIAS_CFG0);
1147         val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
1148         val |= UTMIP_HSSQUELCH_LEVEL(0x2) | UTMIP_HSDISCON_LEVEL(0x1) |
1149                 UTMIP_HSDISCON_LEVEL_MSB;
1150         writel(val, pad_base + UTMIP_BIAS_CFG0);
1151
1152         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1153
1154         clk_disable(phy->utmi_pad_clk);
1155
1156         return 0;
1157 }
1158
1159 static int utmi_phy_pad_power_off(struct tegra_usb_phy *phy)
1160 {
1161         unsigned long val, flags;
1162         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1163
1164         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1165
1166         clk_enable(phy->utmi_pad_clk);
1167         spin_lock_irqsave(&utmip_pad_lock, flags);
1168
1169         if (!utmip_pad_count) {
1170                 pr_err("%s: utmip pad already powered off\n", __func__);
1171                 goto out;
1172         }
1173         if (--utmip_pad_count == 0) {
1174                 val = readl(pad_base + UTMIP_BIAS_CFG0);
1175                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
1176                 val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) | UTMIP_HSDISCON_LEVEL(~0) |
1177                         UTMIP_HSDISCON_LEVEL_MSB);
1178                 writel(val, pad_base + UTMIP_BIAS_CFG0);
1179         }
1180 out:
1181         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1182         clk_disable(phy->utmi_pad_clk);
1183
1184         return 0;
1185 }
1186
1187 static int utmi_phy_irq(struct tegra_usb_phy *phy)
1188 {
1189         void __iomem *base = phy->regs;
1190         unsigned long val = 0;
1191
1192         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1193         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1194                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1195         DBG("USB_USBMODE[0x%x] USB_USBCMD[0x%x]\n",
1196                         readl(base + USB_USBMODE), readl(base + USB_USBCMD));
1197
1198         /* check if there is any remote wake event */
1199         if (utmi_phy_remotewake_detected(phy))
1200                 pr_info("%s: utmip remote wake detected\n", __func__);
1201
1202         if (phy->pdata->u_data.host.hot_plug) {
1203                 val = readl(base + USB_SUSP_CTRL);
1204                 if ((val  & USB_PHY_CLK_VALID_INT_STS)) {
1205                         val &= ~USB_PHY_CLK_VALID_INT_ENB |
1206                                         USB_PHY_CLK_VALID_INT_STS;
1207                         writel(val , (base + USB_SUSP_CTRL));
1208                         pr_info("%s: usb device plugged-in\n", __func__);
1209                         val = readl(base + USB_USBSTS);
1210                         if (!(val  & USB_USBSTS_PCI))
1211                                 return IRQ_NONE;
1212                         val = readl(base + USB_PORTSC);
1213                         val &= ~(USB_PORTSC_WKCN | USB_PORTSC_RWC_BITS);
1214                         writel(val , (base + USB_PORTSC));
1215                 }
1216         }
1217
1218         return IRQ_HANDLED;
1219 }
1220
1221 static int utmi_phy_post_resume(struct tegra_usb_phy *phy)
1222 {
1223         unsigned long val;
1224         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1225         unsigned  int inst = phy->inst;
1226
1227         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1228         val = readl(pmc_base + PMC_SLEEP_CFG);
1229         /* if PMC is not disabled by now then disable it */
1230         if (val & UTMIP_MASTER_ENABLE(inst)) {
1231                 utmip_phy_disable_pmc_bus_ctrl(phy);
1232         }
1233
1234         return 0;
1235 }
1236
1237 static int utmi_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1238 {
1239         unsigned long val;
1240         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1241         unsigned  int inst = phy->inst;
1242
1243         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1244         val = readl(pmc_base + PMC_SLEEP_CFG);
1245         if (val & UTMIP_MASTER_ENABLE(inst)) {
1246                 if (!remote_wakeup)
1247                         utmip_phy_disable_pmc_bus_ctrl(phy);
1248         }
1249
1250         return 0;
1251 }
1252
1253 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
1254 {
1255         unsigned long val;
1256         void __iomem *base = phy->regs;
1257
1258         DBG("%s(%d) inst:[%d] BEGIN\n", __func__, __LINE__, phy->inst);
1259         if (!phy->phy_clk_on) {
1260                 DBG("%s(%d) inst:[%d] phy clk is already off\n",
1261                                         __func__, __LINE__, phy->inst);
1262                 return 0;
1263         }
1264
1265         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1266                 utmip_powerdown_pmc_wake_detect(phy);
1267
1268                 val = readl(base + USB_SUSP_CTRL);
1269                 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
1270                 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
1271                 writel(val, base + USB_SUSP_CTRL);
1272
1273                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1274                 val |= UTMIP_PD_CHRG;
1275                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1276         } else {
1277                 utmip_setup_pmc_wake_detect(phy);
1278         }
1279
1280         if (!phy->pdata->u_data.host.hot_plug) {
1281                 val = readl(base + UTMIP_XCVR_CFG0);
1282                 val |= (UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
1283                          UTMIP_FORCE_PDZI_POWERDOWN);
1284                 writel(val, base + UTMIP_XCVR_CFG0);
1285         }
1286
1287         val = readl(base + UTMIP_XCVR_CFG1);
1288         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1289                    UTMIP_FORCE_PDDR_POWERDOWN;
1290         writel(val, base + UTMIP_XCVR_CFG1);
1291
1292         val = readl(base + UTMIP_BIAS_CFG1);
1293         val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
1294         writel(val, base + UTMIP_BIAS_CFG1);
1295
1296         utmi_phy_pad_power_off(phy);
1297
1298         phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
1299                         HOSTPC1_DEVLC_PSPD_MASK;
1300
1301         if (phy->pdata->u_data.host.hot_plug) {
1302                 bool enable_hotplug = true;
1303                 /* if it is OTG port then make sure to enable hot-plug feature
1304                    only if host adaptor is connected, i.e id is low */
1305                 if (phy->pdata->port_otg) {
1306                         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1307                         enable_hotplug = (val & USB_ID_STATUS) ? false : true;
1308                 }
1309                 if (enable_hotplug) {
1310                         val = readl(base + USB_PORTSC);
1311                         val |= USB_PORTSC_WKCN;
1312                         writel(val, base + USB_PORTSC);
1313
1314                         val = readl(base + USB_SUSP_CTRL);
1315                         val |= USB_PHY_CLK_VALID_INT_ENB;
1316                         writel(val, base + USB_SUSP_CTRL);
1317                 } else {
1318                         /* Disable PHY clock valid interrupts while going into suspend*/
1319                         val = readl(base + USB_SUSP_CTRL);
1320                         val &= ~USB_PHY_CLK_VALID_INT_ENB;
1321                         writel(val, base + USB_SUSP_CTRL);
1322                 }
1323         }
1324
1325         if (phy->inst == 0) {
1326                         val = readl(base + USB_SUSP_CTRL);
1327                         val |= UTMIP_RESET;
1328                         writel(val, base + USB_SUSP_CTRL);
1329         }
1330
1331         val = readl(base + HOSTPC1_DEVLC);
1332         val |= HOSTPC1_DEVLC_PHCD;
1333         writel(val, base + HOSTPC1_DEVLC);
1334
1335         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
1336                                                                 0, 2500))
1337                 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
1338
1339         phy->phy_clk_on = false;
1340         phy->hw_accessible = false;
1341
1342         DBG("%s(%d) inst:[%d] END\n", __func__, __LINE__, phy->inst);
1343
1344         return 0;
1345 }
1346
1347
1348 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
1349 {
1350         unsigned long val;
1351         void __iomem *base = phy->regs;
1352         struct tegra_utmi_config *config = &phy->pdata->u_cfg.utmi;
1353
1354         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1355         if (phy->phy_clk_on) {
1356                 DBG("%s(%d) inst:[%d] phy clk is already On\n",
1357                                         __func__, __LINE__, phy->inst);
1358                 return 0;
1359         }
1360         val = readl(base + USB_SUSP_CTRL);
1361         val |= UTMIP_RESET;
1362         writel(val, base + USB_SUSP_CTRL);
1363
1364         val = readl(base + UTMIP_TX_CFG0);
1365         val |= UTMIP_FS_PREABMLE_J;
1366         writel(val, base + UTMIP_TX_CFG0);
1367
1368         val = readl(base + UTMIP_HSRX_CFG0);
1369         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
1370         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
1371         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
1372         writel(val, base + UTMIP_HSRX_CFG0);
1373
1374         val = readl(base + UTMIP_HSRX_CFG1);
1375         val &= ~UTMIP_HS_SYNC_START_DLY(~0);
1376         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
1377         writel(val, base + UTMIP_HSRX_CFG1);
1378
1379         val = readl(base + UTMIP_DEBOUNCE_CFG0);
1380         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
1381         val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
1382         writel(val, base + UTMIP_DEBOUNCE_CFG0);
1383
1384         val = readl(base + UTMIP_MISC_CFG0);
1385         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
1386         writel(val, base + UTMIP_MISC_CFG0);
1387
1388         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1389                 val = readl(base + USB_SUSP_CTRL);
1390                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
1391                 writel(val, base + USB_SUSP_CTRL);
1392
1393                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1394                 val &= ~UTMIP_PD_CHRG;
1395                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1396         } else {
1397                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1398                 val |= UTMIP_PD_CHRG;
1399                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1400         }
1401
1402         utmi_phy_pad_power_on(phy);
1403
1404         val = readl(base + UTMIP_XCVR_CFG0);
1405         val &= ~(UTMIP_XCVR_LSBIAS_SEL | UTMIP_FORCE_PD_POWERDOWN |
1406                  UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN |
1407                  UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_LSFSLEW(~0) |
1408                  UTMIP_XCVR_LSRSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
1409         val |= UTMIP_XCVR_SETUP(phy->utmi_xcvr_setup);
1410         val |= UTMIP_XCVR_SETUP_MSB(XCVR_SETUP_MSB_CALIB(phy->utmi_xcvr_setup));
1411         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
1412         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
1413         val |= UTMIP_XCVR_HSSLEW_MSB(0x8);
1414         writel(val, base + UTMIP_XCVR_CFG0);
1415
1416         val = readl(base + UTMIP_XCVR_CFG1);
1417         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1418                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
1419         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
1420         writel(val, base + UTMIP_XCVR_CFG1);
1421
1422         val = readl(base + UTMIP_BIAS_CFG1);
1423         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
1424         val |= UTMIP_BIAS_PDTRK_COUNT(phy->freq->pdtrk_count);
1425         writel(val, base + UTMIP_BIAS_CFG1);
1426
1427         val = readl(base + UTMIP_SPARE_CFG0);
1428         val &= ~FUSE_SETUP_SEL;
1429         val |= FUSE_ATERM_SEL;
1430         writel(val, base + UTMIP_SPARE_CFG0);
1431
1432         val = readl(base + USB_SUSP_CTRL);
1433         val |= UTMIP_PHY_ENABLE;
1434         writel(val, base + USB_SUSP_CTRL);
1435
1436         val = readl(base + USB_SUSP_CTRL);
1437         val &= ~UTMIP_RESET;
1438         writel(val, base + USB_SUSP_CTRL);
1439
1440         val = readl(base + HOSTPC1_DEVLC);
1441         val &= ~HOSTPC1_DEVLC_PHCD;
1442         writel(val, base + HOSTPC1_DEVLC);
1443
1444         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1445                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500))
1446                 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
1447
1448         utmi_phy_enable_trking_data(phy);
1449
1450         if (phy->inst == 2)
1451                 writel(0, base + ICUSB_CTRL);
1452
1453         val = readl(base + USB_USBMODE);
1454         val &= ~USB_USBMODE_MASK;
1455         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST)
1456                 val |= USB_USBMODE_HOST;
1457         else
1458                 val |= USB_USBMODE_DEVICE;
1459         writel(val, base + USB_USBMODE);
1460
1461         val = readl(base + HOSTPC1_DEVLC);
1462         val &= ~HOSTPC1_DEVLC_PTS(~0);
1463         val |= HOSTPC1_DEVLC_STS;
1464         writel(val, base + HOSTPC1_DEVLC);
1465
1466         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE)
1467                 utmip_powerup_pmc_wake_detect(phy);
1468         phy->phy_clk_on = true;
1469         phy->hw_accessible = true;
1470         DBG("%s(%d) End\n", __func__, __LINE__);
1471
1472         return 0;
1473 }
1474
1475 static void utmi_phy_restore_start(struct tegra_usb_phy *phy)
1476 {
1477         unsigned long val;
1478         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1479         int inst = phy->inst;
1480
1481         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1482         val = readl(pmc_base + UTMIP_UHSIC_STATUS);
1483         /* check whether we wake up from the remote resume */
1484         if (UTMIP_WALK_PTR_VAL(inst) & val) {
1485                 phy->remote_wakeup = true;
1486         } else {
1487                 if (!((UTMIP_USBON_VAL(phy->inst) |
1488                         UTMIP_USBOP_VAL(phy->inst)) & val)) {
1489                                 utmip_phy_disable_pmc_bus_ctrl(phy);
1490                 }
1491         }
1492 }
1493
1494 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
1495 {
1496         unsigned long val;
1497         void __iomem *base = phy->regs;
1498         int wait_time_us = 3000; /* FPR should be set by this time */
1499
1500         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1501         /* check whether we wake up from the remote resume */
1502         if (phy->remote_wakeup) {
1503                 /* wait until FPR bit is set automatically on remote resume */
1504                 do {
1505                         val = readl(base + USB_PORTSC);
1506                         udelay(1);
1507                         if (wait_time_us == 0)
1508                                 return;
1509                         wait_time_us--;
1510                 } while (!(val & USB_PORTSC_RESUME));
1511                 /* wait for 25 ms to port resume complete */
1512                 msleep(25);
1513                 /* disable PMC master control */
1514                 utmip_phy_disable_pmc_bus_ctrl(phy);
1515
1516                 /* Clear PCI and SRI bits to avoid an interrupt upon resume */
1517                 val = readl(base + USB_USBSTS);
1518                 writel(val, base + USB_USBSTS);
1519                 /* wait to avoid SOF if there is any */
1520                 if (usb_phy_reg_status_wait(base + USB_USBSTS,
1521                         USB_USBSTS_SRI, USB_USBSTS_SRI, 2500) < 0) {
1522                         pr_err("%s: timeout waiting for SOF\n", __func__);
1523                 }
1524                 utmi_phy_post_resume(phy);
1525         }
1526 }
1527
1528 static int utmi_phy_resume(struct tegra_usb_phy *phy)
1529 {
1530         int status = 0;
1531         unsigned long val;
1532         void __iomem *base = phy->regs;
1533
1534         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1535         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) {
1536                 if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
1537                         utmi_phy_restore_start(phy);
1538                         usb_phy_bringup_host_controller(phy);
1539                         utmi_phy_restore_end(phy);
1540                 } else {
1541                         /* device is plugged in when system is in LP0 */
1542                         /* bring up the controller from LP0*/
1543                         val = readl(base + USB_USBCMD);
1544                         val |= USB_CMD_RESET;
1545                         writel(val, base + USB_USBCMD);
1546
1547                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1548                                 USB_CMD_RESET, 0, 2500) < 0) {
1549                                 pr_err("%s: timeout waiting for reset\n", __func__);
1550                         }
1551
1552                         val = readl(base + USB_USBMODE);
1553                         val &= ~USB_USBMODE_MASK;
1554                         val |= USB_USBMODE_HOST;
1555                         writel(val, base + USB_USBMODE);
1556
1557                         val = readl(base + HOSTPC1_DEVLC);
1558                         val &= ~HOSTPC1_DEVLC_PTS(~0);
1559                         val |= HOSTPC1_DEVLC_STS;
1560                         writel(val, base + HOSTPC1_DEVLC);
1561
1562                         writel(USB_USBCMD_RS, base + USB_USBCMD);
1563
1564                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1565                                 USB_USBCMD_RS, USB_USBCMD_RS, 2500) < 0) {
1566                                 pr_err("%s: timeout waiting for run bit\n", __func__);
1567                         }
1568
1569                         /* Enable Port Power */
1570                         val = readl(base + USB_PORTSC);
1571                         val |= USB_PORTSC_PP;
1572                         writel(val, base + USB_PORTSC);
1573                         udelay(10);
1574
1575                         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1576                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1577                 }
1578         }
1579
1580         return status;
1581 }
1582
1583 static bool utmi_phy_charger_detect(struct tegra_usb_phy *phy)
1584 {
1585         unsigned long val;
1586         void __iomem *base = phy->regs;
1587         bool status;
1588
1589         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1590         if (phy->pdata->op_mode != TEGRA_USB_OPMODE_DEVICE) {
1591                 /* Charger detection is not there for ULPI
1592                  * return Charger not available */
1593                 return false;
1594         }
1595
1596         /* Enable charger detection logic */
1597         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1598         val |= UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN;
1599         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1600
1601         /* Source should be on for 100 ms as per USB charging spec */
1602         msleep(TDP_SRC_ON_MS);
1603
1604         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1605         /* If charger is not connected disable the interrupt */
1606         val &= ~VDAT_DET_INT_EN;
1607         val |= VDAT_DET_CHG_DET;
1608         writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
1609
1610         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1611         if (val & VDAT_DET_STS)
1612                 status = true;
1613         else
1614                 status = false;
1615
1616         /* Disable charger detection logic */
1617         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1618         val &= ~(UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN);
1619         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1620
1621         /* Delay of 40 ms before we pull the D+ as per battery charger spec */
1622         msleep(TDPSRC_CON_MS);
1623
1624         return status;
1625 }
1626
1627 static int uhsic_phy_open(struct tegra_usb_phy *phy)
1628 {
1629         unsigned long parent_rate;
1630         int i;
1631
1632         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1633         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
1634         for (i = 0; i < ARRAY_SIZE(uhsic_freq_table); i++) {
1635                 if (uhsic_freq_table[i].freq == parent_rate) {
1636                         phy->freq = &uhsic_freq_table[i];
1637                         break;
1638                 }
1639         }
1640         if (!phy->freq) {
1641                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
1642                 return -EINVAL;
1643         }
1644
1645         uhsic_powerup_pmc_wake_detect(phy);
1646
1647         return 0;
1648 }
1649
1650 static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
1651 {
1652         unsigned long val;
1653         void __iomem *base = phy->regs;
1654         struct tegra_hsic_config *config = &phy->pdata->u_cfg.hsic;
1655
1656         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1657
1658         utmip_powerup_pmc_wake_detect(phy);
1659
1660         if (phy->phy_clk_on) {
1661                 DBG("%s(%d) inst:[%d] phy clk is already On\n",
1662                                         __func__, __LINE__, phy->inst);
1663                 return 0;
1664         }
1665
1666         val = readl(base + UHSIC_PADS_CFG1);
1667         val &= ~(UHSIC_PD_BG | UHSIC_PD_TX | UHSIC_PD_TRK | UHSIC_PD_RX |
1668                         UHSIC_PD_ZI | UHSIC_RPD_DATA | UHSIC_RPD_STROBE);
1669         val |= UHSIC_RX_SEL;
1670         writel(val, base + UHSIC_PADS_CFG1);
1671         udelay(2);
1672
1673         val = readl(base + USB_SUSP_CTRL);
1674         val |= UHSIC_RESET;
1675         writel(val, base + USB_SUSP_CTRL);
1676         udelay(30);
1677
1678         val = readl(base + USB_SUSP_CTRL);
1679         val |= UHSIC_PHY_ENABLE;
1680         writel(val, base + USB_SUSP_CTRL);
1681
1682         val = readl(base + UHSIC_HSRX_CFG0);
1683         val |= UHSIC_IDLE_WAIT(config->idle_wait_delay);
1684         val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(config->elastic_underrun_limit);
1685         val |= UHSIC_ELASTIC_OVERRUN_LIMIT(config->elastic_overrun_limit);
1686         writel(val, base + UHSIC_HSRX_CFG0);
1687
1688         val = readl(base + UHSIC_HSRX_CFG1);
1689         val |= UHSIC_HS_SYNC_START_DLY(config->sync_start_delay);
1690         writel(val, base + UHSIC_HSRX_CFG1);
1691
1692         /* WAR HSIC TX */
1693         val = readl(base + UHSIC_TX_CFG0);
1694         val &= ~UHSIC_HS_READY_WAIT_FOR_VALID;
1695         writel(val, base + UHSIC_TX_CFG0);
1696
1697         val = readl(base + UHSIC_MISC_CFG0);
1698         val |= UHSIC_SUSPEND_EXIT_ON_EDGE;
1699         /* Disable generic bus reset, to allow AP30 specific bus reset*/
1700         val |= UHSIC_DISABLE_BUSRESET;
1701         writel(val, base + UHSIC_MISC_CFG0);
1702
1703         val = readl(base + UHSIC_MISC_CFG1);
1704         val |= UHSIC_PLLU_STABLE_COUNT(phy->freq->stable_count);
1705         writel(val, base + UHSIC_MISC_CFG1);
1706
1707         val = readl(base + UHSIC_PLL_CFG1);
1708         val |= UHSIC_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
1709         val |= UHSIC_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count);
1710         writel(val, base + UHSIC_PLL_CFG1);
1711
1712         val = readl(base + USB_SUSP_CTRL);
1713         val &= ~(UHSIC_RESET);
1714         writel(val, base + USB_SUSP_CTRL);
1715         udelay(2);
1716
1717         val = readl(base + USB_USBMODE);
1718         val |= USB_USBMODE_HOST;
1719         writel(val, base + USB_USBMODE);
1720
1721         /* Change the USB controller PHY type to HSIC */
1722         val = readl(base + HOSTPC1_DEVLC);
1723         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
1724         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
1725         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
1726         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
1727         writel(val, base + HOSTPC1_DEVLC);
1728
1729         val = readl(base + USB_TXFILLTUNING);
1730         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
1731                 val = USB_FIFO_TXFILL_THRES(0x10);
1732                 writel(val, base + USB_TXFILLTUNING);
1733         }
1734
1735         val = readl(base + USB_PORTSC);
1736         val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN);
1737         writel(val, base + USB_PORTSC);
1738
1739         val = readl(base + UHSIC_PADS_CFG0);
1740         val &= ~(UHSIC_TX_RTUNEN);
1741         /* set Rtune impedance to 50 ohm */
1742         val |= UHSIC_TX_RTUNE(8);
1743         writel(val, base + UHSIC_PADS_CFG0);
1744
1745         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1746                                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500)) {
1747                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
1748                 return -ETIMEDOUT;
1749         }
1750
1751         phy->phy_clk_on = true;
1752         phy->hw_accessible = true;
1753
1754         return 0;
1755 }
1756
1757 static int uhsic_phy_power_off(struct tegra_usb_phy *phy)
1758 {
1759         unsigned long val;
1760         void __iomem *base = phy->regs;
1761
1762         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1763         if (!phy->phy_clk_on) {
1764                 DBG("%s(%d) inst:[%d] phy clk is already off\n",
1765                                         __func__, __LINE__, phy->inst);
1766                 return 0;
1767         }
1768
1769         val = readl(base + UHSIC_PADS_CFG1);
1770         val &= ~UHSIC_RPU_STROBE;
1771         val |= UHSIC_RPD_STROBE;
1772         writel(val, base + UHSIC_PADS_CFG1);
1773
1774         val = readl(base + USB_SUSP_CTRL);
1775         val |= UHSIC_RESET;
1776         writel(val, base + USB_SUSP_CTRL);
1777         udelay(30);
1778
1779         utmip_powerdown_pmc_wake_detect(phy);
1780
1781         phy->phy_clk_on = false;
1782         phy->hw_accessible = false;
1783
1784         return 0;
1785 }
1786
1787 static int uhsic_phy_bus_port_power(struct tegra_usb_phy *phy)
1788 {
1789         unsigned long val;
1790         void __iomem *base = phy->regs;
1791
1792         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1793         val = readl(base + UHSIC_STAT_CFG0);
1794         val &= ~UHSIC_CONNECT_DETECT;
1795         writel(val, base + UHSIC_STAT_CFG0);
1796
1797         val = readl(base + USB_USBMODE);
1798         val |= USB_USBMODE_HOST;
1799         writel(val, base + USB_USBMODE);
1800
1801         /* Change the USB controller PHY type to HSIC */
1802         val = readl(base + HOSTPC1_DEVLC);
1803         val &= ~(HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK));
1804         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
1805         val &= ~(HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK));
1806         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
1807         writel(val, base + HOSTPC1_DEVLC);
1808
1809         val = readl(base + UHSIC_MISC_CFG0);
1810         val |= UHSIC_DETECT_SHORT_CONNECT;
1811         writel(val, base + UHSIC_MISC_CFG0);
1812         udelay(1);
1813
1814         val = readl(base + UHSIC_MISC_CFG0);
1815         val |= UHSIC_FORCE_XCVR_MODE;
1816         writel(val, base + UHSIC_MISC_CFG0);
1817
1818         val = readl(base + UHSIC_PADS_CFG1);
1819         val &= ~UHSIC_RPD_STROBE;
1820         /* safe to enable RPU on STROBE at all times during idle */
1821         val |= UHSIC_RPU_STROBE;
1822         writel(val, base + UHSIC_PADS_CFG1);
1823
1824         val = readl(base + USB_USBCMD);
1825         val &= ~USB_USBCMD_RS;
1826         writel(val, base + USB_USBCMD);
1827
1828         if (usb_phy_reg_status_wait(base + UHSIC_STAT_CFG0,
1829                         UHSIC_CONNECT_DETECT, UHSIC_CONNECT_DETECT, 25000)) {
1830                 pr_err("%s: timeout waiting for UHSIC_CONNECT_DETECT\n",
1831                                                                 __func__);
1832                 return -ETIMEDOUT;
1833         }
1834
1835         return 0;
1836 }
1837
1838 static int uhsic_phy_bus_reset(struct tegra_usb_phy *phy)
1839 {
1840         unsigned long val;
1841         void __iomem *base = phy->regs;
1842
1843         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1844
1845         /* Change the USB controller PHY type to HSIC */
1846         val = readl(base + HOSTPC1_DEVLC);
1847         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
1848         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
1849         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
1850         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
1851         writel(val, base + HOSTPC1_DEVLC);
1852         /* wait here, otherwise HOSTPC1_DEVLC_PSPD will timeout */
1853         mdelay(5);
1854
1855         val = readl(base + USB_PORTSC);
1856         val |= USB_PORTSC_PTC(5);
1857         writel(val, base + USB_PORTSC);
1858         udelay(2);
1859
1860         val = readl(base + USB_PORTSC);
1861         val &= ~(USB_PORTSC_PTC(~0));
1862         writel(val, base + USB_PORTSC);
1863         udelay(2);
1864
1865         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_LS(0),
1866                                                  0, 2000)) {
1867                 pr_err("%s: timeout waiting for USB_PORTSC_LS\n", __func__);
1868                 return -ETIMEDOUT;
1869         }
1870
1871         /* Poll until CCS is enabled */
1872         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
1873                                                  USB_PORTSC_CCS, 2000)) {
1874                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
1875                 return -ETIMEDOUT;
1876         }
1877
1878         if (usb_phy_reg_status_wait(base + HOSTPC1_DEVLC,
1879                         HOSTPC1_DEVLC_PSPD(2),
1880                         HOSTPC1_DEVLC_PSPD(2), 2000) < 0) {
1881                 pr_err("%s: timeout waiting hsic high speed configuration\n",
1882                                                 __func__);
1883                         return -ETIMEDOUT;
1884         }
1885
1886         val = readl(base + USB_USBCMD);
1887         val &= ~USB_USBCMD_RS;
1888         writel(val, base + USB_USBCMD);
1889
1890         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
1891                                                  USB_USBSTS_HCH, 2000)) {
1892                 pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
1893                 return -ETIMEDOUT;
1894         }
1895
1896         val = readl(base + UHSIC_PADS_CFG1);
1897         val &= ~UHSIC_RPU_STROBE;
1898         val |= UHSIC_RPD_STROBE;
1899         writel(val, base + UHSIC_PADS_CFG1);
1900
1901         mdelay(50);
1902
1903         val = readl(base + UHSIC_PADS_CFG1);
1904         val &= ~UHSIC_RPD_STROBE;
1905         val |= UHSIC_RPU_STROBE;
1906         writel(val, base + UHSIC_PADS_CFG1);
1907
1908         val = readl(base + USB_USBCMD);
1909         val |= USB_USBCMD_RS;
1910         writel(val, base + USB_USBCMD);
1911
1912         val = readl(base + UHSIC_PADS_CFG1);
1913         val &= ~UHSIC_RPU_STROBE;
1914         writel(val, base + UHSIC_PADS_CFG1);
1915
1916         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
1917                                                  USB_USBCMD_RS, 2000)) {
1918                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
1919                 return -ETIMEDOUT;
1920         }
1921
1922         return 0;
1923 }
1924
1925
1926 static int uhsic_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1927 {
1928         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1929
1930         usb_phy_wait_for_sof(phy);
1931
1932         return 0;
1933 }
1934
1935 static int uhsic_phy_resume(struct tegra_usb_phy *phy)
1936 {
1937         void __iomem *base = phy->regs;
1938         unsigned long val;
1939
1940         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1941
1942         /* Check if the phy resume from LP0. When the phy resume from LP0
1943          * USB register will be reset.to zero */
1944         if (!readl(base + USB_ASYNCLISTADDR)) {
1945
1946                 val = readl(base + USB_USBCMD);
1947                 val |= USB_CMD_RESET;
1948                 writel(val, base + USB_USBCMD);
1949
1950                 if (usb_phy_reg_status_wait(base + USB_USBCMD,
1951                         USB_CMD_RESET, 0, 2500) < 0) {
1952                         pr_err("%s: timeout waiting for reset\n", __func__);
1953                 }
1954
1955                 val = readl(base + USB_USBMODE);
1956                 val &= ~USB_USBMODE_MASK;
1957                 val |= USB_USBMODE_HOST;
1958                 writel(val, base + USB_USBMODE);
1959
1960                 /* Enable Port Power */
1961                 val = readl(base + USB_PORTSC);
1962                 val |= USB_PORTSC_PP;
1963                 writel(val, base + USB_PORTSC);
1964                 udelay(10);
1965
1966                 DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1967                 readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1968
1969                 uhsic_phy_bus_port_power(phy);
1970         }
1971
1972         return 0;
1973 }
1974
1975 static int uhsic_phy_post_resume(struct tegra_usb_phy *phy)
1976 {
1977         unsigned long val;
1978         void __iomem *base = phy->regs;
1979
1980         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1981         val = readl(base + USB_TXFILLTUNING);
1982         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
1983                 val = USB_FIFO_TXFILL_THRES(0x10);
1984                 writel(val, base + USB_TXFILLTUNING);
1985         }
1986
1987         return 0;
1988 }
1989
1990 static void ulpi_set_trimmer(struct tegra_usb_phy *phy)
1991 {
1992         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
1993         void __iomem *base = phy->regs;
1994         unsigned long val;
1995
1996         val = ULPI_DATA_TRIMMER_SEL(config->data_trimmer);
1997         val |= ULPI_STPDIRNXT_TRIMMER_SEL(config->stpdirnxt_trimmer);
1998         val |= ULPI_DIR_TRIMMER_SEL(config->dir_trimmer);
1999         writel(val, base + ULPI_TIMING_CTRL_1);
2000         udelay(10);
2001
2002         val |= ULPI_DATA_TRIMMER_LOAD;
2003         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
2004         val |= ULPI_DIR_TRIMMER_LOAD;
2005         writel(val, base + ULPI_TIMING_CTRL_1);
2006 }
2007
2008 static void reset_utmip_uhsic(void __iomem *base)
2009 {
2010         unsigned long val;
2011
2012         val = readl(base + USB_SUSP_CTRL);
2013         val |= UHSIC_RESET;
2014         writel(val, base + USB_SUSP_CTRL);
2015
2016         val = readl(base + USB_SUSP_CTRL);
2017         val |= UTMIP_RESET;
2018         writel(val, base + USB_SUSP_CTRL);
2019 }
2020
2021 static void ulpi_set_host(void __iomem *base)
2022 {
2023         unsigned long val;
2024
2025         val = readl(base + USB_USBMODE);
2026         val |= USB_USBMODE_HOST;
2027         writel(val, base + USB_USBMODE);
2028
2029         val = readl(base + HOSTPC1_DEVLC);
2030         val |= HOSTPC1_DEVLC_PTS(2);
2031         writel(val, base + HOSTPC1_DEVLC);
2032 }
2033
2034
2035
2036 static inline void null_phy_set_tristate(bool enable)
2037 {
2038 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2039         int tristate = (enable) ? TEGRA_TRI_TRISTATE : TEGRA_TRI_NORMAL;
2040         DBG("%s(%d) inst:[%s] FIXME enable pin group +++\n", __func__,
2041                                 __LINE__, enable ? "TRISTATE" : "NORMAL");
2042
2043         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA0, tristate);
2044         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA1, tristate);
2045         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA2, tristate);
2046         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA3, tristate);
2047         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA4, tristate);
2048         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA5, tristate);
2049         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA6, tristate);
2050         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA7, tristate);
2051         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_NXT, tristate);
2052
2053         if (enable)
2054                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR, tristate);
2055 #endif
2056
2057 }
2058
2059
2060 static int ulpi_null_phy_power_off(struct tegra_usb_phy *phy)
2061 {
2062         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2063
2064         if (!phy->phy_clk_on) {
2065                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
2066                                                         __LINE__, phy->inst);
2067                 return 0;
2068         }
2069
2070         null_phy_set_tristate(true);
2071
2072         phy->phy_clk_on = false;
2073         phy->hw_accessible = false;
2074
2075         return 0;
2076 }
2077
2078 static int ulpi_null_phy_init(struct tegra_usb_phy *phy)
2079 {
2080         unsigned long val;
2081         void __iomem *base = phy->regs;
2082
2083         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2084         usb_phy_init(phy);
2085         val = readl(base + ULPIS2S_CTRL);
2086         val |=  ULPIS2S_SLV0_CLAMP_XMIT;
2087         writel(val, base + ULPIS2S_CTRL);
2088
2089         val = readl(base + USB_SUSP_CTRL);
2090         val |= ULPIS2S_SLV0_RESET;
2091         writel(val, base + USB_SUSP_CTRL);
2092         udelay(10);
2093
2094         return 0;
2095 }
2096
2097 static int ulpi_null_phy_cmd_reset(struct tegra_usb_phy *phy)
2098 {
2099         unsigned long val;
2100         void __iomem *base = phy->regs;
2101
2102         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2103         ulpi_set_host(base);
2104
2105         /* remove slave0 reset */
2106         val = readl(base + USB_SUSP_CTRL);
2107         val &= ~ULPIS2S_SLV0_RESET;
2108         writel(val, base + USB_SUSP_CTRL);
2109
2110         val = readl(base + ULPIS2S_CTRL);
2111         val &=  ~ULPIS2S_SLV0_CLAMP_XMIT;
2112         writel(val, base + ULPIS2S_CTRL);
2113         udelay(10);
2114
2115         return 0;
2116 }
2117
2118 static int ulpi_null_phy_power_on(struct tegra_usb_phy *phy)
2119 {
2120         unsigned long val;
2121         void __iomem *base = phy->regs;
2122         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2123         static bool cold_boot = true;
2124
2125         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2126         if (phy->phy_clk_on) {
2127                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
2128                                                         __LINE__, phy->inst);
2129                 return 0;
2130         }
2131         reset_utmip_uhsic(base);
2132
2133         /* remove ULPI PADS CLKEN reset */
2134         val = readl(base + USB_SUSP_CTRL);
2135         val &= ~ULPI_PADS_CLKEN_RESET;
2136         writel(val, base + USB_SUSP_CTRL);
2137         udelay(10);
2138
2139         val = readl(base + ULPI_TIMING_CTRL_0);
2140         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
2141         writel(val, base + ULPI_TIMING_CTRL_0);
2142
2143         val = readl(base + USB_SUSP_CTRL);
2144         val |= ULPI_PHY_ENABLE;
2145         writel(val, base + USB_SUSP_CTRL);
2146         udelay(10);
2147
2148         /* set timming parameters */
2149         val = readl(base + ULPI_TIMING_CTRL_0);
2150         val |= ULPI_SHADOW_CLK_LOOPBACK_EN;
2151         val &= ~ULPI_SHADOW_CLK_SEL;
2152         val &= ~ULPI_LBK_PAD_EN;
2153         val |= ULPI_SHADOW_CLK_DELAY(config->shadow_clk_delay);
2154         val |= ULPI_CLOCK_OUT_DELAY(config->clock_out_delay);
2155         val |= ULPI_LBK_PAD_E_INPUT_OR;
2156         writel(val, base + ULPI_TIMING_CTRL_0);
2157
2158         writel(0, base + ULPI_TIMING_CTRL_1);
2159         udelay(10);
2160
2161         /* start internal 60MHz clock */
2162         val = readl(base + ULPIS2S_CTRL);
2163         val |= ULPIS2S_ENA;
2164         val |= ULPIS2S_SUPPORT_DISCONNECT;
2165         val |= ULPIS2S_SPARE((phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) ? 3 : 1);
2166         val |= ULPIS2S_PLLU_MASTER_BLASTER60;
2167         writel(val, base + ULPIS2S_CTRL);
2168
2169         /* select ULPI_CORE_CLK_SEL to SHADOW_CLK */
2170         val = readl(base + ULPI_TIMING_CTRL_0);
2171         val |= ULPI_CORE_CLK_SEL;
2172         writel(val, base + ULPI_TIMING_CTRL_0);
2173         udelay(10);
2174
2175         /* enable ULPI null phy clock - can't set the trimmers before this */
2176         val = readl(base + ULPI_TIMING_CTRL_0);
2177         val |= ULPI_CLK_OUT_ENA;
2178         writel(val, base + ULPI_TIMING_CTRL_0);
2179         udelay(10);
2180
2181         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
2182                                                  USB_PHY_CLK_VALID, 2500)) {
2183                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2184                 return -ETIMEDOUT;
2185         }
2186
2187         /* set ULPI trimmers */
2188         ulpi_set_trimmer(phy);
2189
2190         ulpi_set_host(base);
2191
2192         /* remove slave0 reset */
2193         val = readl(base + USB_SUSP_CTRL);
2194         val &= ~ULPIS2S_SLV0_RESET;
2195         writel(val, base + USB_SUSP_CTRL);
2196
2197         /* remove slave1 and line reset */
2198         val = readl(base + USB_SUSP_CTRL);
2199         val &= ~ULPIS2S_SLV1_RESET;
2200         val &= ~ULPIS2S_LINE_RESET;
2201
2202         /* remove ULPI PADS reset */
2203         val &= ~ULPI_PADS_RESET;
2204         writel(val, base + USB_SUSP_CTRL);
2205
2206         if (cold_boot) {
2207                 val = readl(base + ULPI_TIMING_CTRL_0);
2208                 val |= ULPI_CLK_PADOUT_ENA;
2209                 writel(val, base + ULPI_TIMING_CTRL_0);
2210                 cold_boot = false;
2211         }
2212         udelay(10);
2213
2214         phy->phy_clk_on = true;
2215         phy->hw_accessible = true;
2216
2217         return 0;
2218 }
2219
2220
2221 static int ulpi_null_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
2222 {
2223         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2224
2225         usb_phy_wait_for_sof(phy);
2226         return 0;
2227 }
2228
2229 static struct tegra_usb_phy_ops utmi_phy_ops = {
2230         .init           = usb_phy_init,
2231         .open           = utmi_phy_open,
2232         .close          = utmi_phy_close,
2233         .irq            = utmi_phy_irq,
2234         .power_on       = utmi_phy_power_on,
2235         .power_off      = utmi_phy_power_off,
2236         .pre_resume = utmi_phy_pre_resume,
2237         .resume = utmi_phy_resume,
2238         .post_resume    = utmi_phy_post_resume,
2239         .charger_detect = utmi_phy_charger_detect,
2240 };
2241
2242 static struct tegra_usb_phy_ops uhsic_phy_ops = {
2243         .init           = usb_phy_init,
2244         .open           = uhsic_phy_open,
2245         .power_on       = uhsic_phy_power_on,
2246         .power_off      = uhsic_phy_power_off,
2247         .pre_resume = uhsic_phy_pre_resume,
2248         .resume = uhsic_phy_resume,
2249         .post_resume = uhsic_phy_post_resume,
2250         .port_power = uhsic_phy_bus_port_power,
2251         .bus_reset      = uhsic_phy_bus_reset,
2252 };
2253
2254 static struct tegra_usb_phy_ops ulpi_null_phy_ops = {
2255         .init           = ulpi_null_phy_init,
2256         .power_on       = ulpi_null_phy_power_on,
2257         .power_off      = ulpi_null_phy_power_off,
2258         .pre_resume = ulpi_null_phy_pre_resume,
2259         .reset          = ulpi_null_phy_cmd_reset,
2260 };
2261
2262 static struct tegra_usb_phy_ops ulpi_link_phy_ops;
2263 static struct tegra_usb_phy_ops icusb_phy_ops;
2264
2265 static struct tegra_usb_phy_ops *phy_ops[] = {
2266         [TEGRA_USB_PHY_INTF_UTMI] = &utmi_phy_ops,
2267         [TEGRA_USB_PHY_INTF_ULPI_LINK] = &ulpi_link_phy_ops,
2268         [TEGRA_USB_PHY_INTF_ULPI_NULL] = &ulpi_null_phy_ops,
2269         [TEGRA_USB_PHY_INTF_HSIC] = &uhsic_phy_ops,
2270         [TEGRA_USB_PHY_INTF_ICUSB] = &icusb_phy_ops,
2271 };
2272
2273 int tegra11x_usb_phy_init_ops(struct tegra_usb_phy *phy)
2274 {
2275         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2276
2277         phy->ops = phy_ops[phy->pdata->phy_intf];
2278
2279         /* FIXME: uncommenting below line to make USB host mode fail*/
2280         /* usb_phy_power_down_pmc(); */
2281
2282         return 0;
2283 }