arm: tegra11x: usb_phy: Add HSIC changes from main
[linux-2.6.git] / arch / arm / mach-tegra / tegra11x_usb_phy.c
1 /*
2  * arch/arm/mach-tegra/tegra11x_usb_phy.c
3  *
4  * Copyright (C) 2012 NVIDIA Corporation
5  *
6  *
7  * This software is licensed under the terms of the GNU General Public
8  * License version 2, as published by the Free Software Foundation, and
9  * may be copied, distributed, and modified under those terms.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17 #include <linux/resource.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/slab.h>
21 #include <linux/err.h>
22 #include <linux/platform_device.h>
23 #include <linux/io.h>
24 #include <linux/gpio.h>
25 #include <linux/usb/ulpi.h>
26 #include <linux/interrupt.h>
27 #include <linux/clk.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/platform_data/tegra_usb.h>
30 #include <mach/clk.h>
31 #include <mach/iomap.h>
32 #include <mach/pinmux.h>
33 #include <mach/pinmux-t11.h>
34 #include <asm/mach-types.h>
35 #include "tegra_usb_phy.h"
36 #include "gpio-names.h"
37 #include "fuse.h"
38
39 #define USB_USBCMD              0x130
40 #define   USB_USBCMD_RS         (1 << 0)
41 #define   USB_CMD_RESET (1<<1)
42
43 #define USB_USBSTS              0x134
44 #define   USB_USBSTS_PCI        (1 << 2)
45 #define   USB_USBSTS_SRI        (1 << 7)
46 #define   USB_USBSTS_HCH        (1 << 12)
47
48 #define USB_TXFILLTUNING        0x154
49 #define USB_FIFO_TXFILL_THRES(x)   (((x) & 0x1f) << 16)
50 #define USB_FIFO_TXFILL_MASK    0x1f0000
51
52 #define ULPI_VIEWPORT           0x170
53 #define   ULPI_WAKEUP           (1 << 31)
54 #define   ULPI_RUN              (1 << 30)
55 #define   ULPI_RD_WR            (1 << 29)
56
57 #define USB_ASYNCLISTADDR       0x148
58
59 #define ICUSB_CTRL              0x15c
60
61 #define USB_PORTSC              0x174
62 #define   USB_PORTSC_PHCD       (1 << 23)
63 #define   USB_PORTSC_WKOC       (1 << 22)
64 #define   USB_PORTSC_WKDS       (1 << 21)
65 #define   USB_PORTSC_WKCN       (1 << 20)
66 #define   USB_PORTSC_PTC(x)     (((x) & 0xf) << 16)
67 #define   USB_PORTSC_PP (1 << 12)
68 #define   USB_PORTSC_LS(x) (((x) & 0x3) << 10)
69 #define   USB_PORTSC_SUSP       (1 << 7)
70 #define   USB_PORTSC_RESUME     (1 << 6)
71 #define   USB_PORTSC_OCC        (1 << 5)
72 #define   USB_PORTSC_PEC        (1 << 3)
73 #define   USB_PORTSC_PE         (1 << 2)
74 #define   USB_PORTSC_CSC        (1 << 1)
75 #define   USB_PORTSC_CCS        (1 << 0)
76 #define   USB_PORTSC_RWC_BITS (USB_PORTSC_CSC | USB_PORTSC_PEC | USB_PORTSC_OCC)
77 #define   USB_PORTSC_PSPD_MASK  3
78
79 #define HOSTPC1_DEVLC           0x1b4
80 #define   HOSTPC1_DEVLC_PHCD            (1 << 22)
81 #define   HOSTPC1_DEVLC_PTS(x)          (((x) & 0x7) << 29)
82 #define   HOSTPC1_DEVLC_PTS_MASK        7
83 #define   HOSTPC1_DEVLC_PTS_HSIC        4
84 #define   HOSTPC1_DEVLC_STS             (1 << 28)
85 #define   HOSTPC1_DEVLC_PSPD(x)         (((x) & 0x3) << 25)
86 #define   HOSTPC1_DEVLC_PSPD_MASK       3
87 #define   HOSTPC1_DEVLC_PSPD_HIGH_SPEED 2
88 #define   HOSTPC1_DEVLC_NYT_ASUS        1
89
90 #define USB_USBMODE             0x1f8
91 #define   USB_USBMODE_MASK              (3 << 0)
92 #define   USB_USBMODE_HOST              (3 << 0)
93 #define   USB_USBMODE_DEVICE            (2 << 0)
94
95 #define USB_SUSP_CTRL           0x400
96 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
97 #define   USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
98 #define   USB_SUSP_CLR                  (1 << 5)
99 #define   USB_CLKEN             (1 << 6)
100 #define   USB_PHY_CLK_VALID             (1 << 7)
101 #define   USB_PHY_CLK_VALID_INT_ENB     (1 << 9)
102 #define   USB_PHY_CLK_VALID_INT_STS     (1 << 8)
103 #define   UTMIP_RESET                   (1 << 11)
104 #define   UTMIP_PHY_ENABLE              (1 << 12)
105 #define   ULPI_PHY_ENABLE               (1 << 13)
106 #define   UHSIC_RESET                   (1 << 14)
107 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
108 #define   UHSIC_PHY_ENABLE              (1 << 19)
109 #define   ULPIS2S_SLV0_RESET            (1 << 20)
110 #define   ULPIS2S_SLV1_RESET            (1 << 21)
111 #define   ULPIS2S_LINE_RESET            (1 << 22)
112 #define   ULPI_PADS_RESET               (1 << 23)
113 #define   ULPI_PADS_CLKEN_RESET         (1 << 24)
114
115 #define USB_PHY_VBUS_WAKEUP_ID  0x408
116 #define   VDAT_DET_INT_EN       (1 << 16)
117 #define   VDAT_DET_CHG_DET      (1 << 17)
118 #define   VDAT_DET_STS          (1 << 18)
119 #define   USB_ID_STATUS         (1 << 2)
120
121 #define ULPIS2S_CTRL            0x418
122 #define   ULPIS2S_ENA                   (1 << 0)
123 #define   ULPIS2S_SUPPORT_DISCONNECT    (1 << 2)
124 #define   ULPIS2S_PLLU_MASTER_BLASTER60 (1 << 3)
125 #define   ULPIS2S_SPARE(x)              (((x) & 0xF) << 8)
126 #define   ULPIS2S_FORCE_ULPI_CLK_OUT    (1 << 12)
127 #define   ULPIS2S_DISCON_DONT_CHECK_SE0 (1 << 13)
128 #define   ULPIS2S_SUPPORT_HS_KEEP_ALIVE (1 << 14)
129 #define   ULPIS2S_DISABLE_STP_PU        (1 << 15)
130 #define   ULPIS2S_SLV0_CLAMP_XMIT       (1 << 16)
131
132 #define ULPI_TIMING_CTRL_0      0x424
133 #define   ULPI_CLOCK_OUT_DELAY(x)       ((x) & 0x1F)
134 #define   ULPI_OUTPUT_PINMUX_BYP        (1 << 10)
135 #define   ULPI_CLKOUT_PINMUX_BYP        (1 << 11)
136 #define   ULPI_SHADOW_CLK_LOOPBACK_EN   (1 << 12)
137 #define   ULPI_SHADOW_CLK_SEL           (1 << 13)
138 #define   ULPI_CORE_CLK_SEL             (1 << 14)
139 #define   ULPI_SHADOW_CLK_DELAY(x)      (((x) & 0x1F) << 16)
140 #define   ULPI_LBK_PAD_EN               (1 << 26)
141 #define   ULPI_LBK_PAD_E_INPUT_OR       (1 << 27)
142 #define   ULPI_CLK_OUT_ENA              (1 << 28)
143 #define   ULPI_CLK_PADOUT_ENA           (1 << 29)
144
145 #define ULPI_TIMING_CTRL_1      0x428
146 #define   ULPI_DATA_TRIMMER_LOAD        (1 << 0)
147 #define   ULPI_DATA_TRIMMER_SEL(x)      (((x) & 0x7) << 1)
148 #define   ULPI_STPDIRNXT_TRIMMER_LOAD   (1 << 16)
149 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
150 #define   ULPI_DIR_TRIMMER_LOAD         (1 << 24)
151 #define   ULPI_DIR_TRIMMER_SEL(x)       (((x) & 0x7) << 25)
152
153 #define USB_IF_SPARE    0x498
154 #define   USB_HS_RSM_EOP_EN         (1 << 4)
155 #define   USB_PORT_SUSPEND_EN       (1 << 5)
156
157 #define USB_NEW_CONTROL  0x4c0
158 #define   USB_COHRENCY_EN           (1 << 0)
159 #define   USB_MEM_ALLIGNMENT_MUX_EN (1 << 1)
160
161 #define UTMIP_XCVR_CFG0         0x808
162 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
163 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
164 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
165 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
166 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
167 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
168 #define   UTMIP_XCVR_LSBIAS_SEL                 (1 << 21)
169 #define   UTMIP_XCVR_SETUP_MSB(x)               (((x) & 0x7) << 22)
170 #define   UTMIP_XCVR_HSSLEW_MSB(x)              (((x) & 0x7f) << 25)
171 #define   UTMIP_XCVR_MAX_OFFSET         2
172 #define   UTMIP_XCVR_SETUP_MAX_VALUE    0x7f
173 #define   UTMIP_XCVR_SETUP_MIN_VALUE    0
174 #define   XCVR_SETUP_MSB_CALIB(x) ((x) >> 4)
175
176 #define UTMIP_BIAS_CFG0         0x80c
177 #define   UTMIP_OTGPD                   (1 << 11)
178 #define   UTMIP_BIASPD                  (1 << 10)
179 #define   UTMIP_HSSQUELCH_LEVEL(x)      (((x) & 0x3) << 0)
180 #define   UTMIP_HSDISCON_LEVEL(x)       (((x) & 0x3) << 2)
181 #define   UTMIP_HSDISCON_LEVEL_MSB      (1 << 24)
182
183 #define UTMIP_HSRX_CFG0         0x810
184 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
185 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
186
187 #define UTMIP_HSRX_CFG1         0x814
188 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
189
190 #define UTMIP_TX_CFG0           0x820
191 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
192 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
193
194 #define UTMIP_DEBOUNCE_CFG0 0x82c
195 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
196
197 #define UTMIP_BAT_CHRG_CFG0 0x830
198 #define   UTMIP_PD_CHRG                 (1 << 0)
199 #define   UTMIP_ON_SINK_EN              (1 << 2)
200 #define   UTMIP_OP_SRC_EN               (1 << 3)
201
202 #define UTMIP_XCVR_CFG1         0x838
203 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
204 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
205 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
206 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
207
208 #define UTMIP_BIAS_CFG1         0x83c
209 #define   UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
210 #define   UTMIP_BIAS_PDTRK_POWERDOWN    (1 << 0)
211 #define   UTMIP_BIAS_PDTRK_POWERUP      (1 << 1)
212
213 #define UTMIP_MISC_CFG0         0x824
214 #define   UTMIP_DPDM_OBSERVE            (1 << 26)
215 #define   UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
216 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J   UTMIP_DPDM_OBSERVE_SEL(0xf)
217 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K   UTMIP_DPDM_OBSERVE_SEL(0xe)
218 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
219 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
220 #define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
221 #define   FORCE_PULLDN_DM       (1 << 8)
222 #define   FORCE_PULLDN_DP       (1 << 9)
223 #define   COMB_TERMS            (1 << 0)
224 #define   ALWAYS_FREE_RUNNING_TERMS (1 << 1)
225
226 #define UTMIP_SPARE_CFG0        0x834
227 #define   FUSE_SETUP_SEL                (1 << 3)
228 #define   FUSE_ATERM_SEL                (1 << 4)
229
230 #define UTMIP_PMC_WAKEUP0               0x84c
231 #define   EVENT_INT_ENB                 (1 << 0)
232
233 #define UTMIP_BIAS_STS0                 0x840
234 #define   UTMIP_RCTRL_VAL(x)            (((x) & 0xffff) << 0)
235 #define   UTMIP_TCTRL_VAL(x)            (((x) & (0xffff << 16)) >> 16)
236
237 #define UHSIC_PLL_CFG1                          0xc04
238 #define   UHSIC_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
239 #define   UHSIC_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 14)
240
241 #define UHSIC_HSRX_CFG0                         0xc08
242 #define   UHSIC_ELASTIC_UNDERRUN_LIMIT(x)       (((x) & 0x1f) << 2)
243 #define   UHSIC_ELASTIC_OVERRUN_LIMIT(x)        (((x) & 0x1f) << 8)
244 #define   UHSIC_IDLE_WAIT(x)                    (((x) & 0x1f) << 13)
245
246 #define UHSIC_HSRX_CFG1                         0xc0c
247 #define   UHSIC_HS_SYNC_START_DLY(x)            (((x) & 0x1f) << 1)
248
249 #define UHSIC_TX_CFG0                           0xc10
250 #define UHSIC_HS_READY_WAIT_FOR_VALID   (1 << 9)
251 #define UHSIC_MISC_CFG0                         0xc14
252 #define   UHSIC_SUSPEND_EXIT_ON_EDGE            (1 << 7)
253 #define   UHSIC_DETECT_SHORT_CONNECT            (1 << 8)
254 #define   UHSIC_FORCE_XCVR_MODE                 (1 << 15)
255 #define   UHSIC_DISABLE_BUSRESET                (1 << 20)
256 #define UHSIC_MISC_CFG1                         0xc18
257 #define   UHSIC_PLLU_STABLE_COUNT(x)            (((x) & 0xfff) << 2)
258
259 #define UHSIC_PADS_CFG0                         0xc1c
260 #define   UHSIC_TX_RTUNEN                       0xf000
261 #define   UHSIC_TX_RTUNE(x)                     (((x) & 0xf) << 12)
262 #define   UHSIC_TX_SLEWP                        (0xf << 16)
263 #define   UHSIC_TX_SLEWN                        (0xf << 20)
264
265 #define UHSIC_PADS_CFG1                         0xc20
266 #define   UHSIC_PD_BG                           (1 << 2)
267 #define   UHSIC_PD_TX                           (1 << 3)
268 #define   UHSIC_PD_TRK                          (1 << 4)
269 #define   UHSIC_PD_RX                           (1 << 5)
270 #define   UHSIC_PD_ZI                           (1 << 6)
271 #define   UHSIC_RX_SEL                          (1 << 7)
272 #define   UHSIC_RPD_DATA                        (1 << 9)
273 #define   UHSIC_RPD_STROBE                      (1 << 10)
274 #define   UHSIC_RPU_DATA                        (1 << 11)
275 #define   UHSIC_RPU_STROBE                      (1 << 12)
276
277 #define UHSIC_STAT_CFG0         0xc28
278 #define UHSIC_CONNECT_DETECT                    (1 << 0)
279
280 #define UHSIC_CMD_CFG0                                  0xc24
281 #define UHSIC_PRETEND_CONNECT_DETECT    (1 << 5)
282 #define UHSIC_PMC_WAKEUP0                               0xc34
283 #define UHSIC_WAKE_ALARM                                (1 << 19)
284 #define UHSIC_CLR_WAKE_ALARM_P0                 (1 << 15)
285 #define UHSIC_MASTER_ENABLE                             (1 << 24)
286 #define UHSIC_WAKE_VAL(x)                               (((x) & 0xf) << 28)
287 #define UHSIC_MASTER_ENABLE_P0                  (1 << 24)
288 #define UHSIC_WAKE_VAL_P0(x)                    (((x) & 0xf) << 28)
289 #define UHSIC_WAKE_WALK_EN_P0                   (1 << 30)
290 #define UHSIC_LINEVAL_WALK_EN                   (1 << 31)
291 #define UHSIC_CLR_WALK_PTR_P0                   (1 << 3)
292 #define UHSIC_CLR_WAKE_ALARM_P0                 (1 << 15)
293 #define USB_USBINTR                                             0x138
294 #define UHSIC_WALK_PTR_VAL                              (0x3 << 6)
295 #define UHSIC_DATA_VAL_P0                               (1 << 15)
296 #define UHSIC_STROBE_VAL_P0                             (1 << 14)
297 #define HSIC_RESERVED_P0                                (3 << 14)
298 #define STROBE_VAL_PD_P0                                (1 << 12)
299 #define DATA_VAL_PD_P0                                  (1 << 13)
300 #define UHSIC_PWR                                               (1 << 3)
301 #define PMC_SLEEPWALK_UHSIC                             0x210
302 #define UHSIC_STROBE_RPD_A                              (1 << 0)
303 #define UHSIC_DATA_RPD_A                                (1 << 1)
304 #define UHSIC_STROBE_RPU_A                              (1 << 2)
305 #define UHSIC_DATA_RPU_A                                (1 << 3)
306 #define UHSIC_STROBE_RPD_B                              (1 << 8)
307 #define UHSIC_DATA_RPD_B                                (1 << 9)
308 #define UHSIC_STROBE_RPU_B                              (1 << 10)
309 #define UHSIC_DATA_RPU_B                                (1 << 11)
310 #define UHSIC_STROBE_RPD_C                              (1 << 16)
311 #define UHSIC_DATA_RPD_C                                (1 << 17)
312 #define UHSIC_STROBE_RPU_C                              (1 << 18)
313 #define UHSIC_DATA_RPU_C                                (1 << 19)
314 #define UHSIC_STROBE_RPD_D                              (1 << 24)
315 #define UHSIC_DATA_RPD_D                                (1 << 25)
316 #define UHSIC_STROBE_RPU_D                              (1 << 26)
317 #define UHSIC_DATA_RPU_D                                (1 << 27)
318 #define UHSIC_LINE_DEB_CNT(x)                   (((x) & 0xf) << 20)
319 #define   WAKE_VAL_SD10                                 0x2
320
321 #define PMC_USB_DEBOUNCE                        0xec
322 #define   UTMIP_LINE_DEB_CNT(x)                 (((x) & 0xf) << 16)
323
324 #define PMC_USB_AO                              0xf0
325 #define PMC_POWER_DOWN_MASK                     0xffff
326 #define HSIC_RESERVED_P0                        (3 << 14)
327 #define HSIC_STOBE_VAL_PD_P0                    (1 << 13)
328 #define HSIC_DATA_VAL_PD_P0                     (1 << 12)
329 #define USB_ID_PD(inst)                         (1 << ((4*(inst))+3))
330 #define VBUS_WAKEUP_PD(inst)                    (1 << ((4*(inst))+2))
331 #define   USBON_VAL_PD(inst)                    (1 << ((4*(inst))+1))
332 #define   USBON_VAL_PD_P2                       (1 << 9)
333 #define   USBON_VAL_PD_P1                       (1 << 5)
334 #define   USBON_VAL_PD_P0                       (1 << 1)
335 #define   USBOP_VAL_PD(inst)                    (1 << (4*(inst)))
336 #define   USBOP_VAL_PD_P2                       (1 << 8)
337 #define   USBOP_VAL_PD_P1                       (1 << 4)
338 #define   USBOP_VAL_PD_P0                       (1 << 0)
339 #define   PMC_USB_AO_PD_P2                      (0xf << 8)
340 #define   PMC_USB_AO_ID_PD_P0                   (1 << 3)
341 #define   PMC_USB_AO_VBUS_WAKEUP_PD_P0  (1 << 2)
342
343 #define PMC_TRIGGERS                    0x1ec
344 #define   UTMIP_CLR_WALK_PTR(inst)      (1 << (inst))
345 #define   UTMIP_CLR_WALK_PTR_P2         (1 << 2)
346 #define   UTMIP_CLR_WALK_PTR_P1         (1 << 1)
347 #define   UTMIP_CLR_WALK_PTR_P0         (1 << 0)
348 #define   UTMIP_CAP_CFG(inst)   (1 << ((inst)+4))
349 #define   UTMIP_CAP_CFG_P2              (1 << 6)
350 #define   UTMIP_CAP_CFG_P1              (1 << 5)
351 #define   UTMIP_CAP_CFG_P0              (1 << 4)
352 #define   UTMIP_CLR_WAKE_ALARM(inst)            (1 << ((inst)+12))
353 #define   UTMIP_CLR_WAKE_ALARM_P2       (1 << 14)
354
355 #define PMC_PAD_CFG             (0x1f4)
356
357 #define PMC_UTMIP_TERM_PAD_CFG  0x1f8
358 #define   PMC_TCTRL_VAL(x)      (((x) & 0x1f) << 5)
359 #define   PMC_RCTRL_VAL(x)      (((x) & 0x1f) << 0)
360
361 #define UHSIC_SLEEPWALK_REG             0x210
362 #define UHSIC_DATA_RPD_D                (1 << 25)
363 #define UHSIC_STRB_RPD_D                (1 << 24)
364 #define UHSIC_DATA_RPD_C                (1 << 17)
365 #define UHSIC_STRB_RPD_C                (1 << 16)
366 #define UHSIC_DATA_RPD_B                (1 << 9)
367 #define UHSIC_STRB_RPD_B                (1 << 8)
368 #define UHSIC_DATA_RPD_A                (1 << 1)
369 #define UHSIC_STRB_RPD_A                (1 << 0)
370
371 #define PMC_SLEEP_CFG                   0x1fc
372 #define   UTMIP_TCTRL_USE_PMC(inst) (1 << ((8*(inst))+3))
373 #define   UTMIP_TCTRL_USE_PMC_P2                (1 << 19)
374 #define   UTMIP_TCTRL_USE_PMC_P1                (1 << 11)
375 #define   UTMIP_TCTRL_USE_PMC_P0                (1 << 3)
376 #define   UTMIP_RCTRL_USE_PMC(inst) (1 << ((8*(inst))+2))
377 #define   UTMIP_RCTRL_USE_PMC_P2                (1 << 18)
378 #define   UTMIP_RCTRL_USE_PMC_P1                (1 << 10)
379 #define   UTMIP_RCTRL_USE_PMC_P0                (1 << 2)
380 #define   UTMIP_FSLS_USE_PMC(inst)      (1 << ((8*(inst))+1))
381 #define   UTMIP_FSLS_USE_PMC_P2         (1 << 17)
382 #define   UTMIP_FSLS_USE_PMC_P1         (1 << 9)
383 #define   UTMIP_FSLS_USE_PMC_P0         (1 << 1)
384 #define   UTMIP_MASTER_ENABLE(inst) (1 << (8*(inst)))
385 #define   UTMIP_MASTER_ENABLE_P2                (1 << 16)
386 #define   UTMIP_MASTER_ENABLE_P1                (1 << 8)
387 #define   UTMIP_MASTER_ENABLE_P0                (1 << 0)
388 #define UHSIC_MASTER_ENABLE_P0          (1 << 24)
389 #define UHSIC_WAKE_VAL_P0(x)            (((x) & 0xf) << 28)
390
391 #define PMC_SLEEPWALK_CFG               0x200
392 #define   UTMIP_LINEVAL_WALK_EN(inst) (1 << ((8*(inst))+7))
393 #define   UTMIP_LINEVAL_WALK_EN_P2      (1 << 23)
394 #define   UTMIP_LINEVAL_WALK_EN_P1      (1 << 15)
395 #define   UTMIP_LINEVAL_WALK_EN_P0      (1 << 7)
396 #define   UTMIP_WAKE_VAL(inst, x) (((x) & 0xf) << ((8*(inst))+4))
397 #define   UTMIP_WAKE_VAL_P2(x)          (((x) & 0xf) << 20)
398 #define   UTMIP_WAKE_VAL_P1(x)          (((x) & 0xf) << 12)
399 #define   UTMIP_WAKE_VAL_P0(x)          (((x) & 0xf) << 4)
400 #define   WAKE_VAL_NONE         0xc
401 #define   WAKE_VAL_ANY                  0xF
402 #define   WAKE_VAL_FSJ                  0x2
403 #define   WAKE_VAL_FSK                  0x1
404 #define   WAKE_VAL_SE0                  0x0
405
406 #define PMC_SLEEPWALK_REG(inst)         (0x204 + (4*(inst)))
407 #define   UTMIP_USBOP_RPD_A     (1 << 0)
408 #define   UTMIP_USBON_RPD_A     (1 << 1)
409 #define   UTMIP_AP_A                    (1 << 4)
410 #define   UTMIP_AN_A                    (1 << 5)
411 #define   UTMIP_HIGHZ_A         (1 << 6)
412 #define   UTMIP_USBOP_RPD_B     (1 << 8)
413 #define   UTMIP_USBON_RPD_B     (1 << 9)
414 #define   UTMIP_AP_B                    (1 << 12)
415 #define   UTMIP_AN_B                    (1 << 13)
416 #define   UTMIP_HIGHZ_B         (1 << 14)
417 #define   UTMIP_USBOP_RPD_C     (1 << 16)
418 #define   UTMIP_USBON_RPD_C     (1 << 17)
419 #define   UTMIP_AP_C            (1 << 20)
420 #define   UTMIP_AN_C            (1 << 21)
421 #define   UTMIP_HIGHZ_C         (1 << 22)
422 #define   UTMIP_USBOP_RPD_D     (1 << 24)
423 #define   UTMIP_USBON_RPD_D     (1 << 25)
424 #define   UTMIP_AP_D            (1 << 28)
425 #define   UTMIP_AN_D            (1 << 29)
426 #define   UTMIP_HIGHZ_D         (1 << 30)
427
428 #define UTMIP_UHSIC_STATUS              0x214
429 #define   UTMIP_WALK_PTR_VAL(inst)      (0x3 << ((inst)*2))
430 #define   UTMIP_USBOP_VAL(inst)         (1 << ((2*(inst)) + 8))
431 #define   UTMIP_USBOP_VAL_P2            (1 << 12)
432 #define   UTMIP_USBOP_VAL_P1            (1 << 10)
433 #define   UTMIP_USBOP_VAL_P0            (1 << 8)
434 #define   UTMIP_USBON_VAL(inst)         (1 << ((2*(inst)) + 9))
435 #define   UTMIP_USBON_VAL_P2            (1 << 13)
436 #define   UTMIP_USBON_VAL_P1            (1 << 11)
437 #define   UTMIP_USBON_VAL_P0            (1 << 9)
438 #define   UTMIP_WAKE_ALARM(inst)                (1 << ((inst) + 16))
439 #define   UTMIP_WAKE_ALARM_P2   (1 << 18)
440 #define   UTMIP_WAKE_ALARM_P1   (1 << 17)
441 #define   UTMIP_WAKE_ALARM_P0   (1 << 16)
442 #define   UTMIP_WALK_PTR(inst)  (1 << ((inst)*2))
443 #define   UTMIP_WALK_PTR_P2     (1 << 4)
444 #define   UTMIP_WALK_PTR_P1     (1 << 2)
445 #define   UTMIP_WALK_PTR_P0     (1 << 0)
446
447 #define USB1_PREFETCH_ID               6
448 #define USB2_PREFETCH_ID               18
449 #define USB3_PREFETCH_ID               17
450
451 #define PMC_UTMIP_UHSIC_FAKE            0x218
452 #define   USBON_VAL(inst)       (1 << ((4*(inst))+1))
453 #define   USBON_VAL_P2                  (1 << 9)
454 #define   USBON_VAL_P1                  (1 << 5)
455 #define   USBON_VAL_P0                  (1 << 1)
456 #define   USBOP_VAL(inst)       (1 << (4*(inst)))
457 #define   USBOP_VAL_P2                  (1 << 8)
458 #define   USBOP_VAL_P1                  (1 << 4)
459 #define   USBOP_VAL_P0                  (1 << 0)
460
461 #define PMC_UTMIP_BIAS_MASTER_CNTRL 0x30c
462 #define   BIAS_MASTER_PROG_VAL          (1 << 1)
463
464 #define PMC_UTMIP_MASTER_CONFIG         0x310
465 #define   UTMIP_PWR(inst)               (1 << (inst))
466
467 #define FUSE_USB_CALIB_0                0x1F0
468 #define   FUSE_USB_CALIB_XCVR_SETUP(x)  (((x) & 0x7F) << 0)
469
470 #define APB_MISC_GP_OBSCTRL_0   0x818
471 #define APB_MISC_GP_OBSDATA_0   0x81c
472
473 /* ULPI GPIO */
474 #define ULPI_STP        TEGRA_GPIO_PY3
475 #define ULPI_DIR        TEGRA_GPIO_PY1
476 #define ULPI_D0         TEGRA_GPIO_PO1
477 #define ULPI_D1         TEGRA_GPIO_PO2
478
479 #define TEGRA_STREAM_DISABLE    0x1f8
480 #define TEGRA_STREAM_DISABLE_OFFSET     (1 << 4)
481
482 /* These values (in milli second) are taken from the battery charging spec */
483 #define TDP_SRC_ON_MS    100
484 #define TDPSRC_CON_MS    40
485
486 #ifdef DEBUG
487 #define DBG(stuff...)   pr_info("tegra11x_usb_phy: " stuff)
488 #else
489 #define DBG(stuff...)   do {} while (0)
490 #endif
491
492 static u32 utmip_rctrl_val, utmip_tctrl_val;
493 static DEFINE_SPINLOCK(utmip_pad_lock);
494 static int utmip_pad_count;
495
496 static struct tegra_xtal_freq utmip_freq_table[] = {
497         {
498                 .freq = 12000000,
499                 .enable_delay = 0x02,
500                 .stable_count = 0x2F,
501                 .active_delay = 0x04,
502                 .xtal_freq_count = 0x76,
503                 .debounce = 0x7530,
504                 .pdtrk_count = 5,
505         },
506         {
507                 .freq = 13000000,
508                 .enable_delay = 0x02,
509                 .stable_count = 0x33,
510                 .active_delay = 0x05,
511                 .xtal_freq_count = 0x7F,
512                 .debounce = 0x7EF4,
513                 .pdtrk_count = 5,
514         },
515         {
516                 .freq = 19200000,
517                 .enable_delay = 0x03,
518                 .stable_count = 0x4B,
519                 .active_delay = 0x06,
520                 .xtal_freq_count = 0xBB,
521                 .debounce = 0xBB80,
522                 .pdtrk_count = 7,
523         },
524         {
525                 .freq = 26000000,
526                 .enable_delay = 0x04,
527                 .stable_count = 0x66,
528                 .active_delay = 0x09,
529                 .xtal_freq_count = 0xFE,
530                 .debounce = 0xFDE8,
531                 .pdtrk_count = 9,
532         },
533 };
534
535 static struct tegra_xtal_freq uhsic_freq_table[] = {
536         {
537                 .freq = 12000000,
538                 .enable_delay = 0x02,
539                 .stable_count = 0x2F,
540                 .active_delay = 0x0,
541                 .xtal_freq_count = 0x1CA,
542         },
543         {
544                 .freq = 13000000,
545                 .enable_delay = 0x02,
546                 .stable_count = 0x33,
547                 .active_delay = 0x0,
548                 .xtal_freq_count = 0x1F0,
549         },
550         {
551                 .freq = 19200000,
552                 .enable_delay = 0x03,
553                 .stable_count = 0x4B,
554                 .active_delay = 0x0,
555                 .xtal_freq_count = 0x2DD,
556         },
557         {
558                 .freq = 26000000,
559                 .enable_delay = 0x04,
560                 .stable_count = 0x66,
561                 .active_delay = 0x0,
562                 .xtal_freq_count = 0x3E0,
563         },
564 };
565
566 static int _usb_phy_init(struct tegra_usb_phy *phy)
567 {
568         unsigned long val;
569         void __iomem *base = phy->regs;
570
571         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
572
573         val = readl(base + HOSTPC1_DEVLC);
574         val &= ~HOSTPC1_DEVLC_STS;
575         writel(val, base + HOSTPC1_DEVLC);
576
577         val = readl(base + USB_IF_SPARE);
578         val |= USB_HS_RSM_EOP_EN;
579         val |= USB_PORT_SUSPEND_EN;
580         writel(val, base + USB_IF_SPARE);
581
582         val = readl(base + USB_NEW_CONTROL);
583         val |= USB_COHRENCY_EN;
584         val |= USB_MEM_ALLIGNMENT_MUX_EN;
585         writel(val, base + USB_NEW_CONTROL);
586
587 #if !defined(CONFIG_TEGRA_SILICON_PLATFORM)
588         val =  readl(base + TEGRA_STREAM_DISABLE);
589         val |= TEGRA_STREAM_DISABLE_OFFSET;
590         writel(val , base + TEGRA_STREAM_DISABLE);
591 #endif
592
593         return 0;
594 }
595 static int usb_phy_reset(struct tegra_usb_phy *phy)
596 {
597         unsigned long val;
598         void __iomem *base = phy->regs;
599
600         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
601
602 #if !defined(CONFIG_TEGRA_SILICON_PLATFORM)
603         val =  readl(base + TEGRA_STREAM_DISABLE);
604         val |= TEGRA_STREAM_DISABLE_OFFSET;
605         writel(val , base + TEGRA_STREAM_DISABLE);
606 #endif
607         val = readl(base + USB_TXFILLTUNING);
608         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
609                 val = USB_FIFO_TXFILL_THRES(0x10);
610                 writel(val, base + USB_TXFILLTUNING);
611         }
612
613 return 0;
614 }
615
616 static void utmip_setup_pmc_wake_detect(struct tegra_usb_phy *phy)
617 {
618         unsigned long val, pmc_pad_cfg_val;
619         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
620         unsigned  int inst = phy->inst;
621         void __iomem *base = phy->regs;
622         bool port_connected;
623         enum usb_phy_port_speed port_speed;
624
625         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
626
627         /* check for port connect status */
628         val = readl(base + USB_PORTSC);
629         port_connected = val & USB_PORTSC_CCS;
630
631         if (!port_connected)
632                 return;
633
634         port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
635                 HOSTPC1_DEVLC_PSPD_MASK;
636         /*Set PMC MASTER bits to do the following
637         * a. Take over the UTMI drivers
638         * b. set up such that it will take over resume
639         *        if remote wakeup is detected
640         * Prepare PMC to take over suspend-wake detect-drive resume until USB
641         * controller ready
642         */
643
644         /* disable master enable in PMC */
645         val = readl(pmc_base + PMC_SLEEP_CFG);
646         val &= ~UTMIP_MASTER_ENABLE(inst);
647         writel(val, pmc_base + PMC_SLEEP_CFG);
648
649         /* UTMIP_PWR_PX=1 for power savings mode */
650         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
651         val |= UTMIP_PWR(inst);
652         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
653
654         /* config debouncer */
655         val = readl(pmc_base + PMC_USB_DEBOUNCE);
656         val &= ~UTMIP_LINE_DEB_CNT(~0);
657         val |= UTMIP_LINE_DEB_CNT(4);
658         writel(val, pmc_base + PMC_USB_DEBOUNCE);
659
660         /* Make sure nothing is happening on the line with respect to PMC */
661         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
662         val &= ~USBOP_VAL(inst);
663         val &= ~USBON_VAL(inst);
664         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
665
666         /* Make sure wake value for line is none */
667         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
668         val &= ~UTMIP_LINEVAL_WALK_EN(inst);
669         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
670         val = readl(pmc_base + PMC_SLEEP_CFG);
671         val &= ~UTMIP_WAKE_VAL(inst, ~0);
672         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
673         writel(val, pmc_base + PMC_SLEEP_CFG);
674
675         /* turn off pad detectors */
676         val = readl(pmc_base + PMC_USB_AO);
677         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
678         writel(val, pmc_base + PMC_USB_AO);
679
680         /* Remove fake values and make synchronizers work a bit */
681         val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE);
682         val &= ~USBOP_VAL(inst);
683         val &= ~USBON_VAL(inst);
684         writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE);
685
686         /* Enable which type of event can trigger a walk,
687         in this case usb_line_wake */
688         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
689         val |= UTMIP_LINEVAL_WALK_EN(inst);
690         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
691
692         /* Enable which type of event can trigger a walk,
693         * in this case usb_line_wake */
694         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
695         val |= UTMIP_LINEVAL_WALK_EN(inst);
696         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
697
698         /* Clear the walk pointers and wake alarm */
699         val = readl(pmc_base + PMC_TRIGGERS);
700         val |= UTMIP_CLR_WAKE_ALARM(inst) | UTMIP_CLR_WALK_PTR(inst);
701         writel(val, pmc_base + PMC_TRIGGERS);
702
703
704         /* Capture FS/LS pad configurations */
705         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
706         val = readl(pmc_base + PMC_TRIGGERS);
707         val |= UTMIP_CAP_CFG(inst);
708         writel(val, pmc_base + PMC_TRIGGERS);
709         udelay(1);
710         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
711
712         /* BIAS MASTER_ENABLE=0 */
713         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
714         val &= ~BIAS_MASTER_PROG_VAL;
715         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
716
717         /* program walk sequence, maintain a J, followed by a driven K
718         * to signal a resume once an wake event is detected */
719         val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
720         val &= ~UTMIP_AP_A;
721         val |= UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_AN_A |UTMIP_HIGHZ_A |
722                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_AP_B | UTMIP_AN_B |
723                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_AP_C | UTMIP_AN_C |
724                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_AP_D | UTMIP_AN_D;
725         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
726
727         if (port_speed == USB_PHY_PORT_SPEED_LOW) {
728                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
729                 val &= ~(UTMIP_AN_B | UTMIP_HIGHZ_B | UTMIP_AN_C |
730                         UTMIP_HIGHZ_C | UTMIP_AN_D | UTMIP_HIGHZ_D);
731                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
732         } else {
733                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
734                 val &= ~(UTMIP_AP_B | UTMIP_HIGHZ_B | UTMIP_AP_C |
735                         UTMIP_HIGHZ_C | UTMIP_AP_D | UTMIP_HIGHZ_D);
736                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
737         }
738
739         /* turn on pad detectors */
740         val = readl(pmc_base + PMC_USB_AO);
741         val &= ~(USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
742         writel(val, pmc_base + PMC_USB_AO);
743
744         /* Add small delay before usb detectors provide stable line values */
745         mdelay(1);
746
747         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
748         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
749         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
750         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
751
752         phy->remote_wakeup = false;
753
754         /* Turn over pad configuration to PMC  for line wake events*/
755         val = readl(pmc_base + PMC_SLEEP_CFG);
756         val &= ~UTMIP_WAKE_VAL(inst, ~0);
757         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_ANY);
758         val |= UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst);
759         val |= UTMIP_MASTER_ENABLE(inst) | UTMIP_FSLS_USE_PMC(inst);
760         writel(val, pmc_base + PMC_SLEEP_CFG);
761
762         val = readl(base + UTMIP_PMC_WAKEUP0);
763         val |= EVENT_INT_ENB;
764         writel(val, base + UTMIP_PMC_WAKEUP0);
765 }
766
767 static void utmip_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy)
768 {
769         unsigned long val;
770         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
771         unsigned  int inst = phy->inst;
772         void __iomem *base = phy->regs;
773
774         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
775
776         val = readl(pmc_base + PMC_SLEEP_CFG);
777         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
778         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
779         writel(val, pmc_base + PMC_SLEEP_CFG);
780
781         val = readl(pmc_base + PMC_TRIGGERS);
782         val |= UTMIP_CLR_WAKE_ALARM(inst) | UTMIP_CLR_WALK_PTR(inst);
783         writel(val, pmc_base + PMC_TRIGGERS);
784
785         val = readl(base + UTMIP_PMC_WAKEUP0);
786         val &= ~EVENT_INT_ENB;
787         writel(val, base + UTMIP_PMC_WAKEUP0);
788
789         /* Disable PMC master mode by clearing MASTER_EN */
790         val = readl(pmc_base + PMC_SLEEP_CFG);
791         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
792                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
793         writel(val, pmc_base + PMC_SLEEP_CFG);
794
795         val = readl(pmc_base + PMC_TRIGGERS);
796         val &= ~UTMIP_CAP_CFG(inst);
797         writel(val, pmc_base + PMC_TRIGGERS);
798
799         /* turn off pad detectors */
800         val = readl(pmc_base + PMC_USB_AO);
801         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
802         writel(val, pmc_base + PMC_USB_AO);
803
804         phy->remote_wakeup = false;
805 }
806
807 static bool utmi_phy_remotewake_detected(struct tegra_usb_phy *phy)
808 {
809         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
810         void __iomem *base = phy->regs;
811         unsigned  int inst = phy->inst;
812         u32 val;
813
814         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
815         val = readl(base + UTMIP_PMC_WAKEUP0);
816         if (val & EVENT_INT_ENB) {
817                 val = readl(pmc_base + UTMIP_UHSIC_STATUS);
818                 if (UTMIP_WAKE_ALARM(inst) & val) {
819                         val = readl(pmc_base + PMC_SLEEP_CFG);
820                         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
821                         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
822                         writel(val, pmc_base + PMC_SLEEP_CFG);
823
824                         val = readl(pmc_base + PMC_TRIGGERS);
825                         val |= UTMIP_CLR_WAKE_ALARM(inst) |
826                                 UTMIP_CLR_WALK_PTR(inst);
827                         writel(val, pmc_base + PMC_TRIGGERS);
828
829                         val = readl(base + UTMIP_PMC_WAKEUP0);
830                         val &= ~EVENT_INT_ENB;
831                         writel(val, base + UTMIP_PMC_WAKEUP0);
832                         phy->remote_wakeup = true;
833                         return true;
834                 }
835         }
836         return false;
837 }
838
839 static void utmi_phy_enable_trking_data(struct tegra_usb_phy *phy)
840 {
841         void __iomem *base = IO_ADDRESS(TEGRA_USB_BASE);
842         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
843         static bool init_done = false;
844         u32 val;
845
846         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
847
848         /* Should be done only once after system boot */
849         if (init_done)
850                 return;
851
852         clk_enable(phy->utmi_pad_clk);
853         /* Bias pad MASTER_ENABLE=1 */
854         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
855         val |= BIAS_MASTER_PROG_VAL;
856         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
857
858         /* Setting the tracking length time */
859         val = readl(base + UTMIP_BIAS_CFG1);
860         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
861         val |= UTMIP_BIAS_PDTRK_COUNT(5);
862         writel(val, base + UTMIP_BIAS_CFG1);
863
864         /* Bias PDTRK is Shared and MUST be done from USB1 ONLY, PD_TRK=0 */
865         val = readl(base + UTMIP_BIAS_CFG1);
866         val &= ~UTMIP_BIAS_PDTRK_POWERDOWN;
867         writel(val, base + UTMIP_BIAS_CFG1);
868
869         val = readl(base + UTMIP_BIAS_CFG1);
870         val |= UTMIP_BIAS_PDTRK_POWERUP;
871         writel(val, base + UTMIP_BIAS_CFG1);
872
873         /* Wait for 25usec */
874         udelay(25);
875
876         /* Bias pad MASTER_ENABLE=0 */
877         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
878         val &= ~BIAS_MASTER_PROG_VAL;
879         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
880
881         /* Wait for 1usec */
882         udelay(1);
883
884         /* Bias pad MASTER_ENABLE=1 */
885         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
886         val |= BIAS_MASTER_PROG_VAL;
887         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
888
889         /* Read RCTRL and TCTRL from UTMIP space */
890         val = readl(base + UTMIP_BIAS_STS0);
891         utmip_rctrl_val = ffz(UTMIP_RCTRL_VAL(val));
892         utmip_tctrl_val = ffz(UTMIP_TCTRL_VAL(val));
893
894         /* PD_TRK=1 */
895         val = readl(base + UTMIP_BIAS_CFG1);
896         val |= UTMIP_BIAS_PDTRK_POWERDOWN;
897         writel(val, base + UTMIP_BIAS_CFG1);
898
899         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
900         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
901         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
902         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
903         clk_disable(phy->utmi_pad_clk);
904         init_done = true;
905 }
906
907 static void utmip_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy)
908 {
909         unsigned long val;
910         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
911         unsigned  int inst = phy->inst;
912
913         /* power down UTMIP interfaces */
914         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
915         val |= UTMIP_PWR(inst);
916         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
917
918         /* setup sleep walk usb controller */
919         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
920                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
921                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
922                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
923         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
924
925         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
926         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
927         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
928         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
929
930         /* Turn over pad configuration to PMC */
931         val = readl(pmc_base + PMC_SLEEP_CFG);
932         val &= ~UTMIP_WAKE_VAL(inst, ~0);
933         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE) |
934                 UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
935                 UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst);
936         writel(val, pmc_base + PMC_SLEEP_CFG);
937 }
938
939 static void utmip_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
940 {
941         unsigned long val;
942         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
943         unsigned  int inst = phy->inst;
944
945         /* Disable PMC master mode by clearing MASTER_EN */
946         val = readl(pmc_base + PMC_SLEEP_CFG);
947         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
948                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
949         writel(val, pmc_base + PMC_SLEEP_CFG);
950         mdelay(1);
951 }
952
953 static void uhsic_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
954 {
955         unsigned long val;
956         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
957
958         /* turn on pad detectors for HSIC*/
959         val = readl(pmc_base + PMC_USB_AO);
960         val &= ~(HSIC_RESERVED_P0 | HSIC_STOBE_VAL_PD_P0 | HSIC_DATA_VAL_PD_P0);
961         writel(val, pmc_base + PMC_USB_AO);
962
963         /* Disable PMC master mode by clearing MASTER_EN */
964         val = readl(pmc_base + PMC_SLEEP_CFG);
965         val &= ~(UHSIC_MASTER_ENABLE_P0);
966         writel(val, pmc_base + PMC_SLEEP_CFG);
967         mdelay(1);
968 }
969
970 static int usb_phy_bringup_host_controller(struct tegra_usb_phy *phy)
971 {
972         unsigned long val;
973         void __iomem *base = phy->regs;
974
975         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
976         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n",
977                 readl(base + USB_USBSTS), readl(base + USB_PORTSC),
978                                                         phy->port_speed);
979
980         /* Enable Port Power */
981         val = readl(base + USB_PORTSC);
982         val |= USB_PORTSC_PP;
983         writel(val, base + USB_PORTSC);
984         udelay(10);
985
986         /* Check if the phy resume from LP0. When the phy resume from LP0
987          * USB register will be reset.to zero */
988         if (!readl(base + USB_ASYNCLISTADDR)) {
989                 /* Program the field PTC based on the saved speed mode */
990                 val = readl(base + USB_PORTSC);
991                 val &= ~USB_PORTSC_PTC(~0);
992                 if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH)
993                         val |= USB_PORTSC_PTC(5);
994                 else if (phy->port_speed == USB_PHY_PORT_SPEED_FULL)
995                         val |= USB_PORTSC_PTC(6);
996                 else if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
997                         val |= USB_PORTSC_PTC(7);
998                 writel(val, base + USB_PORTSC);
999                 udelay(10);
1000
1001                 /* Disable test mode by setting PTC field to NORMAL_OP */
1002                 val = readl(base + USB_PORTSC);
1003                 val &= ~USB_PORTSC_PTC(~0);
1004                 writel(val, base + USB_PORTSC);
1005                 udelay(10);
1006         }
1007
1008         /* Poll until CCS is enabled */
1009         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
1010                                                  USB_PORTSC_CCS, 2000)) {
1011                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
1012         }
1013
1014         /* Poll until PE is enabled */
1015         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_PE,
1016                                                  USB_PORTSC_PE, 2000)) {
1017                 pr_err("%s: timeout waiting for USB_PORTSC_PE\n", __func__);
1018         }
1019
1020         /* Clear the PCI status, to avoid an interrupt taken upon resume */
1021         val = readl(base + USB_USBSTS);
1022         val |= USB_USBSTS_PCI;
1023         writel(val, base + USB_USBSTS);
1024
1025         /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
1026         val = readl(base + USB_PORTSC);
1027         if ((val & USB_PORTSC_PP) && (val & USB_PORTSC_PE)) {
1028                 val |= USB_PORTSC_SUSP;
1029                 writel(val, base + USB_PORTSC);
1030                 /* Need a 4ms delay before the controller goes to suspend */
1031                 mdelay(4);
1032
1033                 /* Wait until port suspend completes */
1034                 if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_SUSP,
1035                                                  USB_PORTSC_SUSP, 1000)) {
1036                         pr_err("%s: timeout waiting for PORT_SUSPEND\n",
1037                                                                 __func__);
1038                 }
1039         }
1040
1041         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1042                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1043         return 0;
1044 }
1045
1046 static void usb_phy_wait_for_sof(struct tegra_usb_phy *phy)
1047 {
1048         unsigned long val;
1049         void __iomem *base = phy->regs;
1050
1051         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1052
1053         val = readl(base + USB_USBSTS);
1054         writel(val, base + USB_USBSTS);
1055         udelay(20);
1056         /* wait for two SOFs */
1057         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1058                 USB_USBSTS_SRI, 2500))
1059                 pr_err("%s: timeout waiting for SOF\n", __func__);
1060
1061         val = readl(base + USB_USBSTS);
1062         writel(val, base + USB_USBSTS);
1063         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI, 0, 2500))
1064                 pr_err("%s: timeout waiting for SOF\n", __func__);
1065
1066         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_SRI,
1067                         USB_USBSTS_SRI, 2500))
1068                 pr_err("%s: timeout waiting for SOF\n", __func__);
1069
1070         udelay(20);
1071 }
1072
1073 static unsigned int utmi_phy_xcvr_setup_value(struct tegra_usb_phy *phy)
1074 {
1075         struct tegra_utmi_config *cfg = &phy->pdata->u_cfg.utmi;
1076         signed long val;
1077
1078         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1079
1080         if (cfg->xcvr_use_fuses) {
1081                 val = FUSE_USB_CALIB_XCVR_SETUP(
1082                                 tegra_fuse_readl(FUSE_USB_CALIB_0));
1083                 if (cfg->xcvr_setup_offset <= UTMIP_XCVR_MAX_OFFSET)
1084                         val = val + cfg->xcvr_setup_offset;
1085
1086                 if (val > UTMIP_XCVR_SETUP_MAX_VALUE) {
1087                         val = UTMIP_XCVR_SETUP_MAX_VALUE;
1088                         pr_info("%s: reset XCVR_SETUP to max value\n",
1089                                  __func__);
1090                 } else if (val < UTMIP_XCVR_SETUP_MIN_VALUE) {
1091                         val = UTMIP_XCVR_SETUP_MIN_VALUE;
1092                         pr_info("%s: reset XCVR_SETUP to min value\n",
1093                                  __func__);
1094                 }
1095         } else {
1096                 val = cfg->xcvr_setup;
1097         }
1098
1099         return (unsigned int) val;
1100 }
1101
1102 static int utmi_phy_open(struct tegra_usb_phy *phy)
1103 {
1104         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1105         unsigned long parent_rate, val;
1106         int i;
1107
1108         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1109
1110         phy->utmi_pad_clk = clk_get_sys("utmip-pad", NULL);
1111         if (IS_ERR(phy->utmi_pad_clk)) {
1112                 pr_err("%s: can't get utmip pad clock\n", __func__);
1113                 return PTR_ERR(phy->utmi_pad_clk);
1114         }
1115
1116         phy->utmi_xcvr_setup = utmi_phy_xcvr_setup_value(phy);
1117
1118         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
1119         for (i = 0; i < ARRAY_SIZE(utmip_freq_table); i++) {
1120                 if (utmip_freq_table[i].freq == parent_rate) {
1121                         phy->freq = &utmip_freq_table[i];
1122                         break;
1123                 }
1124         }
1125         if (!phy->freq) {
1126                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
1127                 return -EINVAL;
1128         }
1129
1130         /* Power-up the VBUS detector for UTMIP PHY */
1131         val = readl(pmc_base + PMC_USB_AO);
1132         val &= ~(PMC_USB_AO_VBUS_WAKEUP_PD_P0 | PMC_USB_AO_ID_PD_P0);
1133         writel((val | PMC_USB_AO_PD_P2), (pmc_base + PMC_USB_AO));
1134
1135         utmip_powerup_pmc_wake_detect(phy);
1136
1137         return 0;
1138 }
1139
1140 static void utmi_phy_close(struct tegra_usb_phy *phy)
1141 {
1142         unsigned long val;
1143         void __iomem *base = phy->regs;
1144
1145         DBG("%s inst:[%d]\n", __func__, phy->inst);
1146
1147         /* Disable PHY clock valid interrupts while going into suspend*/
1148         if (phy->pdata->u_data.host.hot_plug) {
1149                 val = readl(base + USB_SUSP_CTRL);
1150                 val &= ~USB_PHY_CLK_VALID_INT_ENB;
1151                 writel(val, base + USB_SUSP_CTRL);
1152         }
1153
1154         val = readl(base + USB_PORTSC);
1155         val |= USB_PORTSC_WKCN;
1156         writel(val, base + USB_PORTSC);
1157
1158         clk_put(phy->utmi_pad_clk);
1159 }
1160
1161 static int utmi_phy_pad_power_on(struct tegra_usb_phy *phy)
1162 {
1163         unsigned long val, flags;
1164         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1165
1166         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1167
1168         clk_enable(phy->utmi_pad_clk);
1169
1170         spin_lock_irqsave(&utmip_pad_lock, flags);
1171         utmip_pad_count++;
1172
1173         val = readl(pad_base + UTMIP_BIAS_CFG0);
1174         val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
1175         val |= UTMIP_HSSQUELCH_LEVEL(0x2) | UTMIP_HSDISCON_LEVEL(0x1) |
1176                 UTMIP_HSDISCON_LEVEL_MSB;
1177         writel(val, pad_base + UTMIP_BIAS_CFG0);
1178
1179         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1180
1181         clk_disable(phy->utmi_pad_clk);
1182
1183         return 0;
1184 }
1185
1186 static int utmi_phy_pad_power_off(struct tegra_usb_phy *phy)
1187 {
1188         unsigned long val, flags;
1189         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1190
1191         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1192
1193         clk_enable(phy->utmi_pad_clk);
1194         spin_lock_irqsave(&utmip_pad_lock, flags);
1195
1196         if (!utmip_pad_count) {
1197                 pr_err("%s: utmip pad already powered off\n", __func__);
1198                 goto out;
1199         }
1200         if (--utmip_pad_count == 0) {
1201                 val = readl(pad_base + UTMIP_BIAS_CFG0);
1202                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
1203                 val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) | UTMIP_HSDISCON_LEVEL(~0) |
1204                         UTMIP_HSDISCON_LEVEL_MSB);
1205                 writel(val, pad_base + UTMIP_BIAS_CFG0);
1206         }
1207 out:
1208         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1209         clk_disable(phy->utmi_pad_clk);
1210
1211         return 0;
1212 }
1213
1214 static int utmi_phy_irq(struct tegra_usb_phy *phy)
1215 {
1216         void __iomem *base = phy->regs;
1217         unsigned long val = 0;
1218
1219         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1220         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1221                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1222         DBG("USB_USBMODE[0x%x] USB_USBCMD[0x%x]\n",
1223                         readl(base + USB_USBMODE), readl(base + USB_USBCMD));
1224
1225         /* check if there is any remote wake event */
1226         if (utmi_phy_remotewake_detected(phy))
1227                 pr_info("%s: utmip remote wake detected\n", __func__);
1228
1229         if (phy->pdata->u_data.host.hot_plug) {
1230                 val = readl(base + USB_SUSP_CTRL);
1231                 if ((val  & USB_PHY_CLK_VALID_INT_STS)) {
1232                         val &= ~USB_PHY_CLK_VALID_INT_ENB |
1233                                         USB_PHY_CLK_VALID_INT_STS;
1234                         writel(val , (base + USB_SUSP_CTRL));
1235                         pr_info("%s: usb device plugged-in\n", __func__);
1236                         val = readl(base + USB_USBSTS);
1237                         if (!(val  & USB_USBSTS_PCI))
1238                                 return IRQ_NONE;
1239                         val = readl(base + USB_PORTSC);
1240                         val &= ~(USB_PORTSC_WKCN | USB_PORTSC_RWC_BITS);
1241                         writel(val , (base + USB_PORTSC));
1242                 }
1243         }
1244
1245         return IRQ_HANDLED;
1246 }
1247
1248 static int utmi_phy_post_resume(struct tegra_usb_phy *phy)
1249 {
1250         unsigned long val;
1251         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1252         unsigned  int inst = phy->inst;
1253
1254         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1255         val = readl(pmc_base + PMC_SLEEP_CFG);
1256         /* if PMC is not disabled by now then disable it */
1257         if (val & UTMIP_MASTER_ENABLE(inst)) {
1258                 utmip_phy_disable_pmc_bus_ctrl(phy);
1259         }
1260
1261         return 0;
1262 }
1263
1264 static int utmi_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1265 {
1266         unsigned long val;
1267         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1268         unsigned  int inst = phy->inst;
1269
1270         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1271         val = readl(pmc_base + PMC_SLEEP_CFG);
1272         if (val & UTMIP_MASTER_ENABLE(inst)) {
1273                 if (!remote_wakeup)
1274                         utmip_phy_disable_pmc_bus_ctrl(phy);
1275         }
1276
1277         return 0;
1278 }
1279
1280 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
1281 {
1282         unsigned long val;
1283         void __iomem *base = phy->regs;
1284
1285         DBG("%s(%d) inst:[%d] BEGIN\n", __func__, __LINE__, phy->inst);
1286         if (!phy->phy_clk_on) {
1287                 DBG("%s(%d) inst:[%d] phy clk is already off\n",
1288                                         __func__, __LINE__, phy->inst);
1289                 return 0;
1290         }
1291
1292         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1293                 utmip_powerdown_pmc_wake_detect(phy);
1294
1295                 val = readl(base + USB_SUSP_CTRL);
1296                 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
1297                 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
1298                 writel(val, base + USB_SUSP_CTRL);
1299
1300                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1301                 val |= UTMIP_PD_CHRG;
1302                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1303         } else {
1304                 utmip_setup_pmc_wake_detect(phy);
1305         }
1306
1307         if (!phy->pdata->u_data.host.hot_plug) {
1308                 val = readl(base + UTMIP_XCVR_CFG0);
1309                 val |= (UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
1310                          UTMIP_FORCE_PDZI_POWERDOWN);
1311                 writel(val, base + UTMIP_XCVR_CFG0);
1312         }
1313
1314         val = readl(base + UTMIP_XCVR_CFG1);
1315         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1316                    UTMIP_FORCE_PDDR_POWERDOWN;
1317         writel(val, base + UTMIP_XCVR_CFG1);
1318
1319         val = readl(base + UTMIP_BIAS_CFG1);
1320         val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
1321         writel(val, base + UTMIP_BIAS_CFG1);
1322
1323         utmi_phy_pad_power_off(phy);
1324
1325         phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
1326                         HOSTPC1_DEVLC_PSPD_MASK;
1327
1328         if (phy->pdata->u_data.host.hot_plug) {
1329                 bool enable_hotplug = true;
1330                 /* if it is OTG port then make sure to enable hot-plug feature
1331                    only if host adaptor is connected, i.e id is low */
1332                 if (phy->pdata->port_otg) {
1333                         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1334                         enable_hotplug = (val & USB_ID_STATUS) ? false : true;
1335                 }
1336                 if (enable_hotplug) {
1337                         val = readl(base + USB_PORTSC);
1338                         val |= USB_PORTSC_WKCN;
1339                         writel(val, base + USB_PORTSC);
1340
1341                         val = readl(base + USB_SUSP_CTRL);
1342                         val |= USB_PHY_CLK_VALID_INT_ENB;
1343                         writel(val, base + USB_SUSP_CTRL);
1344                 } else {
1345                         /* Disable PHY clock valid interrupts while going into suspend*/
1346                         val = readl(base + USB_SUSP_CTRL);
1347                         val &= ~USB_PHY_CLK_VALID_INT_ENB;
1348                         writel(val, base + USB_SUSP_CTRL);
1349                 }
1350         }
1351
1352         if (phy->inst == 0) {
1353                         val = readl(base + USB_SUSP_CTRL);
1354                         val |= UTMIP_RESET;
1355                         writel(val, base + USB_SUSP_CTRL);
1356         }
1357
1358         val = readl(base + HOSTPC1_DEVLC);
1359         val |= HOSTPC1_DEVLC_PHCD;
1360         writel(val, base + HOSTPC1_DEVLC);
1361
1362         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
1363                                                                 0, 2500))
1364                 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
1365
1366         phy->phy_clk_on = false;
1367         phy->hw_accessible = false;
1368
1369         DBG("%s(%d) inst:[%d] END\n", __func__, __LINE__, phy->inst);
1370
1371         return 0;
1372 }
1373
1374
1375 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
1376 {
1377         unsigned long val;
1378         void __iomem *base = phy->regs;
1379         struct tegra_utmi_config *config = &phy->pdata->u_cfg.utmi;
1380
1381         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1382         if (phy->phy_clk_on) {
1383                 DBG("%s(%d) inst:[%d] phy clk is already On\n",
1384                                         __func__, __LINE__, phy->inst);
1385                 return 0;
1386         }
1387         val = readl(base + USB_SUSP_CTRL);
1388         val |= UTMIP_RESET;
1389         writel(val, base + USB_SUSP_CTRL);
1390
1391         val = readl(base + UTMIP_TX_CFG0);
1392         val |= UTMIP_FS_PREABMLE_J;
1393         writel(val, base + UTMIP_TX_CFG0);
1394
1395         val = readl(base + UTMIP_HSRX_CFG0);
1396         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
1397         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
1398         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
1399         writel(val, base + UTMIP_HSRX_CFG0);
1400
1401         val = readl(base + UTMIP_HSRX_CFG1);
1402         val &= ~UTMIP_HS_SYNC_START_DLY(~0);
1403         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
1404         writel(val, base + UTMIP_HSRX_CFG1);
1405
1406         val = readl(base + UTMIP_DEBOUNCE_CFG0);
1407         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
1408         val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
1409         writel(val, base + UTMIP_DEBOUNCE_CFG0);
1410
1411         val = readl(base + UTMIP_MISC_CFG0);
1412         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
1413         writel(val, base + UTMIP_MISC_CFG0);
1414
1415         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1416                 val = readl(base + USB_SUSP_CTRL);
1417                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
1418                 writel(val, base + USB_SUSP_CTRL);
1419
1420                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1421                 val &= ~UTMIP_PD_CHRG;
1422                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1423         } else {
1424                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1425                 val |= UTMIP_PD_CHRG;
1426                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1427         }
1428
1429         utmi_phy_pad_power_on(phy);
1430
1431         val = readl(base + UTMIP_XCVR_CFG0);
1432         val &= ~(UTMIP_XCVR_LSBIAS_SEL | UTMIP_FORCE_PD_POWERDOWN |
1433                  UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN |
1434                  UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_LSFSLEW(~0) |
1435                  UTMIP_XCVR_LSRSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
1436         val |= UTMIP_XCVR_SETUP(phy->utmi_xcvr_setup);
1437         val |= UTMIP_XCVR_SETUP_MSB(XCVR_SETUP_MSB_CALIB(phy->utmi_xcvr_setup));
1438         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
1439         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
1440         val |= UTMIP_XCVR_HSSLEW_MSB(0x8);
1441         writel(val, base + UTMIP_XCVR_CFG0);
1442
1443         val = readl(base + UTMIP_XCVR_CFG1);
1444         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1445                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
1446         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
1447         writel(val, base + UTMIP_XCVR_CFG1);
1448
1449         val = readl(base + UTMIP_BIAS_CFG1);
1450         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
1451         val |= UTMIP_BIAS_PDTRK_COUNT(phy->freq->pdtrk_count);
1452         writel(val, base + UTMIP_BIAS_CFG1);
1453
1454         val = readl(base + UTMIP_SPARE_CFG0);
1455         val &= ~FUSE_SETUP_SEL;
1456         val |= FUSE_ATERM_SEL;
1457         writel(val, base + UTMIP_SPARE_CFG0);
1458
1459         val = readl(base + USB_SUSP_CTRL);
1460         val |= UTMIP_PHY_ENABLE;
1461         writel(val, base + USB_SUSP_CTRL);
1462
1463         val = readl(base + USB_SUSP_CTRL);
1464         val &= ~UTMIP_RESET;
1465         writel(val, base + USB_SUSP_CTRL);
1466
1467         val = readl(base + HOSTPC1_DEVLC);
1468         val &= ~HOSTPC1_DEVLC_PHCD;
1469         writel(val, base + HOSTPC1_DEVLC);
1470
1471         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1472                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500))
1473                 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
1474
1475         utmi_phy_enable_trking_data(phy);
1476
1477         if (phy->inst == 2)
1478                 writel(0, base + ICUSB_CTRL);
1479
1480         val = readl(base + USB_USBMODE);
1481         val &= ~USB_USBMODE_MASK;
1482         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST)
1483                 val |= USB_USBMODE_HOST;
1484         else
1485                 val |= USB_USBMODE_DEVICE;
1486         writel(val, base + USB_USBMODE);
1487
1488         val = readl(base + HOSTPC1_DEVLC);
1489         val &= ~HOSTPC1_DEVLC_PTS(~0);
1490         val |= HOSTPC1_DEVLC_STS;
1491         writel(val, base + HOSTPC1_DEVLC);
1492
1493         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE)
1494                 utmip_powerup_pmc_wake_detect(phy);
1495         phy->phy_clk_on = true;
1496         phy->hw_accessible = true;
1497         DBG("%s(%d) End\n", __func__, __LINE__);
1498
1499         return 0;
1500 }
1501
1502 static void utmi_phy_restore_start(struct tegra_usb_phy *phy)
1503 {
1504         unsigned long val;
1505         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1506         int inst = phy->inst;
1507
1508         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1509         val = readl(pmc_base + UTMIP_UHSIC_STATUS);
1510         /* check whether we wake up from the remote resume */
1511         if (UTMIP_WALK_PTR_VAL(inst) & val) {
1512                 phy->remote_wakeup = true;
1513         } else {
1514                 if (!((UTMIP_USBON_VAL(phy->inst) |
1515                         UTMIP_USBOP_VAL(phy->inst)) & val)) {
1516                                 utmip_phy_disable_pmc_bus_ctrl(phy);
1517                 }
1518         }
1519 }
1520
1521 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
1522 {
1523         unsigned long val;
1524         void __iomem *base = phy->regs;
1525         int wait_time_us = 3000; /* FPR should be set by this time */
1526
1527         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1528         /* check whether we wake up from the remote resume */
1529         if (phy->remote_wakeup) {
1530                 /* wait until FPR bit is set automatically on remote resume */
1531                 do {
1532                         val = readl(base + USB_PORTSC);
1533                         udelay(1);
1534                         if (wait_time_us == 0)
1535                                 return;
1536                         wait_time_us--;
1537                 } while (!(val & USB_PORTSC_RESUME));
1538                 /* wait for 25 ms to port resume complete */
1539                 msleep(25);
1540                 /* disable PMC master control */
1541                 utmip_phy_disable_pmc_bus_ctrl(phy);
1542
1543                 /* Clear PCI and SRI bits to avoid an interrupt upon resume */
1544                 val = readl(base + USB_USBSTS);
1545                 writel(val, base + USB_USBSTS);
1546                 /* wait to avoid SOF if there is any */
1547                 if (usb_phy_reg_status_wait(base + USB_USBSTS,
1548                         USB_USBSTS_SRI, USB_USBSTS_SRI, 2500) < 0) {
1549                         pr_err("%s: timeout waiting for SOF\n", __func__);
1550                 }
1551                 utmi_phy_post_resume(phy);
1552         }
1553 }
1554
1555 static int utmi_phy_resume(struct tegra_usb_phy *phy)
1556 {
1557         int status = 0;
1558         unsigned long val;
1559         void __iomem *base = phy->regs;
1560
1561         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1562         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) {
1563                 if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
1564                         utmi_phy_restore_start(phy);
1565                         usb_phy_bringup_host_controller(phy);
1566                         utmi_phy_restore_end(phy);
1567                 } else {
1568                         /* device is plugged in when system is in LP0 */
1569                         /* bring up the controller from LP0*/
1570                         val = readl(base + USB_USBCMD);
1571                         val |= USB_CMD_RESET;
1572                         writel(val, base + USB_USBCMD);
1573
1574                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1575                                 USB_CMD_RESET, 0, 2500) < 0) {
1576                                 pr_err("%s: timeout waiting for reset\n", __func__);
1577                         }
1578
1579                         val = readl(base + USB_USBMODE);
1580                         val &= ~USB_USBMODE_MASK;
1581                         val |= USB_USBMODE_HOST;
1582                         writel(val, base + USB_USBMODE);
1583
1584                         val = readl(base + HOSTPC1_DEVLC);
1585                         val &= ~HOSTPC1_DEVLC_PTS(~0);
1586                         val |= HOSTPC1_DEVLC_STS;
1587                         writel(val, base + HOSTPC1_DEVLC);
1588
1589                         writel(USB_USBCMD_RS, base + USB_USBCMD);
1590
1591                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1592                                 USB_USBCMD_RS, USB_USBCMD_RS, 2500) < 0) {
1593                                 pr_err("%s: timeout waiting for run bit\n", __func__);
1594                         }
1595
1596                         /* Enable Port Power */
1597                         val = readl(base + USB_PORTSC);
1598                         val |= USB_PORTSC_PP;
1599                         writel(val, base + USB_PORTSC);
1600                         udelay(10);
1601
1602                         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1603                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1604                 }
1605         }
1606
1607         return status;
1608 }
1609
1610 static bool utmi_phy_charger_detect(struct tegra_usb_phy *phy)
1611 {
1612         unsigned long val;
1613         void __iomem *base = phy->regs;
1614         bool status;
1615
1616         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1617         if (phy->pdata->op_mode != TEGRA_USB_OPMODE_DEVICE) {
1618                 /* Charger detection is not there for ULPI
1619                  * return Charger not available */
1620                 return false;
1621         }
1622
1623         /* Enable charger detection logic */
1624         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1625         val |= UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN;
1626         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1627
1628         /* Source should be on for 100 ms as per USB charging spec */
1629         msleep(TDP_SRC_ON_MS);
1630
1631         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1632         /* If charger is not connected disable the interrupt */
1633         val &= ~VDAT_DET_INT_EN;
1634         val |= VDAT_DET_CHG_DET;
1635         writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
1636
1637         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1638         if (val & VDAT_DET_STS)
1639                 status = true;
1640         else
1641                 status = false;
1642
1643         /* Disable charger detection logic */
1644         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1645         val &= ~(UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN);
1646         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1647
1648         /* Delay of 40 ms before we pull the D+ as per battery charger spec */
1649         msleep(TDPSRC_CON_MS);
1650
1651         return status;
1652 }
1653
1654 static void uhsic_setup_pmc_wake_detect(struct tegra_usb_phy *phy)
1655 {
1656         unsigned long val;
1657         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1658         void __iomem *base = phy->regs;
1659         bool port_connected;
1660
1661         DBG("%s:%d\n", __func__, __LINE__);
1662
1663         /* check for port connect status */
1664         val = readl(base + USB_PORTSC);
1665         port_connected = val & USB_PORTSC_CCS;
1666
1667         if (!port_connected)
1668                 return;
1669
1670         /*Set PMC MASTER bits to do the following
1671         * a. Take over the hsic drivers
1672         * b. set up such that it will take over resume
1673         *        if remote wakeup is detected
1674         * Prepare PMC to take over suspend-wake detect-drive resume until USB
1675         * controller ready
1676         */
1677
1678         /* disable master enable in PMC */
1679         val = readl(pmc_base + PMC_SLEEP_CFG);
1680         val &= ~UHSIC_MASTER_ENABLE_P0;
1681         writel(val, pmc_base + PMC_SLEEP_CFG);
1682
1683         /* UTMIP_PWR_PX=1 for power savings mode */
1684         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
1685         val |= UHSIC_PWR;
1686         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
1687
1688         /* Enable which type of event can trigger a walk,
1689         * in this case usb_line_wake */
1690         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
1691         val |= UHSIC_LINEVAL_WALK_EN;
1692         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
1693
1694         /* program walk sequence, maintain a J, followed by a driven K
1695         * to signal a resume once an wake event is detected */
1696
1697         val = readl(pmc_base + PMC_SLEEPWALK_UHSIC);
1698
1699         val &= ~UHSIC_DATA_RPU_A;
1700         val |=  UHSIC_DATA_RPD_A;
1701         val &= ~UHSIC_STROBE_RPD_A;
1702         val |=  UHSIC_STROBE_RPU_A;
1703         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1704
1705         val &= ~UHSIC_DATA_RPD_B;
1706         val |=  UHSIC_DATA_RPU_B;
1707         val &= ~UHSIC_STROBE_RPU_B;
1708         val |=  UHSIC_STROBE_RPD_B;
1709         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1710
1711         val &= ~UHSIC_DATA_RPD_C;
1712         val |=  UHSIC_DATA_RPU_C;
1713         val &= ~UHSIC_STROBE_RPU_C;
1714         val |=  UHSIC_STROBE_RPD_C;
1715         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1716
1717         val &= ~UHSIC_DATA_RPD_D;
1718         val |=  UHSIC_DATA_RPU_D;
1719         val &= ~UHSIC_STROBE_RPU_D;
1720         val |=  UHSIC_STROBE_RPD_D;
1721         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC);
1722
1723         /* turn on pad detectors */
1724         val = readl(pmc_base + PMC_USB_AO);
1725         val &= ~(STROBE_VAL_PD_P0 | DATA_VAL_PD_P0);
1726         writel(val, pmc_base + PMC_USB_AO);
1727         /* Add small delay before usb detectors provide stable line values */
1728         udelay(1);
1729
1730         phy->remote_wakeup = false;
1731
1732         /* Turn over pad configuration to PMC  for line wake events*/
1733         val = readl(pmc_base + PMC_SLEEP_CFG);
1734         val &= ~UHSIC_WAKE_VAL(~0);
1735         val |= UHSIC_WAKE_VAL(WAKE_VAL_SD10);
1736         val |= UHSIC_MASTER_ENABLE;
1737         writel(val, pmc_base + PMC_SLEEP_CFG);
1738
1739         val = readl(base + UHSIC_PMC_WAKEUP0);
1740         val |= EVENT_INT_ENB;
1741         writel(val, base + UHSIC_PMC_WAKEUP0);
1742
1743         DBG("%s:PMC enabled for HSIC remote wakeup\n", __func__);
1744 }
1745
1746 static void uhsic_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy)
1747 {
1748         unsigned long val;
1749         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1750         void __iomem *base = phy->regs;
1751
1752         DBG("%s (%d)\n", __func__, __LINE__);
1753         val = readl(pmc_base + PMC_SLEEP_CFG);
1754         val &= ~UHSIC_WAKE_VAL(0x0);
1755         val |= UHSIC_WAKE_VAL(WAKE_VAL_NONE);
1756         writel(val, pmc_base + PMC_SLEEP_CFG);
1757
1758         val = readl(pmc_base + PMC_TRIGGERS);
1759         val |= UHSIC_CLR_WAKE_ALARM_P0 | UHSIC_CLR_WALK_PTR_P0;
1760         writel(val, pmc_base + PMC_TRIGGERS);
1761
1762         val = readl(base + UHSIC_PMC_WAKEUP0);
1763         val &= ~EVENT_INT_ENB;
1764         writel(val, base + UHSIC_PMC_WAKEUP0);
1765
1766         /* Disable PMC master mode by clearing MASTER_EN */
1767         val = readl(pmc_base + PMC_SLEEP_CFG);
1768         val &= ~(UHSIC_MASTER_ENABLE);
1769         writel(val, pmc_base + PMC_SLEEP_CFG);
1770
1771         /* turn off pad detectors */
1772         val = readl(pmc_base + PMC_USB_AO);
1773         val |= (STROBE_VAL_PD_P0 | DATA_VAL_PD_P0);
1774         writel(val, pmc_base + PMC_USB_AO);
1775
1776         phy->remote_wakeup = false;
1777 }
1778
1779 static int uhsic_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1780 {
1781         DBG("%s(%d)\n", __func__, __LINE__);
1782
1783         if (!remote_wakeup)
1784                 usb_phy_wait_for_sof(phy);
1785
1786         return 0;
1787 }
1788
1789 static int uhsic_phy_post_resume(struct tegra_usb_phy *phy)
1790 {
1791         unsigned long val;
1792         void __iomem *base = phy->regs;
1793
1794         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1795         val = readl(base + USB_TXFILLTUNING);
1796         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
1797                 val = USB_FIFO_TXFILL_THRES(0x10);
1798                 writel(val, base + USB_TXFILLTUNING);
1799         }
1800
1801         return 0;
1802 }
1803
1804 static void uhsic_phy_restore_start(struct tegra_usb_phy *phy)
1805 {
1806         unsigned long val;
1807         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1808         void __iomem *base = phy->regs;
1809
1810         val = readl(pmc_base + UTMIP_UHSIC_STATUS);
1811
1812         /* check whether we wake up from the remote resume */
1813         if (UHSIC_WALK_PTR_VAL & val) {
1814                 phy->remote_wakeup = true;
1815                 pr_info("%s: uhsic remote wakeup detected\n", __func__);
1816         } else {
1817                 if (!((UHSIC_STROBE_VAL_P0 | UHSIC_DATA_VAL_P0) & val)) {
1818                                 uhsic_phy_disable_pmc_bus_ctrl(phy);
1819                 } else {
1820                         DBG("%s(%d): setting pretend connect\n", __func__, __LINE__);
1821                         val = readl(base + UHSIC_CMD_CFG0);
1822                         val |= UHSIC_PRETEND_CONNECT_DETECT;
1823                         writel(val, base + UHSIC_CMD_CFG0);
1824                 }
1825         }
1826 }
1827
1828 static void uhsic_phy_restore_end(struct tegra_usb_phy *phy)
1829 {
1830
1831         unsigned long val;
1832         void __iomem *base = phy->regs;
1833         int wait_time_us = 3000; /* FPR should be set by this time */
1834
1835         DBG("%s(%d)\n", __func__, __LINE__);
1836
1837         /* check whether we wake up from the remote resume */
1838         if (phy->remote_wakeup) {
1839                 /* wait until FPR bit is set automatically on remote resume */
1840                 do {
1841                         val = readl(base + USB_PORTSC);
1842                         udelay(1);
1843                         if (wait_time_us == 0) {
1844                                 uhsic_phy_disable_pmc_bus_ctrl(phy);
1845                                 uhsic_phy_post_resume(phy);
1846                                 return;
1847                         }
1848                         wait_time_us--;
1849                 } while (!(val & USB_PORTSC_RESUME));
1850                 /* wait for 25 ms to port resume complete */
1851                 msleep(25);
1852                 /* disable PMC master control */
1853                 uhsic_phy_disable_pmc_bus_ctrl(phy);
1854
1855                 /* Clear PCI and SRI bits to avoid an interrupt upon resume */
1856                 val = readl(base + USB_USBSTS);
1857                 writel(val, base + USB_USBSTS);
1858                 /* wait to avoid SOF if there is any */
1859                 if (usb_phy_reg_status_wait(base + USB_USBSTS,
1860                         USB_USBSTS_SRI, USB_USBSTS_SRI, 2500)) {
1861                         pr_warn("%s: timeout waiting for SOF\n", __func__);
1862                 }
1863                 uhsic_phy_post_resume(phy);
1864         } else {
1865                 uhsic_phy_disable_pmc_bus_ctrl(phy);
1866         }
1867
1868         /* Set RUN bit */
1869         val = readl(base + USB_USBCMD);
1870         val |= USB_USBCMD_RS;
1871         writel(val, base + USB_USBCMD);
1872         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
1873                                                  USB_USBCMD_RS, 2000)) {
1874                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
1875                 return;
1876         }
1877 }
1878
1879 static bool uhsic_phy_remotewake_detected(struct tegra_usb_phy *phy)
1880 {
1881         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1882         void __iomem *base = phy->regs;
1883         u32 val;
1884
1885         val = readl(base + UHSIC_PMC_WAKEUP0);
1886         if (val & EVENT_INT_ENB) {
1887                 val = readl(pmc_base + UTMIP_UHSIC_STATUS);
1888                 if (UHSIC_WAKE_ALARM & val) {
1889                         val = readl(pmc_base + PMC_SLEEP_CFG);
1890                         val &= ~UHSIC_WAKE_VAL(0x0);
1891                         val |= UHSIC_WAKE_VAL(WAKE_VAL_NONE);
1892                         writel(val, pmc_base + PMC_SLEEP_CFG);
1893
1894                         val = readl(pmc_base + PMC_TRIGGERS);
1895                         val |= UHSIC_CLR_WAKE_ALARM_P0 | UHSIC_CLR_WALK_PTR_P0;
1896                         writel(val, pmc_base + PMC_TRIGGERS);
1897
1898                         val = readl(base + UHSIC_PMC_WAKEUP0);
1899                         val &= ~EVENT_INT_ENB;
1900                         writel(val, base + UHSIC_PMC_WAKEUP0);
1901                         phy->remote_wakeup = true;
1902                         DBG("%s:PMC remote wakeup detected for HSIC\n", __func__);
1903                         return true;
1904                 }
1905         }
1906         return false;
1907 }
1908
1909 static void usb_phy_fence_read(struct tegra_usb_phy *phy)
1910 {
1911         /* Fence read for coherency of AHB master intiated writes */
1912         if (phy->inst == 0)
1913                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB1_PREFETCH_ID));
1914         else if (phy->inst == 1)
1915                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB2_PREFETCH_ID));
1916         else if (phy->inst == 2)
1917                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB3_PREFETCH_ID));
1918
1919         return;
1920 }
1921
1922 static int uhsic_phy_irq(struct tegra_usb_phy *phy)
1923 {
1924         usb_phy_fence_read(phy);
1925         /* check if there is any remote wake event */
1926         if (uhsic_phy_remotewake_detected(phy))
1927                 pr_info("%s: uhsic remote wake detected\n", __func__);
1928         return IRQ_HANDLED;
1929 }
1930
1931 static int uhsic_phy_open(struct tegra_usb_phy *phy)
1932 {
1933         unsigned long parent_rate;
1934         int i;
1935
1936         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1937         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
1938         for (i = 0; i < ARRAY_SIZE(uhsic_freq_table); i++) {
1939                 if (uhsic_freq_table[i].freq == parent_rate) {
1940                         phy->freq = &uhsic_freq_table[i];
1941                         break;
1942                 }
1943         }
1944         if (!phy->freq) {
1945                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
1946                 return -EINVAL;
1947         }
1948
1949         uhsic_powerup_pmc_wake_detect(phy);
1950
1951         return 0;
1952 }
1953
1954 static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
1955 {
1956         unsigned long val;
1957         void __iomem *base = phy->regs;
1958         struct tegra_hsic_config *config = &phy->pdata->u_cfg.hsic;
1959
1960         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1961
1962         utmip_powerup_pmc_wake_detect(phy);
1963
1964         if (phy->phy_clk_on) {
1965                 DBG("%s(%d) inst:[%d] phy clk is already On\n",
1966                                         __func__, __LINE__, phy->inst);
1967                 return 0;
1968         }
1969
1970         val = readl(base + UHSIC_PADS_CFG1);
1971         val &= ~(UHSIC_PD_BG | UHSIC_PD_TRK | UHSIC_PD_RX |
1972                         UHSIC_PD_ZI | UHSIC_RPD_DATA | UHSIC_RPD_STROBE);
1973         val |= (UHSIC_RX_SEL | UHSIC_PD_TX);
1974         writel(val, base + UHSIC_PADS_CFG1);
1975         udelay(2);
1976
1977         val = readl(base + USB_SUSP_CTRL);
1978         val |= UHSIC_RESET;
1979         writel(val, base + USB_SUSP_CTRL);
1980         udelay(30);
1981
1982         val = readl(base + USB_SUSP_CTRL);
1983         val |= UHSIC_PHY_ENABLE;
1984         writel(val, base + USB_SUSP_CTRL);
1985
1986         val = readl(base + UHSIC_HSRX_CFG0);
1987         val |= UHSIC_IDLE_WAIT(config->idle_wait_delay);
1988         val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(config->elastic_underrun_limit);
1989         val |= UHSIC_ELASTIC_OVERRUN_LIMIT(config->elastic_overrun_limit);
1990         writel(val, base + UHSIC_HSRX_CFG0);
1991
1992         val = readl(base + UHSIC_HSRX_CFG1);
1993         val |= UHSIC_HS_SYNC_START_DLY(config->sync_start_delay);
1994         writel(val, base + UHSIC_HSRX_CFG1);
1995
1996         /* WAR HSIC TX */
1997         val = readl(base + UHSIC_TX_CFG0);
1998         val &= ~UHSIC_HS_READY_WAIT_FOR_VALID;
1999         writel(val, base + UHSIC_TX_CFG0);
2000
2001         val = readl(base + UHSIC_MISC_CFG0);
2002         val |= UHSIC_SUSPEND_EXIT_ON_EDGE;
2003         /* Disable generic bus reset, to allow AP30 specific bus reset*/
2004         val |= UHSIC_DISABLE_BUSRESET;
2005         writel(val, base + UHSIC_MISC_CFG0);
2006
2007         val = readl(base + UHSIC_MISC_CFG1);
2008         val |= UHSIC_PLLU_STABLE_COUNT(phy->freq->stable_count);
2009         writel(val, base + UHSIC_MISC_CFG1);
2010
2011         val = readl(base + UHSIC_PLL_CFG1);
2012         val |= UHSIC_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
2013         val |= UHSIC_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count);
2014         writel(val, base + UHSIC_PLL_CFG1);
2015
2016         val = readl(base + USB_SUSP_CTRL);
2017         val &= ~(UHSIC_RESET);
2018         writel(val, base + USB_SUSP_CTRL);
2019         udelay(1);
2020
2021         val = readl(base + UHSIC_PADS_CFG1);
2022         val &= ~(UHSIC_PD_TX);
2023         writel(val, base + UHSIC_PADS_CFG1);
2024
2025         val = readl(base + USB_USBMODE);
2026         val |= USB_USBMODE_HOST;
2027         writel(val, base + USB_USBMODE);
2028
2029         /* Change the USB controller PHY type to HSIC */
2030         val = readl(base + HOSTPC1_DEVLC);
2031         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
2032         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2033         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
2034         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2035         val &= ~HOSTPC1_DEVLC_STS;
2036         writel(val, base + HOSTPC1_DEVLC);
2037
2038         val = readl(base + USB_TXFILLTUNING);
2039         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
2040                 val = USB_FIFO_TXFILL_THRES(0x10);
2041                 writel(val, base + USB_TXFILLTUNING);
2042         }
2043
2044         val = readl(base + USB_PORTSC);
2045         val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN);
2046         writel(val, base + USB_PORTSC);
2047
2048         val = readl(base + UHSIC_PADS_CFG0);
2049         /* Clear RTUNEN, SLEWP & SLEWN bit fields */
2050         val &= ~(UHSIC_TX_RTUNEN | UHSIC_TX_SLEWP | UHSIC_TX_SLEWN);
2051         /* set Rtune impedance to 50 ohm */
2052         val |= UHSIC_TX_RTUNE(8);
2053         writel(val, base + UHSIC_PADS_CFG0);
2054
2055         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
2056                                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500)) {
2057                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2058                 return -ETIMEDOUT;
2059         }
2060
2061         phy->phy_clk_on = true;
2062         phy->hw_accessible = true;
2063
2064         if (phy->pmc_sleepwalk) {
2065                 DBG("%s(%d) inst:[%d] restore phy\n", __func__, __LINE__,
2066                                         phy->inst);
2067                 uhsic_phy_restore_start(phy);
2068                 usb_phy_bringup_host_controller(phy);
2069                 uhsic_phy_restore_end(phy);
2070                 phy->pmc_sleepwalk = false;
2071         }
2072
2073         return 0;
2074 }
2075
2076 static int uhsic_phy_power_off(struct tegra_usb_phy *phy)
2077 {
2078         unsigned long val;
2079         void __iomem *base = phy->regs;
2080
2081         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2082         if (!phy->phy_clk_on) {
2083                 DBG("%s(%d) inst:[%d] phy clk is already off\n",
2084                                         __func__, __LINE__, phy->inst);
2085                 return 0;
2086         }
2087
2088         val = readl(base + UHSIC_PADS_CFG1);
2089         val &= ~UHSIC_RPU_STROBE;
2090         val |= UHSIC_RPD_STROBE;
2091         writel(val, base + UHSIC_PADS_CFG1);
2092
2093         val = readl(base + USB_SUSP_CTRL);
2094         val |= UHSIC_RESET;
2095         writel(val, base + USB_SUSP_CTRL);
2096         udelay(30);
2097
2098         phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
2099                         HOSTPC1_DEVLC_PSPD_MASK;
2100
2101         /* Disable interrupts */
2102         writel(0, base + USB_USBINTR);
2103
2104         if (phy->pmc_sleepwalk == false) {
2105                 uhsic_setup_pmc_wake_detect(phy);
2106                 phy->pmc_sleepwalk = true;
2107         }
2108
2109         val = readl(base + HOSTPC1_DEVLC);
2110         val |= HOSTPC1_DEVLC_PHCD;
2111         writel(val, base + HOSTPC1_DEVLC);
2112
2113         phy->phy_clk_on = false;
2114         phy->hw_accessible = false;
2115
2116         return 0;
2117 }
2118
2119 static int uhsic_phy_bus_port_power(struct tegra_usb_phy *phy)
2120 {
2121         unsigned long val;
2122         void __iomem *base = phy->regs;
2123
2124         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2125         val = readl(base + UHSIC_STAT_CFG0);
2126         val &= ~UHSIC_CONNECT_DETECT;
2127         writel(val, base + UHSIC_STAT_CFG0);
2128
2129         val = readl(base + USB_USBMODE);
2130         val |= USB_USBMODE_HOST;
2131         writel(val, base + USB_USBMODE);
2132
2133         /* Change the USB controller PHY type to HSIC */
2134         val = readl(base + HOSTPC1_DEVLC);
2135         val &= ~(HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK));
2136         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2137         val &= ~(HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK));
2138         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2139         writel(val, base + HOSTPC1_DEVLC);
2140
2141         val = readl(base + UHSIC_MISC_CFG0);
2142         val |= UHSIC_DETECT_SHORT_CONNECT;
2143         writel(val, base + UHSIC_MISC_CFG0);
2144         udelay(1);
2145
2146         val = readl(base + UHSIC_MISC_CFG0);
2147         val |= UHSIC_FORCE_XCVR_MODE;
2148         writel(val, base + UHSIC_MISC_CFG0);
2149
2150         val = readl(base + UHSIC_PADS_CFG1);
2151         val &= ~UHSIC_RPD_STROBE;
2152         /* safe to enable RPU on STROBE at all times during idle */
2153         val |= UHSIC_RPU_STROBE;
2154         writel(val, base + UHSIC_PADS_CFG1);
2155
2156         val = readl(base + USB_USBCMD);
2157         val &= ~USB_USBCMD_RS;
2158         writel(val, base + USB_USBCMD);
2159
2160         if (usb_phy_reg_status_wait(base + UHSIC_STAT_CFG0,
2161                         UHSIC_CONNECT_DETECT, UHSIC_CONNECT_DETECT, 25000)) {
2162                 pr_err("%s: timeout waiting for UHSIC_CONNECT_DETECT\n",
2163                                                                 __func__);
2164                 return -ETIMEDOUT;
2165         }
2166
2167         return 0;
2168 }
2169
2170 static int uhsic_phy_bus_reset(struct tegra_usb_phy *phy)
2171 {
2172         unsigned long val;
2173         void __iomem *base = phy->regs;
2174
2175         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2176
2177         /* Change the USB controller PHY type to HSIC */
2178         val = readl(base + HOSTPC1_DEVLC);
2179         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
2180         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2181         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
2182         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2183         val &= ~HOSTPC1_DEVLC_STS;
2184         writel(val, base + HOSTPC1_DEVLC);
2185         /* wait here, otherwise HOSTPC1_DEVLC_PSPD will timeout */
2186         mdelay(5);
2187
2188         val = readl(base + USB_PORTSC);
2189         val |= USB_PORTSC_PTC(5);
2190         writel(val, base + USB_PORTSC);
2191         udelay(2);
2192
2193         val = readl(base + USB_PORTSC);
2194         val &= ~(USB_PORTSC_PTC(~0));
2195         writel(val, base + USB_PORTSC);
2196         udelay(2);
2197
2198         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_LS(0),
2199                                                  0, 2000)) {
2200                 pr_err("%s: timeout waiting for USB_PORTSC_LS\n", __func__);
2201                 return -ETIMEDOUT;
2202         }
2203
2204         /* Poll until CCS is enabled */
2205         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
2206                                                  USB_PORTSC_CCS, 2000)) {
2207                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
2208                 return -ETIMEDOUT;
2209         }
2210
2211         if (usb_phy_reg_status_wait(base + HOSTPC1_DEVLC,
2212                         HOSTPC1_DEVLC_PSPD(2),
2213                         HOSTPC1_DEVLC_PSPD(2), 2000) < 0) {
2214                 pr_err("%s: timeout waiting hsic high speed configuration\n",
2215                                                 __func__);
2216                         return -ETIMEDOUT;
2217         }
2218
2219         val = readl(base + USB_USBCMD);
2220         val &= ~USB_USBCMD_RS;
2221         writel(val, base + USB_USBCMD);
2222
2223         if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
2224                                                  USB_USBSTS_HCH, 2000)) {
2225                 pr_err("%s: timeout waiting for USB_USBSTS_HCH\n", __func__);
2226                 return -ETIMEDOUT;
2227         }
2228
2229         val = readl(base + UHSIC_PADS_CFG1);
2230         val &= ~UHSIC_RPU_STROBE;
2231         val |= UHSIC_RPD_STROBE;
2232         writel(val, base + UHSIC_PADS_CFG1);
2233
2234         mdelay(50);
2235
2236         val = readl(base + UHSIC_PADS_CFG1);
2237         val &= ~UHSIC_RPD_STROBE;
2238         val |= UHSIC_RPU_STROBE;
2239         writel(val, base + UHSIC_PADS_CFG1);
2240
2241         val = readl(base + USB_USBCMD);
2242         val |= USB_USBCMD_RS;
2243         writel(val, base + USB_USBCMD);
2244
2245         val = readl(base + UHSIC_PADS_CFG1);
2246         val &= ~UHSIC_RPU_STROBE;
2247         writel(val, base + UHSIC_PADS_CFG1);
2248
2249         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2250                                                  USB_USBCMD_RS, 2000)) {
2251                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2252                 return -ETIMEDOUT;
2253         }
2254
2255         return 0;
2256 }
2257
2258 static int uhsic_phy_resume(struct tegra_usb_phy *phy)
2259 {
2260         void __iomem *base = phy->regs;
2261         unsigned long val;
2262
2263         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2264
2265         /* Check if the phy resume from LP0. When the phy resume from LP0
2266          * USB register will be reset.to zero */
2267         if (!readl(base + USB_ASYNCLISTADDR)) {
2268
2269                 val = readl(base + USB_USBCMD);
2270                 val |= USB_CMD_RESET;
2271                 writel(val, base + USB_USBCMD);
2272
2273                 if (usb_phy_reg_status_wait(base + USB_USBCMD,
2274                         USB_CMD_RESET, 0, 2500) < 0) {
2275                         pr_err("%s: timeout waiting for reset\n", __func__);
2276                 }
2277
2278                 val = readl(base + USB_USBMODE);
2279                 val &= ~USB_USBMODE_MASK;
2280                 val |= USB_USBMODE_HOST;
2281                 writel(val, base + USB_USBMODE);
2282
2283                 /* Enable Port Power */
2284                 val = readl(base + USB_PORTSC);
2285                 val |= USB_PORTSC_PP;
2286                 writel(val, base + USB_PORTSC);
2287                 udelay(10);
2288
2289                 DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
2290                 readl(base + USB_USBSTS), readl(base + USB_PORTSC));
2291
2292                 uhsic_phy_bus_port_power(phy);
2293         }
2294
2295         return 0;
2296 }
2297
2298 static void ulpi_set_trimmer(struct tegra_usb_phy *phy)
2299 {
2300         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2301         void __iomem *base = phy->regs;
2302         unsigned long val;
2303
2304         val = ULPI_DATA_TRIMMER_SEL(config->data_trimmer);
2305         val |= ULPI_STPDIRNXT_TRIMMER_SEL(config->stpdirnxt_trimmer);
2306         val |= ULPI_DIR_TRIMMER_SEL(config->dir_trimmer);
2307         writel(val, base + ULPI_TIMING_CTRL_1);
2308         udelay(10);
2309
2310         val |= ULPI_DATA_TRIMMER_LOAD;
2311         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
2312         val |= ULPI_DIR_TRIMMER_LOAD;
2313         writel(val, base + ULPI_TIMING_CTRL_1);
2314 }
2315
2316 static int ulpi_link_phy_open(struct tegra_usb_phy *phy)
2317 {
2318 #if defined(CONFIG_TEGRA_SILICON_PLATFORM)
2319         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2320 #endif
2321         int err = 0;
2322
2323         phy->ulpi_clk = NULL;
2324         DBG("%s inst:[%d]\n", __func__, phy->inst);
2325
2326 #if defined(CONFIG_TEGRA_SILICON_PLATFORM)
2327         if (config->clk) {
2328                 phy->ulpi_clk = clk_get_sys(NULL, config->clk);
2329                 if (IS_ERR(phy->ulpi_clk)) {
2330                         pr_err("%s: can't get ulpi clock\n", __func__);
2331                         err = -ENXIO;
2332                 }
2333         }
2334 #endif
2335         phy->ulpi_vp = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
2336         phy->ulpi_vp->io_priv = phy->regs + ULPI_VIEWPORT;
2337
2338         return err;
2339 }
2340
2341 static void ulpi_link_phy_close(struct tegra_usb_phy *phy)
2342 {
2343         DBG("%s inst:[%d]\n", __func__, phy->inst);
2344         if (phy->ulpi_clk)
2345                 clk_put(phy->ulpi_clk);
2346 }
2347
2348 static int ulpi_link_phy_irq(struct tegra_usb_phy *phy)
2349 {
2350         DBG("%s inst:[%d]\n", __func__, phy->inst);
2351         return IRQ_HANDLED;
2352 }
2353
2354 static int ulpi_link_phy_power_off(struct tegra_usb_phy *phy)
2355 {
2356         unsigned long val;
2357         void __iomem *base = phy->regs;
2358         int ret;
2359
2360         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2361         if (!phy->phy_clk_on) {
2362                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
2363                                                         __LINE__, phy->inst);
2364                 return 0;
2365         }
2366
2367         /* Disable VbusValid, SessEnd comparators */
2368         ret = usb_phy_io_write(phy->ulpi_vp, 0x00, 0x0D);
2369         if (ret)
2370                 pr_err("%s: ulpi write 0x0D failed\n", __func__);
2371
2372         ret = usb_phy_io_write(phy->ulpi_vp, 0x00, 0x10);
2373         if (ret)
2374                 pr_err("%s: ulpi write 0x10 failed\n", __func__);
2375
2376         /* Disable IdFloat comparator */
2377         ret = usb_phy_io_write(phy->ulpi_vp, 0x00, 0x19);
2378         if (ret)
2379                 pr_err("%s: ulpi write 0x19 failed\n", __func__);
2380
2381         ret = usb_phy_io_write(phy->ulpi_vp, 0x00, 0x1D);
2382         if (ret)
2383                 pr_err("%s: ulpi write 0x1D failed\n", __func__);
2384
2385         phy->port_speed = (readl(base + USB_PORTSC) >> 26) &
2386                         USB_PORTSC_PSPD_MASK;
2387
2388         /* Clear WKCN/WKDS/WKOC wake-on events that can cause the USB
2389          * Controller to immediately bring the ULPI PHY out of low power
2390          */
2391         val = readl(base + USB_PORTSC);
2392         val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN);
2393         writel(val, base + USB_PORTSC);
2394
2395         /* Put the PHY in the low power mode */
2396         val = readl(base + USB_PORTSC);
2397         val |= USB_PORTSC_PHCD;
2398         writel(val, base + USB_PORTSC);
2399
2400         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
2401                                                          0, 2500)) {
2402                 pr_err("%s: timeout waiting for phy to stop\n", __func__);
2403         }
2404
2405         if (phy->ulpi_clk)
2406                 clk_disable(phy->ulpi_clk);
2407
2408         phy->phy_clk_on = false;
2409         phy->hw_accessible = false;
2410
2411         return 0;
2412 }
2413
2414 static int ulpi_link_phy_power_on(struct tegra_usb_phy *phy)
2415 {
2416         int ret;
2417         unsigned long val;
2418         void __iomem *base = phy->regs;
2419
2420         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2421         if (phy->phy_clk_on) {
2422                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
2423                                                         __LINE__, phy->inst);
2424                 return 0;
2425         }
2426
2427         if (phy->ulpi_clk) {
2428                 clk_enable(phy->ulpi_clk);
2429                 mdelay(1);
2430         }
2431
2432         val = readl(base + USB_SUSP_CTRL);
2433         val |= UHSIC_RESET;
2434         writel(val, base + USB_SUSP_CTRL);
2435
2436         val = readl(base + ULPI_TIMING_CTRL_0);
2437         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
2438         writel(val, base + ULPI_TIMING_CTRL_0);
2439
2440         val = readl(base + USB_SUSP_CTRL);
2441         val |= ULPI_PHY_ENABLE;
2442         writel(val, base + USB_SUSP_CTRL);
2443
2444         val = readl(base + USB_SUSP_CTRL);
2445         val |= USB_SUSP_CLR;
2446         writel(val, base + USB_SUSP_CTRL);
2447
2448         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
2449                                                 USB_PHY_CLK_VALID, 2500))
2450                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2451
2452         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_CLKEN,
2453                                                 USB_CLKEN, 2500))
2454                 pr_err("%s: timeout waiting for AHB clock\n", __func__);
2455
2456         val = readl(base + USB_SUSP_CTRL);
2457         val &= ~USB_SUSP_CLR;
2458         writel(val, base + USB_SUSP_CTRL);
2459
2460         val = 0;
2461         writel(val, base + ULPI_TIMING_CTRL_1);
2462
2463         ulpi_set_trimmer(phy);
2464
2465         /* Fix VbusInvalid due to floating VBUS */
2466         ret = usb_phy_io_write(phy->ulpi_vp, 0x40, 0x08);
2467         if (ret) {
2468                 pr_err("%s: ulpi write failed\n", __func__);
2469                 return ret;
2470         }
2471
2472         ret = usb_phy_io_write(phy->ulpi_vp, 0x80, 0x0B);
2473         if (ret) {
2474                 pr_err("%s: ulpi write failed\n", __func__);
2475                 return ret;
2476         }
2477
2478         val = readl(base + USB_PORTSC);
2479         val |= USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN;
2480         writel(val, base + USB_PORTSC);
2481
2482         phy->phy_clk_on = true;
2483         phy->hw_accessible = true;
2484
2485         return 0;
2486 }
2487
2488 static inline void ulpi_link_phy_set_tristate(bool enable)
2489 {
2490 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2491         int tristate = (enable) ? TEGRA_TRI_TRISTATE : TEGRA_TRI_NORMAL;
2492
2493         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAA, tristate);
2494         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAB, tristate);
2495         tegra_pinmux_set_tristate(TEGRA_PINGROUP_UDA, tristate);
2496 #endif
2497 }
2498
2499 static void ulpi_link_phy_restore_start(struct tegra_usb_phy *phy)
2500 {
2501         unsigned long val;
2502         void __iomem *base = phy->regs;
2503
2504         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2505
2506         /*Tristate ulpi interface before USB controller resume*/
2507         ulpi_link_phy_set_tristate(true);
2508
2509         val = readl(base + ULPI_TIMING_CTRL_0);
2510         val &= ~ULPI_OUTPUT_PINMUX_BYP;
2511         writel(val, base + ULPI_TIMING_CTRL_0);
2512 }
2513
2514 static void ulpi_link_phy_restore_end(struct tegra_usb_phy *phy)
2515 {
2516         unsigned long val;
2517         void __iomem *base = phy->regs;
2518
2519         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2520
2521         val = readl(base + ULPI_TIMING_CTRL_0);
2522         val |= ULPI_OUTPUT_PINMUX_BYP;
2523         writel(val, base + ULPI_TIMING_CTRL_0);
2524
2525         ulpi_link_phy_set_tristate(false);
2526 }
2527
2528 static int ulpi_link_phy_resume(struct tegra_usb_phy *phy)
2529 {
2530         int status = 0;
2531
2532         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2533         if (phy->pdata->u_data.host.power_off_on_suspend) {
2534                 status = ulpi_link_phy_power_on(phy);
2535                 if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
2536                         ulpi_link_phy_restore_start(phy);
2537                         usb_phy_bringup_host_controller(phy);
2538                         ulpi_link_phy_restore_end(phy);
2539                 }
2540         }
2541
2542         return status;
2543 }
2544
2545 static void reset_utmip_uhsic(void __iomem *base)
2546 {
2547         unsigned long val;
2548
2549         val = readl(base + USB_SUSP_CTRL);
2550         val |= UHSIC_RESET;
2551         writel(val, base + USB_SUSP_CTRL);
2552
2553         val = readl(base + USB_SUSP_CTRL);
2554         val |= UTMIP_RESET;
2555         writel(val, base + USB_SUSP_CTRL);
2556 }
2557
2558 static void ulpi_set_host(void __iomem *base)
2559 {
2560         unsigned long val;
2561
2562         val = readl(base + USB_USBMODE);
2563         val &= ~USB_USBMODE_MASK;
2564         val |= USB_USBMODE_HOST;
2565         writel(val, base + USB_USBMODE);
2566
2567         val = readl(base + HOSTPC1_DEVLC);
2568         val |= HOSTPC1_DEVLC_PTS(2);
2569         writel(val, base + HOSTPC1_DEVLC);
2570 }
2571
2572 static inline void ulpi_pinmux_bypass(struct tegra_usb_phy *phy, bool enable)
2573 {
2574         unsigned long val;
2575         void __iomem *base = phy->regs;
2576
2577         val = readl(base + ULPI_TIMING_CTRL_0);
2578
2579         if (enable)
2580                 val |= ULPI_OUTPUT_PINMUX_BYP;
2581         else
2582                 val &= ~ULPI_OUTPUT_PINMUX_BYP;
2583
2584         writel(val, base + ULPI_TIMING_CTRL_0);
2585 }
2586
2587 static inline void ulpi_null_phy_set_tristate(bool enable)
2588 {
2589 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2590         int tristate = (enable) ? TEGRA_TRI_TRISTATE : TEGRA_TRI_NORMAL;
2591         DBG("%s(%d) inst:[%s] FIXME enable pin group +++\n", __func__,
2592                                 __LINE__, enable ? "TRISTATE" : "NORMAL");
2593
2594         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA0, tristate);
2595         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA1, tristate);
2596         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA2, tristate);
2597         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA3, tristate);
2598         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA4, tristate);
2599         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA5, tristate);
2600         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA6, tristate);
2601         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA7, tristate);
2602         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_NXT, tristate);
2603
2604         if (enable)
2605                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR, tristate);
2606 #endif
2607 }
2608
2609 static void ulpi_null_phy_obs_read(void)
2610 {
2611         static void __iomem *apb_misc;
2612         unsigned slv0_obs, s2s_obs;
2613
2614         if (!apb_misc)
2615                 apb_misc = ioremap(TEGRA_APB_MISC_BASE, TEGRA_APB_MISC_SIZE);
2616
2617         writel(0x80d1003c, apb_misc + APB_MISC_GP_OBSCTRL_0);
2618         slv0_obs = readl(apb_misc + APB_MISC_GP_OBSDATA_0);
2619
2620         writel(0x80d10040, apb_misc + APB_MISC_GP_OBSCTRL_0);
2621         s2s_obs = readl(apb_misc + APB_MISC_GP_OBSDATA_0);
2622
2623         pr_debug("slv0 obs: %08x\ns2s obs: %08x\n", slv0_obs, s2s_obs);
2624 }
2625
2626 static const struct gpio ulpi_gpios[] = {
2627         {ULPI_STP, GPIOF_IN, "ULPI_STP"},
2628         {ULPI_DIR, GPIOF_OUT_INIT_LOW, "ULPI_DIR"},
2629         {ULPI_D0, GPIOF_OUT_INIT_LOW, "ULPI_D0"},
2630         {ULPI_D1, GPIOF_OUT_INIT_LOW, "ULPI_D1"},
2631 };
2632
2633 static int ulpi_null_phy_open(struct tegra_usb_phy *phy)
2634 {
2635         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2636         int ret;
2637
2638         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2639
2640         ret = gpio_request_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
2641         if (ret)
2642                 return ret;
2643
2644         if (gpio_is_valid(config->phy_restore_gpio)) {
2645                 ret = gpio_request(config->phy_restore_gpio, "phy_restore");
2646                 if (ret)
2647                         goto err_gpio_free;
2648
2649                 gpio_direction_input(config->phy_restore_gpio);
2650         }
2651
2652         tegra_periph_reset_assert(phy->ctrlr_clk);
2653         udelay(10);
2654         tegra_periph_reset_deassert(phy->ctrlr_clk);
2655
2656         return 0;
2657
2658 err_gpio_free:
2659         gpio_free_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
2660         return ret;
2661 }
2662
2663 static void ulpi_null_phy_close(struct tegra_usb_phy *phy)
2664 {
2665         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2666
2667         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2668
2669         if (gpio_is_valid(config->phy_restore_gpio))
2670                 gpio_free(config->phy_restore_gpio);
2671
2672         gpio_free_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
2673 }
2674
2675 static int ulpi_null_phy_power_off(struct tegra_usb_phy *phy)
2676 {
2677         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2678
2679         if (!phy->phy_clk_on) {
2680                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
2681                                                         __LINE__, phy->inst);
2682                 return 0;
2683         }
2684
2685         phy->phy_clk_on = false;
2686         phy->hw_accessible = false;
2687         ulpi_null_phy_set_tristate(true);
2688         return 0;
2689 }
2690
2691 /* NOTE: this function must be called before ehci reset */
2692 static int ulpi_null_phy_init(struct tegra_usb_phy *phy)
2693 {
2694         unsigned long val;
2695         void __iomem *base = phy->regs;
2696
2697         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2698         _usb_phy_init(phy);
2699         val = readl(base + ULPIS2S_CTRL);
2700         val |=  ULPIS2S_SLV0_CLAMP_XMIT;
2701         writel(val, base + ULPIS2S_CTRL);
2702
2703         val = readl(base + USB_SUSP_CTRL);
2704         val |= ULPIS2S_SLV0_RESET;
2705         writel(val, base + USB_SUSP_CTRL);
2706         udelay(10);
2707
2708         return 0;
2709 }
2710
2711 static int ulpi_null_phy_irq(struct tegra_usb_phy *phy)
2712 {
2713         return IRQ_HANDLED;
2714 }
2715
2716 /* NOTE: this function must be called after ehci reset */
2717 static int ulpi_null_phy_cmd_reset(struct tegra_usb_phy *phy)
2718 {
2719         unsigned long val;
2720         void __iomem *base = phy->regs;
2721
2722         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2723         ulpi_set_host(base);
2724
2725         /* remove slave0 reset */
2726         val = readl(base + USB_SUSP_CTRL);
2727         val &= ~ULPIS2S_SLV0_RESET;
2728         writel(val, base + USB_SUSP_CTRL);
2729
2730         val = readl(base + ULPIS2S_CTRL);
2731         val &=  ~ULPIS2S_SLV0_CLAMP_XMIT;
2732         writel(val, base + ULPIS2S_CTRL);
2733         udelay(10);
2734
2735         return 0;
2736 }
2737
2738 static int ulpi_null_phy_restore(struct tegra_usb_phy *phy)
2739 {
2740         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2741         unsigned long timeout;
2742         int ulpi_stp = ULPI_STP;
2743
2744         if (gpio_is_valid(config->phy_restore_gpio))
2745                 ulpi_stp = config->phy_restore_gpio;
2746
2747         /* disable ULPI pinmux bypass */
2748         ulpi_pinmux_bypass(phy, false);
2749
2750         /* driving linstate by GPIO */
2751         gpio_set_value(ULPI_D0, 0);
2752         gpio_set_value(ULPI_D1, 0);
2753
2754         /* driving DIR high */
2755         gpio_set_value(ULPI_DIR, 1);
2756
2757         /* remove ULPI tristate */
2758         ulpi_null_phy_set_tristate(false);
2759
2760         /* wait for STP high */
2761         timeout = jiffies + msecs_to_jiffies(25);
2762
2763         while (!gpio_get_value(ulpi_stp)) {
2764                 if (time_after(jiffies, timeout)) {
2765                         pr_warn("phy restore timeout\n");
2766                         return 1;
2767                 }
2768         }
2769
2770         return 0;
2771 }
2772
2773 static int ulpi_null_phy_lp0_resume(struct tegra_usb_phy *phy)
2774 {
2775         unsigned long val;
2776         void __iomem *base = phy->regs;
2777
2778         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2779         ulpi_null_phy_init(phy);
2780
2781         val = readl(base + USB_USBCMD);
2782         val |= USB_CMD_RESET;
2783         writel(val, base + USB_USBCMD);
2784
2785         if (usb_phy_reg_status_wait(base + USB_USBCMD,
2786                 USB_CMD_RESET, 0, 2500) < 0) {
2787                 pr_err("%s: timeout waiting for reset\n", __func__);
2788         }
2789
2790         ulpi_null_phy_cmd_reset(phy);
2791
2792         val = readl(base + USB_USBCMD);
2793         val |= USB_USBCMD_RS;
2794         writel(val, base + USB_USBCMD);
2795         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2796                                                  USB_USBCMD_RS, 2000)) {
2797                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2798                 return -ETIMEDOUT;
2799         }
2800
2801         /* Enable Port Power */
2802         val = readl(base + USB_PORTSC);
2803         val |= USB_PORTSC_PP;
2804         writel(val, base + USB_PORTSC);
2805         udelay(10);
2806
2807         ulpi_null_phy_restore(phy);
2808
2809         return 0;
2810 }
2811
2812 static int ulpi_null_phy_power_on(struct tegra_usb_phy *phy)
2813 {
2814         unsigned long val;
2815         void __iomem *base = phy->regs;
2816         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2817
2818         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2819         if (phy->phy_clk_on) {
2820                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
2821                                                         __LINE__, phy->inst);
2822                 return 0;
2823         }
2824         reset_utmip_uhsic(base);
2825
2826         /* remove ULPI PADS CLKEN reset */
2827         val = readl(base + USB_SUSP_CTRL);
2828         val &= ~ULPI_PADS_CLKEN_RESET;
2829         writel(val, base + USB_SUSP_CTRL);
2830         udelay(10);
2831
2832         val = readl(base + ULPI_TIMING_CTRL_0);
2833         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
2834         writel(val, base + ULPI_TIMING_CTRL_0);
2835
2836         val = readl(base + USB_SUSP_CTRL);
2837         val |= ULPI_PHY_ENABLE;
2838         writel(val, base + USB_SUSP_CTRL);
2839         udelay(10);
2840
2841         /* set timming parameters */
2842         val = readl(base + ULPI_TIMING_CTRL_0);
2843         val |= ULPI_SHADOW_CLK_LOOPBACK_EN;
2844         val &= ~ULPI_SHADOW_CLK_SEL;
2845         val &= ~ULPI_LBK_PAD_EN;
2846         val |= ULPI_SHADOW_CLK_DELAY(config->shadow_clk_delay);
2847         val |= ULPI_CLOCK_OUT_DELAY(config->clock_out_delay);
2848         val |= ULPI_LBK_PAD_E_INPUT_OR;
2849         writel(val, base + ULPI_TIMING_CTRL_0);
2850
2851         writel(0, base + ULPI_TIMING_CTRL_1);
2852         udelay(10);
2853
2854         /* start internal 60MHz clock */
2855         val = readl(base + ULPIS2S_CTRL);
2856         val |= ULPIS2S_ENA;
2857         val |= ULPIS2S_SUPPORT_DISCONNECT;
2858         val |= ULPIS2S_SPARE((phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) ? 3 : 1);
2859         val |= ULPIS2S_PLLU_MASTER_BLASTER60;
2860         writel(val, base + ULPIS2S_CTRL);
2861
2862         /* select ULPI_CORE_CLK_SEL to SHADOW_CLK */
2863         val = readl(base + ULPI_TIMING_CTRL_0);
2864         val |= ULPI_CORE_CLK_SEL;
2865         writel(val, base + ULPI_TIMING_CTRL_0);
2866         udelay(10);
2867
2868         /* enable ULPI null phy clock - can't set the trimmers before this */
2869         val = readl(base + ULPI_TIMING_CTRL_0);
2870         val |= ULPI_CLK_OUT_ENA;
2871         writel(val, base + ULPI_TIMING_CTRL_0);
2872         udelay(10);
2873
2874         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
2875                                                  USB_PHY_CLK_VALID, 2500)) {
2876                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2877                 return -ETIMEDOUT;
2878         }
2879
2880         /* set ULPI trimmers */
2881         ulpi_set_trimmer(phy);
2882
2883         ulpi_set_host(base);
2884
2885         /* remove slave0 reset */
2886         val = readl(base + USB_SUSP_CTRL);
2887         val &= ~ULPIS2S_SLV0_RESET;
2888         writel(val, base + USB_SUSP_CTRL);
2889
2890         /* remove slave1 and line reset */
2891         val = readl(base + USB_SUSP_CTRL);
2892         val &= ~ULPIS2S_SLV1_RESET;
2893         val &= ~ULPIS2S_LINE_RESET;
2894
2895         /* remove ULPI PADS reset */
2896         val &= ~ULPI_PADS_RESET;
2897         writel(val, base + USB_SUSP_CTRL);
2898
2899         if (!phy->ulpi_clk_padout_ena) {
2900                 val = readl(base + ULPI_TIMING_CTRL_0);
2901                 val |= ULPI_CLK_PADOUT_ENA;
2902                 writel(val, base + ULPI_TIMING_CTRL_0);
2903                 phy->ulpi_clk_padout_ena = true;
2904         } else {
2905                 if (!readl(base + USB_ASYNCLISTADDR))
2906                         ulpi_null_phy_lp0_resume(phy);
2907         }
2908         udelay(10);
2909
2910         phy->phy_clk_on = true;
2911         phy->hw_accessible = true;
2912
2913         return 0;
2914 }
2915
2916 static int ulpi_null_phy_pre_resume(struct tegra_usb_phy *phy,
2917                                     bool remote_wakeup)
2918 {
2919         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2920         ulpi_null_phy_obs_read();
2921         return 0;
2922 }
2923
2924 static int ulpi_null_phy_post_resume(struct tegra_usb_phy *phy)
2925 {
2926         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2927         ulpi_null_phy_obs_read();
2928         return 0;
2929 }
2930
2931 static int ulpi_null_phy_resume(struct tegra_usb_phy *phy)
2932 {
2933         unsigned long val;
2934         void __iomem *base = phy->regs;
2935
2936         if (!readl(base + USB_ASYNCLISTADDR)) {
2937                 /* enable ULPI CLK output pad */
2938                 val = readl(base + ULPI_TIMING_CTRL_0);
2939                 val |= ULPI_CLK_PADOUT_ENA;
2940                 writel(val, base + ULPI_TIMING_CTRL_0);
2941
2942                 /* enable ULPI pinmux bypass */
2943                 ulpi_pinmux_bypass(phy, true);
2944                 udelay(5);
2945 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2946                 /* remove DIR tristate */
2947                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR,
2948                                           TEGRA_TRI_NORMAL);
2949 #endif
2950         }
2951         return 0;
2952 }
2953
2954 static struct tegra_usb_phy_ops utmi_phy_ops = {
2955         .init           = _usb_phy_init,
2956         .reset          = usb_phy_reset,
2957         .open           = utmi_phy_open,
2958         .close          = utmi_phy_close,
2959         .irq            = utmi_phy_irq,
2960         .power_on       = utmi_phy_power_on,
2961         .power_off      = utmi_phy_power_off,
2962         .pre_resume = utmi_phy_pre_resume,
2963         .resume = utmi_phy_resume,
2964         .post_resume    = utmi_phy_post_resume,
2965         .charger_detect = utmi_phy_charger_detect,
2966 };
2967
2968 static struct tegra_usb_phy_ops uhsic_phy_ops = {
2969         .init           = _usb_phy_init,
2970         .open           = uhsic_phy_open,
2971         .irq            = uhsic_phy_irq,
2972         .power_on       = uhsic_phy_power_on,
2973         .power_off      = uhsic_phy_power_off,
2974         .pre_resume = uhsic_phy_pre_resume,
2975         .resume = uhsic_phy_resume,
2976         .post_resume = uhsic_phy_post_resume,
2977         .port_power = uhsic_phy_bus_port_power,
2978         .bus_reset      = uhsic_phy_bus_reset,
2979 };
2980
2981 static struct tegra_usb_phy_ops ulpi_link_phy_ops = {
2982         .init           = _usb_phy_init,
2983         .reset          = usb_phy_reset,
2984         .open           = ulpi_link_phy_open,
2985         .close          = ulpi_link_phy_close,
2986         .irq            = ulpi_link_phy_irq,
2987         .power_on       = ulpi_link_phy_power_on,
2988         .power_off      = ulpi_link_phy_power_off,
2989         .resume         = ulpi_link_phy_resume,
2990 };
2991
2992 static struct tegra_usb_phy_ops ulpi_null_phy_ops = {
2993         .open           = ulpi_null_phy_open,
2994         .close          = ulpi_null_phy_close,
2995         .init           = ulpi_null_phy_init,
2996         .irq            = ulpi_null_phy_irq,
2997         .power_on       = ulpi_null_phy_power_on,
2998         .power_off      = ulpi_null_phy_power_off,
2999         .pre_resume = ulpi_null_phy_pre_resume,
3000         .resume = ulpi_null_phy_resume,
3001         .post_resume = ulpi_null_phy_post_resume,
3002         .reset          = ulpi_null_phy_cmd_reset,
3003 };
3004
3005 static struct tegra_usb_phy_ops icusb_phy_ops;
3006
3007 static struct tegra_usb_phy_ops *phy_ops[] = {
3008         [TEGRA_USB_PHY_INTF_UTMI] = &utmi_phy_ops,
3009         [TEGRA_USB_PHY_INTF_ULPI_LINK] = &ulpi_link_phy_ops,
3010         [TEGRA_USB_PHY_INTF_ULPI_NULL] = &ulpi_null_phy_ops,
3011         [TEGRA_USB_PHY_INTF_HSIC] = &uhsic_phy_ops,
3012         [TEGRA_USB_PHY_INTF_ICUSB] = &icusb_phy_ops,
3013 };
3014
3015 int tegra11x_usb_phy_init_ops(struct tegra_usb_phy *phy)
3016 {
3017         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
3018
3019         phy->ops = phy_ops[phy->pdata->phy_intf];
3020
3021         /* FIXME: uncommenting below line to make USB host mode fail*/
3022         /* usb_phy_power_down_pmc(); */
3023
3024         return 0;
3025 }