ARM: tegra: usb_phy: Fix terminiation delay for NvCharger
[linux-2.6.git] / arch / arm / mach-tegra / tegra11x_usb_phy.c
1 /*
2  * arch/arm/mach-tegra/tegra11x_usb_phy.c
3  *
4  * Copyright (C) 2012-2013 NVIDIA Corporation
5  *
6  *
7  * This software is licensed under the terms of the GNU General Public
8  * License version 2, as published by the Free Software Foundation, and
9  * may be copied, distributed, and modified under those terms.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17 #include <linux/resource.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/slab.h>
21 #include <linux/err.h>
22 #include <linux/platform_device.h>
23 #include <linux/io.h>
24 #include <linux/gpio.h>
25 #include <linux/usb/ulpi.h>
26 #include <linux/interrupt.h>
27 #include <linux/clk.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/platform_data/tegra_usb.h>
30 #include <mach/clk.h>
31 #include <mach/iomap.h>
32 #include <mach/pinmux.h>
33 #include <mach/pinmux-t11.h>
34 #include <asm/mach-types.h>
35 #include "tegra_usb_phy.h"
36 #include "gpio-names.h"
37 #include "fuse.h"
38
39 #define USB_USBCMD              0x130
40 #define   USB_USBCMD_RS         (1 << 0)
41 #define   USB_CMD_RESET (1<<1)
42
43 #define USB_USBSTS              0x134
44 #define   USB_USBSTS_PCI        (1 << 2)
45 #define   USB_USBSTS_SRI        (1 << 7)
46 #define   USB_USBSTS_HCH        (1 << 12)
47
48 #define USB_TXFILLTUNING        0x154
49 #define   USB_FIFO_TXFILL_THRES(x)   (((x) & 0x1f) << 16)
50 #define   USB_FIFO_TXFILL_MASK    0x1f0000
51
52 #define ULPI_VIEWPORT           0x170
53 #define   ULPI_WAKEUP           (1 << 31)
54 #define   ULPI_RUN              (1 << 30)
55 #define   ULPI_RD_WR            (1 << 29)
56
57 #define USB_ASYNCLISTADDR       0x148
58
59 #define ICUSB_CTRL              0x15c
60
61 #define USB_PORTSC              0x174
62 #define   USB_PORTSC_PHCD       (1 << 23)
63 #define   USB_PORTSC_WKOC       (1 << 22)
64 #define   USB_PORTSC_WKDS       (1 << 21)
65 #define   USB_PORTSC_WKCN       (1 << 20)
66 #define   USB_PORTSC_PTC(x)     (((x) & 0xf) << 16)
67 #define   USB_PORTSC_PP (1 << 12)
68 #define   USB_PORTSC_LS(x) (((x) & 0x3) << 10)
69 #define   USB_PORTSC_SUSP       (1 << 7)
70 #define   USB_PORTSC_RESUME     (1 << 6)
71 #define   USB_PORTSC_OCC        (1 << 5)
72 #define   USB_PORTSC_PEC        (1 << 3)
73 #define   USB_PORTSC_PE         (1 << 2)
74 #define   USB_PORTSC_CSC        (1 << 1)
75 #define   USB_PORTSC_CCS        (1 << 0)
76 #define   USB_PORTSC_RWC_BITS (USB_PORTSC_CSC | USB_PORTSC_PEC | USB_PORTSC_OCC)
77 #define   USB_PORTSC_PSPD_MASK  3
78 #define   USB_PORTSC_LINE_STATE(x) (((x) & (0x3 << 10)) >> 10)
79
80 #define HOSTPC1_DEVLC           0x1b4
81 #define   HOSTPC1_DEVLC_PHCD            (1 << 22)
82 #define   HOSTPC1_DEVLC_PTS(x)          (((x) & 0x7) << 29)
83 #define   HOSTPC1_DEVLC_PTS_MASK        7
84 #define   HOSTPC1_DEVLC_PTS_HSIC        4
85 #define   HOSTPC1_DEVLC_STS             (1 << 28)
86 #define   HOSTPC1_DEVLC_PSPD(x)         (((x) & 0x3) << 25)
87 #define   HOSTPC1_DEVLC_PSPD_MASK       3
88 #define   HOSTPC1_DEVLC_PSPD_HIGH_SPEED 2
89 #define   HOSTPC1_DEVLC_NYT_ASUS        1
90
91 #define USB_USBMODE             0x1f8
92 #define   USB_USBMODE_MASK              (3 << 0)
93 #define   USB_USBMODE_HOST              (3 << 0)
94 #define   USB_USBMODE_DEVICE            (2 << 0)
95
96 #define USB_SUSP_CTRL           0x400
97 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
98 #define   USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
99 #define   USB_SUSP_CLR                  (1 << 5)
100 #define   USB_CLKEN             (1 << 6)
101 #define   USB_PHY_CLK_VALID             (1 << 7)
102 #define   USB_PHY_CLK_VALID_INT_ENB     (1 << 9)
103 #define   USB_PHY_CLK_VALID_INT_STS     (1 << 8)
104 #define   UTMIP_RESET                   (1 << 11)
105 #define   UTMIP_PHY_ENABLE              (1 << 12)
106 #define   ULPI_PHY_ENABLE               (1 << 13)
107 #define   UHSIC_RESET                   (1 << 14)
108 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
109 #define   UHSIC_PHY_ENABLE              (1 << 19)
110 #define   ULPIS2S_SLV0_RESET            (1 << 20)
111 #define   ULPIS2S_SLV1_RESET            (1 << 21)
112 #define   ULPIS2S_LINE_RESET            (1 << 22)
113 #define   ULPI_PADS_RESET               (1 << 23)
114 #define   ULPI_PADS_CLKEN_RESET         (1 << 24)
115
116 #define USB_PHY_VBUS_WAKEUP_ID  0x408
117 #define   VDAT_DET_INT_EN       (1 << 16)
118 #define   VDAT_DET_CHG_DET      (1 << 17)
119 #define   VDAT_DET_STS          (1 << 18)
120 #define   USB_ID_STATUS         (1 << 2)
121
122 #define ULPIS2S_CTRL            0x418
123 #define   ULPIS2S_ENA                   (1 << 0)
124 #define   ULPIS2S_SUPPORT_DISCONNECT    (1 << 2)
125 #define   ULPIS2S_PLLU_MASTER_BLASTER60 (1 << 3)
126 #define   ULPIS2S_SPARE(x)              (((x) & 0xF) << 8)
127 #define   ULPIS2S_FORCE_ULPI_CLK_OUT    (1 << 12)
128 #define   ULPIS2S_DISCON_DONT_CHECK_SE0 (1 << 13)
129 #define   ULPIS2S_SUPPORT_HS_KEEP_ALIVE (1 << 14)
130 #define   ULPIS2S_DISABLE_STP_PU        (1 << 15)
131 #define   ULPIS2S_SLV0_CLAMP_XMIT       (1 << 16)
132
133 #define ULPI_TIMING_CTRL_0      0x424
134 #define   ULPI_CLOCK_OUT_DELAY(x)       ((x) & 0x1F)
135 #define   ULPI_OUTPUT_PINMUX_BYP        (1 << 10)
136 #define   ULPI_CLKOUT_PINMUX_BYP        (1 << 11)
137 #define   ULPI_SHADOW_CLK_LOOPBACK_EN   (1 << 12)
138 #define   ULPI_SHADOW_CLK_SEL           (1 << 13)
139 #define   ULPI_CORE_CLK_SEL             (1 << 14)
140 #define   ULPI_SHADOW_CLK_DELAY(x)      (((x) & 0x1F) << 16)
141 #define   ULPI_LBK_PAD_EN               (1 << 26)
142 #define   ULPI_LBK_PAD_E_INPUT_OR       (1 << 27)
143 #define   ULPI_CLK_OUT_ENA              (1 << 28)
144 #define   ULPI_CLK_PADOUT_ENA           (1 << 29)
145
146 #define ULPI_TIMING_CTRL_1      0x428
147 #define   ULPI_DATA_TRIMMER_LOAD        (1 << 0)
148 #define   ULPI_DATA_TRIMMER_SEL(x)      (((x) & 0x7) << 1)
149 #define   ULPI_STPDIRNXT_TRIMMER_LOAD   (1 << 16)
150 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
151 #define   ULPI_DIR_TRIMMER_LOAD         (1 << 24)
152 #define   ULPI_DIR_TRIMMER_SEL(x)       (((x) & 0x7) << 25)
153
154 #define USB_IF_SPARE    0x498
155 #define   USB_HS_RSM_EOP_EN         (1 << 4)
156 #define   USB_PORT_SUSPEND_EN       (1 << 5)
157
158 #define USB_NEW_CONTROL  0x4c0
159 #define   USB_COHRENCY_EN           (1 << 0)
160 #define   USB_MEM_ALLIGNMENT_MUX_EN (1 << 1)
161
162 #define UTMIP_XCVR_CFG0         0x808
163 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
164 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
165 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
166 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
167 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
168 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
169 #define   UTMIP_XCVR_LSBIAS_SEL                 (1 << 21)
170 #define   UTMIP_XCVR_SETUP_MSB(x)               (((x) & 0x7) << 22)
171 #define   UTMIP_XCVR_HSSLEW_MSB(x)              (((x) & 0x7f) << 25)
172 #define   UTMIP_XCVR_MAX_OFFSET         2
173 #define   UTMIP_XCVR_SETUP_MAX_VALUE    0x7f
174 #define   UTMIP_XCVR_SETUP_MIN_VALUE    0
175 #define   XCVR_SETUP_MSB_CALIB(x) ((x) >> 4)
176
177 #define UTMIP_BIAS_CFG0         0x80c
178 #define   UTMIP_OTGPD                   (1 << 11)
179 #define   UTMIP_BIASPD                  (1 << 10)
180 #define   UTMIP_HSSQUELCH_LEVEL(x)      (((x) & 0x3) << 0)
181 #define   UTMIP_HSDISCON_LEVEL(x)       (((x) & 0x3) << 2)
182 #define   UTMIP_HSDISCON_LEVEL_MSB      (1 << 24)
183
184 #define UTMIP_HSRX_CFG0         0x810
185 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
186 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
187
188 #define UTMIP_HSRX_CFG1         0x814
189 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
190
191 #define UTMIP_TX_CFG0           0x820
192 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
193 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
194
195 #define UTMIP_DEBOUNCE_CFG0 0x82c
196 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
197
198 #define UTMIP_BAT_CHRG_CFG0 0x830
199 #define   UTMIP_PD_CHRG                 (1 << 0)
200 #define   UTMIP_ON_SINK_EN              (1 << 2)
201 #define   UTMIP_OP_SRC_EN               (1 << 3)
202
203 #define UTMIP_XCVR_CFG1         0x838
204 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
205 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
206 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
207 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
208
209 #define UTMIP_BIAS_CFG1         0x83c
210 #define   UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
211 #define   UTMIP_BIAS_PDTRK_POWERDOWN    (1 << 0)
212 #define   UTMIP_BIAS_PDTRK_POWERUP      (1 << 1)
213
214 #define UTMIP_MISC_CFG0         0x824
215 #define   UTMIP_DPDM_OBSERVE            (1 << 26)
216 #define   UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
217 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J   UTMIP_DPDM_OBSERVE_SEL(0xf)
218 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K   UTMIP_DPDM_OBSERVE_SEL(0xe)
219 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
220 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
221 #define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
222 #define   DISABLE_PULLUP_DP (1 << 15)
223 #define   DISABLE_PULLUP_DM (1 << 14)
224 #define   DISABLE_PULLDN_DP (1 << 13)
225 #define   DISABLE_PULLDN_DM (1 << 12)
226 #define   FORCE_PULLUP_DP       (1 << 11)
227 #define   FORCE_PULLUP_DM       (1 << 10)
228 #define   FORCE_PULLDN_DP       (1 << 9)
229 #define   FORCE_PULLDN_DM       (1 << 8)
230 #define   COMB_TERMS            (1 << 0)
231 #define   ALWAYS_FREE_RUNNING_TERMS (1 << 1)
232 #define   MASK_ALL_PULLUP_PULLDOWN (0xff << 8)
233
234 #define UTMIP_SPARE_CFG0        0x834
235 #define   FUSE_SETUP_SEL                (1 << 3)
236 #define   FUSE_ATERM_SEL                (1 << 4)
237
238 #define UTMIP_PMC_WAKEUP0               0x84c
239 #define UHSIC_PMC_WAKEUP0               0xc34
240 #define   EVENT_INT_ENB                 (1 << 0)
241
242 #define UTMIP_BIAS_STS0                 0x840
243 #define   UTMIP_RCTRL_VAL(x)            (((x) & 0xffff) << 0)
244 #define   UTMIP_TCTRL_VAL(x)            (((x) & (0xffff << 16)) >> 16)
245
246 #define UTMIPLL_HW_PWRDN_CFG0                   0x52c
247 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE     (1<<1)
248
249 #define UHSIC_INST(inst, x, y)  ((inst == 1) ? x : y)
250
251 #define UHSIC_PLL_CFG1                          0xc04
252 #define   UHSIC_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
253 #define   UHSIC_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 14)
254
255 #define UHSIC_HSRX_CFG0                         0xc08
256 #define   UHSIC_ELASTIC_UNDERRUN_LIMIT(x)       (((x) & 0x1f) << 2)
257 #define   UHSIC_ELASTIC_OVERRUN_LIMIT(x)        (((x) & 0x1f) << 8)
258 #define   UHSIC_IDLE_WAIT(x)                    (((x) & 0x1f) << 13)
259
260 #define UHSIC_HSRX_CFG1                         0xc0c
261 #define   UHSIC_HS_SYNC_START_DLY(x)            (((x) & 0x1f) << 1)
262
263 #define UHSIC_TX_CFG0                           0xc10
264 #define   UHSIC_HS_READY_WAIT_FOR_VALID (1 << 9)
265
266 #define UHSIC_MISC_CFG0                         0xc14
267 #define   UHSIC_SUSPEND_EXIT_ON_EDGE            (1 << 7)
268 #define   UHSIC_DETECT_SHORT_CONNECT            (1 << 8)
269 #define   UHSIC_FORCE_XCVR_MODE                 (1 << 15)
270 #define   UHSIC_DISABLE_BUSRESET                (1 << 20)
271
272 #define UHSIC_MISC_CFG1                         0xc18
273 #define   UHSIC_PLLU_STABLE_COUNT(x)            (((x) & 0xfff) << 2)
274
275 #define UHSIC_PADS_CFG0                         0xc1c
276 #define   UHSIC_TX_RTUNEN                       0xf000
277 #define   UHSIC_TX_RTUNE(x)                     (((x) & 0xf) << 12)
278 #define   UHSIC_TX_SLEWP                        (0xf << 16)
279 #define   UHSIC_TX_SLEWN                        (0xf << 20)
280
281 #define UHSIC_PADS_CFG1                         0xc20
282 #define   UHSIC_PD_BG                           (1 << 2)
283 #define   UHSIC_PD_TX                           (1 << 3)
284 #define   UHSIC_PD_TRK                          (1 << 4)
285 #define   UHSIC_PD_RX                           (1 << 5)
286 #define   UHSIC_PD_ZI                           (1 << 6)
287 #define   UHSIC_RX_SEL                          (1 << 7)
288 #define   UHSIC_RPD_DATA                        (1 << 9)
289 #define   UHSIC_RPD_STROBE                      (1 << 10)
290 #define   UHSIC_RPU_DATA                        (1 << 11)
291 #define   UHSIC_RPU_STROBE                      (1 << 12)
292
293 #define UHSIC_STAT_CFG0                 0xc28
294 #define   UHSIC_CONNECT_DETECT          (1 << 0)
295
296 #define PMC_UHSIC_TRIGGERS(inst)        UHSIC_INST(inst, 0x1ec, 0x27c)
297 #define   UHSIC_CLR_WALK_PTR(inst)      (1 << UHSIC_INST(inst, 3, 0))
298 #define   UHSIC_CLR_WAKE_ALARM(inst)    (1 << UHSIC_INST(inst, 15, 3))
299
300 #define PMC_UHSIC_SLEEPWALK_CFG(inst)   UHSIC_INST(inst, 0x200, 0x288)
301 #define   UHSIC_LINEVAL_WALK_EN(inst)   (1 << UHSIC_INST(inst, 31, 7))
302
303 #define UHSIC_STATUS(inst)              UHSIC_INST(inst, 0x214, 0x290)
304 #define   UHSIC_WAKE_ALARM(inst)        (1 << UHSIC_INST(inst, 19, 4))
305 #define   UHSIC_WALK_PTR_VAL(inst)      (0x3 << UHSIC_INST(inst, 6, 0))
306 #define   UHSIC_DATA_VAL(inst)          (1 << UHSIC_INST(inst, 15, 3))
307 #define   UHSIC_STROBE_VAL(inst)        (1 << UHSIC_INST(inst, 14, 2))
308
309 #define UHSIC_CMD_CFG0                  0xc24
310 #define   UHSIC_PRETEND_CONNECT_DETECT  (1 << 5)
311
312 #define PMC_UHSIC_SLEEP_CFG(inst)       UHSIC_INST(inst, 0x1fc, 0x284)
313 #define   UHSIC_MASTER_ENABLE(inst)     (1 << UHSIC_INST(inst, 24, 0))
314 #define   UHSIC_WAKE_VAL(inst, x)       (((x) & 0xf) << UHSIC_INST(inst, 28, 4))
315 #define   WAKE_VAL_SD10                 0x2
316
317 #define USB_USBINTR                                             0x138
318
319 #define PMC_UHSIC_MASTER_CONFIG(inst)   UHSIC_INST(inst, 0x274, 0x29c)
320 #define   UHSIC_PWR(inst)               (1 << UHSIC_INST(inst, 3, 0))
321
322 #define PMC_UHSIC_FAKE(inst)            UHSIC_INST(inst, 0x218, 0x294)
323 #define   UHSIC_FAKE_STROBE_VAL(inst)           (1 << UHSIC_INST(inst, 12, 0))
324 #define   UHSIC_FAKE_DATA_VAL(inst)             (1 << UHSIC_INST(inst, 13, 1))
325
326 #define PMC_SLEEPWALK_UHSIC(inst)       UHSIC_INST(inst, 0x210, 0x28c)
327 #define   UHSIC_STROBE_RPD_A                            (1 << 0)
328 #define   UHSIC_DATA_RPD_A                              (1 << 1)
329 #define   UHSIC_STROBE_RPU_A                            (1 << 2)
330 #define   UHSIC_DATA_RPU_A                              (1 << 3)
331 #define   UHSIC_STROBE_RPD_B                            (1 << 8)
332 #define   UHSIC_DATA_RPD_B                              (1 << 9)
333 #define   UHSIC_STROBE_RPU_B                            (1 << 10)
334 #define   UHSIC_DATA_RPU_B                              (1 << 11)
335 #define   UHSIC_STROBE_RPD_C                            (1 << 16)
336 #define   UHSIC_DATA_RPD_C                              (1 << 17)
337 #define   UHSIC_STROBE_RPU_C                            (1 << 18)
338 #define   UHSIC_DATA_RPU_C                              (1 << 19)
339 #define   UHSIC_STROBE_RPD_D                            (1 << 24)
340 #define   UHSIC_DATA_RPD_D                              (1 << 25)
341 #define   UHSIC_STROBE_RPU_D                            (1 << 26)
342 #define   UHSIC_DATA_RPU_D                              (1 << 27)
343 #define   UHSIC_LINE_DEB_CNT(x)                 (((x) & 0xf) << 20)
344
345 #define PMC_USB_DEBOUNCE                        0xec
346 #define   UTMIP_LINE_DEB_CNT(x)                 (((x) & 0xf) << 16)
347 #define   PMC_USB_DEBOUNCE_VAL(x)               ((x) & 0xffff)
348
349 #define PMC_USB_AO                              0xf0
350 #define   HSIC_RESERVED(inst)                   (3 << UHSIC_INST(inst, 14, 18))
351 #define   STROBE_VAL_PD(inst)                   (1 << UHSIC_INST(inst, 12, 16))
352 #define   DATA_VAL_PD(inst)                     (1 << UHSIC_INST(inst, 13, 17))
353 #define   PMC_POWER_DOWN_MASK                   0xffff
354 #define   USB_ID_PD(inst)                               (1 << ((4*(inst))+3))
355 #define   VBUS_WAKEUP_PD(inst)                  (1 << ((4*(inst))+2))
356 #define   USBON_VAL_PD(inst)                    (1 << ((4*(inst))+1))
357 #define   USBON_VAL_PD_P2                       (1 << 9)
358 #define   USBON_VAL_PD_P1                       (1 << 5)
359 #define   USBON_VAL_PD_P0                       (1 << 1)
360 #define   USBOP_VAL_PD(inst)                    (1 << (4*(inst)))
361 #define   USBOP_VAL_PD_P2                       (1 << 8)
362 #define   USBOP_VAL_PD_P1                       (1 << 4)
363 #define   USBOP_VAL_PD_P0                       (1 << 0)
364 #define   PMC_USB_AO_ID_PD_P0                   (1 << 3)
365 #define   PMC_USB_AO_VBUS_WAKEUP_PD_P0  (1 << 2)
366
367 #define PMC_TRIGGERS                    0x1ec
368 #define   UTMIP_CLR_WALK_PTR(inst)      (1 << (inst))
369 #define   UTMIP_CLR_WALK_PTR_P2         (1 << 2)
370 #define   UTMIP_CLR_WALK_PTR_P1         (1 << 1)
371 #define   UTMIP_CLR_WALK_PTR_P0         (1 << 0)
372 #define   UTMIP_CAP_CFG(inst)   (1 << ((inst)+4))
373 #define   UTMIP_CAP_CFG_P2              (1 << 6)
374 #define   UTMIP_CAP_CFG_P1              (1 << 5)
375 #define   UTMIP_CAP_CFG_P0              (1 << 4)
376 #define   UTMIP_CLR_WAKE_ALARM(inst)            (1 << ((inst)+12))
377 #define   UTMIP_CLR_WAKE_ALARM_P2       (1 << 14)
378
379 #define PMC_PAD_CFG             (0x1f4)
380
381 #define PMC_UTMIP_TERM_PAD_CFG  0x1f8
382 #define   PMC_TCTRL_VAL(x)      (((x) & 0x1f) << 5)
383 #define   PMC_RCTRL_VAL(x)      (((x) & 0x1f) << 0)
384
385 #define PMC_SLEEP_CFG                   0x1fc
386 #define   UTMIP_TCTRL_USE_PMC(inst) (1 << ((8*(inst))+3))
387 #define   UTMIP_TCTRL_USE_PMC_P2                (1 << 19)
388 #define   UTMIP_TCTRL_USE_PMC_P1                (1 << 11)
389 #define   UTMIP_TCTRL_USE_PMC_P0                (1 << 3)
390 #define   UTMIP_RCTRL_USE_PMC(inst) (1 << ((8*(inst))+2))
391 #define   UTMIP_RCTRL_USE_PMC_P2                (1 << 18)
392 #define   UTMIP_RCTRL_USE_PMC_P1                (1 << 10)
393 #define   UTMIP_RCTRL_USE_PMC_P0                (1 << 2)
394 #define   UTMIP_FSLS_USE_PMC(inst)      (1 << ((8*(inst))+1))
395 #define   UTMIP_FSLS_USE_PMC_P2         (1 << 17)
396 #define   UTMIP_FSLS_USE_PMC_P1         (1 << 9)
397 #define   UTMIP_FSLS_USE_PMC_P0         (1 << 1)
398 #define   UTMIP_MASTER_ENABLE(inst) (1 << (8*(inst)))
399 #define   UTMIP_MASTER_ENABLE_P2                (1 << 16)
400 #define   UTMIP_MASTER_ENABLE_P1                (1 << 8)
401 #define   UTMIP_MASTER_ENABLE_P0                (1 << 0)
402
403 #define PMC_SLEEPWALK_CFG               0x200
404 #define   UTMIP_LINEVAL_WALK_EN(inst) (1 << ((8*(inst))+7))
405 #define   UTMIP_LINEVAL_WALK_EN_P2      (1 << 23)
406 #define   UTMIP_LINEVAL_WALK_EN_P1      (1 << 15)
407 #define   UTMIP_LINEVAL_WALK_EN_P0      (1 << 7)
408 #define   UTMIP_WAKE_VAL(inst, x) (((x) & 0xf) << ((8*(inst))+4))
409 #define   UTMIP_WAKE_VAL_P2(x)          (((x) & 0xf) << 20)
410 #define   UTMIP_WAKE_VAL_P1(x)          (((x) & 0xf) << 12)
411 #define   UTMIP_WAKE_VAL_P0(x)          (((x) & 0xf) << 4)
412 #define   WAKE_VAL_NONE         0xc
413 #define   WAKE_VAL_ANY                  0xF
414 #define   WAKE_VAL_FSJ                  0x2
415 #define   WAKE_VAL_FSK                  0x1
416 #define   WAKE_VAL_SE0                  0x0
417
418 #define PMC_SLEEPWALK_REG(inst)         (0x204 + (4*(inst)))
419 #define   UTMIP_USBOP_RPD_A     (1 << 0)
420 #define   UTMIP_USBON_RPD_A     (1 << 1)
421 #define   UTMIP_AP_A                    (1 << 4)
422 #define   UTMIP_AN_A                    (1 << 5)
423 #define   UTMIP_HIGHZ_A         (1 << 6)
424 #define   UTMIP_USBOP_RPD_B     (1 << 8)
425 #define   UTMIP_USBON_RPD_B     (1 << 9)
426 #define   UTMIP_AP_B                    (1 << 12)
427 #define   UTMIP_AN_B                    (1 << 13)
428 #define   UTMIP_HIGHZ_B         (1 << 14)
429 #define   UTMIP_USBOP_RPD_C     (1 << 16)
430 #define   UTMIP_USBON_RPD_C     (1 << 17)
431 #define   UTMIP_AP_C            (1 << 20)
432 #define   UTMIP_AN_C            (1 << 21)
433 #define   UTMIP_HIGHZ_C         (1 << 22)
434 #define   UTMIP_USBOP_RPD_D     (1 << 24)
435 #define   UTMIP_USBON_RPD_D     (1 << 25)
436 #define   UTMIP_AP_D            (1 << 28)
437 #define   UTMIP_AN_D            (1 << 29)
438 #define   UTMIP_HIGHZ_D         (1 << 30)
439
440 #define UTMIP_STATUS            0x214
441 #define   UTMIP_WALK_PTR_VAL(inst)      (0x3 << ((inst)*2))
442 #define   UTMIP_USBOP_VAL(inst)         (1 << ((2*(inst)) + 8))
443 #define   UTMIP_USBOP_VAL_P2            (1 << 12)
444 #define   UTMIP_USBOP_VAL_P1            (1 << 10)
445 #define   UTMIP_USBOP_VAL_P0            (1 << 8)
446 #define   UTMIP_USBON_VAL(inst)         (1 << ((2*(inst)) + 9))
447 #define   UTMIP_USBON_VAL_P2            (1 << 13)
448 #define   UTMIP_USBON_VAL_P1            (1 << 11)
449 #define   UTMIP_USBON_VAL_P0            (1 << 9)
450 #define   UTMIP_WAKE_ALARM(inst)                (1 << ((inst) + 16))
451 #define   UTMIP_WAKE_ALARM_P2   (1 << 18)
452 #define   UTMIP_WAKE_ALARM_P1   (1 << 17)
453 #define   UTMIP_WAKE_ALARM_P0   (1 << 16)
454 #define   UTMIP_WALK_PTR(inst)  (1 << ((inst)*2))
455 #define   UTMIP_WALK_PTR_P2     (1 << 4)
456 #define   UTMIP_WALK_PTR_P1     (1 << 2)
457 #define   UTMIP_WALK_PTR_P0     (1 << 0)
458
459 #define USB1_PREFETCH_ID               6
460 #define USB2_PREFETCH_ID               18
461 #define USB3_PREFETCH_ID               17
462
463 #define PMC_UTMIP_FAKE          0x218
464 #define   USBON_VAL(inst)       (1 << ((4*(inst))+1))
465 #define   USBON_VAL_P2                  (1 << 9)
466 #define   USBON_VAL_P1                  (1 << 5)
467 #define   USBON_VAL_P0                  (1 << 1)
468 #define   USBOP_VAL(inst)       (1 << (4*(inst)))
469 #define   USBOP_VAL_P2                  (1 << 8)
470 #define   USBOP_VAL_P1                  (1 << 4)
471 #define   USBOP_VAL_P0                  (1 << 0)
472
473 #define PMC_UTMIP_BIAS_MASTER_CNTRL 0x270
474 #define   BIAS_MASTER_PROG_VAL          (1 << 1)
475
476 #define PMC_UTMIP_MASTER_CONFIG         0x274
477 #define   UTMIP_PWR(inst)               (1 << (inst))
478
479 #define FUSE_USB_CALIB_0                0x1F0
480 #define   XCVR_SETUP(x) (((x) & 0x7F) << 0)
481 #define   XCVR_SETUP_LSB_MASK   0xF
482 #define   XCVR_SETUP_MSB_MASK   0x70
483 #define   XCVR_SETUP_LSB_MAX_VAL        0xF
484
485 #define APB_MISC_GP_OBSCTRL_0   0x818
486 #define APB_MISC_GP_OBSDATA_0   0x81c
487
488 #define PADCTL_SNPS_OC_MAP      0xC
489 #define   CONTROLLER_OC(inst, x)        (((x) & 0x7) << (3 * (inst)))
490 #define   CONTROLLER_OC_P0(x)   (((x) & 0x7) << 0)
491 #define   CONTROLLER_OC_P1(x)   (((x) & 0x7) << 3)
492 #define   CONTROLLER_OC_P2(x)   (((x) & 0x7) << 6)
493
494 #define PADCTL_OC_DET           0x18
495 #define   ENABLE0_OC_MAP(x)     (((x) & 0x7) << 10)
496 #define   ENABLE1_OC_MAP(x)     (((x) & 0x7) << 13)
497
498 /* ULPI GPIO */
499 #define ULPI_STP        TEGRA_GPIO_PY3
500 #define ULPI_DIR        TEGRA_GPIO_PY1
501 #define ULPI_D0         TEGRA_GPIO_PO1
502 #define ULPI_D1         TEGRA_GPIO_PO2
503
504 #define TEGRA_STREAM_DISABLE    0x1f8
505 #define TEGRA_STREAM_DISABLE_OFFSET     (1 << 4)
506
507 /* These values (in milli second) are taken from the battery charging spec */
508 #define TDP_SRC_ON_MS    100
509 #define TDPSRC_CON_MS    40
510
511 /* Force port resume wait time in micro second on remote resume */
512 #define FPR_WAIT_TIME_US 25000
513
514 #ifdef DEBUG
515 #define DBG(stuff...)   pr_info("tegra11x_usb_phy: " stuff)
516 #else
517 #define DBG(stuff...)   do {} while (0)
518 #endif
519
520 #if 0
521 #define PHY_DBG(stuff...)       pr_info("tegra11x_usb_phy: " stuff)
522 #else
523 #define PHY_DBG(stuff...)       do {} while (0)
524 #endif
525
526 /* define HSIC phy params */
527 #define HSIC_SYNC_START_DELAY           9
528 #define HSIC_IDLE_WAIT_DELAY            17
529 #define HSIC_ELASTIC_UNDERRUN_LIMIT     16
530 #define HSIC_ELASTIC_OVERRUN_LIMIT      16
531
532 static u32 utmip_rctrl_val, utmip_tctrl_val;
533 static DEFINE_SPINLOCK(utmip_pad_lock);
534 static int utmip_pad_count;
535
536 static struct tegra_xtal_freq utmip_freq_table[] = {
537         {
538                 .freq = 12000000,
539                 .enable_delay = 0x02,
540                 .stable_count = 0x2F,
541                 .active_delay = 0x04,
542                 .xtal_freq_count = 0x76,
543                 .debounce = 0x7530,
544                 .pdtrk_count = 5,
545         },
546         {
547                 .freq = 13000000,
548                 .enable_delay = 0x02,
549                 .stable_count = 0x33,
550                 .active_delay = 0x05,
551                 .xtal_freq_count = 0x7F,
552                 .debounce = 0x7EF4,
553                 .pdtrk_count = 5,
554         },
555         {
556                 .freq = 19200000,
557                 .enable_delay = 0x03,
558                 .stable_count = 0x4B,
559                 .active_delay = 0x06,
560                 .xtal_freq_count = 0xBB,
561                 .debounce = 0xBB80,
562                 .pdtrk_count = 7,
563         },
564         {
565                 .freq = 26000000,
566                 .enable_delay = 0x04,
567                 .stable_count = 0x66,
568                 .active_delay = 0x09,
569                 .xtal_freq_count = 0xFE,
570                 .debounce = 0xFDE8,
571                 .pdtrk_count = 9,
572         },
573 };
574
575 static struct tegra_xtal_freq uhsic_freq_table[] = {
576         {
577                 .freq = 12000000,
578                 .enable_delay = 0x02,
579                 .stable_count = 0x2F,
580                 .active_delay = 0x0,
581                 .xtal_freq_count = 0x1CA,
582         },
583         {
584                 .freq = 13000000,
585                 .enable_delay = 0x02,
586                 .stable_count = 0x33,
587                 .active_delay = 0x0,
588                 .xtal_freq_count = 0x1F0,
589         },
590         {
591                 .freq = 19200000,
592                 .enable_delay = 0x03,
593                 .stable_count = 0x4B,
594                 .active_delay = 0x0,
595                 .xtal_freq_count = 0x2DD,
596         },
597         {
598                 .freq = 26000000,
599                 .enable_delay = 0x04,
600                 .stable_count = 0x66,
601                 .active_delay = 0x0,
602                 .xtal_freq_count = 0x3E0,
603         },
604 };
605
606 static int _usb_phy_init(struct tegra_usb_phy *phy)
607 {
608         unsigned long val;
609         void __iomem *base = phy->regs;
610
611         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
612
613         val = readl(base + HOSTPC1_DEVLC);
614         val &= ~HOSTPC1_DEVLC_STS;
615         writel(val, base + HOSTPC1_DEVLC);
616
617         val = readl(base + USB_IF_SPARE);
618         val |= USB_HS_RSM_EOP_EN;
619         val |= USB_PORT_SUSPEND_EN;
620         writel(val, base + USB_IF_SPARE);
621
622         val =  readl(base + TEGRA_STREAM_DISABLE);
623 #if !defined(CONFIG_TEGRA_SILICON_PLATFORM)
624         val |= TEGRA_STREAM_DISABLE_OFFSET;
625 #else
626         val &= ~TEGRA_STREAM_DISABLE_OFFSET;
627 #endif
628         writel(val , base + TEGRA_STREAM_DISABLE);
629
630         return 0;
631 }
632
633 static void usb_phy_fence_read(struct tegra_usb_phy *phy)
634 {
635         /* Fence read for coherency of AHB master intiated writes */
636         if (phy->inst == 0)
637                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB1_PREFETCH_ID));
638         else if (phy->inst == 1)
639                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB2_PREFETCH_ID));
640         else if (phy->inst == 2)
641                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB3_PREFETCH_ID));
642         return;
643 }
644
645 static int usb_phy_reset(struct tegra_usb_phy *phy)
646 {
647         unsigned long val;
648         void __iomem *base = phy->regs;
649
650         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
651
652 #if !defined(CONFIG_TEGRA_SILICON_PLATFORM)
653         val =  readl(base + TEGRA_STREAM_DISABLE);
654         val |= TEGRA_STREAM_DISABLE_OFFSET;
655         writel(val , base + TEGRA_STREAM_DISABLE);
656 #endif
657         val = readl(base + USB_TXFILLTUNING);
658         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
659                 val = USB_FIFO_TXFILL_THRES(0x10);
660                 writel(val, base + USB_TXFILLTUNING);
661         }
662
663 return 0;
664 }
665
666 static void utmip_setup_pmc_wake_detect(struct tegra_usb_phy *phy)
667 {
668         unsigned long val, pmc_pad_cfg_val;
669         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
670         unsigned  int inst = phy->inst;
671         void __iomem *base = phy->regs;
672         enum usb_phy_port_speed port_speed;
673
674         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
675
676         port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
677                 HOSTPC1_DEVLC_PSPD_MASK;
678         /*Set PMC MASTER bits to do the following
679         * a. Take over the UTMI drivers
680         * b. set up such that it will take over resume
681         *        if remote wakeup is detected
682         * Prepare PMC to take over suspend-wake detect-drive resume until USB
683         * controller ready
684         */
685
686         /* disable master enable in PMC */
687         val = readl(pmc_base + PMC_SLEEP_CFG);
688         val &= ~UTMIP_MASTER_ENABLE(inst);
689         writel(val, pmc_base + PMC_SLEEP_CFG);
690
691         /* UTMIP_PWR_PX=1 for power savings mode */
692         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
693         val |= UTMIP_PWR(inst);
694         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
695
696         /* config debouncer */
697         val = readl(pmc_base + PMC_USB_DEBOUNCE);
698         val &= ~UTMIP_LINE_DEB_CNT(~0);
699         val |= UTMIP_LINE_DEB_CNT(1);
700         val |= PMC_USB_DEBOUNCE_VAL(2);
701         writel(val, pmc_base + PMC_USB_DEBOUNCE);
702
703         /* Make sure nothing is happening on the line with respect to PMC */
704         val = readl(pmc_base + PMC_UTMIP_FAKE);
705         val &= ~USBOP_VAL(inst);
706         val &= ~USBON_VAL(inst);
707         writel(val, pmc_base + PMC_UTMIP_FAKE);
708
709         /* Make sure wake value for line is none */
710         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
711         val &= ~UTMIP_LINEVAL_WALK_EN(inst);
712         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
713         val = readl(pmc_base + PMC_SLEEP_CFG);
714         val &= ~UTMIP_WAKE_VAL(inst, ~0);
715         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
716         writel(val, pmc_base + PMC_SLEEP_CFG);
717
718         /* turn off pad detectors */
719         val = readl(pmc_base + PMC_USB_AO);
720         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
721         writel(val, pmc_base + PMC_USB_AO);
722
723         /* Remove fake values and make synchronizers work a bit */
724         val = readl(pmc_base + PMC_UTMIP_FAKE);
725         val &= ~USBOP_VAL(inst);
726         val &= ~USBON_VAL(inst);
727         writel(val, pmc_base + PMC_UTMIP_FAKE);
728
729         /* Enable which type of event can trigger a walk,
730         * in this case usb_line_wake */
731         val = readl(pmc_base + PMC_SLEEPWALK_CFG);
732         val |= UTMIP_LINEVAL_WALK_EN(inst);
733         writel(val, pmc_base + PMC_SLEEPWALK_CFG);
734
735         /* Capture FS/LS pad configurations */
736         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
737         val = readl(pmc_base + PMC_TRIGGERS);
738         val |= UTMIP_CAP_CFG(inst);
739         writel(val, pmc_base + PMC_TRIGGERS);
740         udelay(1);
741         pmc_pad_cfg_val = readl(pmc_base + PMC_PAD_CFG);
742
743         /* BIAS MASTER_ENABLE=0 */
744         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
745         val &= ~BIAS_MASTER_PROG_VAL;
746         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
747
748         /* program walk sequence for remote or hotplug wakeup */
749         if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
750                 /* program walk sequence, maintain a J, followed by a driven K
751                 * to signal a resume once an wake event is detected */
752                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
753                 val &= ~UTMIP_AP_A;
754                 val |= UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
755                         UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_AP_B |
756                         UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_AP_C |
757                         UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_AP_D |
758                         UTMIP_AN_A | UTMIP_AN_C | UTMIP_AN_B | UTMIP_AN_D ;
759                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
760
761                 if (port_speed == USB_PHY_PORT_SPEED_LOW) {
762                         val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
763                         val &= ~(UTMIP_AN_B | UTMIP_HIGHZ_B | UTMIP_AN_C |
764                                 UTMIP_HIGHZ_C | UTMIP_AN_D | UTMIP_HIGHZ_D);
765                         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
766                 } else {
767                         val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
768                         val &= ~(UTMIP_AN_A | UTMIP_AP_B | UTMIP_HIGHZ_B |
769                                  UTMIP_AP_C | UTMIP_HIGHZ_C | UTMIP_AP_D |
770                                  UTMIP_HIGHZ_D);
771                         val |= UTMIP_AP_A;
772                         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
773                 }
774                 phy->pmc_remote_wakeup = false;
775         } else {
776                 /* program walk sequence, pull down both dp and dn lines,
777                 * tristate lines once an hotplug-in wake event is detected */
778                 val = readl(pmc_base + PMC_SLEEPWALK_REG(inst));
779                 val |= UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A;
780                 val &= ~UTMIP_AP_A;
781                 val &= ~UTMIP_AN_A;
782                 val |= UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B;
783                 val &= ~UTMIP_AP_B;
784                 val &= ~UTMIP_AN_B;
785                 val |= UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C;
786                 val &= ~UTMIP_AP_C;
787                 val &= ~UTMIP_AN_C;
788                 val |= UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
789                 val &= ~UTMIP_AP_D;
790                 val &= ~UTMIP_AN_D;
791                 writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
792                 phy->pmc_hotplug_wakeup = false;
793         }
794
795         /* turn on pad detectors */
796         val = readl(pmc_base + PMC_USB_AO);
797         val &= ~(USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
798         writel(val, pmc_base + PMC_USB_AO);
799
800         /* Add small delay before usb detectors provide stable line values */
801         mdelay(1);
802
803         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
804         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
805         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
806         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
807
808         /* Turn over pad configuration to PMC  for line wake events*/
809         val = readl(pmc_base + PMC_SLEEP_CFG);
810         val &= ~UTMIP_WAKE_VAL(inst, ~0);
811         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_ANY);
812         val |= UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst);
813         val |= UTMIP_MASTER_ENABLE(inst) | UTMIP_FSLS_USE_PMC(inst);
814         writel(val, pmc_base + PMC_SLEEP_CFG);
815
816         val = readl(base + UTMIP_PMC_WAKEUP0);
817         val |= EVENT_INT_ENB;
818         writel(val, base + UTMIP_PMC_WAKEUP0);
819         PHY_DBG("%s ENABLE_PMC inst = %d\n", __func__, inst);
820 }
821
822 static void utmip_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy)
823 {
824         unsigned long val;
825         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
826         unsigned  int inst = phy->inst;
827         void __iomem *base = phy->regs;
828
829         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
830
831         val = readl(pmc_base + PMC_SLEEP_CFG);
832         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
833         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
834         writel(val, pmc_base + PMC_SLEEP_CFG);
835
836         val = readl(base + UTMIP_PMC_WAKEUP0);
837         val &= ~EVENT_INT_ENB;
838         writel(val, base + UTMIP_PMC_WAKEUP0);
839
840         /* Disable PMC master mode by clearing MASTER_EN */
841         val = readl(pmc_base + PMC_SLEEP_CFG);
842         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
843                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
844         writel(val, pmc_base + PMC_SLEEP_CFG);
845
846         val = readl(pmc_base + PMC_TRIGGERS);
847         val &= ~UTMIP_CAP_CFG(inst);
848         writel(val, pmc_base + PMC_TRIGGERS);
849
850         /* turn off pad detectors */
851         val = readl(pmc_base + PMC_USB_AO);
852         val |= (USBOP_VAL_PD(inst) | USBON_VAL_PD(inst));
853         writel(val, pmc_base + PMC_USB_AO);
854
855         val = readl(pmc_base + PMC_TRIGGERS);
856         val |= UTMIP_CLR_WALK_PTR(inst);
857         val |= UTMIP_CLR_WAKE_ALARM(inst);
858         writel(val, pmc_base + PMC_TRIGGERS);
859
860         phy->pmc_remote_wakeup = false;
861         phy->pmc_hotplug_wakeup = false;
862         PHY_DBG("%s DISABLE_PMC inst = %d\n", __func__, inst);
863 }
864
865 static bool utmi_phy_pmc_wake_detected(struct tegra_usb_phy *phy)
866 {
867         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
868         void __iomem *base = phy->regs;
869         unsigned  int inst = phy->inst;
870         u32 val;
871
872         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
873         val = readl(base + UTMIP_PMC_WAKEUP0);
874         if (val & EVENT_INT_ENB) {
875                 val = readl(pmc_base + UTMIP_STATUS);
876                 if (UTMIP_WAKE_ALARM(inst) & val) {
877                         val = readl(pmc_base + PMC_SLEEP_CFG);
878                         val &= ~UTMIP_WAKE_VAL(inst, 0xF);
879                         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE);
880                         writel(val, pmc_base + PMC_SLEEP_CFG);
881
882                         val = readl(pmc_base + PMC_TRIGGERS);
883                         val |= UTMIP_CLR_WAKE_ALARM(inst);
884                         writel(val, pmc_base + PMC_TRIGGERS);
885
886                         val = readl(base + UTMIP_PMC_WAKEUP0);
887                         val &= ~EVENT_INT_ENB;
888                         writel(val, base + UTMIP_PMC_WAKEUP0);
889
890                         val = readl(pmc_base + UTMIP_STATUS);
891                         if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
892                                 pr_info("%s: utmip remote wake detected\n",
893                                                                 __func__);
894                                 phy->pmc_remote_wakeup = true;
895                         } else {
896                                 phy->pmc_hotplug_wakeup = true;
897                         }
898                         return true;
899                 }
900         }
901         return false;
902 }
903
904 static void utmi_phy_enable_trking_data(struct tegra_usb_phy *phy)
905 {
906         void __iomem *base = IO_ADDRESS(TEGRA_USB_BASE);
907         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
908         static bool init_done = false;
909         u32 val;
910
911         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
912
913         /* Should be done only once after system boot */
914         if (init_done)
915                 return;
916
917         clk_enable(phy->utmi_pad_clk);
918         /* Bias pad MASTER_ENABLE=1 */
919         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
920         val |= BIAS_MASTER_PROG_VAL;
921         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
922
923         /* Setting the tracking length time */
924         val = readl(base + UTMIP_BIAS_CFG1);
925         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
926         val |= UTMIP_BIAS_PDTRK_COUNT(5);
927         writel(val, base + UTMIP_BIAS_CFG1);
928
929         /* Bias PDTRK is Shared and MUST be done from USB1 ONLY, PD_TRK=0 */
930         val = readl(base + UTMIP_BIAS_CFG1);
931         val &= ~UTMIP_BIAS_PDTRK_POWERDOWN;
932         writel(val, base + UTMIP_BIAS_CFG1);
933
934         val = readl(base + UTMIP_BIAS_CFG1);
935         val |= UTMIP_BIAS_PDTRK_POWERUP;
936         writel(val, base + UTMIP_BIAS_CFG1);
937
938         /* Wait for 25usec */
939         udelay(25);
940
941         /* Bias pad MASTER_ENABLE=0 */
942         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
943         val &= ~BIAS_MASTER_PROG_VAL;
944         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
945
946         /* Wait for 1usec */
947         udelay(1);
948
949         /* Bias pad MASTER_ENABLE=1 */
950         val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
951         val |= BIAS_MASTER_PROG_VAL;
952         writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL);
953
954         /* Read RCTRL and TCTRL from UTMIP space */
955         val = readl(base + UTMIP_BIAS_STS0);
956         utmip_rctrl_val = ffz(UTMIP_RCTRL_VAL(val));
957         utmip_tctrl_val = ffz(UTMIP_TCTRL_VAL(val));
958
959         /* PD_TRK=1 */
960         val = readl(base + UTMIP_BIAS_CFG1);
961         val |= UTMIP_BIAS_PDTRK_POWERDOWN;
962         writel(val, base + UTMIP_BIAS_CFG1);
963
964         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
965         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
966         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
967         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
968         clk_disable(phy->utmi_pad_clk);
969         init_done = true;
970 }
971
972 static void utmip_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy)
973 {
974         unsigned long val;
975         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
976         unsigned  int inst = phy->inst;
977
978         /* power down UTMIP interfaces */
979         val = readl(pmc_base + PMC_UTMIP_MASTER_CONFIG);
980         val |= UTMIP_PWR(inst);
981         writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG);
982
983         /* setup sleep walk usb controller */
984         val = UTMIP_USBOP_RPD_A | UTMIP_USBON_RPD_A | UTMIP_HIGHZ_A |
985                 UTMIP_USBOP_RPD_B | UTMIP_USBON_RPD_B | UTMIP_HIGHZ_B |
986                 UTMIP_USBOP_RPD_C | UTMIP_USBON_RPD_C | UTMIP_HIGHZ_C |
987                 UTMIP_USBOP_RPD_D | UTMIP_USBON_RPD_D | UTMIP_HIGHZ_D;
988         writel(val, pmc_base + PMC_SLEEPWALK_REG(inst));
989
990         /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */
991         val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG);
992         val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val);
993         writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG);
994
995         /* Turn over pad configuration to PMC */
996         val = readl(pmc_base + PMC_SLEEP_CFG);
997         val &= ~UTMIP_WAKE_VAL(inst, ~0);
998         val |= UTMIP_WAKE_VAL(inst, WAKE_VAL_NONE) |
999                 UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
1000                 UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst);
1001         writel(val, pmc_base + PMC_SLEEP_CFG);
1002         PHY_DBG("%s ENABLE_PMC inst = %d\n", __func__, inst);
1003 }
1004
1005 static void utmip_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
1006 {
1007         unsigned long val;
1008         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1009         unsigned  int inst = phy->inst;
1010
1011         /* Disable PMC master mode by clearing MASTER_EN */
1012         val = readl(pmc_base + PMC_SLEEP_CFG);
1013         val &= ~(UTMIP_RCTRL_USE_PMC(inst) | UTMIP_TCTRL_USE_PMC(inst) |
1014                         UTMIP_FSLS_USE_PMC(inst) | UTMIP_MASTER_ENABLE(inst));
1015         writel(val, pmc_base + PMC_SLEEP_CFG);
1016         mdelay(1);
1017         PHY_DBG("%s DISABLE_PMC inst = %d\n", __func__, inst);
1018 }
1019
1020
1021
1022 static int usb_phy_bringup_host_controller(struct tegra_usb_phy *phy)
1023 {
1024         unsigned long val;
1025         void __iomem *base = phy->regs;
1026
1027         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1028         PHY_DBG("[%d] USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n",
1029         __LINE__, readl(base + USB_USBSTS), readl(base + USB_PORTSC),
1030                                                         phy->port_speed);
1031
1032         /* Device is plugged in when system is in LP0 */
1033         /* Bring up the controller from LP0*/
1034         val = readl(base + USB_USBCMD);
1035         val |= USB_CMD_RESET;
1036         writel(val, base + USB_USBCMD);
1037
1038         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1039                 USB_CMD_RESET, 0, 2500) < 0) {
1040                 pr_err("%s: timeout waiting for reset\n", __func__);
1041         }
1042
1043         val = readl(base + USB_USBMODE);
1044         val &= ~USB_USBMODE_MASK;
1045         val |= USB_USBMODE_HOST;
1046         writel(val, base + USB_USBMODE);
1047         val = readl(base + HOSTPC1_DEVLC);
1048         val &= ~HOSTPC1_DEVLC_PTS(~0);
1049
1050         if (phy->pdata->phy_intf == TEGRA_USB_PHY_INTF_HSIC)
1051                 val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
1052         else
1053                 val |= HOSTPC1_DEVLC_STS;
1054         writel(val, base + HOSTPC1_DEVLC);
1055
1056         /* Enable Port Power */
1057         val = readl(base + USB_PORTSC);
1058         val |= USB_PORTSC_PP;
1059         writel(val, base + USB_PORTSC);
1060         udelay(10);
1061
1062         /* Check if the phy resume from LP0. When the phy resume from LP0
1063          * USB register will be reset.to zero */
1064         if (!readl(base + USB_ASYNCLISTADDR)) {
1065                 /* Program the field PTC based on the saved speed mode */
1066                 val = readl(base + USB_PORTSC);
1067                 val &= ~USB_PORTSC_PTC(~0);
1068                 if ((phy->port_speed == USB_PHY_PORT_SPEED_HIGH) ||
1069                         (phy->pdata->phy_intf == TEGRA_USB_PHY_INTF_HSIC))
1070                         val |= USB_PORTSC_PTC(5);
1071                 else if (phy->port_speed == USB_PHY_PORT_SPEED_FULL)
1072                         val |= USB_PORTSC_PTC(6);
1073                 else if (phy->port_speed == USB_PHY_PORT_SPEED_LOW)
1074                         val |= USB_PORTSC_PTC(7);
1075                 writel(val, base + USB_PORTSC);
1076                 udelay(10);
1077
1078                 /* Disable test mode by setting PTC field to NORMAL_OP */
1079                 val = readl(base + USB_PORTSC);
1080                 val &= ~USB_PORTSC_PTC(~0);
1081                 writel(val, base + USB_PORTSC);
1082                 udelay(10);
1083         }
1084
1085         /* Poll until CCS is enabled */
1086         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_CCS,
1087                                                  USB_PORTSC_CCS, 2000)) {
1088                 pr_err("%s: timeout waiting for USB_PORTSC_CCS\n", __func__);
1089         }
1090
1091         /* Poll until PE is enabled */
1092         if (usb_phy_reg_status_wait(base + USB_PORTSC, USB_PORTSC_PE,
1093                                                  USB_PORTSC_PE, 2000)) {
1094                 pr_err("%s: timeout waiting for USB_PORTSC_PE\n", __func__);
1095         }
1096
1097         /* Clear the PCI status, to avoid an interrupt taken upon resume */
1098         val = readl(base + USB_USBSTS);
1099         val |= USB_USBSTS_PCI;
1100         writel(val, base + USB_USBSTS);
1101
1102         phy->ctrlr_suspended = false;
1103         if (!phy->pmc_remote_wakeup) {
1104                 /* Put controller in suspend mode by writing 1
1105                  * to SUSP bit of PORTSC */
1106                 val = readl(base + USB_PORTSC);
1107                 if ((val & USB_PORTSC_PP) && (val & USB_PORTSC_PE)) {
1108                         val |= USB_PORTSC_SUSP;
1109                         writel(val, base + USB_PORTSC);
1110                         phy->ctrlr_suspended = true;
1111                         /* Wait until port suspend completes */
1112                         if (usb_phy_reg_status_wait(base + USB_PORTSC,
1113                                 USB_PORTSC_SUSP, USB_PORTSC_SUSP, 4000)) {
1114                                 pr_err("%s: timeout waiting for PORT_SUSPEND\n",
1115                                         __func__);
1116                         }
1117                 }
1118         }
1119         PHY_DBG("[%d] USB_USBSTS[0x%x] USB_PORTSC[0x%x] port_speed[%d]\n",
1120                 __LINE__, readl(base + USB_USBSTS), readl(base + USB_PORTSC),
1121                 phy->port_speed);
1122
1123         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1124                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1125         return 0;
1126 }
1127
1128 static unsigned int utmi_phy_xcvr_setup_value(struct tegra_usb_phy *phy)
1129 {
1130         struct tegra_utmi_config *cfg = &phy->pdata->u_cfg.utmi;
1131         signed long val;
1132
1133         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1134
1135         if (cfg->xcvr_use_fuses) {
1136                 val = XCVR_SETUP(tegra_fuse_readl(FUSE_USB_CALIB_0));
1137                 if (cfg->xcvr_use_lsb) {
1138                         val = min((unsigned int) ((val & XCVR_SETUP_LSB_MASK)
1139                                 + cfg->xcvr_setup_offset),
1140                                 (unsigned int) XCVR_SETUP_LSB_MAX_VAL);
1141                         val |= (cfg->xcvr_setup & XCVR_SETUP_MSB_MASK);
1142                 } else {
1143                         if (cfg->xcvr_setup_offset <= UTMIP_XCVR_MAX_OFFSET)
1144                                 val = val + cfg->xcvr_setup_offset;
1145
1146                         if (val > UTMIP_XCVR_SETUP_MAX_VALUE) {
1147                                 val = UTMIP_XCVR_SETUP_MAX_VALUE;
1148                                 pr_info("%s: reset XCVR_SETUP to max value\n",
1149                                                 __func__);
1150                         } else if (val < UTMIP_XCVR_SETUP_MIN_VALUE) {
1151                                 val = UTMIP_XCVR_SETUP_MIN_VALUE;
1152                                 pr_info("%s: reset XCVR_SETUP to min value\n",
1153                                                 __func__);
1154                         }
1155                 }
1156         } else {
1157                 val = cfg->xcvr_setup;
1158         }
1159
1160         return (unsigned int) val;
1161 }
1162
1163 static int utmi_phy_open(struct tegra_usb_phy *phy)
1164 {
1165         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1166         unsigned long parent_rate, val;
1167         int i;
1168
1169         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1170
1171         phy->utmi_pad_clk = clk_get_sys("utmip-pad", NULL);
1172         if (IS_ERR(phy->utmi_pad_clk)) {
1173                 pr_err("%s: can't get utmip pad clock\n", __func__);
1174                 return PTR_ERR(phy->utmi_pad_clk);
1175         }
1176
1177         phy->utmi_xcvr_setup = utmi_phy_xcvr_setup_value(phy);
1178
1179         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
1180         for (i = 0; i < ARRAY_SIZE(utmip_freq_table); i++) {
1181                 if (utmip_freq_table[i].freq == parent_rate) {
1182                         phy->freq = &utmip_freq_table[i];
1183                         break;
1184                 }
1185         }
1186         if (!phy->freq) {
1187                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
1188                 return -EINVAL;
1189         }
1190
1191         /* Power-up the VBUS detector for UTMIP PHY */
1192         val = readl(pmc_base + PMC_USB_AO);
1193         val &= ~(PMC_USB_AO_VBUS_WAKEUP_PD_P0);
1194         if (phy->pdata->builtin_host_disabled)
1195                 val |= PMC_USB_AO_ID_PD_P0;
1196         else
1197                 val &= ~PMC_USB_AO_ID_PD_P0;
1198         writel(val, (pmc_base + PMC_USB_AO));
1199
1200         utmip_powerup_pmc_wake_detect(phy);
1201
1202         return 0;
1203 }
1204
1205 static void utmi_phy_close(struct tegra_usb_phy *phy)
1206 {
1207         unsigned long val;
1208         void __iomem *base = phy->regs;
1209         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1210
1211         DBG("%s inst:[%d]\n", __func__, phy->inst);
1212
1213         /* Disable PHY clock valid interrupts while going into suspend*/
1214         if (phy->hot_plug) {
1215                 val = readl(base + USB_SUSP_CTRL);
1216                 val &= ~USB_PHY_CLK_VALID_INT_ENB;
1217                 writel(val, base + USB_SUSP_CTRL);
1218         }
1219
1220         val = readl(pmc_base + PMC_SLEEP_CFG);
1221         if (val & UTMIP_MASTER_ENABLE(phy->inst))
1222                 utmip_phy_disable_pmc_bus_ctrl(phy);
1223
1224         clk_put(phy->utmi_pad_clk);
1225 }
1226
1227 static int utmi_phy_pad_power_on(struct tegra_usb_phy *phy)
1228 {
1229         unsigned long val, flags;
1230         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1231         void __iomem *clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
1232
1233         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1234
1235         val = readl(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1236         val &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
1237         writel(val, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1238
1239         clk_enable(phy->utmi_pad_clk);
1240
1241         spin_lock_irqsave(&utmip_pad_lock, flags);
1242         utmip_pad_count++;
1243
1244         val = readl(pad_base + UTMIP_BIAS_CFG0);
1245         val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
1246         val |= UTMIP_HSSQUELCH_LEVEL(0x2) | UTMIP_HSDISCON_LEVEL(0x1) |
1247                 UTMIP_HSDISCON_LEVEL_MSB;
1248         writel(val, pad_base + UTMIP_BIAS_CFG0);
1249
1250         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1251
1252         clk_disable(phy->utmi_pad_clk);
1253
1254         return 0;
1255 }
1256
1257 static int utmi_phy_pad_power_off(struct tegra_usb_phy *phy)
1258 {
1259         unsigned long val, flags;
1260         void __iomem *pad_base =  IO_ADDRESS(TEGRA_USB_BASE);
1261         void __iomem *clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
1262
1263         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1264
1265         clk_enable(phy->utmi_pad_clk);
1266         spin_lock_irqsave(&utmip_pad_lock, flags);
1267
1268         if (!utmip_pad_count) {
1269                 pr_err("%s: utmip pad already powered off\n", __func__);
1270                 goto out;
1271         }
1272         if (--utmip_pad_count == 0) {
1273                 val = readl(pad_base + UTMIP_BIAS_CFG0);
1274                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
1275                 val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) | UTMIP_HSDISCON_LEVEL(~0) |
1276                         UTMIP_HSDISCON_LEVEL_MSB);
1277                 writel(val, pad_base + UTMIP_BIAS_CFG0);
1278
1279                 val = readl(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1280                 val |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
1281                 writel(val, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1282         }
1283 out:
1284         spin_unlock_irqrestore(&utmip_pad_lock, flags);
1285         clk_disable(phy->utmi_pad_clk);
1286
1287         return 0;
1288 }
1289
1290 static int utmi_phy_irq(struct tegra_usb_phy *phy)
1291 {
1292         void __iomem *base = phy->regs;
1293         unsigned long val = 0;
1294         bool remote_wakeup = false;
1295         int irq_status = IRQ_HANDLED;
1296
1297         if (phy->phy_clk_on) {
1298                 DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1299                 DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1300                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1301                 DBG("USB_USBMODE[0x%x] USB_USBCMD[0x%x]\n",
1302                         readl(base + USB_USBMODE), readl(base + USB_USBCMD));
1303         }
1304
1305         usb_phy_fence_read(phy);
1306         /* check if it is pmc wake event */
1307         if (utmi_phy_pmc_wake_detected(phy))
1308                 remote_wakeup = phy->pmc_remote_wakeup;
1309
1310         if (phy->hot_plug) {
1311                 val = readl(base + USB_SUSP_CTRL);
1312                 if ((val  & USB_PHY_CLK_VALID_INT_STS) &&
1313                         (val  & USB_PHY_CLK_VALID_INT_ENB)) {
1314                         val &= ~USB_PHY_CLK_VALID_INT_ENB |
1315                                         USB_PHY_CLK_VALID_INT_STS;
1316                         writel(val , (base + USB_SUSP_CTRL));
1317
1318                         /* In case of remote wakeup PHY clock will not up
1319                          * immediately, so should not access any controller
1320                          * register but normal plug-in/plug-out should be
1321                          * executed
1322                          */
1323                         if (!remote_wakeup) {
1324                                 val = readl(base + USB_USBSTS);
1325                                 if (!(val  & USB_USBSTS_PCI)) {
1326                                         irq_status = IRQ_NONE;
1327                                         goto exit;
1328                                 }
1329
1330                                 val = readl(base + USB_PORTSC);
1331                                 if (val & USB_PORTSC_CCS)
1332                                         val &= ~USB_PORTSC_WKCN;
1333                                 else
1334                                         val &= ~USB_PORTSC_WKDS;
1335                                 val &= ~USB_PORTSC_RWC_BITS;
1336                                 writel(val , (base + USB_PORTSC));
1337                         }
1338                 } else if (!phy->phy_clk_on) {
1339                         if (remote_wakeup)
1340                                 irq_status = IRQ_HANDLED;
1341                         else
1342                                 irq_status = IRQ_NONE;
1343                         goto exit;
1344                 }
1345         }
1346 exit:
1347         return irq_status;
1348 }
1349
1350 static int utmi_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
1351 {
1352         unsigned long val;
1353         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1354         unsigned  int inst = phy->inst;
1355
1356         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1357         val = readl(pmc_base + PMC_SLEEP_CFG);
1358         if (val & UTMIP_MASTER_ENABLE(inst)) {
1359                 if (!remote_wakeup)
1360                         utmip_phy_disable_pmc_bus_ctrl(phy);
1361         }
1362
1363         return 0;
1364 }
1365
1366 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
1367 {
1368         unsigned long val;
1369         void __iomem *base = phy->regs;
1370
1371         PHY_DBG("%s(%d) inst:[%d] BEGIN\n", __func__, __LINE__, phy->inst);
1372         if (!phy->phy_clk_on) {
1373                 PHY_DBG("%s(%d) inst:[%d] phy clk is already off\n",
1374                                         __func__, __LINE__, phy->inst);
1375                 return 0;
1376         }
1377
1378         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1379                 utmip_powerdown_pmc_wake_detect(phy);
1380
1381                 val = readl(base + USB_SUSP_CTRL);
1382                 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
1383                 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
1384                 writel(val, base + USB_SUSP_CTRL);
1385
1386                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1387                 val |= UTMIP_PD_CHRG;
1388                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1389         } else {
1390                 phy->port_speed = (readl(base + HOSTPC1_DEVLC) >> 25) &
1391                                 HOSTPC1_DEVLC_PSPD_MASK;
1392
1393                 /* Disable interrupts */
1394                 writel(0, base + USB_USBINTR);
1395
1396                 /* Clear the run bit to stop SOFs when USB is suspended */
1397                 val = readl(base + USB_USBCMD);
1398                 val &= ~USB_USBCMD_RS;
1399                 writel(val, base + USB_USBCMD);
1400
1401                 if (usb_phy_reg_status_wait(base + USB_USBSTS, USB_USBSTS_HCH,
1402                                                  USB_USBSTS_HCH, 2000)) {
1403                         pr_err("%s: timeout waiting for USB_USBSTS_HCH\n"
1404                                                         , __func__);
1405                 }
1406                 utmip_setup_pmc_wake_detect(phy);
1407         }
1408
1409         if (!phy->hot_plug) {
1410                 val = readl(base + UTMIP_XCVR_CFG0);
1411                 val |= (UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
1412                          UTMIP_FORCE_PDZI_POWERDOWN);
1413                 writel(val, base + UTMIP_XCVR_CFG0);
1414         }
1415
1416         val = readl(base + UTMIP_XCVR_CFG1);
1417         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1418                    UTMIP_FORCE_PDDR_POWERDOWN;
1419         writel(val, base + UTMIP_XCVR_CFG1);
1420
1421         val = readl(base + UTMIP_BIAS_CFG1);
1422         val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
1423         writel(val, base + UTMIP_BIAS_CFG1);
1424
1425         if (phy->hot_plug) {
1426                 bool enable_hotplug = true;
1427                 /* if it is OTG port then make sure to enable hot-plug feature
1428                    only if host adaptor is connected, i.e id is low */
1429                 if (phy->pdata->port_otg) {
1430                         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1431                         enable_hotplug = (val & USB_ID_STATUS) ? false : true;
1432                 }
1433                 if (enable_hotplug) {
1434                         /* Enable wakeup event of device plug-in/plug-out */
1435                         val = readl(base + USB_PORTSC);
1436                         if (val & USB_PORTSC_CCS)
1437                                 val |= USB_PORTSC_WKDS;
1438                         else
1439                                 val |= USB_PORTSC_WKCN;
1440                         writel(val, base + USB_PORTSC);
1441
1442                         if (val & USB_PORTSC_CCS) {
1443                                 val = readl(base + USB_SUSP_CTRL);
1444                                 val &= ~USB_PHY_CLK_VALID_INT_ENB;
1445                         } else {
1446                                 val = readl(base + USB_SUSP_CTRL);
1447                                 val |= USB_PHY_CLK_VALID_INT_ENB;
1448                         }
1449                         writel(val, base + USB_SUSP_CTRL);
1450                 } else {
1451                         /* Disable PHY clock valid interrupts while going into suspend*/
1452                         val = readl(base + USB_SUSP_CTRL);
1453                         val &= ~USB_PHY_CLK_VALID_INT_ENB;
1454                         writel(val, base + USB_SUSP_CTRL);
1455                 }
1456         }
1457
1458         utmi_phy_pad_power_off(phy);
1459
1460         /* Disable PHY clock */
1461         val = readl(base + HOSTPC1_DEVLC);
1462         val |= HOSTPC1_DEVLC_PHCD;
1463         writel(val, base + HOSTPC1_DEVLC);
1464
1465         if (!phy->hot_plug) {
1466                 val = readl(base + USB_SUSP_CTRL);
1467                 val |= UTMIP_RESET;
1468                 writel(val, base + USB_SUSP_CTRL);
1469         }
1470
1471         phy->phy_clk_on = false;
1472         phy->hw_accessible = false;
1473
1474         PHY_DBG("%s(%d) inst:[%d] END\n", __func__, __LINE__, phy->inst);
1475
1476         return 0;
1477 }
1478
1479
1480 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
1481 {
1482         unsigned long val;
1483         void __iomem *base = phy->regs;
1484 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
1485         void __iomem *padctl_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
1486 #endif
1487         struct tegra_utmi_config *config = &phy->pdata->u_cfg.utmi;
1488
1489         PHY_DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1490         if (phy->phy_clk_on) {
1491                 PHY_DBG("%s(%d) inst:[%d] phy clk is already On\n",
1492                                         __func__, __LINE__, phy->inst);
1493                 return 0;
1494         }
1495         val = readl(base + USB_SUSP_CTRL);
1496         val |= UTMIP_RESET;
1497         writel(val, base + USB_SUSP_CTRL);
1498
1499         val = readl(base + UTMIP_TX_CFG0);
1500         val |= UTMIP_FS_PREABMLE_J;
1501         writel(val, base + UTMIP_TX_CFG0);
1502
1503         val = readl(base + USB_USBMODE);
1504         val &= ~USB_USBMODE_MASK;
1505         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST)
1506                 val |= USB_USBMODE_HOST;
1507         else
1508                 val |= USB_USBMODE_DEVICE;
1509         writel(val, base + USB_USBMODE);
1510
1511         val = readl(base + UTMIP_HSRX_CFG0);
1512         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
1513         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
1514         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
1515         writel(val, base + UTMIP_HSRX_CFG0);
1516
1517         val = readl(base + UTMIP_HSRX_CFG1);
1518         val &= ~UTMIP_HS_SYNC_START_DLY(~0);
1519         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
1520         writel(val, base + UTMIP_HSRX_CFG1);
1521
1522         val = readl(base + UTMIP_DEBOUNCE_CFG0);
1523         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
1524         val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
1525         writel(val, base + UTMIP_DEBOUNCE_CFG0);
1526
1527         val = readl(base + UTMIP_MISC_CFG0);
1528         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
1529         writel(val, base + UTMIP_MISC_CFG0);
1530
1531         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE) {
1532                 val = readl(base + USB_SUSP_CTRL);
1533                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
1534                 writel(val, base + USB_SUSP_CTRL);
1535
1536                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1537                 val &= ~UTMIP_PD_CHRG;
1538                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1539         } else {
1540                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
1541                 val |= UTMIP_PD_CHRG;
1542                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
1543         }
1544
1545         utmi_phy_pad_power_on(phy);
1546
1547         val = readl(base + UTMIP_XCVR_CFG0);
1548         val &= ~(UTMIP_XCVR_LSBIAS_SEL | UTMIP_FORCE_PD_POWERDOWN |
1549                  UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN |
1550                  UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_LSFSLEW(~0) |
1551                  UTMIP_XCVR_LSRSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
1552         val |= UTMIP_XCVR_SETUP(phy->utmi_xcvr_setup);
1553         val |= UTMIP_XCVR_SETUP_MSB(XCVR_SETUP_MSB_CALIB(phy->utmi_xcvr_setup));
1554         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
1555         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
1556         if (!config->xcvr_use_lsb)
1557                 val |= UTMIP_XCVR_HSSLEW_MSB(0x3);
1558         writel(val, base + UTMIP_XCVR_CFG0);
1559
1560         val = readl(base + UTMIP_XCVR_CFG1);
1561         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
1562                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
1563         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
1564         writel(val, base + UTMIP_XCVR_CFG1);
1565
1566         val = readl(base + UTMIP_BIAS_CFG1);
1567         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
1568         val |= UTMIP_BIAS_PDTRK_COUNT(phy->freq->pdtrk_count);
1569         writel(val, base + UTMIP_BIAS_CFG1);
1570
1571         val = readl(base + UTMIP_SPARE_CFG0);
1572         val &= ~FUSE_SETUP_SEL;
1573         val |= FUSE_ATERM_SEL;
1574         writel(val, base + UTMIP_SPARE_CFG0);
1575
1576         val = readl(base + USB_SUSP_CTRL);
1577         val |= UTMIP_PHY_ENABLE;
1578         writel(val, base + USB_SUSP_CTRL);
1579
1580         val = readl(base + USB_SUSP_CTRL);
1581         val &= ~UTMIP_RESET;
1582         writel(val, base + USB_SUSP_CTRL);
1583
1584         val = readl(base + HOSTPC1_DEVLC);
1585         val &= ~HOSTPC1_DEVLC_PHCD;
1586         writel(val, base + HOSTPC1_DEVLC);
1587
1588         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
1589                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500))
1590                 pr_warn("%s: timeout waiting for phy to stabilize\n", __func__);
1591
1592         utmi_phy_enable_trking_data(phy);
1593
1594         if (phy->inst == 2)
1595                 writel(0, base + ICUSB_CTRL);
1596
1597         val = readl(base + USB_USBMODE);
1598         val &= ~USB_USBMODE_MASK;
1599         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST)
1600                 val |= USB_USBMODE_HOST;
1601         else
1602                 val |= USB_USBMODE_DEVICE;
1603         writel(val, base + USB_USBMODE);
1604
1605         val = readl(base + HOSTPC1_DEVLC);
1606         val &= ~HOSTPC1_DEVLC_PTS(~0);
1607         val |= HOSTPC1_DEVLC_STS;
1608         writel(val, base + HOSTPC1_DEVLC);
1609
1610         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_DEVICE)
1611                 utmip_powerup_pmc_wake_detect(phy);
1612         phy->phy_clk_on = true;
1613         phy->hw_accessible = true;
1614
1615 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
1616         val = readl(padctl_base + PADCTL_SNPS_OC_MAP);
1617         val |= CONTROLLER_OC(phy->inst, 0x4);
1618         writel(val, padctl_base + PADCTL_SNPS_OC_MAP);
1619
1620         val = readl(padctl_base + PADCTL_OC_DET);
1621         if (phy->inst == 0)
1622                 val |= ENABLE0_OC_MAP(config->vbus_oc_map);
1623         if (phy->inst == 2)
1624                 val |= ENABLE1_OC_MAP(config->vbus_oc_map);
1625         writel(val, padctl_base + PADCTL_OC_DET);
1626 #endif
1627
1628         PHY_DBG("%s(%d) End inst:[%d]\n", __func__, __LINE__, phy->inst);
1629         return 0;
1630 }
1631
1632 static void utmi_phy_restore_start(struct tegra_usb_phy *phy)
1633 {
1634         unsigned long val;
1635         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1636         int inst = phy->inst;
1637
1638         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1639         val = readl(pmc_base + UTMIP_STATUS);
1640         /* Check whether we wake up from the remote resume.
1641            For lp1 case, pmc is not responsible for waking the
1642            system, it's the flow controller and hence
1643            UTMIP_WALK_PTR_VAL(inst) will return 0.
1644            Also, for lp1 case phy->pmc_remote_wakeup will already be set
1645            to true by utmi_phy_irq() when the remote wakeup happens.
1646            Hence change the logic in the else part to enter only
1647            if phy->pmc_remote_wakeup is not set to true by the
1648            utmi_phy_irq(). */
1649         if (UTMIP_WALK_PTR_VAL(inst) & val) {
1650                 phy->pmc_remote_wakeup = true;
1651         }
1652 }
1653
1654 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
1655 {
1656         unsigned long val, flags = 0;
1657         void __iomem *base = phy->regs;
1658         int wait_time_us = 25000; /* FPR should be set by this time */
1659
1660         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1661         /* check whether we wake up from the remote resume */
1662         if (phy->pmc_remote_wakeup) {
1663                 /* wait until SUSPEND and RESUME bit
1664                  * is cleared on remote resume */
1665                 do {
1666                         val = readl(base + USB_PORTSC);
1667                         udelay(1);
1668                         if (wait_time_us == 0) {
1669                                 PHY_DBG("%s PMC FPR" \
1670                                 "timeout val = 0x%lx instance = %d\n", \
1671                                 __func__, val, phy->inst);
1672                                 utmip_phy_disable_pmc_bus_ctrl(phy);
1673                                 return;
1674                         }
1675                         wait_time_us--;
1676                 } while (val & (USB_PORTSC_RESUME | USB_PORTSC_SUSP));
1677
1678                 local_irq_save(flags);
1679                 /* disable PMC master control */
1680                 utmip_phy_disable_pmc_bus_ctrl(phy);
1681
1682                 val = readl(base + USB_USBCMD);
1683                 val |= USB_USBCMD_RS;
1684                 writel(val, base + USB_USBCMD);
1685
1686                 local_irq_restore(flags);
1687
1688                 if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
1689                                                          USB_USBCMD_RS, 2000)) {
1690                         pr_err("%s: timeout waiting for USB_USBCMD_RS\n",\
1691                         __func__);
1692                 }
1693
1694                 /* Clear PCI and SRI bits to avoid an interrupt upon resume */
1695                 val = readl(base + USB_USBSTS);
1696                 writel(val, base + USB_USBSTS);
1697                 /* wait to avoid SOF if there is any */
1698                 if (usb_phy_reg_status_wait(base + USB_USBSTS,
1699                         USB_USBSTS_SRI, USB_USBSTS_SRI, 2500) < 0) {
1700                         pr_err("%s: timeout waiting for SOF\n", __func__);
1701                 }
1702         } else {
1703                 utmip_phy_disable_pmc_bus_ctrl(phy);
1704         }
1705 }
1706
1707 static int utmi_phy_resume(struct tegra_usb_phy *phy)
1708 {
1709         int status = 0;
1710         unsigned long val;
1711         void __iomem *base = phy->regs;
1712
1713         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1714         if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) {
1715                 if (readl(base + USB_ASYNCLISTADDR) &&
1716                         !phy->pdata->u_data.host.power_off_on_suspend)
1717                         return 0;
1718
1719                 if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
1720                         utmi_phy_restore_start(phy);
1721                         usb_phy_bringup_host_controller(phy);
1722                         utmi_phy_restore_end(phy);
1723                 } else {
1724                         utmip_phy_disable_pmc_bus_ctrl(phy);
1725
1726                         /* bring up the controller from suspend*/
1727                         val = readl(base + USB_USBCMD);
1728                         val |= USB_CMD_RESET;
1729                         writel(val, base + USB_USBCMD);
1730
1731                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1732                                 USB_CMD_RESET, 0, 2500) < 0) {
1733                                 pr_err("%s: timeout waiting for reset\n", __func__);
1734                         }
1735
1736                         val = readl(base + USB_USBMODE);
1737                         val &= ~USB_USBMODE_MASK;
1738                         val |= USB_USBMODE_HOST;
1739                         writel(val, base + USB_USBMODE);
1740
1741                         val = readl(base + HOSTPC1_DEVLC);
1742                         val &= ~HOSTPC1_DEVLC_PTS(~0);
1743                         val |= HOSTPC1_DEVLC_STS;
1744                         writel(val, base + HOSTPC1_DEVLC);
1745
1746                         writel(USB_USBCMD_RS, base + USB_USBCMD);
1747
1748                         if (usb_phy_reg_status_wait(base + USB_USBCMD,
1749                                 USB_USBCMD_RS, USB_USBCMD_RS, 2500) < 0) {
1750                                 pr_err("%s: timeout waiting for run bit\n", __func__);
1751                         }
1752
1753                         /* Enable Port Power */
1754                         val = readl(base + USB_PORTSC);
1755                         val |= USB_PORTSC_PP;
1756                         writel(val, base + USB_PORTSC);
1757                         udelay(10);
1758
1759                         DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n",
1760                         readl(base + USB_USBSTS), readl(base + USB_PORTSC));
1761                 }
1762         }
1763
1764         return status;
1765 }
1766
1767 static bool utmi_phy_charger_detect(struct tegra_usb_phy *phy)
1768 {
1769         unsigned long val;
1770         void __iomem *base = phy->regs;
1771         bool status;
1772
1773         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1774         if (phy->pdata->op_mode != TEGRA_USB_OPMODE_DEVICE) {
1775                 /* Charger detection is not there for ULPI
1776                  * return Charger not available */
1777                 return false;
1778         }
1779
1780         /* Enable charger detection logic */
1781         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1782         val |= UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN;
1783         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1784
1785         /* Source should be on for 100 ms as per USB charging spec */
1786         msleep(TDP_SRC_ON_MS);
1787
1788         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1789         /* If charger is not connected disable the interrupt */
1790         val &= ~VDAT_DET_INT_EN;
1791         val |= VDAT_DET_CHG_DET;
1792         writel(val, base + USB_PHY_VBUS_WAKEUP_ID);
1793
1794         val = readl(base + USB_PHY_VBUS_WAKEUP_ID);
1795         if (val & VDAT_DET_STS)
1796                 status = true;
1797         else
1798                 status = false;
1799
1800         /* Disable charger detection logic */
1801         val = readl(base + UTMIP_BAT_CHRG_CFG0);
1802         val &= ~(UTMIP_OP_SRC_EN | UTMIP_ON_SINK_EN);
1803         writel(val, base + UTMIP_BAT_CHRG_CFG0);
1804
1805         /* Delay of 40 ms before we pull the D+ as per battery charger spec */
1806         msleep(TDPSRC_CON_MS);
1807
1808         return status;
1809 }
1810
1811 static bool utmi_phy_nv_charger_detect(struct tegra_usb_phy *phy)
1812 {
1813         unsigned long val;
1814         void __iomem *base = phy->regs;
1815         bool status;
1816         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
1817
1818         /* Turn off all terminations so we see DPDN states clearly,
1819                 and only leave on DM pulldown */
1820         val = readl(base + UTMIP_MISC_CFG0);
1821         val &= ~MASK_ALL_PULLUP_PULLDOWN;
1822         val |= (DISABLE_PULLUP_DP | DISABLE_PULLUP_DM
1823                         | FORCE_PULLDN_DP | DISABLE_PULLDN_DM);
1824         writel(val, base + UTMIP_MISC_CFG0);
1825
1826         /*Wait for 20 ms to turn off terminations and stabilize line satus*/
1827         msleep(20);
1828
1829         val = readl(base + USB_PORTSC);
1830         status = (USB_PORTSC_LINE_STATE(val) == 0);
1831
1832         /* Turn off all terminations except for DP pullup */
1833         val = readl(base + UTMIP_MISC_CFG0);
1834         val &= ~MASK_ALL_PULLUP_PULLDOWN;
1835         val |= (FORCE_PULLUP_DP | DISABLE_PULLUP_DM
1836                         | DISABLE_PULLDN_DP | DISABLE_PULLDN_DM);
1837         writel(val, base + UTMIP_MISC_CFG0);
1838
1839         msleep(20);
1840
1841         val = readl(base + USB_PORTSC);
1842         if (status & (USB_PORTSC_LINE_STATE(val) == 0x3)) {
1843                 status = false;
1844         } else {
1845                 status = false;
1846
1847                 /* Check for NV charger DISABLE all terminations */
1848                 val = readl(base + UTMIP_MISC_CFG0);
1849                 val &= ~MASK_ALL_PULLUP_PULLDOWN;
1850                 val |= (DISABLE_PULLUP_DP | DISABLE_PULLUP_DM
1851                                 | DISABLE_PULLDN_DP | DISABLE_PULLDN_DM);
1852                 writel(val, base + UTMIP_MISC_CFG0);
1853
1854                 val = readl(base + USB_PORTSC);
1855                 if (USB_PORTSC_LINE_STATE(val) == 0x3)
1856                         status = true;
1857         }
1858
1859         /* Restore standard termination by hardware. */
1860         val = readl(base + UTMIP_MISC_CFG0);
1861         val &= ~MASK_ALL_PULLUP_PULLDOWN;
1862         writel(val, base + UTMIP_MISC_CFG0);
1863
1864         return status;
1865 }
1866
1867 static void uhsic_powerup_pmc_wake_detect(struct tegra_usb_phy *phy)
1868 {
1869         unsigned long val;
1870         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1871         unsigned int inst = phy->inst;
1872
1873         DBG("%s:%d\n", __func__, __LINE__);
1874
1875         /* turn on pad detectors for HSIC*/
1876         val = readl(pmc_base + PMC_USB_AO);
1877         val &= ~(HSIC_RESERVED(inst) | STROBE_VAL_PD(inst) | DATA_VAL_PD(inst));
1878         writel(val, pmc_base + PMC_USB_AO);
1879
1880         /* Disable PMC master mode by clearing MASTER_EN */
1881         val = readl(pmc_base + PMC_UHSIC_SLEEP_CFG(inst));
1882         val &= ~(UHSIC_MASTER_ENABLE(inst));
1883         writel(val, pmc_base + PMC_UHSIC_SLEEP_CFG(inst));
1884         mdelay(1);
1885 }
1886
1887 static void uhsic_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy)
1888 {
1889         unsigned long val;
1890         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1891         unsigned int inst = phy->inst;
1892
1893         DBG("%s:%d\n", __func__, __LINE__);
1894
1895         /* turn off pad detectors for HSIC*/
1896         val = readl(pmc_base + PMC_USB_AO);
1897         val |= (HSIC_RESERVED(inst) | STROBE_VAL_PD(inst) | DATA_VAL_PD(inst));
1898         writel(val, pmc_base + PMC_USB_AO);
1899
1900         /* enable pull downs on HSIC PMC */
1901         val = UHSIC_STROBE_RPD_A | UHSIC_DATA_RPD_A | UHSIC_STROBE_RPD_B |
1902                 UHSIC_DATA_RPD_B | UHSIC_STROBE_RPD_C | UHSIC_DATA_RPD_C |
1903                 UHSIC_STROBE_RPD_D | UHSIC_DATA_RPD_D;
1904         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC(inst));
1905
1906         /* Turn over pad configuration to PMC */
1907         val = readl(pmc_base + PMC_UHSIC_SLEEP_CFG(inst));
1908         val &= ~UHSIC_WAKE_VAL(inst, ~0);
1909         val |= UHSIC_WAKE_VAL(inst, WAKE_VAL_NONE) | UHSIC_MASTER_ENABLE(inst);
1910         writel(val, pmc_base + PMC_UHSIC_SLEEP_CFG(inst));
1911 }
1912
1913 static void uhsic_setup_pmc_wake_detect(struct tegra_usb_phy *phy)
1914 {
1915         unsigned long val;
1916         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
1917         void __iomem *base = phy->regs;
1918         bool port_connected;
1919         unsigned int inst = phy->inst;
1920
1921         DBG("%s:%d\n", __func__, __LINE__);
1922
1923         /* check for port connect status */
1924         val = readl(base + USB_PORTSC);
1925         port_connected = val & USB_PORTSC_CCS;
1926
1927         if (!port_connected)
1928                 return;
1929
1930         /*Set PMC MASTER bits to do the following
1931         * a. Take over the hsic drivers
1932         * b. set up such that it will take over resume
1933         *        if remote wakeup is detected
1934         * Prepare PMC to take over suspend-wake detect-drive resume until USB
1935         * controller ready
1936         */
1937
1938         /* disable master enable in PMC */
1939         val = readl(pmc_base + PMC_UHSIC_SLEEP_CFG(inst));
1940         val &= ~UHSIC_MASTER_ENABLE(inst);
1941         writel(val, pmc_base + PMC_UHSIC_SLEEP_CFG(inst));
1942
1943         /* UTMIP_PWR_PX=1 for power savings mode */
1944         val = readl(pmc_base + PMC_UHSIC_MASTER_CONFIG(inst));
1945         val |= UHSIC_PWR(inst);
1946         writel(val, pmc_base + PMC_UHSIC_MASTER_CONFIG(inst));
1947
1948         /* config debouncer */
1949         val = readl(pmc_base + PMC_USB_DEBOUNCE);
1950         val |= PMC_USB_DEBOUNCE_VAL(2);
1951         writel(val, pmc_base + PMC_USB_DEBOUNCE);
1952
1953         /* Make sure nothing is happening on the line with respect to PMC */
1954         val = readl(pmc_base + PMC_UHSIC_FAKE(inst));
1955         val &= ~UHSIC_FAKE_STROBE_VAL(inst);
1956         val &= ~UHSIC_FAKE_DATA_VAL(inst);
1957         writel(val, pmc_base + PMC_UHSIC_FAKE(inst));
1958
1959         /* Clear walk enable */
1960         val = readl(pmc_base + PMC_UHSIC_SLEEPWALK_CFG(inst));
1961         val &= ~UHSIC_LINEVAL_WALK_EN(inst);
1962         writel(val, pmc_base + PMC_UHSIC_SLEEPWALK_CFG(inst));
1963
1964         /* Make sure wake value for line is none */
1965         val = readl(pmc_base + PMC_UHSIC_SLEEP_CFG(inst));
1966         val &= ~UHSIC_WAKE_VAL(inst, WAKE_VAL_ANY);
1967         val |= UHSIC_WAKE_VAL(inst, WAKE_VAL_NONE);
1968         writel(val, pmc_base + PMC_UHSIC_SLEEP_CFG(inst));
1969
1970         /* turn on pad detectors */
1971         val = readl(pmc_base + PMC_USB_AO);
1972         val &= ~(STROBE_VAL_PD(inst) | DATA_VAL_PD(inst));
1973         writel(val, pmc_base + PMC_USB_AO);
1974
1975         /* Add small delay before usb detectors provide stable line values */
1976         udelay(1);
1977
1978         /* Enable which type of event can trigger a walk,
1979         * in this case usb_line_wake */
1980         val = readl(pmc_base + PMC_UHSIC_SLEEPWALK_CFG(inst));
1981         val |= UHSIC_LINEVAL_WALK_EN(inst);
1982         writel(val, pmc_base + PMC_UHSIC_SLEEPWALK_CFG(inst));
1983
1984         /* program walk sequence, maintain a J, followed by a driven K
1985         * to signal a resume once an wake event is detected */
1986
1987         val = readl(pmc_base + PMC_SLEEPWALK_UHSIC(inst));
1988
1989         val &= ~UHSIC_DATA_RPU_A;
1990         val |=  UHSIC_DATA_RPD_A;
1991         val &= ~UHSIC_STROBE_RPD_A;
1992         val |=  UHSIC_STROBE_RPU_A;
1993
1994         val &= ~UHSIC_DATA_RPD_B;
1995         val |=  UHSIC_DATA_RPU_B;
1996         val &= ~UHSIC_STROBE_RPU_B;
1997         val |=  UHSIC_STROBE_RPD_B;
1998
1999         val &= ~UHSIC_DATA_RPD_C;
2000         val |=  UHSIC_DATA_RPU_C;
2001         val &= ~UHSIC_STROBE_RPU_C;
2002         val |=  UHSIC_STROBE_RPD_C;
2003
2004         val &= ~UHSIC_DATA_RPD_D;
2005         val |=  UHSIC_DATA_RPU_D;
2006         val &= ~UHSIC_STROBE_RPU_D;
2007         val |=  UHSIC_STROBE_RPD_D;
2008         writel(val, pmc_base + PMC_SLEEPWALK_UHSIC(inst));
2009
2010         phy->pmc_remote_wakeup = false;
2011
2012         /* Setting Wake event*/
2013         val = readl(pmc_base + PMC_UHSIC_SLEEP_CFG(inst));
2014         val &= ~UHSIC_WAKE_VAL(inst, WAKE_VAL_ANY);
2015         val |= UHSIC_WAKE_VAL(inst, WAKE_VAL_SD10);
2016         writel(val, pmc_base + PMC_UHSIC_SLEEP_CFG(inst));
2017
2018         /* Clear the walk pointers and wake alarm */
2019         val = readl(pmc_base + PMC_UHSIC_TRIGGERS(inst));
2020         val |= UHSIC_CLR_WAKE_ALARM(inst) | UHSIC_CLR_WALK_PTR(inst);
2021         writel(val, pmc_base + PMC_UHSIC_TRIGGERS(inst));
2022
2023         /* Turn over pad configuration to PMC  for line wake events*/
2024         val = readl(pmc_base + PMC_UHSIC_SLEEP_CFG(inst));
2025         val |= UHSIC_MASTER_ENABLE(inst);
2026         writel(val, pmc_base + PMC_UHSIC_SLEEP_CFG(inst));
2027
2028         val = readl(base + UHSIC_PMC_WAKEUP0);
2029         val |= EVENT_INT_ENB;
2030         writel(val, base + UHSIC_PMC_WAKEUP0);
2031
2032         DBG("%s:PMC enabled for HSIC remote wakeup\n", __func__);
2033 }
2034
2035 static void uhsic_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy)
2036 {
2037         unsigned long val;
2038         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
2039         void __iomem *base = phy->regs;
2040         unsigned int inst = phy->inst;
2041
2042         DBG("%s (%d)\n", __func__, __LINE__);
2043         val = readl(pmc_base + PMC_UHSIC_SLEEP_CFG(inst));
2044         val &= ~UHSIC_WAKE_VAL(inst, WAKE_VAL_ANY);
2045         val |= UHSIC_WAKE_VAL(inst, WAKE_VAL_NONE);
2046         writel(val, pmc_base + PMC_UHSIC_SLEEP_CFG(inst));
2047
2048         val = readl(base + UHSIC_PMC_WAKEUP0);
2049         val &= ~EVENT_INT_ENB;
2050         writel(val, base + UHSIC_PMC_WAKEUP0);
2051
2052         /*
2053          * If pmc wakeup is detected after putting controller in suspend
2054          * in usb_phy_bringup_host_cotroller, restart bringing up host
2055          * controller as in case of only pmc wakeup.
2056          */
2057         if (phy->pmc_remote_wakeup && phy->ctrlr_suspended) {
2058                 usb_phy_bringup_host_controller(phy);
2059                 if (usb_phy_reg_status_wait(base + USB_PORTSC,
2060                         (USB_PORTSC_RESUME | USB_PORTSC_SUSP), 0,
2061                                 FPR_WAIT_TIME_US) < 0)
2062                         pr_err("%s: timeout waiting for SUSPEND to clear\n",
2063                                 __func__);
2064                 phy->ctrlr_suspended = false;
2065         }
2066
2067         /* Disable PMC master mode by clearing MASTER_EN */
2068         val = readl(pmc_base + PMC_UHSIC_SLEEP_CFG(inst));
2069         val &= ~(UHSIC_MASTER_ENABLE(inst));
2070         writel(val, pmc_base + PMC_UHSIC_SLEEP_CFG(inst));
2071
2072         /* turn off pad detectors */
2073         val = readl(pmc_base + PMC_USB_AO);
2074         val |= (STROBE_VAL_PD(inst) | DATA_VAL_PD(inst));
2075         writel(val, pmc_base + PMC_USB_AO);
2076
2077         val = readl(pmc_base + PMC_UHSIC_TRIGGERS(inst));
2078         val |= (UHSIC_CLR_WALK_PTR(inst) | UHSIC_CLR_WAKE_ALARM(inst));
2079         writel(val, pmc_base + PMC_UHSIC_TRIGGERS(inst));
2080
2081         phy->pmc_remote_wakeup = false;
2082 }
2083
2084 static bool uhsic_phy_remotewake_detected(struct tegra_usb_phy *phy)
2085 {
2086         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
2087         void __iomem *base = phy->regs;
2088         u32 val;
2089         unsigned int inst = phy->inst;
2090
2091         val = readl(base + UHSIC_PMC_WAKEUP0);
2092         if (!(val & EVENT_INT_ENB))
2093                 return false;
2094         val = readl(pmc_base + UHSIC_STATUS(inst));
2095         if (!(UHSIC_WAKE_ALARM(inst) & val))
2096                 return false;
2097         val = readl(pmc_base + PMC_UHSIC_SLEEP_CFG(inst));
2098         val &= ~UHSIC_WAKE_VAL(inst, WAKE_VAL_ANY);
2099         val |= UHSIC_WAKE_VAL(inst, WAKE_VAL_NONE);
2100         writel(val, pmc_base + PMC_UHSIC_SLEEP_CFG(inst));
2101
2102         val = readl(pmc_base + PMC_UHSIC_TRIGGERS(inst));
2103         val |= UHSIC_CLR_WAKE_ALARM(inst);
2104         writel(val, pmc_base + PMC_UHSIC_TRIGGERS(inst));
2105
2106         val = readl(base + UHSIC_PMC_WAKEUP0);
2107         val &= ~EVENT_INT_ENB;
2108         writel(val, base + UHSIC_PMC_WAKEUP0);
2109         phy->pmc_remote_wakeup = true;
2110         DBG("%s:PMC remote wakeup detected for HSIC\n", __func__);
2111         return true;
2112 }
2113
2114 static int uhsic_phy_pre_resume(struct tegra_usb_phy *phy, bool remote_wakeup)
2115 {
2116         unsigned long val;
2117         void __iomem *base = phy->regs;
2118
2119         if (remote_wakeup) {
2120                 /* Set RUN bit */
2121                 val = readl(base + USB_USBCMD);
2122                 val |= USB_USBCMD_RS;
2123                 writel(val, base + USB_USBCMD);
2124         }
2125
2126         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2127
2128         return 0;
2129 }
2130
2131 static void uhsic_phy_restore_start(struct tegra_usb_phy *phy)
2132 {
2133         unsigned long val;
2134         void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
2135         void __iomem *base = phy->regs;
2136         unsigned int inst = phy->inst;
2137
2138         val = readl(pmc_base + UHSIC_STATUS(inst));
2139
2140         /* check whether we wake up from the remote resume */
2141         if (UHSIC_WALK_PTR_VAL(inst) & val) {
2142                 phy->pmc_remote_wakeup = true;
2143                 DBG("%s: uhsic remote wakeup detected\n", __func__);
2144         } else {
2145                 if (!((UHSIC_STROBE_VAL(inst) | UHSIC_DATA_VAL(inst)) & val)) {
2146                                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2147                 } else {
2148                         DBG("%s(%d): setting pretend connect\n", __func__, __LINE__);
2149                         val = readl(base + UHSIC_CMD_CFG0);
2150                         val |= UHSIC_PRETEND_CONNECT_DETECT;
2151                         writel(val, base + UHSIC_CMD_CFG0);
2152                 }
2153         }
2154 }
2155
2156 static void uhsic_phy_restore_end(struct tegra_usb_phy *phy)
2157 {
2158
2159         unsigned long val, flags = 0;
2160         void __iomem *base = phy->regs;
2161         int wait_time_us = FPR_WAIT_TIME_US; /* FPR should be set by this time */
2162         bool irq_disabled = false;
2163
2164         DBG("%s(%d)\n", __func__, __LINE__);
2165
2166         /*
2167          * check whether we wake up from the remote wake detected before putting
2168          * controller in suspend in usb_phy_bringup_host_controller.
2169          */
2170         if (!phy->ctrlr_suspended) {
2171                 /* wait until FPR bit is set automatically on remote resume */
2172                 do {
2173                         val = readl(base + USB_PORTSC);
2174                         udelay(1);
2175                         if (wait_time_us == 0) {
2176                                 uhsic_phy_disable_pmc_bus_ctrl(phy);
2177                                 return;
2178                         }
2179                         wait_time_us--;
2180                 } while (val & (USB_PORTSC_RESUME | USB_PORTSC_SUSP));
2181                 /* In case of remote wakeup, disable local irq to prevent
2182                  * context switch b/t disable PMC and set RUN bit ops */
2183                 local_irq_save(flags);
2184                 irq_disabled = true;
2185         }
2186         /* disable PMC master control */
2187         uhsic_phy_disable_pmc_bus_ctrl(phy);
2188
2189         /* Set RUN bit */
2190         val = readl(base + USB_USBCMD);
2191         val |= USB_USBCMD_RS;
2192         writel(val, base + USB_USBCMD);
2193         /* Restore local irq if disabled before */
2194         if (irq_disabled)
2195                 local_irq_restore(flags);
2196         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
2197                                                  USB_USBCMD_RS, 2000)) {
2198                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
2199                 return;
2200         }
2201 }
2202
2203 static int uhsic_rail_enable(struct tegra_usb_phy *phy)
2204 {
2205         int ret;
2206
2207         if (phy->hsic_reg == NULL) {
2208                 phy->hsic_reg = regulator_get(&phy->pdev->dev, "vddio_hsic");
2209                 if (IS_ERR_OR_NULL(phy->hsic_reg)) {
2210                         pr_err("UHSIC: Could not get regulator vddio_hsic\n");
2211                         ret = PTR_ERR(phy->hsic_reg);
2212                         phy->hsic_reg = NULL;
2213                         return ret;
2214                 }
2215         }
2216
2217         ret = regulator_enable(phy->hsic_reg);
2218         if (ret < 0) {
2219                 pr_err("%s vddio_hsic could not be enabled\n", __func__);
2220                 return ret;
2221         }
2222
2223         return 0;
2224 }
2225
2226 static int uhsic_rail_disable(struct tegra_usb_phy *phy)
2227 {
2228         int ret;
2229
2230         if (phy->hsic_reg == NULL) {
2231                 pr_warn("%s: unbalanced disable\n", __func__);
2232                 return -EIO;
2233         }
2234
2235         ret = regulator_disable(phy->hsic_reg);
2236         if (ret < 0) {
2237                 pr_err("HSIC regulator vddio_hsic cannot be disabled\n");
2238                 return ret;
2239         }
2240         regulator_put(phy->hsic_reg);
2241         phy->hsic_reg = NULL;
2242         return 0;
2243 }
2244
2245 static int uhsic_phy_open(struct tegra_usb_phy *phy)
2246 {
2247         unsigned long parent_rate;
2248         int i;
2249         int ret;
2250
2251         phy->hsic_reg = NULL;
2252         ret = uhsic_rail_enable(phy);
2253         if (ret < 0) {
2254                 pr_err("%s vddio_hsic could not be enabled\n", __func__);
2255                 return ret;
2256         }
2257
2258         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2259         parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk));
2260         for (i = 0; i < ARRAY_SIZE(uhsic_freq_table); i++) {
2261                 if (uhsic_freq_table[i].freq == parent_rate) {
2262                         phy->freq = &uhsic_freq_table[i];
2263                         break;
2264                 }
2265         }
2266         if (!phy->freq) {
2267                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
2268                 return -EINVAL;
2269         }
2270
2271         uhsic_powerup_pmc_wake_detect(phy);
2272
2273         return 0;
2274 }
2275
2276 static void uhsic_phy_close(struct tegra_usb_phy *phy)
2277 {
2278         int ret;
2279
2280         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2281         uhsic_powerdown_pmc_wake_detect(phy);
2282
2283         ret = uhsic_rail_disable(phy);
2284         if (ret < 0)
2285                 pr_err("%s vddio_hsic could not be disabled\n", __func__);
2286 }
2287
2288 static int uhsic_phy_irq(struct tegra_usb_phy *phy)
2289 {
2290         /* check if there is any remote wake event */
2291         usb_phy_fence_read(phy);
2292         if (uhsic_phy_remotewake_detected(phy))
2293                 DBG("%s: uhsic remote wake detected\n", __func__);
2294         return IRQ_HANDLED;
2295 }
2296
2297 static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
2298 {
2299         unsigned long val;
2300         void __iomem *base = phy->regs;
2301 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
2302         void __iomem *padctl_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
2303 #endif
2304
2305         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2306
2307         if (phy->phy_clk_on) {
2308                 DBG("%s(%d) inst:[%d] phy clk is already On\n",
2309                                         __func__, __LINE__, phy->inst);
2310                 return 0;
2311         }
2312
2313 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
2314         val = readl(padctl_base + PADCTL_SNPS_OC_MAP);
2315         val |= CONTROLLER_OC(phy->inst, 0x7);
2316         writel(val, padctl_base + PADCTL_SNPS_OC_MAP);
2317 #endif
2318
2319         val = readl(base + UHSIC_PADS_CFG1);
2320         val &= ~(UHSIC_PD_BG | UHSIC_PD_RX |
2321                         UHSIC_PD_ZI | UHSIC_RPD_DATA | UHSIC_RPD_STROBE);
2322         writel(val, base + UHSIC_PADS_CFG1);
2323
2324         val |= (UHSIC_RX_SEL | UHSIC_PD_TX);
2325         writel(val, base + UHSIC_PADS_CFG1);
2326
2327         val = readl(base + USB_SUSP_CTRL);
2328         val |= UHSIC_RESET;
2329         writel(val, base + USB_SUSP_CTRL);
2330         udelay(1);
2331
2332         val = readl(base + USB_SUSP_CTRL);
2333         val |= UHSIC_PHY_ENABLE;
2334         writel(val, base + USB_SUSP_CTRL);
2335
2336         val = readl(base + UHSIC_HSRX_CFG0);
2337         val |= UHSIC_IDLE_WAIT(HSIC_IDLE_WAIT_DELAY);
2338         val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(HSIC_ELASTIC_UNDERRUN_LIMIT);
2339         val |= UHSIC_ELASTIC_OVERRUN_LIMIT(HSIC_ELASTIC_OVERRUN_LIMIT);
2340         writel(val, base + UHSIC_HSRX_CFG0);
2341
2342         val = readl(base + UHSIC_HSRX_CFG1);
2343         val |= UHSIC_HS_SYNC_START_DLY(HSIC_SYNC_START_DELAY);
2344         writel(val, base + UHSIC_HSRX_CFG1);
2345
2346         /* WAR HSIC TX */
2347         val = readl(base + UHSIC_TX_CFG0);
2348         val &= ~UHSIC_HS_READY_WAIT_FOR_VALID;
2349         writel(val, base + UHSIC_TX_CFG0);
2350
2351         val = readl(base + UHSIC_MISC_CFG0);
2352         val |= UHSIC_SUSPEND_EXIT_ON_EDGE;
2353         writel(val, base + UHSIC_MISC_CFG0);
2354
2355         val = readl(base + UHSIC_MISC_CFG1);
2356         val |= UHSIC_PLLU_STABLE_COUNT(phy->freq->stable_count);
2357         writel(val, base + UHSIC_MISC_CFG1);
2358
2359         val = readl(base + UHSIC_PLL_CFG1);
2360         val |= UHSIC_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
2361         val |= UHSIC_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count);
2362         writel(val, base + UHSIC_PLL_CFG1);
2363
2364         val = readl(base + USB_SUSP_CTRL);
2365         val &= ~(UHSIC_RESET);
2366         writel(val, base + USB_SUSP_CTRL);
2367         udelay(1);
2368
2369         val = readl(base + UHSIC_PADS_CFG1);
2370         val &= ~(UHSIC_PD_TX);
2371         writel(val, base + UHSIC_PADS_CFG1);
2372
2373         /* HSIC pad tracking circuit power down sequence */
2374         val = readl(base + UHSIC_PADS_CFG1);
2375         val &= ~(UHSIC_PD_TRK);
2376         writel(val, base + UHSIC_PADS_CFG1);
2377         /* Wait for 25usec */
2378         udelay(25);
2379         val |= UHSIC_PD_TRK;
2380         writel(val, base + UHSIC_PADS_CFG1);
2381
2382         /*SUSP_CTRL has to be toggled to enable host PHY clock */
2383         val = readl(base + USB_SUSP_CTRL);
2384         val |= USB_SUSP_CLR;
2385         writel(val, base + USB_SUSP_CTRL);
2386
2387         val = readl(base + USB_SUSP_CTRL);
2388         val &= ~USB_SUSP_CLR;
2389         writel(val, base + USB_SUSP_CTRL);
2390
2391         val = readl(base + USB_USBMODE);
2392         val |= USB_USBMODE_HOST;
2393         writel(val, base + USB_USBMODE);
2394
2395         /* Change the USB controller PHY type to HSIC */
2396         val = readl(base + HOSTPC1_DEVLC);
2397         val &= ~HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK);
2398         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2399         val &= ~HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK);
2400         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2401         val &= ~HOSTPC1_DEVLC_STS;
2402         writel(val, base + HOSTPC1_DEVLC);
2403
2404         val = readl(base + USB_PORTSC);
2405         val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN);
2406         writel(val, base + USB_PORTSC);
2407
2408         val = readl(base + UHSIC_PADS_CFG0);
2409         /* Clear RTUNEN, SLEWP & SLEWN bit fields */
2410         val &= ~(UHSIC_TX_RTUNEN | UHSIC_TX_SLEWP | UHSIC_TX_SLEWN);
2411         /* set Rtune impedance to 50 ohm */
2412         val |= UHSIC_TX_RTUNE(0xC);
2413         writel(val, base + UHSIC_PADS_CFG0);
2414
2415         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
2416                                 USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500)) {
2417                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2418                 return -ETIMEDOUT;
2419         }
2420
2421         phy->phy_clk_on = true;
2422         phy->hw_accessible = true;
2423
2424         if (phy->pmc_sleepwalk) {
2425                 DBG("%s(%d) inst:[%d] restore phy\n", __func__, __LINE__,
2426                                         phy->inst);
2427                 uhsic_phy_restore_start(phy);
2428                 usb_phy_bringup_host_controller(phy);
2429                 uhsic_phy_restore_end(phy);
2430                 phy->pmc_sleepwalk = false;
2431         }
2432
2433         val = readl(base + USB_TXFILLTUNING);
2434         if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
2435                 val = USB_FIFO_TXFILL_THRES(0x10);
2436                 writel(val, base + USB_TXFILLTUNING);
2437         }
2438
2439         return 0;
2440 }
2441
2442 static int uhsic_phy_power_off(struct tegra_usb_phy *phy)
2443 {
2444         unsigned long val;
2445         void __iomem *base = phy->regs;
2446
2447         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2448         if (!phy->phy_clk_on) {
2449                 DBG("%s(%d) inst:[%d] phy clk is already off\n",
2450                                         __func__, __LINE__, phy->inst);
2451                 return 0;
2452         }
2453
2454         /* Disable interrupts */
2455         writel(0, base + USB_USBINTR);
2456
2457         if (phy->pmc_sleepwalk == false) {
2458                 uhsic_setup_pmc_wake_detect(phy);
2459                 phy->pmc_sleepwalk = true;
2460         }
2461
2462         val = readl(base + HOSTPC1_DEVLC);
2463         val |= HOSTPC1_DEVLC_PHCD;
2464         writel(val, base + HOSTPC1_DEVLC);
2465
2466         /* Remove power downs for HSIC from PADS CFG1 register */
2467         val = readl(base + UHSIC_PADS_CFG1);
2468         val |= (UHSIC_PD_BG | UHSIC_PD_TRK |
2469                         UHSIC_PD_ZI | UHSIC_PD_TX);
2470         writel(val, base + UHSIC_PADS_CFG1);
2471
2472         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL,
2473                 USB_PHY_CLK_VALID, 0, 2500))
2474                 pr_warn("%s: timeout waiting for phy to disable\n", __func__);
2475
2476         DBG("%s(%d) inst:[%d] End\n", __func__, __LINE__, phy->inst);
2477
2478         phy->phy_clk_on = false;
2479         phy->hw_accessible = false;
2480
2481         return 0;
2482 }
2483
2484 static int uhsic_phy_bus_port_power(struct tegra_usb_phy *phy)
2485 {
2486         unsigned long val;
2487         void __iomem *base = phy->regs;
2488
2489         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2490
2491         val = readl(base + USB_USBMODE);
2492         val |= USB_USBMODE_HOST;
2493         writel(val, base + USB_USBMODE);
2494
2495         /* Change the USB controller PHY type to HSIC */
2496         val = readl(base + HOSTPC1_DEVLC);
2497         val &= ~(HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_MASK));
2498         val |= HOSTPC1_DEVLC_PTS(HOSTPC1_DEVLC_PTS_HSIC);
2499         val &= ~(HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_MASK));
2500         val |= HOSTPC1_DEVLC_PSPD(HOSTPC1_DEVLC_PSPD_HIGH_SPEED);
2501         writel(val, base + HOSTPC1_DEVLC);
2502
2503         val = readl(base + UHSIC_MISC_CFG0);
2504         val |= UHSIC_DETECT_SHORT_CONNECT;
2505         writel(val, base + UHSIC_MISC_CFG0);
2506         udelay(1);
2507         if (phy->pdata->ops && phy->pdata->ops->port_power)
2508                 phy->pdata->ops->port_power();
2509
2510         return 0;
2511 }
2512
2513 static void ulpi_set_trimmer(struct tegra_usb_phy *phy)
2514 {
2515         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2516         void __iomem *base = phy->regs;
2517         unsigned long val;
2518
2519         val = ULPI_DATA_TRIMMER_SEL(config->data_trimmer);
2520         val |= ULPI_STPDIRNXT_TRIMMER_SEL(config->stpdirnxt_trimmer);
2521         val |= ULPI_DIR_TRIMMER_SEL(config->dir_trimmer);
2522         writel(val, base + ULPI_TIMING_CTRL_1);
2523         udelay(10);
2524
2525         val |= ULPI_DATA_TRIMMER_LOAD;
2526         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
2527         val |= ULPI_DIR_TRIMMER_LOAD;
2528         writel(val, base + ULPI_TIMING_CTRL_1);
2529 }
2530
2531 static int ulpi_link_phy_open(struct tegra_usb_phy *phy)
2532 {
2533 #if defined(CONFIG_TEGRA_SILICON_PLATFORM)
2534         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2535 #endif
2536         int err = 0;
2537
2538         phy->ulpi_clk = NULL;
2539         DBG("%s inst:[%d]\n", __func__, phy->inst);
2540
2541 #if defined(CONFIG_TEGRA_SILICON_PLATFORM)
2542         if (config->clk) {
2543                 phy->ulpi_clk = clk_get_sys(NULL, config->clk);
2544                 if (IS_ERR(phy->ulpi_clk)) {
2545                         pr_err("%s: can't get ulpi clock\n", __func__);
2546                         err = -ENXIO;
2547                 }
2548         }
2549 #endif
2550         phy->ulpi_vp = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
2551         phy->ulpi_vp->io_priv = phy->regs + ULPI_VIEWPORT;
2552
2553         return err;
2554 }
2555
2556 static void ulpi_link_phy_close(struct tegra_usb_phy *phy)
2557 {
2558         DBG("%s inst:[%d]\n", __func__, phy->inst);
2559         if (phy->ulpi_clk)
2560                 clk_put(phy->ulpi_clk);
2561 }
2562
2563 static int ulpi_link_phy_irq(struct tegra_usb_phy *phy)
2564 {
2565         DBG("%s inst:[%d]\n", __func__, phy->inst);
2566         return IRQ_HANDLED;
2567 }
2568
2569 static int ulpi_link_phy_power_off(struct tegra_usb_phy *phy)
2570 {
2571         unsigned long val;
2572         void __iomem *base = phy->regs;
2573         int ret;
2574
2575         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2576         if (!phy->phy_clk_on) {
2577                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
2578                                                         __LINE__, phy->inst);
2579                 return 0;
2580         }
2581
2582         /* Disable VbusValid, SessEnd comparators */
2583         ret = usb_phy_io_write(phy->ulpi_vp, 0x00, 0x0D);
2584         if (ret)
2585                 pr_err("%s: ulpi write 0x0D failed\n", __func__);
2586
2587         ret = usb_phy_io_write(phy->ulpi_vp, 0x00, 0x10);
2588         if (ret)
2589                 pr_err("%s: ulpi write 0x10 failed\n", __func__);
2590
2591         /* Disable IdFloat comparator */
2592         ret = usb_phy_io_write(phy->ulpi_vp, 0x00, 0x19);
2593         if (ret)
2594                 pr_err("%s: ulpi write 0x19 failed\n", __func__);
2595
2596         ret = usb_phy_io_write(phy->ulpi_vp, 0x00, 0x1D);
2597         if (ret)
2598                 pr_err("%s: ulpi write 0x1D failed\n", __func__);
2599
2600         phy->port_speed = (readl(base + USB_PORTSC) >> 26) &
2601                         USB_PORTSC_PSPD_MASK;
2602
2603         /* Clear WKCN/WKDS/WKOC wake-on events that can cause the USB
2604          * Controller to immediately bring the ULPI PHY out of low power
2605          */
2606         val = readl(base + USB_PORTSC);
2607         val &= ~(USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN);
2608         writel(val, base + USB_PORTSC);
2609
2610         /* Put the PHY in the low power mode */
2611         val = readl(base + USB_PORTSC);
2612         val |= USB_PORTSC_PHCD;
2613         writel(val, base + USB_PORTSC);
2614
2615         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
2616                                                          0, 2500)) {
2617                 pr_err("%s: timeout waiting for phy to stop\n", __func__);
2618         }
2619
2620         if (phy->ulpi_clk)
2621                 clk_disable(phy->ulpi_clk);
2622
2623         phy->phy_clk_on = false;
2624         phy->hw_accessible = false;
2625
2626         return 0;
2627 }
2628
2629 static int ulpi_link_phy_power_on(struct tegra_usb_phy *phy)
2630 {
2631         int ret;
2632         unsigned long val;
2633         void __iomem *base = phy->regs;
2634
2635         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2636         if (phy->phy_clk_on) {
2637                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
2638                                                         __LINE__, phy->inst);
2639                 return 0;
2640         }
2641
2642         if (phy->ulpi_clk) {
2643                 clk_enable(phy->ulpi_clk);
2644                 mdelay(1);
2645         }
2646
2647         val = readl(base + USB_SUSP_CTRL);
2648         val |= UHSIC_RESET;
2649         writel(val, base + USB_SUSP_CTRL);
2650
2651         val = readl(base + ULPI_TIMING_CTRL_0);
2652         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
2653         writel(val, base + ULPI_TIMING_CTRL_0);
2654
2655         val = readl(base + USB_SUSP_CTRL);
2656         val |= ULPI_PHY_ENABLE;
2657         writel(val, base + USB_SUSP_CTRL);
2658
2659         val = readl(base + USB_SUSP_CTRL);
2660         val |= USB_SUSP_CLR;
2661         writel(val, base + USB_SUSP_CTRL);
2662
2663         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
2664                                                 USB_PHY_CLK_VALID, 2500))
2665                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
2666
2667         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_CLKEN,
2668                                                 USB_CLKEN, 2500))
2669                 pr_err("%s: timeout waiting for AHB clock\n", __func__);
2670
2671         val = readl(base + USB_SUSP_CTRL);
2672         val &= ~USB_SUSP_CLR;
2673         writel(val, base + USB_SUSP_CTRL);
2674
2675         val = 0;
2676         writel(val, base + ULPI_TIMING_CTRL_1);
2677
2678         ulpi_set_trimmer(phy);
2679
2680         /* Fix VbusInvalid due to floating VBUS */
2681         ret = usb_phy_io_write(phy->ulpi_vp, 0x40, 0x08);
2682         if (ret) {
2683                 pr_err("%s: ulpi write failed\n", __func__);
2684                 return ret;
2685         }
2686
2687         ret = usb_phy_io_write(phy->ulpi_vp, 0x80, 0x0B);
2688         if (ret) {
2689                 pr_err("%s: ulpi write failed\n", __func__);
2690                 return ret;
2691         }
2692
2693         val = readl(base + USB_PORTSC);
2694         val |= USB_PORTSC_WKOC | USB_PORTSC_WKDS | USB_PORTSC_WKCN;
2695         writel(val, base + USB_PORTSC);
2696
2697         phy->phy_clk_on = true;
2698         phy->hw_accessible = true;
2699
2700         return 0;
2701 }
2702
2703 static inline void ulpi_link_phy_set_tristate(bool enable)
2704 {
2705
2706 }
2707
2708 static void ulpi_link_phy_restore_start(struct tegra_usb_phy *phy)
2709 {
2710         unsigned long val;
2711         void __iomem *base = phy->regs;
2712
2713         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2714
2715         /*Tristate ulpi interface before USB controller resume*/
2716         ulpi_link_phy_set_tristate(true);
2717
2718         val = readl(base + ULPI_TIMING_CTRL_0);
2719         val &= ~ULPI_OUTPUT_PINMUX_BYP;
2720         writel(val, base + ULPI_TIMING_CTRL_0);
2721 }
2722
2723 static void ulpi_link_phy_restore_end(struct tegra_usb_phy *phy)
2724 {
2725         unsigned long val;
2726         void __iomem *base = phy->regs;
2727
2728         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2729
2730         val = readl(base + ULPI_TIMING_CTRL_0);
2731         val |= ULPI_OUTPUT_PINMUX_BYP;
2732         writel(val, base + ULPI_TIMING_CTRL_0);
2733
2734         ulpi_link_phy_set_tristate(false);
2735 }
2736
2737 static int ulpi_link_phy_resume(struct tegra_usb_phy *phy)
2738 {
2739         int status = 0;
2740
2741         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2742         if (phy->pdata->u_data.host.power_off_on_suspend) {
2743                 status = ulpi_link_phy_power_on(phy);
2744                 if (phy->port_speed < USB_PHY_PORT_SPEED_UNKNOWN) {
2745                         ulpi_link_phy_restore_start(phy);
2746                         usb_phy_bringup_host_controller(phy);
2747                         ulpi_link_phy_restore_end(phy);
2748                 }
2749         }
2750
2751         return status;
2752 }
2753
2754 static void reset_utmip_uhsic(void __iomem *base)
2755 {
2756         unsigned long val;
2757
2758         val = readl(base + USB_SUSP_CTRL);
2759         val |= UHSIC_RESET;
2760         writel(val, base + USB_SUSP_CTRL);
2761
2762         val = readl(base + USB_SUSP_CTRL);
2763         val |= UTMIP_RESET;
2764         writel(val, base + USB_SUSP_CTRL);
2765 }
2766
2767 static void ulpi_set_host(void __iomem *base)
2768 {
2769         unsigned long val;
2770
2771         val = readl(base + USB_USBMODE);
2772         val &= ~USB_USBMODE_MASK;
2773         val |= USB_USBMODE_HOST;
2774         writel(val, base + USB_USBMODE);
2775
2776         val = readl(base + HOSTPC1_DEVLC);
2777         val |= HOSTPC1_DEVLC_PTS(2);
2778         writel(val, base + HOSTPC1_DEVLC);
2779 }
2780
2781 static inline void ulpi_pinmux_bypass(struct tegra_usb_phy *phy, bool enable)
2782 {
2783         unsigned long val;
2784         void __iomem *base = phy->regs;
2785
2786         val = readl(base + ULPI_TIMING_CTRL_0);
2787
2788         if (enable)
2789                 val |= ULPI_OUTPUT_PINMUX_BYP;
2790         else
2791                 val &= ~ULPI_OUTPUT_PINMUX_BYP;
2792
2793         writel(val, base + ULPI_TIMING_CTRL_0);
2794 }
2795
2796 static inline void ulpi_null_phy_set_tristate(bool enable)
2797 {
2798 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2799         int tristate = (enable) ? TEGRA_TRI_TRISTATE : TEGRA_TRI_NORMAL;
2800         DBG("%s(%d) inst:[%s] FIXME enable pin group +++\n", __func__,
2801                                 __LINE__, enable ? "TRISTATE" : "NORMAL");
2802
2803         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA0, tristate);
2804         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA1, tristate);
2805         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA2, tristate);
2806         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA3, tristate);
2807         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA4, tristate);
2808         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA5, tristate);
2809         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA6, tristate);
2810         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DATA7, tristate);
2811         tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_NXT, tristate);
2812
2813         if (enable)
2814                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR, tristate);
2815 #endif
2816 }
2817
2818 static void ulpi_null_phy_obs_read(void)
2819 {
2820         static void __iomem *apb_misc;
2821         unsigned slv0_obs, s2s_obs;
2822
2823         if (!apb_misc)
2824                 apb_misc = ioremap(TEGRA_APB_MISC_BASE, TEGRA_APB_MISC_SIZE);
2825
2826         writel(0x80d1003c, apb_misc + APB_MISC_GP_OBSCTRL_0);
2827         slv0_obs = readl(apb_misc + APB_MISC_GP_OBSDATA_0);
2828
2829         writel(0x80d10040, apb_misc + APB_MISC_GP_OBSCTRL_0);
2830         s2s_obs = readl(apb_misc + APB_MISC_GP_OBSDATA_0);
2831
2832         pr_debug("slv0 obs: %08x\ns2s obs: %08x\n", slv0_obs, s2s_obs);
2833 }
2834
2835 static const struct gpio ulpi_gpios[] = {
2836         {ULPI_STP, GPIOF_IN, "ULPI_STP"},
2837         {ULPI_DIR, GPIOF_OUT_INIT_LOW, "ULPI_DIR"},
2838         {ULPI_D0, GPIOF_OUT_INIT_LOW, "ULPI_D0"},
2839         {ULPI_D1, GPIOF_OUT_INIT_LOW, "ULPI_D1"},
2840 };
2841
2842 static int ulpi_null_phy_open(struct tegra_usb_phy *phy)
2843 {
2844         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2845         int ret;
2846
2847         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2848
2849         ret = gpio_request_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
2850         if (ret)
2851                 return ret;
2852
2853         if (gpio_is_valid(config->phy_restore_gpio)) {
2854                 ret = gpio_request(config->phy_restore_gpio, "phy_restore");
2855                 if (ret)
2856                         goto err_gpio_free;
2857
2858                 gpio_direction_input(config->phy_restore_gpio);
2859         }
2860
2861         tegra_periph_reset_assert(phy->ctrlr_clk);
2862         udelay(10);
2863         tegra_periph_reset_deassert(phy->ctrlr_clk);
2864
2865         return 0;
2866
2867 err_gpio_free:
2868         gpio_free_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
2869         return ret;
2870 }
2871
2872 static void ulpi_null_phy_close(struct tegra_usb_phy *phy)
2873 {
2874         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2875
2876         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2877
2878         if (gpio_is_valid(config->phy_restore_gpio))
2879                 gpio_free(config->phy_restore_gpio);
2880
2881         gpio_free_array(ulpi_gpios, ARRAY_SIZE(ulpi_gpios));
2882 }
2883
2884 static int ulpi_null_phy_power_off(struct tegra_usb_phy *phy)
2885 {
2886         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2887
2888         if (!phy->phy_clk_on) {
2889                 DBG("%s(%d) inst:[%d] phy clk is already off\n", __func__,
2890                                                         __LINE__, phy->inst);
2891                 return 0;
2892         }
2893
2894         phy->phy_clk_on = false;
2895         phy->hw_accessible = false;
2896         ulpi_null_phy_set_tristate(true);
2897         return 0;
2898 }
2899
2900 /* NOTE: this function must be called before ehci reset */
2901 static int ulpi_null_phy_init(struct tegra_usb_phy *phy)
2902 {
2903         unsigned long val;
2904         void __iomem *base = phy->regs;
2905
2906         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2907         _usb_phy_init(phy);
2908         val = readl(base + ULPIS2S_CTRL);
2909         val |=  ULPIS2S_SLV0_CLAMP_XMIT;
2910         writel(val, base + ULPIS2S_CTRL);
2911
2912         val = readl(base + USB_SUSP_CTRL);
2913         val |= ULPIS2S_SLV0_RESET;
2914         writel(val, base + USB_SUSP_CTRL);
2915         udelay(10);
2916
2917         return 0;
2918 }
2919
2920 static int ulpi_null_phy_irq(struct tegra_usb_phy *phy)
2921 {
2922         return IRQ_HANDLED;
2923 }
2924
2925 /* NOTE: this function must be called after ehci reset */
2926 static int ulpi_null_phy_cmd_reset(struct tegra_usb_phy *phy)
2927 {
2928         unsigned long val;
2929         void __iomem *base = phy->regs;
2930
2931         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2932         ulpi_set_host(base);
2933
2934         /* remove slave0 reset */
2935         val = readl(base + USB_SUSP_CTRL);
2936         val &= ~ULPIS2S_SLV0_RESET;
2937         writel(val, base + USB_SUSP_CTRL);
2938
2939         val = readl(base + ULPIS2S_CTRL);
2940         val &=  ~ULPIS2S_SLV0_CLAMP_XMIT;
2941         writel(val, base + ULPIS2S_CTRL);
2942         udelay(10);
2943
2944         return 0;
2945 }
2946
2947 static int ulpi_null_phy_restore(struct tegra_usb_phy *phy)
2948 {
2949         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
2950         unsigned long timeout;
2951         int ulpi_stp = ULPI_STP;
2952
2953         if (gpio_is_valid(config->phy_restore_gpio))
2954                 ulpi_stp = config->phy_restore_gpio;
2955
2956         /* disable ULPI pinmux bypass */
2957         ulpi_pinmux_bypass(phy, false);
2958
2959         /* driving linstate by GPIO */
2960         gpio_set_value(ULPI_D0, 0);
2961         gpio_set_value(ULPI_D1, 0);
2962
2963         /* driving DIR high */
2964         gpio_set_value(ULPI_DIR, 1);
2965
2966         /* remove ULPI tristate */
2967         ulpi_null_phy_set_tristate(false);
2968
2969         /* wait for STP high */
2970         timeout = jiffies + msecs_to_jiffies(25);
2971
2972         while (!gpio_get_value(ulpi_stp)) {
2973                 if (time_after(jiffies, timeout)) {
2974                         pr_warn("phy restore timeout\n");
2975                         return 1;
2976                 }
2977         }
2978
2979         return 0;
2980 }
2981
2982 static int ulpi_null_phy_lp0_resume(struct tegra_usb_phy *phy)
2983 {
2984         unsigned long val;
2985         void __iomem *base = phy->regs;
2986
2987         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
2988         ulpi_null_phy_init(phy);
2989
2990         val = readl(base + USB_USBCMD);
2991         val |= USB_CMD_RESET;
2992         writel(val, base + USB_USBCMD);
2993
2994         if (usb_phy_reg_status_wait(base + USB_USBCMD,
2995                 USB_CMD_RESET, 0, 2500) < 0) {
2996                 pr_err("%s: timeout waiting for reset\n", __func__);
2997         }
2998
2999         ulpi_null_phy_cmd_reset(phy);
3000
3001         val = readl(base + USB_USBCMD);
3002         val |= USB_USBCMD_RS;
3003         writel(val, base + USB_USBCMD);
3004         if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS,
3005                                                  USB_USBCMD_RS, 2000)) {
3006                 pr_err("%s: timeout waiting for USB_USBCMD_RS\n", __func__);
3007                 return -ETIMEDOUT;
3008         }
3009
3010         /* Enable Port Power */
3011         val = readl(base + USB_PORTSC);
3012         val |= USB_PORTSC_PP;
3013         writel(val, base + USB_PORTSC);
3014         udelay(10);
3015
3016         ulpi_null_phy_restore(phy);
3017
3018         return 0;
3019 }
3020
3021 static int ulpi_null_phy_power_on(struct tegra_usb_phy *phy)
3022 {
3023         unsigned long val;
3024         void __iomem *base = phy->regs;
3025         struct tegra_ulpi_config *config = &phy->pdata->u_cfg.ulpi;
3026
3027         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
3028         if (phy->phy_clk_on) {
3029                 DBG("%s(%d) inst:[%d] phy clk is already On\n", __func__,
3030                                                         __LINE__, phy->inst);
3031                 return 0;
3032         }
3033         reset_utmip_uhsic(base);
3034
3035         /* remove ULPI PADS CLKEN reset */
3036         val = readl(base + USB_SUSP_CTRL);
3037         val &= ~ULPI_PADS_CLKEN_RESET;
3038         writel(val, base + USB_SUSP_CTRL);
3039         udelay(10);
3040
3041         val = readl(base + ULPI_TIMING_CTRL_0);
3042         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
3043         writel(val, base + ULPI_TIMING_CTRL_0);
3044
3045         val = readl(base + USB_SUSP_CTRL);
3046         val |= ULPI_PHY_ENABLE;
3047         writel(val, base + USB_SUSP_CTRL);
3048         udelay(10);
3049
3050         /* set timming parameters */
3051         val = readl(base + ULPI_TIMING_CTRL_0);
3052         val |= ULPI_SHADOW_CLK_LOOPBACK_EN;
3053         val &= ~ULPI_SHADOW_CLK_SEL;
3054         val &= ~ULPI_LBK_PAD_EN;
3055         val |= ULPI_SHADOW_CLK_DELAY(config->shadow_clk_delay);
3056         val |= ULPI_CLOCK_OUT_DELAY(config->clock_out_delay);
3057         val |= ULPI_LBK_PAD_E_INPUT_OR;
3058         writel(val, base + ULPI_TIMING_CTRL_0);
3059
3060         writel(0, base + ULPI_TIMING_CTRL_1);
3061         udelay(10);
3062
3063         /* start internal 60MHz clock */
3064         val = readl(base + ULPIS2S_CTRL);
3065         val |= ULPIS2S_ENA;
3066         val |= ULPIS2S_SUPPORT_DISCONNECT;
3067         val |= ULPIS2S_SPARE((phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) ? 3 : 1);
3068         val |= ULPIS2S_PLLU_MASTER_BLASTER60;
3069         writel(val, base + ULPIS2S_CTRL);
3070
3071         /* select ULPI_CORE_CLK_SEL to SHADOW_CLK */
3072         val = readl(base + ULPI_TIMING_CTRL_0);
3073         val |= ULPI_CORE_CLK_SEL;
3074         writel(val, base + ULPI_TIMING_CTRL_0);
3075         udelay(10);
3076
3077         /* enable ULPI null phy clock - can't set the trimmers before this */
3078         val = readl(base + ULPI_TIMING_CTRL_0);
3079         val |= ULPI_CLK_OUT_ENA;
3080         writel(val, base + ULPI_TIMING_CTRL_0);
3081         udelay(10);
3082
3083         if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
3084                                                  USB_PHY_CLK_VALID, 2500)) {
3085                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
3086                 return -ETIMEDOUT;
3087         }
3088
3089         /* set ULPI trimmers */
3090         ulpi_set_trimmer(phy);
3091
3092         ulpi_set_host(base);
3093
3094         /* remove slave0 reset */
3095         val = readl(base + USB_SUSP_CTRL);
3096         val &= ~ULPIS2S_SLV0_RESET;
3097         writel(val, base + USB_SUSP_CTRL);
3098
3099         /* remove slave1 and line reset */
3100         val = readl(base + USB_SUSP_CTRL);
3101         val &= ~ULPIS2S_SLV1_RESET;
3102         val &= ~ULPIS2S_LINE_RESET;
3103
3104         /* remove ULPI PADS reset */
3105         val &= ~ULPI_PADS_RESET;
3106         writel(val, base + USB_SUSP_CTRL);
3107
3108         if (!phy->ulpi_clk_padout_ena) {
3109                 val = readl(base + ULPI_TIMING_CTRL_0);
3110                 val |= ULPI_CLK_PADOUT_ENA;
3111                 writel(val, base + ULPI_TIMING_CTRL_0);
3112                 phy->ulpi_clk_padout_ena = true;
3113         } else {
3114                 if (!readl(base + USB_ASYNCLISTADDR))
3115                         ulpi_null_phy_lp0_resume(phy);
3116         }
3117         udelay(10);
3118
3119         phy->phy_clk_on = true;
3120         phy->hw_accessible = true;
3121
3122         return 0;
3123 }
3124
3125 static int ulpi_null_phy_pre_resume(struct tegra_usb_phy *phy,
3126                                     bool remote_wakeup)
3127 {
3128         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
3129         ulpi_null_phy_obs_read();
3130         return 0;
3131 }
3132
3133 static int ulpi_null_phy_post_resume(struct tegra_usb_phy *phy)
3134 {
3135         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
3136         ulpi_null_phy_obs_read();
3137         return 0;
3138 }
3139
3140 static int ulpi_null_phy_resume(struct tegra_usb_phy *phy)
3141 {
3142         unsigned long val;
3143         void __iomem *base = phy->regs;
3144
3145         if (!readl(base + USB_ASYNCLISTADDR)) {
3146                 /* enable ULPI CLK output pad */
3147                 val = readl(base + ULPI_TIMING_CTRL_0);
3148                 val |= ULPI_CLK_PADOUT_ENA;
3149                 writel(val, base + ULPI_TIMING_CTRL_0);
3150
3151                 /* enable ULPI pinmux bypass */
3152                 ulpi_pinmux_bypass(phy, true);
3153                 udelay(5);
3154 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
3155                 /* remove DIR tristate */
3156                 tegra_pinmux_set_tristate(TEGRA_PINGROUP_ULPI_DIR,
3157                                           TEGRA_TRI_NORMAL);
3158 #endif
3159         }
3160         return 0;
3161 }
3162
3163 static struct tegra_usb_phy_ops utmi_phy_ops = {
3164         .init           = _usb_phy_init,
3165         .reset          = usb_phy_reset,
3166         .open           = utmi_phy_open,
3167         .close          = utmi_phy_close,
3168         .irq            = utmi_phy_irq,
3169         .power_on       = utmi_phy_power_on,
3170         .power_off      = utmi_phy_power_off,
3171         .pre_resume = utmi_phy_pre_resume,
3172         .resume = utmi_phy_resume,
3173         .charger_detect = utmi_phy_charger_detect,
3174         .nv_charger_detect = utmi_phy_nv_charger_detect,
3175 };
3176
3177 static struct tegra_usb_phy_ops uhsic_phy_ops = {
3178         .init           = _usb_phy_init,
3179         .open           = uhsic_phy_open,
3180         .close          = uhsic_phy_close,
3181         .irq            = uhsic_phy_irq,
3182         .power_on       = uhsic_phy_power_on,
3183         .power_off      = uhsic_phy_power_off,
3184         .pre_resume     = uhsic_phy_pre_resume,
3185         .port_power = uhsic_phy_bus_port_power,
3186 };
3187
3188 static struct tegra_usb_phy_ops ulpi_link_phy_ops = {
3189         .init           = _usb_phy_init,
3190         .reset          = usb_phy_reset,
3191         .open           = ulpi_link_phy_open,
3192         .close          = ulpi_link_phy_close,
3193         .irq            = ulpi_link_phy_irq,
3194         .power_on       = ulpi_link_phy_power_on,
3195         .power_off      = ulpi_link_phy_power_off,
3196         .resume         = ulpi_link_phy_resume,
3197 };
3198
3199 static struct tegra_usb_phy_ops ulpi_null_phy_ops = {
3200         .open           = ulpi_null_phy_open,
3201         .close          = ulpi_null_phy_close,
3202         .init           = ulpi_null_phy_init,
3203         .irq            = ulpi_null_phy_irq,
3204         .power_on       = ulpi_null_phy_power_on,
3205         .power_off      = ulpi_null_phy_power_off,
3206         .pre_resume = ulpi_null_phy_pre_resume,
3207         .resume = ulpi_null_phy_resume,
3208         .post_resume = ulpi_null_phy_post_resume,
3209         .reset          = ulpi_null_phy_cmd_reset,
3210 };
3211
3212 static struct tegra_usb_phy_ops icusb_phy_ops;
3213
3214 static struct tegra_usb_phy_ops *phy_ops[] = {
3215         [TEGRA_USB_PHY_INTF_UTMI] = &utmi_phy_ops,
3216         [TEGRA_USB_PHY_INTF_ULPI_LINK] = &ulpi_link_phy_ops,
3217         [TEGRA_USB_PHY_INTF_ULPI_NULL] = &ulpi_null_phy_ops,
3218         [TEGRA_USB_PHY_INTF_HSIC] = &uhsic_phy_ops,
3219         [TEGRA_USB_PHY_INTF_ICUSB] = &icusb_phy_ops,
3220 };
3221
3222 int tegra11x_usb_phy_init_ops(struct tegra_usb_phy *phy)
3223 {
3224         DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
3225
3226         phy->ops = phy_ops[phy->pdata->phy_intf];
3227
3228         /* FIXME: uncommenting below line to make USB host mode fail*/
3229         /* usb_phy_power_down_pmc(); */
3230
3231         return 0;
3232 }