ARM: tegra11: clock: Use tabulated EMC clock register
[linux-2.6.git] / arch / arm / mach-tegra / tegra11_emc.c
1 /*
2  * arch/arm/mach-tegra/tegra11_emc.c
3  *
4  * Copyright (C) 2011-2012 NVIDIA Corporation
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  *
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/clk.h>
23 #include <linux/err.h>
24 #include <linux/io.h>
25 #include <linux/module.h>
26 #include <linux/delay.h>
27 #include <linux/platform_device.h>
28 #include <linux/platform_data/tegra_emc.h>
29 #include <linux/debugfs.h>
30 #include <linux/seq_file.h>
31 #include <linux/hrtimer.h>
32
33 #include <asm/cputime.h>
34
35 #include <mach/iomap.h>
36
37 #include "clock.h"
38 #include "dvfs.h"
39 #include "tegra11_emc.h"
40
41 #ifdef CONFIG_TEGRA_EMC_SCALING_ENABLE
42 static bool emc_enable = true;
43 #else
44 static bool emc_enable;
45 #endif
46 module_param(emc_enable, bool, 0644);
47
48 u8 tegra_emc_bw_efficiency = 100;
49
50 #define PLL_C_DIRECT_FLOOR              333500000
51 #define EMC_STATUS_UPDATE_TIMEOUT       100
52 #define TEGRA_EMC_TABLE_MAX_SIZE        16
53
54 enum {
55         DLL_CHANGE_NONE = 0,
56         DLL_CHANGE_ON,
57         DLL_CHANGE_OFF,
58 };
59
60 #define EMC_CLK_DIV_SHIFT               0
61 #define EMC_CLK_DIV_MASK                (0xFF << EMC_CLK_DIV_SHIFT)
62 #define EMC_CLK_SOURCE_SHIFT            29
63 #define EMC_CLK_SOURCE_MASK             (0x7 << EMC_CLK_SOURCE_SHIFT)
64 #define EMC_CLK_LOW_JITTER_ENABLE       (0x1 << 31)
65 #define EMC_CLK_MC_SAME_FREQ            (0x1 << 16)
66
67 /* FIXME: actual Tegar11 list */
68 #define BURST_REG_LIST \
69         DEFINE_REG(TEGRA_EMC_BASE, EMC_RC),                     \
70         DEFINE_REG(TEGRA_EMC_BASE, EMC_RFC),                    \
71         DEFINE_REG(TEGRA_EMC_BASE, EMC_RFC_SLR),                \
72         DEFINE_REG(TEGRA_EMC_BASE, EMC_RAS),                    \
73         DEFINE_REG(TEGRA_EMC_BASE, EMC_RP),                     \
74         DEFINE_REG(TEGRA_EMC_BASE, EMC_R2W),                    \
75         DEFINE_REG(TEGRA_EMC_BASE, EMC_W2R),                    \
76         DEFINE_REG(TEGRA_EMC_BASE, EMC_R2P),                    \
77         DEFINE_REG(TEGRA_EMC_BASE, EMC_W2P),                    \
78         DEFINE_REG(TEGRA_EMC_BASE, EMC_RD_RCD),                 \
79         DEFINE_REG(TEGRA_EMC_BASE, EMC_WR_RCD),                 \
80         DEFINE_REG(TEGRA_EMC_BASE, EMC_RRD),                    \
81         DEFINE_REG(TEGRA_EMC_BASE, EMC_REXT),                   \
82         DEFINE_REG(TEGRA_EMC_BASE, EMC_WEXT),                   \
83         DEFINE_REG(TEGRA_EMC_BASE, EMC_WDV),                    \
84         DEFINE_REG(TEGRA_EMC_BASE, EMC_WDV_MASK),               \
85         DEFINE_REG(TEGRA_EMC_BASE, EMC_IBDLY),                  \
86         DEFINE_REG(TEGRA_EMC_BASE, EMC_PUTERM_EXTRA),           \
87         DEFINE_REG(TEGRA_EMC_BASE, EMC_CDB_CNTL_2),             \
88         DEFINE_REG(TEGRA_EMC_BASE, EMC_QRST),                   \
89         DEFINE_REG(TEGRA_EMC_BASE, EMC_RDV_MASK),               \
90         DEFINE_REG(TEGRA_EMC_BASE, EMC_REFRESH),                \
91         DEFINE_REG(TEGRA_EMC_BASE, EMC_BURST_REFRESH_NUM),      \
92         DEFINE_REG(TEGRA_EMC_BASE, EMC_PRE_REFRESH_REQ_CNT),    \
93         DEFINE_REG(TEGRA_EMC_BASE, EMC_PDEX2WR),                \
94         DEFINE_REG(TEGRA_EMC_BASE, EMC_PDEX2RD),                \
95         DEFINE_REG(TEGRA_EMC_BASE, EMC_PCHG2PDEN),              \
96         DEFINE_REG(TEGRA_EMC_BASE, EMC_ACT2PDEN),               \
97         DEFINE_REG(TEGRA_EMC_BASE, EMC_AR2PDEN),                \
98         DEFINE_REG(TEGRA_EMC_BASE, EMC_RW2PDEN),                \
99         DEFINE_REG(TEGRA_EMC_BASE, EMC_TXSR),                   \
100         DEFINE_REG(TEGRA_EMC_BASE, EMC_TXSRDLL),                \
101         DEFINE_REG(TEGRA_EMC_BASE, EMC_TCKE),                   \
102         DEFINE_REG(TEGRA_EMC_BASE, EMC_TCKESR),                 \
103         DEFINE_REG(TEGRA_EMC_BASE, EMC_TPD),                    \
104         DEFINE_REG(TEGRA_EMC_BASE, EMC_TFAW),                   \
105         DEFINE_REG(TEGRA_EMC_BASE, EMC_TRPAB),                  \
106         DEFINE_REG(TEGRA_EMC_BASE, EMC_TCLKSTABLE),             \
107         DEFINE_REG(TEGRA_EMC_BASE, EMC_TCLKSTOP),               \
108         DEFINE_REG(TEGRA_EMC_BASE, EMC_TREFBW),                 \
109         DEFINE_REG(TEGRA_EMC_BASE, EMC_QUSE_EXTRA),             \
110         DEFINE_REG(TEGRA_EMC_BASE, EMC_ODT_WRITE),              \
111         DEFINE_REG(TEGRA_EMC_BASE, EMC_ODT_READ),               \
112         DEFINE_REG(TEGRA_EMC_BASE, EMC_FBIO_CFG5),              \
113         DEFINE_REG(TEGRA_EMC_BASE, EMC_CFG_DIG_DLL),            \
114         DEFINE_REG(TEGRA_EMC_BASE, EMC_CFG_DIG_DLL_PERIOD),     \
115         DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_DQS4),         \
116         DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_DQS5),         \
117         DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_DQS6),         \
118         DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_DQS7),         \
119         DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_QUSE4),        \
120         DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_QUSE5),        \
121         DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_QUSE6),        \
122         DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_QUSE7),        \
123         DEFINE_REG(TEGRA_EMC_BASE, EMC_DLI_TRIM_TXDQS4),        \
124         DEFINE_REG(TEGRA_EMC_BASE, EMC_DLI_TRIM_TXDQS5),        \
125         DEFINE_REG(TEGRA_EMC_BASE, EMC_DLI_TRIM_TXDQS6),        \
126         DEFINE_REG(TEGRA_EMC_BASE, EMC_DLI_TRIM_TXDQS7),        \
127         DEFINE_REG(TEGRA_EMC_BASE, EMC_XM2CMDPADCTRL),          \
128         DEFINE_REG(TEGRA_EMC_BASE, EMC_XM2CMDPADCTRL4),         \
129         DEFINE_REG(TEGRA_EMC_BASE, EMC_XM2DQSPADCTRL2),         \
130         DEFINE_REG(TEGRA_EMC_BASE, EMC_XM2DQPADCTRL2),          \
131         DEFINE_REG(TEGRA_EMC_BASE, EMC_XM2CLKPADCTRL),          \
132         DEFINE_REG(TEGRA_EMC_BASE, EMC_XM2COMPPADCTRL),         \
133         DEFINE_REG(TEGRA_EMC_BASE, EMC_XM2VTTGENPADCTRL),       \
134         DEFINE_REG(TEGRA_EMC_BASE, EMC_XM2VTTGENPADCTRL2),      \
135         DEFINE_REG(TEGRA_EMC_BASE, EMC_DSR_VTTGEN_DRV),         \
136         DEFINE_REG(TEGRA_EMC_BASE, EMC_TXDSRVTTGEN),            \
137         DEFINE_REG(TEGRA_EMC_BASE, EMC_FBIO_SPARE),             \
138         DEFINE_REG(TEGRA_EMC_BASE, EMC_CTT_TERM_CTRL),          \
139         DEFINE_REG(TEGRA_EMC_BASE, EMC_ZCAL_INTERVAL),          \
140         DEFINE_REG(TEGRA_EMC_BASE, EMC_ZCAL_WAIT_CNT),          \
141         DEFINE_REG(TEGRA_EMC_BASE, EMC_MRS_WAIT_CNT),           \
142         DEFINE_REG(TEGRA_EMC_BASE, EMC_MRS_WAIT_CNT2),          \
143         DEFINE_REG(TEGRA_EMC_BASE, EMC_AUTO_CAL_CONFIG2),       \
144         DEFINE_REG(TEGRA_EMC_BASE, EMC_AUTO_CAL_CONFIG3),       \
145         DEFINE_REG(TEGRA_EMC_BASE, EMC_CTT),                    \
146         DEFINE_REG(TEGRA_EMC_BASE, EMC_CTT_DURATION),           \
147         DEFINE_REG(TEGRA_EMC_BASE, EMC_DYN_SELF_REF_CONTROL),   \
148         DEFINE_REG(TEGRA_EMC_BASE, EMC_CA_TRAINING_TIMING_CNTL1),       \
149         DEFINE_REG(TEGRA_EMC_BASE, EMC_CA_TRAINING_TIMING_CNTL2),       \
150                                                                         \
151         DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_CFG),             \
152         DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_OUTSTANDING_REQ), \
153         DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_RCD),      \
154         DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_RP),       \
155         DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_RC),       \
156         DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_RAS),      \
157         DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_FAW),      \
158         DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_RRD),      \
159         DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_RAP2PRE),  \
160         DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_WAP2PRE),  \
161         DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_R2R),      \
162         DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_W2W),      \
163         DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_R2W),      \
164         DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_W2R),      \
165         DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_DA_TURNS),        \
166         DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_DA_COVERS),       \
167         DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_MISC0),           \
168         DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_RING1_THROTTLE),
169
170 #define BURST_UP_DOWN_REG_LIST \
171         DEFINE_REG(TEGRA_MC_BASE, MC_PTSA_GRANT_DECREMENT),     \
172         DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_G2_0),   \
173         DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_G2_1),   \
174         DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_NV_0),   \
175         DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_NV2_0),  \
176         DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_NV_2),   \
177         DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_NV_1),   \
178         DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_NV2_1),  \
179         DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_NV_3),   \
180         DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_EPP_0),  \
181         DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_EPP_1),
182
183 #define EMC_TRIMMERS_REG_LIST \
184         DEFINE_REG(0, EMC_CDB_CNTL_1),                          \
185         DEFINE_REG(0, EMC_FBIO_CFG6),                           \
186         DEFINE_REG(0, EMC_QUSE),                                \
187         DEFINE_REG(0, EMC_EINPUT),                              \
188         DEFINE_REG(0, EMC_EINPUT_DURATION),                     \
189         DEFINE_REG(0, EMC_DLL_XFORM_DQS0),                      \
190         DEFINE_REG(0, EMC_QSAFE),                               \
191         DEFINE_REG(0, EMC_DLL_XFORM_QUSE0),                     \
192         DEFINE_REG(0, EMC_RDV),                                 \
193         DEFINE_REG(0, EMC_XM2DQSPADCTRL4),                      \
194         DEFINE_REG(0, EMC_XM2DQSPADCTRL3),                      \
195         DEFINE_REG(0, EMC_DLL_XFORM_DQ0),                       \
196         DEFINE_REG(0, EMC_AUTO_CAL_CONFIG),                     \
197         DEFINE_REG(0, EMC_DLL_XFORM_ADDR0),                     \
198         DEFINE_REG(0, EMC_XM2CLKPADCTRL2),                      \
199         DEFINE_REG(0, EMC_DLI_TRIM_TXDQS0),                     \
200         DEFINE_REG(0, EMC_DLL_XFORM_ADDR1),                     \
201         DEFINE_REG(0, EMC_DLL_XFORM_ADDR2),                     \
202         DEFINE_REG(0, EMC_DLL_XFORM_DQS1),                      \
203         DEFINE_REG(0, EMC_DLL_XFORM_DQS2),                      \
204         DEFINE_REG(0, EMC_DLL_XFORM_DQS3),                      \
205         DEFINE_REG(0, EMC_DLL_XFORM_DQ1),                       \
206         DEFINE_REG(0, EMC_DLL_XFORM_DQ2),                       \
207         DEFINE_REG(0, EMC_DLL_XFORM_DQ3),                       \
208         DEFINE_REG(0, EMC_DLI_TRIM_TXDQS1),                     \
209         DEFINE_REG(0, EMC_DLI_TRIM_TXDQS2),                     \
210         DEFINE_REG(0, EMC_DLI_TRIM_TXDQS3),                     \
211         DEFINE_REG(0, EMC_DLL_XFORM_QUSE1),                     \
212         DEFINE_REG(0, EMC_DLL_XFORM_QUSE2),                     \
213         DEFINE_REG(0, EMC_DLL_XFORM_QUSE3),
214
215
216 #define DEFINE_REG(base, reg) ((base) ? (IO_ADDRESS((base)) + (reg)) : 0)
217 static const void __iomem *burst_reg_addr[TEGRA11_EMC_MAX_NUM_REGS] = {
218         BURST_REG_LIST
219 };
220 #ifndef EMULATE_CLOCK_SWITCH
221 static const void __iomem *burst_up_down_reg_addr[TEGRA11_EMC_MAX_NUM_REGS] = {
222         BURST_UP_DOWN_REG_LIST
223 };
224 #endif
225 #undef DEFINE_REG
226
227
228 #define DEFINE_REG(base, reg) (reg)
229 #ifndef EMULATE_CLOCK_SWITCH
230 static const u32 emc_trimmer_offs[TEGRA11_EMC_MAX_NUM_REGS] = {
231         EMC_TRIMMERS_REG_LIST
232 };
233 #endif
234 #undef DEFINE_REG
235
236
237 #define DEFINE_REG(base, reg)   reg##_INDEX
238 enum {
239         BURST_REG_LIST
240 };
241 #undef DEFINE_REG
242
243 #define DEFINE_REG(base, reg)   reg##_TRIM_INDEX
244 enum {
245         EMC_TRIMMERS_REG_LIST
246 };
247 #undef DEFINE_REG
248
249
250 struct emc_sel {
251         struct clk      *input;
252         u32             value;
253         unsigned long   input_rate;
254 };
255 static struct emc_sel tegra_emc_clk_sel[TEGRA_EMC_TABLE_MAX_SIZE];
256 static struct tegra11_emc_table start_timing;
257 static const struct tegra11_emc_table *emc_timing;
258
259 static ktime_t clkchange_time;
260 static int clkchange_delay = 100;
261
262 static const u32 *dram_to_soc_bit_map;
263 static const struct tegra11_emc_table *tegra_emc_table;
264 static int tegra_emc_table_size;
265
266 static u32 dram_dev_num;
267 static u32 dram_type = -1;
268
269 static struct clk *emc;
270
271 static struct {
272         cputime64_t time_at_clock[TEGRA_EMC_TABLE_MAX_SIZE];
273         int last_sel;
274         u64 last_update;
275         u64 clkchange_count;
276         spinlock_t spinlock;
277 } emc_stats;
278
279 static DEFINE_SPINLOCK(emc_access_lock);
280
281 static void __iomem *emc_base = IO_ADDRESS(TEGRA_EMC_BASE);
282 static void __iomem *emc0_base = IO_ADDRESS(TEGRA_EMC0_BASE);
283 static void __iomem *emc1_base = IO_ADDRESS(TEGRA_EMC1_BASE);
284 static void __iomem *mc_base = IO_ADDRESS(TEGRA_MC_BASE);
285 static void __iomem *clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
286
287 static inline void emc_writel(u32 val, unsigned long addr)
288 {
289         writel(val, (u32)emc_base + addr);
290 }
291 static inline void emc0_writel(u32 val, unsigned long addr)
292 {
293         writel(val, (u32)emc0_base + addr);
294 }
295 static inline void emc1_writel(u32 val, unsigned long addr)
296 {
297         writel(val, (u32)emc1_base + addr);
298 }
299 static inline u32 emc_readl(unsigned long addr)
300 {
301         return readl((u32)emc_base + addr);
302 }
303 static inline void mc_writel(u32 val, unsigned long addr)
304 {
305         writel(val, (u32)mc_base + addr);
306 }
307 static inline u32 mc_readl(unsigned long addr)
308 {
309         return readl((u32)mc_base + addr);
310 }
311
312 static inline void ccfifo_writel(u32 val, unsigned long addr)
313 {
314         writel(val, (u32)emc_base + EMC_CCFIFO_DATA);
315         writel(addr, (u32)emc_base + EMC_CCFIFO_ADDR);
316 }
317
318 static void emc_last_stats_update(int last_sel)
319 {
320         unsigned long flags;
321         u64 cur_jiffies = get_jiffies_64();
322
323         spin_lock_irqsave(&emc_stats.spinlock, flags);
324
325         if (emc_stats.last_sel < TEGRA_EMC_TABLE_MAX_SIZE)
326                 emc_stats.time_at_clock[emc_stats.last_sel] =
327                         emc_stats.time_at_clock[emc_stats.last_sel] +
328                         (cur_jiffies - emc_stats.last_update);
329
330         emc_stats.last_update = cur_jiffies;
331
332         if (last_sel < TEGRA_EMC_TABLE_MAX_SIZE) {
333                 emc_stats.clkchange_count++;
334                 emc_stats.last_sel = last_sel;
335         }
336         spin_unlock_irqrestore(&emc_stats.spinlock, flags);
337 }
338
339 static int wait_for_update(u32 status_reg, u32 bit_mask, bool updated_state)
340 {
341         int i;
342         for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; i++) {
343                 if (!!(emc_readl(status_reg) & bit_mask) == updated_state)
344                         return 0;
345                 udelay(1);
346         }
347         return -ETIMEDOUT;
348 }
349
350 static inline void emc_timing_update(void)
351 {
352         int err;
353
354         emc_writel(0x1, EMC_TIMING_CONTROL);
355         err = wait_for_update(EMC_STATUS,
356                               EMC_STATUS_TIMING_UPDATE_STALLED, false);
357         if (err) {
358                 pr_err("%s: timing update error: %d", __func__, err);
359                 BUG();
360         }
361 }
362
363 static inline void auto_cal_disable(void)
364 {
365         int err;
366
367         emc_writel(0, EMC_AUTO_CAL_INTERVAL);
368         err = wait_for_update(EMC_AUTO_CAL_STATUS,
369                               EMC_AUTO_CAL_STATUS_ACTIVE, false);
370         if (err) {
371                 pr_err("%s: disable auto-cal error: %d", __func__, err);
372                 BUG();
373         }
374 }
375
376 static inline bool dqs_preset(const struct tegra11_emc_table *next_timing,
377                               const struct tegra11_emc_table *last_timing)
378 {
379         bool ret = false;
380
381 #define DQS_SET(reg, bit)                                                     \
382         do {                                                                  \
383                 if ((next_timing->burst_regs[EMC_##reg##_INDEX] &             \
384                      EMC_##reg##_##bit##_ENABLE) &&                           \
385                     (!(last_timing->burst_regs[EMC_##reg##_INDEX] &           \
386                        EMC_##reg##_##bit##_ENABLE)))   {                      \
387                         emc_writel(last_timing->burst_regs[EMC_##reg##_INDEX] \
388                                    | EMC_##reg##_##bit##_ENABLE, EMC_##reg);  \
389                         ret = true;                                           \
390                 }                                                             \
391         } while (0)
392
393
394 #define DQS_SET_TRIM(reg, bit, ch)                                             \
395         do {                                                                   \
396                 if ((next_timing->emc_trimmers_##ch[EMC_##reg##_TRIM_INDEX]    \
397                      & EMC_##reg##_##bit##_ENABLE) &&                          \
398                     (!(last_timing->emc_trimmers_##ch[EMC_##reg##_TRIM_INDEX]  \
399                        & EMC_##reg##_##bit##_ENABLE)))   {                     \
400                         emc##ch##_writel(last_timing->emc_trimmers_##ch[EMC_##reg##_TRIM_INDEX] \
401                                    | EMC_##reg##_##bit##_ENABLE, EMC_##reg);   \
402                         ret = true;                                            \
403                 }                                                              \
404         } while (0)
405
406         DQS_SET(XM2DQSPADCTRL2, VREF);
407         DQS_SET_TRIM(XM2DQSPADCTRL3, VREF, 0);
408         DQS_SET_TRIM(XM2DQSPADCTRL3, VREF, 1);
409
410         return ret;
411 }
412
413 static inline void overwrite_mrs_wait_cnt(
414         const struct tegra11_emc_table *next_timing,
415         bool zcal_long)
416 {
417         u32 reg;
418         u32 cnt = 512;
419
420         /* For ddr3 when DLL is re-started: overwrite EMC DFS table settings
421            for MRS_WAIT_LONG with maximum of MRS_WAIT_SHORT settings and
422            expected operation length. Reduce the latter by the overlapping
423            zq-calibration, if any */
424         if (zcal_long)
425                 cnt -= dram_dev_num * 256;
426
427         reg = (next_timing->burst_regs[EMC_MRS_WAIT_CNT_INDEX] &
428                 EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK) >>
429                 EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT;
430         if (cnt < reg)
431                 cnt = reg;
432
433         reg = (next_timing->burst_regs[EMC_MRS_WAIT_CNT_INDEX] &
434                 (~EMC_MRS_WAIT_CNT_LONG_WAIT_MASK));
435         reg |= (cnt << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT) &
436                 EMC_MRS_WAIT_CNT_LONG_WAIT_MASK;
437
438         emc_writel(reg, EMC_MRS_WAIT_CNT);
439 }
440
441 static inline int get_dll_change(const struct tegra11_emc_table *next_timing,
442                                  const struct tegra11_emc_table *last_timing)
443 {
444         bool next_dll_enabled = !(next_timing->emc_mode_1 & 0x1);
445         bool last_dll_enabled = !(last_timing->emc_mode_1 & 0x1);
446
447         if (next_dll_enabled == last_dll_enabled)
448                 return DLL_CHANGE_NONE;
449         else if (next_dll_enabled)
450                 return DLL_CHANGE_ON;
451         else
452                 return DLL_CHANGE_OFF;
453 }
454
455 static inline void set_dram_mode(const struct tegra11_emc_table *next_timing,
456                                  const struct tegra11_emc_table *last_timing,
457                                  int dll_change)
458 {
459         if (dram_type == DRAM_TYPE_DDR3) {
460                 /* first mode_1, then mode_2, then mode_reset*/
461                 if (next_timing->emc_mode_1 != last_timing->emc_mode_1)
462                         ccfifo_writel(next_timing->emc_mode_1, EMC_EMRS);
463                 if (next_timing->emc_mode_2 != last_timing->emc_mode_2)
464                         ccfifo_writel(next_timing->emc_mode_2, EMC_EMRS2);
465
466                 if ((next_timing->emc_mode_reset !=
467                      last_timing->emc_mode_reset) ||
468                     (dll_change == DLL_CHANGE_ON)) {
469                         u32 reg = next_timing->emc_mode_reset &
470                                 (~EMC_MODE_SET_DLL_RESET);
471                         if (dll_change == DLL_CHANGE_ON) {
472                                 reg |= EMC_MODE_SET_DLL_RESET;
473                                 reg |= EMC_MODE_SET_LONG_CNT;
474                         }
475                         ccfifo_writel(reg, EMC_MRS);
476                 }
477         } else {
478                 /* first mode_2, then mode_1; mode_reset is not applicable */
479                 if (next_timing->emc_mode_2 != last_timing->emc_mode_2)
480                         ccfifo_writel(next_timing->emc_mode_2, EMC_MRW2);
481                 if (next_timing->emc_mode_1 != last_timing->emc_mode_1)
482                         ccfifo_writel(next_timing->emc_mode_1, EMC_MRW);
483                 if (next_timing->emc_mode_4 != last_timing->emc_mode_4)
484                         ccfifo_writel(next_timing->emc_mode_4, EMC_MRW4);
485         }
486 }
487
488 static inline void do_clock_change(u32 clk_setting)
489 {
490         int err;
491
492         mc_readl(MC_EMEM_ADR_CFG);      /* completes prev writes */
493         writel(clk_setting, (u32)clk_base + emc->reg);
494         readl((u32)clk_base + emc->reg);/* completes prev write */
495
496         err = wait_for_update(EMC_INTSTATUS,
497                               EMC_INTSTATUS_CLKCHANGE_COMPLETE, true);
498         if (err) {
499                 pr_err("%s: clock change completion error: %d", __func__, err);
500                 BUG();
501         }
502 }
503
504 static noinline void emc_set_clock(const struct tegra11_emc_table *next_timing,
505                                    const struct tegra11_emc_table *last_timing,
506                                    u32 clk_setting)
507 {
508 #ifndef EMULATE_CLOCK_SWITCH
509         int i, dll_change, pre_wait;
510         bool dyn_sref_enabled, zcal_long;
511
512         u32 emc_cfg_reg = emc_readl(EMC_CFG);
513
514         dyn_sref_enabled = emc_cfg_reg & EMC_CFG_DYN_SREF_ENABLE;
515         dll_change = get_dll_change(next_timing, last_timing);
516         zcal_long = (next_timing->burst_regs[EMC_ZCAL_INTERVAL_INDEX] != 0) &&
517                 (last_timing->burst_regs[EMC_ZCAL_INTERVAL_INDEX] == 0);
518
519         /* FIXME: remove steps enumeration below? */
520
521         /* 1. clear clkchange_complete interrupts */
522         emc_writel(EMC_INTSTATUS_CLKCHANGE_COMPLETE, EMC_INTSTATUS);
523
524         /* 2. disable dynamic self-refresh and preset dqs vref, then wait for
525            possible self-refresh entry/exit and/or dqs vref settled - waiting
526            before the clock change decreases worst case change stall time */
527         pre_wait = 0;
528         if (dyn_sref_enabled) {
529                 emc_cfg_reg &= ~EMC_CFG_DYN_SREF_ENABLE;
530                 emc_writel(emc_cfg_reg, EMC_CFG);
531                 pre_wait = 5;           /* 5us+ for self-refresh entry/exit */
532         }
533
534         /* 2.5 check dq/dqs vref delay */
535         if (dqs_preset(next_timing, last_timing)) {
536                 if (pre_wait < 3)
537                         pre_wait = 3;   /* 3us+ for dqs vref settled */
538         }
539         if (pre_wait) {
540                 emc_timing_update();
541                 udelay(pre_wait);
542         }
543
544         /* 3. disable auto-cal if vref mode is switching - removed */
545
546         /* 4. program burst shadow registers */
547         for (i = 0; i < next_timing->burst_regs_num; i++) {
548                 if (!burst_reg_addr[i])
549                         continue;
550                 __raw_writel(next_timing->burst_regs[i], burst_reg_addr[i]);
551         }
552         for (i = 0; i < next_timing->emc_trimmers_num; i++) {
553                 __raw_writel(next_timing->emc_trimmers_0[i],
554                         (u32)emc0_base + emc_trimmer_offs[i]);
555                 __raw_writel(next_timing->emc_trimmers_1[i],
556                         (u32)emc1_base + emc_trimmer_offs[i]);
557         }
558         emc_cfg_reg &= ~EMC_CFG_UPDATE_MASK;
559         emc_cfg_reg |= next_timing->emc_cfg & EMC_CFG_UPDATE_MASK;
560         emc_writel(emc_cfg_reg, EMC_CFG);
561         wmb();
562         barrier();
563
564         /* 4.1 On ddr3 when DLL is re-started predict MRS long wait count and
565            overwrite DFS table setting */
566         if ((dram_type == DRAM_TYPE_DDR3) && (dll_change == DLL_CHANGE_ON))
567                 overwrite_mrs_wait_cnt(next_timing, zcal_long);
568
569         /* 5.2 disable auto-refresh to save time after clock change */
570         emc_writel(EMC_REFCTRL_DISABLE_ALL(dram_dev_num), EMC_REFCTRL);
571
572         /* 6. turn Off dll and enter self-refresh on DDR3 */
573         if (dram_type == DRAM_TYPE_DDR3) {
574                 if (dll_change == DLL_CHANGE_OFF)
575                         ccfifo_writel(next_timing->emc_mode_1, EMC_EMRS);
576                 ccfifo_writel(DRAM_BROADCAST(dram_dev_num) |
577                               EMC_SELF_REF_CMD_ENABLED, EMC_SELF_REF);
578         }
579
580         /* 7. flow control marker 2 */
581         ccfifo_writel(1, EMC_STALL_THEN_EXE_AFTER_CLKCHANGE);
582
583         /* 8. exit self-refresh on DDR3 */
584         if (dram_type == DRAM_TYPE_DDR3)
585                 ccfifo_writel(DRAM_BROADCAST(dram_dev_num), EMC_SELF_REF);
586
587         /* 9. set dram mode registers */
588         set_dram_mode(next_timing, last_timing, dll_change);
589
590         /* 10. issue zcal command if turning zcal On */
591         if (zcal_long) {
592                 ccfifo_writel(EMC_ZQ_CAL_LONG_CMD_DEV0, EMC_ZQ_CAL);
593                 if (dram_dev_num > 1)
594                         ccfifo_writel(EMC_ZQ_CAL_LONG_CMD_DEV1, EMC_ZQ_CAL);
595         }
596
597         /* 10.1 dummy write to RO register to remove stall after change */
598         ccfifo_writel(0, EMC_CCFIFO_STATUS);
599
600         /* 11.5 program burst_up_down registers if emc rate is going down */
601         if (next_timing->rate < last_timing->rate) {
602                 for (i = 0; i < next_timing->burst_up_down_regs_num; i++)
603                         __raw_writel(next_timing->burst_up_down_regs[i],
604                                 burst_up_down_reg_addr[i]);
605                 wmb();
606         }
607
608         /* 12-14. read any MC register to ensure the programming is done
609            change EMC clock source register wait for clk change completion */
610         do_clock_change(clk_setting);
611
612         /* 14.1 re-enable auto-refresh */
613         emc_writel(EMC_REFCTRL_ENABLE_ALL(dram_dev_num), EMC_REFCTRL);
614
615         /* 14.2 program burst_up_down registers if emc rate is going up */
616         if (next_timing->rate > last_timing->rate) {
617                 for (i = 0; i < next_timing->burst_up_down_regs_num; i++)
618                         __raw_writel(next_timing->burst_up_down_regs[i],
619                                 burst_up_down_reg_addr[i]);
620                 wmb();
621         }
622
623         /* 15. restore auto-cal - removed */
624
625         /* 16. restore dynamic self-refresh */
626         if (next_timing->emc_cfg & EMC_CFG_DYN_SREF_ENABLE) {
627                 emc_cfg_reg |= EMC_CFG_DYN_SREF_ENABLE;
628                 emc_writel(emc_cfg_reg, EMC_CFG);
629         }
630
631         /* 17. set zcal wait count */
632         if (zcal_long)
633                 emc_writel(next_timing->emc_zcal_cnt_long, EMC_ZCAL_WAIT_CNT);
634
635         /* 18. update restored timing */
636         udelay(2);
637         emc_timing_update();
638 #else
639         /* FIXME: implement */
640         pr_info("tegra11_emc: Configuring EMC rate %lu (setting: 0x%x)\n",
641                 next_timing->rate, clk_setting);
642 #endif
643 }
644
645 static inline void emc_get_timing(struct tegra11_emc_table *timing)
646 {
647         int i;
648
649         /* burst and trimmers updates depends on previous state; burst_up_down
650            are stateless */
651         for (i = 0; i < timing->burst_regs_num; i++) {
652                 if (burst_reg_addr[i])
653                         timing->burst_regs[i] = __raw_readl(burst_reg_addr[i]);
654                 else
655                         timing->burst_regs[i] = 0;
656         }
657         for (i = 0; i < timing->emc_trimmers_num; i++) {
658                 timing->emc_trimmers_0[i] =
659                         __raw_readl((u32)emc0_base + emc_trimmer_offs[i]);
660                 timing->emc_trimmers_1[i] =
661                         __raw_readl((u32)emc1_base + emc_trimmer_offs[i]);
662         }
663         timing->emc_acal_interval = 0;
664         timing->emc_zcal_cnt_long = 0;
665         timing->emc_mode_reset = 0;
666         timing->emc_mode_1 = 0;
667         timing->emc_mode_2 = 0;
668         timing->emc_mode_4 = 0;
669         timing->emc_cfg = emc_readl(EMC_CFG);
670         timing->rate = clk_get_rate_locked(emc) / 1000;
671 }
672
673 /* The EMC registers have shadow registers. When the EMC clock is updated
674  * in the clock controller, the shadow registers are copied to the active
675  * registers, allowing glitchless memory bus frequency changes.
676  * This function updates the shadow registers for a new clock frequency,
677  * and relies on the clock lock on the emc clock to avoid races between
678  * multiple frequency changes. In addition access lock prevents concurrent
679  * access to EMC registers from reading MRR registers */
680 int tegra_emc_set_rate(unsigned long rate)
681 {
682         int i;
683         u32 clk_setting;
684         const struct tegra11_emc_table *last_timing;
685         unsigned long flags;
686         s64 last_change_delay;
687
688         if (!tegra_emc_table)
689                 return -EINVAL;
690
691         /* Table entries specify rate in kHz */
692         rate = rate / 1000;
693
694         for (i = 0; i < tegra_emc_table_size; i++) {
695                 if (tegra_emc_clk_sel[i].input == NULL)
696                         continue;       /* invalid entry */
697
698                 if (tegra_emc_table[i].rate == rate)
699                         break;
700         }
701
702         if (i >= tegra_emc_table_size)
703                 return -EINVAL;
704
705         if (!emc_timing) {
706                 /* can not assume that boot timing matches dfs table even
707                    if boot frequency matches one of the table nodes */
708                 emc_get_timing(&start_timing);
709                 last_timing = &start_timing;
710         }
711         else
712                 last_timing = emc_timing;
713
714         clk_setting = tegra_emc_clk_sel[i].value;
715
716         last_change_delay = ktime_us_delta(ktime_get(), clkchange_time);
717         if ((last_change_delay >= 0) && (last_change_delay < clkchange_delay))
718                 udelay(clkchange_delay - (int)last_change_delay);
719
720         spin_lock_irqsave(&emc_access_lock, flags);
721         emc_set_clock(&tegra_emc_table[i], last_timing, clk_setting);
722         clkchange_time = ktime_get();
723         emc_timing = &tegra_emc_table[i];
724         spin_unlock_irqrestore(&emc_access_lock, flags);
725
726         emc_last_stats_update(i);
727
728         pr_debug("%s: rate %lu setting 0x%x\n", __func__, rate, clk_setting);
729
730         return 0;
731 }
732
733 long tegra_emc_round_rate(unsigned long rate)
734 {
735         int i;
736
737         if (!tegra_emc_table)
738                 return clk_get_rate_locked(emc); /* no table - no rate change */
739
740         if (!emc_enable)
741                 return -EINVAL;
742
743         pr_debug("%s: %lu\n", __func__, rate);
744
745         /* Table entries specify rate in kHz */
746         rate = rate / 1000;
747
748         for (i = 0; i < tegra_emc_table_size; i++) {
749                 if (tegra_emc_clk_sel[i].input == NULL)
750                         continue;       /* invalid entry */
751
752                 if (tegra_emc_table[i].rate >= rate) {
753                         pr_debug("%s: using %lu\n",
754                                  __func__, tegra_emc_table[i].rate);
755                         return tegra_emc_table[i].rate * 1000;
756                 }
757         }
758
759         return -EINVAL;
760 }
761
762 struct clk *tegra_emc_predict_parent(unsigned long rate, u32 *div_value)
763 {
764         int i;
765
766         if (!tegra_emc_table) {
767                 if (rate == clk_get_rate_locked(emc)) {
768                         *div_value = emc->div - 2;
769                         return emc->parent;
770                 }
771                 return NULL;
772         }
773
774         pr_debug("%s: %lu\n", __func__, rate);
775
776         /* Table entries specify rate in kHz */
777         rate = rate / 1000;
778
779         for (i = 0; i < tegra_emc_table_size; i++) {
780                 if (tegra_emc_table[i].rate == rate) {
781                         struct clk *p = tegra_emc_clk_sel[i].input;
782
783                         if (p && (tegra_emc_clk_sel[i].input_rate ==
784                                   clk_get_rate(p))) {
785                                 *div_value = (tegra_emc_clk_sel[i].value &
786                                         EMC_CLK_DIV_MASK) >> EMC_CLK_DIV_SHIFT;
787                                 return p;
788                         }
789                 }
790         }
791         return NULL;
792 }
793
794 bool tegra_emc_is_parent_ready(unsigned long rate, struct clk **parent,
795                 unsigned long *parent_rate, unsigned long *backup_rate)
796 {
797
798         int i;
799         struct clk *p = NULL;
800         unsigned long p_rate = 0;
801
802         if (!tegra_emc_table || !emc_enable)
803                 return true;
804
805         pr_debug("%s: %lu\n", __func__, rate);
806
807         /* Table entries specify rate in kHz */
808         rate = rate / 1000;
809
810         for (i = 0; i < tegra_emc_table_size; i++) {
811                 if (tegra_emc_table[i].rate == rate) {
812                         p = tegra_emc_clk_sel[i].input;
813                         if (!p)
814                                 continue;       /* invalid entry */
815
816                         p_rate = tegra_emc_clk_sel[i].input_rate;
817                         if (p_rate == clk_get_rate(p))
818                                 return true;
819                         break;
820                 }
821         }
822
823         /* Table match not found - "non existing parent" is ready */
824         if (!p)
825                 return true;
826
827         /*
828          * Table match found, but parent is not ready - continue search
829          * for backup rate: min rate above requested that has different
830          * parent source (since only pll_c is scaled and may not be ready,
831          * any other parent can provide backup)
832          */
833         *parent = p;
834         *parent_rate = p_rate;
835
836         for (i++; i < tegra_emc_table_size; i++) {
837                 p = tegra_emc_clk_sel[i].input;
838                 if (!p)
839                         continue;       /* invalid entry */
840
841                 if (p != (*parent)) {
842                         *backup_rate = tegra_emc_table[i].rate * 1000;
843                         return false;
844                 }
845         }
846
847         /* Parent is not ready, and no backup found */
848         *backup_rate = -EINVAL;
849         return false;
850 }
851
852 static inline const struct clk_mux_sel *get_emc_input(u32 val)
853 {
854         const struct clk_mux_sel *sel;
855
856         for (sel = emc->inputs; sel->input != NULL; sel++) {
857                 if (sel->value == val)
858                         break;
859         }
860         return sel;
861 }
862
863 static int find_matching_input(const struct tegra11_emc_table *table,
864                         struct clk *pll_c, struct emc_sel *emc_clk_sel)
865 {
866         u32 div_value = (table->src_sel_reg & EMC_CLK_DIV_MASK) >>
867                 EMC_CLK_DIV_SHIFT;
868         u32 src_value = (table->src_sel_reg & EMC_CLK_SOURCE_MASK) >>
869                 EMC_CLK_SOURCE_SHIFT;
870         unsigned long input_rate = 0;
871         unsigned long table_rate = table->rate * 1000; /* table rate in kHz */
872         const struct clk_mux_sel *sel = get_emc_input(src_value);
873
874         if (div_value & 0x1) {
875                 pr_warn("tegra: invalid odd divider for EMC rate %lu\n",
876                         table_rate);
877                 return -EINVAL;
878         }
879         if (!sel->input) {
880                 pr_warn("tegra: no matching input found for EMC rate %lu\n",
881                         table_rate);
882                 return -EINVAL;
883         }
884         if (div_value && (table->src_sel_reg & EMC_CLK_LOW_JITTER_ENABLE)) {
885                 pr_warn("tegra: invalid LJ path for EMC rate %lu\n",
886                         table_rate);
887                 return -EINVAL;
888         }
889         if (!(table->src_sel_reg & EMC_CLK_MC_SAME_FREQ) !=
890             !(MC_EMEM_ARB_MISC0_EMC_SAME_FREQ &
891               table->burst_regs[MC_EMEM_ARB_MISC0_INDEX])) {
892                 pr_warn("tegra: ambiguous EMC to MC ratio for EMC rate %lu\n",
893                         table_rate);
894                 return -EINVAL;
895         }
896
897         if (sel->input == pll_c) {
898                 /* PLLC is a scalable source */
899 #ifdef CONFIG_TEGRA_DUAL_CBUS
900                 input_rate = table_rate * (1 + div_value / 2);
901 #else
902                 pr_warn("tegra: %s cannot be used as EMC rate %lu source\n",
903                         sel->input->name, table_rate);
904                 return -EINVAL;
905 #endif
906         } else {
907                 /* all other sources are fixed, must exactly match the rate */
908                 input_rate = clk_get_rate(sel->input);
909                 if (input_rate != (table_rate * (1 + div_value / 2))) {
910                         pr_warn("tegra: %s rate %lu does not match EMC rate %lu\n",
911                                 sel->input->name, input_rate, table_rate);
912                         return -EINVAL;
913                 }
914         }
915
916         /* Get ready emc clock selection settings for this table rate */
917         emc_clk_sel->input = sel->input;
918         emc_clk_sel->input_rate = input_rate;
919         emc_clk_sel->value = table->src_sel_reg;
920
921         return 0;
922 }
923
924 static void adjust_emc_dvfs_table(const struct tegra11_emc_table *table,
925                                   int table_size)
926 {
927         int i, j;
928         unsigned long rate;
929
930         for (i = 0; i < MAX_DVFS_FREQS; i++) {
931                 int mv = emc->dvfs->millivolts[i];
932                 if (!mv)
933                         break;
934
935                 /* For each dvfs voltage find maximum supported rate;
936                    use 1MHz placeholder if not found */
937                 for (rate = 1000, j = 0; j < table_size; j++) {
938                         if (tegra_emc_clk_sel[j].input == NULL)
939                                 continue;       /* invalid entry */
940
941                         if ((mv >= table[j].emc_min_mv) &&
942                             (rate < table[j].rate))
943                                 rate = table[j].rate;
944                 }
945                 /* Table entries specify rate in kHz */
946                 emc->dvfs->freqs[i] = rate * 1000;
947         }
948 }
949
950 static int init_emc_table(const struct tegra11_emc_table *table, int table_size)
951 {
952         int i, mv;
953         u32 reg;
954         bool max_entry = false;
955         unsigned long boot_rate, max_rate;
956         struct clk *pll_c = tegra_get_clock_by_name("pll_c");
957
958         emc_stats.clkchange_count = 0;
959         spin_lock_init(&emc_stats.spinlock);
960         emc_stats.last_update = get_jiffies_64();
961         emc_stats.last_sel = TEGRA_EMC_TABLE_MAX_SIZE;
962
963         boot_rate = clk_get_rate(emc) / 1000;
964         max_rate = clk_get_max_rate(emc) / 1000;
965
966         if ((dram_type != DRAM_TYPE_DDR3) && (dram_type != DRAM_TYPE_LPDDR2)) {
967                 pr_err("tegra: not supported DRAM type %u\n", dram_type);
968                 return -ENODATA;
969         }
970
971         if (emc->parent != tegra_get_clock_by_name("pll_m")) {
972                 pr_err("tegra: boot parent %s is not supported by EMC DFS\n",
973                         emc->parent->name);
974                 return -ENODATA;
975         }
976
977         if (!table || !table_size) {
978                 pr_err("tegra: EMC DFS table is empty\n");
979                 return -ENODATA;
980         }
981
982         tegra_emc_table_size = min(table_size, TEGRA_EMC_TABLE_MAX_SIZE);
983         switch (table[0].rev) {
984         case 0x40:
985         case 0x41:
986                 start_timing.burst_regs_num = table[0].burst_regs_num;
987                 start_timing.emc_trimmers_num = table[0].emc_trimmers_num;
988                 break;
989         default:
990                 pr_err("tegra: invalid EMC DFS table: unknown rev 0x%x\n",
991                         table[0].rev);
992                 return -ENODATA;
993         }
994
995         /* Match EMC source/divider settings with table entries */
996         for (i = 0; i < tegra_emc_table_size; i++) {
997                 unsigned long table_rate = table[i].rate;
998
999                 /* Skip "no-rate" entry, or entry violating ascending order */
1000                 if (!table_rate ||
1001                     (i && (table_rate <= table[i-1].rate)))
1002                         continue;
1003
1004                 BUG_ON(table[i].rev != table[0].rev);
1005
1006                 if (find_matching_input(&table[i], pll_c,
1007                                         &tegra_emc_clk_sel[i]))
1008                         continue;
1009
1010                 if (table_rate == boot_rate)
1011                         emc_stats.last_sel = i;
1012
1013                 if (table_rate == max_rate)
1014                         max_entry = true;
1015         }
1016
1017         /* Validate EMC rate and voltage limits */
1018         if (!max_entry) {
1019                 pr_err("tegra: invalid EMC DFS table: entry for max rate"
1020                        " %lu kHz is not found\n", max_rate);
1021                 return -ENODATA;
1022         }
1023
1024         tegra_emc_table = table;
1025
1026         if (emc->dvfs) {
1027                 adjust_emc_dvfs_table(tegra_emc_table, tegra_emc_table_size);
1028                 mv = tegra_dvfs_predict_millivolts(emc, max_rate * 1000);
1029                 if ((mv <= 0) || (mv > emc->dvfs->max_millivolts)) {
1030                         tegra_emc_table = NULL;
1031                         pr_err("tegra: invalid EMC DFS table: maximum rate %lu"
1032                                " kHz does not match nominal voltage %d\n",
1033                                max_rate, emc->dvfs->max_millivolts);
1034                         return -ENODATA;
1035                 }
1036         }
1037
1038         pr_info("tegra: validated EMC DFS table\n");
1039
1040         /* Configure clock change mode according to dram type */
1041         reg = emc_readl(EMC_CFG_2) & (~EMC_CFG_2_MODE_MASK);
1042         reg |= ((dram_type == DRAM_TYPE_LPDDR2) ? EMC_CFG_2_PD_MODE :
1043                 EMC_CFG_2_SREF_MODE) << EMC_CFG_2_MODE_SHIFT;
1044         emc_writel(reg, EMC_CFG_2);
1045         return 0;
1046 }
1047
1048 static int __devinit tegra11_emc_probe(struct platform_device *pdev)
1049 {
1050         struct tegra11_emc_pdata *pdata;
1051         struct resource *res;
1052
1053         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1054         if (!res) {
1055                 dev_err(&pdev->dev, "missing register base\n");
1056                 return -ENOMEM;
1057         }
1058
1059         pdata = pdev->dev.platform_data;
1060         if (!pdata) {
1061                 dev_err(&pdev->dev, "missing platform data\n");
1062                 return -ENODATA;
1063         }
1064
1065         return init_emc_table(pdata->tables, pdata->num_tables);
1066 }
1067
1068 static struct platform_driver tegra11_emc_driver = {
1069         .driver         = {
1070                 .name   = "tegra-emc",
1071                 .owner  = THIS_MODULE,
1072         },
1073         .probe          = tegra11_emc_probe,
1074 };
1075
1076 int __init tegra11_emc_init(void)
1077 {
1078         return platform_driver_register(&tegra11_emc_driver);
1079 }
1080
1081 void tegra_emc_timing_invalidate(void)
1082 {
1083         emc_timing = NULL;
1084 }
1085
1086 void tegra_emc_dram_type_init(struct clk *c)
1087 {
1088         emc = c;
1089
1090         dram_type = (emc_readl(EMC_FBIO_CFG5) &
1091                      EMC_CFG5_TYPE_MASK) >> EMC_CFG5_TYPE_SHIFT;
1092
1093         dram_dev_num = (mc_readl(MC_EMEM_ADR_CFG) & 0x1) + 1; /* 2 dev max */
1094 }
1095
1096 int tegra_emc_get_dram_type(void)
1097 {
1098         return dram_type;
1099 }
1100
1101 static u32 soc_to_dram_bit_swap(u32 soc_val, u32 dram_mask, u32 dram_shift)
1102 {
1103         int bit;
1104         u32 dram_val = 0;
1105
1106         /* tegra clocks definitions use shifted mask always */
1107         if (!dram_to_soc_bit_map)
1108                 return soc_val & dram_mask;
1109
1110         for (bit = dram_shift; bit < 32; bit++) {
1111                 u32 dram_bit_mask = 0x1 << bit;
1112                 u32 soc_bit_mask = dram_to_soc_bit_map[bit];
1113
1114                 if (!(dram_bit_mask & dram_mask))
1115                         break;
1116
1117                 if (soc_bit_mask & soc_val)
1118                         dram_val |= dram_bit_mask;
1119         }
1120
1121         return dram_val;
1122 }
1123
1124 static int emc_read_mrr(int dev, int addr)
1125 {
1126         int ret;
1127         u32 val;
1128
1129         if (dram_type != DRAM_TYPE_LPDDR2)
1130                 return -ENODEV;
1131
1132         ret = wait_for_update(EMC_STATUS, EMC_STATUS_MRR_DIVLD, false);
1133         if (ret)
1134                 return ret;
1135
1136         val = dev ? DRAM_DEV_SEL_1 : DRAM_DEV_SEL_0;
1137         val |= (addr << EMC_MRR_MA_SHIFT) & EMC_MRR_MA_MASK;
1138         emc_writel(val, EMC_MRR);
1139
1140         ret = wait_for_update(EMC_STATUS, EMC_STATUS_MRR_DIVLD, true);
1141         if (ret)
1142                 return ret;
1143
1144         val = emc_readl(EMC_MRR) & EMC_MRR_DATA_MASK;
1145         return val;
1146 }
1147
1148 int tegra_emc_get_dram_temperature(void)
1149 {
1150         int mr4;
1151         unsigned long flags;
1152
1153         spin_lock_irqsave(&emc_access_lock, flags);
1154
1155         mr4 = emc_read_mrr(0, 4);
1156         if (IS_ERR_VALUE(mr4)) {
1157                 spin_unlock_irqrestore(&emc_access_lock, flags);
1158                 return mr4;
1159         }
1160         spin_unlock_irqrestore(&emc_access_lock, flags);
1161
1162         mr4 = soc_to_dram_bit_swap(
1163                 mr4, LPDDR2_MR4_TEMP_MASK, LPDDR2_MR4_TEMP_SHIFT);
1164         return mr4;
1165 }
1166
1167 #ifdef CONFIG_DEBUG_FS
1168
1169 static struct dentry *emc_debugfs_root;
1170
1171 static int emc_stats_show(struct seq_file *s, void *data)
1172 {
1173         int i;
1174
1175         emc_last_stats_update(TEGRA_EMC_TABLE_MAX_SIZE);
1176
1177         seq_printf(s, "%-10s %-10s \n", "rate kHz", "time");
1178         for (i = 0; i < tegra_emc_table_size; i++) {
1179                 if (tegra_emc_clk_sel[i].input == NULL)
1180                         continue;       /* invalid entry */
1181
1182                 seq_printf(s, "%-10lu %-10llu \n", tegra_emc_table[i].rate,
1183                            cputime64_to_clock_t(emc_stats.time_at_clock[i]));
1184         }
1185         seq_printf(s, "%-15s %llu\n", "transitions:",
1186                    emc_stats.clkchange_count);
1187         seq_printf(s, "%-15s %llu\n", "time-stamp:",
1188                    cputime64_to_clock_t(emc_stats.last_update));
1189
1190         return 0;
1191 }
1192
1193 static int emc_stats_open(struct inode *inode, struct file *file)
1194 {
1195         return single_open(file, emc_stats_show, inode->i_private);
1196 }
1197
1198 static const struct file_operations emc_stats_fops = {
1199         .open           = emc_stats_open,
1200         .read           = seq_read,
1201         .llseek         = seq_lseek,
1202         .release        = single_release,
1203 };
1204
1205 static int dram_temperature_get(void *data, u64 *val)
1206 {
1207         *val = tegra_emc_get_dram_temperature();
1208         return 0;
1209 }
1210 DEFINE_SIMPLE_ATTRIBUTE(dram_temperature_fops, dram_temperature_get,
1211                         NULL, "%lld\n");
1212
1213 static int efficiency_get(void *data, u64 *val)
1214 {
1215         *val = tegra_emc_bw_efficiency;
1216         return 0;
1217 }
1218 static int efficiency_set(void *data, u64 val)
1219 {
1220         tegra_emc_bw_efficiency = (val > 100) ? 100 : val;
1221         if (emc)
1222                 tegra_clk_shared_bus_update(emc);
1223
1224         return 0;
1225 }
1226 DEFINE_SIMPLE_ATTRIBUTE(efficiency_fops, efficiency_get,
1227                         efficiency_set, "%llu\n");
1228
1229 static int __init tegra_emc_debug_init(void)
1230 {
1231         if (!tegra_emc_table)
1232                 return 0;
1233
1234         emc_debugfs_root = debugfs_create_dir("tegra_emc", NULL);
1235         if (!emc_debugfs_root)
1236                 return -ENOMEM;
1237
1238         if (!debugfs_create_file(
1239                 "stats", S_IRUGO, emc_debugfs_root, NULL, &emc_stats_fops))
1240                 goto err_out;
1241
1242         if (!debugfs_create_u32("clkchange_delay", S_IRUGO | S_IWUSR,
1243                 emc_debugfs_root, (u32 *)&clkchange_delay))
1244                 goto err_out;
1245
1246         if (!debugfs_create_file("dram_temperature", S_IRUGO, emc_debugfs_root,
1247                                  NULL, &dram_temperature_fops))
1248                 goto err_out;
1249
1250         if (!debugfs_create_file("efficiency", S_IRUGO | S_IWUSR,
1251                                  emc_debugfs_root, NULL, &efficiency_fops))
1252                 goto err_out;
1253
1254         return 0;
1255
1256 err_out:
1257         debugfs_remove_recursive(emc_debugfs_root);
1258         return -ENOMEM;
1259 }
1260
1261 late_initcall(tegra_emc_debug_init);
1262 #endif