ARM: tegra11: clock: Add dummy EMC ccfifo write
[linux-2.6.git] / arch / arm / mach-tegra / tegra11_emc.c
1 /*
2  * arch/arm/mach-tegra/tegra11_emc.c
3  *
4  * Copyright (C) 2011-2012 NVIDIA Corporation
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  *
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/clk.h>
23 #include <linux/err.h>
24 #include <linux/io.h>
25 #include <linux/module.h>
26 #include <linux/delay.h>
27 #include <linux/platform_device.h>
28 #include <linux/platform_data/tegra_emc.h>
29 #include <linux/debugfs.h>
30 #include <linux/seq_file.h>
31 #include <linux/hrtimer.h>
32
33 #include <asm/cputime.h>
34
35 #include <mach/iomap.h>
36
37 #include "clock.h"
38 #include "dvfs.h"
39 #include "tegra11_emc.h"
40
41 #ifdef CONFIG_TEGRA_EMC_SCALING_ENABLE
42 static bool emc_enable = true;
43 #else
44 static bool emc_enable;
45 #endif
46 module_param(emc_enable, bool, 0644);
47
48 u8 tegra_emc_bw_efficiency = 100;
49
50 #define PLL_C_DIRECT_FLOOR              333500000
51 #define EMC_STATUS_UPDATE_TIMEOUT       100
52 #define TEGRA_EMC_TABLE_MAX_SIZE        16
53
54 enum {
55         DLL_CHANGE_NONE = 0,
56         DLL_CHANGE_ON,
57         DLL_CHANGE_OFF,
58 };
59
60 #define EMC_CLK_DIV_SHIFT               0
61 #define EMC_CLK_DIV_MAX_VALUE           0xFF
62 #define EMC_CLK_DIV_MASK                (0xFF << EMC_CLK_DIV_SHIFT)
63 #define EMC_CLK_SOURCE_SHIFT            29
64 #define EMC_CLK_SOURCE_MAX_VALUE        3
65 #define EMC_CLK_LOW_JITTER_ENABLE       (0x1 << 31)
66 #define EMC_CLK_MC_SAME_FREQ            (0x1 << 16)
67
68 /* FIXME: actual Tegar11 list */
69 #define BURST_REG_LIST \
70         DEFINE_REG(TEGRA_EMC_BASE, EMC_RC),                     \
71         DEFINE_REG(TEGRA_EMC_BASE, EMC_RFC),                    \
72         DEFINE_REG(TEGRA_EMC_BASE, EMC_RFC_SLR),                \
73         DEFINE_REG(TEGRA_EMC_BASE, EMC_RAS),                    \
74         DEFINE_REG(TEGRA_EMC_BASE, EMC_RP),                     \
75         DEFINE_REG(TEGRA_EMC_BASE, EMC_R2W),                    \
76         DEFINE_REG(TEGRA_EMC_BASE, EMC_W2R),                    \
77         DEFINE_REG(TEGRA_EMC_BASE, EMC_R2P),                    \
78         DEFINE_REG(TEGRA_EMC_BASE, EMC_W2P),                    \
79         DEFINE_REG(TEGRA_EMC_BASE, EMC_RD_RCD),                 \
80         DEFINE_REG(TEGRA_EMC_BASE, EMC_WR_RCD),                 \
81         DEFINE_REG(TEGRA_EMC_BASE, EMC_RRD),                    \
82         DEFINE_REG(TEGRA_EMC_BASE, EMC_REXT),                   \
83         DEFINE_REG(TEGRA_EMC_BASE, EMC_WEXT),                   \
84         DEFINE_REG(TEGRA_EMC_BASE, EMC_WDV),                    \
85         DEFINE_REG(TEGRA_EMC_BASE, EMC_WDV_MASK),               \
86         DEFINE_REG(TEGRA_EMC_BASE, EMC_IBDLY),                  \
87         DEFINE_REG(TEGRA_EMC_BASE, EMC_PUTERM_EXTRA),           \
88         DEFINE_REG(TEGRA_EMC_BASE, EMC_CDB_CNTL_2),             \
89         DEFINE_REG(TEGRA_EMC_BASE, EMC_QRST),                   \
90         DEFINE_REG(TEGRA_EMC_BASE, EMC_RDV_MASK),               \
91         DEFINE_REG(TEGRA_EMC_BASE, EMC_REFRESH),                \
92         DEFINE_REG(TEGRA_EMC_BASE, EMC_BURST_REFRESH_NUM),      \
93         DEFINE_REG(TEGRA_EMC_BASE, EMC_PRE_REFRESH_REQ_CNT),    \
94         DEFINE_REG(TEGRA_EMC_BASE, EMC_PDEX2WR),                \
95         DEFINE_REG(TEGRA_EMC_BASE, EMC_PDEX2RD),                \
96         DEFINE_REG(TEGRA_EMC_BASE, EMC_PCHG2PDEN),              \
97         DEFINE_REG(TEGRA_EMC_BASE, EMC_ACT2PDEN),               \
98         DEFINE_REG(TEGRA_EMC_BASE, EMC_AR2PDEN),                \
99         DEFINE_REG(TEGRA_EMC_BASE, EMC_RW2PDEN),                \
100         DEFINE_REG(TEGRA_EMC_BASE, EMC_TXSR),                   \
101         DEFINE_REG(TEGRA_EMC_BASE, EMC_TXSRDLL),                \
102         DEFINE_REG(TEGRA_EMC_BASE, EMC_TCKE),                   \
103         DEFINE_REG(TEGRA_EMC_BASE, EMC_TCKESR),                 \
104         DEFINE_REG(TEGRA_EMC_BASE, EMC_TPD),                    \
105         DEFINE_REG(TEGRA_EMC_BASE, EMC_TFAW),                   \
106         DEFINE_REG(TEGRA_EMC_BASE, EMC_TRPAB),                  \
107         DEFINE_REG(TEGRA_EMC_BASE, EMC_TCLKSTABLE),             \
108         DEFINE_REG(TEGRA_EMC_BASE, EMC_TCLKSTOP),               \
109         DEFINE_REG(TEGRA_EMC_BASE, EMC_TREFBW),                 \
110         DEFINE_REG(TEGRA_EMC_BASE, EMC_QUSE_EXTRA),             \
111         DEFINE_REG(TEGRA_EMC_BASE, EMC_ODT_WRITE),              \
112         DEFINE_REG(TEGRA_EMC_BASE, EMC_ODT_READ),               \
113         DEFINE_REG(TEGRA_EMC_BASE, EMC_FBIO_CFG5),              \
114         DEFINE_REG(TEGRA_EMC_BASE, EMC_CFG_DIG_DLL),            \
115         DEFINE_REG(TEGRA_EMC_BASE, EMC_CFG_DIG_DLL_PERIOD),     \
116         DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_DQS4),         \
117         DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_DQS5),         \
118         DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_DQS6),         \
119         DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_DQS7),         \
120         DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_QUSE4),        \
121         DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_QUSE5),        \
122         DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_QUSE6),        \
123         DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_XFORM_QUSE7),        \
124         DEFINE_REG(TEGRA_EMC_BASE, EMC_DLI_TRIM_TXDQS4),        \
125         DEFINE_REG(TEGRA_EMC_BASE, EMC_DLI_TRIM_TXDQS5),        \
126         DEFINE_REG(TEGRA_EMC_BASE, EMC_DLI_TRIM_TXDQS6),        \
127         DEFINE_REG(TEGRA_EMC_BASE, EMC_DLI_TRIM_TXDQS7),        \
128         DEFINE_REG(TEGRA_EMC_BASE, EMC_XM2CMDPADCTRL),          \
129         DEFINE_REG(TEGRA_EMC_BASE, EMC_XM2CMDPADCTRL4),         \
130         DEFINE_REG(TEGRA_EMC_BASE, EMC_XM2DQSPADCTRL2),         \
131         DEFINE_REG(TEGRA_EMC_BASE, EMC_XM2DQPADCTRL2),          \
132         DEFINE_REG(TEGRA_EMC_BASE, EMC_XM2CLKPADCTRL),          \
133         DEFINE_REG(TEGRA_EMC_BASE, EMC_XM2COMPPADCTRL),         \
134         DEFINE_REG(TEGRA_EMC_BASE, EMC_XM2VTTGENPADCTRL),       \
135         DEFINE_REG(TEGRA_EMC_BASE, EMC_XM2VTTGENPADCTRL2),      \
136         DEFINE_REG(TEGRA_EMC_BASE, EMC_DSR_VTTGEN_DRV),         \
137         DEFINE_REG(TEGRA_EMC_BASE, EMC_TXDSRVTTGEN),            \
138         DEFINE_REG(TEGRA_EMC_BASE, EMC_FBIO_SPARE),             \
139         DEFINE_REG(TEGRA_EMC_BASE, EMC_CTT_TERM_CTRL),          \
140         DEFINE_REG(TEGRA_EMC_BASE, EMC_ZCAL_INTERVAL),          \
141         DEFINE_REG(TEGRA_EMC_BASE, EMC_ZCAL_WAIT_CNT),          \
142         DEFINE_REG(TEGRA_EMC_BASE, EMC_MRS_WAIT_CNT),           \
143         DEFINE_REG(TEGRA_EMC_BASE, EMC_MRS_WAIT_CNT2),          \
144         DEFINE_REG(TEGRA_EMC_BASE, EMC_AUTO_CAL_CONFIG2),       \
145         DEFINE_REG(TEGRA_EMC_BASE, EMC_AUTO_CAL_CONFIG3),       \
146         DEFINE_REG(TEGRA_EMC_BASE, EMC_CTT),                    \
147         DEFINE_REG(TEGRA_EMC_BASE, EMC_CTT_DURATION),           \
148         DEFINE_REG(TEGRA_EMC_BASE, EMC_DYN_SELF_REF_CONTROL),   \
149         DEFINE_REG(TEGRA_EMC_BASE, EMC_CA_TRAINING_TIMING_CNTL1),       \
150         DEFINE_REG(TEGRA_EMC_BASE, EMC_CA_TRAINING_TIMING_CNTL2),       \
151                                                                         \
152         DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_CFG),             \
153         DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_OUTSTANDING_REQ), \
154         DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_RCD),      \
155         DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_RP),       \
156         DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_RC),       \
157         DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_RAS),      \
158         DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_FAW),      \
159         DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_RRD),      \
160         DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_RAP2PRE),  \
161         DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_WAP2PRE),  \
162         DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_R2R),      \
163         DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_W2W),      \
164         DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_R2W),      \
165         DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_W2R),      \
166         DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_DA_TURNS),        \
167         DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_DA_COVERS),       \
168         DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_MISC0),           \
169         DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_RING1_THROTTLE),
170
171 #define BURST_UP_DOWN_REG_LIST \
172         DEFINE_REG(TEGRA_MC_BASE, MC_PTSA_GRANT_DECREMENT),     \
173         DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_G2_0),   \
174         DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_G2_1),   \
175         DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_NV_0),   \
176         DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_NV2_0),  \
177         DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_NV_2),   \
178         DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_NV_1),   \
179         DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_NV2_1),  \
180         DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_NV_3),   \
181         DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_EPP_0),  \
182         DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_EPP_1),
183
184 #define EMC_TRIMMERS_REG_LIST \
185         DEFINE_REG(0, EMC_CDB_CNTL_1),                          \
186         DEFINE_REG(0, EMC_FBIO_CFG6),                           \
187         DEFINE_REG(0, EMC_QUSE),                                \
188         DEFINE_REG(0, EMC_EINPUT),                              \
189         DEFINE_REG(0, EMC_EINPUT_DURATION),                     \
190         DEFINE_REG(0, EMC_DLL_XFORM_DQS0),                      \
191         DEFINE_REG(0, EMC_QSAFE),                               \
192         DEFINE_REG(0, EMC_DLL_XFORM_QUSE0),                     \
193         DEFINE_REG(0, EMC_RDV),                                 \
194         DEFINE_REG(0, EMC_XM2DQSPADCTRL4),                      \
195         DEFINE_REG(0, EMC_XM2DQSPADCTRL3),                      \
196         DEFINE_REG(0, EMC_DLL_XFORM_DQ0),                       \
197         DEFINE_REG(0, EMC_AUTO_CAL_CONFIG),                     \
198         DEFINE_REG(0, EMC_DLL_XFORM_ADDR0),                     \
199         DEFINE_REG(0, EMC_XM2CLKPADCTRL2),                      \
200         DEFINE_REG(0, EMC_DLI_TRIM_TXDQS0),                     \
201         DEFINE_REG(0, EMC_DLL_XFORM_ADDR1),                     \
202         DEFINE_REG(0, EMC_DLL_XFORM_ADDR2),                     \
203         DEFINE_REG(0, EMC_DLL_XFORM_DQS1),                      \
204         DEFINE_REG(0, EMC_DLL_XFORM_DQS2),                      \
205         DEFINE_REG(0, EMC_DLL_XFORM_DQS3),                      \
206         DEFINE_REG(0, EMC_DLL_XFORM_DQ1),                       \
207         DEFINE_REG(0, EMC_DLL_XFORM_DQ2),                       \
208         DEFINE_REG(0, EMC_DLL_XFORM_DQ3),                       \
209         DEFINE_REG(0, EMC_DLI_TRIM_TXDQS1),                     \
210         DEFINE_REG(0, EMC_DLI_TRIM_TXDQS2),                     \
211         DEFINE_REG(0, EMC_DLI_TRIM_TXDQS3),                     \
212         DEFINE_REG(0, EMC_DLL_XFORM_QUSE1),                     \
213         DEFINE_REG(0, EMC_DLL_XFORM_QUSE2),                     \
214         DEFINE_REG(0, EMC_DLL_XFORM_QUSE3),
215
216
217 #define DEFINE_REG(base, reg) ((base) ? (IO_ADDRESS((base)) + (reg)) : 0)
218 static const void __iomem *burst_reg_addr[TEGRA11_EMC_MAX_NUM_REGS] = {
219         BURST_REG_LIST
220 };
221 #ifndef EMULATE_CLOCK_SWITCH
222 static const void __iomem *burst_up_down_reg_addr[TEGRA11_EMC_MAX_NUM_REGS] = {
223         BURST_UP_DOWN_REG_LIST
224 };
225 #endif
226 #undef DEFINE_REG
227
228
229 #define DEFINE_REG(base, reg) (reg)
230 #ifndef EMULATE_CLOCK_SWITCH
231 static const u32 emc_trimmer_offs[TEGRA11_EMC_MAX_NUM_REGS] = {
232         EMC_TRIMMERS_REG_LIST
233 };
234 #endif
235 #undef DEFINE_REG
236
237
238 #define DEFINE_REG(base, reg)   reg##_INDEX
239 enum {
240         BURST_REG_LIST
241 };
242 #undef DEFINE_REG
243
244 #define DEFINE_REG(base, reg)   reg##_TRIM_INDEX
245 enum {
246         EMC_TRIMMERS_REG_LIST
247 };
248 #undef DEFINE_REG
249
250
251 struct emc_sel {
252         struct clk      *input;
253         u32             value;
254         unsigned long   input_rate;
255 };
256 static struct emc_sel tegra_emc_clk_sel[TEGRA_EMC_TABLE_MAX_SIZE];
257 static struct tegra11_emc_table start_timing;
258 static const struct tegra11_emc_table *emc_timing;
259
260 static ktime_t clkchange_time;
261 static int clkchange_delay = 100;
262
263 static const u32 *dram_to_soc_bit_map;
264 static const struct tegra11_emc_table *tegra_emc_table;
265 static int tegra_emc_table_size;
266
267 static u32 dram_dev_num;
268 static u32 dram_type = -1;
269
270 static struct clk *emc;
271
272 static struct {
273         cputime64_t time_at_clock[TEGRA_EMC_TABLE_MAX_SIZE];
274         int last_sel;
275         u64 last_update;
276         u64 clkchange_count;
277         spinlock_t spinlock;
278 } emc_stats;
279
280 static DEFINE_SPINLOCK(emc_access_lock);
281
282 static void __iomem *emc_base = IO_ADDRESS(TEGRA_EMC_BASE);
283 static void __iomem *emc0_base = IO_ADDRESS(TEGRA_EMC0_BASE);
284 static void __iomem *emc1_base = IO_ADDRESS(TEGRA_EMC1_BASE);
285 static void __iomem *mc_base = IO_ADDRESS(TEGRA_MC_BASE);
286 static void __iomem *clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
287
288 static inline void emc_writel(u32 val, unsigned long addr)
289 {
290         writel(val, (u32)emc_base + addr);
291 }
292 static inline void emc0_writel(u32 val, unsigned long addr)
293 {
294         writel(val, (u32)emc0_base + addr);
295 }
296 static inline void emc1_writel(u32 val, unsigned long addr)
297 {
298         writel(val, (u32)emc1_base + addr);
299 }
300 static inline u32 emc_readl(unsigned long addr)
301 {
302         return readl((u32)emc_base + addr);
303 }
304 static inline void mc_writel(u32 val, unsigned long addr)
305 {
306         writel(val, (u32)mc_base + addr);
307 }
308 static inline u32 mc_readl(unsigned long addr)
309 {
310         return readl((u32)mc_base + addr);
311 }
312
313 static inline void ccfifo_writel(u32 val, unsigned long addr)
314 {
315         writel(val, (u32)emc_base + EMC_CCFIFO_DATA);
316         writel(addr, (u32)emc_base + EMC_CCFIFO_ADDR);
317 }
318
319 static void emc_last_stats_update(int last_sel)
320 {
321         unsigned long flags;
322         u64 cur_jiffies = get_jiffies_64();
323
324         spin_lock_irqsave(&emc_stats.spinlock, flags);
325
326         if (emc_stats.last_sel < TEGRA_EMC_TABLE_MAX_SIZE)
327                 emc_stats.time_at_clock[emc_stats.last_sel] =
328                         emc_stats.time_at_clock[emc_stats.last_sel] +
329                         (cur_jiffies - emc_stats.last_update);
330
331         emc_stats.last_update = cur_jiffies;
332
333         if (last_sel < TEGRA_EMC_TABLE_MAX_SIZE) {
334                 emc_stats.clkchange_count++;
335                 emc_stats.last_sel = last_sel;
336         }
337         spin_unlock_irqrestore(&emc_stats.spinlock, flags);
338 }
339
340 static int wait_for_update(u32 status_reg, u32 bit_mask, bool updated_state)
341 {
342         int i;
343         for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; i++) {
344                 if (!!(emc_readl(status_reg) & bit_mask) == updated_state)
345                         return 0;
346                 udelay(1);
347         }
348         return -ETIMEDOUT;
349 }
350
351 static inline void emc_timing_update(void)
352 {
353         int err;
354
355         emc_writel(0x1, EMC_TIMING_CONTROL);
356         err = wait_for_update(EMC_STATUS,
357                               EMC_STATUS_TIMING_UPDATE_STALLED, false);
358         if (err) {
359                 pr_err("%s: timing update error: %d", __func__, err);
360                 BUG();
361         }
362 }
363
364 static inline void auto_cal_disable(void)
365 {
366         int err;
367
368         emc_writel(0, EMC_AUTO_CAL_INTERVAL);
369         err = wait_for_update(EMC_AUTO_CAL_STATUS,
370                               EMC_AUTO_CAL_STATUS_ACTIVE, false);
371         if (err) {
372                 pr_err("%s: disable auto-cal error: %d", __func__, err);
373                 BUG();
374         }
375 }
376
377 static inline bool dqs_preset(const struct tegra11_emc_table *next_timing,
378                               const struct tegra11_emc_table *last_timing)
379 {
380         bool ret = false;
381
382 #define DQS_SET(reg, bit)                                                     \
383         do {                                                                  \
384                 if ((next_timing->burst_regs[EMC_##reg##_INDEX] &             \
385                      EMC_##reg##_##bit##_ENABLE) &&                           \
386                     (!(last_timing->burst_regs[EMC_##reg##_INDEX] &           \
387                        EMC_##reg##_##bit##_ENABLE)))   {                      \
388                         emc_writel(last_timing->burst_regs[EMC_##reg##_INDEX] \
389                                    | EMC_##reg##_##bit##_ENABLE, EMC_##reg);  \
390                         ret = true;                                           \
391                 }                                                             \
392         } while (0)
393
394
395 #define DQS_SET_TRIM(reg, bit, ch)                                             \
396         do {                                                                   \
397                 if ((next_timing->emc_trimmers_##ch[EMC_##reg##_TRIM_INDEX]    \
398                      & EMC_##reg##_##bit##_ENABLE) &&                          \
399                     (!(last_timing->emc_trimmers_##ch[EMC_##reg##_TRIM_INDEX]  \
400                        & EMC_##reg##_##bit##_ENABLE)))   {                     \
401                         emc##ch##_writel(last_timing->emc_trimmers_##ch[EMC_##reg##_TRIM_INDEX] \
402                                    | EMC_##reg##_##bit##_ENABLE, EMC_##reg);   \
403                         ret = true;                                            \
404                 }                                                              \
405         } while (0)
406
407         DQS_SET(XM2DQSPADCTRL2, VREF);
408         DQS_SET_TRIM(XM2DQSPADCTRL3, VREF, 0);
409         DQS_SET_TRIM(XM2DQSPADCTRL3, VREF, 1);
410
411         return ret;
412 }
413
414 static inline void overwrite_mrs_wait_cnt(
415         const struct tegra11_emc_table *next_timing,
416         bool zcal_long)
417 {
418         u32 reg;
419         u32 cnt = 512;
420
421         /* For ddr3 when DLL is re-started: overwrite EMC DFS table settings
422            for MRS_WAIT_LONG with maximum of MRS_WAIT_SHORT settings and
423            expected operation length. Reduce the latter by the overlapping
424            zq-calibration, if any */
425         if (zcal_long)
426                 cnt -= dram_dev_num * 256;
427
428         reg = (next_timing->burst_regs[EMC_MRS_WAIT_CNT_INDEX] &
429                 EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK) >>
430                 EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT;
431         if (cnt < reg)
432                 cnt = reg;
433
434         reg = (next_timing->burst_regs[EMC_MRS_WAIT_CNT_INDEX] &
435                 (~EMC_MRS_WAIT_CNT_LONG_WAIT_MASK));
436         reg |= (cnt << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT) &
437                 EMC_MRS_WAIT_CNT_LONG_WAIT_MASK;
438
439         emc_writel(reg, EMC_MRS_WAIT_CNT);
440 }
441
442 static inline int get_dll_change(const struct tegra11_emc_table *next_timing,
443                                  const struct tegra11_emc_table *last_timing)
444 {
445         bool next_dll_enabled = !(next_timing->emc_mode_1 & 0x1);
446         bool last_dll_enabled = !(last_timing->emc_mode_1 & 0x1);
447
448         if (next_dll_enabled == last_dll_enabled)
449                 return DLL_CHANGE_NONE;
450         else if (next_dll_enabled)
451                 return DLL_CHANGE_ON;
452         else
453                 return DLL_CHANGE_OFF;
454 }
455
456 static inline void set_dram_mode(const struct tegra11_emc_table *next_timing,
457                                  const struct tegra11_emc_table *last_timing,
458                                  int dll_change)
459 {
460         if (dram_type == DRAM_TYPE_DDR3) {
461                 /* first mode_1, then mode_2, then mode_reset*/
462                 if (next_timing->emc_mode_1 != last_timing->emc_mode_1)
463                         ccfifo_writel(next_timing->emc_mode_1, EMC_EMRS);
464                 if (next_timing->emc_mode_2 != last_timing->emc_mode_2)
465                         ccfifo_writel(next_timing->emc_mode_2, EMC_EMRS2);
466
467                 if ((next_timing->emc_mode_reset !=
468                      last_timing->emc_mode_reset) ||
469                     (dll_change == DLL_CHANGE_ON)) {
470                         u32 reg = next_timing->emc_mode_reset &
471                                 (~EMC_MODE_SET_DLL_RESET);
472                         if (dll_change == DLL_CHANGE_ON) {
473                                 reg |= EMC_MODE_SET_DLL_RESET;
474                                 reg |= EMC_MODE_SET_LONG_CNT;
475                         }
476                         ccfifo_writel(reg, EMC_MRS);
477                 }
478         } else {
479                 /* first mode_2, then mode_1; mode_reset is not applicable */
480                 if (next_timing->emc_mode_2 != last_timing->emc_mode_2)
481                         ccfifo_writel(next_timing->emc_mode_2, EMC_MRW2);
482                 if (next_timing->emc_mode_1 != last_timing->emc_mode_1)
483                         ccfifo_writel(next_timing->emc_mode_1, EMC_MRW);
484                 if (next_timing->emc_mode_4 != last_timing->emc_mode_4)
485                         ccfifo_writel(next_timing->emc_mode_4, EMC_MRW4);
486         }
487 }
488
489 static inline void do_clock_change(u32 clk_setting)
490 {
491         int err;
492
493         mc_readl(MC_EMEM_ADR_CFG);      /* completes prev writes */
494         writel(clk_setting, (u32)clk_base + emc->reg);
495         readl((u32)clk_base + emc->reg);/* completes prev write */
496
497         err = wait_for_update(EMC_INTSTATUS,
498                               EMC_INTSTATUS_CLKCHANGE_COMPLETE, true);
499         if (err) {
500                 pr_err("%s: clock change completion error: %d", __func__, err);
501                 BUG();
502         }
503 }
504
505 static noinline void emc_set_clock(const struct tegra11_emc_table *next_timing,
506                                    const struct tegra11_emc_table *last_timing,
507                                    u32 clk_setting)
508 {
509 #ifndef EMULATE_CLOCK_SWITCH
510         int i, dll_change, pre_wait;
511         bool dyn_sref_enabled, vref_cal_toggle, zcal_long;
512
513         u32 emc_cfg_reg = emc_readl(EMC_CFG);
514
515         dyn_sref_enabled = emc_cfg_reg & EMC_CFG_DYN_SREF_ENABLE;
516         dll_change = get_dll_change(next_timing, last_timing);
517         zcal_long = (next_timing->burst_regs[EMC_ZCAL_INTERVAL_INDEX] != 0) &&
518                 (last_timing->burst_regs[EMC_ZCAL_INTERVAL_INDEX] == 0);
519
520         /* FIXME: remove steps enumeration below? */
521
522         /* 1. clear clkchange_complete interrupts */
523         emc_writel(EMC_INTSTATUS_CLKCHANGE_COMPLETE, EMC_INTSTATUS);
524
525         /* 2. disable dynamic self-refresh and preset dqs vref, then wait for
526            possible self-refresh entry/exit and/or dqs vref settled - waiting
527            before the clock change decreases worst case change stall time */
528         pre_wait = 0;
529         if (dyn_sref_enabled) {
530                 emc_cfg_reg &= ~EMC_CFG_DYN_SREF_ENABLE;
531                 emc_writel(emc_cfg_reg, EMC_CFG);
532                 pre_wait = 5;           /* 5us+ for self-refresh entry/exit */
533         }
534
535         /* 2.5 check dq/dqs vref delay */
536         if (dqs_preset(next_timing, last_timing)) {
537                 if (pre_wait < 3)
538                         pre_wait = 3;   /* 3us+ for dqs vref settled */
539         }
540         if (pre_wait) {
541                 emc_timing_update();
542                 udelay(pre_wait);
543         }
544
545         /* 3. disable auto-cal if vref mode is switching */
546         vref_cal_toggle = (next_timing->emc_acal_interval != 0) &&
547                 ((next_timing->burst_regs[EMC_XM2COMPPADCTRL_INDEX] ^
548                   last_timing->burst_regs[EMC_XM2COMPPADCTRL_INDEX]) &
549                  EMC_XM2COMPPADCTRL_VREF_CAL_ENABLE);
550         if (vref_cal_toggle)
551                 auto_cal_disable();
552
553         /* 4. program burst shadow registers */
554         for (i = 0; i < next_timing->burst_regs_num; i++) {
555                 if (!burst_reg_addr[i])
556                         continue;
557                 __raw_writel(next_timing->burst_regs[i], burst_reg_addr[i]);
558         }
559         for (i = 0; i < next_timing->emc_trimmers_num; i++) {
560                 __raw_writel(next_timing->emc_trimmers_0[i],
561                         (u32)emc0_base + emc_trimmer_offs[i]);
562                 __raw_writel(next_timing->emc_trimmers_1[i],
563                         (u32)emc1_base + emc_trimmer_offs[i]);
564         }
565         wmb();
566         barrier();
567
568         /* 4.1 On ddr3 when DLL is re-started predict MRS long wait count and
569            overwrite DFS table setting */
570         if ((dram_type == DRAM_TYPE_DDR3) && (dll_change == DLL_CHANGE_ON))
571                 overwrite_mrs_wait_cnt(next_timing, zcal_long);
572
573         /* 5.2 disable auto-refresh to save time after clock change */
574         emc_writel(EMC_REFCTRL_DISABLE_ALL(dram_dev_num), EMC_REFCTRL);
575
576         /* 6. turn Off dll and enter self-refresh on DDR3 */
577         if (dram_type == DRAM_TYPE_DDR3) {
578                 if (dll_change == DLL_CHANGE_OFF)
579                         ccfifo_writel(next_timing->emc_mode_1, EMC_EMRS);
580                 ccfifo_writel(DRAM_BROADCAST(dram_dev_num) |
581                               EMC_SELF_REF_CMD_ENABLED, EMC_SELF_REF);
582         }
583
584         /* 7. flow control marker 2 */
585         ccfifo_writel(1, EMC_STALL_THEN_EXE_AFTER_CLKCHANGE);
586
587         /* 8. exit self-refresh on DDR3 */
588         if (dram_type == DRAM_TYPE_DDR3)
589                 ccfifo_writel(DRAM_BROADCAST(dram_dev_num), EMC_SELF_REF);
590
591         /* 9. set dram mode registers */
592         set_dram_mode(next_timing, last_timing, dll_change);
593
594         /* 10. issue zcal command if turning zcal On */
595         if (zcal_long) {
596                 ccfifo_writel(EMC_ZQ_CAL_LONG_CMD_DEV0, EMC_ZQ_CAL);
597                 if (dram_dev_num > 1)
598                         ccfifo_writel(EMC_ZQ_CAL_LONG_CMD_DEV1, EMC_ZQ_CAL);
599         }
600
601         /* 10.1 dummy write to RO register to remove stall after change */
602         ccfifo_writel(0, EMC_CCFIFO_STATUS);
603
604         /* 11.5 program burst_up_down registers if emc rate is going down */
605         if (next_timing->rate < last_timing->rate) {
606                 for (i = 0; i < next_timing->burst_up_down_regs_num; i++)
607                         __raw_writel(next_timing->burst_up_down_regs[i],
608                                 burst_up_down_reg_addr[i]);
609                 wmb();
610         }
611
612         /* 12-14. read any MC register to ensure the programming is done
613            change EMC clock source register wait for clk change completion */
614         do_clock_change(clk_setting);
615
616         /* 14.1 re-enable auto-refresh */
617         emc_writel(EMC_REFCTRL_ENABLE_ALL(dram_dev_num), EMC_REFCTRL);
618
619         /* 14.2 program burst_up_down registers if emc rate is going up */
620         if (next_timing->rate > last_timing->rate) {
621                 for (i = 0; i < next_timing->burst_up_down_regs_num; i++)
622                         __raw_writel(next_timing->burst_up_down_regs[i],
623                                 burst_up_down_reg_addr[i]);
624                 wmb();
625         }
626
627         /* 15. restore auto-cal */
628         if (vref_cal_toggle)
629                 emc_writel(next_timing->emc_acal_interval,
630                            EMC_AUTO_CAL_INTERVAL);
631
632         /* 16. restore dynamic self-refresh */
633         if (next_timing->emc_cfg & EMC_CFG_DYN_SREF_ENABLE) {
634                 emc_cfg_reg |= EMC_CFG_DYN_SREF_ENABLE;
635                 emc_writel(emc_cfg_reg, EMC_CFG);
636         }
637
638         /* 17. set zcal wait count */
639         if (zcal_long)
640                 emc_writel(next_timing->emc_zcal_cnt_long, EMC_ZCAL_WAIT_CNT);
641
642         /* 18. update restored timing */
643         udelay(2);
644         emc_timing_update();
645 #else
646         /* FIXME: implement */
647         pr_info("tegra11_emc: Configuring EMC rate %lu (setting: 0x%x)\n",
648                 next_timing->rate, clk_setting);
649 #endif
650 }
651
652 static inline void emc_get_timing(struct tegra11_emc_table *timing)
653 {
654         int i;
655
656         /* burst and trimmers updates depends on previous state; burst_up_down
657            are stateless */
658         for (i = 0; i < timing->burst_regs_num; i++) {
659                 if (burst_reg_addr[i])
660                         timing->burst_regs[i] = __raw_readl(burst_reg_addr[i]);
661                 else
662                         timing->burst_regs[i] = 0;
663         }
664         for (i = 0; i < timing->emc_trimmers_num; i++) {
665                 timing->emc_trimmers_0[i] =
666                         __raw_readl((u32)emc0_base + emc_trimmer_offs[i]);
667                 timing->emc_trimmers_1[i] =
668                         __raw_readl((u32)emc1_base + emc_trimmer_offs[i]);
669         }
670         timing->emc_acal_interval = 0;
671         timing->emc_zcal_cnt_long = 0;
672         timing->emc_mode_reset = 0;
673         timing->emc_mode_1 = 0;
674         timing->emc_mode_2 = 0;
675         timing->emc_mode_4 = 0;
676         timing->emc_cfg = emc_readl(EMC_CFG);
677         timing->rate = clk_get_rate_locked(emc) / 1000;
678 }
679
680 /* The EMC registers have shadow registers. When the EMC clock is updated
681  * in the clock controller, the shadow registers are copied to the active
682  * registers, allowing glitchless memory bus frequency changes.
683  * This function updates the shadow registers for a new clock frequency,
684  * and relies on the clock lock on the emc clock to avoid races between
685  * multiple frequency changes. In addition access lock prevents concurrent
686  * access to EMC registers from reading MRR registers */
687 int tegra_emc_set_rate(unsigned long rate)
688 {
689         int i;
690         u32 clk_setting;
691         const struct tegra11_emc_table *last_timing;
692         unsigned long flags;
693         s64 last_change_delay;
694
695         if (!tegra_emc_table)
696                 return -EINVAL;
697
698         /* Table entries specify rate in kHz */
699         rate = rate / 1000;
700
701         for (i = 0; i < tegra_emc_table_size; i++) {
702                 if (tegra_emc_clk_sel[i].input == NULL)
703                         continue;       /* invalid entry */
704
705                 if (tegra_emc_table[i].rate == rate)
706                         break;
707         }
708
709         if (i >= tegra_emc_table_size)
710                 return -EINVAL;
711
712         if (!emc_timing) {
713                 /* can not assume that boot timing matches dfs table even
714                    if boot frequency matches one of the table nodes */
715                 emc_get_timing(&start_timing);
716                 last_timing = &start_timing;
717         }
718         else
719                 last_timing = emc_timing;
720
721         clk_setting = tegra_emc_clk_sel[i].value;
722
723         last_change_delay = ktime_us_delta(ktime_get(), clkchange_time);
724         if ((last_change_delay >= 0) && (last_change_delay < clkchange_delay))
725                 udelay(clkchange_delay - (int)last_change_delay);
726
727         spin_lock_irqsave(&emc_access_lock, flags);
728         emc_set_clock(&tegra_emc_table[i], last_timing, clk_setting);
729         clkchange_time = ktime_get();
730         emc_timing = &tegra_emc_table[i];
731         spin_unlock_irqrestore(&emc_access_lock, flags);
732
733         emc_last_stats_update(i);
734
735         pr_debug("%s: rate %lu setting 0x%x\n", __func__, rate, clk_setting);
736
737         return 0;
738 }
739
740 long tegra_emc_round_rate(unsigned long rate)
741 {
742         int i;
743
744         if (!tegra_emc_table)
745                 return clk_get_rate_locked(emc); /* no table - no rate change */
746
747         if (!emc_enable)
748                 return -EINVAL;
749
750         pr_debug("%s: %lu\n", __func__, rate);
751
752         /* Table entries specify rate in kHz */
753         rate = rate / 1000;
754
755         for (i = 0; i < tegra_emc_table_size; i++) {
756                 if (tegra_emc_clk_sel[i].input == NULL)
757                         continue;       /* invalid entry */
758
759                 if (tegra_emc_table[i].rate >= rate) {
760                         pr_debug("%s: using %lu\n",
761                                  __func__, tegra_emc_table[i].rate);
762                         return tegra_emc_table[i].rate * 1000;
763                 }
764         }
765
766         return -EINVAL;
767 }
768
769 struct clk *tegra_emc_predict_parent(unsigned long rate, u32 *div_value)
770 {
771         int i;
772
773         if (!tegra_emc_table) {
774                 if (rate == clk_get_rate_locked(emc)) {
775                         *div_value = emc->div - 2;
776                         return emc->parent;
777                 }
778                 return NULL;
779         }
780
781         pr_debug("%s: %lu\n", __func__, rate);
782
783         /* Table entries specify rate in kHz */
784         rate = rate / 1000;
785
786         for (i = 0; i < tegra_emc_table_size; i++) {
787                 if (tegra_emc_table[i].rate == rate) {
788                         struct clk *p = tegra_emc_clk_sel[i].input;
789
790                         if (p && (tegra_emc_clk_sel[i].input_rate ==
791                                   clk_get_rate(p))) {
792                                 *div_value = (tegra_emc_clk_sel[i].value &
793                                         EMC_CLK_DIV_MASK) >> EMC_CLK_DIV_SHIFT;
794                                 return p;
795                         }
796                 }
797         }
798         return NULL;
799 }
800
801 bool tegra_emc_is_parent_ready(unsigned long rate, struct clk **parent,
802                 unsigned long *parent_rate, unsigned long *backup_rate)
803 {
804
805         int i;
806         struct clk *p = NULL;
807         unsigned long p_rate = 0;
808
809         if (!tegra_emc_table || !emc_enable)
810                 return true;
811
812         pr_debug("%s: %lu\n", __func__, rate);
813
814         /* Table entries specify rate in kHz */
815         rate = rate / 1000;
816
817         for (i = 0; i < tegra_emc_table_size; i++) {
818                 if (tegra_emc_table[i].rate == rate) {
819                         p = tegra_emc_clk_sel[i].input;
820                         if (!p)
821                                 continue;       /* invalid entry */
822
823                         p_rate = tegra_emc_clk_sel[i].input_rate;
824                         if (p_rate == clk_get_rate(p))
825                                 return true;
826                         break;
827                 }
828         }
829
830         /* Table match not found - "non existing parent" is ready */
831         if (!p)
832                 return true;
833
834         /*
835          * Table match found, but parent is not ready - continue search
836          * for backup rate: min rate above requested that has different
837          * parent source (since only pll_c is scaled and may not be ready,
838          * any other parent can provide backup)
839          */
840         *parent = p;
841         *parent_rate = p_rate;
842
843         for (i++; i < tegra_emc_table_size; i++) {
844                 p = tegra_emc_clk_sel[i].input;
845                 if (!p)
846                         continue;       /* invalid entry */
847
848                 if (p != (*parent)) {
849                         *backup_rate = tegra_emc_table[i].rate * 1000;
850                         return false;
851                 }
852         }
853
854         /* Parent is not ready, and no backup found */
855         *backup_rate = -EINVAL;
856         return false;
857 }
858
859 /* FIXME: take advantage of table->src_sel_reg */
860 static int find_matching_input(const struct tegra11_emc_table *table,
861                         struct clk *pll_c, struct emc_sel *emc_clk_sel)
862 {
863         u32 div_value = 0;
864         unsigned long input_rate = 0;
865         unsigned long table_rate = table->rate * 1000; /* table rate in kHz */
866         struct clk *src = tegra_get_clock_by_name(table->src_name);
867         const struct clk_mux_sel *sel;
868
869         for (sel = emc->inputs; sel->input != NULL; sel++) {
870                 if (sel->input != src)
871                         continue;
872                 /*
873                  * PLLC is a scalable source. For rates below PLL_C_DIRECT_FLOOR
874                  * configure PLLC at double rate and set 1:2 divider, otherwise
875                  * configure PLLC at target rate with divider 1:1.
876                  */
877                 if (src == pll_c) {
878 #ifdef CONFIG_TEGRA_DUAL_CBUS
879                         if (table_rate < PLL_C_DIRECT_FLOOR) {
880                                 input_rate = 2 * table_rate;
881                                 div_value = 2;
882                         } else {
883                                 input_rate = table_rate;
884                                 div_value = 0;
885                         }
886                         break;
887 #else
888                         continue;       /* pll_c is used for cbus - skip */
889 #endif
890                 }
891
892                 /*
893                  * All other clock sources are fixed rate sources, and must
894                  * run at rate that is an exact multiple of the target.
895                  */
896                 input_rate = clk_get_rate(src);
897
898                 if ((input_rate >= table_rate) &&
899                      (input_rate % table_rate == 0)) {
900                         div_value = 2 * input_rate / table_rate - 2;
901                         break;
902                 }
903         }
904
905         if (!sel->input || (sel->value > EMC_CLK_SOURCE_MAX_VALUE) ||
906             (div_value > EMC_CLK_DIV_MAX_VALUE)) {
907                 pr_warn("tegra: no matching input found for EMC rate %lu\n",
908                         table_rate);
909                 return -EINVAL;
910         }
911
912         emc_clk_sel->input = sel->input;
913         emc_clk_sel->input_rate = input_rate;
914
915         /* Get ready emc clock selection settings for this table rate */
916         emc_clk_sel->value = sel->value << EMC_CLK_SOURCE_SHIFT;
917         emc_clk_sel->value |= (div_value << EMC_CLK_DIV_SHIFT);
918         if ((div_value == 0) && (emc_clk_sel->input == emc->parent))
919                 emc_clk_sel->value |= EMC_CLK_LOW_JITTER_ENABLE;
920
921         if (MC_EMEM_ARB_MISC0_EMC_SAME_FREQ &
922             table->burst_regs[MC_EMEM_ARB_MISC0_INDEX])
923                 emc_clk_sel->value |= EMC_CLK_MC_SAME_FREQ;
924
925         return 0;
926 }
927
928 static void adjust_emc_dvfs_table(const struct tegra11_emc_table *table,
929                                   int table_size)
930 {
931         int i, j;
932         unsigned long rate;
933
934         for (i = 0; i < MAX_DVFS_FREQS; i++) {
935                 int mv = emc->dvfs->millivolts[i];
936                 if (!mv)
937                         break;
938
939                 /* For each dvfs voltage find maximum supported rate;
940                    use 1MHz placeholder if not found */
941                 for (rate = 1000, j = 0; j < table_size; j++) {
942                         if (tegra_emc_clk_sel[j].input == NULL)
943                                 continue;       /* invalid entry */
944
945                         if ((mv >= table[j].emc_min_mv) &&
946                             (rate < table[j].rate))
947                                 rate = table[j].rate;
948                 }
949                 /* Table entries specify rate in kHz */
950                 emc->dvfs->freqs[i] = rate * 1000;
951         }
952 }
953
954 static int init_emc_table(const struct tegra11_emc_table *table, int table_size)
955 {
956         int i, mv;
957         u32 reg;
958         bool max_entry = false;
959         unsigned long boot_rate, max_rate;
960         struct clk *pll_c = tegra_get_clock_by_name("pll_c");
961
962         emc_stats.clkchange_count = 0;
963         spin_lock_init(&emc_stats.spinlock);
964         emc_stats.last_update = get_jiffies_64();
965         emc_stats.last_sel = TEGRA_EMC_TABLE_MAX_SIZE;
966
967         boot_rate = clk_get_rate(emc) / 1000;
968         max_rate = clk_get_max_rate(emc) / 1000;
969
970         if ((dram_type != DRAM_TYPE_DDR3) && (dram_type != DRAM_TYPE_LPDDR2)) {
971                 pr_err("tegra: not supported DRAM type %u\n", dram_type);
972                 return -ENODATA;
973         }
974
975         if (emc->parent != tegra_get_clock_by_name("pll_m")) {
976                 pr_err("tegra: boot parent %s is not supported by EMC DFS\n",
977                         emc->parent->name);
978                 return -ENODATA;
979         }
980
981         if (!table || !table_size) {
982                 pr_err("tegra: EMC DFS table is empty\n");
983                 return -ENODATA;
984         }
985
986         tegra_emc_table_size = min(table_size, TEGRA_EMC_TABLE_MAX_SIZE);
987         switch (table[0].rev) {
988         case 0x40:
989                 start_timing.burst_regs_num = table[0].burst_regs_num;
990                 start_timing.emc_trimmers_num = table[0].emc_trimmers_num;
991                 break;
992         default:
993                 pr_err("tegra: invalid EMC DFS table: unknown rev 0x%x\n",
994                         table[0].rev);
995                 return -ENODATA;
996         }
997
998         /* Match EMC source/divider settings with table entries */
999         for (i = 0; i < tegra_emc_table_size; i++) {
1000                 unsigned long table_rate = table[i].rate;
1001
1002                 /* Skip "no-rate" entry, or entry violating ascending order */
1003                 if (!table_rate ||
1004                     (i && (table_rate <= table[i-1].rate)))
1005                         continue;
1006
1007                 BUG_ON(table[i].rev != table[0].rev);
1008
1009                 if (find_matching_input(&table[i], pll_c,
1010                                         &tegra_emc_clk_sel[i]))
1011                         continue;
1012
1013                 if (table_rate == boot_rate)
1014                         emc_stats.last_sel = i;
1015
1016                 if (table_rate == max_rate)
1017                         max_entry = true;
1018         }
1019
1020         /* Validate EMC rate and voltage limits */
1021         if (!max_entry) {
1022                 pr_err("tegra: invalid EMC DFS table: entry for max rate"
1023                        " %lu kHz is not found\n", max_rate);
1024                 return -ENODATA;
1025         }
1026
1027         tegra_emc_table = table;
1028
1029         if (emc->dvfs) {
1030                 adjust_emc_dvfs_table(tegra_emc_table, tegra_emc_table_size);
1031                 mv = tegra_dvfs_predict_millivolts(emc, max_rate * 1000);
1032                 if ((mv <= 0) || (mv > emc->dvfs->max_millivolts)) {
1033                         tegra_emc_table = NULL;
1034                         pr_err("tegra: invalid EMC DFS table: maximum rate %lu"
1035                                " kHz does not match nominal voltage %d\n",
1036                                max_rate, emc->dvfs->max_millivolts);
1037                         return -ENODATA;
1038                 }
1039         }
1040
1041         pr_info("tegra: validated EMC DFS table\n");
1042
1043         /* Configure clock change mode according to dram type */
1044         reg = emc_readl(EMC_CFG_2) & (~EMC_CFG_2_MODE_MASK);
1045         reg |= ((dram_type == DRAM_TYPE_LPDDR2) ? EMC_CFG_2_PD_MODE :
1046                 EMC_CFG_2_SREF_MODE) << EMC_CFG_2_MODE_SHIFT;
1047         emc_writel(reg, EMC_CFG_2);
1048         return 0;
1049 }
1050
1051 static int __devinit tegra11_emc_probe(struct platform_device *pdev)
1052 {
1053         struct tegra11_emc_pdata *pdata;
1054         struct resource *res;
1055
1056         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1057         if (!res) {
1058                 dev_err(&pdev->dev, "missing register base\n");
1059                 return -ENOMEM;
1060         }
1061
1062         pdata = pdev->dev.platform_data;
1063         if (!pdata) {
1064                 dev_err(&pdev->dev, "missing platform data\n");
1065                 return -ENODATA;
1066         }
1067
1068         return init_emc_table(pdata->tables, pdata->num_tables);
1069 }
1070
1071 static struct platform_driver tegra11_emc_driver = {
1072         .driver         = {
1073                 .name   = "tegra-emc",
1074                 .owner  = THIS_MODULE,
1075         },
1076         .probe          = tegra11_emc_probe,
1077 };
1078
1079 int __init tegra11_emc_init(void)
1080 {
1081         return platform_driver_register(&tegra11_emc_driver);
1082 }
1083
1084 void tegra_emc_timing_invalidate(void)
1085 {
1086         emc_timing = NULL;
1087 }
1088
1089 void tegra_emc_dram_type_init(struct clk *c)
1090 {
1091         emc = c;
1092
1093         dram_type = (emc_readl(EMC_FBIO_CFG5) &
1094                      EMC_CFG5_TYPE_MASK) >> EMC_CFG5_TYPE_SHIFT;
1095
1096         dram_dev_num = (mc_readl(MC_EMEM_ADR_CFG) & 0x1) + 1; /* 2 dev max */
1097 }
1098
1099 int tegra_emc_get_dram_type(void)
1100 {
1101         return dram_type;
1102 }
1103
1104 static u32 soc_to_dram_bit_swap(u32 soc_val, u32 dram_mask, u32 dram_shift)
1105 {
1106         int bit;
1107         u32 dram_val = 0;
1108
1109         /* tegra clocks definitions use shifted mask always */
1110         if (!dram_to_soc_bit_map)
1111                 return soc_val & dram_mask;
1112
1113         for (bit = dram_shift; bit < 32; bit++) {
1114                 u32 dram_bit_mask = 0x1 << bit;
1115                 u32 soc_bit_mask = dram_to_soc_bit_map[bit];
1116
1117                 if (!(dram_bit_mask & dram_mask))
1118                         break;
1119
1120                 if (soc_bit_mask & soc_val)
1121                         dram_val |= dram_bit_mask;
1122         }
1123
1124         return dram_val;
1125 }
1126
1127 static int emc_read_mrr(int dev, int addr)
1128 {
1129         int ret;
1130         u32 val;
1131
1132         if (dram_type != DRAM_TYPE_LPDDR2)
1133                 return -ENODEV;
1134
1135         ret = wait_for_update(EMC_STATUS, EMC_STATUS_MRR_DIVLD, false);
1136         if (ret)
1137                 return ret;
1138
1139         val = dev ? DRAM_DEV_SEL_1 : DRAM_DEV_SEL_0;
1140         val |= (addr << EMC_MRR_MA_SHIFT) & EMC_MRR_MA_MASK;
1141         emc_writel(val, EMC_MRR);
1142
1143         ret = wait_for_update(EMC_STATUS, EMC_STATUS_MRR_DIVLD, true);
1144         if (ret)
1145                 return ret;
1146
1147         val = emc_readl(EMC_MRR) & EMC_MRR_DATA_MASK;
1148         return val;
1149 }
1150
1151 int tegra_emc_get_dram_temperature(void)
1152 {
1153         int mr4;
1154         unsigned long flags;
1155
1156         spin_lock_irqsave(&emc_access_lock, flags);
1157
1158         mr4 = emc_read_mrr(0, 4);
1159         if (IS_ERR_VALUE(mr4)) {
1160                 spin_unlock_irqrestore(&emc_access_lock, flags);
1161                 return mr4;
1162         }
1163         spin_unlock_irqrestore(&emc_access_lock, flags);
1164
1165         mr4 = soc_to_dram_bit_swap(
1166                 mr4, LPDDR2_MR4_TEMP_MASK, LPDDR2_MR4_TEMP_SHIFT);
1167         return mr4;
1168 }
1169
1170 #ifdef CONFIG_DEBUG_FS
1171
1172 static struct dentry *emc_debugfs_root;
1173
1174 static int emc_stats_show(struct seq_file *s, void *data)
1175 {
1176         int i;
1177
1178         emc_last_stats_update(TEGRA_EMC_TABLE_MAX_SIZE);
1179
1180         seq_printf(s, "%-10s %-10s \n", "rate kHz", "time");
1181         for (i = 0; i < tegra_emc_table_size; i++) {
1182                 if (tegra_emc_clk_sel[i].input == NULL)
1183                         continue;       /* invalid entry */
1184
1185                 seq_printf(s, "%-10lu %-10llu \n", tegra_emc_table[i].rate,
1186                            cputime64_to_clock_t(emc_stats.time_at_clock[i]));
1187         }
1188         seq_printf(s, "%-15s %llu\n", "transitions:",
1189                    emc_stats.clkchange_count);
1190         seq_printf(s, "%-15s %llu\n", "time-stamp:",
1191                    cputime64_to_clock_t(emc_stats.last_update));
1192
1193         return 0;
1194 }
1195
1196 static int emc_stats_open(struct inode *inode, struct file *file)
1197 {
1198         return single_open(file, emc_stats_show, inode->i_private);
1199 }
1200
1201 static const struct file_operations emc_stats_fops = {
1202         .open           = emc_stats_open,
1203         .read           = seq_read,
1204         .llseek         = seq_lseek,
1205         .release        = single_release,
1206 };
1207
1208 static int dram_temperature_get(void *data, u64 *val)
1209 {
1210         *val = tegra_emc_get_dram_temperature();
1211         return 0;
1212 }
1213 DEFINE_SIMPLE_ATTRIBUTE(dram_temperature_fops, dram_temperature_get,
1214                         NULL, "%lld\n");
1215
1216 static int efficiency_get(void *data, u64 *val)
1217 {
1218         *val = tegra_emc_bw_efficiency;
1219         return 0;
1220 }
1221 static int efficiency_set(void *data, u64 val)
1222 {
1223         tegra_emc_bw_efficiency = (val > 100) ? 100 : val;
1224         if (emc)
1225                 tegra_clk_shared_bus_update(emc);
1226
1227         return 0;
1228 }
1229 DEFINE_SIMPLE_ATTRIBUTE(efficiency_fops, efficiency_get,
1230                         efficiency_set, "%llu\n");
1231
1232 static int __init tegra_emc_debug_init(void)
1233 {
1234         if (!tegra_emc_table)
1235                 return 0;
1236
1237         emc_debugfs_root = debugfs_create_dir("tegra_emc", NULL);
1238         if (!emc_debugfs_root)
1239                 return -ENOMEM;
1240
1241         if (!debugfs_create_file(
1242                 "stats", S_IRUGO, emc_debugfs_root, NULL, &emc_stats_fops))
1243                 goto err_out;
1244
1245         if (!debugfs_create_u32("clkchange_delay", S_IRUGO | S_IWUSR,
1246                 emc_debugfs_root, (u32 *)&clkchange_delay))
1247                 goto err_out;
1248
1249         if (!debugfs_create_file("dram_temperature", S_IRUGO, emc_debugfs_root,
1250                                  NULL, &dram_temperature_fops))
1251                 goto err_out;
1252
1253         if (!debugfs_create_file("efficiency", S_IRUGO | S_IWUSR,
1254                                  emc_debugfs_root, NULL, &efficiency_fops))
1255                 goto err_out;
1256
1257         return 0;
1258
1259 err_out:
1260         debugfs_remove_recursive(emc_debugfs_root);
1261         return -ENOMEM;
1262 }
1263
1264 late_initcall(tegra_emc_debug_init);
1265 #endif