ARM: tegra: resolve compilation time warnings
[linux-2.6.git] / arch / arm / mach-tegra / sleep.h
1 /*
2  * arch/arm/mach-tegra/sleep.h
3  *
4  * Declarations for power state transition code
5  *
6  * Copyright (c) 2010-2012, NVIDIA Corporation.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful, but WITHOUT
14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
16  * more details.
17  *
18  * You should have received a copy of the GNU General Public License along
19  * with this program; if not, write to the Free Software Foundation, Inc.,
20  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
21  */
22
23 #ifndef __MACH_TEGRA_SLEEP_H
24 #define __MACH_TEGRA_SLEEP_H
25
26 #include <mach/iomap.h>
27
28 #ifndef CONFIG_TRUSTED_FOUNDATIONS
29 /* FIXME: The code associated with this should be removed if our change to
30    save the diagnostic regsiter in the CPU context is accepted. */
31 #define USE_TEGRA_DIAG_REG_SAVE 1
32 #else
33 #define USE_TEGRA_DIAG_REG_SAVE 0
34 #endif
35
36 #define TEGRA_POWER_LP1_AUDIO           (1 << 25) /* do not turn off pll-p in LP1 */
37
38 #ifdef CONFIG_ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE
39 #define TEGRA_POWER_CLUSTER_PART_CRAIL  (1 << 24) /* Power gate CRAIL partition */
40 #define TEGRA_POWER_CLUSTER_PART_NONCPU (1 << 25) /* Power gate CxNC partition */
41 #define TEGRA_POWER_CLUSTER_PART_MASK   (TEGRA_POWER_CLUSTER_PART_CRAIL | \
42                                                 TEGRA_POWER_CLUSTER_PART_NONCPU)
43 #define TEGRA_POWER_CLUSTER_PART_DEFAULT TEGRA_POWER_CLUSTER_PART_CRAIL
44 #else
45 #define TEGRA_POWER_CLUSTER_PART_DEFAULT 0
46 #endif
47
48 #define TEGRA_POWER_SDRAM_SELFREFRESH   (1 << 26) /* SDRAM is in self-refresh */
49 #define TEGRA_POWER_HOTPLUG_SHUTDOWN    (1 << 27) /* Hotplug shutdown */
50 #define TEGRA_POWER_CLUSTER_G           (1 << 28) /* G CPU */
51 #define TEGRA_POWER_CLUSTER_LP          (1 << 29) /* LP CPU */
52 #define TEGRA_POWER_CLUSTER_MASK        (TEGRA_POWER_CLUSTER_G | \
53                                                 TEGRA_POWER_CLUSTER_LP)
54 #define TEGRA_POWER_CLUSTER_IMMEDIATE   (1 << 30) /* Immediate wake */
55 #define TEGRA_POWER_CLUSTER_FORCE       (1 << 31) /* Force switch */
56
57 #define TEGRA_IRAM_CODE_AREA            (TEGRA_IRAM_BASE + SZ_4K)
58
59 /* PMC_SCRATCH37-39 and 41 are used for tegra_pen_lock in Tegra2 idle */
60 #define PMC_SCRATCH37                   0x130
61 #define PMC_SCRATCH38                   0x134
62 /* PMC_SCRATCH39 stores the reset vector of the AVP (always 0) after LP0 */
63 #define PMC_SCRATCH39                   0x138
64 /* PMC_SCRATCH41 stores the reset vector of the CPU after LP0 and LP1 */
65 #define PMC_SCRATCH41                   0x140
66
67 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
68 #define CPU_RESETTABLE                  2
69 #define CPU_RESETTABLE_SOON             1
70 #define CPU_NOT_RESETTABLE              0
71 #endif
72
73 #define FLOW_CTRL_HALT_CPU0_EVENTS      0x0
74 #define   FLOW_CTRL_WAITEVENT           (2 << 29)
75 #define   FLOW_CTRL_WAIT_FOR_INTERRUPT  (4 << 29)
76 #define   FLOW_CTRL_JTAG_RESUME         (1 << 28)
77 #define   FLOW_CTRL_HALT_CPU_IRQ        (1 << 10)
78 #define   FLOW_CTRL_HALT_CPU_FIQ        (1 << 8)
79 #define   FLOW_CTRL_HALT_LIC_IRQ        (1 << 11)
80 #define   FLOW_CTRL_HALT_LIC_FIQ        (1 << 10)
81 #define   FLOW_CTRL_HALT_GIC_IRQ        (1 << 9)
82 #define   FLOW_CTRL_HALT_GIC_FIQ        (1 << 8)
83 #define   FLOW_CTRL_IMMEDIATE_WAKE      (1 << 3)
84 #define FLOW_CTRL_CPU0_CSR              0x8
85 #define   FLOW_CTRL_CSR_INTR_FLAG               (1 << 15)
86 #define   FLOW_CTRL_CSR_EVENT_FLAG              (1 << 14)
87 #define   FLOW_CTRL_CSR_ENABLE_EXT_NONE (0)
88 #define   FLOW_CTRL_CSR_ENABLE_EXT_CRAIL        (1<<13)
89 #define   FLOW_CTRL_CSR_ENABLE_EXT_NCPU (1<<12)
90 #define   FLOW_CTRL_CSR_ENABLE_EXT_MASK ( \
91                                         FLOW_CTRL_CSR_ENABLE_EXT_NCPU | \
92                                         FLOW_CTRL_CSR_ENABLE_EXT_CRAIL )
93 #define   FLOW_CTRL_CSR_ENABLE_EXT_EMU FLOW_CTRL_CSR_ENABLE_EXT_MASK
94 #define   FLOW_CTRL_CSR_IMMEDIATE_WAKE          (1<<3)
95 #define   FLOW_CTRL_CSR_SWITCH_CLUSTER          (1<<2)
96 #define   FLOW_CTRL_CSR_ENABLE                  (1 << 0)
97
98 #define FLOW_CTRL_HALT_CPU1_EVENTS      0x14
99 #define FLOW_CTRL_CPU1_CSR              0x18
100
101 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
102 #define FLOW_CTRL_CSR_WFE_CPU0          (1 << 4)
103 #define FLOW_CTRL_CSR_WFE_BITMAP        (3 << 4)
104 #define FLOW_CTRL_CSR_WFI_BITMAP        0
105 #else
106 #define FLOW_CTRL_CSR_WFE_BITMAP        (0xF << 4)
107 #define FLOW_CTRL_CSR_WFI_CPU0          (1 << 8)
108 #define FLOW_CTRL_CSR_WFI_BITMAP        (0xF << 8)
109 #endif
110
111 #ifdef CONFIG_CACHE_L2X0
112 #define TEGRA_PL310_VIRT (TEGRA_ARM_PL310_BASE - IO_CPU_PHYS + IO_CPU_VIRT)
113 #endif
114 #ifdef CONFIG_HAVE_ARM_SCU
115 #define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS + IO_CPU_VIRT)
116 #endif
117 #define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS + IO_PPSB_VIRT)
118
119 #ifdef __ASSEMBLY__
120
121 /* Macro to exit SMP coherency. */
122 .macro exit_smp, tmp1, tmp2
123         mrc     p15, 0, \tmp1, c1, c0, 1        @ ACTLR
124         bic     \tmp1, \tmp1, #(1<<6) | (1<<0)  @ clear ACTLR.SMP | ACTLR.FW
125         mcr     p15, 0, \tmp1, c1, c0, 1        @ ACTLR
126         isb
127 #ifdef CONFIG_HAVE_ARM_SCU
128         cpu_id  \tmp1
129         mov     \tmp1, \tmp1, lsl #2
130         mov     \tmp2, #0xf
131         mov     \tmp2, \tmp2, lsl \tmp1
132         mov32   \tmp1, TEGRA_ARM_PERIF_VIRT + 0xC
133         str     \tmp2, [\tmp1]                  @ invalidate SCU tags for CPU
134         dsb
135 #endif
136 .endm
137
138 #define DEBUG_CONTEXT_STACK     0
139
140 /* pops a debug check token from the stack */
141 .macro  pop_stack_token tmp1, tmp2
142 #if DEBUG_CONTEXT_STACK
143         mov32   \tmp1, 0xBAB1F00D
144         ldmfd   sp!, {\tmp2}
145         cmp     \tmp1, \tmp2
146         movne   pc, #0
147 #endif
148 .endm
149
150 /* pushes a debug check token onto the stack */
151 .macro  push_stack_token tmp1
152 #if DEBUG_CONTEXT_STACK
153         mov32   \tmp1, 0xBAB1F00D
154         stmfd   sp!, {\tmp1}
155 #endif
156 .endm
157
158 #else   /* !defined(__ASSEMBLY__) */
159
160 #define FLOW_CTRL_HALT_CPU(cpu) (IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) +     \
161         ((cpu) ? (FLOW_CTRL_HALT_CPU1_EVENTS + 8 * ((cpu) - 1)) :       \
162          FLOW_CTRL_HALT_CPU0_EVENTS))
163
164 #define FLOW_CTRL_CPU_CSR(cpu)  (IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) +     \
165         ((cpu) ? (FLOW_CTRL_CPU1_CSR + 8 * ((cpu) - 1)) :       \
166          FLOW_CTRL_CPU0_CSR))
167
168 static inline void flowctrl_writel(unsigned long val, void __iomem *addr)
169 {
170         writel(val, addr);
171 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
172         wmb();
173 #endif
174         (void)__raw_readl(addr);
175 }
176
177 void tegra_pen_lock(void);
178 void tegra_pen_unlock(void);
179 void tegra_cpu_wfi(void);
180 int tegra_sleep_cpu_finish(unsigned long v2p);
181 void tegra_resume(void);
182 void tegra_flush_l1_cache(void);
183
184 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
185 extern unsigned int tegra2_iram_start;
186 extern unsigned int tegra2_iram_end;
187 int  tegra2_cpu_is_resettable_soon(void);
188 void tegra2_cpu_reset(int cpu);
189 void tegra2_cpu_set_resettable_soon(void);
190 void tegra2_cpu_clear_resettable(void);
191 int tegra2_sleep_core_finish(unsigned long int);
192 void tegra2_hotplug_shutdown(void);
193 void tegra2_sleep_wfi(unsigned long v2p);
194 int tegra2_finish_sleep_cpu_secondary(unsigned long int);
195 #else
196 extern unsigned int tegra3_iram_start;
197 extern unsigned int tegra3_iram_end;
198 int tegra3_sleep_core_finish(unsigned long int);
199 int tegra3_sleep_cpu_secondary_finish(unsigned long int);
200 void tegra3_hotplug_shutdown(void);
201 #endif
202
203 static inline void *tegra_iram_start(void)
204 {
205 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
206         return &tegra2_iram_start;
207 #else
208         return &tegra3_iram_start;
209 #endif
210 }
211
212 static inline void *tegra_iram_end(void)
213 {
214 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
215         return &tegra2_iram_end;
216 #else
217         return &tegra3_iram_end;
218 #endif
219 }
220 #endif
221 #endif