2 * arch/arm/mach-tegra/include/mach/sleep-t3.S
4 * Copyright (c) 2010-2011, NVIDIA Corporation.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
21 #include <linux/const.h>
22 #include <linux/init.h>
23 #include <linux/linkage.h>
25 #include <asm/assembler.h>
26 #include <asm/cache.h>
27 #include <asm/domain.h>
28 #include <asm/memory.h>
30 #include <asm/ptrace.h>
31 #include <asm/asm-offsets.h>
32 #include <asm/glue-cache.h>
33 #include <asm/glue-proc.h>
34 #include <asm/system.h>
36 #include <mach/iomap.h>
39 #include "asm_macros.h"
44 #define EMC_ADR_CFG 0x10
45 #define EMC_TIMING_CONTROL 0x28
46 #define EMC_REFRESH 0x70
48 #define EMC_SELF_REF 0xe0
50 #define EMC_REQ_CTRL 0x2b0
51 #define EMC_EMC_STATUS 0x2b4
52 #define EMC_FBIO_CFG5 0x104
53 #define EMC_AUTO_CAL_CONFIG 0x2a4
54 #define EMC_AUTO_CAL_INTERVAL 0x2a8
55 #define EMC_AUTO_CAL_STATUS 0x2ac
56 #define EMC_CFG_DIG_DLL 0x2bc
57 #define EMC_ZCAL_INTERVAL 0x2e0
58 #define EMC_ZQ_CAL 0x2ec
59 #define EMC_XM2VTTGENPADCTRL 0x310
60 #define EMC_XM2VTTGENPADCTRL2 0x314
63 #define PMC_CTRL_SIDE_EFFECT_LP0 (1 << 14) /* enter LP0 when CPU pwr gated */
65 #define PMC_PWRGATE_TOGGLE 0x30
66 #define PMC_REMOVE_CLAMPING_CMD 0x34
67 #define PMC_PWRGATE_STATUS 0x38
69 #define PMC_PWRGATE_PARTID_L2C (0x5)
71 #define PMC_IO_DPD_REQ 0x1b8
72 #define PMC_IO_DPD_STATUS 0x1bc
74 #define CLK_RESET_CCLK_BURST 0x20
75 #define CLK_RESET_CCLK_DIVIDER 0x24
76 #define CLK_RESET_SCLK_BURST 0x28
77 #define CLK_RESET_SCLK_DIVIDER 0x2c
79 #define CLK_RESET_PLLC_BASE 0x80
80 #define CLK_RESET_PLLM_BASE 0x90
81 #define CLK_RESET_PLLP_BASE 0xa0
82 #define CLK_RESET_PLLA_BASE 0xb0
83 #define CLK_RESET_PLLX_BASE 0xe0
85 #define CLK_RESET_PLLC_MISC 0x8c
86 #define CLK_RESET_PLLM_MISC 0x9c
87 #define CLK_RESET_PLLP_MISC 0xac
88 #define CLK_RESET_PLLA_MISC 0xbc
89 #define CLK_RESET_PLLX_MISC 0xe4
91 #define CLK_RESET_PLLP_OUTA 0xa4
92 #define CLK_RESET_PLLP_OUTB 0xa8
94 #define PMC_PLLP_WB0_OVERRIDE 0xf8
95 #define PMC_PLLM_WB0_OVERRIDE 0x1dc
97 #define CLK_RESET_CLK_SOURCE_MSELECT 0x3b4
99 #define MSELECT_CLKM (0x3 << 30)
101 #if USE_PLL_LOCK_BITS
102 #define LOCK_DELAY PLL_POST_LOCK_DELAY
104 #define LOCK_DELAY 0xff /* 255uS delay for PLL stabilization */
107 #define USE_PLLP_ON_SLEEP_ENTRY 0
109 .macro emc_device_mask, rd, base
110 ldr \rd, [\base, #EMC_ADR_CFG]
112 moveq \rd, #(0x1<<8) @ just 1 device
113 movne \rd, #(0x3<<8) @ 2 devices
116 .macro emc_timing_update, rd, base
118 str \rd, [\base, #EMC_TIMING_CONTROL]
120 ldr \rd, [\base, #EMC_EMC_STATUS]
121 tst \rd, #(0x1<<23) @ wait until EMC_STATUS_TIMING_UPDATE_STALLED is clear
125 #ifdef CONFIG_HOTPLUG_CPU
127 * tegra3_hotplug_shutdown(void)
129 * Powergates the current CPU.
130 * Should never return.
132 ENTRY(tegra3_hotplug_shutdown)
134 bl tegra_cpu_exit_coherency
136 /* Powergate this CPU. */
137 mov r0, #TEGRA_POWER_HOTPLUG_SHUTDOWN
139 mov pc, r6 @ should never get here
140 ENDPROC(tegra3_hotplug_shutdown)
143 #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
145 * tegra3_cpu_reset(unsigned long flags)
147 * Puts the current CPU in wait-for-event mode on the flow controller
148 * and powergates it -- flags (in R0) indicate the request type.
149 * Must never be called for CPU 0.
151 * corrupts r0-r4, r12
153 ENTRY(tegra3_cpu_reset)
156 moveq pc, lr @ Must never be called for CPU 0
158 mov32 r12, TEGRA_FLOW_CTRL_VIRT
159 cpu_to_csr_reg r1, r3
160 add r1, r1, r12 @ virtual CSR address for this CPU
161 cpu_to_halt_reg r2, r3
162 add r2, r2, r12 @ virtual HALT_EVENTS address for this CPU
164 /* Clear this CPU's "event" and "interrupt" flags and power gate
165 it when halting but not before it is in the "WFE" state. */
166 movw r12, FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | FLOW_CTRL_CSR_ENABLE
168 orr r12, r12, r4, lsl r3
174 subs r3, r3, #1 @ delay as a part of wfe war.
176 cpsid a @ disable imprecise aborts.
177 ldr r3, [r1] @ read CSR
178 str r3, [r1] @ clear CSR
179 tst r0, #TEGRA_POWER_HOTPLUG_SHUTDOWN
180 moveq r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT @ For LP2
181 movne r3, #FLOW_CTRL_WAITEVENT @ For hotplug
189 wfe @ CPU should be power gated here
193 /* 38 nop's, which fills reset of wfe cache line and 4 more cachelines with nop*/
197 b . @ should never get here
199 ENDPROC(tegra3_cpu_reset)
202 #ifdef CONFIG_PM_SLEEP
205 * tegra3_sleep_core(unsigned long v2p)
207 * enters suspend in LP0 or LP1 by turning off the mmu and jumping to
208 * tegra3_tear_down_core in IRAM
210 ENTRY(tegra3_sleep_core)
211 mov r12, pc @ return here is via r12
214 /* preload all the address literals that are needed for the
215 * CPU power-gating process, to avoid loads from SDRAM (which are
216 * not supported once SDRAM is put into self-refresh.
217 * LP0 / LP1 use physical address, since the MMU needs to be
218 * disabled before putting SDRAM into self-refresh to avoid
219 * memory access due to page table walks */
220 mov32 r4, TEGRA_PMC_BASE
221 mov32 r5, TEGRA_CLK_RESET_BASE
222 mov32 r6, TEGRA_FLOW_CTRL_BASE
223 mov32 r7, TEGRA_TMRUS_BASE
225 mov32 r1, tegra3_tear_down_core
226 mov32 r2, tegra3_iram_start
228 mov32 r2, TEGRA_IRAM_CODE_AREA
231 ENDPROC(tegra3_sleep_core)
234 * tegra3_sleep_cpu_secondary(unsigned long v2p)
236 * Enters LP2 on secondary CPU by exiting coherency and powergating the CPU.
238 ENTRY(tegra3_sleep_cpu_secondary)
239 mov r12, pc @ return here is via r12
242 /* Powergate this CPU. */
243 mov r0, #0 @ power mode flags (!hotplug)
245 b . @ should never get here
246 ENDPROC(tegra3_sleep_cpu_secondary)
249 * tegra3_tear_down_cpu
251 * Switches the CPU cluster to PLL-P and enters sleep.
253 ENTRY(tegra3_tear_down_cpu)
254 mov32 r4, TEGRA_PMC_BASE
255 mov32 r5, TEGRA_CLK_RESET_BASE
256 mov32 r6, TEGRA_FLOW_CTRL_BASE
257 mov32 r7, TEGRA_TMRUS_BASE
258 #if USE_PLLP_ON_SLEEP_ENTRY
262 ENDPROC(tegra3_tear_down_cpu)
264 /* START OF ROUTINES COPIED TO IRAM */
265 .align L1_CACHE_SHIFT
266 .globl tegra3_iram_start
272 * reset vector for LP1 restore; copied into IRAM during suspend.
273 * brings the system back up to a safe starting point (SDRAM out of
274 * self-refresh, PLLC, PLLM and PLLP reenabled, CPU running on PLLP,
275 * system clock running on the same PLL that it suspended at), and
276 * jumps to tegra_lp2_startup to restore PLLX and virtual addressing.
277 * physical address of tegra_lp2_startup expected to be stored in
280 * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_CODE_AREA AND MUST BE FIRST.
282 .macro pll_enable, rd, car, base, misc
283 ldr \rd, [\car, #\base]
285 orreq \rd, \rd, #(1<<30)
286 streq \rd, [\car, #\base]
287 #if USE_PLL_LOCK_BITS
288 ldr \rd, [\car, #\misc]
289 orr \rd, \rd, #(1<<18)
290 str \rd, [\car, #\misc]
294 .macro pll_locked, rd, car, base
295 #if USE_PLL_LOCK_BITS
297 ldr \rd, [\car, #\base]
303 ENTRY(tegra3_lp1_reset)
304 /* the CPU and system bus are running at 32KHz and executing from
305 * IRAM when this code is executed; immediately switch to CLKM and
306 * enable PLLP, PLLM, PLLC, PLLA and PLLX. */
307 mov32 r0, TEGRA_CLK_RESET_BASE
308 #ifndef CONFIG_TRUSTED_FOUNDATIONS
309 /* secure code handles 32KHz to CLKM/OSC clock switch */
311 str r1, [r0, #CLK_RESET_SCLK_BURST]
312 str r1, [r0, #CLK_RESET_CCLK_BURST]
314 str r1, [r0, #CLK_RESET_SCLK_DIVIDER]
315 str r1, [r0, #CLK_RESET_CCLK_DIVIDER]
317 /* enable PLLM via PMC */
318 mov32 r2, TEGRA_PMC_BASE
319 ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
321 str r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
323 pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC
324 pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC
325 pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC
326 pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC
327 pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC
329 pll_locked r1, r0, CLK_RESET_PLLM_BASE
330 pll_locked r1, r0, CLK_RESET_PLLP_BASE
331 pll_locked r1, r0, CLK_RESET_PLLA_BASE
332 pll_locked r1, r0, CLK_RESET_PLLC_BASE
333 pll_locked r1, r0, CLK_RESET_PLLX_BASE
335 mov32 r7, TEGRA_TMRUS_BASE
337 add r1, r1, #LOCK_DELAY
338 wait_until r1, r7, r3
340 add r5, pc, #tegra3_sdram_pad_save-(.+8) @ r5 reserved for pad base
343 str r4, [r0, #CLK_RESET_CLK_SOURCE_MSELECT]
346 str r4, [r0, #CLK_RESET_SCLK_BURST]
348 mov32 r4, ((1<<28) | (8)) @ burst policy is PLLX
349 str r4, [r0, #CLK_RESET_CCLK_BURST]
351 #if defined (CONFIG_CACHE_L2X0)
353 ldr r0, [r2, #PMC_PWRGATE_STATUS]
354 tst r0, #(1<<PMC_PWRGATE_PARTID_L2C)
356 movw r0, #(1<<8) | PMC_PWRGATE_PARTID_L2C
357 str r0, [r2, #PMC_PWRGATE_TOGGLE]
359 ldr r0, [r2, #PMC_PWRGATE_STATUS]
360 tst r0, #(1<<PMC_PWRGATE_PARTID_L2C)
363 mov r0, #PMC_PWRGATE_PARTID_L2C
364 str r0, [r2, #PMC_REMOVE_CLAMPING_CMD]
367 mov32 r0, TEGRA_EMC_BASE @ r0 reserved for emc base
369 ldr r1, [r5, #0x14] @ PMC_IO_DPD_STATUS
371 bic r1, r1, #(0x1<<31)
372 orr r1, r1, #(0x1<<30)
373 str r1, [r2, #PMC_IO_DPD_REQ]
375 str r1, [r0, #EMC_XM2VTTGENPADCTRL]
377 str r1, [r0, #EMC_XM2VTTGENPADCTRL2]
379 str r1, [r0, #EMC_AUTO_CAL_INTERVAL]
381 ldr r1, [r0, #EMC_CFG_DIG_DLL]
382 orr r1, r1, #(0x1<<30) @ set DLL_RESET
383 str r1, [r0, #EMC_CFG_DIG_DLL]
385 emc_timing_update r1, r0
387 ldr r1, [r0, #EMC_AUTO_CAL_CONFIG]
388 orr r1, r1, #(0x1<<31) @ set AUTO_CAL_ACTIVE
389 str r1, [r0, #EMC_AUTO_CAL_CONFIG]
391 emc_wait_audo_cal_onetime:
392 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
393 tst r1, #(0x1<<31) @ wait until AUTO_CAL_ACTIVE is clear
394 bne emc_wait_audo_cal_onetime
396 ldr r1, [r0, #EMC_CFG]
397 bic r1, r1, #(1<<31) @ disable DRAM_CLK_STOP
398 str r1, [r0, #EMC_CFG]
401 str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
403 str r1, [r0, #EMC_NOP]
404 str r1, [r0, #EMC_NOP]
405 str r1, [r0, #EMC_REFRESH]
407 emc_device_mask r1, r0
409 exit_selfrefresh_loop:
410 ldr r2, [r0, #EMC_EMC_STATUS]
412 bne exit_selfrefresh_loop
414 lsr r1, r1, #8 @ devSel, bit0:dev0 bit1:dev1
416 mov32 r7, TEGRA_TMRUS_BASE
417 ldr r2, [r0, #EMC_FBIO_CFG5]
424 str r2, [r0, #EMC_ZQ_CAL]
427 wait_until r2, r7, r3
433 str r2, [r0, #EMC_ZQ_CAL]
436 wait_until r2, r7, r3
442 str r2, [r0, #EMC_MRW]
445 wait_until r2, r7, r3
451 str r2, [r0, #EMC_MRW]
454 wait_until r2, r7, r3
459 str r1, [r0, #EMC_REQ_CTRL]
461 str r1, [r0, #EMC_ZCAL_INTERVAL]
463 str r1, [r0, #EMC_CFG]
465 mov32 r0, TEGRA_PMC_BASE
466 ldr r0, [r0, #PMC_SCRATCH41]
468 ENDPROC(tegra3_lp1_reset)
470 .align L1_CACHE_SHIFT
471 .type tegra3_sdram_pad_save, %object
472 tegra3_sdram_pad_save:
482 tegra3_sdram_pad_address:
483 .word TEGRA_EMC_BASE + EMC_CFG @0x0
484 .word TEGRA_EMC_BASE + EMC_ZCAL_INTERVAL @0x4
485 .word TEGRA_EMC_BASE + EMC_AUTO_CAL_INTERVAL @0x8
486 .word TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL @0xc
487 .word TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL2 @0x10
488 .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
489 .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
490 .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
492 tegra3_sdram_pad_size:
493 .word tegra3_sdram_pad_address - tegra3_sdram_pad_save
496 * tegra3_tear_down_core
498 * copied into and executed from IRAM
499 * puts memory in self-refresh for LP0 and LP1
501 tegra3_tear_down_core:
502 bl tegra3_sdram_self_refresh
509 * In LP0 and LP1 all plls will be turned off. Switch the CPU and system clock
510 * to the 32khz clock (clks)
511 * r4 = TEGRA_PMC_BASE
512 * r5 = TEGRA_CLK_RESET_BASE
513 * r6 = TEGRA_FLOW_CTRL_BASE
514 * r7 = TEGRA_TMRUS_BASE
517 ldr r0, [r4, #PMC_CTRL]
518 tst r0, #PMC_CTRL_SIDE_EFFECT_LP0
519 beq lp1_clocks_prepare
521 /* enable PLLM auto-restart via PMC in LP0; restore override settings */
522 ldr r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
523 orr r0, r0, #((1 << 12) | (1 << 11))
524 str r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
525 ldr r0, [r4, #PMC_SCRATCH2]
526 str r0, [r4, #PMC_PLLM_WB0_OVERRIDE]
529 /* start by jumping to clkm to safely disable PLLs, then jump
533 str r0, [r5, #CLK_RESET_SCLK_BURST]
534 str r0, [r5, #CLK_RESET_CCLK_BURST]
536 str r0, [r5, #CLK_RESET_CCLK_DIVIDER]
537 str r0, [r5, #CLK_RESET_SCLK_DIVIDER]
539 /* switch the clock source for mselect to be CLK_M */
540 ldr r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
541 orr r0, r0, #MSELECT_CLKM
542 str r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
544 /* 2 us delay between changing sclk and disabling PLLs */
545 wait_for_us r1, r7, r9
547 wait_until r1, r7, r9
550 mov r0, #0 /* burst policy = 32KHz */
551 str r0, [r5, #CLK_RESET_SCLK_BURST]
553 /* disable PLLM via PMC in LP1 */
554 ldr r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
555 bic r0, r0, #(1 << 12)
556 str r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
560 ldr r11, [r4, #PMC_SCRATCH37] @ load the LP1 flags
561 tst r11, #TEGRA_POWER_LP1_AUDIO @ check if voice call is going on
562 bne powerdown_pll_cx @ if yes, do not turn off pll-p/pll-a
564 ldr r0, [r5, #CLK_RESET_PLLP_BASE]
566 str r0, [r5, #CLK_RESET_PLLP_BASE]
567 ldr r0, [r5, #CLK_RESET_PLLA_BASE]
569 str r0, [r5, #CLK_RESET_PLLA_BASE]
572 ldr r0, [r5, #CLK_RESET_PLLC_BASE]
574 str r0, [r5, #CLK_RESET_PLLC_BASE]
575 ldr r0, [r5, #CLK_RESET_PLLX_BASE]
577 str r0, [r5, #CLK_RESET_PLLX_BASE]
584 * uses flow controller to enter sleep state
585 * executes from IRAM with SDRAM in selfrefresh when target state is LP0 or LP1
586 * executes from SDRAM with target state is LP2
587 * r4 = TEGRA_PMC_BASE
588 * r5 = TEGRA_CLK_RESET_BASE
589 * r6 = TEGRA_FLOW_CTRL_BASE
590 * r7 = TEGRA_TMRUS_BASE
594 str r1, [r4, #PMC_SCRATCH38]
598 cpu_to_csr_reg r2, r1
600 orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
601 orr r0, r0, #FLOW_CTRL_CSR_ENABLE
604 mov r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT
605 orr r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ
606 cpu_to_halt_reg r2, r1
609 ldr r0, [r6, r2] /* memory barrier */
614 wfi /* CPU should be power gated here */
616 /* !!!FIXME!!! Implement halt failure handler */
620 * tegra3_sdram_self_refresh
622 * called with MMU off and caches disabled
623 /* puts sdram in self refresh
624 * must execute from IRAM
625 * r4 = TEGRA_PMC_BASE
626 * r5 = TEGRA_CLK_RESET_BASE
627 * r6 = TEGRA_FLOW_CTRL_BASE
628 * r7 = TEGRA_TMRUS_BASE
631 tegra3_sdram_self_refresh:
633 adr r2, tegra3_sdram_pad_address
634 adr r8, tegra3_sdram_pad_save
638 ldr r0, [r2, r9] @ r0 is emc register address
641 str r1, [r8, r9] @ save emc register
644 ldr r0, tegra3_sdram_pad_size
651 mov32 r0, TEGRA_EMC_BASE @ r0 reserved for emc base
654 str r1, [r0, #EMC_ZCAL_INTERVAL]
655 str r1, [r0, #EMC_AUTO_CAL_INTERVAL]
656 ldr r1, [r0, #EMC_CFG]
658 str r1, [r0, #EMC_CFG] @ disable DYN_SELF_REF
660 emc_timing_update r1, r0
664 wait_until r1, r7, r2
667 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
668 tst r1, #(0x1<<31) @ wait until AUTO_CAL_ACTIVE is clear
669 bne emc_wait_audo_cal
672 str r1, [r0, #EMC_REQ_CTRL] @ stall incoming DRAM requests
675 ldr r1, [r0, #EMC_EMC_STATUS]
680 str r1, [r0, #EMC_SELF_REF]
682 emc_device_mask r1, r0
685 ldr r2, [r0, #EMC_EMC_STATUS]
688 bne emcself @ loop until DDR in self-refresh
690 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL]
691 mov32 r2, 0xF8F8FFFF @ clear XM2VTTGEN_DRVUP and XM2VTTGEN_DRVDN
693 str r1, [r0, #EMC_XM2VTTGENPADCTRL]
694 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL2]
695 orr r1, r1, #7 @ set E_NO_VTTGEN
696 str r1, [r0, #EMC_XM2VTTGENPADCTRL2]
698 emc_timing_update r1, r0
700 ldr r1, [r4, #PMC_CTRL]
701 tst r1, #PMC_CTRL_SIDE_EFFECT_LP0
704 str r1, [r4, #PMC_IO_DPD_REQ]
712 /* dummy symbol for end of IRAM */
713 .align L1_CACHE_SHIFT
714 .globl tegra3_iram_end